VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHdaStream.h@ 88466

Last change on this file since 88466 was 88357, checked in by vboxsync, 4 years ago

Audio: Moved PDMAUDIOFILE and associated stuff out of pdmaudioifs.h and into AudioHlp.h, renaming the typedefs & defines. bugref:9890

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1/* $Id: DevHdaStream.h 88357 2021-04-04 22:58:35Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Streams.
4 */
5
6/*
7 * Copyright (C) 2017-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VBOX_INCLUDED_SRC_Audio_DevHdaStream_h
19#define VBOX_INCLUDED_SRC_Audio_DevHdaStream_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include "DevHdaCommon.h"
25#include "DevHdaStreamMap.h"
26
27
28#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
29/**
30 * HDA stream's state for asynchronous I/O.
31 */
32typedef struct HDASTREAMSTATEAIO
33{
34 /** Thread handle for the actual I/O thread. */
35 RTTHREAD hThread;
36 /** Event for letting the thread know there is some data to process. */
37 RTSEMEVENT hEvent;
38 /** Critical section for synchronizing access. */
39 RTCRITSECT CritSect;
40 /** Started indicator. */
41 volatile bool fStarted;
42 /** Shutdown indicator. */
43 volatile bool fShutdown;
44 /** Whether the thread should do any data processing or not. */
45 volatile bool fEnabled;
46 bool afPadding[1+4];
47} HDASTREAMSTATEAIO;
48/** Pointer to a HDA stream's asynchronous I/O state. */
49typedef HDASTREAMSTATEAIO *PHDASTREAMSTATEAIO;
50#endif
51
52/**
53 * Structure containing HDA stream debug stuff, configurable at runtime.
54 */
55typedef struct HDASTREAMDEBUGRT
56{
57 /** Whether debugging is enabled or not. */
58 bool fEnabled;
59 uint8_t Padding[7];
60 /** File for dumping stream reads / writes.
61 * For input streams, this dumps data being written to the device FIFO,
62 * whereas for output streams this dumps data being read from the device FIFO. */
63 R3PTRTYPE(PAUDIOHLPFILE) pFileStream;
64 /** File for dumping raw DMA reads / writes.
65 * For input streams, this dumps data being written to the device DMA,
66 * whereas for output streams this dumps data being read from the device DMA. */
67 R3PTRTYPE(PAUDIOHLPFILE) pFileDMARaw;
68 /** File for dumping mapped (that is, extracted) DMA reads / writes. */
69 R3PTRTYPE(PAUDIOHLPFILE) pFileDMAMapped;
70} HDASTREAMDEBUGRT;
71
72/**
73 * Structure containing HDA stream debug information.
74 */
75typedef struct HDASTREAMDEBUG
76{
77 /** Runtime debug info. */
78 HDASTREAMDEBUGRT Runtime;
79#ifdef DEBUG
80 /** Critical section to serialize access if needed. */
81 RTCRITSECT CritSect;
82 uint32_t Padding0[2];
83 /** Number of total read accesses. */
84 uint64_t cReadsTotal;
85 /** Number of total DMA bytes read. */
86 uint64_t cbReadTotal;
87 /** Timestamp (in ns) of last read access. */
88 uint64_t tsLastReadNs;
89 /** Number of total write accesses. */
90 uint64_t cWritesTotal;
91 /** Number of total DMA bytes written. */
92 uint64_t cbWrittenTotal;
93 /** Number of total write accesses since last iteration (Hz). */
94 uint64_t cWritesHz;
95 /** Number of total DMA bytes written since last iteration (Hz). */
96 uint64_t cbWrittenHz;
97 /** Timestamp (in ns) of beginning a new write slot. */
98 uint64_t tsWriteSlotBegin;
99 /** Number of current silence samples in a (consecutive) row. */
100 uint64_t csSilence;
101 /** Number of silent samples in a row to consider an audio block as audio gap (silence). */
102 uint64_t cSilenceThreshold;
103 /** How many bytes to skip in an audio stream before detecting silence.
104 * (useful for intros and silence at the beginning of a song). */
105 uint64_t cbSilenceReadMin;
106#else
107 uint64_t au64Alignment[2];
108#endif
109} HDASTREAMDEBUG;
110typedef HDASTREAMDEBUG *PHDASTREAMDEBUG;
111
112/**
113 * Internal state of a HDA stream.
114 */
115typedef struct HDASTREAMSTATE
116{
117 /** Flag indicating whether this stream currently is
118 * in reset mode and therefore not acccessible by the guest. */
119 volatile bool fInReset;
120 /** Flag indicating if the stream is in running state or not. */
121 volatile bool fRunning;
122 /** The stream's I/O timer Hz rate. */
123 uint16_t uTimerIoHz;
124 /** How many interrupts are pending due to
125 * BDLE interrupt-on-completion (IOC) bits set. */
126 uint8_t cTransferPendingInterrupts;
127 /** Unused, padding. */
128 uint8_t abPadding1[2];
129 /** Input streams only: Set when we switch from feeding the guest silence and
130 * commits to proving actual audio input bytes. */
131 bool fInputPreBuffered;
132 /** Input streams only: The number of bytes we need to prebuffer. */
133 uint32_t cbInputPreBuffer;
134 uint32_t u32Padding2;
135 /** Timestamp (absolute, in timer ticks) of the last DMA data transfer.
136 * @note This is used for wall clock (WALCLK) calculations. */
137 uint64_t volatile tsTransferLast;
138 /** Timestamp (absolute, in timer ticks) of the next DMA data transfer.
139 * Next for determining the next scheduling window.
140 * Can be 0 if no next transfer is scheduled. */
141 uint64_t tsTransferNext;
142 /** Total transfer size (in bytes) of a transfer period.
143 * @note This is in host side frames, in case we're doing any mapping. */
144 uint32_t cbTransferSize;
145 /** The size of an average transfer. */
146 uint32_t cbAvgTransfer;
147 /** The stream's current host side configuration.
148 * This should match the SDnFMT in all respects but maybe the channel count as
149 * we may need to expand mono or into/from into stereo. The unmodified SDnFMT
150 * properties can be found in HDASTREAMR3::Mapping::PCMProps. */
151 PDMAUDIOSTREAMCFG Cfg;
152 /** Timestamp (real time, in ns) of last DMA transfer. */
153 uint64_t tsLastTransferNs;
154 /** Timestamp (real time, in ns) of last stream read (to backends).
155 * When running in async I/O mode, this differs from \a tsLastTransferNs,
156 * because reading / processing will be done in a separate stream. */
157 uint64_t tsLastReadNs;
158
159 /** This is set to the timer clock time when the msInitialDelay period is over.
160 * Once reached, this is set to zero to avoid unnecessary time queries. */
161 uint64_t tsAioDelayEnd;
162 /** The start time for the playback (on the timer clock). */
163 uint64_t tsStart;
164
165 /** @name DMA engine
166 * @{ */
167 /** The offset into the current BDLE. */
168 uint32_t offCurBdle;
169 /** LVI + 1 */
170 uint16_t cBdles;
171 /** The index of the current BDLE.
172 * This is the entry which period is currently "running" on the DMA timer. */
173 uint8_t idxCurBdle;
174 /** The number of prologue scheduling steps.
175 * This is used when the tail BDLEs doesn't have IOC set. */
176 uint8_t cSchedulePrologue;
177 /** Number of scheduling steps. */
178 uint16_t cSchedule;
179 /** Current scheduling step. */
180 uint16_t idxSchedule;
181 /** Current loop number within the current scheduling step. */
182 uint32_t idxScheduleLoop;
183
184 /** Buffer descriptors and additional timer scheduling state.
185 * (Same as HDABDLEDESC, with more sensible naming.) */
186 struct
187 {
188 /** The buffer address. */
189 uint64_t GCPhys;
190 /** The buffer size (guest bytes). */
191 uint32_t cb;
192 /** The flags (only bit 0 is defined). */
193 uint32_t fFlags;
194 } aBdl[256];
195 /** Scheduling steps. */
196 struct
197 {
198 /** Number of timer ticks per period.
199 * ASSUMES that we don't need a full second and that the timer resolution
200 * isn't much higher than nanoseconds. */
201 uint32_t cPeriodTicks;
202 /** The period length in host bytes. */
203 uint32_t cbPeriod;
204 /** Number of times to repeat the period. */
205 uint32_t cLoops;
206 /** The BDL index of the first entry. */
207 uint8_t idxFirst;
208 /** The number of BDL entries. */
209 uint8_t cEntries;
210 uint8_t abPadding[2];
211 } aSchedule[512+8];
212 /** @} */
213} HDASTREAMSTATE;
214AssertCompileSizeAlignment(HDASTREAMSTATE, 8);
215AssertCompileMemberAlignment(HDASTREAMSTATE, aBdl, 8);
216AssertCompileMemberAlignment(HDASTREAMSTATE, aBdl, 16);
217AssertCompileMemberAlignment(HDASTREAMSTATE, aSchedule, 16);
218
219/**
220 * An HDA stream (SDI / SDO) - shared.
221 *
222 * @note This HDA stream has nothing to do with a regular audio stream handled
223 * by the audio connector or the audio mixer. This HDA stream is a serial
224 * data in/out stream (SDI/SDO) defined in hardware and can contain
225 * multiple audio streams in one single SDI/SDO (interleaving streams).
226 *
227 * How a specific SDI/SDO is mapped to our internal audio streams relies on the
228 * stream channel mappings.
229 *
230 * Contains only register values which do *not* change until a stream reset
231 * occurs.
232 */
233typedef struct HDASTREAM
234{
235 /** Internal state of this stream. */
236 HDASTREAMSTATE State;
237
238 /** Stream descriptor number (SDn). */
239 uint8_t u8SD;
240 /** Current channel index.
241 * For a stereo stream, this is u8Channel + 1. */
242 uint8_t u8Channel;
243 /** FIFO Watermark (checked + translated in bytes, FIFOW).
244 * This will be update from hdaRegWriteSDFIFOW() and also copied
245 * hdaR3StreamInit() for some reason. */
246 uint8_t u8FIFOW;
247
248 /** @name Register values at stream setup.
249 * These will all be copied in hdaR3StreamInit().
250 * @{ */
251 /** FIFO Size (checked + translated in bytes, FIFOS).
252 * This is supposedly the max number of bytes we'll be DMA'ing in one chunk
253 * and correspondingly the LPIB & wall clock update jumps. However, we're
254 * not at all being honest with the guest about this. */
255 uint8_t u8FIFOS;
256 /** Cyclic Buffer Length (SDnCBL) - Represents the size of the ring buffer. */
257 uint32_t u32CBL;
258 /** Last Valid Index (SDnLVI). */
259 uint16_t u16LVI;
260 /** Format (SDnFMT). */
261 uint16_t u16FMT;
262 uint8_t abPadding[4];
263 /** DMA base address (SDnBDPU - SDnBDPL). */
264 uint64_t u64BDLBase;
265 /** @} */
266
267 /** The timer for pumping data thru the attached LUN drivers. */
268 TMTIMERHANDLE hTimer;
269
270#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
271 /** Pad the structure size to a 64 byte alignment. */
272 uint64_t au64Padding1[4];
273 /** Critical section for serialize access to the stream state between the async
274 * I/O thread and (basically) the guest. */
275 PDMCRITSECT CritSect;
276#endif
277} HDASTREAM;
278AssertCompileMemberAlignment(HDASTREAM, State.aBdl, 16);
279AssertCompileMemberAlignment(HDASTREAM, State.aSchedule, 16);
280AssertCompileSizeAlignment(HDASTREAM, 64);
281/** Pointer to an HDA stream (SDI / SDO). */
282typedef HDASTREAM *PHDASTREAM;
283
284
285/**
286 * An HDA stream (SDI / SDO) - ring-3 bits.
287 */
288typedef struct HDASTREAMR3
289{
290 /** Stream descriptor number (SDn). */
291 uint8_t u8SD;
292 uint8_t abPadding[7];
293 /** The shared state for the parent HDA device. */
294 R3PTRTYPE(PHDASTATE) pHDAStateShared;
295 /** The ring-3 state for the parent HDA device. */
296 R3PTRTYPE(PHDASTATER3) pHDAStateR3;
297 /** Pointer to HDA sink this stream is attached to. */
298 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
299 /** Internal state of this stream. */
300 struct
301 {
302 /** This stream's data mapping. */
303 HDASTREAMMAP Mapping;
304 /** Circular buffer (FIFO) for holding DMA'ed data. */
305 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
306 /** Current circular buffer read offset (for tracing & logging). */
307 uint64_t offRead;
308 /** Current circular buffer write offset (for tracing & logging). */
309 uint64_t offWrite;
310#ifdef HDA_USE_DMA_ACCESS_HANDLER
311 /** List of DMA handlers. */
312 RTLISTANCHORR3 lstDMAHandlers;
313#endif
314#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
315 /** Asynchronous I/O state members. */
316 HDASTREAMSTATEAIO AIO;
317#endif
318 /** Size of the DMA buffer (pCircBuf) in bytes. */
319 uint32_t StatDmaBufSize;
320 /** Number of used bytes in the DMA buffer (pCircBuf). */
321 uint32_t StatDmaBufUsed;
322 /** Counter for all under/overflows problems. */
323 STAMCOUNTER StatDmaFlowProblems;
324 /** Counter for unresovled under/overflows problems. */
325 STAMCOUNTER StatDmaFlowErrors;
326 /** Number of bytes involved in unresolved flow errors. */
327 STAMCOUNTER StatDmaFlowErrorBytes;
328 } State;
329 /** Debug bits. */
330 HDASTREAMDEBUG Dbg;
331 uint64_t au64Alignment[1];
332} HDASTREAMR3;
333AssertCompileSizeAlignment(HDASTREAMR3, 64);
334/** Pointer to an HDA stream (SDI / SDO). */
335typedef HDASTREAMR3 *PHDASTREAMR3;
336
337/** @name Stream functions (shared).
338 * @{
339 */
340void hdaStreamLock(PHDASTREAM pStreamShared);
341void hdaStreamUnlock(PHDASTREAM pStreamShared);
342/** @} */
343
344#ifdef IN_RING3
345
346/** @name Stream functions (ring-3).
347 * @{
348 */
349int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis,
350 PHDASTATER3 pThisCC, uint8_t uSD);
351void hdaR3StreamDestroy(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
352int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
353 PHDASTREAMR3 pStreamR3, uint8_t uSD);
354void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC,
355 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD);
356int hdaR3StreamEnable(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable);
357void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow);
358void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared);
359
360void hdaR3StreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uToAdd);
361uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
362 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
363void hdaR3StreamUpdate(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
364 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fInTimer);
365PHDASTREAM hdaR3StreamR3ToShared(PHDASTREAMR3 pStreamCC);
366# ifdef HDA_USE_DMA_ACCESS_HANDLER
367bool hdaR3StreamRegisterDMAHandlers(PHDASTREAM pStream);
368void hdaR3StreamUnregisterDMAHandlers(PHDASTREAM pStream);
369# endif
370/** @} */
371
372/** @name Async I/O stream functions (ring-3).
373 * @{
374 */
375# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
376int hdaR3StreamAsyncIOCreate(PHDASTREAMR3 pStreamR3);
377void hdaR3StreamAsyncIOLock(PHDASTREAMR3 pStreamR3);
378void hdaR3StreamAsyncIOUnlock(PHDASTREAMR3 pStreamR3);
379void hdaR3StreamAsyncIOEnable(PHDASTREAMR3 pStreamR3, bool fEnable);
380int hdaR3StreamAsyncIONotify(PHDASTREAMR3 pStreamR3);
381# endif /* VBOX_WITH_AUDIO_HDA_ASYNC_IO */
382/** @} */
383
384#endif /* IN_RING3 */
385#endif /* !VBOX_INCLUDED_SRC_Audio_DevHdaStream_h */
386
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