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source: vbox/trunk/src/VBox/Devices/Audio/DevHdaStream.h@ 89840

Last change on this file since 89840 was 89821, checked in by vboxsync, 4 years ago

Audio: Some info item fixes and docs updates. bugref:9890

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1/* $Id: DevHdaStream.h 89821 2021-06-21 13:04:40Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Streams.
4 */
5
6/*
7 * Copyright (C) 2017-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VBOX_INCLUDED_SRC_Audio_DevHdaStream_h
19#define VBOX_INCLUDED_SRC_Audio_DevHdaStream_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include "DevHdaCommon.h"
25
26
27/**
28 * Structure containing HDA stream debug stuff, configurable at runtime.
29 */
30typedef struct HDASTREAMDEBUGRT
31{
32 /** Whether debugging is enabled or not. */
33 bool fEnabled;
34 uint8_t Padding[7];
35 /** File for dumping stream reads / writes.
36 * For input streams, this dumps data being written to the device FIFO,
37 * whereas for output streams this dumps data being read from the device FIFO. */
38 R3PTRTYPE(PAUDIOHLPFILE) pFileStream;
39 /** File for dumping raw DMA reads / writes.
40 * For input streams, this dumps data being written to the device DMA,
41 * whereas for output streams this dumps data being read from the device DMA. */
42 R3PTRTYPE(PAUDIOHLPFILE) pFileDMARaw;
43 /** File for dumping mapped (that is, extracted) DMA reads / writes. */
44 R3PTRTYPE(PAUDIOHLPFILE) pFileDMAMapped;
45} HDASTREAMDEBUGRT;
46
47/**
48 * Structure containing HDA stream debug information.
49 */
50typedef struct HDASTREAMDEBUG
51{
52 /** Runtime debug info. */
53 HDASTREAMDEBUGRT Runtime;
54#ifdef DEBUG
55 /** Critical section to serialize access if needed. */
56 RTCRITSECT CritSect;
57 uint32_t Padding0[2];
58 /** Number of total read accesses. */
59 uint64_t cReadsTotal;
60 /** Number of total DMA bytes read. */
61 uint64_t cbReadTotal;
62 /** Timestamp (in ns) of last read access. */
63 uint64_t tsLastReadNs;
64 /** Number of total write accesses. */
65 uint64_t cWritesTotal;
66 /** Number of total DMA bytes written. */
67 uint64_t cbWrittenTotal;
68 /** Number of total write accesses since last iteration (Hz). */
69 uint64_t cWritesHz;
70 /** Number of total DMA bytes written since last iteration (Hz). */
71 uint64_t cbWrittenHz;
72 /** Timestamp (in ns) of beginning a new write slot. */
73 uint64_t tsWriteSlotBegin;
74 /** Number of current silence samples in a (consecutive) row. */
75 uint64_t csSilence;
76 /** Number of silent samples in a row to consider an audio block as audio gap (silence). */
77 uint64_t cSilenceThreshold;
78 /** How many bytes to skip in an audio stream before detecting silence.
79 * (useful for intros and silence at the beginning of a song). */
80 uint64_t cbSilenceReadMin;
81#else
82 uint64_t au64Alignment[2];
83#endif
84} HDASTREAMDEBUG;
85typedef HDASTREAMDEBUG *PHDASTREAMDEBUG;
86
87/**
88 * Internal state of a HDA stream.
89 */
90typedef struct HDASTREAMSTATE
91{
92 /** Flag indicating whether this stream currently is
93 * in reset mode and therefore not acccessible by the guest. */
94 volatile bool fInReset;
95 /** Flag indicating if the stream is in running state or not. */
96 volatile bool fRunning;
97 /** The stream's I/O timer Hz rate. */
98 uint16_t uTimerIoHz;
99 /** How many interrupts are pending due to
100 * BDLE interrupt-on-completion (IOC) bits set. */
101 uint8_t cTransferPendingInterrupts;
102 /** Unused, padding. */
103 uint8_t abPadding1[2];
104 /** Input streams only: Set when we switch from feeding the guest silence and
105 * commits to proving actual audio input bytes. */
106 bool fInputPreBuffered;
107 /** Input streams only: The number of bytes we need to prebuffer. */
108 uint32_t cbInputPreBuffer;
109 uint32_t u32Padding2;
110 /** Timestamp (absolute, in timer ticks) of the last DMA data transfer.
111 * @note This is used for wall clock (WALCLK) calculations. */
112 uint64_t volatile tsTransferLast;
113 /** Timestamp (absolute, in timer ticks) of the next DMA data transfer.
114 * Next for determining the next scheduling window.
115 * Can be 0 if no next transfer is scheduled. */
116 uint64_t tsTransferNext;
117 /** Total transfer size (in bytes) of a transfer period. */
118 uint32_t cbTransferSize;
119 /** The size of an average transfer. */
120 uint32_t cbAvgTransfer;
121 /** The stream's current configuration (matches SDnFMT). */
122 PDMAUDIOSTREAMCFG Cfg;
123 /** Timestamp (real time, in ns) of last DMA transfer. */
124 uint64_t tsLastTransferNs;
125 /** Timestamp (real time, in ns) of last stream read (to backends).
126 * When running in async I/O mode, this differs from \a tsLastTransferNs,
127 * because reading / processing will be done in a separate stream. */
128 uint64_t tsLastReadNs;
129
130 /** This is set to the timer clock time when the msInitialDelay period is over.
131 * Once reached, this is set to zero to avoid unnecessary time queries. */
132 uint64_t tsAioDelayEnd;
133 /** The start time for the playback (on the timer clock). */
134 uint64_t tsStart;
135
136 /** @name DMA engine
137 * @{ */
138 /** The offset into the current BDLE. */
139 uint32_t offCurBdle;
140 /** LVI + 1 */
141 uint16_t cBdles;
142 /** The index of the current BDLE.
143 * This is the entry which period is currently "running" on the DMA timer. */
144 uint8_t idxCurBdle;
145 /** The number of prologue scheduling steps.
146 * This is used when the tail BDLEs doesn't have IOC set. */
147 uint8_t cSchedulePrologue;
148 /** Number of scheduling steps. */
149 uint16_t cSchedule;
150 /** Current scheduling step. */
151 uint16_t idxSchedule;
152 /** Current loop number within the current scheduling step. */
153 uint32_t idxScheduleLoop;
154
155 /** Buffer descriptors and additional timer scheduling state.
156 * (Same as HDABDLEDESC, with more sensible naming.) */
157 struct
158 {
159 /** The buffer address. */
160 uint64_t GCPhys;
161 /** The buffer size (guest bytes). */
162 uint32_t cb;
163 /** The flags (only bit 0 is defined). */
164 uint32_t fFlags;
165 } aBdl[256];
166 /** Scheduling steps. */
167 struct
168 {
169 /** Number of timer ticks per period.
170 * ASSUMES that we don't need a full second and that the timer resolution
171 * isn't much higher than nanoseconds. */
172 uint32_t cPeriodTicks;
173 /** The period length in host bytes. */
174 uint32_t cbPeriod;
175 /** Number of times to repeat the period. */
176 uint32_t cLoops;
177 /** The BDL index of the first entry. */
178 uint8_t idxFirst;
179 /** The number of BDL entries. */
180 uint8_t cEntries;
181 uint8_t abPadding[2];
182 } aSchedule[512+8];
183 /** @} */
184} HDASTREAMSTATE;
185AssertCompileSizeAlignment(HDASTREAMSTATE, 8);
186AssertCompileMemberAlignment(HDASTREAMSTATE, aBdl, 8);
187AssertCompileMemberAlignment(HDASTREAMSTATE, aBdl, 16);
188AssertCompileMemberAlignment(HDASTREAMSTATE, aSchedule, 16);
189
190/**
191 * An HDA stream (SDI / SDO) - shared.
192 *
193 * @note This HDA stream has nothing to do with a regular audio stream handled
194 * by the audio connector or the audio mixer. This HDA stream is a serial
195 * data in/out stream (SDI/SDO) defined in hardware and can contain
196 * multiple audio streams in one single SDI/SDO (interleaving streams).
197 *
198 * Contains only register values which do *not* change until a stream reset
199 * occurs.
200 */
201typedef struct HDASTREAM
202{
203 /** Internal state of this stream. */
204 HDASTREAMSTATE State;
205
206 /** Stream descriptor number (SDn). */
207 uint8_t u8SD;
208 /** Current channel index.
209 * For a stereo stream, this is u8Channel + 1. */
210 uint8_t u8Channel;
211 /** FIFO Watermark (checked + translated in bytes, FIFOW).
212 * This will be update from hdaRegWriteSDFIFOW() and also copied
213 * hdaR3StreamInit() for some reason. */
214 uint8_t u8FIFOW;
215
216 /** @name Register values at stream setup.
217 * These will all be copied in hdaR3StreamInit().
218 * @{ */
219 /** FIFO Size (checked + translated in bytes, FIFOS).
220 * This is supposedly the max number of bytes we'll be DMA'ing in one chunk
221 * and correspondingly the LPIB & wall clock update jumps. However, we're
222 * not at all being honest with the guest about this. */
223 uint8_t u8FIFOS;
224 /** Cyclic Buffer Length (SDnCBL) - Represents the size of the ring buffer. */
225 uint32_t u32CBL;
226 /** Last Valid Index (SDnLVI). */
227 uint16_t u16LVI;
228 /** Format (SDnFMT). */
229 uint16_t u16FMT;
230 uint8_t abPadding[4];
231 /** DMA base address (SDnBDPU - SDnBDPL). */
232 uint64_t u64BDLBase;
233 /** @} */
234
235 /** The timer for pumping data thru the attached LUN drivers. */
236 TMTIMERHANDLE hTimer;
237
238 /** Pad the structure size to a 64 byte alignment. */
239 uint64_t au64Padding1[2];
240 /** Critical section for serialize access to the stream state between the async
241 * I/O thread and (basically) the guest. */
242 PDMCRITSECT CritSect;
243} HDASTREAM;
244AssertCompileMemberAlignment(HDASTREAM, State.aBdl, 16);
245AssertCompileMemberAlignment(HDASTREAM, State.aSchedule, 16);
246AssertCompileSizeAlignment(HDASTREAM, 64);
247/** Pointer to an HDA stream (SDI / SDO). */
248typedef HDASTREAM *PHDASTREAM;
249
250
251/**
252 * An HDA stream (SDI / SDO) - ring-3 bits.
253 */
254typedef struct HDASTREAMR3
255{
256 /** Stream descriptor number (SDn). */
257 uint8_t u8SD;
258 uint8_t abPadding[7];
259 /** The shared state for the parent HDA device. */
260 R3PTRTYPE(PHDASTATE) pHDAStateShared;
261 /** The ring-3 state for the parent HDA device. */
262 R3PTRTYPE(PHDASTATER3) pHDAStateR3;
263 /** Pointer to HDA sink this stream is attached to. */
264 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
265 /** Internal state of this stream. */
266 struct
267 {
268 /** Circular buffer (FIFO) for holding DMA'ed data. */
269 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
270 /** Current circular buffer read offset (for tracing & logging). */
271 uint64_t offRead;
272 /** Current circular buffer write offset (for tracing & logging). */
273 uint64_t offWrite;
274#ifdef HDA_USE_DMA_ACCESS_HANDLER
275 /** List of DMA handlers. */
276 RTLISTANCHORR3 lstDMAHandlers;
277#endif
278 /** The mixer sink this stream has registered AIO update callback with.
279 * This is NULL till we register it, typically in hdaR3StreamEnable.
280 * (The problem with following the pMixSink assignment is that hdaR3StreamReset
281 * sets it without updating the HDA sink structure, so things get out of
282 * wack in hdaR3MixerControl later in the initial device reset.) */
283 PAUDMIXSINK pAioRegSink;
284
285 /** Size of the DMA buffer (pCircBuf) in bytes. */
286 uint32_t StatDmaBufSize;
287 /** Number of used bytes in the DMA buffer (pCircBuf). */
288 uint32_t StatDmaBufUsed;
289 /** Counter for all under/overflows problems. */
290 STAMCOUNTER StatDmaFlowProblems;
291 /** Counter for unresovled under/overflows problems. */
292 STAMCOUNTER StatDmaFlowErrors;
293 /** Number of bytes involved in unresolved flow errors. */
294 STAMCOUNTER StatDmaFlowErrorBytes;
295
296 STAMPROFILE StatStart;
297 STAMPROFILE StatReset;
298 STAMPROFILE StatStop;
299 STAMPROFILE StatUnusedPadding;
300 } State;
301 /** Debug bits. */
302 HDASTREAMDEBUG Dbg;
303 uint64_t au64Alignment[2+4];
304} HDASTREAMR3;
305AssertCompileSizeAlignment(HDASTREAMR3, 64);
306/** Pointer to an HDA stream (SDI / SDO). */
307typedef HDASTREAMR3 *PHDASTREAMR3;
308
309/** @name Stream functions (shared).
310 * @{
311 */
312void hdaStreamLock(PHDASTREAM pStreamShared);
313void hdaStreamUnlock(PHDASTREAM pStreamShared);
314/** @} */
315
316#ifdef IN_RING3
317
318/** @name Stream functions (ring-3).
319 * @{
320 */
321int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis,
322 PHDASTATER3 pThisCC, uint8_t uSD);
323void hdaR3StreamDestroy(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
324int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
325 PHDASTREAMR3 pStreamR3, uint8_t uSD);
326void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC,
327 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD);
328int hdaR3StreamEnable(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable);
329void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow);
330void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared);
331
332uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
333 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
334DECLCALLBACK(void) hdaR3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser);
335# ifdef HDA_USE_DMA_ACCESS_HANDLER
336bool hdaR3StreamRegisterDMAHandlers(PHDASTREAM pStream);
337void hdaR3StreamUnregisterDMAHandlers(PHDASTREAM pStream);
338# endif
339/** @} */
340
341#endif /* IN_RING3 */
342#endif /* !VBOX_INCLUDED_SRC_Audio_DevHdaStream_h */
343
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