DevIchAc97.cpp@ 49498

Last change on this file since 49498 was 45025, checked in by vboxsync, 12 years ago
Update PDMDEVREG initialization comment so they refer to pfnMemSetup instead of pfnIOCtl.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 54.9 KB

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1	/* $Id: DevIchAc97.cpp 45025 2013-03-13 16:45:15Z vboxsync $ */
2	/** @file
3	* DevIchAc97 - VBox ICH AC97 Audio Controller.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22	#include <VBox/vmm/pdmdev.h>
23	#include <iprt/assert.h>
24	#include <iprt/uuid.h>
25	#include <iprt/string.h>
26
27	#include "VBoxDD.h"
28
29	extern "C" {
30	#include "audio.h"
31	}
32
33
34	/*******************************************************************************
35	* Defined Constants And Macros *
36	*******************************************************************************/
37	#undef LOG_VOICES
38	#ifndef VBOX
39	//#define USE_MIXER
40	#else
41	# define USE_MIXER
42	#endif
43
44	#define AC97_SSM_VERSION 1
45
46	#ifndef VBOX
47	# define SOFT_VOLUME
48	#else
49	# undef SOFT_VOLUME
50	#endif
51	#define SR_FIFOE RT_BIT(4) /* rwc, fifo error */
52	#define SR_BCIS RT_BIT(3) /* rwc, buffer completion interrupt status */
53	#define SR_LVBCI RT_BIT(2) /* rwc, last valid buffer completion interrupt */
54	#define SR_CELV RT_BIT(1) /* ro, current equals last valid */
55	#define SR_DCH RT_BIT(0) /* ro, controller halted */
56	#define SR_VALID_MASK (RT_BIT(5) - 1)
57	#define SR_WCLEAR_MASK (SR_FIFOE \| SR_BCIS \| SR_LVBCI)
58	#define SR_RO_MASK (SR_DCH \| SR_CELV)
59	#define SR_INT_MASK (SR_FIFOE \| SR_BCIS \| SR_LVBCI)
60
61	#define CR_IOCE RT_BIT(4) /* rw */
62	#define CR_FEIE RT_BIT(3) /* rw */
63	#define CR_LVBIE RT_BIT(2) /* rw */
64	#define CR_RR RT_BIT(1) /* rw */
65	#define CR_RPBM RT_BIT(0) /* rw */
66	#define CR_VALID_MASK (RT_BIT(5) - 1)
67	#define CR_DONT_CLEAR_MASK (CR_IOCE \| CR_FEIE \| CR_LVBIE)
68
69	#define GC_WR 4 /* rw */
70	#define GC_CR 2 /* rw */
71	#define GC_VALID_MASK (RT_BIT(6) - 1)
72
73	#define GS_MD3 RT_BIT(17) /* rw */
74	#define GS_AD3 RT_BIT(16) /* rw */
75	#define GS_RCS RT_BIT(15) /* rwc */
76	#define GS_B3S12 RT_BIT(14) /* ro */
77	#define GS_B2S12 RT_BIT(13) /* ro */
78	#define GS_B1S12 RT_BIT(12) /* ro */
79	#define GS_S1R1 RT_BIT(11) /* rwc */
80	#define GS_S0R1 RT_BIT(10) /* rwc */
81	#define GS_S1CR RT_BIT(9) /* ro */
82	#define GS_S0CR RT_BIT(8) /* ro */
83	#define GS_MINT RT_BIT(7) /* ro */
84	#define GS_POINT RT_BIT(6) /* ro */
85	#define GS_PIINT RT_BIT(5) /* ro */
86	#define GS_RSRVD (RT_BIT(4)\|RT_BIT(3))
87	#define GS_MOINT RT_BIT(2) /* ro */
88	#define GS_MIINT RT_BIT(1) /* ro */
89	#define GS_GSCI RT_BIT(0) /* rwc */
90	#define GS_RO_MASK (GS_B3S12 \| \
91	GS_B2S12 \| \
92	GS_B1S12 \| \
93	GS_S1CR \| \
94	GS_S0CR \| \
95	GS_MINT \| \
96	GS_POINT \| \
97	GS_PIINT \| \
98	GS_RSRVD \| \
99	GS_MOINT \| \
100	GS_MIINT)
101	#define GS_VALID_MASK (RT_BIT(18) - 1)
102	#define GS_WCLEAR_MASK (GS_RCS\|GS_S1R1\|GS_S0R1\|GS_GSCI)
103
104	/** @name Buffer Descriptor
105	* @{ */
106	#define BD_IOC RT_BIT(31) /*< Interrupt on Completion /
107	#define BD_BUP RT_BIT(30) /*< Buffer Underrun Policy /
108	/** @} */
109
110	#define EACS_VRA 1
111	#define EACS_VRM 8
112
113	#define VOL_MASK 0x1f
114	#define MUTE_SHIFT 15
115
116	#define REC_MASK 7
117	enum
118	{
119	REC_MIC = 0,
120	REC_CD,
121	REC_VIDEO,
122	REC_AUX,
123	REC_LINE_IN,
124	REC_STEREO_MIX,
125	REC_MONO_MIX,
126	REC_PHONE
127	};
128
129	enum
130	{
131	AC97_Reset = 0x00,
132	AC97_Master_Volume_Mute = 0x02,
133	AC97_Headphone_Volume_Mute = 0x04,
134	AC97_Master_Volume_Mono_Mute = 0x06,
135	AC97_Master_Tone_RL = 0x08,
136	AC97_PC_BEEP_Volume_Mute = 0x0A,
137	AC97_Phone_Volume_Mute = 0x0C,
138	AC97_Mic_Volume_Mute = 0x0E,
139	AC97_Line_In_Volume_Mute = 0x10,
140	AC97_CD_Volume_Mute = 0x12,
141	AC97_Video_Volume_Mute = 0x14,
142	AC97_Aux_Volume_Mute = 0x16,
143	AC97_PCM_Out_Volume_Mute = 0x18,
144	AC97_Record_Select = 0x1A,
145	AC97_Record_Gain_Mute = 0x1C,
146	AC97_Record_Gain_Mic_Mute = 0x1E,
147	AC97_General_Purpose = 0x20,
148	AC97_3D_Control = 0x22,
149	AC97_AC_97_RESERVED = 0x24,
150	AC97_Powerdown_Ctrl_Stat = 0x26,
151	AC97_Extended_Audio_ID = 0x28,
152	AC97_Extended_Audio_Ctrl_Stat = 0x2A,
153	AC97_PCM_Front_DAC_Rate = 0x2C,
154	AC97_PCM_Surround_DAC_Rate = 0x2E,
155	AC97_PCM_LFE_DAC_Rate = 0x30,
156	AC97_PCM_LR_ADC_Rate = 0x32,
157	AC97_MIC_ADC_Rate = 0x34,
158	AC97_6Ch_Vol_C_LFE_Mute = 0x36,
159	AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
160	AC97_Vendor_Reserved = 0x58,
161	AC97_Vendor_ID1 = 0x7c,
162	AC97_Vendor_ID2 = 0x7e
163	};
164
165
166	/*******************************************************************************
167	* Structures and Typedefs *
168	*******************************************************************************/
169	typedef struct BD
170	{
171	uint32_t addr;
172	uint32_t ctl_len;
173	} BD;
174
175	typedef struct AC97BusMasterRegs
176	{
177	uint32_t bdbar; /*< rw 0, buffer descriptor list base address register /
178	uint8_t civ; /*< ro 0, current index value /
179	uint8_t lvi; /*< rw 0, last valid index /
180	uint16_t sr; /*< rw 1, status register /
181	uint16_t picb; /*< ro 0, position in current buffer /
182	uint8_t piv; /*< ro 0, prefetched index value /
183	uint8_t cr; /*< rw 0, control register /
184	int bd_valid; /*< initialized? /
185	BD bd;
186	} AC97BusMasterRegs;
187	/** Pointer to a AC97 bus master register. */
188	typedef AC97BusMasterRegs *PAC97BMREG;
189
190	typedef struct AC97STATE
191	{
192	/** The PCI device state. */
193	PCIDevice PciDev;
194
195	/** Audio stuff. */
196	QEMUSoundCard card;
197
198	/** Global Control (Bus Master Control Register) */
199	uint32_t glob_cnt;
200	/** Global Status (Bus Master Control Register) */
201	uint32_t glob_sta;
202	/** Codec Access Semaphore Register (Bus Master Control Register) */
203	uint32_t cas;
204	uint32_t last_samp;
205	/** Bus Master Control Registers for PCM in, PCM out, and Mic in */
206	AC97BusMasterRegs bm_regs[3];
207	uint8_t mixer_data[256];
208	/** PCM in */
209	SWVoiceIn *voice_pi;
210	/** PCM out */
211	SWVoiceOut *voice_po;
212	/** Mic in */
213	SWVoiceIn *voice_mc;
214	uint8_t silence[128];
215	int bup_flag;
216	/** Pointer to the device instance. */
217	PPDMDEVINSR3 pDevIns;
218	/** Pointer to the connector of the attached audio driver. */
219	PPDMIAUDIOCONNECTOR pDrv;
220	/** Pointer to the attached audio driver. */
221	PPDMIBASE pDrvBase;
222	/** The base interface for LUN\#0. */
223	PDMIBASE IBase;
224	/** Base port of the I/O space region. */
225	RTIOPORT IOPortBase[2];
226	} AC97STATE;
227	/** Pointer to the AC97 device state. */
228	typedef AC97STATE *PAC97STATE;
229
230	#define ICHAC97STATE_2_DEVINS(a_pAC97) ((a_pAC97)->pDevIns)
231
232	enum
233	{
234	BUP_SET = RT_BIT(0),
235	BUP_LAST = RT_BIT(1)
236	};
237
238	#define MKREGS(prefix, start) \
239	enum { \
240	prefix ## _BDBAR = start, \
241	prefix ## _CIV = start + 4, \
242	prefix ## _LVI = start + 5, \
243	prefix ## _SR = start + 6, \
244	prefix ## _PICB = start + 8, \
245	prefix ## _PIV = start + 10, \
246	prefix ## _CR = start + 11 \
247	}
248
249	enum
250	{
251	PI_INDEX = 0, /* PCM in */
252	PO_INDEX, /* PCM out */
253	MC_INDEX, /* Mic in */
254	LAST_INDEX
255	};
256
257	MKREGS (PI, PI_INDEX * 16);
258	MKREGS (PO, PO_INDEX * 16);
259	MKREGS (MC, MC_INDEX * 16);
260
261	enum
262	{
263	GLOB_CNT = 0x2c,
264	GLOB_STA = 0x30,
265	CAS = 0x34
266	};
267
268	#define GET_BM(a_idx) ( ((a_idx) >> 4) & 3 )
269
270	static void po_callback(void *opaque, int free);
271	static void pi_callback(void *opaque, int avail);
272	static void mc_callback(void *opaque, int avail);
273
274	static void warm_reset(PAC97STATE pThis)
275	{
276	NOREF(pThis);
277	}
278
279	static void cold_reset(PAC97STATE pThis)
280	{
281	NOREF(pThis);
282	}
283
284	/** Fetch Buffer Descriptor at _CIV */
285	static void fetch_bd(PAC97STATE pThis, PAC97BMREG pReg)
286	{
287	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
288	uint8_t b[8];
289
290	PDMDevHlpPhysRead(pDevIns, pReg->bdbar + pReg->civ * 8, b, sizeof(b));
291	pReg->bd_valid = 1;
292	#if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)
293	# error Please adapt the code (audio buffers are little endian)!
294	#else
295	pReg->bd.addr = ((uint32_t ) &b[0]) & ~3;
296	pReg->bd.ctl_len = ((uint32_t ) &b[4]);
297	#endif
298	pReg->picb = pReg->bd.ctl_len & 0xffff;
299	Log(("ac97: bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
300	pReg->civ, pReg->bd.addr, pReg->bd.ctl_len >> 16,
301	pReg->bd.ctl_len & 0xffff, (pReg->bd.ctl_len & 0xffff) << 1));
302	}
303
304	/**
305	* Update the BM status register
306	*/
307	static void update_sr(PAC97STATE pThis, PAC97BMREG pReg, uint32_t new_sr)
308	{
309	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
310	int event = 0;
311	int level = 0;
312	uint32_t new_mask = new_sr & SR_INT_MASK;
313	uint32_t old_mask = pReg->sr & SR_INT_MASK;
314	static uint32_t const masks[] = { GS_PIINT, GS_POINT, GS_MINT };
315
316	if (new_mask ^ old_mask)
317	{
318	/** @todo is IRQ deasserted when only one of status bits is cleared? */
319	if (!new_mask)
320	{
321	event = 1;
322	level = 0;
323	}
324	else if ((new_mask & SR_LVBCI) && (pReg->cr & CR_LVBIE))
325	{
326	event = 1;
327	level = 1;
328	}
329	else if ((new_mask & SR_BCIS) && (pReg->cr & CR_IOCE))
330	{
331	event = 1;
332	level = 1;
333	}
334	}
335
336	pReg->sr = new_sr;
337
338	Log(("ac97: IOC%d LVB%d sr=%#x event=%d level=%d\n",
339	pReg->sr & SR_BCIS, pReg->sr & SR_LVBCI, pReg->sr, event, level));
340
341	if (event)
342	{
343	if (level)
344	pThis->glob_sta \|= masks[pReg - pThis->bm_regs];
345	else
346	pThis->glob_sta &= ~masks[pReg - pThis->bm_regs];
347
348	Log(("ac97: set irq level=%d\n", !!level));
349	PDMDevHlpPCISetIrq(pDevIns, 0, !!level);
350	}
351	}
352
353	static void voice_set_active(PAC97STATE pThis, int bm_index, int on)
354	{
355	switch (bm_index)
356	{
357	case PI_INDEX: AUD_set_active_in( pThis->voice_pi, on); break;
358	case PO_INDEX: AUD_set_active_out(pThis->voice_po, on); break;
359	case MC_INDEX: AUD_set_active_in( pThis->voice_mc, on); break;
360	default: AssertFailed (); break;
361	}
362	}
363
364	static void reset_bm_regs(PAC97STATE pThis, PAC97BMREG pReg)
365	{
366	Log(("ac97: reset_bm_regs\n"));
367	pReg->bdbar = 0;
368	pReg->civ = 0;
369	pReg->lvi = 0;
370	/** @todo do we need to do that? */
371	update_sr(pThis, pReg, SR_DCH);
372	pReg->picb = 0;
373	pReg->piv = 0;
374	pReg->cr = pReg->cr & CR_DONT_CLEAR_MASK;
375	pReg->bd_valid = 0;
376
377	voice_set_active(pThis, pReg - pThis->bm_regs, 0);
378	memset(pThis->silence, 0, sizeof(pThis->silence));
379	}
380
381	static void mixer_store(PAC97STATE pThis, uint32_t i, uint16_t v)
382	{
383	if (i + 2 > sizeof(pThis->mixer_data))
384	{
385	Log(("ac97: mixer_store: index %d out of bounds %d\n", i, sizeof(pThis->mixer_data)));
386	return;
387	}
388
389	pThis->mixer_data[i + 0] = v & 0xff;
390	pThis->mixer_data[i + 1] = v >> 8;
391	}
392
393	static uint16_t mixer_load(PAC97STATE pThis, uint32_t i)
394	{
395	uint16_t val;
396
397	if (i + 2 > sizeof(pThis->mixer_data))
398	{
399	Log(("ac97: mixer_store: index %d out of bounds %d\n", i, sizeof(pThis->mixer_data)));
400	val = 0xffff;
401	}
402	else
403	val = pThis->mixer_data[i + 0] \| (pThis->mixer_data[i + 1] << 8);
404
405	return val;
406	}
407
408	static void open_voice(PAC97STATE pThis, int index, int freq)
409	{
410	audsettings_t as;
411
412	if (freq)
413	{
414	as.freq = freq;
415	as.nchannels = 2;
416	as.fmt = AUD_FMT_S16;
417	as.endianness = 0;
418
419	switch (index)
420	{
421	case PI_INDEX: /* PCM in */
422	pThis->voice_pi = AUD_open_in(&pThis->card, pThis->voice_pi, "ac97.pi", pThis, pi_callback, &as);
423	#ifdef LOG_VOICES
424	LogRel(("AC97: open PI freq=%d (%s)\n", freq, pThis->voice_pi ? "ok" : "FAIL"));
425	#endif
426	break;
427
428	case PO_INDEX: /* PCM out */
429	pThis->voice_po = AUD_open_out(&pThis->card, pThis->voice_po, "ac97.po", pThis, po_callback, &as);
430	#ifdef LOG_VOICES
431	LogRel(("AC97: open PO freq=%d (%s)\n", freq, pThis->voice_po ? "ok" : "FAIL"));
432	#endif
433	break;
434
435	case MC_INDEX: /* Mic in */
436	pThis->voice_mc = AUD_open_in(&pThis->card, pThis->voice_mc, "ac97.mc", pThis, mc_callback, &as);
437	#ifdef LOG_VOICES
438	LogRel(("AC97: open MC freq=%d (%s)\n", freq, pThis->voice_mc ? "ok" : "FAIL"));
439	#endif
440	break;
441	}
442	}
443	else
444	{
445	switch (index)
446	{
447	case PI_INDEX:
448	AUD_close_in(&pThis->card, pThis->voice_pi);
449	#ifdef LOG_VOICES
450	LogRel(("AC97: Closing PCM IN\n"));
451	#endif
452	pThis->voice_pi = NULL;
453	break;
454
455	case PO_INDEX:
456	AUD_close_out(&pThis->card, pThis->voice_po);
457	#ifdef LOG_VOICES
458	LogRel(("AC97: Closing PCM OUT\n"));
459	#endif
460	pThis->voice_po = NULL;
461	break;
462
463	case MC_INDEX:
464	AUD_close_in(&pThis->card, pThis->voice_mc);
465	#ifdef LOG_VOICES
466	LogRel(("AC97: Closing MIC IN\n"));
467	#endif
468	pThis->voice_mc = NULL;
469	break;
470	}
471	}
472	}
473
474	static void reset_voices(PAC97STATE pThis, uint8_t active[LAST_INDEX])
475	{
476	uint16_t freq;
477
478	freq = mixer_load(pThis, AC97_PCM_LR_ADC_Rate);
479	open_voice(pThis, PI_INDEX, freq);
480	AUD_set_active_in(pThis->voice_pi, active[PI_INDEX]);
481
482	freq = mixer_load(pThis, AC97_PCM_Front_DAC_Rate);
483	open_voice(pThis, PO_INDEX, freq);
484	AUD_set_active_out(pThis->voice_po, active[PO_INDEX]);
485
486	freq = mixer_load(pThis, AC97_MIC_ADC_Rate);
487	open_voice(pThis, MC_INDEX, freq);
488	AUD_set_active_in(pThis->voice_mc, active[MC_INDEX]);
489	}
490
491	#ifdef USE_MIXER
492
493	static void set_volume(PAC97STATE pThis, int index, audmixerctl_t mt, uint32_t val)
494	{
495	int mute = (val >> MUTE_SHIFT) & 1;
496	uint8_t rvol = VOL_MASK - (val & VOL_MASK);
497	uint8_t lvol = VOL_MASK - ((val >> 8) & VOL_MASK);
498	rvol = 255 * rvol / VOL_MASK;
499	lvol = 255 * lvol / VOL_MASK;
500
501	# ifdef SOFT_VOLUME
502	if (index == AC97_Master_Volume_Mute)
503	AUD_set_volume_out(pThis->voice_po, mute, lvol, rvol);
504	else
505	AUD_set_volume(mt, &mute, &lvol, &rvol);
506	# else
507	AUD_set_volume(mt, &mute, &lvol, &rvol);
508	# endif
509
510	rvol = VOL_MASK - ((VOL_MASK * rvol) / 255);
511	lvol = VOL_MASK - ((VOL_MASK * lvol) / 255);
512
513	/*
514	* From AC'97 SoundMax Codec AD1981A: "Because AC '97 defines 6-bit volume registers, to
515	* maintain compatibility whenever the D5 or D13 bits are set to `1,' their respective
516	* lower five volume bits are automatically set to `1' by the Codec logic. On readback,
517	* all lower 5 bits will read ones whenever these bits are set to `1.'"
518	*
519	* Linux ALSA depends on this behavior.
520	*/
521	if (val & RT_BIT(5))
522	val \|= RT_BIT(4) \| RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1) \| RT_BIT(0);
523	if (val & RT_BIT(13))
524	val \|= RT_BIT(12) \| RT_BIT(11) \| RT_BIT(10) \| RT_BIT(9) \| RT_BIT(8);
525
526	mixer_store(pThis, index, val);
527	}
528
529	static audrecsource_t ac97_to_aud_record_source(uint8_t i)
530	{
531	switch (i)
532	{
533	case REC_MIC: return AUD_REC_MIC;
534	case REC_CD: return AUD_REC_CD;
535	case REC_VIDEO: return AUD_REC_VIDEO;
536	case REC_AUX: return AUD_REC_AUX;
537	case REC_LINE_IN: return AUD_REC_LINE_IN;
538	case REC_PHONE: return AUD_REC_PHONE;
539	default:
540	Log(("ac97: Unknown record source %d, using MIC\n", i));
541	return AUD_REC_MIC;
542	}
543	}
544
545	static uint8_t aud_to_ac97_record_source(audrecsource_t rs)
546	{
547	switch (rs)
548	{
549	case AUD_REC_MIC: return REC_MIC;
550	case AUD_REC_CD: return REC_CD;
551	case AUD_REC_VIDEO: return REC_VIDEO;
552	case AUD_REC_AUX: return REC_AUX;
553	case AUD_REC_LINE_IN: return REC_LINE_IN;
554	case AUD_REC_PHONE: return REC_PHONE;
555	default:
556	Log(("ac97: Unknown audio recording source %d using MIC\n", rs));
557	return REC_MIC;
558	}
559	}
560
561	static void record_select(PAC97STATE pThis, uint32_t val)
562	{
563	uint8_t rs = val & REC_MASK;
564	uint8_t ls = (val >> 8) & REC_MASK;
565	audrecsource_t ars = ac97_to_aud_record_source(rs);
566	audrecsource_t als = ac97_to_aud_record_source(ls);
567	AUD_set_record_source(&als, &ars);
568	rs = aud_to_ac97_record_source(ars);
569	ls = aud_to_ac97_record_source(als);
570	mixer_store(pThis, AC97_Record_Select, rs \| (ls << 8));
571	}
572
573	#endif /* USE_MIXER */
574
575	static void mixer_reset(PAC97STATE pThis)
576	{
577	uint8_t active[LAST_INDEX];
578
579	Log(("ac97: mixer_reset\n"));
580	memset(pThis->mixer_data, 0, sizeof(pThis->mixer_data));
581	memset(active, 0, sizeof(active));
582	mixer_store(pThis, AC97_Reset , 0x0000); /* 6940 */
583	mixer_store(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
584	mixer_store(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
585
586	mixer_store(pThis, AC97_Phone_Volume_Mute , 0x8008);
587	mixer_store(pThis, AC97_Mic_Volume_Mute , 0x8008);
588	mixer_store(pThis, AC97_CD_Volume_Mute , 0x8808);
589	mixer_store(pThis, AC97_Aux_Volume_Mute , 0x8808);
590	mixer_store(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
591	mixer_store(pThis, AC97_General_Purpose , 0x0000);
592	mixer_store(pThis, AC97_3D_Control , 0x0000);
593	mixer_store(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
594
595	/*
596	* Sigmatel 9700 (STAC9700)
597	*/
598	mixer_store(pThis, AC97_Vendor_ID1 , 0x8384);
599	mixer_store(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
600
601	mixer_store(pThis, AC97_Extended_Audio_ID , 0x0809);
602	mixer_store(pThis, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
603	mixer_store(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80);
604	mixer_store(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80);
605	mixer_store(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80);
606	mixer_store(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80);
607	mixer_store(pThis, AC97_MIC_ADC_Rate , 0xbb80);
608
609	#ifdef USE_MIXER
610	record_select(pThis, 0);
611	set_volume(pThis, AC97_Master_Volume_Mute, AUD_MIXER_VOLUME, 0x8000);
612	set_volume(pThis, AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM, 0x8808);
613	set_volume(pThis, AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN, 0x8808);
614	#else
615	mixer_store(pThis, AC97_Record_Select, 0);
616	mixer_store(pThis, AC97_Master_Volume_Mute, 0x8000);
617	mixer_store(pThis, AC97_PCM_Out_Volume_Mute, 0x8808);
618	mixer_store(pThis, AC97_Line_In_Volume_Mute, 0x8808);
619	#endif
620
621	reset_voices(pThis, active);
622	}
623
624	static int write_audio(PAC97STATE pThis, PAC97BMREG pReg, int max, int *stop)
625	{
626	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
627	uint8_t tmpbuf[4096];
628	uint32_t addr = pReg->bd.addr;
629	uint32_t temp = pReg->picb << 1;
630	uint32_t written = 0;
631	int to_copy = 0;
632
633	temp = audio_MIN(temp, (uint32_t)max);
634	if (!temp)
635	{
636	*stop = 1;
637	return 0;
638	}
639
640	while (temp)
641	{
642	int copied;
643	to_copy = audio_MIN(temp, sizeof(tmpbuf));
644	PDMDevHlpPhysRead(pDevIns, addr, tmpbuf, to_copy);
645	copied = AUD_write(pThis->voice_po, tmpbuf, to_copy);
646	Log(("ac97: write_audio max=%x to_copy=%x copied=%x\n", max, to_copy, copied));
647	if (!copied)
648	{
649	*stop = 1;
650	break;
651	}
652	temp -= copied;
653	addr += copied;
654	written += copied;
655	}
656
657	if (!temp)
658	{
659	if (to_copy < 4)
660	{
661	Log(("ac97: whoops\n"));
662	pThis->last_samp = 0;
663	}
664	else
665	pThis->last_samp = (uint32_t )&tmpbuf[to_copy - 4];
666	}
667
668	pReg->bd.addr = addr;
669	return written;
670	}
671
672	static void write_bup(PAC97STATE pThis, int elapsed)
673	{
674	int written = 0;
675
676	Log(("ac97: write_bup\n"));
677	if (!(pThis->bup_flag & BUP_SET))
678	{
679	if (pThis->bup_flag & BUP_LAST)
680	{
681	unsigned int i;
682	uint32_t p = (uint32_t)pThis->silence;
683	for (i = 0; i < sizeof(pThis->silence) / 4; i++)
684	*p++ = pThis->last_samp;
685	}
686	else
687	memset(pThis->silence, 0, sizeof(pThis->silence));
688
689	pThis->bup_flag \|= BUP_SET;
690	}
691
692	while (elapsed)
693	{
694	unsigned int temp = audio_MIN((unsigned int)elapsed, sizeof(pThis->silence));
695	while (temp)
696	{
697	int copied = AUD_write(pThis->voice_po, pThis->silence, temp);
698	if (!copied)
699	return;
700	temp -= copied;
701	elapsed -= copied;
702	written += copied;
703	}
704	}
705	}
706
707	static int read_audio(PAC97STATE pThis, PAC97BMREG pReg, int max, int *stop)
708	{
709	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
710	uint8_t tmpbuf[4096];
711	uint32_t addr = pReg->bd.addr;
712	uint32_t temp = pReg->picb << 1;
713	uint32_t nread = 0;
714	int to_copy = 0;
715	SWVoiceIn *voice = (pReg - pThis->bm_regs) == MC_INDEX ? pThis->voice_mc : pThis->voice_pi;
716
717	temp = audio_MIN(temp, (uint32_t)max);
718	if (!temp)
719	{
720	*stop = 1;
721	return 0;
722	}
723
724	while (temp)
725	{
726	int acquired;
727	to_copy = audio_MIN(temp, sizeof(tmpbuf));
728	acquired = AUD_read(voice, tmpbuf, to_copy);
729	if (!acquired)
730	{
731	*stop = 1;
732	break;
733	}
734	PDMDevHlpPCIPhysWrite(pDevIns, addr, tmpbuf, acquired);
735	temp -= acquired;
736	addr += acquired;
737	nread += acquired;
738	}
739
740	pReg->bd.addr = addr;
741	return nread;
742	}
743
744	static void transfer_audio(PAC97STATE pThis, int index, int elapsed)
745	{
746	PAC97BMREG pReg = &pThis->bm_regs[index];
747	int written = 0;
748	int stop = 0;
749
750	if (pReg->sr & SR_DCH)
751	{
752	if (pReg->cr & CR_RPBM)
753	{
754	switch (index)
755	{
756	case PO_INDEX:
757	write_bup(pThis, elapsed);
758	break;
759	}
760	}
761	return;
762	}
763
764	while ((elapsed >> 1) && !stop)
765	{
766	int temp;
767
768	if (!pReg->bd_valid)
769	{
770	Log(("ac97: invalid bd\n"));
771	fetch_bd(pThis, pReg);
772	}
773
774	if (!pReg->picb)
775	{
776	Log(("ac97: fresh bd %d is empty %#x %#x, skipping\n", pReg->civ, pReg->bd.addr, pReg->bd.ctl_len));
777	if (pReg->civ == pReg->lvi)
778	{
779	pReg->sr \|= SR_DCH; /* CELV? */
780	pThis->bup_flag = 0;
781	break;
782	}
783	pReg->sr &= ~SR_CELV;
784	pReg->civ = pReg->piv;
785	pReg->piv = (pReg->piv + 1) % 32;
786	fetch_bd(pThis, pReg);
787	continue;
788	}
789
790	switch (index)
791	{
792	case PO_INDEX:
793	temp = write_audio(pThis, pReg, elapsed, &stop);
794	written += temp;
795	elapsed -= temp;
796	Assert((temp & 1) == 0); /* Else the following shift won't work */
797	pReg->picb -= (temp >> 1);
798	break;
799
800	case PI_INDEX:
801	case MC_INDEX:
802	temp = read_audio(pThis, pReg, elapsed, &stop);
803	elapsed -= temp;
804	Assert((temp & 1) == 0); /* Else the following shift won't work */
805	pReg->picb -= (temp >> 1);
806	break;
807	}
808
809	Log(("pReg->picb = %d\n", pReg->picb));
810
811	if (!pReg->picb)
812	{
813	uint32_t new_sr = pReg->sr & ~SR_CELV;
814
815	if (pReg->bd.ctl_len & BD_IOC)
816	new_sr \|= SR_BCIS;
817
818	if (pReg->civ == pReg->lvi)
819	{
820	Log(("ac97: Underrun civ (%d) == lvi (%d)\n", pReg->civ, pReg->lvi));
821	new_sr \|= SR_LVBCI \| SR_DCH \| SR_CELV;
822	stop = 1;
823	pThis->bup_flag = (pReg->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
824	}
825	else
826	{
827	pReg->civ = pReg->piv;
828	pReg->piv = (pReg->piv + 1) % 32;
829	fetch_bd(pThis, pReg);
830	}
831	update_sr(pThis, pReg, new_sr);
832	}
833	}
834	}
835
836	static void pi_callback(void *opaque, int avail)
837	{
838	transfer_audio((AC97STATE *)opaque, PI_INDEX, avail);
839	}
840
841	static void mc_callback(void *opaque, int avail)
842	{
843	transfer_audio((AC97STATE *)opaque, MC_INDEX, avail);
844	}
845
846	static void po_callback(void *opaque, int free)
847	{
848	transfer_audio((AC97STATE *)opaque, PO_INDEX, free);
849	}
850
851	/**
852	* @callback_method_impl{FNIOMIOPORTIN}
853	*/
854	static DECLCALLBACK(int) ichac97IOPortNABMRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
855	{
856	PAC97STATE pThis = (PAC97STATE)pvUser;
857
858	switch (cb)
859	{
860	case 1:
861	{
862	PAC97BMREG pReg = NULL;
863	uint32_t index = Port - pThis->IOPortBase[1];
864	*pu32 = ~0U;
865
866	switch (index)
867	{
868	case CAS:
869	/* Codec Access Semaphore Register */
870	Log(("ac97: CAS %d\n", pThis->cas));
871	*pu32 = pThis->cas;
872	pThis->cas = 1;
873	break;
874	case PI_CIV:
875	case PO_CIV:
876	case MC_CIV:
877	/* Current Index Value Register */
878	pReg = &pThis->bm_regs[GET_BM(index)];
879	*pu32 = pReg->civ;
880	Log(("ac97: CIV[%d] -> %#x\n", GET_BM(index), *pu32));
881	break;
882	case PI_LVI:
883	case PO_LVI:
884	case MC_LVI:
885	/* Last Valid Index Register */
886	pReg = &pThis->bm_regs[GET_BM(index)];
887	*pu32 = pReg->lvi;
888	Log(("ac97: LVI[%d] -> %#x\n", GET_BM(index), *pu32));
889	break;
890	case PI_PIV:
891	case PO_PIV:
892	case MC_PIV:
893	/* Prefetched Index Value Register */
894	pReg = &pThis->bm_regs[GET_BM(index)];
895	*pu32 = pReg->piv;
896	Log(("ac97: PIV[%d] -> %#x\n", GET_BM(index), *pu32));
897	break;
898	case PI_CR:
899	case PO_CR:
900	case MC_CR:
901	/* Control Register */
902	pReg = &pThis->bm_regs[GET_BM(index)];
903	*pu32 = pReg->cr;
904	Log(("ac97: CR[%d] -> %#x\n", GET_BM(index), *pu32));
905	break;
906	case PI_SR:
907	case PO_SR:
908	case MC_SR:
909	/* Status Register (lower part) */
910	pReg = &pThis->bm_regs[GET_BM(index)];
911	*pu32 = pReg->sr & 0xff;
912	Log(("ac97: SRb[%d] -> %#x\n", GET_BM(index), *pu32));
913	break;
914	default:
915	Log(("ac97: U nabm readb %#x -> %#x\n", Port, *pu32));
916	break;
917	}
918	break;
919	}
920
921	case 2:
922	{
923	PAC97BMREG pReg = NULL;
924	uint32_t index = Port - pThis->IOPortBase[1];
925	*pu32 = ~0U;
926
927	switch (index)
928	{
929	case PI_SR:
930	case PO_SR:
931	case MC_SR:
932	/* Status Register */
933	pReg = &pThis->bm_regs[GET_BM(index)];
934	*pu32 = pReg->sr;
935	Log(("ac97: SR[%d] -> %#x\n", GET_BM(index), *pu32));
936	break;
937	case PI_PICB:
938	case PO_PICB:
939	case MC_PICB:
940	/* Position in Current Buffer Register */
941	pReg = &pThis->bm_regs[GET_BM(index)];
942	*pu32 = pReg->picb;
943	Log(("ac97: PICB[%d] -> %#x\n", GET_BM(index), *pu32));
944	break;
945	default:
946	Log(("ac97: U nabm readw %#x -> %#x\n", Port, *pu32));
947	break;
948	}
949	break;
950	}
951
952	case 4:
953	{
954	PAC97BMREG pReg = NULL;
955	uint32_t index = Port - pThis->IOPortBase[1];
956	*pu32 = ~0U;
957
958	switch (index)
959	{
960	case PI_BDBAR:
961	case PO_BDBAR:
962	case MC_BDBAR:
963	/* Buffer Descriptor Base Address Register */
964	pReg = &pThis->bm_regs[GET_BM(index)];
965	*pu32 = pReg->bdbar;
966	Log(("ac97: BMADDR[%d] -> %#x\n", GET_BM(index), *pu32));
967	break;
968	case PI_CIV:
969	case PO_CIV:
970	case MC_CIV:
971	/* 32-bit access: Current Index Value Register +
972	* Last Valid Index Register +
973	* Status Register */
974	pReg = &pThis->bm_regs[GET_BM(index)];
975	*pu32 = pReg->civ \| (pReg->lvi << 8) \| (pReg->sr << 16);
976	Log(("ac97: CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM(index), pReg->civ, pReg->lvi, pReg->sr));
977	break;
978	case PI_PICB:
979	case PO_PICB:
980	case MC_PICB:
981	/* 32-bit access: Position in Current Buffer Register +
982	* Prefetched Index Value Register +
983	* Control Register */
984	pReg = &pThis->bm_regs[GET_BM(index)];
985	*pu32 = pReg->picb \| (pReg->piv << 16) \| (pReg->cr << 24);
986	Log(("ac97: PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM(index), *pu32, pReg->picb, pReg->piv, pReg->cr));
987	break;
988	case GLOB_CNT:
989	/* Global Control */
990	*pu32 = pThis->glob_cnt;
991	Log(("ac97: glob_cnt -> %#x\n", *pu32));
992	break;
993	case GLOB_STA:
994	/* Global Status */
995	*pu32 = pThis->glob_sta \| GS_S0CR;
996	Log(("ac97: glob_sta -> %#x\n", *pu32));
997	break;
998	default:
999	Log(("ac97: U nabm readl %#x -> %#x\n", Port, *pu32));
1000	break;
1001	}
1002	break;
1003	}
1004
1005	default:
1006	return VERR_IOM_IOPORT_UNUSED;
1007	}
1008	return VINF_SUCCESS;
1009	}
1010
1011	/**
1012	* @callback_method_impl{FNIOMIOPORTOUT}
1013	*/
1014	static DECLCALLBACK(int) ichac97IOPortNABMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1015	{
1016	PAC97STATE pThis = (PAC97STATE)pvUser;
1017
1018	switch (cb)
1019	{
1020	case 1:
1021	{
1022	PAC97BMREG pReg = NULL;
1023	uint32_t index = Port - pThis->IOPortBase[1];
1024	switch (index)
1025	{
1026	case PI_LVI:
1027	case PO_LVI:
1028	case MC_LVI:
1029	/* Last Valid Index */
1030	pReg = &pThis->bm_regs[GET_BM(index)];
1031	if ((pReg->cr & CR_RPBM) && (pReg->sr & SR_DCH))
1032	{
1033	pReg->sr &= ~(SR_DCH \| SR_CELV);
1034	pReg->civ = pReg->piv;
1035	pReg->piv = (pReg->piv + 1) % 32;
1036	fetch_bd(pThis, pReg);
1037	}
1038	pReg->lvi = u32 % 32;
1039	Log(("ac97: LVI[%d] <- %#x\n", GET_BM(index), u32));
1040	break;
1041	case PI_CR:
1042	case PO_CR:
1043	case MC_CR:
1044	/* Control Register */
1045	pReg = &pThis->bm_regs[GET_BM(index)];
1046	if (u32 & CR_RR)
1047	reset_bm_regs(pThis, pReg);
1048	else
1049	{
1050	pReg->cr = u32 & CR_VALID_MASK;
1051	if (!(pReg->cr & CR_RPBM))
1052	{
1053	voice_set_active(pThis, pReg - pThis->bm_regs, 0);
1054	pReg->sr \|= SR_DCH;
1055	}
1056	else
1057	{
1058	pReg->civ = pReg->piv;
1059	pReg->piv = (pReg->piv + 1) % 32;
1060	fetch_bd(pThis, pReg);
1061	pReg->sr &= ~SR_DCH;
1062	voice_set_active(pThis, pReg - pThis->bm_regs, 1);
1063	}
1064	}
1065	Log(("ac97: CR[%d] <- %#x (cr %#x)\n", GET_BM(index), u32, pReg->cr));
1066	break;
1067	case PI_SR:
1068	case PO_SR:
1069	case MC_SR:
1070	/* Status Register */
1071	pReg = &pThis->bm_regs[GET_BM(index)];
1072	pReg->sr \|= u32 & ~(SR_RO_MASK \| SR_WCLEAR_MASK);
1073	update_sr(pThis, pReg, pReg->sr & ~(u32 & SR_WCLEAR_MASK));
1074	Log(("ac97: SR[%d] <- %#x (sr %#x)\n", GET_BM(index), u32, pReg->sr));
1075	break;
1076	default:
1077	Log(("ac97: U nabm writeb %#x <- %#x\n", Port, u32));
1078	break;
1079	}
1080	break;
1081	}
1082
1083	case 2:
1084	{
1085	PAC97BMREG pReg = NULL;
1086	uint32_t index = Port - pThis->IOPortBase[1];
1087	switch (index)
1088	{
1089	case PI_SR:
1090	case PO_SR:
1091	case MC_SR:
1092	/* Status Register */
1093	pReg = &pThis->bm_regs[GET_BM(index)];
1094	pReg->sr \|= u32 & ~(SR_RO_MASK \| SR_WCLEAR_MASK);
1095	update_sr(pThis, pReg, pReg->sr & ~(u32 & SR_WCLEAR_MASK));
1096	Log(("ac97: SR[%d] <- %#x (sr %#x)\n", GET_BM(index), u32, pReg->sr));
1097	break;
1098	default:
1099	Log(("ac97: U nabm writew %#x <- %#x\n", Port, u32));
1100	break;
1101	}
1102	break;
1103	}
1104
1105	case 4:
1106	{
1107	PAC97BMREG pReg = NULL;
1108	uint32_t index = Port - pThis->IOPortBase[1];
1109	switch (index)
1110	{
1111	case PI_BDBAR:
1112	case PO_BDBAR:
1113	case MC_BDBAR:
1114	/* Buffer Descriptor list Base Address Register */
1115	pReg = &pThis->bm_regs[GET_BM(index)];
1116	pReg->bdbar = u32 & ~3;
1117	Log(("ac97: BDBAR[%d] <- %#x (bdbar %#x)\n", GET_BM(index), u32, pReg->bdbar));
1118	break;
1119	case GLOB_CNT:
1120	/* Global Control */
1121	if (u32 & GC_WR)
1122	warm_reset(pThis);
1123	if (u32 & GC_CR)
1124	cold_reset(pThis);
1125	if (!(u32 & (GC_WR \| GC_CR)))
1126	pThis->glob_cnt = u32 & GC_VALID_MASK;
1127	Log(("ac97: glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt));
1128	break;
1129	case GLOB_STA:
1130	/* Global Status */
1131	pThis->glob_sta &= ~(u32 & GS_WCLEAR_MASK);
1132	pThis->glob_sta \|= (u32 & ~(GS_WCLEAR_MASK \| GS_RO_MASK)) & GS_VALID_MASK;
1133	Log(("ac97: glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta));
1134	break;
1135	default:
1136	Log(("ac97: U nabm writel %#x <- %#x\n", Port, u32));
1137	break;
1138	}
1139	break;
1140	}
1141
1142	default:
1143	AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1144	break;
1145	}
1146	return VINF_SUCCESS;
1147	}
1148
1149	/**
1150	* @callback_method_impl{FNIOMIOPORTIN}
1151	*/
1152	static DECLCALLBACK(int) ichac97IOPortNAMRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1153	{
1154	PAC97STATE pThis = (PAC97STATE)pvUser;
1155
1156	switch (cb)
1157	{
1158	case 1:
1159	{
1160	Log(("ac97: U nam readb %#x\n", Port));
1161	pThis->cas = 0;
1162	*pu32 = ~0U;
1163	break;
1164	}
1165
1166	case 2:
1167	{
1168	uint32_t index = Port - pThis->IOPortBase[0];
1169	*pu32 = ~0U;
1170	pThis->cas = 0;
1171	switch (index)
1172	{
1173	default:
1174	*pu32 = mixer_load(pThis, index);
1175	Log(("ac97: nam readw %#x -> %#x\n", Port, *pu32));
1176	break;
1177	}
1178	break;
1179	}
1180
1181	case 4:
1182	{
1183	Log(("ac97: U nam readl %#x\n", Port));
1184	pThis->cas = 0;
1185	*pu32 = ~0U;
1186	break;
1187	}
1188
1189	default:
1190	return VERR_IOM_IOPORT_UNUSED;
1191	}
1192	return VINF_SUCCESS;
1193	}
1194
1195	/**
1196	* @callback_method_impl{FNIOMIOPORTOUT}
1197	*/
1198	static DECLCALLBACK(int) ichac97IOPortNAMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1199	{
1200	PAC97STATE pThis = (PAC97STATE)pvUser;
1201
1202	switch (cb)
1203	{
1204	case 1:
1205	{
1206	Log(("ac97: U nam writeb %#x <- %#x\n", Port, u32));
1207	pThis->cas = 0;
1208	break;
1209	}
1210
1211	case 2:
1212	{
1213	uint32_t index = Port - pThis->IOPortBase[0];
1214	pThis->cas = 0;
1215	switch (index)
1216	{
1217	case AC97_Reset:
1218	mixer_reset(pThis);
1219	break;
1220	case AC97_Powerdown_Ctrl_Stat:
1221	u32 &= ~0xf;
1222	u32 \|= mixer_load(pThis, index) & 0xf;
1223	mixer_store(pThis, index, u32);
1224	break;
1225	#ifdef USE_MIXER
1226	case AC97_Master_Volume_Mute:
1227	set_volume(pThis, index, AUD_MIXER_VOLUME, u32);
1228	break;
1229	case AC97_PCM_Out_Volume_Mute:
1230	set_volume(pThis, index, AUD_MIXER_PCM, u32);
1231	break;
1232	case AC97_Line_In_Volume_Mute:
1233	set_volume(pThis, index, AUD_MIXER_LINE_IN, u32);
1234	break;
1235	case AC97_Record_Select:
1236	record_select(pThis, u32);
1237	break;
1238	#else /* !USE_MIXER */
1239	case AC97_Master_Volume_Mute:
1240	case AC97_PCM_Out_Volume_Mute:
1241	case AC97_Line_In_Volume_Mute:
1242	case AC97_Record_Select:
1243	mixer_store(pThis, index, u32);
1244	break;
1245	#endif /* !USE_MIXER */
1246	case AC97_Vendor_ID1:
1247	case AC97_Vendor_ID2:
1248	Log(("ac97: Attempt to write vendor ID to %#x\n", u32));
1249	break;
1250	case AC97_Extended_Audio_ID:
1251	Log(("ac97: Attempt to write extended audio ID to %#x\n", u32));
1252	break;
1253	case AC97_Extended_Audio_Ctrl_Stat:
1254	if (!(u32 & EACS_VRA))
1255	{
1256	mixer_store(pThis, AC97_PCM_Front_DAC_Rate, 0xbb80);
1257	mixer_store(pThis, AC97_PCM_LR_ADC_Rate, 0xbb80);
1258	open_voice(pThis, PI_INDEX, 48000);
1259	open_voice(pThis, PO_INDEX, 48000);
1260	}
1261	if (!(u32 & EACS_VRM))
1262	{
1263	mixer_store(pThis, AC97_MIC_ADC_Rate, 0xbb80);
1264	open_voice(pThis, MC_INDEX, 48000);
1265	}
1266	Log(("ac97: Setting extended audio control to %#x\n", u32));
1267	mixer_store(pThis, AC97_Extended_Audio_Ctrl_Stat, u32);
1268	break;
1269	case AC97_PCM_Front_DAC_Rate:
1270	if (mixer_load(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)
1271	{
1272	mixer_store(pThis, index, u32);
1273	Log(("ac97: Set front DAC rate to %d\n", u32));
1274	open_voice(pThis, PO_INDEX, u32);
1275	}
1276	else
1277	Log(("ac97: Attempt to set front DAC rate to %d, but VRA is not set\n", u32));
1278	break;
1279	case AC97_MIC_ADC_Rate:
1280	if (mixer_load(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM)
1281	{
1282	mixer_store(pThis, index, u32);
1283	Log(("ac97: Set MIC ADC rate to %d\n", u32));
1284	open_voice(pThis, MC_INDEX, u32);
1285	}
1286	else
1287	Log(("ac97: Attempt to set MIC ADC rate to %d, but VRM is not set\n", u32));
1288	break;
1289	case AC97_PCM_LR_ADC_Rate:
1290	if (mixer_load(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)
1291	{
1292	mixer_store(pThis, index, u32);
1293	Log(("ac97: Set front LR ADC rate to %d\n", u32));
1294	open_voice(pThis, PI_INDEX, u32);
1295	}
1296	else
1297	Log(("ac97: Attempt to set LR ADC rate to %d, but VRA is not set\n", u32));
1298	break;
1299	default:
1300	Log(("ac97: U nam writew %#x <- %#x\n", Port, u32));
1301	mixer_store(pThis, index, u32);
1302	break;
1303	}
1304	break;
1305	}
1306
1307	case 4:
1308	{
1309	Log(("ac97: U nam writel %#x <- %#x\n", Port, u32));
1310	pThis->cas = 0;
1311	break;
1312	}
1313
1314	default:
1315	AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1316	break;
1317	}
1318	return VINF_SUCCESS;
1319	}
1320
1321
1322	/**
1323	* @callback_method_impl{FNPCIIOREGIONMAP}
1324	*/
1325	static DECLCALLBACK(int) ichac97IOPortMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
1326	PCIADDRESSSPACE enmType)
1327	{
1328	PPDMDEVINS pDevIns = pPciDev->pDevIns;
1329	PAC97STATE pThis = RT_FROM_MEMBER(pPciDev, AC97STATE, PciDev);
1330	RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1331	int rc;
1332
1333	Assert(enmType == PCI_ADDRESS_SPACE_IO);
1334	Assert(cb >= 0x20);
1335
1336	if (iRegion == 0)
1337	rc = PDMDevHlpIOPortRegister(pDevIns, Port, 256, pThis,
1338	ichac97IOPortNAMWrite, ichac97IOPortNAMRead,
1339	NULL, NULL, "ICHAC97 NAM");
1340	else
1341	rc = PDMDevHlpIOPortRegister(pDevIns, Port, 64, pThis,
1342	ichac97IOPortNABMWrite, ichac97IOPortNABMRead,
1343	NULL, NULL, "ICHAC97 NABM");
1344	if (RT_FAILURE(rc))
1345	return rc;
1346
1347	pThis->IOPortBase[iRegion] = Port;
1348	return VINF_SUCCESS;
1349	}
1350
1351
1352	/**
1353	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1354	*/
1355	static DECLCALLBACK(int) ichac97SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1356	{
1357	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, AC97STATE *);
1358
1359	SSMR3PutU32(pSSM, pThis->glob_cnt);
1360	SSMR3PutU32(pSSM, pThis->glob_sta);
1361	SSMR3PutU32(pSSM, pThis->cas);
1362
1363	for (unsigned i = 0; i < RT_ELEMENTS(pThis->bm_regs); i++)
1364	{
1365	PAC97BMREG pReg = &pThis->bm_regs[i];
1366	SSMR3PutU32(pSSM, pReg->bdbar);
1367	SSMR3PutU8( pSSM, pReg->civ);
1368	SSMR3PutU8( pSSM, pReg->lvi);
1369	SSMR3PutU16(pSSM, pReg->sr);
1370	SSMR3PutU16(pSSM, pReg->picb);
1371	SSMR3PutU8( pSSM, pReg->piv);
1372	SSMR3PutU8( pSSM, pReg->cr);
1373	SSMR3PutS32(pSSM, pReg->bd_valid);
1374	SSMR3PutU32(pSSM, pReg->bd.addr);
1375	SSMR3PutU32(pSSM, pReg->bd.ctl_len);
1376	}
1377	SSMR3PutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
1378
1379	uint8_t active[LAST_INDEX];
1380	active[PI_INDEX] = AUD_is_active_in( pThis->voice_pi) ? 1 : 0;
1381	active[PO_INDEX] = AUD_is_active_out(pThis->voice_po) ? 1 : 0;
1382	active[MC_INDEX] = AUD_is_active_in( pThis->voice_mc) ? 1 : 0;
1383	SSMR3PutMem(pSSM, active, sizeof(active));
1384
1385	return VINF_SUCCESS;
1386	}
1387
1388
1389	/**
1390	* @callback_method_impl{FNSSMDEVLOADEXEC}
1391	*/
1392	static DECLCALLBACK(int) ichac97LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1393	{
1394	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, AC97STATE *);
1395
1396	AssertMsgReturn (uVersion == AC97_SSM_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1397	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1398
1399	SSMR3GetU32(pSSM, &pThis->glob_cnt);
1400	SSMR3GetU32(pSSM, &pThis->glob_sta);
1401	SSMR3GetU32(pSSM, &pThis->cas);
1402
1403	for (unsigned i = 0; i < RT_ELEMENTS(pThis->bm_regs); i++)
1404	{
1405	PAC97BMREG pReg = &pThis->bm_regs[i];
1406	SSMR3GetU32(pSSM, &pReg->bdbar);
1407	SSMR3GetU8( pSSM, &pReg->civ);
1408	SSMR3GetU8( pSSM, &pReg->lvi);
1409	SSMR3GetU16(pSSM, &pReg->sr);
1410	SSMR3GetU16(pSSM, &pReg->picb);
1411	SSMR3GetU8( pSSM, &pReg->piv);
1412	SSMR3GetU8( pSSM, &pReg->cr);
1413	SSMR3GetS32(pSSM, &pReg->bd_valid);
1414	SSMR3GetU32(pSSM, &pReg->bd.addr);
1415	SSMR3GetU32(pSSM, &pReg->bd.ctl_len);
1416	}
1417
1418	SSMR3GetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
1419	uint8_t active[LAST_INDEX];
1420	SSMR3GetMem(pSSM, active, sizeof(active));
1421
1422	#ifdef USE_MIXER
1423	record_select(pThis, mixer_load(pThis, AC97_Record_Select));
1424	# define V_(a, b) set_volume(pThis, a, b, mixer_load(pThis, a))
1425	V_(AC97_Master_Volume_Mute, AUD_MIXER_VOLUME);
1426	V_(AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM);
1427	V_(AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN);
1428	# undef V_
1429	#endif /* USE_MIXER */
1430	reset_voices(pThis, active);
1431
1432	pThis->bup_flag = 0;
1433	pThis->last_samp = 0;
1434
1435	return VINF_SUCCESS;
1436	}
1437
1438
1439	/**
1440	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1441	*/
1442	static DECLCALLBACK(void ) ichac97QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
1443	{
1444	PAC97STATE pThis = RT_FROM_MEMBER(pInterface, AC97STATE, IBase);
1445	Assert(&pThis->IBase == pInterface);
1446
1447	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
1448	return NULL;
1449	}
1450
1451
1452	/**
1453	* @interface_method_impl{PDMDEVREG,pfnReset}
1454	*
1455	* @remarks The original sources didn't install a reset handler, but it seems to
1456	* make sense to me so we'll do it.
1457	*/
1458	static DECLCALLBACK(void) ac97Reset(PPDMDEVINS pDevIns)
1459	{
1460	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, AC97STATE *);
1461
1462	/*
1463	* Reset the device state (will need pDrv later).
1464	*/
1465	reset_bm_regs(pThis, &pThis->bm_regs[0]);
1466	reset_bm_regs(pThis, &pThis->bm_regs[1]);
1467	reset_bm_regs(pThis, &pThis->bm_regs[2]);
1468
1469	/*
1470	* Reset the mixer too. The Windows XP driver seems to rely on
1471	* this. At least it wants to read the vendor id before it resets
1472	* the codec manually.
1473	*/
1474	mixer_reset(pThis);
1475	}
1476
1477
1478	/**
1479	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1480	*/
1481	static DECLCALLBACK(int) ichac97Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1482	{
1483	AC97STATE pThis = PDMINS_2_DATA(pDevIns, AC97STATE );
1484	int rc;
1485
1486	Assert(iInstance == 0);
1487	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1488
1489	/*
1490	* Validations.
1491	*/
1492	if (!CFGMR3AreValuesValid(pCfg, "\0"))
1493	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1494	N_("Invalid configuration for the AC97 device"));
1495
1496	/*
1497	* Initialize data (most of it anyway).
1498	*/
1499	pThis->pDevIns = pDevIns;
1500	/* IBase */
1501	pThis->IBase.pfnQueryInterface = ichac97QueryInterface;
1502
1503	/* PCI Device (the assertions will be removed later) */
1504	PCIDevSetVendorId (&pThis->PciDev, 0x8086); /* 00 ro - intel. */ Assert(pThis->PciDev.config[0x00] == 0x86); Assert(pThis->PciDev.config[0x01] == 0x80);
1505	PCIDevSetDeviceId (&pThis->PciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pThis->PciDev.config[0x02] == 0x15); Assert(pThis->PciDev.config[0x03] == 0x24);
1506	PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pThis->PciDev.config[0x04] == 0x00); Assert(pThis->PciDev.config[0x05] == 0x00);
1507	PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM \| VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pThis->PciDev.config[0x06] == 0x80); Assert(pThis->PciDev.config[0x07] == 0x02);
1508	PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */ Assert(pThis->PciDev.config[0x08] == 0x01);
1509	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */ Assert(pThis->PciDev.config[0x09] == 0x00);
1510	PCIDevSetClassSub (&pThis->PciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pThis->PciDev.config[0x0a] == 0x01);
1511	PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */ Assert(pThis->PciDev.config[0x0b] == 0x04);
1512	PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */ Assert(pThis->PciDev.config[0x0e] == 0x00);
1513	PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - nambar - native audio mixer base. */
1514	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pThis->PciDev.config[0x10] == 0x01); Assert(pThis->PciDev.config[0x11] == 0x00); Assert(pThis->PciDev.config[0x12] == 0x00); Assert(pThis->PciDev.config[0x13] == 0x00);
1515	PCIDevSetBaseAddress (&pThis->PciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
1516	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pThis->PciDev.config[0x14] == 0x01); Assert(pThis->PciDev.config[0x15] == 0x00); Assert(pThis->PciDev.config[0x16] == 0x00); Assert(pThis->PciDev.config[0x17] == 0x00);
1517	PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x8086); /* 2c ro - intel.) */ Assert(pThis->PciDev.config[0x2c] == 0x86); Assert(pThis->PciDev.config[0x2d] == 0x80);
1518	PCIDevSetSubSystemId (&pThis->PciDev, 0x0000); /* 2e ro. */ Assert(pThis->PciDev.config[0x2e] == 0x00); Assert(pThis->PciDev.config[0x2f] == 0x00);
1519	PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */ Assert(pThis->PciDev.config[0x3c] == 0x00);
1520	PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */ Assert(pThis->PciDev.config[0x3d] == 0x01);
1521
1522	/*
1523	* Register the PCI device, it's I/O regions, the timer and the
1524	* saved state item.
1525	*/
1526	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
1527	if (RT_FAILURE (rc))
1528	return rc;
1529
1530	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 256, PCI_ADDRESS_SPACE_IO, ichac97IOPortMap);
1531	if (RT_FAILURE (rc))
1532	return rc;
1533
1534	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 64, PCI_ADDRESS_SPACE_IO, ichac97IOPortMap);
1535	if (RT_FAILURE (rc))
1536	return rc;
1537
1538	rc = PDMDevHlpSSMRegister(pDevIns, AC97_SSM_VERSION, sizeof(*pThis), ichac97SaveExec, ichac97LoadExec);
1539	if (RT_FAILURE (rc))
1540	return rc;
1541
1542	/*
1543	* Attach driver.
1544	*/
1545	rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Audio Driver Port");
1546	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1547	Log(("ac97: No attached driver!\n"));
1548	else if (RT_FAILURE(rc))
1549	{
1550	AssertMsgFailed(("Failed to attach AC97 LUN #0! rc=%Rrc\n", rc));
1551	return rc;
1552	}
1553
1554	AUD_register_card("ICH0", &pThis->card);
1555
1556	ac97Reset(pDevIns);
1557
1558	if (!AUD_is_host_voice_in_ok(pThis->voice_pi))
1559	LogRel(("AC97: WARNING: Unable to open PCM IN!\n"));
1560	if (!AUD_is_host_voice_in_ok(pThis->voice_mc))
1561	LogRel(("AC97: WARNING: Unable to open PCM MC!\n"));
1562	if (!AUD_is_host_voice_out_ok(pThis->voice_po))
1563	LogRel(("AC97: WARNING: Unable to open PCM OUT!\n"));
1564
1565	if ( !AUD_is_host_voice_in_ok( pThis->voice_pi)
1566	&& !AUD_is_host_voice_out_ok(pThis->voice_po)
1567	&& !AUD_is_host_voice_in_ok( pThis->voice_mc))
1568	{
1569	/* Was not able initialize any voice. Select the NULL audio driver instead */
1570	AUD_close_in( &pThis->card, pThis->voice_pi);
1571	AUD_close_out(&pThis->card, pThis->voice_po);
1572	AUD_close_in( &pThis->card, pThis->voice_mc);
1573	pThis->voice_po = NULL;
1574	pThis->voice_pi = NULL;
1575	pThis->voice_mc = NULL;
1576	AUD_init_null();
1577	ac97Reset(pDevIns);
1578
1579	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
1580	N_("No audio devices could be opened. Selecting the NULL audio backend "
1581	"with the consequence that no sound is audible"));
1582	}
1583	else if ( !AUD_is_host_voice_in_ok( pThis->voice_pi)
1584	\|\| !AUD_is_host_voice_out_ok(pThis->voice_po)
1585	\|\| !AUD_is_host_voice_in_ok( pThis->voice_mc))
1586	{
1587	char szMissingVoices[128];
1588	size_t len = 0;
1589	if (!AUD_is_host_voice_in_ok(pThis->voice_pi))
1590	len = RTStrPrintf(szMissingVoices, sizeof(szMissingVoices), "PCM_in");
1591	if (!AUD_is_host_voice_out_ok(pThis->voice_po))
1592	len += RTStrPrintf(szMissingVoices + len, sizeof(szMissingVoices) - len, len ? ", PCM_out" : "PCM_out");
1593	if (!AUD_is_host_voice_in_ok(pThis->voice_mc))
1594	len += RTStrPrintf(szMissingVoices + len, sizeof(szMissingVoices) - len, len ? ", PCM_mic" : "PCM_mic");
1595
1596	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
1597	N_("Some audio devices (%s) could not be opened. Guest applications generating audio "
1598	"output or depending on audio input may hang. Make sure your host audio device "
1599	"is working properly. Check the logfile for error messages of the audio "
1600	"subsystem"), szMissingVoices);
1601	}
1602
1603	return VINF_SUCCESS;
1604	}
1605
1606	/**
1607	* The device registration structure.
1608	*/
1609	const PDMDEVREG g_DeviceICHAC97 =
1610	{
1611	/* u32Version */
1612	PDM_DEVREG_VERSION,
1613	/* szName */
1614	"ichac97",
1615	/* szRCMod */
1616	"",
1617	/* szR0Mod */
1618	"",
1619	/* pszDescription */
1620	"ICH AC'97 Audio Controller",
1621	/* fFlags */
1622	PDM_DEVREG_FLAGS_DEFAULT_BITS,
1623	/* fClass */
1624	PDM_DEVREG_CLASS_AUDIO,
1625	/* cMaxInstances */
1626	1,
1627	/* cbInstance */
1628	sizeof(AC97STATE),
1629	/* pfnConstruct */
1630	ichac97Construct,
1631	/* pfnDestruct */
1632	NULL,
1633	/* pfnRelocate */
1634	NULL,
1635	/* pfnMemSetup */
1636	NULL,
1637	/* pfnPowerOn */
1638	NULL,
1639	/* pfnReset */
1640	ac97Reset,
1641	/* pfnSuspend */
1642	NULL,
1643	/* pfnResume */
1644	NULL,
1645	/* pfnAttach */
1646	NULL,
1647	/* pfnDetach */
1648	NULL,
1649	/* pfnQueryInterface. */
1650	NULL,
1651	/* pfnInitComplete */
1652	NULL,
1653	/* pfnPowerOff */
1654	NULL,
1655	/* pfnSoftReset */
1656	NULL,
1657	/* u32VersionEnd */
1658	PDM_DEVREG_VERSION
1659	};

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source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 49498

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