VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 59113

Last change on this file since 59113 was 59102, checked in by vboxsync, 9 years ago

Audio: Fixed recording glitches.
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File size: 88.2 KB
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1/* $Id: DevIchAc97.cpp 59102 2015-12-11 16:27:22Z vboxsync $ */
2/** @file
3 * DevIchAc97 - VBox ICH AC97 Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_AC97
23#include <VBox/log.h>
24#include <VBox/vmm/pdmdev.h>
25#include <VBox/vmm/pdmaudioifs.h>
26
27#include <iprt/assert.h>
28#ifdef IN_RING3
29# include <iprt/mem.h>
30# include <iprt/string.h>
31# include <iprt/uuid.h>
32#endif
33
34#include "VBoxDD.h"
35
36#include "AudioMixBuffer.h"
37#include "AudioMixer.h"
38
39
40/*********************************************************************************************************************************
41* Defined Constants And Macros *
42*********************************************************************************************************************************/
43
44#ifdef DEBUG
45//#define DEBUG_LUN
46# ifdef DEBUG_LUN
47# define DEBUG_LUN_NUM 1
48# endif
49#endif /* DEBUG */
50
51#define AC97_SSM_VERSION 1
52
53#ifdef VBOX
54# define SOFT_VOLUME /** @todo Get rid of this crap. */
55#else
56# define SOFT_VOLUME
57#endif
58
59#define SR_FIFOE RT_BIT(4) /* rwc, FIFO error. */
60#define SR_BCIS RT_BIT(3) /* rwc, Buffer completion interrupt status. */
61#define SR_LVBCI RT_BIT(2) /* rwc, Last valid buffer completion interrupt. */
62#define SR_CELV RT_BIT(1) /* ro, Current equals last valid. */
63#define SR_DCH RT_BIT(0) /* ro, Controller halted. */
64#define SR_VALID_MASK (RT_BIT(5) - 1)
65#define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
66#define SR_RO_MASK (SR_DCH | SR_CELV)
67#define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
68
69#define CR_IOCE RT_BIT(4) /* rw, Interrupt On Completion Enable. */
70#define CR_FEIE RT_BIT(3) /* rw FIFO Error Interrupt Enable. */
71#define CR_LVBIE RT_BIT(2) /* rw */
72#define CR_RR RT_BIT(1) /* rw */
73#define CR_RPBM RT_BIT(0) /* rw */
74#define CR_VALID_MASK (RT_BIT(5) - 1)
75#define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
76
77#define GC_WR 4 /* rw */
78#define GC_CR 2 /* rw */
79#define GC_VALID_MASK (RT_BIT(6) - 1)
80
81#define GS_MD3 RT_BIT(17) /* rw */
82#define GS_AD3 RT_BIT(16) /* rw */
83#define GS_RCS RT_BIT(15) /* rwc */
84#define GS_B3S12 RT_BIT(14) /* ro */
85#define GS_B2S12 RT_BIT(13) /* ro */
86#define GS_B1S12 RT_BIT(12) /* ro */
87#define GS_S1R1 RT_BIT(11) /* rwc */
88#define GS_S0R1 RT_BIT(10) /* rwc */
89#define GS_S1CR RT_BIT(9) /* ro */
90#define GS_S0CR RT_BIT(8) /* ro */
91#define GS_MINT RT_BIT(7) /* ro */
92#define GS_POINT RT_BIT(6) /* ro */
93#define GS_PIINT RT_BIT(5) /* ro */
94#define GS_RSRVD (RT_BIT(4)|RT_BIT(3))
95#define GS_MOINT RT_BIT(2) /* ro */
96#define GS_MIINT RT_BIT(1) /* ro */
97#define GS_GSCI RT_BIT(0) /* rwc */
98#define GS_RO_MASK (GS_B3S12 | \
99 GS_B2S12 | \
100 GS_B1S12 | \
101 GS_S1CR | \
102 GS_S0CR | \
103 GS_MINT | \
104 GS_POINT | \
105 GS_PIINT | \
106 GS_RSRVD | \
107 GS_MOINT | \
108 GS_MIINT)
109#define GS_VALID_MASK (RT_BIT(18) - 1)
110#define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
111
112/** @name Buffer Descriptor
113 * @{ */
114#define BD_IOC RT_BIT(31) /**< Interrupt on Completion */
115#define BD_BUP RT_BIT(30) /**< Buffer Underrun Policy */
116/** @} */
117
118#define EACS_VRA 1
119#define EACS_VRM 8
120
121#define VOL_MASK 0x1f
122#define MUTE_SHIFT 15
123
124#define REC_MASK 7
125enum
126{
127 REC_MIC = 0,
128 REC_CD,
129 REC_VIDEO,
130 REC_AUX,
131 REC_LINE_IN,
132 REC_STEREO_MIX,
133 REC_MONO_MIX,
134 REC_PHONE
135};
136
137enum
138{
139 AC97_Reset = 0x00,
140 AC97_Master_Volume_Mute = 0x02,
141 AC97_Headphone_Volume_Mute = 0x04, /** Also known as AUX, see table 16, section 5.7. */
142 AC97_Master_Volume_Mono_Mute = 0x06,
143 AC97_Master_Tone_RL = 0x08,
144 AC97_PC_BEEP_Volume_Mute = 0x0A,
145 AC97_Phone_Volume_Mute = 0x0C,
146 AC97_Mic_Volume_Mute = 0x0E,
147 AC97_Line_In_Volume_Mute = 0x10,
148 AC97_CD_Volume_Mute = 0x12,
149 AC97_Video_Volume_Mute = 0x14,
150 AC97_Aux_Volume_Mute = 0x16,
151 AC97_PCM_Out_Volume_Mute = 0x18,
152 AC97_Record_Select = 0x1A,
153 AC97_Record_Gain_Mute = 0x1C,
154 AC97_Record_Gain_Mic_Mute = 0x1E,
155 AC97_General_Purpose = 0x20,
156 AC97_3D_Control = 0x22,
157 AC97_AC_97_RESERVED = 0x24,
158 AC97_Powerdown_Ctrl_Stat = 0x26,
159 AC97_Extended_Audio_ID = 0x28,
160 AC97_Extended_Audio_Ctrl_Stat = 0x2A,
161 AC97_PCM_Front_DAC_Rate = 0x2C,
162 AC97_PCM_Surround_DAC_Rate = 0x2E,
163 AC97_PCM_LFE_DAC_Rate = 0x30,
164 AC97_PCM_LR_ADC_Rate = 0x32,
165 AC97_MIC_ADC_Rate = 0x34,
166 AC97_6Ch_Vol_C_LFE_Mute = 0x36,
167 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
168 AC97_Vendor_Reserved = 0x58,
169 AC97_AD_Misc = 0x76,
170 AC97_Vendor_ID1 = 0x7c,
171 AC97_Vendor_ID2 = 0x7e
172};
173
174/* Codec models. */
175enum {
176 Codec_STAC9700 = 0, /* SigmaTel STAC9700 */
177 Codec_AD1980, /* Analog Devices AD1980 */
178 Codec_AD1981B /* Analog Devices AD1981B */
179};
180
181/* Analog Devices miscellaneous regiter bits used in AD1980. */
182#define AD_MISC_LOSEL RT_BIT(5) /* Surround (rear) goes to line out outputs. */
183#define AD_MISC_HPSEL RT_BIT(10) /* PCM (front) goes to headphone outputs. */
184
185#define ICHAC97STATE_2_DEVINS(a_pAC97) ((a_pAC97)->pDevInsR3)
186
187enum
188{
189 BUP_SET = RT_BIT(0),
190 BUP_LAST = RT_BIT(1)
191};
192
193/** Emits registers for a specific (Native Audio Bus Master BAR) NABMBAR. */
194#define AC97_NABMBAR_REGS(prefix, off) \
195 enum { \
196 prefix ## _BDBAR = off, \
197 prefix ## _CIV = off + 4, \
198 prefix ## _LVI = off + 5, \
199 prefix ## _SR = off + 6, \
200 prefix ## _PICB = off + 8, \
201 prefix ## _PIV = off + 10, \
202 prefix ## _CR = off + 11 \
203 }
204
205#ifndef VBOX_DEVICE_STRUCT_TESTCASE
206typedef enum
207{
208 PI_INDEX = 0, /** PCM in */
209 PO_INDEX, /** PCM out */
210 MC_INDEX, /** Mic in */
211 LAST_INDEX
212} AC97SOUNDSOURCE;
213
214AC97_NABMBAR_REGS(PI, PI_INDEX * 16);
215AC97_NABMBAR_REGS(PO, PO_INDEX * 16);
216AC97_NABMBAR_REGS(MC, MC_INDEX * 16);
217#endif
218
219enum
220{
221 /** NABMBAR: Global Control Register. */
222 GLOB_CNT = 0x2c,
223 /** NABMBAR Global Status. */
224 GLOB_STA = 0x30,
225 /** Codec Access Semaphore Register. */
226 CAS = 0x34
227};
228
229#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
230
231/*********************************************************************************************************************************
232* Structures and Typedefs *
233*********************************************************************************************************************************/
234
235/**
236 * Buffer Descriptor List Entry (BDLE).
237 */
238typedef struct AC97BDLE
239{
240 uint32_t addr;
241 uint32_t ctl_len;
242} AC97BDLE, *PAC97BDLE;
243
244/**
245 * Bus master register set for an audio stream.
246 */
247typedef struct AC97BMREGS
248{
249 uint32_t bdbar; /** rw 0, Buffer Descriptor List: BAR (Base Address Register). */
250 uint8_t civ; /** ro 0, Current index value. */
251 uint8_t lvi; /** rw 0, Last valid index. */
252 uint16_t sr; /** rw 1, Status register. */
253 uint16_t picb; /** ro 0, Position in current buffer. */
254 uint8_t piv; /** ro 0, Prefetched index value. */
255 uint8_t cr; /** rw 0, Control register. */
256 int bd_valid; /** Whether current BDLE is initialized or not. */
257 AC97BDLE bd; /** Current Buffer Descriptor List Entry (BDLE). */
258} AC97BMREGS, *PAC97BMREGS;
259
260/**
261 * Internal state of an AC97 stream.
262 */
263typedef struct AC97STREAMSTATE
264{
265 /* Nothing yet. */
266} AC97STREAMSTATE, *PAC97STREAMSTATE;
267
268/**
269 * Structure for keeping an AC97 stream state.
270 *
271 * Contains only register values which do *not* change until a
272 * stream reset occurs.
273 */
274typedef struct AC97STREAM
275{
276 /** Stream number (SDn). */
277 uint8_t u8Strm;
278 /** Bus master registers of this stream. */
279 AC97BMREGS Regs;
280 /** Internal state of this stream. */
281 AC97STREAMSTATE State;
282} AC97STREAM, *PAC97STREAM;
283
284typedef struct AC97INPUTSTREAM
285{
286 /** PCM line input stream. */
287 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
288 /** Mixer handle for line input stream. */
289 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
290} AC97INPUTSTREAM, *PAC97INPUTSTREAM;
291
292typedef struct AC97OUTPUTSTREAM
293{
294 /** PCM output stream. */
295 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
296 /** Mixer handle for output stream. */
297 R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
298} AC97OUTPUTSTREAM, *PAC97OUTPUTSTREAM;
299
300/**
301 * Struct for maintaining a host backend driver.
302 */
303typedef struct AC97STATE *PAC97STATE;
304typedef struct AC97DRIVER
305{
306 union
307 {
308 /** Node for storing this driver in our device driver
309 * list of AC97STATE. */
310 RTLISTNODE Node;
311 struct
312 {
313 R3PTRTYPE(void *) dummy1;
314 R3PTRTYPE(void *) dummy2;
315 } dummy;
316 };
317
318 /** Pointer to AC97 controller (state). */
319 R3PTRTYPE(PAC97STATE) pAC97State;
320 /** Driver flags. */
321 PDMAUDIODRVFLAGS Flags;
322 uint32_t PaddingFlags;
323 /** LUN # to which this driver has been assigned. */
324 uint8_t uLUN;
325 uint8_t Padding[5];
326 /** Audio connector interface to the underlying
327 * host backend. */
328 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
329 /** Stream for line input. */
330 AC97INPUTSTREAM LineIn;
331 /** Stream for mic input. */
332 AC97INPUTSTREAM MicIn;
333 /** Stream for output. */
334 AC97OUTPUTSTREAM Out;
335} AC97DRIVER, *PAC97DRIVER;
336
337typedef struct AC97STATE
338{
339 /** The PCI device state. */
340 PCIDevice PciDev;
341 /** R3 Pointer to the device instance. */
342 PPDMDEVINSR3 pDevInsR3;
343 /** Global Control (Bus Master Control Register) */
344 uint32_t glob_cnt;
345 /** Global Status (Bus Master Control Register) */
346 uint32_t glob_sta;
347 /** Codec Access Semaphore Register (Bus Master Control Register) */
348 uint32_t cas;
349 uint32_t last_samp;
350 uint8_t mixer_data[256];
351 /** Stream state for line-in. */
352 AC97STREAM StrmStLineIn;
353 /** Stream state for microphone-in. */
354 AC97STREAM StrmStMicIn;
355 /** Stream state for output. */
356 AC97STREAM StrmStOut;
357#ifndef VBOX_WITH_AUDIO_CALLBACKS
358 /** The emulation timer for handling the attached
359 * LUN drivers. */
360 PTMTIMERR3 pTimer;
361 /** Timer ticks for handling the LUN drivers. */
362 uint64_t uTimerTicks;
363 /** Timestamp (delta) since last timer call. */
364 uint64_t uTimerTS;
365#endif
366#ifdef VBOX_WITH_STATISTICS
367 STAMPROFILE StatTimer;
368 STAMCOUNTER StatBytesRead;
369 STAMCOUNTER StatBytesWritten;
370#endif
371 /** List of associated LUN drivers. */
372 RTLISTANCHOR lstDrv;
373 /** The device' software mixer. */
374 R3PTRTYPE(PAUDIOMIXER) pMixer;
375 /** Audio sink for PCM output. */
376 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
377 /** Audio sink for line input. */
378 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
379 /** Audio sink for microphone input. */
380 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
381 uint8_t silence[128];
382 int bup_flag;
383 /** Pointer to the attached audio driver. */
384 PPDMIBASE pDrvBase;
385 /** The base interface for LUN\#0. */
386 PDMIBASE IBase;
387 /** Base port of the I/O space region. */
388 RTIOPORT IOPortBase[2];
389 /** Pointer to temporary scratch read/write buffer. */
390 R3PTRTYPE(uint8_t *) pvReadWriteBuf;
391 /** Size of the temporary scratch read/write buffer. */
392 uint32_t cbReadWriteBuf;
393 /** Codec model. */
394 uint32_t uCodecModel;
395} AC97STATE, *PAC97STATE;
396
397#ifdef VBOX_WITH_STATISTICS
398AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
399#endif
400
401#ifndef VBOX_DEVICE_STRUCT_TESTCASE
402
403DECLINLINE(PAC97STREAM) ichac97GetStreamFromID(PAC97STATE pThis, uint32_t uID);
404static DECLCALLBACK(void) ichac97Reset(PPDMDEVINS pDevIns);
405#ifndef VBOX_WITH_AUDIO_CALLBACKS
406static DECLCALLBACK(void) ichac97Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
407#endif
408static int ichac97TransferAudio(PAC97STATE pThis, AC97SOUNDSOURCE enmSrc, uint32_t cbElapsed);
409
410static void ichac97WarmReset(PAC97STATE pThis)
411{
412 NOREF(pThis);
413}
414
415static void ichac97ColdReset(PAC97STATE pThis)
416{
417 NOREF(pThis);
418}
419
420/** Fetches the buffer descriptor at _CIV. */
421static void ichac97StreamFetchBDLE(PAC97STATE pThis, PAC97STREAM pStrmSt)
422{
423 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
424 PAC97BMREGS pRegs = &pStrmSt->Regs;
425
426 uint32_t u32[2];
427
428 PDMDevHlpPhysRead(pDevIns, pRegs->bdbar + pRegs->civ * 8, &u32[0], sizeof(u32));
429 pRegs->bd_valid = 1;
430#if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)
431# error Please adapt the code (audio buffers are little endian)!
432#else
433 pRegs->bd.addr = RT_H2LE_U32(u32[0] & ~3);
434 pRegs->bd.ctl_len = RT_H2LE_U32(u32[1]);
435#endif
436 pRegs->picb = pRegs->bd.ctl_len & 0xffff;
437 LogFlowFunc(("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
438 pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len >> 16,
439 pRegs->bd.ctl_len & 0xffff, (pRegs->bd.ctl_len & 0xffff) << 1));
440}
441
442/**
443 * Update the BM status register
444 */
445static void ichac97StreamUpdateStatus(PAC97STATE pThis, PAC97STREAM pStrmSt, uint32_t new_sr)
446{
447 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
448 PAC97BMREGS pRegs = &pStrmSt->Regs;
449
450 bool fSignal = false;
451 bool iIrqLevel;
452
453 uint32_t new_mask = new_sr & SR_INT_MASK;
454 uint32_t old_mask = pRegs->sr & SR_INT_MASK;
455
456 static uint32_t const masks[] = { GS_PIINT, GS_POINT, GS_MINT };
457
458 if (new_mask ^ old_mask)
459 {
460 /** @todo Is IRQ deasserted when only one of status bits is cleared? */
461 if (!new_mask)
462 {
463 fSignal = true;
464 iIrqLevel = 0;
465 }
466 else if ((new_mask & SR_LVBCI) && (pRegs->cr & CR_LVBIE))
467 {
468 fSignal = true;
469 iIrqLevel = 1;
470 }
471 else if ((new_mask & SR_BCIS) && (pRegs->cr & CR_IOCE))
472 {
473 fSignal = true;
474 iIrqLevel = 1;
475 }
476 }
477
478 pRegs->sr = new_sr;
479
480 LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, iIrqLevel=%d\n",
481 pRegs->sr & SR_BCIS, pRegs->sr & SR_LVBCI, pRegs->sr, fSignal, iIrqLevel));
482
483 if (fSignal)
484 {
485 if (iIrqLevel)
486 pThis->glob_sta |= masks[pStrmSt->u8Strm];
487 else
488 pThis->glob_sta &= ~masks[pStrmSt->u8Strm];
489
490 LogFlowFunc(("set irq level=%d\n", !!iIrqLevel));
491 PDMDevHlpPCISetIrq(pDevIns, 0, !!iIrqLevel);
492 }
493}
494
495static int ichac97StreamSetActive(PAC97STATE pThis, PAC97STREAM pStrmSt, bool fActive)
496{
497 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
498 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
499
500 LogFlowFunc(("u8Strm=%RU8, fActive=%RTbool\n", pStrmSt->u8Strm, fActive));
501
502 int rc = VINF_SUCCESS;
503
504 PAC97DRIVER pDrv;
505 switch (pStrmSt->u8Strm)
506 {
507 case PI_INDEX:
508 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
509 {
510 int rc2 = pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
511 pDrv->LineIn.pStrmIn, fActive);
512 if (RT_SUCCESS(rc))
513 rc = rc2;
514 }
515 break;
516
517 case PO_INDEX:
518 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
519 {
520 int rc2 = pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
521 pDrv->Out.pStrmOut, fActive);
522 if (RT_SUCCESS(rc))
523 rc = rc2;
524 }
525 break;
526
527 case MC_INDEX:
528 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
529 {
530 int rc2 = pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
531 pDrv->MicIn.pStrmIn, fActive);
532 if (RT_SUCCESS(rc))
533 rc = rc2;
534 }
535 break;
536
537 default:
538 AssertMsgFailed(("Wrong index %RU32\n", pStrmSt->u8Strm));
539 rc = VERR_NOT_SUPPORTED;
540 break;
541 }
542
543 return rc;
544}
545
546static void ichac97StreamResetBMRegs(PAC97STATE pThis, PAC97STREAM pStrmSt)
547{
548 AssertPtrReturnVoid(pThis);
549 AssertPtrReturnVoid(pStrmSt);
550
551 LogFlowFuncEnter();
552
553 PAC97BMREGS pRegs = &pStrmSt->Regs;
554
555 pRegs->bdbar = 0;
556 pRegs->civ = 0;
557 pRegs->lvi = 0;
558
559 ichac97StreamUpdateStatus(pThis, pStrmSt, SR_DCH); /** @todo Do we need to do that? */
560
561 pRegs->picb = 0;
562 pRegs->piv = 0;
563 pRegs->cr = pRegs->cr & CR_DONT_CLEAR_MASK;
564 pRegs->bd_valid = 0;
565
566 int rc = ichac97StreamSetActive(pThis, pStrmSt, false /* fActive */);
567 AssertRC(rc);
568
569 RT_ZERO(pThis->silence);
570}
571
572static void ichac97MixerSet(PAC97STATE pThis, uint32_t u8Idx, uint16_t v)
573{
574 if (u8Idx + 2 > sizeof(pThis->mixer_data))
575 {
576 AssertMsgFailed(("Index %RU8 out of bounds(%zu)\n", u8Idx, sizeof(pThis->mixer_data)));
577 return;
578 }
579
580 pThis->mixer_data[u8Idx + 0] = RT_LO_U8(v);
581 pThis->mixer_data[u8Idx + 1] = RT_HI_U8(v);
582}
583
584static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t u8Idx)
585{
586 uint16_t uVal;
587
588 if (u8Idx + 2 > sizeof(pThis->mixer_data))
589 {
590 AssertMsgFailed(("Index %RU8 out of bounds (%zu)\n", u8Idx, sizeof(pThis->mixer_data)));
591 uVal = UINT16_MAX;
592 }
593 else
594 uVal = RT_MAKE_U16(pThis->mixer_data[u8Idx + 0], pThis->mixer_data[u8Idx + 1]);
595
596 return uVal;
597}
598
599static DECLCALLBACK(void) ichac97CloseIn(PAC97STATE pThis, PDMAUDIORECSOURCE enmRecSource)
600{
601 NOREF(pThis);
602 NOREF(enmRecSource);
603 LogFlowFuncEnter();
604}
605
606static DECLCALLBACK(void) ichac97CloseOut(PAC97STATE pThis)
607{
608 NOREF(pThis);
609 LogFlowFuncEnter();
610}
611
612static int ichac97OpenIn(PAC97STATE pThis,
613 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
614 PPDMAUDIOSTREAMCFG pCfg)
615{
616 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
617 AssertPtrReturn(pszName, VERR_INVALID_POINTER);
618 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
619
620 PAUDMIXSINK pSink;
621 switch (enmRecSource)
622 {
623 case PDMAUDIORECSOURCE_MIC:
624 pSink = pThis->pSinkMicIn;
625 break;
626 case PDMAUDIORECSOURCE_LINE_IN:
627 pSink = pThis->pSinkLineIn;
628 break;
629 default:
630 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
631 return VERR_NOT_SUPPORTED;
632 }
633
634 int rc = VINF_SUCCESS;
635
636 PAC97DRIVER pDrv;
637 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
638 {
639 char *pszDesc;
640 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
641 {
642 rc = VERR_NO_MEMORY;
643 break;
644 }
645
646 PAC97INPUTSTREAM pStrmIn;
647 if (enmRecSource == PDMAUDIORECSOURCE_MIC) /** @todo Refine this once we have more streams. */
648 pStrmIn = &pDrv->MicIn;
649 else
650 pStrmIn = &pDrv->LineIn;
651
652 rc = pDrv->pConnector->pfnCreateIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pStrmIn->pStrmIn);
653
654 LogFlowFunc(("LUN#%RU8: Created input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
655 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
656 {
657 AudioMixerRemoveStream(pSink, pStrmIn->phStrmIn);
658 rc = AudioMixerAddStreamIn(pSink,
659 pDrv->pConnector, pStrmIn->pStrmIn,
660 0 /* uFlags */, &pStrmIn->phStrmIn);
661 }
662
663 RTStrFree(pszDesc);
664 }
665
666 LogFlowFuncLeaveRC(rc);
667 return rc;
668}
669
670static int ichac97OpenOut(PAC97STATE pThis, const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
671{
672 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
673 AssertPtrReturn(pszName, VERR_INVALID_POINTER);
674 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
675
676 int rc = VINF_SUCCESS;
677 char *pszDesc;
678
679 PAC97DRIVER pDrv;
680 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
681 {
682 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s (%RU32Hz, %RU8 %s)",
683 pDrv->uLUN, pszName, pCfg->uHz, pCfg->cChannels, pCfg->cChannels > 1 ? "Channels" : "Channel") <= 0)
684 {
685 rc = VERR_NO_MEMORY;
686 break;
687 }
688
689 rc = pDrv->pConnector->pfnCreateOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
690 LogFlowFunc(("LUN#%RU8: Created output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
691 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
692 {
693 AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
694 rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
695 pDrv->pConnector, pDrv->Out.pStrmOut,
696 0 /* uFlags */, &pDrv->Out.phStrmOut);
697 }
698
699 RTStrFree(pszDesc);
700 }
701
702 LogFlowFuncLeaveRC(rc);
703 return rc;
704}
705
706static int ichac97StreamInitEx(PAC97STATE pThis, PAC97STREAM pStrmSt, uint8_t u8Strm, PPDMAUDIOSTREAMCFG pCfg)
707{
708 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
709 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
710 AssertReturn(u8Strm <= LAST_INDEX, VERR_INVALID_PARAMETER);
711 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
712
713 pStrmSt->u8Strm = u8Strm;
714
715 LogFlowFunc(("u8Strm=%RU8, %RU32Hz, %RU8 %s\n",
716 pStrmSt->u8Strm, pCfg->uHz, pCfg->cChannels, pCfg->cChannels > 1 ? "Channels" : "Channel"));
717
718 int rc;
719 switch (pStrmSt->u8Strm)
720 {
721 case PI_INDEX:
722 rc = ichac97OpenIn(pThis, "ac97.pi", PDMAUDIORECSOURCE_LINE_IN, pCfg);
723 break;
724
725 case MC_INDEX:
726 rc = ichac97OpenIn(pThis, "ac97.mc", PDMAUDIORECSOURCE_MIC, pCfg);
727 break;
728
729 case PO_INDEX:
730 rc = ichac97OpenOut(pThis, "ac97.po", pCfg);
731 break;
732
733 default:
734 rc = VERR_NOT_SUPPORTED;
735 break;
736 }
737
738 LogFlowFuncLeaveRC(rc);
739 return rc;
740}
741
742static int ichac97StreamInit(PAC97STATE pThis, PAC97STREAM pStrmSt, uint8_t u8Strm)
743{
744 int rc = VINF_SUCCESS;
745
746 PDMAUDIOSTREAMCFG streamCfg;
747 RT_ZERO(streamCfg);
748
749 switch (u8Strm)
750 {
751 case PI_INDEX:
752 streamCfg.uHz = ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate);
753 break;
754
755 case MC_INDEX:
756 streamCfg.uHz = ichac97MixerGet(pThis, AC97_MIC_ADC_Rate);
757 break;
758
759 case PO_INDEX:
760 streamCfg.uHz = ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate);
761 break;
762
763 default:
764 rc = VERR_NOT_SUPPORTED;
765 break;
766 }
767
768 if (RT_FAILURE(rc))
769 return rc;
770
771 if (streamCfg.uHz)
772 {
773 streamCfg.cChannels = 2;
774 streamCfg.enmFormat = AUD_FMT_S16;
775 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
776
777 return ichac97StreamInitEx(pThis, pStrmSt, u8Strm, &streamCfg);
778 }
779
780 /* If no frequency is given, disable the stream. */
781 return ichac97StreamSetActive(pThis, pStrmSt, false /* fActive */);
782}
783
784static int ichac97StreamReInit(PAC97STATE pThis, PAC97STREAM pStrmSt)
785{
786 return ichac97StreamInit(pThis, pStrmSt, pStrmSt->u8Strm);
787}
788
789static void ichac97StreamReset(PAC97STATE pThis, PAC97STREAM pStrmSt)
790{
791 AssertPtrReturnVoid(pThis);
792 AssertPtrReturnVoid(pStrmSt);
793
794 LogFlowFunc(("uStrm=%RU8\n", pStrmSt->u8Strm));
795}
796
797static int ichac97MixerSetVolume(PAC97STATE pThis, int index, PDMAUDIOMIXERCTL mt, uint32_t val)
798{
799 int mute = (val >> MUTE_SHIFT) & 1;
800 uint8_t rvol = val & VOL_MASK;
801 uint8_t lvol = (val >> 8) & VOL_MASK;
802
803 /* For the master volume, 0 corresponds to 0dB gain. But for the other
804 * volume controls, 0 corresponds to +12dB and 8 to 0dB. */
805 if (mt != PDMAUDIOMIXERCTL_VOLUME)
806 {
807 /* NB: Currently there is no gain support, only attenuation. */
808 lvol = lvol < 8 ? 0 : lvol - 8;
809 rvol = rvol < 8 ? 0 : rvol - 8;
810 }
811
812 /* AC'97 has 1.5dB steps; we use 0.375dB steps. */
813 rvol = 255 - rvol * 4;
814 lvol = 255 - lvol * 4;
815
816 LogFunc(("mt=%ld, val=%RX32, mute=%RTbool\n", mt, val, RT_BOOL(mute)));
817
818 int rc;
819
820#ifdef SOFT_VOLUME
821 if (pThis->pMixer) /* Device can be in reset state, so no mixer available. */
822 {
823 PDMAUDIOVOLUME vol = { RT_BOOL(mute), lvol, rvol };
824 switch (mt)
825 {
826 case PDMAUDIOMIXERCTL_VOLUME:
827 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
828 break;
829
830 case PDMAUDIOMIXERCTL_PCM:
831 rc = AudioMixerSetSinkVolume(pThis->pSinkOutput, &vol);
832 break;
833
834 case PDMAUDIOMIXERCTL_MIC_IN:
835 rc = AudioMixerSetSinkVolume(pThis->pSinkMicIn, &vol);
836 break;
837
838 case PDMAUDIOMIXERCTL_LINE_IN:
839 rc = AudioMixerSetSinkVolume(pThis->pSinkLineIn, &vol);
840 break;
841
842 default:
843 rc = VERR_NOT_SUPPORTED;
844 break;
845 }
846 }
847
848 if (RT_FAILURE(rc))
849 return rc;
850#else
851 rc = VINF_SUCCESS;
852#endif /* SOFT_VOLUME */
853
854 rvol = VOL_MASK - ((VOL_MASK * rvol) / 255);
855 lvol = VOL_MASK - ((VOL_MASK * lvol) / 255);
856
857 /*
858 * From AC'97 SoundMax Codec AD1981A: "Because AC '97 defines 6-bit volume registers, to
859 * maintain compatibility whenever the D5 or D13 bits are set to `1,' their respective
860 * lower five volume bits are automatically set to `1' by the Codec logic. On readback,
861 * all lower 5 bits will read ones whenever these bits are set to `1.'"
862 *
863 * Linux ALSA depends on this behavior.
864 */
865 if (val & RT_BIT(5))
866 val |= RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0);
867 if (val & RT_BIT(13))
868 val |= RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8);
869
870 ichac97MixerSet(pThis, index, val);
871
872 return rc;
873}
874
875static PDMAUDIORECSOURCE ichac97IndextoRecSource(uint8_t i)
876{
877 switch (i)
878 {
879 case REC_MIC: return PDMAUDIORECSOURCE_MIC;
880 case REC_CD: return PDMAUDIORECSOURCE_CD;
881 case REC_VIDEO: return PDMAUDIORECSOURCE_VIDEO;
882 case REC_AUX: return PDMAUDIORECSOURCE_AUX;
883 case REC_LINE_IN: return PDMAUDIORECSOURCE_LINE_IN;
884 case REC_PHONE: return PDMAUDIORECSOURCE_PHONE;
885 default:
886 break;
887 }
888
889 LogFlowFunc(("Unknown record source %d, using MIC\n", i));
890 return PDMAUDIORECSOURCE_MIC;
891}
892
893static uint8_t ichac97RecSourceToIndex(PDMAUDIORECSOURCE rs)
894{
895 switch (rs)
896 {
897 case PDMAUDIORECSOURCE_MIC: return REC_MIC;
898 case PDMAUDIORECSOURCE_CD: return REC_CD;
899 case PDMAUDIORECSOURCE_VIDEO: return REC_VIDEO;
900 case PDMAUDIORECSOURCE_AUX: return REC_AUX;
901 case PDMAUDIORECSOURCE_LINE_IN: return REC_LINE_IN;
902 case PDMAUDIORECSOURCE_PHONE: return REC_PHONE;
903 default:
904 break;
905 }
906
907 LogFlowFunc(("Unknown audio recording source %d using MIC\n", rs));
908 return REC_MIC;
909}
910
911static void ichac97RecordSelect(PAC97STATE pThis, uint32_t val)
912{
913 uint8_t rs = val & REC_MASK;
914 uint8_t ls = (val >> 8) & REC_MASK;
915 PDMAUDIORECSOURCE ars = ichac97IndextoRecSource(rs);
916 PDMAUDIORECSOURCE als = ichac97IndextoRecSource(ls);
917 //AUD_set_record_source(&als, &ars);
918 rs = ichac97RecSourceToIndex(ars);
919 ls = ichac97RecSourceToIndex(als);
920 ichac97MixerSet(pThis, AC97_Record_Select, rs | (ls << 8));
921}
922
923static int ichac97MixerReset(PAC97STATE pThis)
924{
925 AssertPtrReturn(pThis, VERR_INVALID_PARAMETER);
926
927 LogFlowFuncEnter();
928
929 RT_ZERO(pThis->mixer_data);
930
931 /* Note: Make sure to reset all registers first before bailing out on error. */
932
933 ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
934 ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
935 ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
936
937 ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
938 ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
939 ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
940 ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
941 ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
942 ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
943 ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
944 ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
945
946 ichac97MixerSet(pThis, AC97_Extended_Audio_ID , 0x0809);
947 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
948 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80);
949 ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80);
950 ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80);
951 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80);
952 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80);
953
954 if (pThis->uCodecModel == Codec_AD1980)
955 {
956 /* Analog Devices 1980 (AD1980) */
957 ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
958 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
959 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
960 ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
961 }
962 else if (pThis->uCodecModel == Codec_AD1981B)
963 {
964 /* Analog Devices 1981B (AD1981B) */
965 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
966 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
967 }
968 else
969 {
970 /* Sigmatel 9700 (STAC9700) */
971 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
972 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
973 }
974 ichac97RecordSelect(pThis, 0);
975
976 ichac97MixerSetVolume(pThis, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME, 0x8000);
977 ichac97MixerSetVolume(pThis, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_PCM, 0x8808);
978 ichac97MixerSetVolume(pThis, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
979
980 return VINF_SUCCESS;
981}
982
983/**
984 * Writes data from the device to the host backends.
985 *
986 * @return IPRT status code.
987 * @param pThis
988 * @param pStrmSt
989 * @param cbMax
990 * @param pcbWritten
991 */
992static int ichac97WriteAudio(PAC97STATE pThis, PAC97STREAM pStrmSt, uint32_t cbMax, uint32_t *pcbWritten)
993{
994 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
995 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
996 AssertReturn(cbMax, VERR_INVALID_PARAMETER);
997 /* pcbWritten is optional. */
998
999 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
1000 PAC97BMREGS pRegs = &pStrmSt->Regs;
1001
1002 uint32_t addr = pRegs->bd.addr;
1003 uint32_t cbWrittenTotal = 0;
1004 uint32_t cbToRead;
1005
1006 uint32_t cbToWrite = RT_MIN((uint32_t)(pRegs->picb << 1), cbMax);
1007 if (!cbToWrite)
1008 {
1009 if (pcbWritten)
1010 *pcbWritten = 0;
1011 return VINF_EOF;
1012 }
1013
1014 int rc = VINF_SUCCESS;
1015
1016 LogFlowFunc(("pReg=%p, cbMax=%RU32, cbToWrite=%RU32\n", pRegs, cbMax, cbToWrite));
1017
1018 while (cbToWrite)
1019 {
1020 cbToRead = RT_MIN(cbToWrite, pThis->cbReadWriteBuf);
1021 PDMDevHlpPhysRead(pDevIns, addr, pThis->pvReadWriteBuf, cbToRead); /** @todo Check rc? */
1022
1023 uint32_t cbWritten;
1024
1025 /* Just multiplex the output to the connected backends.
1026 * No need to utilize the virtual mixer here (yet). */
1027 PAC97DRIVER pDrv;
1028 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
1029 {
1030 int rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
1031 pThis->pvReadWriteBuf, cbToRead, &cbWritten);
1032 LogFlowFunc(("\tLUN#%RU8: rc=%Rrc, cbWritten=%RU32\n", pDrv->uLUN, rc2, cbWritten));
1033 }
1034
1035 LogFlowFunc(("\tcbToRead=%RU32, cbToWrite=%RU32, cbLeft=%RU32\n",
1036 cbToRead, cbToWrite, cbToWrite - cbWrittenTotal));
1037
1038 Assert(cbToWrite >= cbToRead);
1039 cbToWrite -= cbToRead;
1040 addr += cbToRead;
1041 cbWrittenTotal += cbToRead;
1042 }
1043
1044 pRegs->bd.addr = addr;
1045
1046 if (RT_SUCCESS(rc))
1047 {
1048 if (!cbToWrite) /* All data written? */
1049 {
1050 if (cbToRead < 4)
1051 {
1052 AssertMsgFailed(("Unable to save last written sample, cbToRead < 4 (is %RU32)\n", cbToRead));
1053 pThis->last_samp = 0;
1054 }
1055 else
1056 pThis->last_samp = *(uint32_t *)&pThis->pvReadWriteBuf[cbToRead - 4];
1057 }
1058
1059 if (pcbWritten)
1060 *pcbWritten = cbWrittenTotal;
1061 }
1062
1063 LogFlowFunc(("cbWrittenTotal=%RU32, rc=%Rrc\n", cbWrittenTotal, rc));
1064 return rc;
1065}
1066
1067static void ichac97WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
1068{
1069 if (!(pThis->bup_flag & BUP_SET))
1070 {
1071 if (pThis->bup_flag & BUP_LAST)
1072 {
1073 unsigned int i;
1074 uint32_t *p = (uint32_t*)pThis->silence;
1075 for (i = 0; i < sizeof(pThis->silence) / 4; i++)
1076 *p++ = pThis->last_samp;
1077 }
1078 else
1079 RT_ZERO(pThis->silence);
1080
1081 pThis->bup_flag |= BUP_SET;
1082 }
1083
1084 while (cbElapsed)
1085 {
1086 uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
1087 uint32_t cbWrittenToStream;
1088 int rc2;
1089
1090 PAC97DRIVER pDrv;
1091 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
1092 {
1093 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
1094 {
1095 rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
1096 pThis->silence, cbToWrite, &cbWrittenToStream);
1097 if (RT_SUCCESS(rc2))
1098 {
1099 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
1100 LogFlowFunc(("\tLUN#%RU8: Warning: Only written %RU32 / %RU32 bytes, expect lags\n",
1101 pDrv->uLUN, cbWrittenToStream, cbToWrite));
1102 }
1103 }
1104 else /* Stream disabled, not fatal. */
1105 {
1106 cbWrittenToStream = 0;
1107 rc2 = VERR_NOT_AVAILABLE;
1108 /* Keep going. */
1109 }
1110 }
1111
1112 /* Always report all data as being written;
1113 * backends who were not able to catch up have to deal with it themselves. */
1114 Assert(cbElapsed >= cbToWrite);
1115 cbElapsed -= cbToWrite;
1116 }
1117}
1118
1119static int ichac97ReadAudio(PAC97STATE pThis, PAC97STREAM pStrmSt, uint32_t cbMax, uint32_t *pcbRead)
1120{
1121 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1122 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1123 AssertReturn(cbMax, VERR_INVALID_PARAMETER);
1124 /* pcbRead is optional. */
1125
1126 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
1127 PAC97BMREGS pRegs = &pStrmSt->Regs;
1128
1129 /* Select audio sink to process. */
1130 AssertMsg(pStrmSt->u8Strm != PO_INDEX, ("Can't read from output\n"));
1131 PAUDMIXSINK pSink = pStrmSt->u8Strm == MC_INDEX ? pThis->pSinkMicIn : pThis->pSinkLineIn;
1132 AssertPtr(pSink);
1133
1134 uint32_t cbRead = 0;
1135
1136 uint32_t cbMixBuf = cbMax;
1137 uint32_t cbToRead = RT_MIN((uint32_t)(pRegs->picb << 1), cbMixBuf);
1138
1139 if (!cbToRead)
1140 {
1141 if (pcbRead)
1142 *pcbRead = 0;
1143 return VINF_EOF;
1144 }
1145
1146 int rc;
1147
1148 uint8_t *pvMixBuf = (uint8_t *)RTMemAlloc(cbMixBuf);
1149 if (pvMixBuf)
1150 {
1151 rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pvMixBuf, cbToRead, &cbRead);
1152 if ( RT_SUCCESS(rc)
1153 && cbRead)
1154 {
1155 PDMDevHlpPCIPhysWrite(pDevIns, pRegs->bd.addr, pvMixBuf, cbRead);
1156 pRegs->bd.addr += cbRead;
1157 }
1158
1159 RTMemFree(pvMixBuf);
1160 }
1161 else
1162 rc = VERR_NO_MEMORY;
1163
1164 if (RT_SUCCESS(rc))
1165 {
1166 if (pcbRead)
1167 *pcbRead = cbRead;
1168 }
1169
1170 return rc;
1171}
1172
1173#ifndef VBOX_WITH_AUDIO_CALLBACKS
1174
1175static DECLCALLBACK(void) ichac97Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1176{
1177 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
1178 AssertPtrReturnVoid(pThis);
1179
1180 STAM_PROFILE_START(&pThis->StatTimer, a);
1181
1182 int rc = VINF_SUCCESS;
1183
1184 uint32_t cbInMax = 0;
1185 uint32_t cbOutMin = UINT32_MAX;
1186
1187 PAC97DRIVER pDrv;
1188
1189 uint32_t cbIn, cbOut;
1190
1191 uint64_t uTicksNow = PDMDevHlpTMTimeVirtGet(pDevIns);
1192 uint64_t uTicksElapsed = uTicksNow - pThis->uTimerTS;
1193 uint64_t uTicksPerSec = PDMDevHlpTMTimeVirtGetFreq(pDevIns);
1194
1195 pThis->uTimerTS = uTicksNow;
1196
1197 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
1198 {
1199 cbIn = cbOut = 0;
1200 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
1201 &cbIn, &cbOut, NULL /* cSamplesLive */);
1202 if (RT_SUCCESS(rc))
1203 rc = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, NULL /* cSamplesPlayed */);
1204
1205#ifdef DEBUG_TIMER
1206 LogFlowFunc(("LUN#%RU8: rc=%Rrc, cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, rc, cbIn, cbOut));
1207#endif
1208 const bool fIsActiveOut = pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut);
1209
1210 /* If we there was an error handling (available) output or there simply is no output available,
1211 * then calculate the minimum data rate which must be processed by the device emulation in order
1212 * to function correctly.
1213 *
1214 * This is not the optimal solution, but as we have to deal with this on a timer-based approach
1215 * (until we have the audio callbacks) we need to have device' DMA engines running. */
1216 if ( RT_FAILURE(rc)
1217 || !fIsActiveOut)
1218 {
1219 uint32_t cSamplesMin = (int)((2 * uTicksElapsed * pDrv->Out.pStrmOut->Props.uHz + uTicksPerSec) / uTicksPerSec / 2);
1220 uint32_t cbSamplesMin = AUDIOMIXBUF_S2B(&pDrv->Out.pStrmOut->MixBuf, cSamplesMin);
1221
1222#ifdef DEBUG_TIMER
1223 LogFlowFunc(("\trc=%Rrc, cSamplesMin=%RU32, cbSamplesMin=%RU32\n", rc, cSamplesMin, cbSamplesMin));
1224#endif
1225 cbOut = RT_MAX(cbOut, cbSamplesMin);
1226 }
1227
1228 cbOutMin = RT_MIN(cbOutMin, cbOut);
1229 cbInMax = RT_MAX(cbInMax, cbIn);
1230 }
1231
1232#ifdef DEBUG_TIMER
1233 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
1234#endif
1235
1236 if (cbOutMin == UINT32_MAX)
1237 cbOutMin = 0;
1238
1239 /*
1240 * Playback.
1241 */
1242 if (cbOutMin)
1243 {
1244 Assert(cbOutMin != UINT32_MAX);
1245 ichac97TransferAudio(pThis, PO_INDEX, cbOutMin); /** @todo Add rc! */
1246 }
1247
1248 /*
1249 * Recording.
1250 */
1251 if (cbInMax)
1252 ichac97TransferAudio(pThis, PI_INDEX, cbInMax); /** @todo Add rc! */
1253
1254 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTimerTicks);
1255
1256 STAM_PROFILE_STOP(&pThis->StatTimer, a);
1257}
1258
1259#endif
1260
1261static int ichac97TransferAudio(PAC97STATE pThis, AC97SOUNDSOURCE enmSrc, uint32_t cbElapsed)
1262{
1263 LogFlowFunc(("pThis=%p, enmSrc=%RU32, cbElapsed=%RU32\n", pThis, enmSrc, cbElapsed));
1264
1265 PAC97STREAM pStrmSt;
1266 switch (enmSrc)
1267 {
1268 case PI_INDEX: pStrmSt = &pThis->StrmStLineIn; break;
1269 case MC_INDEX: pStrmSt = &pThis->StrmStMicIn; break;
1270 case PO_INDEX: pStrmSt = &pThis->StrmStOut; break;
1271 default:
1272 {
1273 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
1274 return VERR_NOT_SUPPORTED;
1275 }
1276 }
1277
1278 PAC97BMREGS pRegs = &pStrmSt->Regs;
1279
1280 if (pRegs->sr & SR_DCH) /* Controller halted? */
1281 {
1282 if (pRegs->cr & CR_RPBM)
1283 {
1284 switch (enmSrc)
1285 {
1286 case PO_INDEX:
1287 ichac97WriteBUP(pThis, cbElapsed);
1288 break;
1289
1290 default:
1291 break;
1292 }
1293 }
1294
1295 return VINF_SUCCESS;
1296 }
1297
1298 int rc = VINF_SUCCESS;
1299 uint32_t cbWrittenTotal = 0;
1300
1301 while (cbElapsed >> 1)
1302 {
1303 if (!pRegs->bd_valid)
1304 {
1305 LogFlowFunc(("Invalid buffer descriptor, fetching next one ...\n"));
1306 ichac97StreamFetchBDLE(pThis, pStrmSt);
1307 }
1308
1309 if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
1310 {
1311 LogFlowFunc(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
1312 pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
1313 if (pRegs->civ == pRegs->lvi)
1314 {
1315 pRegs->sr |= SR_DCH; /* CELV? */
1316 pThis->bup_flag = 0;
1317
1318 rc = VINF_EOF;
1319 break;
1320 }
1321
1322 pRegs->sr &= ~SR_CELV;
1323 pRegs->civ = pRegs->piv;
1324 pRegs->piv = (pRegs->piv + 1) % 32;
1325
1326 ichac97StreamFetchBDLE(pThis, pStrmSt);
1327 continue;
1328 }
1329
1330 uint32_t cbTransferred;
1331 switch (enmSrc)
1332 {
1333 case PO_INDEX:
1334 {
1335 rc = ichac97WriteAudio(pThis, pStrmSt, cbElapsed, &cbTransferred);
1336 if ( RT_SUCCESS(rc)
1337 && cbTransferred)
1338 {
1339 cbWrittenTotal += cbTransferred;
1340 Assert(cbElapsed >= cbTransferred);
1341 cbElapsed -= cbTransferred;
1342 Assert((cbTransferred & 1) == 0); /* Else the following shift won't work */
1343 pRegs->picb -= (cbTransferred >> 1);
1344 }
1345 break;
1346 }
1347
1348 case PI_INDEX:
1349 case MC_INDEX:
1350 {
1351 rc = ichac97ReadAudio(pThis, pStrmSt, cbElapsed, &cbTransferred);
1352 if ( RT_SUCCESS(rc)
1353 && cbTransferred)
1354 {
1355 Assert(cbElapsed >= cbTransferred);
1356 cbElapsed -= cbTransferred;
1357 Assert((cbTransferred & 1) == 0); /* Else the following shift won't work */
1358 pRegs->picb -= (cbTransferred >> 1);
1359 }
1360 break;
1361 }
1362
1363 default:
1364 AssertMsgFailed(("Source %RU32 not supported\n", enmSrc));
1365 rc = VERR_NOT_SUPPORTED;
1366 break;
1367 }
1368
1369 LogFlowFunc(("pReg->picb=%#x, cbWrittenTotal=%RU32\n", pRegs->picb, cbWrittenTotal));
1370
1371 if (!pRegs->picb)
1372 {
1373 uint32_t new_sr = pRegs->sr & ~SR_CELV;
1374
1375 if (pRegs->bd.ctl_len & BD_IOC)
1376 {
1377 new_sr |= SR_BCIS;
1378 }
1379
1380 if (pRegs->civ == pRegs->lvi)
1381 {
1382 LogFlowFunc(("Underrun civ (%RU8) == lvi (%RU8)\n", pRegs->civ, pRegs->lvi));
1383 new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
1384 pThis->bup_flag = (pRegs->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1385
1386 rc = VINF_EOF;
1387 }
1388 else
1389 {
1390 pRegs->civ = pRegs->piv;
1391 pRegs->piv = (pRegs->piv + 1) % 32;
1392 ichac97StreamFetchBDLE(pThis, pStrmSt);
1393 }
1394
1395 ichac97StreamUpdateStatus(pThis, pStrmSt, new_sr);
1396 }
1397
1398 if ( RT_FAILURE(rc)
1399 || rc == VINF_EOF) /* All data processed? */
1400 {
1401 break;
1402 }
1403 }
1404
1405 LogFlowFuncLeaveRC(rc);
1406 return rc;
1407}
1408
1409/**
1410 * @callback_method_impl{FNIOMIOPORTIN}
1411 */
1412static DECLCALLBACK(int) ichac97IOPortNABMRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
1413 uint32_t *pu32Val, unsigned cbVal)
1414{
1415 PAC97STATE pThis = (PAC97STATE)pvUser;
1416
1417 /* Get the index of the NABMBAR port. */
1418 const uint32_t uPortIdx = Port - pThis->IOPortBase[1];
1419
1420 PAC97STREAM pStrmSt = ichac97GetStreamFromID(pThis, AC97_PORT2IDX(uPortIdx));
1421 PAC97BMREGS pRegs = pStrmSt ? &pStrmSt->Regs : NULL;
1422
1423 switch (cbVal)
1424 {
1425 case 1:
1426 {
1427 switch (uPortIdx)
1428 {
1429 case CAS:
1430 /* Codec Access Semaphore Register */
1431 LogFlowFunc(("CAS %d\n", pThis->cas));
1432 *pu32Val = pThis->cas;
1433 pThis->cas = 1;
1434 break;
1435 case PI_CIV:
1436 case PO_CIV:
1437 case MC_CIV:
1438 /* Current Index Value Register */
1439 *pu32Val = pRegs->civ;
1440 LogFlowFunc(("CIV[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1441 break;
1442 case PI_LVI:
1443 case PO_LVI:
1444 case MC_LVI:
1445 /* Last Valid Index Register */
1446 *pu32Val = pRegs->lvi;
1447 LogFlowFunc(("LVI[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1448 break;
1449 case PI_PIV:
1450 case PO_PIV:
1451 case MC_PIV:
1452 /* Prefetched Index Value Register */
1453 *pu32Val = pRegs->piv;
1454 LogFlowFunc(("PIV[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1455 break;
1456 case PI_CR:
1457 case PO_CR:
1458 case MC_CR:
1459 /* Control Register */
1460 *pu32Val = pRegs->cr;
1461 LogFlowFunc(("CR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1462 break;
1463 case PI_SR:
1464 case PO_SR:
1465 case MC_SR:
1466 /* Status Register (lower part) */
1467 *pu32Val = pRegs->sr & 0xff; /** @todo r=andy Use RT_LO_U8. */
1468 LogFlowFunc(("SRb[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1469 break;
1470 default:
1471 *pu32Val = UINT32_MAX;
1472 LogFlowFunc(("U nabm readb %#x -> %#x\n", Port, *pu32Val));
1473 break;
1474 }
1475 break;
1476 }
1477
1478 case 2:
1479 {
1480 switch (uPortIdx)
1481 {
1482 case PI_SR:
1483 case PO_SR:
1484 case MC_SR:
1485 /* Status Register */
1486 *pu32Val = pRegs->sr;
1487 LogFlowFunc(("SR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1488 break;
1489 case PI_PICB:
1490 case PO_PICB:
1491 case MC_PICB:
1492 /* Position in Current Buffer Register */
1493 *pu32Val = pRegs->picb;
1494 LogFlowFunc(("PICB[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1495 break;
1496 default:
1497 *pu32Val = UINT32_MAX;
1498 LogFlowFunc(("U nabm readw %#x -> %#x\n", Port, *pu32Val));
1499 break;
1500 }
1501 break;
1502 }
1503
1504 case 4:
1505 {
1506 switch (uPortIdx)
1507 {
1508 case PI_BDBAR:
1509 case PO_BDBAR:
1510 case MC_BDBAR:
1511 /* Buffer Descriptor Base Address Register */
1512 *pu32Val = pRegs->bdbar;
1513 LogFlowFunc(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1514 break;
1515 case PI_CIV:
1516 case PO_CIV:
1517 case MC_CIV:
1518 /* 32-bit access: Current Index Value Register +
1519 * Last Valid Index Register +
1520 * Status Register */
1521 *pu32Val = pRegs->civ | (pRegs->lvi << 8) | (pRegs->sr << 16); /** @todo r=andy Use RT_MAKE_U32_FROM_U8. */
1522 LogFlowFunc(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
1523 AC97_PORT2IDX(uPortIdx), pRegs->civ, pRegs->lvi, pRegs->sr));
1524 break;
1525 case PI_PICB:
1526 case PO_PICB:
1527 case MC_PICB:
1528 /* 32-bit access: Position in Current Buffer Register +
1529 * Prefetched Index Value Register +
1530 * Control Register */
1531 *pu32Val = pRegs->picb | (pRegs->piv << 16) | (pRegs->cr << 24); /** @todo r=andy Use RT_MAKE_U32_FROM_U8. */
1532 LogFlowFunc(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
1533 AC97_PORT2IDX(uPortIdx), *pu32Val, pRegs->picb, pRegs->piv, pRegs->cr));
1534 break;
1535 case GLOB_CNT:
1536 /* Global Control */
1537 *pu32Val = pThis->glob_cnt;
1538 LogFlowFunc(("glob_cnt -> %#x\n", *pu32Val));
1539 break;
1540 case GLOB_STA:
1541 /* Global Status */
1542 *pu32Val = pThis->glob_sta | GS_S0CR;
1543 LogFlowFunc(("glob_sta -> %#x\n", *pu32Val));
1544 break;
1545 default:
1546 *pu32Val = UINT32_MAX;
1547 LogFlowFunc(("U nabm readl %#x -> %#x\n", Port, *pu32Val));
1548 break;
1549 }
1550 break;
1551 }
1552
1553 default:
1554 return VERR_IOM_IOPORT_UNUSED;
1555 }
1556 return VINF_SUCCESS;
1557}
1558
1559/**
1560 * @callback_method_impl{FNIOMIOPORTOUT}
1561 */
1562static DECLCALLBACK(int) ichac97IOPortNABMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
1563 uint32_t u32Val, unsigned cbVal)
1564{
1565 PAC97STATE pThis = (PAC97STATE)pvUser;
1566
1567 /* Get the index of the NABMBAR register. */
1568 const uint32_t uPortIdx = Port - pThis->IOPortBase[1];
1569
1570 PAC97STREAM pStrmSt = ichac97GetStreamFromID(pThis, AC97_PORT2IDX(uPortIdx));
1571 PAC97BMREGS pRegs = pStrmSt ? &pStrmSt->Regs : NULL;
1572
1573 switch (cbVal)
1574 {
1575 case 1:
1576 {
1577 switch (uPortIdx)
1578 {
1579 case PI_LVI:
1580 case PO_LVI:
1581 case MC_LVI:
1582 /* Last Valid Index */
1583 if ((pRegs->cr & CR_RPBM) && (pRegs->sr & SR_DCH))
1584 {
1585 pRegs->sr &= ~(SR_DCH | SR_CELV);
1586 pRegs->civ = pRegs->piv;
1587 pRegs->piv = (pRegs->piv + 1) % 32;
1588
1589 ichac97StreamFetchBDLE(pThis, pStrmSt);
1590 }
1591 pRegs->lvi = u32Val % 32;
1592 LogFlowFunc(("LVI[%d] <- %#x\n", AC97_PORT2IDX(uPortIdx), u32Val));
1593 break;
1594 case PI_CR:
1595 case PO_CR:
1596 case MC_CR:
1597 {
1598 /* Control Register */
1599 if (u32Val & CR_RR) /* Busmaster reset */
1600 {
1601 ichac97StreamResetBMRegs(pThis, pStrmSt);
1602 }
1603 else
1604 {
1605 pRegs->cr = u32Val & CR_VALID_MASK;
1606 if (!(pRegs->cr & CR_RPBM))
1607 {
1608 ichac97StreamSetActive(pThis, pStrmSt, false /* fActive */);
1609 pRegs->sr |= SR_DCH;
1610 }
1611 else
1612 {
1613 pRegs->civ = pRegs->piv;
1614 pRegs->piv = (pRegs->piv + 1) % 32;
1615
1616 ichac97StreamFetchBDLE(pThis, pStrmSt);
1617
1618 pRegs->sr &= ~SR_DCH;
1619 ichac97StreamSetActive(pThis, pStrmSt, true /* fActive */);
1620 }
1621 }
1622 LogFlowFunc(("CR[%d] <- %#x (cr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->cr));
1623 break;
1624 }
1625 case PI_SR:
1626 case PO_SR:
1627 case MC_SR:
1628 /* Status Register */
1629 pRegs->sr |= u32Val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
1630 ichac97StreamUpdateStatus(pThis, pStrmSt, pRegs->sr & ~(u32Val & SR_WCLEAR_MASK));
1631 LogFlowFunc(("SR[%d] <- %#x (sr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->sr));
1632 break;
1633 default:
1634 LogFlowFunc(("U nabm writeb %#x <- %#x\n", Port, u32Val));
1635 break;
1636 }
1637 break;
1638 }
1639
1640 case 2:
1641 {
1642 switch (uPortIdx)
1643 {
1644 case PI_SR:
1645 case PO_SR:
1646 case MC_SR:
1647 /* Status Register */
1648 pRegs->sr |= u32Val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
1649 ichac97StreamUpdateStatus(pThis, pStrmSt, pRegs->sr & ~(u32Val & SR_WCLEAR_MASK));
1650 LogFlowFunc(("SR[%d] <- %#x (sr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->sr));
1651 break;
1652 default:
1653 LogFlowFunc(("U nabm writew %#x <- %#x\n", Port, u32Val));
1654 break;
1655 }
1656 break;
1657 }
1658
1659 case 4:
1660 {
1661 switch (uPortIdx)
1662 {
1663 case PI_BDBAR:
1664 case PO_BDBAR:
1665 case MC_BDBAR:
1666 /* Buffer Descriptor list Base Address Register */
1667 pRegs->bdbar = u32Val & ~3;
1668 LogFlowFunc(("BDBAR[%d] <- %#x (bdbar %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->bdbar));
1669 break;
1670 case GLOB_CNT:
1671 /* Global Control */
1672 if (u32Val & GC_WR)
1673 ichac97WarmReset(pThis);
1674 if (u32Val & GC_CR)
1675 ichac97ColdReset(pThis);
1676 if (!(u32Val & (GC_WR | GC_CR)))
1677 pThis->glob_cnt = u32Val & GC_VALID_MASK;
1678 LogFlowFunc(("glob_cnt <- %#x (glob_cnt %#x)\n", u32Val, pThis->glob_cnt));
1679 break;
1680 case GLOB_STA:
1681 /* Global Status */
1682 pThis->glob_sta &= ~(u32Val & GS_WCLEAR_MASK);
1683 pThis->glob_sta |= (u32Val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
1684 LogFlowFunc(("glob_sta <- %#x (glob_sta %#x)\n", u32Val, pThis->glob_sta));
1685 break;
1686 default:
1687 LogFlowFunc(("U nabm writel %#x <- %#x\n", Port, u32Val));
1688 break;
1689 }
1690 break;
1691 }
1692
1693 default:
1694 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cbVal, u32Val));
1695 break;
1696 }
1697 return VINF_SUCCESS;
1698}
1699
1700/**
1701 * @callback_method_impl{FNIOMIOPORTIN}
1702 */
1703static DECLCALLBACK(int) ichac97IOPortNAMRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32Val, unsigned cbVal)
1704{
1705 PAC97STATE pThis = (PAC97STATE)pvUser;
1706
1707 switch (cbVal)
1708 {
1709 case 1:
1710 {
1711 LogFlowFunc(("U nam readb %#x\n", Port));
1712 pThis->cas = 0;
1713 *pu32Val = UINT32_MAX;
1714 break;
1715 }
1716
1717 case 2:
1718 {
1719 uint32_t index = Port - pThis->IOPortBase[0];
1720 *pu32Val = UINT32_MAX;
1721 pThis->cas = 0;
1722 switch (index)
1723 {
1724 default:
1725 *pu32Val = ichac97MixerGet(pThis, index);
1726 LogFlowFunc(("nam readw %#x -> %#x\n", Port, *pu32Val));
1727 break;
1728 }
1729 break;
1730 }
1731
1732 case 4:
1733 {
1734 LogFlowFunc(("U nam readl %#x\n", Port));
1735 pThis->cas = 0;
1736 *pu32Val = UINT32_MAX;
1737 break;
1738 }
1739
1740 default:
1741 return VERR_IOM_IOPORT_UNUSED;
1742 }
1743 return VINF_SUCCESS;
1744}
1745
1746/**
1747 * @callback_method_impl{FNIOMIOPORTOUT}
1748 */
1749static DECLCALLBACK(int) ichac97IOPortNAMWrite(PPDMDEVINS pDevIns,
1750 void *pvUser, RTIOPORT Port, uint32_t u32Val, unsigned cbVal)
1751{
1752 PAC97STATE pThis = (PAC97STATE)pvUser;
1753
1754 switch (cbVal)
1755 {
1756 case 1:
1757 {
1758 LogFlowFunc(("U nam writeb %#x <- %#x\n", Port, u32Val));
1759 pThis->cas = 0;
1760 break;
1761 }
1762
1763 case 2:
1764 {
1765 uint32_t index = Port - pThis->IOPortBase[0];
1766 pThis->cas = 0;
1767 switch (index)
1768 {
1769 case AC97_Reset:
1770 ichac97Reset(pThis->CTX_SUFF(pDevIns));
1771 break;
1772 case AC97_Powerdown_Ctrl_Stat:
1773 u32Val &= ~0xf;
1774 u32Val |= ichac97MixerGet(pThis, index) & 0xf;
1775 ichac97MixerSet(pThis, index, u32Val);
1776 break;
1777 case AC97_Master_Volume_Mute:
1778 if (pThis->uCodecModel == Codec_AD1980)
1779 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AD_MISC_LOSEL)
1780 break; /* Register controls surround (rear), do nothing. */
1781 ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_VOLUME, u32Val);
1782 break;
1783 case AC97_Headphone_Volume_Mute:
1784 if (pThis->uCodecModel == Codec_AD1980)
1785 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AD_MISC_HPSEL)
1786 /* Register controls PCM (front) outputs. */
1787 ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_VOLUME, u32Val);
1788 break;
1789 case AC97_PCM_Out_Volume_Mute:
1790 ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_PCM, u32Val);
1791 break;
1792 case AC97_Line_In_Volume_Mute:
1793 ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_LINE_IN, u32Val);
1794 break;
1795 case AC97_Record_Select:
1796 ichac97RecordSelect(pThis, u32Val);
1797 break;
1798 case AC97_Vendor_ID1:
1799 case AC97_Vendor_ID2:
1800 LogFlowFunc(("Attempt to write vendor ID to %#x\n", u32Val));
1801 break;
1802 case AC97_Extended_Audio_ID:
1803 LogFlowFunc(("Attempt to write extended audio ID to %#x\n", u32Val));
1804 break;
1805 case AC97_Extended_Audio_Ctrl_Stat:
1806 if (!(u32Val & EACS_VRA))
1807 {
1808 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 48000);
1809 ichac97StreamReInit(pThis, &pThis->StrmStOut);
1810
1811 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 48000);
1812 ichac97StreamReInit(pThis, &pThis->StrmStLineIn);
1813 }
1814 if (!(u32Val & EACS_VRM))
1815 {
1816 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 48000);
1817 ichac97StreamReInit(pThis, &pThis->StrmStMicIn);
1818 }
1819 LogFlowFunc(("Setting extended audio control to %#x\n", u32Val));
1820 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32Val);
1821 break;
1822 case AC97_PCM_Front_DAC_Rate:
1823 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)
1824 {
1825 ichac97MixerSet(pThis, index, u32Val);
1826 LogFlowFunc(("Set front DAC rate to %RU32\n", u32Val));
1827 ichac97StreamReInit(pThis, &pThis->StrmStOut);
1828 }
1829 else
1830 LogFlowFunc(("Attempt to set front DAC rate to %RU32, but VRA is not set\n", u32Val));
1831 break;
1832 case AC97_MIC_ADC_Rate:
1833 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM)
1834 {
1835 ichac97MixerSet(pThis, index, u32Val);
1836 LogFlowFunc(("Set MIC ADC rate to %RU32\n", u32Val));
1837 ichac97StreamReInit(pThis, &pThis->StrmStMicIn);
1838 }
1839 else
1840 LogFlowFunc(("Attempt to set MIC ADC rate to %RU32, but VRM is not set\n", u32Val));
1841 break;
1842 case AC97_PCM_LR_ADC_Rate:
1843 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)
1844 {
1845 ichac97MixerSet(pThis, index, u32Val);
1846 LogFlowFunc(("Set front LR ADC rate to %RU32\n", u32Val));
1847 ichac97StreamReInit(pThis, &pThis->StrmStLineIn);
1848 }
1849 else
1850 LogFlowFunc(("Attempt to set LR ADC rate to %RU32, but VRA is not set\n", u32Val));
1851 break;
1852 default:
1853 LogFlowFunc(("U nam writew %#x <- %#x\n", Port, u32Val));
1854 ichac97MixerSet(pThis, index, u32Val);
1855 break;
1856 }
1857 break;
1858 }
1859
1860 case 4:
1861 {
1862 LogFlowFunc(("U nam writel %#x <- %#x\n", Port, u32Val));
1863 pThis->cas = 0;
1864 break;
1865 }
1866
1867 default:
1868 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cbVal, u32Val));
1869 break;
1870 }
1871
1872 return VINF_SUCCESS;
1873}
1874
1875
1876/**
1877 * @callback_method_impl{FNPCIIOREGIONMAP}
1878 */
1879static DECLCALLBACK(int) ichac97IOPortMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
1880 PCIADDRESSSPACE enmType)
1881{
1882 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1883 PAC97STATE pThis = RT_FROM_MEMBER(pPciDev, AC97STATE, PciDev);
1884 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1885
1886 Assert(enmType == PCI_ADDRESS_SPACE_IO);
1887 Assert(cb >= 0x20);
1888
1889 if (iRegion < 0 || iRegion > 1) /* We support 2 regions max. at the moment. */
1890 return VERR_INVALID_PARAMETER;
1891
1892 int rc;
1893 if (iRegion == 0)
1894 rc = PDMDevHlpIOPortRegister(pDevIns, Port, 256, pThis,
1895 ichac97IOPortNAMWrite, ichac97IOPortNAMRead,
1896 NULL, NULL, "ICHAC97 NAM");
1897 else
1898 rc = PDMDevHlpIOPortRegister(pDevIns, Port, 64, pThis,
1899 ichac97IOPortNABMWrite, ichac97IOPortNABMRead,
1900 NULL, NULL, "ICHAC97 NABM");
1901 if (RT_FAILURE(rc))
1902 return rc;
1903
1904 pThis->IOPortBase[iRegion] = Port;
1905 return VINF_SUCCESS;
1906}
1907
1908DECLINLINE(PAC97STREAM) ichac97GetStreamFromID(PAC97STATE pThis, uint32_t uID)
1909{
1910 switch (uID)
1911 {
1912 case PI_INDEX: return &pThis->StrmStLineIn;
1913 case MC_INDEX: return &pThis->StrmStMicIn;
1914 case PO_INDEX: return &pThis->StrmStOut;
1915 default: break;
1916 }
1917
1918 return NULL;
1919}
1920
1921#ifdef IN_RING3
1922static int ichac97SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStrmSt)
1923{
1924 PAC97BMREGS pRegs = &pStrmSt->Regs;
1925
1926 SSMR3PutU32(pSSM, pRegs->bdbar);
1927 SSMR3PutU8( pSSM, pRegs->civ);
1928 SSMR3PutU8( pSSM, pRegs->lvi);
1929 SSMR3PutU16(pSSM, pRegs->sr);
1930 SSMR3PutU16(pSSM, pRegs->picb);
1931 SSMR3PutU8( pSSM, pRegs->piv);
1932 SSMR3PutU8( pSSM, pRegs->cr);
1933 SSMR3PutS32(pSSM, pRegs->bd_valid);
1934 SSMR3PutU32(pSSM, pRegs->bd.addr);
1935 SSMR3PutU32(pSSM, pRegs->bd.ctl_len);
1936
1937 return VINF_SUCCESS;
1938}
1939
1940/**
1941 * @callback_method_impl{FNSSMDEVSAVEEXEC}
1942 */
1943static DECLCALLBACK(int) ichac97SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1944{
1945 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
1946
1947 SSMR3PutU32(pSSM, pThis->glob_cnt);
1948 SSMR3PutU32(pSSM, pThis->glob_sta);
1949 SSMR3PutU32(pSSM, pThis->cas);
1950
1951 /** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
1952 /* Note: The order the streams are saved here is critical, so don't touch. */
1953 int rc2 = ichac97SaveStream(pDevIns, pSSM, &pThis->StrmStLineIn);
1954 AssertRC(rc2);
1955 rc2 = ichac97SaveStream(pDevIns, pSSM, &pThis->StrmStOut);
1956 AssertRC(rc2);
1957 rc2 = ichac97SaveStream(pDevIns, pSSM, &pThis->StrmStMicIn);
1958 AssertRC(rc2);
1959
1960 SSMR3PutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
1961
1962 uint8_t active[LAST_INDEX];
1963
1964 PAC97DRIVER pDrv;
1965 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
1966 {
1967 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
1968 AssertPtr(pCon);
1969 active[PI_INDEX] = pCon->pfnIsActiveIn (pCon, pDrv->LineIn.pStrmIn) ? 1 : 0;
1970 active[PO_INDEX] = pCon->pfnIsActiveOut(pCon, pDrv->Out.pStrmOut) ? 1 : 0;
1971 active[MC_INDEX] = pCon->pfnIsActiveIn (pCon, pDrv->MicIn.pStrmIn) ? 1 : 0;
1972 }
1973
1974 SSMR3PutMem(pSSM, active, sizeof(active));
1975
1976 return VINF_SUCCESS;
1977}
1978
1979static int ichac97LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStrmSt)
1980{
1981 PAC97BMREGS pRegs = &pStrmSt->Regs;
1982
1983 SSMR3GetU32(pSSM, &pRegs->bdbar);
1984 SSMR3GetU8( pSSM, &pRegs->civ);
1985 SSMR3GetU8( pSSM, &pRegs->lvi);
1986 SSMR3GetU16(pSSM, &pRegs->sr);
1987 SSMR3GetU16(pSSM, &pRegs->picb);
1988 SSMR3GetU8( pSSM, &pRegs->piv);
1989 SSMR3GetU8( pSSM, &pRegs->cr);
1990 SSMR3GetS32(pSSM, &pRegs->bd_valid);
1991 SSMR3GetU32(pSSM, &pRegs->bd.addr);
1992 SSMR3GetU32(pSSM, &pRegs->bd.ctl_len);
1993
1994 return VINF_SUCCESS;
1995}
1996
1997/**
1998 * @callback_method_impl{FNSSMDEVLOADEXEC}
1999 */
2000static DECLCALLBACK(int) ichac97LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2001{
2002 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2003
2004 AssertMsgReturn (uVersion == AC97_SSM_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
2005 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2006
2007 SSMR3GetU32(pSSM, &pThis->glob_cnt);
2008 SSMR3GetU32(pSSM, &pThis->glob_sta);
2009 SSMR3GetU32(pSSM, &pThis->cas);
2010
2011 /** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
2012 /* Note: The order the streams are loaded here is critical, so don't touch. */
2013 int rc2 = ichac97LoadStream(pDevIns, pSSM, &pThis->StrmStLineIn);
2014 AssertRC(rc2);
2015 rc2 = ichac97LoadStream(pDevIns, pSSM, &pThis->StrmStOut);
2016 AssertRC(rc2);
2017 rc2 = ichac97LoadStream(pDevIns, pSSM, &pThis->StrmStMicIn);
2018 AssertRC(rc2);
2019
2020 SSMR3GetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
2021
2022 /** @todo r=andy Stream IDs are hardcoded to certain streams. */
2023 uint8_t uaStrmsActive[LAST_INDEX];
2024 SSMR3GetMem(pSSM, uaStrmsActive, sizeof(uaStrmsActive));
2025
2026 ichac97RecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
2027# define V_(a, b) ichac97MixerSetVolume(pThis, a, b, ichac97MixerGet(pThis, a))
2028 V_(AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME);
2029 V_(AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_PCM);
2030 V_(AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN);
2031# undef V_
2032 if (pThis->uCodecModel == Codec_AD1980)
2033 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AD_MISC_HPSEL)
2034 ichac97MixerSetVolume(pThis, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME,
2035 ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
2036
2037 int rc;
2038 rc = ichac97StreamInit(pThis, &pThis->StrmStLineIn, PI_INDEX);
2039 AssertRC(rc);
2040 rc = ichac97StreamInit(pThis, &pThis->StrmStMicIn, MC_INDEX);
2041 AssertRC(rc);
2042 rc = ichac97StreamInit(pThis, &pThis->StrmStOut, PO_INDEX);
2043 AssertRC(rc);
2044
2045 /** @todo r=andy Stream IDs are hardcoded to certain streams. */
2046 rc = ichac97StreamSetActive(pThis, &pThis->StrmStLineIn, RT_BOOL(uaStrmsActive[PI_INDEX]));
2047 AssertRC(rc);
2048 rc = ichac97StreamSetActive(pThis, &pThis->StrmStMicIn, RT_BOOL(uaStrmsActive[MC_INDEX]));
2049 AssertRC(rc);
2050 rc = ichac97StreamSetActive(pThis, &pThis->StrmStOut, RT_BOOL(uaStrmsActive[PO_INDEX]));
2051 AssertRC(rc);
2052
2053 pThis->bup_flag = 0;
2054 pThis->last_samp = 0;
2055
2056 return VINF_SUCCESS;
2057}
2058
2059
2060/**
2061 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2062 */
2063static DECLCALLBACK(void *) ichac97QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
2064{
2065 PAC97STATE pThis = RT_FROM_MEMBER(pInterface, AC97STATE, IBase);
2066 Assert(&pThis->IBase == pInterface);
2067
2068 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2069 return NULL;
2070}
2071
2072
2073/**
2074 * @interface_method_impl{PDMDEVREG,pfnReset}
2075 *
2076 * @remarks The original sources didn't install a reset handler, but it seems to
2077 * make sense to me so we'll do it.
2078 */
2079static DECLCALLBACK(void) ichac97Reset(PPDMDEVINS pDevIns)
2080{
2081 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2082
2083 LogFlowFuncEnter();
2084
2085 /*
2086 * Reset the device state (will need pDrv later).
2087 */
2088 ichac97StreamResetBMRegs(pThis, &pThis->StrmStLineIn);
2089 ichac97StreamResetBMRegs(pThis, &pThis->StrmStMicIn);
2090 ichac97StreamResetBMRegs(pThis, &pThis->StrmStOut);
2091
2092 /*
2093 * Reset the mixer too. The Windows XP driver seems to rely on
2094 * this. At least it wants to read the vendor id before it resets
2095 * the codec manually.
2096 */
2097 ichac97MixerReset(pThis);
2098
2099 /*
2100 * Stop any audio currently playing.
2101 */
2102 PAC97DRIVER pDrv;
2103 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
2104 {
2105 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
2106 /* Ignore rc. */
2107 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
2108 /* Ditto. */
2109 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
2110 /* Ditto. */
2111 }
2112
2113 /*
2114 * Reset all streams.
2115 */
2116 ichac97StreamReset(pThis, &pThis->StrmStLineIn);
2117 ichac97StreamReset(pThis, &pThis->StrmStMicIn);
2118 ichac97StreamReset(pThis, &pThis->StrmStOut);
2119
2120 LogRel(("AC97: Reset\n"));
2121}
2122
2123
2124/**
2125 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2126 */
2127static DECLCALLBACK(int) ichac97Destruct(PPDMDEVINS pDevIns)
2128{
2129 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2130
2131 LogFlowFuncEnter();
2132
2133 PAC97DRIVER pDrv;
2134 while (!RTListIsEmpty(&pThis->lstDrv))
2135 {
2136 pDrv = RTListGetFirst(&pThis->lstDrv, AC97DRIVER, Node);
2137
2138 RTListNodeRemove(&pDrv->Node);
2139 RTMemFree(pDrv);
2140 }
2141
2142 if (pThis->pMixer)
2143 {
2144 AudioMixerDestroy(pThis->pMixer);
2145 pThis->pMixer = NULL;
2146 }
2147
2148 if (pThis->pvReadWriteBuf)
2149 {
2150 RTMemFree(pThis->pvReadWriteBuf);
2151 pThis->pvReadWriteBuf = NULL;
2152 pThis->cbReadWriteBuf = 0;
2153 }
2154
2155 LogFlowFuncLeave();
2156 return VINF_SUCCESS;
2157}
2158
2159
2160/**
2161 * Attach command.
2162 *
2163 * This is called to let the device attach to a driver for a specified LUN
2164 * during runtime. This is not called during VM construction, the device
2165 * constructor have to attach to all the available drivers.
2166 *
2167 * @returns VBox status code.
2168 * @param pDevIns The device instance.
2169 * @param uLUN The logical unit which is being detached.
2170 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
2171 */
2172static DECLCALLBACK(int) ichac97Attach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
2173{
2174 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2175
2176 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
2177 ("AC'97 device does not support hotplugging\n"),
2178 VERR_INVALID_PARAMETER);
2179
2180 /*
2181 * Attach driver.
2182 */
2183 char *pszDesc = NULL;
2184 if (RTStrAPrintf(&pszDesc, "Audio driver port (AC'97) for LUN #%u", uLUN) <= 0)
2185 AssertMsgReturn(pszDesc,
2186 ("Not enough memory for AC'97 driver port description of LUN #%u\n", uLUN),
2187 VERR_NO_MEMORY);
2188
2189 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
2190 &pThis->IBase, &pThis->pDrvBase, pszDesc);
2191 if (RT_SUCCESS(rc))
2192 {
2193 PAC97DRIVER pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
2194 if (pDrv)
2195 {
2196 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
2197 AssertMsg(pDrv->pConnector != NULL,
2198 ("Configuration error: LUN #%u has no host audio interface, rc=%Rrc\n",
2199 uLUN, rc));
2200 pDrv->pAC97State = pThis;
2201 pDrv->uLUN = uLUN;
2202
2203 /*
2204 * For now we always set the driver at LUN 0 as our primary
2205 * host backend. This might change in the future.
2206 */
2207 if (pDrv->uLUN == 0)
2208 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
2209
2210 LogFunc(("LUN#%RU8: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
2211
2212 /* Attach to driver list. */
2213 RTListAppend(&pThis->lstDrv, &pDrv->Node);
2214 }
2215 else
2216 rc = VERR_NO_MEMORY;
2217 }
2218 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2219 {
2220 LogFunc(("No attached driver for LUN #%u\n", uLUN));
2221 }
2222 else if (RT_FAILURE(rc))
2223 AssertMsgFailed(("Failed to attach AC'97 LUN #%u (\"%s\"), rc=%Rrc\n",
2224 uLUN, pszDesc, rc));
2225
2226 RTStrFree(pszDesc);
2227
2228 LogFunc(("iLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
2229 return rc;
2230}
2231
2232
2233/**
2234 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2235 */
2236static DECLCALLBACK(int) ichac97Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2237{
2238 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2239
2240 /* NB: This must be done *before* any possible failure (and running the destructor). */
2241 RTListInit(&pThis->lstDrv);
2242
2243 Assert(iInstance == 0);
2244 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2245
2246 /*
2247 * Validations.
2248 */
2249 if (!CFGMR3AreValuesValid(pCfg, "Codec\0"))
2250 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2251 N_("Invalid configuration for the AC'97 device"));
2252
2253 /*
2254 * Determine the codec model.
2255 */
2256 char szCodec[20];
2257 int rc = CFGMR3QueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
2258 if (RT_FAILURE(rc))
2259 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2260 N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
2261
2262 /*
2263 * The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
2264 * in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
2265 * 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
2266 */
2267 bool fChipAD1980 = false;
2268 if (!strcmp(szCodec, "STAC9700"))
2269 pThis->uCodecModel = Codec_STAC9700;
2270 else if (!strcmp(szCodec, "AD1980"))
2271 pThis->uCodecModel = Codec_AD1980;
2272 else if (!strcmp(szCodec, "AD1981B"))
2273 pThis->uCodecModel = Codec_AD1981B;
2274 else
2275 {
2276 return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
2277 N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"),
2278 szCodec);
2279 }
2280
2281 /*
2282 * Initialize data (most of it anyway).
2283 */
2284 pThis->pDevInsR3 = pDevIns;
2285 /* IBase */
2286 pThis->IBase.pfnQueryInterface = ichac97QueryInterface;
2287
2288 /* PCI Device (the assertions will be removed later) */
2289 PCIDevSetVendorId (&pThis->PciDev, 0x8086); /* 00 ro - intel. */ Assert(pThis->PciDev.config[0x00] == 0x86); Assert(pThis->PciDev.config[0x01] == 0x80);
2290 PCIDevSetDeviceId (&pThis->PciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pThis->PciDev.config[0x02] == 0x15); Assert(pThis->PciDev.config[0x03] == 0x24);
2291 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pThis->PciDev.config[0x04] == 0x00); Assert(pThis->PciDev.config[0x05] == 0x00);
2292 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pThis->PciDev.config[0x06] == 0x80); Assert(pThis->PciDev.config[0x07] == 0x02);
2293 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */ Assert(pThis->PciDev.config[0x08] == 0x01);
2294 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */ Assert(pThis->PciDev.config[0x09] == 0x00);
2295 PCIDevSetClassSub (&pThis->PciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pThis->PciDev.config[0x0a] == 0x01);
2296 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */ Assert(pThis->PciDev.config[0x0b] == 0x04);
2297 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */ Assert(pThis->PciDev.config[0x0e] == 0x00);
2298 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - nambar - native audio mixer base. */
2299 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pThis->PciDev.config[0x10] == 0x01); Assert(pThis->PciDev.config[0x11] == 0x00); Assert(pThis->PciDev.config[0x12] == 0x00); Assert(pThis->PciDev.config[0x13] == 0x00);
2300 PCIDevSetBaseAddress (&pThis->PciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
2301 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pThis->PciDev.config[0x14] == 0x01); Assert(pThis->PciDev.config[0x15] == 0x00); Assert(pThis->PciDev.config[0x16] == 0x00); Assert(pThis->PciDev.config[0x17] == 0x00);
2302 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */ Assert(pThis->PciDev.config[0x3c] == 0x00);
2303 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */ Assert(pThis->PciDev.config[0x3d] == 0x01);
2304
2305 if (pThis->uCodecModel == Codec_AD1980)
2306 {
2307 PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x1028); /* 2c ro - Dell.) */
2308 PCIDevSetSubSystemId (&pThis->PciDev, 0x0177); /* 2e ro. */
2309 }
2310 else if (pThis->uCodecModel == Codec_AD1981B)
2311 {
2312 PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x1028); /* 2c ro - Dell.) */
2313 PCIDevSetSubSystemId (&pThis->PciDev, 0x01ad); /* 2e ro. */
2314 }
2315 else
2316 {
2317 PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x8086); /* 2c ro - Intel.) */
2318 PCIDevSetSubSystemId (&pThis->PciDev, 0x0000); /* 2e ro. */
2319 }
2320
2321 /*
2322 * Register the PCI device, it's I/O regions, the timer and the
2323 * saved state item.
2324 */
2325 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
2326 if (RT_FAILURE(rc))
2327 return rc;
2328
2329 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 256, PCI_ADDRESS_SPACE_IO, ichac97IOPortMap);
2330 if (RT_FAILURE(rc))
2331 return rc;
2332
2333 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 64, PCI_ADDRESS_SPACE_IO, ichac97IOPortMap);
2334 if (RT_FAILURE(rc))
2335 return rc;
2336
2337 rc = PDMDevHlpSSMRegister(pDevIns, AC97_SSM_VERSION, sizeof(*pThis), ichac97SaveExec, ichac97LoadExec);
2338 if (RT_FAILURE(rc))
2339 return rc;
2340
2341 /*
2342 * Attach driver.
2343 */
2344 uint8_t uLUN;
2345 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
2346 {
2347 LogFunc(("Trying to attach driver for LUN #%RU8 ...\n", uLUN));
2348 rc = ichac97Attach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
2349 if (RT_FAILURE(rc))
2350 {
2351 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2352 rc = VINF_SUCCESS;
2353 break;
2354 }
2355
2356 uLUN++;
2357 }
2358
2359 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
2360
2361 if (RT_SUCCESS(rc))
2362 {
2363 rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThis->pMixer);
2364 if (RT_SUCCESS(rc))
2365 {
2366 /* Set a default audio format for our mixer. */
2367 PDMAUDIOSTREAMCFG streamCfg;
2368 streamCfg.uHz = 44100;
2369 streamCfg.cChannels = 2;
2370 streamCfg.enmFormat = AUD_FMT_S16;
2371 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
2372
2373 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
2374 AssertRC(rc);
2375
2376 /* Add all required audio sinks. */
2377 rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output", AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
2378 AssertRC(rc);
2379
2380 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In", AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
2381 AssertRC(rc);
2382
2383 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In", AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
2384 AssertRC(rc);
2385 }
2386 }
2387
2388 ichac97Reset(pDevIns);
2389
2390 if (RT_SUCCESS(rc))
2391 {
2392 rc = ichac97StreamInit(pThis, &pThis->StrmStLineIn, PI_INDEX);
2393 if (RT_FAILURE(rc))
2394 return rc;
2395 rc = ichac97StreamInit(pThis, &pThis->StrmStMicIn, MC_INDEX);
2396 if (RT_FAILURE(rc))
2397 return rc;
2398 rc = ichac97StreamInit(pThis, &pThis->StrmStOut, PO_INDEX);
2399 if (RT_FAILURE(rc))
2400 return rc;
2401
2402 PAC97DRIVER pDrv;
2403 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
2404 {
2405 /*
2406 * Only primary drivers are critical for the VM to run. Everything else
2407 * might not worth showing an own error message box in the GUI.
2408 */
2409 if (!(pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY))
2410 continue;
2411
2412 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
2413 AssertPtr(pCon);
2414
2415 uint8_t cFailed = 0;
2416 if (!pCon->pfnIsInputOK (pCon, pDrv->LineIn.pStrmIn))
2417 cFailed++;
2418 if (!pCon->pfnIsInputOK (pCon, pDrv->MicIn.pStrmIn))
2419 cFailed++;
2420 if (!pCon->pfnIsOutputOK(pCon, pDrv->Out.pStrmOut))
2421 cFailed++;
2422
2423 if (cFailed == 3)
2424 {
2425 LogRel(("AC97: Falling back to NULL driver (no sound audible)\n"));
2426
2427 ichac97Reset(pDevIns);
2428
2429 /* Was not able initialize *any* stream.
2430 * Select the NULL audio driver instead. */
2431 pCon->pfnInitNull(pCon);
2432
2433 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
2434 N_("No audio devices could be opened. Selecting the NULL audio backend "
2435 "with the consequence that no sound is audible"));
2436 }
2437 else if (cFailed)
2438 {
2439 if (!pDrv->pConnector->pfnIsInputOK(pDrv->pConnector, pDrv->LineIn.pStrmIn))
2440 LogRel(("AC97: WARNING: Unable to open PCM line input for LUN #%RU32!\n", pDrv->uLUN));
2441 if (!pDrv->pConnector->pfnIsInputOK(pDrv->pConnector, pDrv->MicIn.pStrmIn))
2442 LogRel(("AC97: WARNING: Unable to open PCM microphone input for LUN #%RU32!\n", pDrv->uLUN));
2443 if (!pDrv->pConnector->pfnIsOutputOK(pDrv->pConnector, pDrv->Out.pStrmOut))
2444 LogRel(("AC97: WARNING: Unable to open PCM output for LUN #%RU32!\n", pDrv->uLUN));
2445
2446 char szMissingStreams[255];
2447 size_t len = 0;
2448 if (!pCon->pfnIsInputOK (pCon, pDrv->LineIn.pStrmIn))
2449 len = RTStrPrintf(szMissingStreams,
2450 sizeof(szMissingStreams), "PCM Input");
2451 if (!pCon->pfnIsOutputOK(pCon, pDrv->Out.pStrmOut))
2452 len += RTStrPrintf(szMissingStreams + len,
2453 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
2454 if (!pCon->pfnIsInputOK (pCon, pDrv->MicIn.pStrmIn))
2455 len += RTStrPrintf(szMissingStreams + len,
2456 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
2457
2458 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
2459 N_("Some AC'97 audio streams (%s) could not be opened. Guest applications generating audio "
2460 "output or depending on audio input may hang. Make sure your host audio device "
2461 "is working properly. Check the logfile for error messages of the audio "
2462 "subsystem"), szMissingStreams);
2463 }
2464 }
2465 }
2466
2467 if (RT_SUCCESS(rc))
2468 {
2469 pThis->cbReadWriteBuf = _4K; /** @todo Make this configurable. */
2470 pThis->pvReadWriteBuf = (uint8_t *)RTMemAllocZ(pThis->cbReadWriteBuf);
2471 if (!pThis->pvReadWriteBuf)
2472 rc = VERR_NO_MEMORY;
2473 }
2474
2475# ifndef VBOX_WITH_AUDIO_CALLBACKS
2476 if (RT_SUCCESS(rc))
2477 {
2478 /* Start the emulation timer. */
2479 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, ichac97Timer, pThis,
2480 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchAc97", &pThis->pTimer);
2481 AssertRCReturn(rc, rc);
2482
2483 if (RT_SUCCESS(rc))
2484 {
2485 pThis->uTimerTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 200; /** Hz. @todo Make this configurable! */
2486 pThis->uTimerTS = PDMDevHlpTMTimeVirtGet(pDevIns);
2487 if (pThis->uTimerTicks < 100)
2488 pThis->uTimerTicks = 100;
2489 LogFunc(("Timer ticks=%RU64\n", pThis->uTimerTicks));
2490
2491 /* Fire off timer. */
2492 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTimerTicks);
2493 }
2494 }
2495# else
2496 if (RT_SUCCESS(rc))
2497 {
2498 PAC97DRIVER pDrv;
2499 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
2500 {
2501 /* Only register primary driver.
2502 * The device emulation does the output multiplexing then. */
2503 if (pDrv->Flags != PDMAUDIODRVFLAG_PRIMARY)
2504 continue;
2505
2506 PDMAUDIOCALLBACK AudioCallbacks[2];
2507
2508 AC97CALLBACKCTX Ctx = { pThis, pDrv };
2509
2510 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
2511 AudioCallbacks[0].pfnCallback = ac97CallbackInput;
2512 AudioCallbacks[0].pvCtx = &Ctx;
2513 AudioCallbacks[0].cbCtx = sizeof(AC97CALLBACKCTX);
2514
2515 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
2516 AudioCallbacks[1].pfnCallback = ac97CallbackOutput;
2517 AudioCallbacks[1].pvCtx = &Ctx;
2518 AudioCallbacks[1].cbCtx = sizeof(AC97CALLBACKCTX);
2519
2520 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
2521 if (RT_FAILURE(rc))
2522 break;
2523 }
2524 }
2525# endif
2526
2527# ifdef VBOX_WITH_STATISTICS
2528 if (RT_SUCCESS(rc))
2529 {
2530 /*
2531 * Register statistics.
2532 */
2533 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/AC97/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
2534 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/AC97/BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
2535 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/AC97/BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
2536 }
2537# endif
2538
2539 LogFlowFuncLeaveRC(rc);
2540 return rc;
2541}
2542
2543/**
2544 * The device registration structure.
2545 */
2546const PDMDEVREG g_DeviceICHAC97 =
2547{
2548 /* u32Version */
2549 PDM_DEVREG_VERSION,
2550 /* szName */
2551 "ichac97",
2552 /* szRCMod */
2553 "",
2554 /* szR0Mod */
2555 "",
2556 /* pszDescription */
2557 "ICH AC'97 Audio Controller",
2558 /* fFlags */
2559 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2560 /* fClass */
2561 PDM_DEVREG_CLASS_AUDIO,
2562 /* cMaxInstances */
2563 1,
2564 /* cbInstance */
2565 sizeof(AC97STATE),
2566 /* pfnConstruct */
2567 ichac97Construct,
2568 /* pfnDestruct */
2569 ichac97Destruct,
2570 /* pfnRelocate */
2571 NULL,
2572 /* pfnMemSetup */
2573 NULL,
2574 /* pfnPowerOn */
2575 NULL,
2576 /* pfnReset */
2577 ichac97Reset,
2578 /* pfnSuspend */
2579 NULL,
2580 /* pfnResume */
2581 NULL,
2582 /* pfnAttach */
2583 NULL,
2584 /* pfnDetach */
2585 NULL,
2586 /* pfnQueryInterface. */
2587 NULL,
2588 /* pfnInitComplete */
2589 NULL,
2590 /* pfnPowerOff */
2591 NULL,
2592 /* pfnSoftReset */
2593 NULL,
2594 /* u32VersionEnd */
2595 PDM_DEVREG_VERSION
2596};
2597
2598#endif /* !IN_RING3 */
2599#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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