VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 59185

Last change on this file since 59185 was 59171, checked in by vboxsync, 9 years ago

Audio/DevIchAc97: warning
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1/* $Id: DevIchAc97.cpp 59171 2015-12-17 10:07:19Z vboxsync $ */
2/** @file
3 * DevIchAc97 - VBox ICH AC97 Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_AC97
23#include <VBox/log.h>
24#include <VBox/vmm/pdmdev.h>
25#include <VBox/vmm/pdmaudioifs.h>
26
27#include <iprt/assert.h>
28#ifdef IN_RING3
29# include <iprt/mem.h>
30# include <iprt/string.h>
31# include <iprt/uuid.h>
32#endif
33
34#include "VBoxDD.h"
35
36#include "AudioMixBuffer.h"
37#include "AudioMixer.h"
38
39
40/*********************************************************************************************************************************
41* Defined Constants And Macros *
42*********************************************************************************************************************************/
43
44#ifdef DEBUG
45//#define DEBUG_LUN
46# ifdef DEBUG_LUN
47# define DEBUG_LUN_NUM 1
48# endif
49#endif /* DEBUG */
50
51#define AC97_SSM_VERSION 1
52
53#ifdef VBOX
54# define SOFT_VOLUME /** @todo Get rid of this crap. */
55#else
56# define SOFT_VOLUME
57#endif
58
59#define SR_FIFOE RT_BIT(4) /* rwc, FIFO error. */
60#define SR_BCIS RT_BIT(3) /* rwc, Buffer completion interrupt status. */
61#define SR_LVBCI RT_BIT(2) /* rwc, Last valid buffer completion interrupt. */
62#define SR_CELV RT_BIT(1) /* ro, Current equals last valid. */
63#define SR_DCH RT_BIT(0) /* ro, Controller halted. */
64#define SR_VALID_MASK (RT_BIT(5) - 1)
65#define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
66#define SR_RO_MASK (SR_DCH | SR_CELV)
67#define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
68
69#define CR_IOCE RT_BIT(4) /* rw, Interrupt On Completion Enable. */
70#define CR_FEIE RT_BIT(3) /* rw FIFO Error Interrupt Enable. */
71#define CR_LVBIE RT_BIT(2) /* rw */
72#define CR_RR RT_BIT(1) /* rw */
73#define CR_RPBM RT_BIT(0) /* rw */
74#define CR_VALID_MASK (RT_BIT(5) - 1)
75#define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
76
77#define GC_WR 4 /* rw */
78#define GC_CR 2 /* rw */
79#define GC_VALID_MASK (RT_BIT(6) - 1)
80
81#define GS_MD3 RT_BIT(17) /* rw */
82#define GS_AD3 RT_BIT(16) /* rw */
83#define GS_RCS RT_BIT(15) /* rwc */
84#define GS_B3S12 RT_BIT(14) /* ro */
85#define GS_B2S12 RT_BIT(13) /* ro */
86#define GS_B1S12 RT_BIT(12) /* ro */
87#define GS_S1R1 RT_BIT(11) /* rwc */
88#define GS_S0R1 RT_BIT(10) /* rwc */
89#define GS_S1CR RT_BIT(9) /* ro */
90#define GS_S0CR RT_BIT(8) /* ro */
91#define GS_MINT RT_BIT(7) /* ro */
92#define GS_POINT RT_BIT(6) /* ro */
93#define GS_PIINT RT_BIT(5) /* ro */
94#define GS_RSRVD (RT_BIT(4)|RT_BIT(3))
95#define GS_MOINT RT_BIT(2) /* ro */
96#define GS_MIINT RT_BIT(1) /* ro */
97#define GS_GSCI RT_BIT(0) /* rwc */
98#define GS_RO_MASK (GS_B3S12 | \
99 GS_B2S12 | \
100 GS_B1S12 | \
101 GS_S1CR | \
102 GS_S0CR | \
103 GS_MINT | \
104 GS_POINT | \
105 GS_PIINT | \
106 GS_RSRVD | \
107 GS_MOINT | \
108 GS_MIINT)
109#define GS_VALID_MASK (RT_BIT(18) - 1)
110#define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
111
112/** @name Buffer Descriptor
113 * @{ */
114#define BD_IOC RT_BIT(31) /**< Interrupt on Completion */
115#define BD_BUP RT_BIT(30) /**< Buffer Underrun Policy */
116/** @} */
117
118#define EACS_VRA 1
119#define EACS_VRM 8
120
121#define VOL_MASK 0x1f
122#define MUTE_SHIFT 15
123
124#define REC_MASK 7
125enum
126{
127 REC_MIC = 0,
128 REC_CD,
129 REC_VIDEO,
130 REC_AUX,
131 REC_LINE_IN,
132 REC_STEREO_MIX,
133 REC_MONO_MIX,
134 REC_PHONE
135};
136
137enum
138{
139 AC97_Reset = 0x00,
140 AC97_Master_Volume_Mute = 0x02,
141 AC97_Headphone_Volume_Mute = 0x04, /** Also known as AUX, see table 16, section 5.7. */
142 AC97_Master_Volume_Mono_Mute = 0x06,
143 AC97_Master_Tone_RL = 0x08,
144 AC97_PC_BEEP_Volume_Mute = 0x0A,
145 AC97_Phone_Volume_Mute = 0x0C,
146 AC97_Mic_Volume_Mute = 0x0E,
147 AC97_Line_In_Volume_Mute = 0x10,
148 AC97_CD_Volume_Mute = 0x12,
149 AC97_Video_Volume_Mute = 0x14,
150 AC97_Aux_Volume_Mute = 0x16,
151 AC97_PCM_Out_Volume_Mute = 0x18,
152 AC97_Record_Select = 0x1A,
153 AC97_Record_Gain_Mute = 0x1C,
154 AC97_Record_Gain_Mic_Mute = 0x1E,
155 AC97_General_Purpose = 0x20,
156 AC97_3D_Control = 0x22,
157 AC97_AC_97_RESERVED = 0x24,
158 AC97_Powerdown_Ctrl_Stat = 0x26,
159 AC97_Extended_Audio_ID = 0x28,
160 AC97_Extended_Audio_Ctrl_Stat = 0x2A,
161 AC97_PCM_Front_DAC_Rate = 0x2C,
162 AC97_PCM_Surround_DAC_Rate = 0x2E,
163 AC97_PCM_LFE_DAC_Rate = 0x30,
164 AC97_PCM_LR_ADC_Rate = 0x32,
165 AC97_MIC_ADC_Rate = 0x34,
166 AC97_6Ch_Vol_C_LFE_Mute = 0x36,
167 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
168 AC97_Vendor_Reserved = 0x58,
169 AC97_AD_Misc = 0x76,
170 AC97_Vendor_ID1 = 0x7c,
171 AC97_Vendor_ID2 = 0x7e
172};
173
174/* Codec models. */
175enum {
176 Codec_STAC9700 = 0, /* SigmaTel STAC9700 */
177 Codec_AD1980, /* Analog Devices AD1980 */
178 Codec_AD1981B /* Analog Devices AD1981B */
179};
180
181/* Analog Devices miscellaneous regiter bits used in AD1980. */
182#define AD_MISC_LOSEL RT_BIT(5) /* Surround (rear) goes to line out outputs. */
183#define AD_MISC_HPSEL RT_BIT(10) /* PCM (front) goes to headphone outputs. */
184
185#define ICHAC97STATE_2_DEVINS(a_pAC97) ((a_pAC97)->pDevInsR3)
186
187enum
188{
189 BUP_SET = RT_BIT(0),
190 BUP_LAST = RT_BIT(1)
191};
192
193/** Emits registers for a specific (Native Audio Bus Master BAR) NABMBAR. */
194#define AC97_NABMBAR_REGS(prefix, off) \
195 enum { \
196 prefix ## _BDBAR = off, \
197 prefix ## _CIV = off + 4, \
198 prefix ## _LVI = off + 5, \
199 prefix ## _SR = off + 6, \
200 prefix ## _PICB = off + 8, \
201 prefix ## _PIV = off + 10, \
202 prefix ## _CR = off + 11 \
203 }
204
205#ifndef VBOX_DEVICE_STRUCT_TESTCASE
206typedef enum
207{
208 PI_INDEX = 0, /** PCM in */
209 PO_INDEX, /** PCM out */
210 MC_INDEX, /** Mic in */
211 LAST_INDEX
212} AC97SOUNDSOURCE;
213
214AC97_NABMBAR_REGS(PI, PI_INDEX * 16);
215AC97_NABMBAR_REGS(PO, PO_INDEX * 16);
216AC97_NABMBAR_REGS(MC, MC_INDEX * 16);
217#endif
218
219enum
220{
221 /** NABMBAR: Global Control Register. */
222 GLOB_CNT = 0x2c,
223 /** NABMBAR Global Status. */
224 GLOB_STA = 0x30,
225 /** Codec Access Semaphore Register. */
226 CAS = 0x34
227};
228
229#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
230
231/*********************************************************************************************************************************
232* Structures and Typedefs *
233*********************************************************************************************************************************/
234
235/**
236 * Buffer Descriptor List Entry (BDLE).
237 */
238typedef struct AC97BDLE
239{
240 uint32_t addr;
241 uint32_t ctl_len;
242} AC97BDLE, *PAC97BDLE;
243
244/**
245 * Bus master register set for an audio stream.
246 */
247typedef struct AC97BMREGS
248{
249 uint32_t bdbar; /** rw 0, Buffer Descriptor List: BAR (Base Address Register). */
250 uint8_t civ; /** ro 0, Current index value. */
251 uint8_t lvi; /** rw 0, Last valid index. */
252 uint16_t sr; /** rw 1, Status register. */
253 uint16_t picb; /** ro 0, Position in current buffer. */
254 uint8_t piv; /** ro 0, Prefetched index value. */
255 uint8_t cr; /** rw 0, Control register. */
256 int bd_valid; /** Whether current BDLE is initialized or not. */
257 AC97BDLE bd; /** Current Buffer Descriptor List Entry (BDLE). */
258} AC97BMREGS, *PAC97BMREGS;
259
260/**
261 * Internal state of an AC97 stream.
262 */
263typedef struct AC97STREAMSTATE
264{
265 /* Nothing yet. */
266} AC97STREAMSTATE, *PAC97STREAMSTATE;
267
268/**
269 * Structure for keeping an AC97 stream state.
270 *
271 * Contains only register values which do *not* change until a
272 * stream reset occurs.
273 */
274typedef struct AC97STREAM
275{
276 /** Stream number (SDn). */
277 uint8_t u8Strm;
278 /** Bus master registers of this stream. */
279 AC97BMREGS Regs;
280 /** Internal state of this stream. */
281 AC97STREAMSTATE State;
282} AC97STREAM, *PAC97STREAM;
283
284typedef struct AC97INPUTSTREAM
285{
286 /** PCM line input stream. */
287 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
288 /** Mixer handle for line input stream. */
289 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
290} AC97INPUTSTREAM, *PAC97INPUTSTREAM;
291
292typedef struct AC97OUTPUTSTREAM
293{
294 /** PCM output stream. */
295 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
296 /** Mixer handle for output stream. */
297 R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
298} AC97OUTPUTSTREAM, *PAC97OUTPUTSTREAM;
299
300/**
301 * Struct for maintaining a host backend driver.
302 */
303typedef struct AC97STATE *PAC97STATE;
304typedef struct AC97DRIVER
305{
306 union
307 {
308 /** Node for storing this driver in our device driver
309 * list of AC97STATE. */
310 RTLISTNODE Node;
311 struct
312 {
313 R3PTRTYPE(void *) dummy1;
314 R3PTRTYPE(void *) dummy2;
315 } dummy;
316 };
317
318 /** Pointer to AC97 controller (state). */
319 R3PTRTYPE(PAC97STATE) pAC97State;
320 /** Driver flags. */
321 PDMAUDIODRVFLAGS Flags;
322 uint32_t PaddingFlags;
323 /** LUN # to which this driver has been assigned. */
324 uint8_t uLUN;
325 uint8_t Padding[5];
326 /** Audio connector interface to the underlying
327 * host backend. */
328 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
329 /** Stream for line input. */
330 AC97INPUTSTREAM LineIn;
331 /** Stream for mic input. */
332 AC97INPUTSTREAM MicIn;
333 /** Stream for output. */
334 AC97OUTPUTSTREAM Out;
335} AC97DRIVER, *PAC97DRIVER;
336
337typedef struct AC97STATE
338{
339 /** The PCI device state. */
340 PCIDevice PciDev;
341 /** R3 Pointer to the device instance. */
342 PPDMDEVINSR3 pDevInsR3;
343 /** Global Control (Bus Master Control Register) */
344 uint32_t glob_cnt;
345 /** Global Status (Bus Master Control Register) */
346 uint32_t glob_sta;
347 /** Codec Access Semaphore Register (Bus Master Control Register) */
348 uint32_t cas;
349 uint32_t last_samp;
350 uint8_t mixer_data[256];
351 /** Stream state for line-in. */
352 AC97STREAM StrmStLineIn;
353 /** Stream state for microphone-in. */
354 AC97STREAM StrmStMicIn;
355 /** Stream state for output. */
356 AC97STREAM StrmStOut;
357#ifndef VBOX_WITH_AUDIO_CALLBACKS
358 /** The emulation timer for handling the attached
359 * LUN drivers. */
360 PTMTIMERR3 pTimer;
361 /** Timer ticks for handling the LUN drivers. */
362 uint64_t uTimerTicks;
363 /** Timestamp (delta) since last timer call. */
364 uint64_t uTimerTS;
365#endif
366#ifdef VBOX_WITH_STATISTICS
367 STAMPROFILE StatTimer;
368 STAMCOUNTER StatBytesRead;
369 STAMCOUNTER StatBytesWritten;
370#endif
371 /** List of associated LUN drivers. */
372 RTLISTANCHOR lstDrv;
373 /** The device' software mixer. */
374 R3PTRTYPE(PAUDIOMIXER) pMixer;
375 /** Audio sink for PCM output. */
376 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
377 /** Audio sink for line input. */
378 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
379 /** Audio sink for microphone input. */
380 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
381 uint8_t silence[128];
382 int bup_flag;
383 /** Pointer to the attached audio driver. */
384 PPDMIBASE pDrvBase;
385 /** The base interface for LUN\#0. */
386 PDMIBASE IBase;
387 /** Base port of the I/O space region. */
388 RTIOPORT IOPortBase[2];
389 /** Pointer to temporary scratch read/write buffer. */
390 R3PTRTYPE(uint8_t *) pvReadWriteBuf;
391 /** Size of the temporary scratch read/write buffer. */
392 uint32_t cbReadWriteBuf;
393 /** Codec model. */
394 uint32_t uCodecModel;
395} AC97STATE, *PAC97STATE;
396
397#ifdef VBOX_WITH_STATISTICS
398AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
399#endif
400
401#ifndef VBOX_DEVICE_STRUCT_TESTCASE
402
403DECLINLINE(PAC97STREAM) ichac97GetStreamFromID(PAC97STATE pThis, uint32_t uID);
404static DECLCALLBACK(void) ichac97Reset(PPDMDEVINS pDevIns);
405#ifndef VBOX_WITH_AUDIO_CALLBACKS
406static DECLCALLBACK(void) ichac97Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
407#endif
408static int ichac97TransferAudio(PAC97STATE pThis, AC97SOUNDSOURCE enmSrc, uint32_t cbElapsed);
409
410static void ichac97WarmReset(PAC97STATE pThis)
411{
412 NOREF(pThis);
413}
414
415static void ichac97ColdReset(PAC97STATE pThis)
416{
417 NOREF(pThis);
418}
419
420/** Fetches the buffer descriptor at _CIV. */
421static void ichac97StreamFetchBDLE(PAC97STATE pThis, PAC97STREAM pStrmSt)
422{
423 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
424 PAC97BMREGS pRegs = &pStrmSt->Regs;
425
426 uint32_t u32[2];
427
428 PDMDevHlpPhysRead(pDevIns, pRegs->bdbar + pRegs->civ * 8, &u32[0], sizeof(u32));
429 pRegs->bd_valid = 1;
430#if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)
431# error Please adapt the code (audio buffers are little endian)!
432#else
433 pRegs->bd.addr = RT_H2LE_U32(u32[0] & ~3);
434 pRegs->bd.ctl_len = RT_H2LE_U32(u32[1]);
435#endif
436 pRegs->picb = pRegs->bd.ctl_len & 0xffff;
437 LogFlowFunc(("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
438 pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len >> 16,
439 pRegs->bd.ctl_len & 0xffff, (pRegs->bd.ctl_len & 0xffff) << 1));
440}
441
442/**
443 * Update the BM status register
444 */
445static void ichac97StreamUpdateStatus(PAC97STATE pThis, PAC97STREAM pStrmSt, uint32_t new_sr)
446{
447 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
448 PAC97BMREGS pRegs = &pStrmSt->Regs;
449
450 bool fSignal = false;
451 bool iIrqLevel;
452
453 uint32_t new_mask = new_sr & SR_INT_MASK;
454 uint32_t old_mask = pRegs->sr & SR_INT_MASK;
455
456 static uint32_t const masks[] = { GS_PIINT, GS_POINT, GS_MINT };
457
458 if (new_mask ^ old_mask)
459 {
460 /** @todo Is IRQ deasserted when only one of status bits is cleared? */
461 if (!new_mask)
462 {
463 fSignal = true;
464 iIrqLevel = 0;
465 }
466 else if ((new_mask & SR_LVBCI) && (pRegs->cr & CR_LVBIE))
467 {
468 fSignal = true;
469 iIrqLevel = 1;
470 }
471 else if ((new_mask & SR_BCIS) && (pRegs->cr & CR_IOCE))
472 {
473 fSignal = true;
474 iIrqLevel = 1;
475 }
476 }
477
478 pRegs->sr = new_sr;
479
480 LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, iIrqLevel=%d\n",
481 pRegs->sr & SR_BCIS, pRegs->sr & SR_LVBCI, pRegs->sr, fSignal, iIrqLevel));
482
483 if (fSignal)
484 {
485 if (iIrqLevel)
486 pThis->glob_sta |= masks[pStrmSt->u8Strm];
487 else
488 pThis->glob_sta &= ~masks[pStrmSt->u8Strm];
489
490 LogFlowFunc(("set irq level=%d\n", !!iIrqLevel));
491 PDMDevHlpPCISetIrq(pDevIns, 0, !!iIrqLevel);
492 }
493}
494
495static int ichac97StreamSetActive(PAC97STATE pThis, PAC97STREAM pStrmSt, bool fActive)
496{
497 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
498 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
499
500 LogFlowFunc(("u8Strm=%RU8, fActive=%RTbool\n", pStrmSt->u8Strm, fActive));
501
502 int rc = VINF_SUCCESS;
503
504 PAC97DRIVER pDrv;
505 switch (pStrmSt->u8Strm)
506 {
507 case PI_INDEX:
508 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
509 {
510 int rc2 = pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
511 pDrv->LineIn.pStrmIn, fActive);
512 if (RT_SUCCESS(rc))
513 rc = rc2;
514 }
515 break;
516
517 case PO_INDEX:
518 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
519 {
520 int rc2 = pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
521 pDrv->Out.pStrmOut, fActive);
522 if (RT_SUCCESS(rc))
523 rc = rc2;
524 }
525 break;
526
527 case MC_INDEX:
528 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
529 {
530 int rc2 = pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
531 pDrv->MicIn.pStrmIn, fActive);
532 if (RT_SUCCESS(rc))
533 rc = rc2;
534 }
535 break;
536
537 default:
538 AssertMsgFailed(("Wrong index %RU32\n", pStrmSt->u8Strm));
539 rc = VERR_NOT_SUPPORTED;
540 break;
541 }
542
543 return rc;
544}
545
546static void ichac97StreamResetBMRegs(PAC97STATE pThis, PAC97STREAM pStrmSt)
547{
548 AssertPtrReturnVoid(pThis);
549 AssertPtrReturnVoid(pStrmSt);
550
551 LogFlowFuncEnter();
552
553 PAC97BMREGS pRegs = &pStrmSt->Regs;
554
555 pRegs->bdbar = 0;
556 pRegs->civ = 0;
557 pRegs->lvi = 0;
558
559 ichac97StreamUpdateStatus(pThis, pStrmSt, SR_DCH); /** @todo Do we need to do that? */
560
561 pRegs->picb = 0;
562 pRegs->piv = 0;
563 pRegs->cr = pRegs->cr & CR_DONT_CLEAR_MASK;
564 pRegs->bd_valid = 0;
565
566 int rc = ichac97StreamSetActive(pThis, pStrmSt, false /* fActive */);
567 AssertRC(rc);
568
569 RT_ZERO(pThis->silence);
570}
571
572static void ichac97MixerSet(PAC97STATE pThis, uint32_t u8Idx, uint16_t v)
573{
574 if (u8Idx + 2 > sizeof(pThis->mixer_data))
575 {
576 AssertMsgFailed(("Index %RU8 out of bounds(%zu)\n", u8Idx, sizeof(pThis->mixer_data)));
577 return;
578 }
579
580 pThis->mixer_data[u8Idx + 0] = RT_LO_U8(v);
581 pThis->mixer_data[u8Idx + 1] = RT_HI_U8(v);
582}
583
584static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t u8Idx)
585{
586 uint16_t uVal;
587
588 if (u8Idx + 2 > sizeof(pThis->mixer_data))
589 {
590 AssertMsgFailed(("Index %RU8 out of bounds (%zu)\n", u8Idx, sizeof(pThis->mixer_data)));
591 uVal = UINT16_MAX;
592 }
593 else
594 uVal = RT_MAKE_U16(pThis->mixer_data[u8Idx + 0], pThis->mixer_data[u8Idx + 1]);
595
596 return uVal;
597}
598
599static DECLCALLBACK(void) ichac97CloseIn(PAC97STATE pThis, PDMAUDIORECSOURCE enmRecSource)
600{
601 NOREF(pThis);
602 NOREF(enmRecSource);
603 LogFlowFuncEnter();
604}
605
606static DECLCALLBACK(void) ichac97CloseOut(PAC97STATE pThis)
607{
608 NOREF(pThis);
609 LogFlowFuncEnter();
610}
611
612static int ichac97OpenIn(PAC97STATE pThis,
613 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
614 PPDMAUDIOSTREAMCFG pCfg)
615{
616 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
617 AssertPtrReturn(pszName, VERR_INVALID_POINTER);
618 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
619
620 PAUDMIXSINK pSink;
621 switch (enmRecSource)
622 {
623 case PDMAUDIORECSOURCE_MIC:
624 pSink = pThis->pSinkMicIn;
625 break;
626 case PDMAUDIORECSOURCE_LINE_IN:
627 pSink = pThis->pSinkLineIn;
628 break;
629 default:
630 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
631 return VERR_NOT_SUPPORTED;
632 }
633
634 int rc = VINF_SUCCESS;
635
636 PAC97DRIVER pDrv;
637 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
638 {
639 char *pszDesc;
640 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
641 {
642 rc = VERR_NO_MEMORY;
643 break;
644 }
645
646 PAC97INPUTSTREAM pStrmIn;
647 if (enmRecSource == PDMAUDIORECSOURCE_MIC) /** @todo Refine this once we have more streams. */
648 pStrmIn = &pDrv->MicIn;
649 else
650 pStrmIn = &pDrv->LineIn;
651
652 rc = pDrv->pConnector->pfnCreateIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pStrmIn->pStrmIn);
653
654 LogFlowFunc(("LUN#%RU8: Created input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
655 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
656 {
657 AudioMixerRemoveStream(pSink, pStrmIn->phStrmIn);
658 rc = AudioMixerAddStreamIn(pSink,
659 pDrv->pConnector, pStrmIn->pStrmIn,
660 0 /* uFlags */, &pStrmIn->phStrmIn);
661 }
662
663 RTStrFree(pszDesc);
664 }
665
666 LogFlowFuncLeaveRC(rc);
667 return rc;
668}
669
670static int ichac97OpenOut(PAC97STATE pThis, const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
671{
672 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
673 AssertPtrReturn(pszName, VERR_INVALID_POINTER);
674 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
675
676 int rc = VINF_SUCCESS;
677 char *pszDesc;
678
679 PAC97DRIVER pDrv;
680 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
681 {
682 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s (%RU32Hz, %RU8 %s)",
683 pDrv->uLUN, pszName, pCfg->uHz, pCfg->cChannels, pCfg->cChannels > 1 ? "Channels" : "Channel") <= 0)
684 {
685 rc = VERR_NO_MEMORY;
686 break;
687 }
688
689 rc = pDrv->pConnector->pfnCreateOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
690 LogFlowFunc(("LUN#%RU8: Created output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
691 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
692 {
693 AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
694 rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
695 pDrv->pConnector, pDrv->Out.pStrmOut,
696 0 /* uFlags */, &pDrv->Out.phStrmOut);
697 }
698
699 RTStrFree(pszDesc);
700 }
701
702 LogFlowFuncLeaveRC(rc);
703 return rc;
704}
705
706static int ichac97StreamInitEx(PAC97STATE pThis, PAC97STREAM pStrmSt, uint8_t u8Strm, PPDMAUDIOSTREAMCFG pCfg)
707{
708 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
709 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
710 AssertReturn(u8Strm <= LAST_INDEX, VERR_INVALID_PARAMETER);
711 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
712
713 pStrmSt->u8Strm = u8Strm;
714
715 LogFlowFunc(("u8Strm=%RU8, %RU32Hz, %RU8 %s\n",
716 pStrmSt->u8Strm, pCfg->uHz, pCfg->cChannels, pCfg->cChannels > 1 ? "Channels" : "Channel"));
717
718 int rc;
719 switch (pStrmSt->u8Strm)
720 {
721 case PI_INDEX:
722 rc = ichac97OpenIn(pThis, "ac97.pi", PDMAUDIORECSOURCE_LINE_IN, pCfg);
723 break;
724
725 case MC_INDEX:
726 rc = ichac97OpenIn(pThis, "ac97.mc", PDMAUDIORECSOURCE_MIC, pCfg);
727 break;
728
729 case PO_INDEX:
730 rc = ichac97OpenOut(pThis, "ac97.po", pCfg);
731 break;
732
733 default:
734 rc = VERR_NOT_SUPPORTED;
735 break;
736 }
737
738 LogFlowFuncLeaveRC(rc);
739 return rc;
740}
741
742static int ichac97StreamInit(PAC97STATE pThis, PAC97STREAM pStrmSt, uint8_t u8Strm)
743{
744 int rc = VINF_SUCCESS;
745
746 PDMAUDIOSTREAMCFG streamCfg;
747 RT_ZERO(streamCfg);
748
749 switch (u8Strm)
750 {
751 case PI_INDEX:
752 streamCfg.uHz = ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate);
753 break;
754
755 case MC_INDEX:
756 streamCfg.uHz = ichac97MixerGet(pThis, AC97_MIC_ADC_Rate);
757 break;
758
759 case PO_INDEX:
760 streamCfg.uHz = ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate);
761 break;
762
763 default:
764 rc = VERR_NOT_SUPPORTED;
765 break;
766 }
767
768 if (RT_FAILURE(rc))
769 return rc;
770
771 if (streamCfg.uHz)
772 {
773 streamCfg.cChannels = 2;
774 streamCfg.enmFormat = AUD_FMT_S16;
775 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
776
777 return ichac97StreamInitEx(pThis, pStrmSt, u8Strm, &streamCfg);
778 }
779
780 /* If no frequency is given, disable the stream. */
781 return ichac97StreamSetActive(pThis, pStrmSt, false /* fActive */);
782}
783
784static int ichac97StreamReInit(PAC97STATE pThis, PAC97STREAM pStrmSt)
785{
786 return ichac97StreamInit(pThis, pStrmSt, pStrmSt->u8Strm);
787}
788
789static void ichac97StreamReset(PAC97STATE pThis, PAC97STREAM pStrmSt)
790{
791 AssertPtrReturnVoid(pThis);
792 AssertPtrReturnVoid(pStrmSt);
793
794 LogFlowFunc(("uStrm=%RU8\n", pStrmSt->u8Strm));
795}
796
797static int ichac97MixerSetVolume(PAC97STATE pThis, int index, PDMAUDIOMIXERCTL mt, uint32_t val)
798{
799 int mute = (val >> MUTE_SHIFT) & 1;
800 uint8_t rvol = val & VOL_MASK;
801 uint8_t lvol = (val >> 8) & VOL_MASK;
802
803 /* For the master volume, 0 corresponds to 0dB gain. But for the other
804 * volume controls, 0 corresponds to +12dB and 8 to 0dB. */
805 if (mt != PDMAUDIOMIXERCTL_VOLUME)
806 {
807 /* NB: Currently there is no gain support, only attenuation. */
808 lvol = lvol < 8 ? 0 : lvol - 8;
809 rvol = rvol < 8 ? 0 : rvol - 8;
810 }
811
812 /* AC'97 has 1.5dB steps; we use 0.375dB steps. */
813 rvol = 255 - rvol * 4;
814 lvol = 255 - lvol * 4;
815
816 LogFunc(("mt=%ld, val=%RX32, mute=%RTbool\n", mt, val, RT_BOOL(mute)));
817
818 int rc;
819
820#ifdef SOFT_VOLUME
821 if (pThis->pMixer) /* Device can be in reset state, so no mixer available. */
822 {
823 PDMAUDIOVOLUME vol = { RT_BOOL(mute), lvol, rvol };
824 switch (mt)
825 {
826 case PDMAUDIOMIXERCTL_VOLUME:
827 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
828 break;
829
830 case PDMAUDIOMIXERCTL_PCM:
831 rc = AudioMixerSetSinkVolume(pThis->pSinkOutput, &vol);
832 break;
833
834 case PDMAUDIOMIXERCTL_MIC_IN:
835 rc = AudioMixerSetSinkVolume(pThis->pSinkMicIn, &vol);
836 break;
837
838 case PDMAUDIOMIXERCTL_LINE_IN:
839 rc = AudioMixerSetSinkVolume(pThis->pSinkLineIn, &vol);
840 break;
841
842 default:
843 rc = VERR_NOT_SUPPORTED;
844 break;
845 }
846 }
847 else
848 rc = VERR_NOT_SUPPORTED;
849
850 if (RT_FAILURE(rc))
851 return rc;
852#else
853 rc = VINF_SUCCESS;
854#endif /* SOFT_VOLUME */
855
856 rvol = VOL_MASK - ((VOL_MASK * rvol) / 255);
857 lvol = VOL_MASK - ((VOL_MASK * lvol) / 255);
858
859 /*
860 * From AC'97 SoundMax Codec AD1981A: "Because AC '97 defines 6-bit volume registers, to
861 * maintain compatibility whenever the D5 or D13 bits are set to `1,' their respective
862 * lower five volume bits are automatically set to `1' by the Codec logic. On readback,
863 * all lower 5 bits will read ones whenever these bits are set to `1.'"
864 *
865 * Linux ALSA depends on this behavior.
866 */
867 if (val & RT_BIT(5))
868 val |= RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0);
869 if (val & RT_BIT(13))
870 val |= RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8);
871
872 ichac97MixerSet(pThis, index, val);
873
874 return rc;
875}
876
877static PDMAUDIORECSOURCE ichac97IndextoRecSource(uint8_t i)
878{
879 switch (i)
880 {
881 case REC_MIC: return PDMAUDIORECSOURCE_MIC;
882 case REC_CD: return PDMAUDIORECSOURCE_CD;
883 case REC_VIDEO: return PDMAUDIORECSOURCE_VIDEO;
884 case REC_AUX: return PDMAUDIORECSOURCE_AUX;
885 case REC_LINE_IN: return PDMAUDIORECSOURCE_LINE_IN;
886 case REC_PHONE: return PDMAUDIORECSOURCE_PHONE;
887 default:
888 break;
889 }
890
891 LogFlowFunc(("Unknown record source %d, using MIC\n", i));
892 return PDMAUDIORECSOURCE_MIC;
893}
894
895static uint8_t ichac97RecSourceToIndex(PDMAUDIORECSOURCE rs)
896{
897 switch (rs)
898 {
899 case PDMAUDIORECSOURCE_MIC: return REC_MIC;
900 case PDMAUDIORECSOURCE_CD: return REC_CD;
901 case PDMAUDIORECSOURCE_VIDEO: return REC_VIDEO;
902 case PDMAUDIORECSOURCE_AUX: return REC_AUX;
903 case PDMAUDIORECSOURCE_LINE_IN: return REC_LINE_IN;
904 case PDMAUDIORECSOURCE_PHONE: return REC_PHONE;
905 default:
906 break;
907 }
908
909 LogFlowFunc(("Unknown audio recording source %d using MIC\n", rs));
910 return REC_MIC;
911}
912
913static void ichac97RecordSelect(PAC97STATE pThis, uint32_t val)
914{
915 uint8_t rs = val & REC_MASK;
916 uint8_t ls = (val >> 8) & REC_MASK;
917 PDMAUDIORECSOURCE ars = ichac97IndextoRecSource(rs);
918 PDMAUDIORECSOURCE als = ichac97IndextoRecSource(ls);
919 //AUD_set_record_source(&als, &ars);
920 rs = ichac97RecSourceToIndex(ars);
921 ls = ichac97RecSourceToIndex(als);
922 ichac97MixerSet(pThis, AC97_Record_Select, rs | (ls << 8));
923}
924
925static int ichac97MixerReset(PAC97STATE pThis)
926{
927 AssertPtrReturn(pThis, VERR_INVALID_PARAMETER);
928
929 LogFlowFuncEnter();
930
931 RT_ZERO(pThis->mixer_data);
932
933 /* Note: Make sure to reset all registers first before bailing out on error. */
934
935 ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
936 ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
937 ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
938
939 ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
940 ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
941 ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
942 ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
943 ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
944 ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
945 ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
946 ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
947
948 ichac97MixerSet(pThis, AC97_Extended_Audio_ID , 0x0809);
949 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
950 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80);
951 ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80);
952 ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80);
953 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80);
954 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80);
955
956 if (pThis->uCodecModel == Codec_AD1980)
957 {
958 /* Analog Devices 1980 (AD1980) */
959 ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
960 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
961 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
962 ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
963 }
964 else if (pThis->uCodecModel == Codec_AD1981B)
965 {
966 /* Analog Devices 1981B (AD1981B) */
967 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
968 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
969 }
970 else
971 {
972 /* Sigmatel 9700 (STAC9700) */
973 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
974 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
975 }
976 ichac97RecordSelect(pThis, 0);
977
978 ichac97MixerSetVolume(pThis, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME, 0x8000);
979 ichac97MixerSetVolume(pThis, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_PCM, 0x8808);
980 ichac97MixerSetVolume(pThis, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
981
982 return VINF_SUCCESS;
983}
984
985/**
986 * Writes data from the device to the host backends.
987 *
988 * @return IPRT status code.
989 * @param pThis
990 * @param pStrmSt
991 * @param cbMax
992 * @param pcbWritten
993 */
994static int ichac97WriteAudio(PAC97STATE pThis, PAC97STREAM pStrmSt, uint32_t cbMax, uint32_t *pcbWritten)
995{
996 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
997 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
998 AssertReturn(cbMax, VERR_INVALID_PARAMETER);
999 /* pcbWritten is optional. */
1000
1001 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
1002 PAC97BMREGS pRegs = &pStrmSt->Regs;
1003
1004 uint32_t addr = pRegs->bd.addr;
1005 uint32_t cbWrittenTotal = 0;
1006 uint32_t cbToRead;
1007
1008 uint32_t cbToWrite = RT_MIN((uint32_t)(pRegs->picb << 1), cbMax);
1009 if (!cbToWrite)
1010 {
1011 if (pcbWritten)
1012 *pcbWritten = 0;
1013 return VINF_EOF;
1014 }
1015
1016 int rc = VINF_SUCCESS;
1017
1018 LogFlowFunc(("pReg=%p, cbMax=%RU32, cbToWrite=%RU32\n", pRegs, cbMax, cbToWrite));
1019
1020 while (cbToWrite)
1021 {
1022 cbToRead = RT_MIN(cbToWrite, pThis->cbReadWriteBuf);
1023 PDMDevHlpPhysRead(pDevIns, addr, pThis->pvReadWriteBuf, cbToRead); /** @todo Check rc? */
1024
1025 uint32_t cbWritten;
1026
1027 /* Just multiplex the output to the connected backends.
1028 * No need to utilize the virtual mixer here (yet). */
1029 PAC97DRIVER pDrv;
1030 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
1031 {
1032 int rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
1033 pThis->pvReadWriteBuf, cbToRead, &cbWritten);
1034 LogFlowFunc(("\tLUN#%RU8: rc=%Rrc, cbWritten=%RU32\n", pDrv->uLUN, rc2, cbWritten));
1035 }
1036
1037 LogFlowFunc(("\tcbToRead=%RU32, cbToWrite=%RU32, cbLeft=%RU32\n",
1038 cbToRead, cbToWrite, cbToWrite - cbWrittenTotal));
1039
1040 Assert(cbToWrite >= cbToRead);
1041 cbToWrite -= cbToRead;
1042 addr += cbToRead;
1043 cbWrittenTotal += cbToRead;
1044 }
1045
1046 pRegs->bd.addr = addr;
1047
1048 if (RT_SUCCESS(rc))
1049 {
1050 if (!cbToWrite) /* All data written? */
1051 {
1052 if (cbToRead < 4)
1053 {
1054 AssertMsgFailed(("Unable to save last written sample, cbToRead < 4 (is %RU32)\n", cbToRead));
1055 pThis->last_samp = 0;
1056 }
1057 else
1058 pThis->last_samp = *(uint32_t *)&pThis->pvReadWriteBuf[cbToRead - 4];
1059 }
1060
1061 if (pcbWritten)
1062 *pcbWritten = cbWrittenTotal;
1063 }
1064
1065 LogFlowFunc(("cbWrittenTotal=%RU32, rc=%Rrc\n", cbWrittenTotal, rc));
1066 return rc;
1067}
1068
1069static void ichac97WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
1070{
1071 if (!(pThis->bup_flag & BUP_SET))
1072 {
1073 if (pThis->bup_flag & BUP_LAST)
1074 {
1075 unsigned int i;
1076 uint32_t *p = (uint32_t*)pThis->silence;
1077 for (i = 0; i < sizeof(pThis->silence) / 4; i++)
1078 *p++ = pThis->last_samp;
1079 }
1080 else
1081 RT_ZERO(pThis->silence);
1082
1083 pThis->bup_flag |= BUP_SET;
1084 }
1085
1086 while (cbElapsed)
1087 {
1088 uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
1089 uint32_t cbWrittenToStream;
1090 int rc2;
1091
1092 PAC97DRIVER pDrv;
1093 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
1094 {
1095 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
1096 {
1097 rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
1098 pThis->silence, cbToWrite, &cbWrittenToStream);
1099 if (RT_SUCCESS(rc2))
1100 {
1101 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
1102 LogFlowFunc(("\tLUN#%RU8: Warning: Only written %RU32 / %RU32 bytes, expect lags\n",
1103 pDrv->uLUN, cbWrittenToStream, cbToWrite));
1104 }
1105 }
1106 else /* Stream disabled, not fatal. */
1107 {
1108 cbWrittenToStream = 0;
1109 rc2 = VERR_NOT_AVAILABLE;
1110 /* Keep going. */
1111 }
1112 }
1113
1114 /* Always report all data as being written;
1115 * backends who were not able to catch up have to deal with it themselves. */
1116 Assert(cbElapsed >= cbToWrite);
1117 cbElapsed -= cbToWrite;
1118 }
1119}
1120
1121static int ichac97ReadAudio(PAC97STATE pThis, PAC97STREAM pStrmSt, uint32_t cbMax, uint32_t *pcbRead)
1122{
1123 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1124 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1125 AssertReturn(cbMax, VERR_INVALID_PARAMETER);
1126 /* pcbRead is optional. */
1127
1128 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
1129 PAC97BMREGS pRegs = &pStrmSt->Regs;
1130
1131 /* Select audio sink to process. */
1132 AssertMsg(pStrmSt->u8Strm != PO_INDEX, ("Can't read from output\n"));
1133 PAUDMIXSINK pSink = pStrmSt->u8Strm == MC_INDEX ? pThis->pSinkMicIn : pThis->pSinkLineIn;
1134 AssertPtr(pSink);
1135
1136 uint32_t cbRead = 0;
1137
1138 uint32_t cbMixBuf = cbMax;
1139 uint32_t cbToRead = RT_MIN((uint32_t)(pRegs->picb << 1), cbMixBuf);
1140
1141 if (!cbToRead)
1142 {
1143 if (pcbRead)
1144 *pcbRead = 0;
1145 return VINF_EOF;
1146 }
1147
1148 int rc;
1149
1150 uint8_t *pvMixBuf = (uint8_t *)RTMemAlloc(cbMixBuf);
1151 if (pvMixBuf)
1152 {
1153 rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pvMixBuf, cbToRead, &cbRead);
1154 if ( RT_SUCCESS(rc)
1155 && cbRead)
1156 {
1157 PDMDevHlpPCIPhysWrite(pDevIns, pRegs->bd.addr, pvMixBuf, cbRead);
1158 pRegs->bd.addr += cbRead;
1159 }
1160
1161 RTMemFree(pvMixBuf);
1162 }
1163 else
1164 rc = VERR_NO_MEMORY;
1165
1166 if (RT_SUCCESS(rc))
1167 {
1168 if (pcbRead)
1169 *pcbRead = cbRead;
1170 }
1171
1172 return rc;
1173}
1174
1175#ifndef VBOX_WITH_AUDIO_CALLBACKS
1176
1177static DECLCALLBACK(void) ichac97Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1178{
1179 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
1180 AssertPtrReturnVoid(pThis);
1181
1182 STAM_PROFILE_START(&pThis->StatTimer, a);
1183
1184 int rc = VINF_SUCCESS;
1185
1186 uint32_t cbInMax = 0;
1187 uint32_t cbOutMin = UINT32_MAX;
1188
1189 PAC97DRIVER pDrv;
1190
1191 uint32_t cbIn, cbOut;
1192
1193 uint64_t uTicksNow = PDMDevHlpTMTimeVirtGet(pDevIns);
1194 uint64_t uTicksElapsed = uTicksNow - pThis->uTimerTS;
1195 uint64_t uTicksPerSec = PDMDevHlpTMTimeVirtGetFreq(pDevIns);
1196
1197 pThis->uTimerTS = uTicksNow;
1198
1199 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
1200 {
1201 cbIn = cbOut = 0;
1202 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
1203 &cbIn, &cbOut, NULL /* cSamplesLive */);
1204 if (RT_SUCCESS(rc))
1205 rc = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, NULL /* cSamplesPlayed */);
1206
1207#ifdef DEBUG_TIMER
1208 LogFlowFunc(("LUN#%RU8: rc=%Rrc, cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, rc, cbIn, cbOut));
1209#endif
1210 const bool fIsActiveOut = pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut);
1211
1212 /* If we there was an error handling (available) output or there simply is no output available,
1213 * then calculate the minimum data rate which must be processed by the device emulation in order
1214 * to function correctly.
1215 *
1216 * This is not the optimal solution, but as we have to deal with this on a timer-based approach
1217 * (until we have the audio callbacks) we need to have device' DMA engines running. */
1218 if ( RT_FAILURE(rc)
1219 || !fIsActiveOut)
1220 {
1221 uint32_t cSamplesMin = (int)((2 * uTicksElapsed * pDrv->Out.pStrmOut->Props.uHz + uTicksPerSec) / uTicksPerSec / 2);
1222 uint32_t cbSamplesMin = AUDIOMIXBUF_S2B(&pDrv->Out.pStrmOut->MixBuf, cSamplesMin);
1223
1224#ifdef DEBUG_TIMER
1225 LogFlowFunc(("\trc=%Rrc, cSamplesMin=%RU32, cbSamplesMin=%RU32\n", rc, cSamplesMin, cbSamplesMin));
1226#endif
1227 cbOut = RT_MAX(cbOut, cbSamplesMin);
1228 }
1229
1230 cbOutMin = RT_MIN(cbOutMin, cbOut);
1231 cbInMax = RT_MAX(cbInMax, cbIn);
1232 }
1233
1234#ifdef DEBUG_TIMER
1235 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
1236#endif
1237
1238 if (cbOutMin == UINT32_MAX)
1239 cbOutMin = 0;
1240
1241 /*
1242 * Playback.
1243 */
1244 if (cbOutMin)
1245 {
1246 Assert(cbOutMin != UINT32_MAX);
1247 ichac97TransferAudio(pThis, PO_INDEX, cbOutMin); /** @todo Add rc! */
1248 }
1249
1250 /*
1251 * Recording.
1252 */
1253 if (cbInMax)
1254 ichac97TransferAudio(pThis, PI_INDEX, cbInMax); /** @todo Add rc! */
1255
1256 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTimerTicks);
1257
1258 STAM_PROFILE_STOP(&pThis->StatTimer, a);
1259}
1260
1261#endif
1262
1263static int ichac97TransferAudio(PAC97STATE pThis, AC97SOUNDSOURCE enmSrc, uint32_t cbElapsed)
1264{
1265 LogFlowFunc(("pThis=%p, enmSrc=%RU32, cbElapsed=%RU32\n", pThis, enmSrc, cbElapsed));
1266
1267 PAC97STREAM pStrmSt;
1268 switch (enmSrc)
1269 {
1270 case PI_INDEX: pStrmSt = &pThis->StrmStLineIn; break;
1271 case MC_INDEX: pStrmSt = &pThis->StrmStMicIn; break;
1272 case PO_INDEX: pStrmSt = &pThis->StrmStOut; break;
1273 default:
1274 {
1275 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
1276 return VERR_NOT_SUPPORTED;
1277 }
1278 }
1279
1280 PAC97BMREGS pRegs = &pStrmSt->Regs;
1281
1282 if (pRegs->sr & SR_DCH) /* Controller halted? */
1283 {
1284 if (pRegs->cr & CR_RPBM)
1285 {
1286 switch (enmSrc)
1287 {
1288 case PO_INDEX:
1289 ichac97WriteBUP(pThis, cbElapsed);
1290 break;
1291
1292 default:
1293 break;
1294 }
1295 }
1296
1297 return VINF_SUCCESS;
1298 }
1299
1300 int rc = VINF_SUCCESS;
1301 uint32_t cbWrittenTotal = 0;
1302
1303 while (cbElapsed >> 1)
1304 {
1305 if (!pRegs->bd_valid)
1306 {
1307 LogFlowFunc(("Invalid buffer descriptor, fetching next one ...\n"));
1308 ichac97StreamFetchBDLE(pThis, pStrmSt);
1309 }
1310
1311 if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
1312 {
1313 LogFlowFunc(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
1314 pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
1315 if (pRegs->civ == pRegs->lvi)
1316 {
1317 pRegs->sr |= SR_DCH; /* CELV? */
1318 pThis->bup_flag = 0;
1319
1320 rc = VINF_EOF;
1321 break;
1322 }
1323
1324 pRegs->sr &= ~SR_CELV;
1325 pRegs->civ = pRegs->piv;
1326 pRegs->piv = (pRegs->piv + 1) % 32;
1327
1328 ichac97StreamFetchBDLE(pThis, pStrmSt);
1329 continue;
1330 }
1331
1332 uint32_t cbTransferred;
1333 switch (enmSrc)
1334 {
1335 case PO_INDEX:
1336 {
1337 rc = ichac97WriteAudio(pThis, pStrmSt, cbElapsed, &cbTransferred);
1338 if ( RT_SUCCESS(rc)
1339 && cbTransferred)
1340 {
1341 cbWrittenTotal += cbTransferred;
1342 Assert(cbElapsed >= cbTransferred);
1343 cbElapsed -= cbTransferred;
1344 Assert((cbTransferred & 1) == 0); /* Else the following shift won't work */
1345 pRegs->picb -= (cbTransferred >> 1);
1346 }
1347 break;
1348 }
1349
1350 case PI_INDEX:
1351 case MC_INDEX:
1352 {
1353 rc = ichac97ReadAudio(pThis, pStrmSt, cbElapsed, &cbTransferred);
1354 if ( RT_SUCCESS(rc)
1355 && cbTransferred)
1356 {
1357 Assert(cbElapsed >= cbTransferred);
1358 cbElapsed -= cbTransferred;
1359 Assert((cbTransferred & 1) == 0); /* Else the following shift won't work */
1360 pRegs->picb -= (cbTransferred >> 1);
1361 }
1362 break;
1363 }
1364
1365 default:
1366 AssertMsgFailed(("Source %RU32 not supported\n", enmSrc));
1367 rc = VERR_NOT_SUPPORTED;
1368 break;
1369 }
1370
1371 LogFlowFunc(("pReg->picb=%#x, cbWrittenTotal=%RU32\n", pRegs->picb, cbWrittenTotal));
1372
1373 if (!pRegs->picb)
1374 {
1375 uint32_t new_sr = pRegs->sr & ~SR_CELV;
1376
1377 if (pRegs->bd.ctl_len & BD_IOC)
1378 {
1379 new_sr |= SR_BCIS;
1380 }
1381
1382 if (pRegs->civ == pRegs->lvi)
1383 {
1384 LogFlowFunc(("Underrun civ (%RU8) == lvi (%RU8)\n", pRegs->civ, pRegs->lvi));
1385 new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
1386 pThis->bup_flag = (pRegs->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1387
1388 rc = VINF_EOF;
1389 }
1390 else
1391 {
1392 pRegs->civ = pRegs->piv;
1393 pRegs->piv = (pRegs->piv + 1) % 32;
1394 ichac97StreamFetchBDLE(pThis, pStrmSt);
1395 }
1396
1397 ichac97StreamUpdateStatus(pThis, pStrmSt, new_sr);
1398 }
1399
1400 if ( RT_FAILURE(rc)
1401 || rc == VINF_EOF) /* All data processed? */
1402 {
1403 break;
1404 }
1405 }
1406
1407 LogFlowFuncLeaveRC(rc);
1408 return rc;
1409}
1410
1411/**
1412 * @callback_method_impl{FNIOMIOPORTIN}
1413 */
1414static DECLCALLBACK(int) ichac97IOPortNABMRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
1415 uint32_t *pu32Val, unsigned cbVal)
1416{
1417 PAC97STATE pThis = (PAC97STATE)pvUser;
1418
1419 /* Get the index of the NABMBAR port. */
1420 const uint32_t uPortIdx = Port - pThis->IOPortBase[1];
1421
1422 PAC97STREAM pStrmSt = ichac97GetStreamFromID(pThis, AC97_PORT2IDX(uPortIdx));
1423 PAC97BMREGS pRegs = pStrmSt ? &pStrmSt->Regs : NULL;
1424
1425 switch (cbVal)
1426 {
1427 case 1:
1428 {
1429 switch (uPortIdx)
1430 {
1431 case CAS:
1432 /* Codec Access Semaphore Register */
1433 LogFlowFunc(("CAS %d\n", pThis->cas));
1434 *pu32Val = pThis->cas;
1435 pThis->cas = 1;
1436 break;
1437 case PI_CIV:
1438 case PO_CIV:
1439 case MC_CIV:
1440 /* Current Index Value Register */
1441 *pu32Val = pRegs->civ;
1442 LogFlowFunc(("CIV[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1443 break;
1444 case PI_LVI:
1445 case PO_LVI:
1446 case MC_LVI:
1447 /* Last Valid Index Register */
1448 *pu32Val = pRegs->lvi;
1449 LogFlowFunc(("LVI[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1450 break;
1451 case PI_PIV:
1452 case PO_PIV:
1453 case MC_PIV:
1454 /* Prefetched Index Value Register */
1455 *pu32Val = pRegs->piv;
1456 LogFlowFunc(("PIV[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1457 break;
1458 case PI_CR:
1459 case PO_CR:
1460 case MC_CR:
1461 /* Control Register */
1462 *pu32Val = pRegs->cr;
1463 LogFlowFunc(("CR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1464 break;
1465 case PI_SR:
1466 case PO_SR:
1467 case MC_SR:
1468 /* Status Register (lower part) */
1469 *pu32Val = pRegs->sr & 0xff; /** @todo r=andy Use RT_LO_U8. */
1470 LogFlowFunc(("SRb[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1471 break;
1472 default:
1473 *pu32Val = UINT32_MAX;
1474 LogFlowFunc(("U nabm readb %#x -> %#x\n", Port, *pu32Val));
1475 break;
1476 }
1477 break;
1478 }
1479
1480 case 2:
1481 {
1482 switch (uPortIdx)
1483 {
1484 case PI_SR:
1485 case PO_SR:
1486 case MC_SR:
1487 /* Status Register */
1488 *pu32Val = pRegs->sr;
1489 LogFlowFunc(("SR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1490 break;
1491 case PI_PICB:
1492 case PO_PICB:
1493 case MC_PICB:
1494 /* Position in Current Buffer Register */
1495 *pu32Val = pRegs->picb;
1496 LogFlowFunc(("PICB[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1497 break;
1498 default:
1499 *pu32Val = UINT32_MAX;
1500 LogFlowFunc(("U nabm readw %#x -> %#x\n", Port, *pu32Val));
1501 break;
1502 }
1503 break;
1504 }
1505
1506 case 4:
1507 {
1508 switch (uPortIdx)
1509 {
1510 case PI_BDBAR:
1511 case PO_BDBAR:
1512 case MC_BDBAR:
1513 /* Buffer Descriptor Base Address Register */
1514 *pu32Val = pRegs->bdbar;
1515 LogFlowFunc(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1516 break;
1517 case PI_CIV:
1518 case PO_CIV:
1519 case MC_CIV:
1520 /* 32-bit access: Current Index Value Register +
1521 * Last Valid Index Register +
1522 * Status Register */
1523 *pu32Val = pRegs->civ | (pRegs->lvi << 8) | (pRegs->sr << 16); /** @todo r=andy Use RT_MAKE_U32_FROM_U8. */
1524 LogFlowFunc(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
1525 AC97_PORT2IDX(uPortIdx), pRegs->civ, pRegs->lvi, pRegs->sr));
1526 break;
1527 case PI_PICB:
1528 case PO_PICB:
1529 case MC_PICB:
1530 /* 32-bit access: Position in Current Buffer Register +
1531 * Prefetched Index Value Register +
1532 * Control Register */
1533 *pu32Val = pRegs->picb | (pRegs->piv << 16) | (pRegs->cr << 24); /** @todo r=andy Use RT_MAKE_U32_FROM_U8. */
1534 LogFlowFunc(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
1535 AC97_PORT2IDX(uPortIdx), *pu32Val, pRegs->picb, pRegs->piv, pRegs->cr));
1536 break;
1537 case GLOB_CNT:
1538 /* Global Control */
1539 *pu32Val = pThis->glob_cnt;
1540 LogFlowFunc(("glob_cnt -> %#x\n", *pu32Val));
1541 break;
1542 case GLOB_STA:
1543 /* Global Status */
1544 *pu32Val = pThis->glob_sta | GS_S0CR;
1545 LogFlowFunc(("glob_sta -> %#x\n", *pu32Val));
1546 break;
1547 default:
1548 *pu32Val = UINT32_MAX;
1549 LogFlowFunc(("U nabm readl %#x -> %#x\n", Port, *pu32Val));
1550 break;
1551 }
1552 break;
1553 }
1554
1555 default:
1556 return VERR_IOM_IOPORT_UNUSED;
1557 }
1558 return VINF_SUCCESS;
1559}
1560
1561/**
1562 * @callback_method_impl{FNIOMIOPORTOUT}
1563 */
1564static DECLCALLBACK(int) ichac97IOPortNABMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
1565 uint32_t u32Val, unsigned cbVal)
1566{
1567 PAC97STATE pThis = (PAC97STATE)pvUser;
1568
1569 /* Get the index of the NABMBAR register. */
1570 const uint32_t uPortIdx = Port - pThis->IOPortBase[1];
1571
1572 PAC97STREAM pStrmSt = ichac97GetStreamFromID(pThis, AC97_PORT2IDX(uPortIdx));
1573 PAC97BMREGS pRegs = pStrmSt ? &pStrmSt->Regs : NULL;
1574
1575 switch (cbVal)
1576 {
1577 case 1:
1578 {
1579 switch (uPortIdx)
1580 {
1581 case PI_LVI:
1582 case PO_LVI:
1583 case MC_LVI:
1584 /* Last Valid Index */
1585 if ((pRegs->cr & CR_RPBM) && (pRegs->sr & SR_DCH))
1586 {
1587 pRegs->sr &= ~(SR_DCH | SR_CELV);
1588 pRegs->civ = pRegs->piv;
1589 pRegs->piv = (pRegs->piv + 1) % 32;
1590
1591 ichac97StreamFetchBDLE(pThis, pStrmSt);
1592 }
1593 pRegs->lvi = u32Val % 32;
1594 LogFlowFunc(("LVI[%d] <- %#x\n", AC97_PORT2IDX(uPortIdx), u32Val));
1595 break;
1596 case PI_CR:
1597 case PO_CR:
1598 case MC_CR:
1599 {
1600 /* Control Register */
1601 if (u32Val & CR_RR) /* Busmaster reset */
1602 {
1603 ichac97StreamResetBMRegs(pThis, pStrmSt);
1604 }
1605 else
1606 {
1607 pRegs->cr = u32Val & CR_VALID_MASK;
1608 if (!(pRegs->cr & CR_RPBM))
1609 {
1610 ichac97StreamSetActive(pThis, pStrmSt, false /* fActive */);
1611 pRegs->sr |= SR_DCH;
1612 }
1613 else
1614 {
1615 pRegs->civ = pRegs->piv;
1616 pRegs->piv = (pRegs->piv + 1) % 32;
1617
1618 ichac97StreamFetchBDLE(pThis, pStrmSt);
1619
1620 pRegs->sr &= ~SR_DCH;
1621 ichac97StreamSetActive(pThis, pStrmSt, true /* fActive */);
1622 }
1623 }
1624 LogFlowFunc(("CR[%d] <- %#x (cr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->cr));
1625 break;
1626 }
1627 case PI_SR:
1628 case PO_SR:
1629 case MC_SR:
1630 /* Status Register */
1631 pRegs->sr |= u32Val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
1632 ichac97StreamUpdateStatus(pThis, pStrmSt, pRegs->sr & ~(u32Val & SR_WCLEAR_MASK));
1633 LogFlowFunc(("SR[%d] <- %#x (sr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->sr));
1634 break;
1635 default:
1636 LogFlowFunc(("U nabm writeb %#x <- %#x\n", Port, u32Val));
1637 break;
1638 }
1639 break;
1640 }
1641
1642 case 2:
1643 {
1644 switch (uPortIdx)
1645 {
1646 case PI_SR:
1647 case PO_SR:
1648 case MC_SR:
1649 /* Status Register */
1650 pRegs->sr |= u32Val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
1651 ichac97StreamUpdateStatus(pThis, pStrmSt, pRegs->sr & ~(u32Val & SR_WCLEAR_MASK));
1652 LogFlowFunc(("SR[%d] <- %#x (sr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->sr));
1653 break;
1654 default:
1655 LogFlowFunc(("U nabm writew %#x <- %#x\n", Port, u32Val));
1656 break;
1657 }
1658 break;
1659 }
1660
1661 case 4:
1662 {
1663 switch (uPortIdx)
1664 {
1665 case PI_BDBAR:
1666 case PO_BDBAR:
1667 case MC_BDBAR:
1668 /* Buffer Descriptor list Base Address Register */
1669 pRegs->bdbar = u32Val & ~3;
1670 LogFlowFunc(("BDBAR[%d] <- %#x (bdbar %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->bdbar));
1671 break;
1672 case GLOB_CNT:
1673 /* Global Control */
1674 if (u32Val & GC_WR)
1675 ichac97WarmReset(pThis);
1676 if (u32Val & GC_CR)
1677 ichac97ColdReset(pThis);
1678 if (!(u32Val & (GC_WR | GC_CR)))
1679 pThis->glob_cnt = u32Val & GC_VALID_MASK;
1680 LogFlowFunc(("glob_cnt <- %#x (glob_cnt %#x)\n", u32Val, pThis->glob_cnt));
1681 break;
1682 case GLOB_STA:
1683 /* Global Status */
1684 pThis->glob_sta &= ~(u32Val & GS_WCLEAR_MASK);
1685 pThis->glob_sta |= (u32Val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
1686 LogFlowFunc(("glob_sta <- %#x (glob_sta %#x)\n", u32Val, pThis->glob_sta));
1687 break;
1688 default:
1689 LogFlowFunc(("U nabm writel %#x <- %#x\n", Port, u32Val));
1690 break;
1691 }
1692 break;
1693 }
1694
1695 default:
1696 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cbVal, u32Val));
1697 break;
1698 }
1699 return VINF_SUCCESS;
1700}
1701
1702/**
1703 * @callback_method_impl{FNIOMIOPORTIN}
1704 */
1705static DECLCALLBACK(int) ichac97IOPortNAMRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32Val, unsigned cbVal)
1706{
1707 PAC97STATE pThis = (PAC97STATE)pvUser;
1708
1709 switch (cbVal)
1710 {
1711 case 1:
1712 {
1713 LogFlowFunc(("U nam readb %#x\n", Port));
1714 pThis->cas = 0;
1715 *pu32Val = UINT32_MAX;
1716 break;
1717 }
1718
1719 case 2:
1720 {
1721 uint32_t index = Port - pThis->IOPortBase[0];
1722 *pu32Val = UINT32_MAX;
1723 pThis->cas = 0;
1724 switch (index)
1725 {
1726 default:
1727 *pu32Val = ichac97MixerGet(pThis, index);
1728 LogFlowFunc(("nam readw %#x -> %#x\n", Port, *pu32Val));
1729 break;
1730 }
1731 break;
1732 }
1733
1734 case 4:
1735 {
1736 LogFlowFunc(("U nam readl %#x\n", Port));
1737 pThis->cas = 0;
1738 *pu32Val = UINT32_MAX;
1739 break;
1740 }
1741
1742 default:
1743 return VERR_IOM_IOPORT_UNUSED;
1744 }
1745 return VINF_SUCCESS;
1746}
1747
1748/**
1749 * @callback_method_impl{FNIOMIOPORTOUT}
1750 */
1751static DECLCALLBACK(int) ichac97IOPortNAMWrite(PPDMDEVINS pDevIns,
1752 void *pvUser, RTIOPORT Port, uint32_t u32Val, unsigned cbVal)
1753{
1754 PAC97STATE pThis = (PAC97STATE)pvUser;
1755
1756 switch (cbVal)
1757 {
1758 case 1:
1759 {
1760 LogFlowFunc(("U nam writeb %#x <- %#x\n", Port, u32Val));
1761 pThis->cas = 0;
1762 break;
1763 }
1764
1765 case 2:
1766 {
1767 uint32_t index = Port - pThis->IOPortBase[0];
1768 pThis->cas = 0;
1769 switch (index)
1770 {
1771 case AC97_Reset:
1772 ichac97Reset(pThis->CTX_SUFF(pDevIns));
1773 break;
1774 case AC97_Powerdown_Ctrl_Stat:
1775 u32Val &= ~0xf;
1776 u32Val |= ichac97MixerGet(pThis, index) & 0xf;
1777 ichac97MixerSet(pThis, index, u32Val);
1778 break;
1779 case AC97_Master_Volume_Mute:
1780 if (pThis->uCodecModel == Codec_AD1980)
1781 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AD_MISC_LOSEL)
1782 break; /* Register controls surround (rear), do nothing. */
1783 ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_VOLUME, u32Val);
1784 break;
1785 case AC97_Headphone_Volume_Mute:
1786 if (pThis->uCodecModel == Codec_AD1980)
1787 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AD_MISC_HPSEL)
1788 /* Register controls PCM (front) outputs. */
1789 ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_VOLUME, u32Val);
1790 break;
1791 case AC97_PCM_Out_Volume_Mute:
1792 ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_PCM, u32Val);
1793 break;
1794 case AC97_Line_In_Volume_Mute:
1795 ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_LINE_IN, u32Val);
1796 break;
1797 case AC97_Record_Select:
1798 ichac97RecordSelect(pThis, u32Val);
1799 break;
1800 case AC97_Vendor_ID1:
1801 case AC97_Vendor_ID2:
1802 LogFlowFunc(("Attempt to write vendor ID to %#x\n", u32Val));
1803 break;
1804 case AC97_Extended_Audio_ID:
1805 LogFlowFunc(("Attempt to write extended audio ID to %#x\n", u32Val));
1806 break;
1807 case AC97_Extended_Audio_Ctrl_Stat:
1808 if (!(u32Val & EACS_VRA))
1809 {
1810 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 48000);
1811 ichac97StreamReInit(pThis, &pThis->StrmStOut);
1812
1813 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 48000);
1814 ichac97StreamReInit(pThis, &pThis->StrmStLineIn);
1815 }
1816 if (!(u32Val & EACS_VRM))
1817 {
1818 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 48000);
1819 ichac97StreamReInit(pThis, &pThis->StrmStMicIn);
1820 }
1821 LogFlowFunc(("Setting extended audio control to %#x\n", u32Val));
1822 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32Val);
1823 break;
1824 case AC97_PCM_Front_DAC_Rate:
1825 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)
1826 {
1827 ichac97MixerSet(pThis, index, u32Val);
1828 LogFlowFunc(("Set front DAC rate to %RU32\n", u32Val));
1829 ichac97StreamReInit(pThis, &pThis->StrmStOut);
1830 }
1831 else
1832 LogFlowFunc(("Attempt to set front DAC rate to %RU32, but VRA is not set\n", u32Val));
1833 break;
1834 case AC97_MIC_ADC_Rate:
1835 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM)
1836 {
1837 ichac97MixerSet(pThis, index, u32Val);
1838 LogFlowFunc(("Set MIC ADC rate to %RU32\n", u32Val));
1839 ichac97StreamReInit(pThis, &pThis->StrmStMicIn);
1840 }
1841 else
1842 LogFlowFunc(("Attempt to set MIC ADC rate to %RU32, but VRM is not set\n", u32Val));
1843 break;
1844 case AC97_PCM_LR_ADC_Rate:
1845 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)
1846 {
1847 ichac97MixerSet(pThis, index, u32Val);
1848 LogFlowFunc(("Set front LR ADC rate to %RU32\n", u32Val));
1849 ichac97StreamReInit(pThis, &pThis->StrmStLineIn);
1850 }
1851 else
1852 LogFlowFunc(("Attempt to set LR ADC rate to %RU32, but VRA is not set\n", u32Val));
1853 break;
1854 default:
1855 LogFlowFunc(("U nam writew %#x <- %#x\n", Port, u32Val));
1856 ichac97MixerSet(pThis, index, u32Val);
1857 break;
1858 }
1859 break;
1860 }
1861
1862 case 4:
1863 {
1864 LogFlowFunc(("U nam writel %#x <- %#x\n", Port, u32Val));
1865 pThis->cas = 0;
1866 break;
1867 }
1868
1869 default:
1870 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cbVal, u32Val));
1871 break;
1872 }
1873
1874 return VINF_SUCCESS;
1875}
1876
1877
1878/**
1879 * @callback_method_impl{FNPCIIOREGIONMAP}
1880 */
1881static DECLCALLBACK(int) ichac97IOPortMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
1882 PCIADDRESSSPACE enmType)
1883{
1884 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1885 PAC97STATE pThis = RT_FROM_MEMBER(pPciDev, AC97STATE, PciDev);
1886 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1887
1888 Assert(enmType == PCI_ADDRESS_SPACE_IO);
1889 Assert(cb >= 0x20);
1890
1891 if (iRegion < 0 || iRegion > 1) /* We support 2 regions max. at the moment. */
1892 return VERR_INVALID_PARAMETER;
1893
1894 int rc;
1895 if (iRegion == 0)
1896 rc = PDMDevHlpIOPortRegister(pDevIns, Port, 256, pThis,
1897 ichac97IOPortNAMWrite, ichac97IOPortNAMRead,
1898 NULL, NULL, "ICHAC97 NAM");
1899 else
1900 rc = PDMDevHlpIOPortRegister(pDevIns, Port, 64, pThis,
1901 ichac97IOPortNABMWrite, ichac97IOPortNABMRead,
1902 NULL, NULL, "ICHAC97 NABM");
1903 if (RT_FAILURE(rc))
1904 return rc;
1905
1906 pThis->IOPortBase[iRegion] = Port;
1907 return VINF_SUCCESS;
1908}
1909
1910DECLINLINE(PAC97STREAM) ichac97GetStreamFromID(PAC97STATE pThis, uint32_t uID)
1911{
1912 switch (uID)
1913 {
1914 case PI_INDEX: return &pThis->StrmStLineIn;
1915 case MC_INDEX: return &pThis->StrmStMicIn;
1916 case PO_INDEX: return &pThis->StrmStOut;
1917 default: break;
1918 }
1919
1920 return NULL;
1921}
1922
1923#ifdef IN_RING3
1924static int ichac97SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStrmSt)
1925{
1926 PAC97BMREGS pRegs = &pStrmSt->Regs;
1927
1928 SSMR3PutU32(pSSM, pRegs->bdbar);
1929 SSMR3PutU8( pSSM, pRegs->civ);
1930 SSMR3PutU8( pSSM, pRegs->lvi);
1931 SSMR3PutU16(pSSM, pRegs->sr);
1932 SSMR3PutU16(pSSM, pRegs->picb);
1933 SSMR3PutU8( pSSM, pRegs->piv);
1934 SSMR3PutU8( pSSM, pRegs->cr);
1935 SSMR3PutS32(pSSM, pRegs->bd_valid);
1936 SSMR3PutU32(pSSM, pRegs->bd.addr);
1937 SSMR3PutU32(pSSM, pRegs->bd.ctl_len);
1938
1939 return VINF_SUCCESS;
1940}
1941
1942/**
1943 * @callback_method_impl{FNSSMDEVSAVEEXEC}
1944 */
1945static DECLCALLBACK(int) ichac97SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1946{
1947 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
1948
1949 SSMR3PutU32(pSSM, pThis->glob_cnt);
1950 SSMR3PutU32(pSSM, pThis->glob_sta);
1951 SSMR3PutU32(pSSM, pThis->cas);
1952
1953 /** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
1954 /* Note: The order the streams are saved here is critical, so don't touch. */
1955 int rc2 = ichac97SaveStream(pDevIns, pSSM, &pThis->StrmStLineIn);
1956 AssertRC(rc2);
1957 rc2 = ichac97SaveStream(pDevIns, pSSM, &pThis->StrmStOut);
1958 AssertRC(rc2);
1959 rc2 = ichac97SaveStream(pDevIns, pSSM, &pThis->StrmStMicIn);
1960 AssertRC(rc2);
1961
1962 SSMR3PutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
1963
1964 uint8_t active[LAST_INDEX];
1965
1966 PAC97DRIVER pDrv;
1967 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
1968 {
1969 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
1970 AssertPtr(pCon);
1971 active[PI_INDEX] = pCon->pfnIsActiveIn (pCon, pDrv->LineIn.pStrmIn) ? 1 : 0;
1972 active[PO_INDEX] = pCon->pfnIsActiveOut(pCon, pDrv->Out.pStrmOut) ? 1 : 0;
1973 active[MC_INDEX] = pCon->pfnIsActiveIn (pCon, pDrv->MicIn.pStrmIn) ? 1 : 0;
1974 }
1975
1976 SSMR3PutMem(pSSM, active, sizeof(active));
1977
1978 return VINF_SUCCESS;
1979}
1980
1981static int ichac97LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStrmSt)
1982{
1983 PAC97BMREGS pRegs = &pStrmSt->Regs;
1984
1985 SSMR3GetU32(pSSM, &pRegs->bdbar);
1986 SSMR3GetU8( pSSM, &pRegs->civ);
1987 SSMR3GetU8( pSSM, &pRegs->lvi);
1988 SSMR3GetU16(pSSM, &pRegs->sr);
1989 SSMR3GetU16(pSSM, &pRegs->picb);
1990 SSMR3GetU8( pSSM, &pRegs->piv);
1991 SSMR3GetU8( pSSM, &pRegs->cr);
1992 SSMR3GetS32(pSSM, &pRegs->bd_valid);
1993 SSMR3GetU32(pSSM, &pRegs->bd.addr);
1994 SSMR3GetU32(pSSM, &pRegs->bd.ctl_len);
1995
1996 return VINF_SUCCESS;
1997}
1998
1999/**
2000 * @callback_method_impl{FNSSMDEVLOADEXEC}
2001 */
2002static DECLCALLBACK(int) ichac97LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2003{
2004 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2005
2006 AssertMsgReturn (uVersion == AC97_SSM_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
2007 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2008
2009 SSMR3GetU32(pSSM, &pThis->glob_cnt);
2010 SSMR3GetU32(pSSM, &pThis->glob_sta);
2011 SSMR3GetU32(pSSM, &pThis->cas);
2012
2013 /** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
2014 /* Note: The order the streams are loaded here is critical, so don't touch. */
2015 int rc2 = ichac97LoadStream(pDevIns, pSSM, &pThis->StrmStLineIn);
2016 AssertRC(rc2);
2017 rc2 = ichac97LoadStream(pDevIns, pSSM, &pThis->StrmStOut);
2018 AssertRC(rc2);
2019 rc2 = ichac97LoadStream(pDevIns, pSSM, &pThis->StrmStMicIn);
2020 AssertRC(rc2);
2021
2022 SSMR3GetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
2023
2024 /** @todo r=andy Stream IDs are hardcoded to certain streams. */
2025 uint8_t uaStrmsActive[LAST_INDEX];
2026 SSMR3GetMem(pSSM, uaStrmsActive, sizeof(uaStrmsActive));
2027
2028 ichac97RecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
2029# define V_(a, b) ichac97MixerSetVolume(pThis, a, b, ichac97MixerGet(pThis, a))
2030 V_(AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME);
2031 V_(AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_PCM);
2032 V_(AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN);
2033# undef V_
2034 if (pThis->uCodecModel == Codec_AD1980)
2035 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AD_MISC_HPSEL)
2036 ichac97MixerSetVolume(pThis, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME,
2037 ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
2038
2039 int rc;
2040 rc = ichac97StreamInit(pThis, &pThis->StrmStLineIn, PI_INDEX);
2041 AssertRC(rc);
2042 rc = ichac97StreamInit(pThis, &pThis->StrmStMicIn, MC_INDEX);
2043 AssertRC(rc);
2044 rc = ichac97StreamInit(pThis, &pThis->StrmStOut, PO_INDEX);
2045 AssertRC(rc);
2046
2047 /** @todo r=andy Stream IDs are hardcoded to certain streams. */
2048 rc = ichac97StreamSetActive(pThis, &pThis->StrmStLineIn, RT_BOOL(uaStrmsActive[PI_INDEX]));
2049 AssertRC(rc);
2050 rc = ichac97StreamSetActive(pThis, &pThis->StrmStMicIn, RT_BOOL(uaStrmsActive[MC_INDEX]));
2051 AssertRC(rc);
2052 rc = ichac97StreamSetActive(pThis, &pThis->StrmStOut, RT_BOOL(uaStrmsActive[PO_INDEX]));
2053 AssertRC(rc);
2054
2055 pThis->bup_flag = 0;
2056 pThis->last_samp = 0;
2057
2058 return VINF_SUCCESS;
2059}
2060
2061
2062/**
2063 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2064 */
2065static DECLCALLBACK(void *) ichac97QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
2066{
2067 PAC97STATE pThis = RT_FROM_MEMBER(pInterface, AC97STATE, IBase);
2068 Assert(&pThis->IBase == pInterface);
2069
2070 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2071 return NULL;
2072}
2073
2074
2075/**
2076 * @interface_method_impl{PDMDEVREG,pfnReset}
2077 *
2078 * @remarks The original sources didn't install a reset handler, but it seems to
2079 * make sense to me so we'll do it.
2080 */
2081static DECLCALLBACK(void) ichac97Reset(PPDMDEVINS pDevIns)
2082{
2083 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2084
2085 LogFlowFuncEnter();
2086
2087 /*
2088 * Reset the device state (will need pDrv later).
2089 */
2090 ichac97StreamResetBMRegs(pThis, &pThis->StrmStLineIn);
2091 ichac97StreamResetBMRegs(pThis, &pThis->StrmStMicIn);
2092 ichac97StreamResetBMRegs(pThis, &pThis->StrmStOut);
2093
2094 /*
2095 * Reset the mixer too. The Windows XP driver seems to rely on
2096 * this. At least it wants to read the vendor id before it resets
2097 * the codec manually.
2098 */
2099 ichac97MixerReset(pThis);
2100
2101 /*
2102 * Stop any audio currently playing.
2103 */
2104 PAC97DRIVER pDrv;
2105 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
2106 {
2107 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
2108 /* Ignore rc. */
2109 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
2110 /* Ditto. */
2111 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
2112 /* Ditto. */
2113 }
2114
2115 /*
2116 * Reset all streams.
2117 */
2118 ichac97StreamReset(pThis, &pThis->StrmStLineIn);
2119 ichac97StreamReset(pThis, &pThis->StrmStMicIn);
2120 ichac97StreamReset(pThis, &pThis->StrmStOut);
2121
2122 LogRel(("AC97: Reset\n"));
2123}
2124
2125
2126/**
2127 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2128 */
2129static DECLCALLBACK(int) ichac97Destruct(PPDMDEVINS pDevIns)
2130{
2131 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2132
2133 LogFlowFuncEnter();
2134
2135 PAC97DRIVER pDrv;
2136 while (!RTListIsEmpty(&pThis->lstDrv))
2137 {
2138 pDrv = RTListGetFirst(&pThis->lstDrv, AC97DRIVER, Node);
2139
2140 RTListNodeRemove(&pDrv->Node);
2141 RTMemFree(pDrv);
2142 }
2143
2144 if (pThis->pMixer)
2145 {
2146 AudioMixerDestroy(pThis->pMixer);
2147 pThis->pMixer = NULL;
2148 }
2149
2150 if (pThis->pvReadWriteBuf)
2151 {
2152 RTMemFree(pThis->pvReadWriteBuf);
2153 pThis->pvReadWriteBuf = NULL;
2154 pThis->cbReadWriteBuf = 0;
2155 }
2156
2157 LogFlowFuncLeave();
2158 return VINF_SUCCESS;
2159}
2160
2161
2162/**
2163 * Attach command.
2164 *
2165 * This is called to let the device attach to a driver for a specified LUN
2166 * during runtime. This is not called during VM construction, the device
2167 * constructor have to attach to all the available drivers.
2168 *
2169 * @returns VBox status code.
2170 * @param pDevIns The device instance.
2171 * @param uLUN The logical unit which is being detached.
2172 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
2173 */
2174static DECLCALLBACK(int) ichac97Attach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
2175{
2176 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2177
2178 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
2179 ("AC'97 device does not support hotplugging\n"),
2180 VERR_INVALID_PARAMETER);
2181
2182 /*
2183 * Attach driver.
2184 */
2185 char *pszDesc = NULL;
2186 if (RTStrAPrintf(&pszDesc, "Audio driver port (AC'97) for LUN #%u", uLUN) <= 0)
2187 AssertMsgReturn(pszDesc,
2188 ("Not enough memory for AC'97 driver port description of LUN #%u\n", uLUN),
2189 VERR_NO_MEMORY);
2190
2191 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
2192 &pThis->IBase, &pThis->pDrvBase, pszDesc);
2193 if (RT_SUCCESS(rc))
2194 {
2195 PAC97DRIVER pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
2196 if (pDrv)
2197 {
2198 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
2199 AssertMsg(pDrv->pConnector != NULL,
2200 ("Configuration error: LUN #%u has no host audio interface, rc=%Rrc\n",
2201 uLUN, rc));
2202 pDrv->pAC97State = pThis;
2203 pDrv->uLUN = uLUN;
2204
2205 /*
2206 * For now we always set the driver at LUN 0 as our primary
2207 * host backend. This might change in the future.
2208 */
2209 if (pDrv->uLUN == 0)
2210 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
2211
2212 LogFunc(("LUN#%RU8: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
2213
2214 /* Attach to driver list. */
2215 RTListAppend(&pThis->lstDrv, &pDrv->Node);
2216 }
2217 else
2218 rc = VERR_NO_MEMORY;
2219 }
2220 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2221 {
2222 LogFunc(("No attached driver for LUN #%u\n", uLUN));
2223 }
2224 else if (RT_FAILURE(rc))
2225 AssertMsgFailed(("Failed to attach AC'97 LUN #%u (\"%s\"), rc=%Rrc\n",
2226 uLUN, pszDesc, rc));
2227
2228 RTStrFree(pszDesc);
2229
2230 LogFunc(("iLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
2231 return rc;
2232}
2233
2234
2235/**
2236 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2237 */
2238static DECLCALLBACK(int) ichac97Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2239{
2240 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2241
2242 /* NB: This must be done *before* any possible failure (and running the destructor). */
2243 RTListInit(&pThis->lstDrv);
2244
2245 Assert(iInstance == 0);
2246 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2247
2248 /*
2249 * Validations.
2250 */
2251 if (!CFGMR3AreValuesValid(pCfg, "Codec\0"))
2252 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2253 N_("Invalid configuration for the AC'97 device"));
2254
2255 /*
2256 * Determine the codec model.
2257 */
2258 char szCodec[20];
2259 int rc = CFGMR3QueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
2260 if (RT_FAILURE(rc))
2261 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2262 N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
2263
2264 /*
2265 * The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
2266 * in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
2267 * 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
2268 */
2269 bool fChipAD1980 = false;
2270 if (!strcmp(szCodec, "STAC9700"))
2271 pThis->uCodecModel = Codec_STAC9700;
2272 else if (!strcmp(szCodec, "AD1980"))
2273 pThis->uCodecModel = Codec_AD1980;
2274 else if (!strcmp(szCodec, "AD1981B"))
2275 pThis->uCodecModel = Codec_AD1981B;
2276 else
2277 {
2278 return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
2279 N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"),
2280 szCodec);
2281 }
2282
2283 /*
2284 * Initialize data (most of it anyway).
2285 */
2286 pThis->pDevInsR3 = pDevIns;
2287 /* IBase */
2288 pThis->IBase.pfnQueryInterface = ichac97QueryInterface;
2289
2290 /* PCI Device (the assertions will be removed later) */
2291 PCIDevSetVendorId (&pThis->PciDev, 0x8086); /* 00 ro - intel. */ Assert(pThis->PciDev.config[0x00] == 0x86); Assert(pThis->PciDev.config[0x01] == 0x80);
2292 PCIDevSetDeviceId (&pThis->PciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pThis->PciDev.config[0x02] == 0x15); Assert(pThis->PciDev.config[0x03] == 0x24);
2293 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pThis->PciDev.config[0x04] == 0x00); Assert(pThis->PciDev.config[0x05] == 0x00);
2294 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pThis->PciDev.config[0x06] == 0x80); Assert(pThis->PciDev.config[0x07] == 0x02);
2295 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */ Assert(pThis->PciDev.config[0x08] == 0x01);
2296 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */ Assert(pThis->PciDev.config[0x09] == 0x00);
2297 PCIDevSetClassSub (&pThis->PciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pThis->PciDev.config[0x0a] == 0x01);
2298 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */ Assert(pThis->PciDev.config[0x0b] == 0x04);
2299 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */ Assert(pThis->PciDev.config[0x0e] == 0x00);
2300 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - nambar - native audio mixer base. */
2301 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pThis->PciDev.config[0x10] == 0x01); Assert(pThis->PciDev.config[0x11] == 0x00); Assert(pThis->PciDev.config[0x12] == 0x00); Assert(pThis->PciDev.config[0x13] == 0x00);
2302 PCIDevSetBaseAddress (&pThis->PciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
2303 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pThis->PciDev.config[0x14] == 0x01); Assert(pThis->PciDev.config[0x15] == 0x00); Assert(pThis->PciDev.config[0x16] == 0x00); Assert(pThis->PciDev.config[0x17] == 0x00);
2304 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */ Assert(pThis->PciDev.config[0x3c] == 0x00);
2305 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */ Assert(pThis->PciDev.config[0x3d] == 0x01);
2306
2307 if (pThis->uCodecModel == Codec_AD1980)
2308 {
2309 PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x1028); /* 2c ro - Dell.) */
2310 PCIDevSetSubSystemId (&pThis->PciDev, 0x0177); /* 2e ro. */
2311 }
2312 else if (pThis->uCodecModel == Codec_AD1981B)
2313 {
2314 PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x1028); /* 2c ro - Dell.) */
2315 PCIDevSetSubSystemId (&pThis->PciDev, 0x01ad); /* 2e ro. */
2316 }
2317 else
2318 {
2319 PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x8086); /* 2c ro - Intel.) */
2320 PCIDevSetSubSystemId (&pThis->PciDev, 0x0000); /* 2e ro. */
2321 }
2322
2323 /*
2324 * Register the PCI device, it's I/O regions, the timer and the
2325 * saved state item.
2326 */
2327 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
2328 if (RT_FAILURE(rc))
2329 return rc;
2330
2331 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 256, PCI_ADDRESS_SPACE_IO, ichac97IOPortMap);
2332 if (RT_FAILURE(rc))
2333 return rc;
2334
2335 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 64, PCI_ADDRESS_SPACE_IO, ichac97IOPortMap);
2336 if (RT_FAILURE(rc))
2337 return rc;
2338
2339 rc = PDMDevHlpSSMRegister(pDevIns, AC97_SSM_VERSION, sizeof(*pThis), ichac97SaveExec, ichac97LoadExec);
2340 if (RT_FAILURE(rc))
2341 return rc;
2342
2343 /*
2344 * Attach driver.
2345 */
2346 uint8_t uLUN;
2347 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
2348 {
2349 LogFunc(("Trying to attach driver for LUN #%RU8 ...\n", uLUN));
2350 rc = ichac97Attach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
2351 if (RT_FAILURE(rc))
2352 {
2353 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2354 rc = VINF_SUCCESS;
2355 break;
2356 }
2357
2358 uLUN++;
2359 }
2360
2361 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
2362
2363 if (RT_SUCCESS(rc))
2364 {
2365 rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThis->pMixer);
2366 if (RT_SUCCESS(rc))
2367 {
2368 /* Set a default audio format for our mixer. */
2369 PDMAUDIOSTREAMCFG streamCfg;
2370 streamCfg.uHz = 44100;
2371 streamCfg.cChannels = 2;
2372 streamCfg.enmFormat = AUD_FMT_S16;
2373 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
2374
2375 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
2376 AssertRC(rc);
2377
2378 /* Add all required audio sinks. */
2379 rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output", AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
2380 AssertRC(rc);
2381
2382 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In", AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
2383 AssertRC(rc);
2384
2385 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In", AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
2386 AssertRC(rc);
2387 }
2388 }
2389
2390 ichac97Reset(pDevIns);
2391
2392 if (RT_SUCCESS(rc))
2393 {
2394 rc = ichac97StreamInit(pThis, &pThis->StrmStLineIn, PI_INDEX);
2395 if (RT_FAILURE(rc))
2396 return rc;
2397 rc = ichac97StreamInit(pThis, &pThis->StrmStMicIn, MC_INDEX);
2398 if (RT_FAILURE(rc))
2399 return rc;
2400 rc = ichac97StreamInit(pThis, &pThis->StrmStOut, PO_INDEX);
2401 if (RT_FAILURE(rc))
2402 return rc;
2403
2404 PAC97DRIVER pDrv;
2405 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
2406 {
2407 /*
2408 * Only primary drivers are critical for the VM to run. Everything else
2409 * might not worth showing an own error message box in the GUI.
2410 */
2411 if (!(pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY))
2412 continue;
2413
2414 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
2415 AssertPtr(pCon);
2416
2417 uint8_t cFailed = 0;
2418 if (!pCon->pfnIsInputOK (pCon, pDrv->LineIn.pStrmIn))
2419 cFailed++;
2420 if (!pCon->pfnIsInputOK (pCon, pDrv->MicIn.pStrmIn))
2421 cFailed++;
2422 if (!pCon->pfnIsOutputOK(pCon, pDrv->Out.pStrmOut))
2423 cFailed++;
2424
2425 if (cFailed == 3)
2426 {
2427 LogRel(("AC97: Falling back to NULL driver (no sound audible)\n"));
2428
2429 ichac97Reset(pDevIns);
2430
2431 /* Was not able initialize *any* stream.
2432 * Select the NULL audio driver instead. */
2433 pCon->pfnInitNull(pCon);
2434
2435 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
2436 N_("No audio devices could be opened. Selecting the NULL audio backend "
2437 "with the consequence that no sound is audible"));
2438 }
2439 else if (cFailed)
2440 {
2441 if (!pDrv->pConnector->pfnIsInputOK(pDrv->pConnector, pDrv->LineIn.pStrmIn))
2442 LogRel(("AC97: WARNING: Unable to open PCM line input for LUN #%RU32!\n", pDrv->uLUN));
2443 if (!pDrv->pConnector->pfnIsInputOK(pDrv->pConnector, pDrv->MicIn.pStrmIn))
2444 LogRel(("AC97: WARNING: Unable to open PCM microphone input for LUN #%RU32!\n", pDrv->uLUN));
2445 if (!pDrv->pConnector->pfnIsOutputOK(pDrv->pConnector, pDrv->Out.pStrmOut))
2446 LogRel(("AC97: WARNING: Unable to open PCM output for LUN #%RU32!\n", pDrv->uLUN));
2447
2448 char szMissingStreams[255];
2449 size_t len = 0;
2450 if (!pCon->pfnIsInputOK (pCon, pDrv->LineIn.pStrmIn))
2451 len = RTStrPrintf(szMissingStreams,
2452 sizeof(szMissingStreams), "PCM Input");
2453 if (!pCon->pfnIsOutputOK(pCon, pDrv->Out.pStrmOut))
2454 len += RTStrPrintf(szMissingStreams + len,
2455 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
2456 if (!pCon->pfnIsInputOK (pCon, pDrv->MicIn.pStrmIn))
2457 len += RTStrPrintf(szMissingStreams + len,
2458 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
2459
2460 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
2461 N_("Some AC'97 audio streams (%s) could not be opened. Guest applications generating audio "
2462 "output or depending on audio input may hang. Make sure your host audio device "
2463 "is working properly. Check the logfile for error messages of the audio "
2464 "subsystem"), szMissingStreams);
2465 }
2466 }
2467 }
2468
2469 if (RT_SUCCESS(rc))
2470 {
2471 pThis->cbReadWriteBuf = _4K; /** @todo Make this configurable. */
2472 pThis->pvReadWriteBuf = (uint8_t *)RTMemAllocZ(pThis->cbReadWriteBuf);
2473 if (!pThis->pvReadWriteBuf)
2474 rc = VERR_NO_MEMORY;
2475 }
2476
2477# ifndef VBOX_WITH_AUDIO_CALLBACKS
2478 if (RT_SUCCESS(rc))
2479 {
2480 /* Start the emulation timer. */
2481 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, ichac97Timer, pThis,
2482 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchAc97", &pThis->pTimer);
2483 AssertRCReturn(rc, rc);
2484
2485 if (RT_SUCCESS(rc))
2486 {
2487 pThis->uTimerTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 200; /** Hz. @todo Make this configurable! */
2488 pThis->uTimerTS = PDMDevHlpTMTimeVirtGet(pDevIns);
2489 if (pThis->uTimerTicks < 100)
2490 pThis->uTimerTicks = 100;
2491 LogFunc(("Timer ticks=%RU64\n", pThis->uTimerTicks));
2492
2493 /* Fire off timer. */
2494 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTimerTicks);
2495 }
2496 }
2497# else
2498 if (RT_SUCCESS(rc))
2499 {
2500 PAC97DRIVER pDrv;
2501 RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
2502 {
2503 /* Only register primary driver.
2504 * The device emulation does the output multiplexing then. */
2505 if (pDrv->Flags != PDMAUDIODRVFLAG_PRIMARY)
2506 continue;
2507
2508 PDMAUDIOCALLBACK AudioCallbacks[2];
2509
2510 AC97CALLBACKCTX Ctx = { pThis, pDrv };
2511
2512 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
2513 AudioCallbacks[0].pfnCallback = ac97CallbackInput;
2514 AudioCallbacks[0].pvCtx = &Ctx;
2515 AudioCallbacks[0].cbCtx = sizeof(AC97CALLBACKCTX);
2516
2517 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
2518 AudioCallbacks[1].pfnCallback = ac97CallbackOutput;
2519 AudioCallbacks[1].pvCtx = &Ctx;
2520 AudioCallbacks[1].cbCtx = sizeof(AC97CALLBACKCTX);
2521
2522 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
2523 if (RT_FAILURE(rc))
2524 break;
2525 }
2526 }
2527# endif
2528
2529# ifdef VBOX_WITH_STATISTICS
2530 if (RT_SUCCESS(rc))
2531 {
2532 /*
2533 * Register statistics.
2534 */
2535 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/AC97/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
2536 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/AC97/BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
2537 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/AC97/BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
2538 }
2539# endif
2540
2541 LogFlowFuncLeaveRC(rc);
2542 return rc;
2543}
2544
2545/**
2546 * The device registration structure.
2547 */
2548const PDMDEVREG g_DeviceICHAC97 =
2549{
2550 /* u32Version */
2551 PDM_DEVREG_VERSION,
2552 /* szName */
2553 "ichac97",
2554 /* szRCMod */
2555 "",
2556 /* szR0Mod */
2557 "",
2558 /* pszDescription */
2559 "ICH AC'97 Audio Controller",
2560 /* fFlags */
2561 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2562 /* fClass */
2563 PDM_DEVREG_CLASS_AUDIO,
2564 /* cMaxInstances */
2565 1,
2566 /* cbInstance */
2567 sizeof(AC97STATE),
2568 /* pfnConstruct */
2569 ichac97Construct,
2570 /* pfnDestruct */
2571 ichac97Destruct,
2572 /* pfnRelocate */
2573 NULL,
2574 /* pfnMemSetup */
2575 NULL,
2576 /* pfnPowerOn */
2577 NULL,
2578 /* pfnReset */
2579 ichac97Reset,
2580 /* pfnSuspend */
2581 NULL,
2582 /* pfnResume */
2583 NULL,
2584 /* pfnAttach */
2585 NULL,
2586 /* pfnDetach */
2587 NULL,
2588 /* pfnQueryInterface. */
2589 NULL,
2590 /* pfnInitComplete */
2591 NULL,
2592 /* pfnPowerOff */
2593 NULL,
2594 /* pfnSoftReset */
2595 NULL,
2596 /* u32VersionEnd */
2597 PDM_DEVREG_VERSION
2598};
2599
2600#endif /* !IN_RING3 */
2601#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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