DevIchAc97.cpp@ 61523

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1	/* $Id: DevIchAc97.cpp 61523 2016-06-07 09:47:21Z vboxsync $ */
2	/** @file
3	* DevIchAc97 - VBox ICH AC97 Audio Controller.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_AC97
23	#include <VBox/log.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/vmm/pdmaudioifs.h>
26
27	#include <iprt/assert.h>
28	#ifdef IN_RING3
29	# ifdef DEBUG
30	# include <iprt/file.h>
31	# endif
32	# include <iprt/mem.h>
33	# include <iprt/string.h>
34	# include <iprt/uuid.h>
35	#endif
36
37	#include "VBoxDD.h"
38
39	#include "AudioMixBuffer.h"
40	#include "AudioMixer.h"
41	#include "DrvAudio.h"
42
43
44	/*********************************************************************************************************************************
45	* Defined Constants And Macros *
46	*********************************************************************************************************************************/
47
48	#ifdef DEBUG_andy
49	/*
50	* AC97_DEBUG_DUMP_PCM_DATA enables dumping the raw PCM data
51	* to a file on the host. Be sure to adjust AC97_DEBUG_DUMP_PCM_DATA_PATH
52	* to your needs before using this!
53	*/
54	# define AC97_DEBUG_DUMP_PCM_DATA
55	# ifdef RT_OS_WINDOWS
56	# define AC97_DEBUG_DUMP_PCM_DATA_PATH "c:\\temp\\"
57	# else
58	# define AC97_DEBUG_DUMP_PCM_DATA_PATH "/tmp/"
59	# endif
60	#endif /* DEBUG_andy */
61
62	#define AC97_SSM_VERSION 1
63
64	#define AC97_TIMER_HZ 50
65
66	#ifdef VBOX
67	# define SOFT_VOLUME /** @todo Get rid of this crap. */
68	#else
69	# define SOFT_VOLUME
70	#endif
71
72	/** @todo Use AC97_ prefixes! */
73	#define SR_FIFOE RT_BIT(4) /* rwc, FIFO error. */
74	#define SR_BCIS RT_BIT(3) /* rwc, Buffer completion interrupt status. */
75	#define SR_LVBCI RT_BIT(2) /* rwc, Last valid buffer completion interrupt. */
76	#define SR_CELV RT_BIT(1) /* ro, Current equals last valid. */
77	#define SR_DCH RT_BIT(0) /* ro, Controller halted. */
78	#define SR_VALID_MASK (RT_BIT(5) - 1)
79	#define SR_WCLEAR_MASK (SR_FIFOE \| SR_BCIS \| SR_LVBCI)
80	#define SR_RO_MASK (SR_DCH \| SR_CELV)
81	#define SR_INT_MASK (SR_FIFOE \| SR_BCIS \| SR_LVBCI)
82
83	#define CR_IOCE RT_BIT(4) /* rw, Interrupt On Completion Enable. */
84	#define CR_FEIE RT_BIT(3) /* rw FIFO Error Interrupt Enable. */
85	#define CR_LVBIE RT_BIT(2) /* rw Last Valid Buffer Interrupt Enable. */
86	#define CR_RR RT_BIT(1) /* rw Reset Registers. */
87	#define CR_RPBM RT_BIT(0) /* rw Run/Pause Bus Master. */
88	#define CR_VALID_MASK (RT_BIT(5) - 1)
89	#define CR_DONT_CLEAR_MASK (CR_IOCE \| CR_FEIE \| CR_LVBIE)
90
91	#define GC_WR 4 /* rw */
92	#define GC_CR 2 /* rw */
93	#define GC_VALID_MASK (RT_BIT(6) - 1)
94
95	#define GS_MD3 RT_BIT(17) /* rw */
96	#define GS_AD3 RT_BIT(16) /* rw */
97	#define GS_RCS RT_BIT(15) /* rwc */
98	#define GS_B3S12 RT_BIT(14) /* ro */
99	#define GS_B2S12 RT_BIT(13) /* ro */
100	#define GS_B1S12 RT_BIT(12) /* ro */
101	#define GS_S1R1 RT_BIT(11) /* rwc */
102	#define GS_S0R1 RT_BIT(10) /* rwc */
103	#define GS_S1CR RT_BIT(9) /* ro */
104	#define GS_S0CR RT_BIT(8) /* ro */
105	#define GS_MINT RT_BIT(7) /* ro */
106	#define GS_POINT RT_BIT(6) /* ro */
107	#define GS_PIINT RT_BIT(5) /* ro */
108	#define GS_RSRVD (RT_BIT(4)\|RT_BIT(3))
109	#define GS_MOINT RT_BIT(2) /* ro */
110	#define GS_MIINT RT_BIT(1) /* ro */
111	#define GS_GSCI RT_BIT(0) /* rwc */
112	#define GS_RO_MASK (GS_B3S12 \| \
113	GS_B2S12 \| \
114	GS_B1S12 \| \
115	GS_S1CR \| \
116	GS_S0CR \| \
117	GS_MINT \| \
118	GS_POINT \| \
119	GS_PIINT \| \
120	GS_RSRVD \| \
121	GS_MOINT \| \
122	GS_MIINT)
123	#define GS_VALID_MASK (RT_BIT(18) - 1)
124	#define GS_WCLEAR_MASK (GS_RCS\|GS_S1R1\|GS_S0R1\|GS_GSCI)
125
126	/** @name Buffer Descriptor
127	* @{ */
128	#define BD_IOC RT_BIT(31) /*< Interrupt on Completion. /
129	#define BD_BUP RT_BIT(30) /*< Buffer Underrun Policy. /
130
131	#define BD_MAX_LEN_MASK 0xFFFE
132	/** @} */
133
134	/** @name Extended Audio Status and Control Register
135	* @{ */
136	#define EACS_VRA 1 /*< Variable Rate Audio (4.2.1.1). /
137	#define EACS_VRM 8 /*< Variable Rate Mic Audio (4.2.1.1). /
138	/** @} */
139
140	#define VOL_MASK 0x1f
141	#define MUTE_SHIFT 15
142
143	#define REC_MASK 7
144	enum
145	{
146	REC_MIC = 0,
147	REC_CD,
148	REC_VIDEO,
149	REC_AUX,
150	REC_LINE_IN,
151	REC_STEREO_MIX,
152	REC_MONO_MIX,
153	REC_PHONE
154	};
155
156	enum
157	{
158	AC97_Reset = 0x00,
159	AC97_Master_Volume_Mute = 0x02,
160	AC97_Headphone_Volume_Mute = 0x04, /** Also known as AUX, see table 16, section 5.7. */
161	AC97_Master_Volume_Mono_Mute = 0x06,
162	AC97_Master_Tone_RL = 0x08,
163	AC97_PC_BEEP_Volume_Mute = 0x0A,
164	AC97_Phone_Volume_Mute = 0x0C,
165	AC97_Mic_Volume_Mute = 0x0E,
166	AC97_Line_In_Volume_Mute = 0x10,
167	AC97_CD_Volume_Mute = 0x12,
168	AC97_Video_Volume_Mute = 0x14,
169	AC97_Aux_Volume_Mute = 0x16,
170	AC97_PCM_Out_Volume_Mute = 0x18,
171	AC97_Record_Select = 0x1A,
172	AC97_Record_Gain_Mute = 0x1C,
173	AC97_Record_Gain_Mic_Mute = 0x1E,
174	AC97_General_Purpose = 0x20,
175	AC97_3D_Control = 0x22,
176	AC97_AC_97_RESERVED = 0x24,
177	AC97_Powerdown_Ctrl_Stat = 0x26,
178	AC97_Extended_Audio_ID = 0x28,
179	AC97_Extended_Audio_Ctrl_Stat = 0x2A,
180	AC97_PCM_Front_DAC_Rate = 0x2C,
181	AC97_PCM_Surround_DAC_Rate = 0x2E,
182	AC97_PCM_LFE_DAC_Rate = 0x30,
183	AC97_PCM_LR_ADC_Rate = 0x32,
184	AC97_MIC_ADC_Rate = 0x34,
185	AC97_6Ch_Vol_C_LFE_Mute = 0x36,
186	AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
187	AC97_Vendor_Reserved = 0x58,
188	AC97_AD_Misc = 0x76,
189	AC97_Vendor_ID1 = 0x7c,
190	AC97_Vendor_ID2 = 0x7e
191	};
192
193	/* Codec models. */
194	enum {
195	Codec_STAC9700 = 0, /* SigmaTel STAC9700 */
196	Codec_AD1980, /* Analog Devices AD1980 */
197	Codec_AD1981B /* Analog Devices AD1981B */
198	};
199
200	/* Analog Devices miscellaneous regiter bits used in AD1980. */
201	#define AD_MISC_LOSEL RT_BIT(5) /* Surround (rear) goes to line out outputs. */
202	#define AD_MISC_HPSEL RT_BIT(10) /* PCM (front) goes to headphone outputs. */
203
204	#define ICHAC97STATE_2_DEVINS(a_pAC97) ((a_pAC97)->pDevInsR3)
205
206	enum
207	{
208	BUP_SET = RT_BIT(0),
209	BUP_LAST = RT_BIT(1)
210	};
211
212	/** Emits registers for a specific (Native Audio Bus Master BAR) NABMBAR. */
213	#define AC97_NABMBAR_REGS(prefix, off) \
214	enum { \
215	prefix ## _BDBAR = off, /* Buffer Descriptor Base Address */ \
216	prefix ## _CIV = off + 4, /* Current Index Value */ \
217	prefix ## _LVI = off + 5, /* Last Valid Index */ \
218	prefix ## _SR = off + 6, /* Status Register */ \
219	prefix ## _PICB = off + 8, /* Position in Current Buffer */ \
220	prefix ## _PIV = off + 10, /* Prefetched Index Value */ \
221	prefix ## _CR = off + 11 /* Control Register */ \
222	}
223
224	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
225	typedef enum
226	{
227	PI_INDEX = 0, /** PCM in */
228	PO_INDEX, /** PCM out */
229	MC_INDEX, /** Mic in */
230	LAST_INDEX
231	} AC97SOUNDSOURCE;
232
233	AC97_NABMBAR_REGS(PI, PI_INDEX * 16);
234	AC97_NABMBAR_REGS(PO, PO_INDEX * 16);
235	AC97_NABMBAR_REGS(MC, MC_INDEX * 16);
236	#endif
237
238	enum
239	{
240	/** NABMBAR: Global Control Register. */
241	GLOB_CNT = 0x2c,
242	/** NABMBAR Global Status. */
243	GLOB_STA = 0x30,
244	/** Codec Access Semaphore Register. */
245	CAS = 0x34
246	};
247
248	#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
249
250	/*********************************************************************************************************************************
251	* Structures and Typedefs *
252	*********************************************************************************************************************************/
253
254	/**
255	* Buffer Descriptor List Entry (BDLE).
256	*/
257	typedef struct AC97BDLE
258	{
259	uint32_t addr;
260	uint32_t ctl_len;
261	} AC97BDLE, *PAC97BDLE;
262
263	/**
264	* Bus master register set for an audio stream.
265	*/
266	typedef struct AC97BMREGS
267	{
268	uint32_t bdbar; /** rw 0, Buffer Descriptor List: BAR (Base Address Register). */
269	uint8_t civ; /** ro 0, Current index value. */
270	uint8_t lvi; /** rw 0, Last valid index. */
271	uint16_t sr; /** rw 1, Status register. */
272	uint16_t picb; /** ro 0, Position in current buffer (in samples). */
273	uint8_t piv; /** ro 0, Prefetched index value. */
274	uint8_t cr; /** rw 0, Control register. */
275	int bd_valid; /** Whether current BDLE is initialized or not. */
276	AC97BDLE bd; /** Current Buffer Descriptor List Entry (BDLE). */
277	} AC97BMREGS, *PAC97BMREGS;
278
279	/**
280	* Internal state of an AC97 stream.
281	*/
282	typedef struct AC97STREAMSTATE
283	{
284	/** Temporary FIFO write buffer. */
285	R3PTRTYPE(uint8_t *) au8FIFOW;
286	/** Size of the temporary FIFO write buffer. */
287	uint32_t cbFIFOW;
288	/** Current write offset in FIFO write buffer. */
289	uint32_t offFIFOW;
290	uint8_t Padding;
291	} AC97STREAMSTATE, *PAC97STREAMSTATE;
292
293	/**
294	* Structure for keeping an AC97 stream state.
295	*
296	* Contains only register values which do not change until a
297	* stream reset occurs.
298	*/
299	typedef struct AC97STREAM
300	{
301	/** Stream number (SDn). */
302	uint8_t u8Strm;
303	/** Bus master registers of this stream. */
304	AC97BMREGS Regs;
305	/** Internal state of this stream. */
306	AC97STREAMSTATE State;
307	} AC97STREAM, *PAC97STREAM;
308
309	typedef struct AC97INPUTSTREAM
310	{
311	/** Mixer handle for input stream. */
312	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
313	} AC97INPUTSTREAM, *PAC97INPUTSTREAM;
314
315	typedef struct AC97OUTPUTSTREAM
316	{
317	/** Mixer handle for output stream. */
318	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
319	} AC97OUTPUTSTREAM, *PAC97OUTPUTSTREAM;
320
321	/**
322	* Struct for maintaining a host backend driver.
323	*/
324	typedef struct AC97STATE *PAC97STATE;
325	typedef struct AC97DRIVER
326	{
327	/** Node for storing this driver in our device driver list of AC97STATE. */
328	RTLISTNODER3 Node;
329	/** Pointer to AC97 controller (state). */
330	R3PTRTYPE(PAC97STATE) pAC97State;
331	/** Driver flags. */
332	PDMAUDIODRVFLAGS Flags;
333	uint32_t PaddingFlags;
334	/** LUN # to which this driver has been assigned. */
335	uint8_t uLUN;
336	/** Whether this driver is in an attached state or not. */
337	bool fAttached;
338	uint8_t Padding[4];
339	/** Pointer to attached driver base interface. */
340	R3PTRTYPE(PPDMIBASE) pDrvBase;
341	/** Audio connector interface to the underlying host backend. */
342	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
343	/** Stream for line input. */
344	AC97INPUTSTREAM LineIn;
345	/** Stream for mic input. */
346	AC97INPUTSTREAM MicIn;
347	/** Stream for output. */
348	AC97OUTPUTSTREAM Out;
349	} AC97DRIVER, *PAC97DRIVER;
350
351	typedef struct AC97STATE
352	{
353	/** The PCI device state. */
354	PCIDevice PciDev;
355	/** R3 Pointer to the device instance. */
356	PPDMDEVINSR3 pDevInsR3;
357	/** Global Control (Bus Master Control Register). */
358	uint32_t glob_cnt;
359	/** Global Status (Bus Master Control Register). */
360	uint32_t glob_sta;
361	/** Codec Access Semaphore Register (Bus Master Control Register). */
362	uint32_t cas;
363	uint32_t last_samp;
364	uint8_t mixer_data[256];
365	/** Stream state for line-in. */
366	AC97STREAM StreamLineIn;
367	/** Stream state for microphone-in. */
368	AC97STREAM StreamMicIn;
369	/** Stream state for output. */
370	AC97STREAM StreamOut;
371	/** Number of active (running) SDn streams. */
372	uint8_t cStreamsActive;
373	#ifndef VBOX_WITH_AUDIO_CALLBACKS
374	/** The timer for pumping data thru the attached LUN drivers. */
375	PTMTIMERR3 pTimer;
376	# if HC_ARCH_BITS == 32
377	uint32_t Padding0;
378	# endif
379	/** Flag indicating whether the timer is active or not. */
380	bool fTimerActive;
381	uint8_t u8Padding1[7];
382	/** The timer interval for pumping data thru the LUN drivers in timer ticks. */
383	uint64_t cTimerTicks;
384	/** Timestamp of the last timer callback (ac97Timer).
385	* Used to calculate the time actually elapsed between two timer callbacks. */
386	uint64_t uTimerTS;
387	#endif
388	#ifdef VBOX_WITH_STATISTICS
389	uint8_t Padding1;
390	STAMPROFILE StatTimer;
391	STAMCOUNTER StatBytesRead;
392	STAMCOUNTER StatBytesWritten;
393	#endif
394	/** List of associated LUN drivers (AC97DRIVER). */
395	RTLISTANCHOR lstDrv;
396	/** The device's software mixer. */
397	R3PTRTYPE(PAUDIOMIXER) pMixer;
398	/** Audio sink for PCM output. */
399	R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
400	/** Audio sink for line input. */
401	R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
402	/** Audio sink for microphone input. */
403	R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
404	uint8_t silence[128];
405	int bup_flag;
406	/** The base interface for LUN\#0. */
407	PDMIBASE IBase;
408	/** Base port of the I/O space region. */
409	RTIOPORT IOPortBase[2];
410	/** Codec model. */
411	uint32_t uCodecModel;
412	} AC97STATE, *PAC97STATE;
413
414	#ifdef VBOX_WITH_STATISTICS
415	AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
416	AssertCompileMemberAlignment(AC97STATE, StatBytesRead, 8);
417	AssertCompileMemberAlignment(AC97STATE, StatBytesWritten, 8);
418	#endif
419
420	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
421
422	static void ichac97DestroyIn(PAC97STATE pThis, PDMAUDIORECSOURCE enmRecSource);
423	static void ichac97DestroyOut(PAC97STATE pThis);
424	DECLINLINE(PAC97STREAM) ichac97GetStreamFromID(PAC97STATE pThis, uint32_t uID);
425	static int ichac97StreamInit(PAC97STATE pThis, PAC97STREAM pStream, uint8_t u8Strm);
426	static DECLCALLBACK(void) ichac97Reset(PPDMDEVINS pDevIns);
427	#ifndef VBOX_WITH_AUDIO_CALLBACKS
428	static void ichac97TimerMaybeStart(PAC97STATE pThis);
429	static void ichac97TimerMaybeStop(PAC97STATE pThis);
430	static DECLCALLBACK(void) ichac97Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
431	#endif
432	static int ichac97TransferAudio(PAC97STATE pThis, PAC97STREAM pStream);
433
434	static void ichac97WarmReset(PAC97STATE pThis)
435	{
436	NOREF(pThis);
437	}
438
439	static void ichac97ColdReset(PAC97STATE pThis)
440	{
441	NOREF(pThis);
442	}
443
444	DECLINLINE(PAUDMIXSINK) ichac97IndexToSink(PAC97STATE pThis, uint8_t uIndex)
445	{
446	AssertPtrReturn(pThis, NULL);
447
448	switch (uIndex)
449	{
450	case PI_INDEX: return pThis->pSinkLineIn; break;
451	case PO_INDEX: return pThis->pSinkOutput; break;
452	case MC_INDEX: return pThis->pSinkMicIn; break;
453	default: break;
454	}
455
456	AssertMsgFailed(("Wrong index %RU8\n", uIndex));
457	return NULL;
458	}
459
460	/** Fetches the buffer descriptor at _CIV. */
461	static void ichac97StreamFetchBDLE(PAC97STATE pThis, PAC97STREAM pStream)
462	{
463	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
464	PAC97BMREGS pRegs = &pStream->Regs;
465
466	uint32_t u32[2];
467
468	PDMDevHlpPhysRead(pDevIns, pRegs->bdbar + pRegs->civ * 8, &u32[0], sizeof(u32));
469	pRegs->bd_valid = 1;
470	#if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)
471	# error Please adapt the code (audio buffers are little endian)!
472	#else
473	pRegs->bd.addr = RT_H2LE_U32(u32[0] & ~3);
474	pRegs->bd.ctl_len = RT_H2LE_U32(u32[1]);
475	#endif
476	pRegs->picb = pRegs->bd.ctl_len & BD_MAX_LEN_MASK;
477	LogFlowFunc(("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
478	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len >> 16,
479	pRegs->bd.ctl_len & BD_MAX_LEN_MASK,
480	(pRegs->bd.ctl_len & BD_MAX_LEN_MASK) << 1)); /** @todo r=andy Assumes 16bit samples. */
481	}
482
483	/**
484	* Update the BM status register
485	*/
486	static void ichac97StreamUpdateStatus(PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr)
487	{
488	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
489	PAC97BMREGS pRegs = &pStream->Regs;
490
491	bool fSignal = false;
492	int iIRQL;
493
494	uint32_t new_mask = new_sr & SR_INT_MASK;
495	uint32_t old_mask = pRegs->sr & SR_INT_MASK;
496
497	static uint32_t const masks[] = { GS_PIINT, GS_POINT, GS_MINT };
498
499	if (new_mask ^ old_mask)
500	{
501	/** @todo Is IRQ deasserted when only one of status bits is cleared? */
502	if (!new_mask)
503	{
504	fSignal = true;
505	iIRQL = 0;
506	}
507	else if ((new_mask & SR_LVBCI) && (pRegs->cr & CR_LVBIE))
508	{
509	fSignal = true;
510	iIRQL = 1;
511	}
512	else if ((new_mask & SR_BCIS) && (pRegs->cr & CR_IOCE))
513	{
514	fSignal = true;
515	iIRQL = 1;
516	}
517	}
518
519	pRegs->sr = new_sr;
520
521	LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n",
522	pRegs->sr & SR_BCIS, pRegs->sr & SR_LVBCI, pRegs->sr, fSignal, iIRQL));
523
524	if (fSignal)
525	{
526	if (iIRQL)
527	pThis->glob_sta \|= masks[pStream->u8Strm];
528	else
529	pThis->glob_sta &= ~masks[pStream->u8Strm];
530
531	LogFlowFunc(("Setting IRQ level=%d\n", iIRQL));
532	PDMDevHlpPCISetIrq(pDevIns, 0, iIRQL);
533	}
534	}
535
536	static bool ichac97StreamIsActive(PAC97STATE pThis, PAC97STREAM pStream)
537	{
538	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
539	AssertPtrReturn(pStream, VERR_INVALID_POINTER);
540
541	bool fActive = AudioMixerSinkGetStatus(ichac97IndexToSink(pThis, pStream->u8Strm));
542
543	LogFlowFunc(("SD=%RU8, fActive=%RTbool\n", pStream->u8Strm, fActive));
544	return fActive;
545	}
546
547	static int ichac97StreamSetActive(PAC97STATE pThis, PAC97STREAM pStream, bool fActive)
548	{
549	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
550	AssertPtrReturn(pStream, VERR_INVALID_POINTER);
551
552	if (!fActive)
553	{
554	if (pThis->cStreamsActive) /* Disable can be called mupltiple times. */
555	pThis->cStreamsActive--;
556
557	#ifndef VBOX_WITH_AUDIO_CALLBACKS
558	ichac97TimerMaybeStop(pThis);
559	#endif
560	}
561	else
562	{
563	pThis->cStreamsActive++;
564	#ifndef VBOX_WITH_AUDIO_CALLBACKS
565	ichac97TimerMaybeStart(pThis);
566	#endif
567	}
568
569	int rc = AudioMixerSinkCtl(ichac97IndexToSink(pThis, pStream->u8Strm),
570	fActive ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE);
571
572	LogFlowFunc(("SD=%RU8, fActive=%RTbool, cStreamsActive=%RU8, rc=%Rrc\n",
573	pStream->u8Strm, fActive, pThis->cStreamsActive, rc));
574
575	return rc;
576	}
577
578	static void ichac97StreamResetBMRegs(PAC97STATE pThis, PAC97STREAM pStream)
579	{
580	AssertPtrReturnVoid(pThis);
581	AssertPtrReturnVoid(pStream);
582
583	LogFlowFuncEnter();
584
585	PAC97BMREGS pRegs = &pStream->Regs;
586
587	pRegs->bdbar = 0;
588	pRegs->civ = 0;
589	pRegs->lvi = 0;
590
591	ichac97StreamUpdateStatus(pThis, pStream, SR_DCH); /** @todo Do we need to do that? */
592
593	pRegs->picb = 0;
594	pRegs->piv = 0;
595	pRegs->cr = pRegs->cr & CR_DONT_CLEAR_MASK;
596	pRegs->bd_valid = 0;
597
598	ichac97StreamSetActive(pThis, pStream, false /* fActive */);
599
600	RT_ZERO(pThis->silence);
601	}
602
603	static void ichac97StreamDestroy(PAC97STREAM pStream)
604	{
605	LogFlowFunc(("SD=%RU8\n", pStream->u8Strm));
606
607	if (pStream->State.au8FIFOW)
608	{
609	Assert(pStream->State.cbFIFOW);
610	RTMemFree(pStream->State.au8FIFOW);
611	pStream->State.au8FIFOW = NULL;
612	}
613
614	pStream->State.cbFIFOW = 0;
615	pStream->State.offFIFOW = 0;
616	}
617
618	static void ichac97StreamsDestroy(PAC97STATE pThis)
619	{
620	LogFlowFuncEnter();
621
622	ichac97DestroyIn(pThis, PDMAUDIORECSOURCE_LINE);
623	ichac97DestroyIn(pThis, PDMAUDIORECSOURCE_MIC);
624	ichac97DestroyOut(pThis);
625
626	ichac97StreamDestroy(&pThis->StreamLineIn);
627	ichac97StreamDestroy(&pThis->StreamMicIn);
628	ichac97StreamDestroy(&pThis->StreamOut);
629	}
630
631	static int ichac97StreamsInit(PAC97STATE pThis)
632	{
633	LogFlowFuncEnter();
634
635	ichac97StreamInit(pThis, &pThis->StreamLineIn, PI_INDEX);
636	ichac97StreamInit(pThis, &pThis->StreamMicIn, MC_INDEX);
637	ichac97StreamInit(pThis, &pThis->StreamOut, PO_INDEX);
638
639	return VINF_SUCCESS;
640	}
641
642	static void ichac97MixerSet(PAC97STATE pThis, uint32_t u8Idx, uint16_t v)
643	{
644	if (u8Idx + 2 > sizeof(pThis->mixer_data))
645	{
646	AssertMsgFailed(("Index %RU8 out of bounds(%zu)\n", u8Idx, sizeof(pThis->mixer_data)));
647	return;
648	}
649
650	pThis->mixer_data[u8Idx + 0] = RT_LO_U8(v);
651	pThis->mixer_data[u8Idx + 1] = RT_HI_U8(v);
652	}
653
654	static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t u8Idx)
655	{
656	uint16_t uVal;
657
658	if (u8Idx + 2 > sizeof(pThis->mixer_data))
659	{
660	AssertMsgFailed(("Index %RU8 out of bounds (%zu)\n", u8Idx, sizeof(pThis->mixer_data)));
661	uVal = UINT16_MAX;
662	}
663	else
664	uVal = RT_MAKE_U16(pThis->mixer_data[u8Idx + 0], pThis->mixer_data[u8Idx + 1]);
665
666	return uVal;
667	}
668
669	static void ichac97DestroyIn(PAC97STATE pThis, PDMAUDIORECSOURCE enmRecSource)
670	{
671	AssertPtrReturnVoid(pThis);
672
673	LogFlowFuncEnter();
674
675	PAUDMIXSINK pSink;
676	switch (enmRecSource)
677	{
678	case PDMAUDIORECSOURCE_MIC:
679	pSink = pThis->pSinkMicIn;
680	break;
681	case PDMAUDIORECSOURCE_LINE:
682	pSink = pThis->pSinkLineIn;
683	break;
684	default:
685	AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
686	return;
687	}
688
689	PAC97DRIVER pDrv;
690	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
691	{
692	PAC97INPUTSTREAM pStream;
693	if (enmRecSource == PDMAUDIORECSOURCE_MIC) /** @todo Refine this once we have more streams. */
694	pStream = &pDrv->MicIn;
695	else
696	pStream = &pDrv->LineIn;
697
698	if (pStream->pMixStrm)
699	{
700	AudioMixerSinkRemoveStream(pSink, pStream->pMixStrm);
701	AudioMixerStreamDestroy(pStream->pMixStrm);
702	}
703	pStream->pMixStrm = NULL;
704	}
705	}
706
707	static void ichac97DestroyOut(PAC97STATE pThis)
708	{
709	AssertPtrReturnVoid(pThis);
710
711	LogFlowFuncEnter();
712
713	PAC97DRIVER pDrv;
714	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
715	{
716	if (pDrv->Out.pMixStrm)
717	{
718	AudioMixerSinkRemoveStream(pThis->pSinkOutput, pDrv->Out.pMixStrm);
719	AudioMixerStreamDestroy(pDrv->Out.pMixStrm);
720
721	pDrv->Out.pMixStrm = NULL;
722	}
723	}
724	}
725
726	static int ichac97CreateIn(PAC97STATE pThis,
727	const char *pszName, PDMAUDIORECSOURCE enmRecSource, PPDMAUDIOSTREAMCFG pCfg)
728	{
729	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
730	AssertPtrReturn(pszName, VERR_INVALID_POINTER);
731	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
732
733	PAUDMIXSINK pSink;
734	switch (enmRecSource)
735	{
736	case PDMAUDIORECSOURCE_MIC:
737	pSink = pThis->pSinkMicIn;
738	break;
739	case PDMAUDIORECSOURCE_LINE:
740	pSink = pThis->pSinkLineIn;
741	break;
742	default:
743	AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
744	return VERR_NOT_SUPPORTED;
745	}
746
747	/* Update the sink's format. */
748	PDMPCMPROPS PCMProps;
749	int rc = DrvAudioHlpStreamCfgToProps(pCfg, &PCMProps);
750	if (RT_SUCCESS(rc))
751	rc = AudioMixerSinkSetFormat(pSink, &PCMProps);
752
753	if (RT_FAILURE(rc))
754	return rc;
755
756	PAC97DRIVER pDrv;
757	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
758	{
759	if (!RTStrPrintf(pCfg->szName, sizeof(pCfg->szName), "[LUN#%RU8] %s", pDrv->uLUN, pszName))
760	{
761	rc = VERR_BUFFER_OVERFLOW;
762	break;
763	}
764
765	PAC97INPUTSTREAM pStream;
766	if (enmRecSource == PDMAUDIORECSOURCE_MIC) /** @todo Refine this once we have more streams. */
767	pStream = &pDrv->MicIn;
768	else
769	pStream = &pDrv->LineIn;
770
771	AudioMixerSinkRemoveStream(pSink, pStream->pMixStrm);
772
773	AudioMixerStreamDestroy(pStream->pMixStrm);
774	pStream->pMixStrm = NULL;
775
776	int rc2 = AudioMixerSinkCreateStream(pSink, pDrv->pConnector, pCfg, 0 /* fFlags */ , &pStream->pMixStrm);
777	if (RT_SUCCESS(rc2))
778	{
779	rc2 = AudioMixerSinkAddStream(pSink, pStream->pMixStrm);
780	LogFlowFunc(("LUN#%RU8: Created input \"%s\", rc=%Rrc\n", pDrv->uLUN, pCfg->szName, rc2));
781	}
782
783	if (RT_SUCCESS(rc))
784	rc = rc2;
785	}
786
787	LogFlowFuncLeaveRC(rc);
788	return rc;
789	}
790
791	static int ichac97CreateOut(PAC97STATE pThis, const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
792	{
793	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
794	AssertPtrReturn(pszName, VERR_INVALID_POINTER);
795	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
796
797	/* Update the sink's format. */
798	PDMPCMPROPS PCMProps;
799	int rc = DrvAudioHlpStreamCfgToProps(pCfg, &PCMProps);
800	if (RT_SUCCESS(rc))
801	rc = AudioMixerSinkSetFormat(pThis->pSinkOutput, &PCMProps);
802
803	if (RT_FAILURE(rc))
804	return rc;
805
806	PAC97DRIVER pDrv;
807	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
808	{
809	if (!RTStrPrintf(pCfg->szName, sizeof(pCfg->szName), "[LUN#%RU8] %s (%RU32Hz, %RU8 %s)",
810	pDrv->uLUN, pszName, pCfg->uHz, pCfg->cChannels, pCfg->cChannels > 1 ? "Channels" : "Channel"))
811	{
812	rc = VERR_BUFFER_OVERFLOW;
813	break;
814	}
815
816	AudioMixerSinkRemoveStream(pThis->pSinkOutput, pDrv->Out.pMixStrm);
817
818	AudioMixerStreamDestroy(pDrv->Out.pMixStrm);
819	pDrv->Out.pMixStrm = NULL;
820
821	int rc2 = AudioMixerSinkCreateStream(pThis->pSinkOutput, pDrv->pConnector, pCfg, 0 /* fFlags */, &pDrv->Out.pMixStrm);
822	if (RT_SUCCESS(rc2))
823	{
824	rc2 = AudioMixerSinkAddStream(pThis->pSinkOutput, pDrv->Out.pMixStrm);
825	LogFlowFunc(("LUN#%RU8: Created output \"%s\", rc=%Rrc\n", pDrv->uLUN, pCfg->szName, rc2));
826	}
827
828	if (RT_SUCCESS(rc))
829	rc = rc2;
830	}
831
832	LogFlowFuncLeaveRC(rc);
833	return rc;
834	}
835
836	static int ichac97StreamInitEx(PAC97STATE pThis, PAC97STREAM pStream, uint8_t u8Strm, PPDMAUDIOSTREAMCFG pCfg)
837	{
838	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
839	AssertPtrReturn(pStream, VERR_INVALID_POINTER);
840	AssertReturn(u8Strm <= LAST_INDEX, VERR_INVALID_PARAMETER);
841	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
842
843	pStream->u8Strm = u8Strm;
844
845	LogFlowFunc(("u8Strm=%RU8, %RU32Hz, %RU8 %s\n",
846	pStream->u8Strm, pCfg->uHz, pCfg->cChannels, pCfg->cChannels > 1 ? "Channels" : "Channel"));
847
848	int rc;
849	switch (pStream->u8Strm)
850	{
851	case PI_INDEX:
852	rc = ichac97CreateIn(pThis, "ac97.pi", PDMAUDIORECSOURCE_LINE, pCfg);
853	break;
854
855	case MC_INDEX:
856	rc = ichac97CreateIn(pThis, "ac97.mc", PDMAUDIORECSOURCE_MIC, pCfg);
857	break;
858
859	case PO_INDEX:
860	rc = ichac97CreateOut(pThis, "ac97.po", pCfg);
861	break;
862
863	default:
864	rc = VERR_NOT_SUPPORTED;
865	break;
866	}
867
868	if (RT_FAILURE(rc))
869	LogRel2(("AC97: Error opening stream #%RU8, rc=%Rrc\n", pStream->u8Strm, rc));
870
871	LogFlowFuncLeaveRC(rc);
872	return rc;
873	}
874
875	static int ichac97StreamInit(PAC97STATE pThis, PAC97STREAM pStream, uint8_t u8Strm)
876	{
877	int rc = VINF_SUCCESS;
878
879	PDMAUDIOSTREAMCFG streamCfg;
880	RT_ZERO(streamCfg);
881
882	switch (u8Strm)
883	{
884	case PI_INDEX:
885	streamCfg.uHz = ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate);
886	streamCfg.enmDir = PDMAUDIODIR_IN;
887	streamCfg.DestSource.Source = PDMAUDIORECSOURCE_LINE;
888	break;
889
890	case MC_INDEX:
891	streamCfg.uHz = ichac97MixerGet(pThis, AC97_MIC_ADC_Rate);
892	streamCfg.enmDir = PDMAUDIODIR_IN;
893	streamCfg.DestSource.Source = PDMAUDIORECSOURCE_MIC;
894	break;
895
896	case PO_INDEX:
897	streamCfg.uHz = ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate);
898	streamCfg.enmDir = PDMAUDIODIR_OUT;
899	streamCfg.DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
900	break;
901
902	default:
903	rc = VERR_NOT_SUPPORTED;
904	break;
905	}
906
907	if (RT_SUCCESS(rc))
908	{
909	pStream->State.cbFIFOW = _4K; /** @todo Make FIFOW size configurable. */
910	pStream->State.offFIFOW = 0;
911	pStream->State.au8FIFOW = (uint8_t *)RTMemAllocZ(pStream->State.cbFIFOW);
912	if (!pStream->State.au8FIFOW)
913	rc = VERR_NO_MEMORY;
914	}
915
916	if (RT_SUCCESS(rc))
917	{
918	if (streamCfg.uHz)
919	{
920	streamCfg.cChannels = 2; /** @todo Handle mono channels? */
921	streamCfg.enmFormat = PDMAUDIOFMT_S16;
922	streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
923
924	rc = ichac97StreamInitEx(pThis, pStream, u8Strm, &streamCfg);
925	}
926	else
927	{
928	/* If no frequency is given, disable the stream. */
929	rc = ichac97StreamSetActive(pThis, pStream, false /* fActive */);
930	}
931	}
932
933	LogFlowFunc(("SD=%RU8, rc=%Rrc\n", u8Strm, rc));
934	return rc;
935	}
936
937	static int ichac97StreamReInit(PAC97STATE pThis, PAC97STREAM pStrm)
938	{
939	return ichac97StreamInit(pThis, pStrm, pStrm->u8Strm);
940	}
941
942	static void ichac97StreamReset(PAC97STATE pThis, PAC97STREAM pStrm)
943	{
944	AssertPtrReturnVoid(pThis);
945	AssertPtrReturnVoid(pStrm);
946
947	LogFlowFunc(("SD=%RU8\n", pStrm->u8Strm));
948
949	if (pStrm->State.au8FIFOW)
950	{
951	Assert(pStrm->State.cbFIFOW);
952	RT_BZERO(pStrm->State.au8FIFOW, pStrm->State.cbFIFOW);
953	}
954
955	pStrm->State.offFIFOW = 0;
956	}
957
958	static int ichac97MixerSetVolume(PAC97STATE pThis, int index, PDMAUDIOMIXERCTL mt, uint32_t val)
959	{
960	int mute = (val >> MUTE_SHIFT) & 1;
961	uint8_t rvol = val & VOL_MASK;
962	uint8_t lvol = (val >> 8) & VOL_MASK;
963
964	/* For the master volume, 0 corresponds to 0dB gain. But for the other
965	* volume controls, 0 corresponds to +12dB and 8 to 0dB. */
966	if (mt != PDMAUDIOMIXERCTL_VOLUME)
967	{
968	/* NB: Currently there is no gain support, only attenuation. */
969	lvol = lvol < 8 ? 0 : lvol - 8;
970	rvol = rvol < 8 ? 0 : rvol - 8;
971	}
972
973	/* AC'97 has 1.5dB steps; we use 0.375dB steps. */
974	rvol = 255 - rvol * 4;
975	lvol = 255 - lvol * 4;
976
977	LogFunc(("mt=%ld, val=%RX32, mute=%RTbool\n", mt, val, RT_BOOL(mute)));
978
979	int rc;
980
981	#ifdef SOFT_VOLUME
982	if (pThis->pMixer) /* Device can be in reset state, so no mixer available. */
983	{
984	PDMAUDIOVOLUME vol = { RT_BOOL(mute), lvol, rvol };
985	switch (mt)
986	{
987	case PDMAUDIOMIXERCTL_VOLUME:
988	rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
989	break;
990
991	case PDMAUDIOMIXERCTL_FRONT:
992	rc = AudioMixerSinkSetVolume(pThis->pSinkOutput, &vol);
993	break;
994
995	case PDMAUDIOMIXERCTL_MIC_IN:
996	rc = AudioMixerSinkSetVolume(pThis->pSinkMicIn, &vol);
997	break;
998
999	case PDMAUDIOMIXERCTL_LINE_IN:
1000	rc = AudioMixerSinkSetVolume(pThis->pSinkLineIn, &vol);
1001	break;
1002
1003	default:
1004	rc = VERR_NOT_SUPPORTED;
1005	break;
1006	}
1007	}
1008	else
1009	rc = VERR_NOT_SUPPORTED;
1010
1011	if (RT_FAILURE(rc))
1012	return rc;
1013	#else
1014	rc = VINF_SUCCESS;
1015	#endif /* SOFT_VOLUME */
1016
1017	rvol = VOL_MASK - ((VOL_MASK * rvol) / 255);
1018	lvol = VOL_MASK - ((VOL_MASK * lvol) / 255);
1019
1020	/*
1021	* From AC'97 SoundMax Codec AD1981A: "Because AC '97 defines 6-bit volume registers, to
1022	* maintain compatibility whenever the D5 or D13 bits are set to `1,' their respective
1023	* lower five volume bits are automatically set to `1' by the Codec logic. On readback,
1024	* all lower 5 bits will read ones whenever these bits are set to `1.'"
1025	*
1026	* Linux ALSA depends on this behavior.
1027	*/
1028	if (val & RT_BIT(5))
1029	val \|= RT_BIT(4) \| RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1) \| RT_BIT(0);
1030	if (val & RT_BIT(13))
1031	val \|= RT_BIT(12) \| RT_BIT(11) \| RT_BIT(10) \| RT_BIT(9) \| RT_BIT(8);
1032
1033	ichac97MixerSet(pThis, index, val);
1034
1035	return rc;
1036	}
1037
1038	static PDMAUDIORECSOURCE ichac97IndextoRecSource(uint8_t i)
1039	{
1040	switch (i)
1041	{
1042	case REC_MIC: return PDMAUDIORECSOURCE_MIC;
1043	case REC_CD: return PDMAUDIORECSOURCE_CD;
1044	case REC_VIDEO: return PDMAUDIORECSOURCE_VIDEO;
1045	case REC_AUX: return PDMAUDIORECSOURCE_AUX;
1046	case REC_LINE_IN: return PDMAUDIORECSOURCE_LINE;
1047	case REC_PHONE: return PDMAUDIORECSOURCE_PHONE;
1048	default:
1049	break;
1050	}
1051
1052	LogFlowFunc(("Unknown record source %d, using MIC\n", i));
1053	return PDMAUDIORECSOURCE_MIC;
1054	}
1055
1056	static uint8_t ichac97RecSourceToIndex(PDMAUDIORECSOURCE rs)
1057	{
1058	switch (rs)
1059	{
1060	case PDMAUDIORECSOURCE_MIC: return REC_MIC;
1061	case PDMAUDIORECSOURCE_CD: return REC_CD;
1062	case PDMAUDIORECSOURCE_VIDEO: return REC_VIDEO;
1063	case PDMAUDIORECSOURCE_AUX: return REC_AUX;
1064	case PDMAUDIORECSOURCE_LINE: return REC_LINE_IN;
1065	case PDMAUDIORECSOURCE_PHONE: return REC_PHONE;
1066	default:
1067	break;
1068	}
1069
1070	LogFlowFunc(("Unknown audio recording source %d using MIC\n", rs));
1071	return REC_MIC;
1072	}
1073
1074	static void ichac97RecordSelect(PAC97STATE pThis, uint32_t val)
1075	{
1076	uint8_t rs = val & REC_MASK;
1077	uint8_t ls = (val >> 8) & REC_MASK;
1078	PDMAUDIORECSOURCE ars = ichac97IndextoRecSource(rs);
1079	PDMAUDIORECSOURCE als = ichac97IndextoRecSource(ls);
1080	rs = ichac97RecSourceToIndex(ars);
1081	ls = ichac97RecSourceToIndex(als);
1082	ichac97MixerSet(pThis, AC97_Record_Select, rs \| (ls << 8));
1083	}
1084
1085	static int ichac97MixerReset(PAC97STATE pThis)
1086	{
1087	AssertPtrReturn(pThis, VERR_INVALID_PARAMETER);
1088
1089	LogFlowFuncEnter();
1090
1091	RT_ZERO(pThis->mixer_data);
1092
1093	/* Note: Make sure to reset all registers first before bailing out on error. */
1094
1095	ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
1096	ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
1097	ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
1098
1099	ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
1100	ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
1101	ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
1102	ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
1103	ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
1104	ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
1105	ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
1106	ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
1107
1108	ichac97MixerSet(pThis, AC97_Extended_Audio_ID , 0x0809);
1109	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
1110	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80);
1111	ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80);
1112	ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80);
1113	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80);
1114	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80);
1115
1116	if (pThis->uCodecModel == Codec_AD1980)
1117	{
1118	/* Analog Devices 1980 (AD1980) */
1119	ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
1120	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
1121	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
1122	ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
1123	}
1124	else if (pThis->uCodecModel == Codec_AD1981B)
1125	{
1126	/* Analog Devices 1981B (AD1981B) */
1127	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
1128	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
1129	}
1130	else
1131	{
1132	/* Sigmatel 9700 (STAC9700) */
1133	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
1134	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
1135	}
1136	ichac97RecordSelect(pThis, 0);
1137
1138	ichac97MixerSetVolume(pThis, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME, 0x8000);
1139	ichac97MixerSetVolume(pThis, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT, 0x8808);
1140	ichac97MixerSetVolume(pThis, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
1141
1142	return VINF_SUCCESS;
1143	}
1144
1145	/**
1146	* Writes data from the device to the host backends.
1147	*
1148	* @return IPRT status code.
1149	* @param pThis
1150	* @param pStream
1151	* @param cbMax
1152	* @param pcbWritten
1153	*/
1154	static int ichac97WriteAudio(PAC97STATE pThis, PAC97STREAM pStream, uint32_t cbToWrite, uint32_t *pcbWritten)
1155	{
1156	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1157	AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1158	AssertReturn(cbToWrite, VERR_INVALID_PARAMETER);
1159	/* pcbWritten is optional. */
1160
1161	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
1162	PAC97BMREGS pRegs = &pStream->Regs;
1163
1164	uint32_t addr = pRegs->bd.addr;
1165	uint32_t cbWrittenTotal = 0;
1166
1167	Log3Func(("PICB=%RU16, cbMax=%RU32\n", pRegs->picb, cbToWrite));
1168
1169	cbToWrite = RT_MIN((uint32_t)(pRegs->picb << 1), cbToWrite); /** @todo r=andy Assumes 16bit sample size. */
1170	if (!cbToWrite)
1171	{
1172	if (pcbWritten)
1173	*pcbWritten = 0;
1174	return VINF_EOF;
1175	}
1176
1177	int rc = VINF_SUCCESS;
1178
1179	LogFlowFunc(("pRegs=%p, cbMax=%RU32, cbToWrite=%RU32\n", pRegs, cbToWrite, cbToWrite));
1180
1181	Assert(pStream->State.offFIFOW <= pStream->State.cbFIFOW);
1182	uint32_t cbFIFOW = pStream->State.cbFIFOW - pStream->State.offFIFOW;
1183	uint8_t *pu8FIFOW = &pStream->State.au8FIFOW[pStream->State.offFIFOW];
1184
1185	uint32_t cbToRead;
1186	while (cbToWrite)
1187	{
1188	cbToRead = RT_MIN(cbToWrite, cbFIFOW);
1189	PDMDevHlpPhysRead(pDevIns, addr, pu8FIFOW, cbToRead); /** @todo r=andy Check rc? */
1190
1191	#ifdef AC97_DEBUG_DUMP_PCM_DATA
1192	RTFILE fh;
1193	RTFileOpen(&fh, AC97_DEBUG_DUMP_PCM_DATA_PATH "ac97WriteAudio.pcm",
1194	RTFILE_O_OPEN_CREATE \| RTFILE_O_APPEND \| RTFILE_O_WRITE \| RTFILE_O_DENY_NONE);
1195	RTFileWrite(fh, pu8FIFOW, cbToRead, NULL);
1196	RTFileClose(fh);
1197	#endif
1198	/*
1199	* Write data to the mixer sink.
1200	*/
1201	uint32_t cbWritten;
1202	rc = AudioMixerSinkWrite(pThis->pSinkOutput, AUDMIXOP_COPY, pu8FIFOW, cbToRead, &cbWritten);
1203
1204	LogFlowFunc(("\tcbToRead=%RU32, cbToWrite=%RU32, cbWritten=%RU32, cbLeft=%RU32, rc=%Rrc\n",
1205	cbToRead, cbToWrite, cbWritten, cbToWrite - cbWrittenTotal, rc));
1206
1207	if (RT_FAILURE(rc))
1208	break;
1209
1210	/* Advance. */
1211	Assert(cbToWrite >= cbToRead);
1212	cbToWrite -= cbToRead;
1213	addr += cbToRead;
1214	cbWrittenTotal += cbToRead;
1215	}
1216
1217	/* Set new buffer descriptor address. */
1218	pRegs->bd.addr = addr;
1219
1220	if (RT_SUCCESS(rc))
1221	{
1222	if (!cbToWrite) /* All data written? */
1223	{
1224	if (cbToRead < 4)
1225	{
1226	AssertMsgFailed(("Unable to save last written sample, cbToRead < 4 (is %RU32)\n", cbToRead));
1227	pThis->last_samp = 0;
1228	}
1229	else
1230	pThis->last_samp = (uint32_t )&pStream->State.au8FIFOW[pStream->State.offFIFOW + cbToRead - 4];
1231	}
1232
1233	if (pcbWritten)
1234	*pcbWritten = cbWrittenTotal;
1235	}
1236
1237	LogFlowFunc(("cbWrittenTotal=%RU32, rc=%Rrc\n", cbWrittenTotal, rc));
1238	return rc;
1239	}
1240
1241	static void ichac97WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
1242	{
1243	LogFlowFunc(("cbElapsed=%RU32\n", cbElapsed));
1244
1245	if (!(pThis->bup_flag & BUP_SET))
1246	{
1247	if (pThis->bup_flag & BUP_LAST)
1248	{
1249	unsigned int i;
1250	uint32_t p = (uint32_t)pThis->silence;
1251	for (i = 0; i < sizeof(pThis->silence) / 4; i++) /** @todo r=andy Assumes 16-bit samples, stereo. */
1252	*p++ = pThis->last_samp;
1253	}
1254	else
1255	RT_ZERO(pThis->silence);
1256
1257	pThis->bup_flag \|= BUP_SET;
1258	}
1259
1260	while (cbElapsed)
1261	{
1262	uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
1263	uint32_t cbWrittenToStream;
1264
1265	int rc2 = AudioMixerSinkWrite(pThis->pSinkOutput, AUDMIXOP_COPY,
1266	pThis->silence, cbToWrite, &cbWrittenToStream);
1267	if (RT_SUCCESS(rc2))
1268	{
1269	if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
1270	LogFlowFunc(("Warning: Only written %RU32 / %RU32 bytes, expect lags\n", cbWrittenToStream, cbToWrite));
1271	}
1272
1273	/* Always report all data as being written;
1274	* backends who were not able to catch up have to deal with it themselves. */
1275	Assert(cbElapsed >= cbToWrite);
1276	cbElapsed -= cbToWrite;
1277	}
1278	}
1279
1280	static int ichac97ReadAudio(PAC97STATE pThis, PAC97STREAM pStream, uint32_t cbToRead, uint32_t *pcbRead)
1281	{
1282	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1283	AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1284	AssertReturn(cbToRead, VERR_INVALID_PARAMETER);
1285	/* pcbRead is optional. */
1286
1287	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
1288	PAC97BMREGS pRegs = &pStream->Regs;
1289
1290	/* Select audio sink to process. */
1291	AssertMsg(pStream->u8Strm != PO_INDEX, ("Can't read from output\n"));
1292	PAUDMIXSINK pSink = pStream->u8Strm == MC_INDEX ? pThis->pSinkMicIn : pThis->pSinkLineIn;
1293	AssertPtr(pSink);
1294
1295	uint32_t cbRead = 0;
1296
1297	cbToRead = RT_MIN((uint32_t)(pRegs->picb << 1),
1298	RT_MIN(pStream->State.cbFIFOW, cbToRead)); /** @todo r=andy Assumes 16bit samples. */
1299
1300	if (!cbToRead)
1301	{
1302	if (pcbRead)
1303	*pcbRead = 0;
1304	return VINF_EOF;
1305	}
1306
1307	int rc;
1308
1309	rc = AudioMixerSinkRead(pSink, AUDMIXOP_BLEND, &pStream->State.au8FIFOW[pStream->State.offFIFOW], cbToRead, &cbRead);
1310	if ( RT_SUCCESS(rc)
1311	&& cbRead)
1312	{
1313	PDMDevHlpPCIPhysWrite(pDevIns, pRegs->bd.addr, &pStream->State.au8FIFOW[pStream->State.offFIFOW], cbRead);
1314	pRegs->bd.addr += cbRead;
1315	}
1316
1317	if (RT_SUCCESS(rc))
1318	{
1319	if (!cbRead)
1320	rc = VINF_EOF;
1321
1322	if (pcbRead)
1323	*pcbRead = cbRead;
1324	}
1325
1326	return rc;
1327	}
1328
1329	#ifndef VBOX_WITH_AUDIO_CALLBACKS
1330
1331	static void ichac97TimerMaybeStart(PAC97STATE pThis)
1332	{
1333	LogFlowFunc(("cStreamsActive=%RU8\n", pThis->cStreamsActive));
1334
1335	if (pThis->cStreamsActive == 0) /* Only start the timer if there are no active streams. */
1336	return;
1337
1338	if (!pThis->pTimer)
1339	return;
1340
1341	/* Set timer flag. */
1342	ASMAtomicXchgBool(&pThis->fTimerActive, true);
1343
1344	/* Update current time timestamp. */
1345	pThis->uTimerTS = TMTimerGet(pThis->pTimer);
1346
1347	/* Fire off timer. */
1348	TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
1349	}
1350
1351	static void ichac97TimerMaybeStop(PAC97STATE pThis)
1352	{
1353	LogFlowFunc(("cStreamsActive=%RU8\n", pThis->cStreamsActive));
1354
1355	if (pThis->cStreamsActive) /* Some streams still active? Bail out. */
1356	return;
1357
1358	if (!pThis->pTimer)
1359	return;
1360
1361	/* Set timer flag. */
1362	ASMAtomicXchgBool(&pThis->fTimerActive, false);
1363	}
1364
1365	static DECLCALLBACK(void) ichac97Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1366	{
1367	PAC97STATE pThis = (PAC97STATE)pvUser;
1368	Assert(pThis == PDMINS_2_DATA(pDevIns, PAC97STATE));
1369	AssertPtr(pThis);
1370
1371	STAM_PROFILE_START(&pThis->StatTimer, a);
1372
1373	uint64_t cTicksNow = TMTimerGet(pTimer);
1374	uint64_t cTicksElapsed = cTicksNow - pThis->uTimerTS;
1375	uint64_t cTicksPerSec = TMTimerGetFreq(pTimer);
1376
1377	LogFlowFuncEnter();
1378
1379	/* Update current time timestamp. */
1380	pThis->uTimerTS = cTicksNow;
1381
1382	/* Flag indicating whether to kick the timer again for a
1383	* new data processing round. */
1384	bool fKickTimer = false;
1385
1386	AudioMixerSinkTimerUpdate(pThis->pSinkLineIn, pThis->cTimerTicks, cTicksPerSec);
1387	ichac97TransferAudio(pThis, &pThis->StreamLineIn);
1388
1389	fKickTimer = AudioMixerSinkGetStatus(pThis->pSinkLineIn) & AUDMIXSINK_STS_DIRTY;
1390
1391	AudioMixerSinkTimerUpdate(pThis->pSinkMicIn , pThis->cTimerTicks, cTicksPerSec);
1392	ichac97TransferAudio(pThis, &pThis->StreamMicIn);
1393
1394	fKickTimer = AudioMixerSinkGetStatus(pThis->pSinkMicIn) & AUDMIXSINK_STS_DIRTY;
1395
1396	AudioMixerSinkTimerUpdate(pThis->pSinkOutput, pThis->cTimerTicks, cTicksPerSec);
1397	ichac97TransferAudio(pThis, &pThis->StreamOut);
1398
1399	fKickTimer = AudioMixerSinkGetStatus(pThis->pSinkOutput) & AUDMIXSINK_STS_DIRTY;
1400
1401	if ( ASMAtomicReadBool(&pThis->fTimerActive)
1402	\|\| fKickTimer)
1403	{
1404	/* Kick the timer again. */
1405	uint64_t cTicks = pThis->cTimerTicks;
1406	/** @todo adjust cTicks down by now much cbOutMin represents. */
1407	TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
1408	}
1409
1410	STAM_PROFILE_STOP(&pThis->StatTimer, a);
1411	}
1412
1413	#endif /* !VBOX_WITH_AUDIO_CALLBACKS */
1414
1415	static int ichac97TransferAudio(PAC97STATE pThis, PAC97STREAM pStream)
1416	{
1417	Log3Func(("SD=%RU8\n", pStream->u8Strm));
1418
1419	PAC97BMREGS pRegs = &pStream->Regs;
1420
1421	if (pRegs->sr & SR_DCH) /* Controller halted? */
1422	{
1423	if (pRegs->cr & CR_RPBM) /* Bus master operation starts. */
1424	{
1425	switch (pStream->u8Strm)
1426	{
1427	case PO_INDEX:
1428	ichac97WriteBUP(pThis, (uint32_t)(pRegs->picb << 1));
1429	break;
1430
1431	default:
1432	break;
1433	}
1434	}
1435
1436	return VINF_SUCCESS;
1437	}
1438
1439	/* BCIS flag still set? Skip iteration. */
1440	if (pRegs->sr & SR_BCIS)
1441	return VINF_SUCCESS;
1442
1443	int rc = VINF_SUCCESS;
1444	uint32_t cbWrittenTotal = 0;
1445
1446	do
1447	{
1448	if (!pRegs->bd_valid)
1449	{
1450	LogFlowFunc(("Invalid buffer descriptor, fetching next one ...\n"));
1451	ichac97StreamFetchBDLE(pThis, pStream);
1452	}
1453
1454	if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
1455	{
1456	LogFlowFunc(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
1457	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
1458	if (pRegs->civ == pRegs->lvi)
1459	{
1460	pRegs->sr \|= SR_DCH; /** @todo r=andy Also set CELV? */
1461	pThis->bup_flag = 0;
1462
1463	rc = VINF_EOF;
1464	break;
1465	}
1466
1467	pRegs->sr &= ~SR_CELV;
1468	pRegs->civ = pRegs->piv;
1469	pRegs->piv = (pRegs->piv + 1) % 32; /** @todo r=andy Define for max BDLEs? */
1470
1471	ichac97StreamFetchBDLE(pThis, pStream);
1472	continue;
1473	}
1474
1475	uint32_t cbToTransfer, cbTransferred;
1476	switch (pStream->u8Strm)
1477	{
1478	case PO_INDEX:
1479	{
1480	cbToTransfer = (uint32_t)(pRegs->picb << 1);
1481
1482	rc = ichac97WriteAudio(pThis, pStream, cbToTransfer, &cbTransferred);
1483	if ( RT_SUCCESS(rc)
1484	&& cbTransferred)
1485	{
1486	cbWrittenTotal += cbTransferred;
1487	Assert((cbTransferred & 1) == 0); /* Else the following shift won't work */
1488	pRegs->picb -= (cbTransferred >> 1); /** @todo r=andy Assumes 16bit samples. */
1489	}
1490	break;
1491	}
1492
1493	case PI_INDEX:
1494	case MC_INDEX:
1495	{
1496	cbToTransfer = (uint32_t)(pRegs->picb << 1);
1497
1498	rc = ichac97ReadAudio(pThis, pStream, cbToTransfer, &cbTransferred);
1499	if ( RT_SUCCESS(rc)
1500	&& cbTransferred)
1501	{
1502	Assert((cbTransferred & 1) == 0); /* Else the following shift won't work */
1503	pRegs->picb -= (cbTransferred >> 1); /** @todo r=andy Assumes 16bit samples. */
1504	}
1505	break;
1506	}
1507
1508	default:
1509	AssertMsgFailed(("Stream #%RU8 not supported\n", pStream->u8Strm));
1510	rc = VERR_NOT_SUPPORTED;
1511	break;
1512	}
1513
1514	Log3Func(("PICB=%RU16 (%#x), cbTransferred=%RU32 (%zu samples), cbWrittenTotal=%RU32\n",
1515	pRegs->picb, pRegs->picb, cbTransferred, (cbTransferred >> 1), cbWrittenTotal));
1516
1517	if (!pRegs->picb)
1518	{
1519	uint32_t new_sr = pRegs->sr & ~SR_CELV;
1520
1521	if (pRegs->bd.ctl_len & BD_IOC)
1522	{
1523	new_sr \|= SR_BCIS;
1524	}
1525
1526	if (pRegs->civ == pRegs->lvi)
1527	{
1528	/* Did we run out of data? */
1529	LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pRegs->civ, pRegs->lvi));
1530
1531	new_sr \|= SR_LVBCI \| SR_DCH \| SR_CELV;
1532	pThis->bup_flag = (pRegs->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1533
1534	rc = VINF_EOF;
1535	}
1536	else
1537	{
1538	pRegs->civ = pRegs->piv;
1539	pRegs->piv = (pRegs->piv + 1) % 32; /** @todo r=andy Define for max BDLEs? */
1540	ichac97StreamFetchBDLE(pThis, pStream);
1541	}
1542
1543	ichac97StreamUpdateStatus(pThis, pStream, new_sr);
1544	}
1545
1546	if (rc == VINF_EOF) /* All data processed? */
1547	break;
1548
1549	} while (RT_SUCCESS(rc));
1550
1551	LogFlowFuncLeaveRC(rc);
1552	return rc;
1553	}
1554
1555	/**
1556	* @callback_method_impl{FNIOMIOPORTIN}
1557	*/
1558	static DECLCALLBACK(int) ichac97IOPortNABMRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
1559	uint32_t *pu32Val, unsigned cbVal)
1560	{
1561	PAC97STATE pThis = (PAC97STATE)pvUser;
1562
1563	/* Get the index of the NABMBAR port. */
1564	const uint32_t uPortIdx = Port - pThis->IOPortBase[1];
1565
1566	PAC97STREAM pStream = ichac97GetStreamFromID(pThis, AC97_PORT2IDX(uPortIdx));
1567	PAC97BMREGS pRegs = pStream ? &pStream->Regs : NULL;
1568
1569	switch (cbVal)
1570	{
1571	case 1:
1572	{
1573	switch (uPortIdx)
1574	{
1575	case CAS:
1576	/* Codec Access Semaphore Register */
1577	LogFlowFunc(("CAS %d\n", pThis->cas));
1578	*pu32Val = pThis->cas;
1579	pThis->cas = 1;
1580	break;
1581	case PI_CIV:
1582	case PO_CIV:
1583	case MC_CIV:
1584	/* Current Index Value Register */
1585	*pu32Val = pRegs->civ;
1586	LogFlowFunc(("CIV[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1587	break;
1588	case PI_LVI:
1589	case PO_LVI:
1590	case MC_LVI:
1591	/* Last Valid Index Register */
1592	*pu32Val = pRegs->lvi;
1593	LogFlowFunc(("LVI[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1594	break;
1595	case PI_PIV:
1596	case PO_PIV:
1597	case MC_PIV:
1598	/* Prefetched Index Value Register */
1599	*pu32Val = pRegs->piv;
1600	LogFlowFunc(("PIV[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1601	break;
1602	case PI_CR:
1603	case PO_CR:
1604	case MC_CR:
1605	/* Control Register */
1606	*pu32Val = pRegs->cr;
1607	LogFlowFunc(("CR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1608	break;
1609	case PI_SR:
1610	case PO_SR:
1611	case MC_SR:
1612	/* Status Register (lower part) */
1613	pu32Val = pRegs->sr & 0xff; /* @todo r=andy Use RT_LO_U8. */
1614	LogFlowFunc(("SRb[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1615	break;
1616	default:
1617	*pu32Val = UINT32_MAX;
1618	LogFlowFunc(("U nabm readb %#x -> %#x\n", Port, *pu32Val));
1619	break;
1620	}
1621	break;
1622	}
1623
1624	case 2:
1625	{
1626	switch (uPortIdx)
1627	{
1628	case PI_SR:
1629	case PO_SR:
1630	case MC_SR:
1631	/* Status Register */
1632	*pu32Val = pRegs->sr;
1633	LogFlowFunc(("SR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1634	break;
1635	case PI_PICB:
1636	case PO_PICB:
1637	case MC_PICB:
1638	/* Position in Current Buffer */
1639	*pu32Val = pRegs->picb;
1640	LogFlowFunc(("PICB[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1641	break;
1642	default:
1643	*pu32Val = UINT32_MAX;
1644	LogFlowFunc(("U nabm readw %#x -> %#x\n", Port, *pu32Val));
1645	break;
1646	}
1647	break;
1648	}
1649
1650	case 4:
1651	{
1652	switch (uPortIdx)
1653	{
1654	case PI_BDBAR:
1655	case PO_BDBAR:
1656	case MC_BDBAR:
1657	/* Buffer Descriptor Base Address Register */
1658	*pu32Val = pRegs->bdbar;
1659	LogFlowFunc(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1660	break;
1661	case PI_CIV:
1662	case PO_CIV:
1663	case MC_CIV:
1664	/* 32-bit access: Current Index Value Register +
1665	* Last Valid Index Register +
1666	* Status Register */
1667	pu32Val = pRegs->civ \| (pRegs->lvi << 8) \| (pRegs->sr << 16); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
1668	LogFlowFunc(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
1669	AC97_PORT2IDX(uPortIdx), pRegs->civ, pRegs->lvi, pRegs->sr));
1670	break;
1671	case PI_PICB:
1672	case PO_PICB:
1673	case MC_PICB:
1674	/* 32-bit access: Position in Current Buffer Register +
1675	* Prefetched Index Value Register +
1676	* Control Register */
1677	pu32Val = pRegs->picb \| (pRegs->piv << 16) \| (pRegs->cr << 24); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
1678	LogFlowFunc(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
1679	AC97_PORT2IDX(uPortIdx), *pu32Val, pRegs->picb, pRegs->piv, pRegs->cr));
1680	break;
1681	case GLOB_CNT:
1682	/* Global Control */
1683	*pu32Val = pThis->glob_cnt;
1684	LogFlowFunc(("glob_cnt -> %#x\n", *pu32Val));
1685	break;
1686	case GLOB_STA:
1687	/* Global Status */
1688	*pu32Val = pThis->glob_sta \| GS_S0CR;
1689	LogFlowFunc(("glob_sta -> %#x\n", *pu32Val));
1690	break;
1691	default:
1692	*pu32Val = UINT32_MAX;
1693	LogFlowFunc(("U nabm readl %#x -> %#x\n", Port, *pu32Val));
1694	break;
1695	}
1696	break;
1697	}
1698
1699	default:
1700	return VERR_IOM_IOPORT_UNUSED;
1701	}
1702	return VINF_SUCCESS;
1703	}
1704
1705	/**
1706	* @callback_method_impl{FNIOMIOPORTOUT}
1707	*/
1708	static DECLCALLBACK(int) ichac97IOPortNABMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
1709	uint32_t u32Val, unsigned cbVal)
1710	{
1711	PAC97STATE pThis = (PAC97STATE)pvUser;
1712
1713	/* Get the index of the NABMBAR register. */
1714	const uint32_t uPortIdx = Port - pThis->IOPortBase[1];
1715
1716	PAC97STREAM pStream = ichac97GetStreamFromID(pThis, AC97_PORT2IDX(uPortIdx));
1717	PAC97BMREGS pRegs = pStream ? &pStream->Regs : NULL;
1718
1719	switch (cbVal)
1720	{
1721	case 1:
1722	{
1723	switch (uPortIdx)
1724	{
1725	case PI_LVI:
1726	case PO_LVI:
1727	case MC_LVI:
1728	/* Last Valid Index */
1729	if ((pRegs->cr & CR_RPBM) && (pRegs->sr & SR_DCH))
1730	{
1731	pRegs->sr &= ~(SR_DCH \| SR_CELV);
1732	pRegs->civ = pRegs->piv;
1733	pRegs->piv = (pRegs->piv + 1) % 32;
1734
1735	ichac97StreamFetchBDLE(pThis, pStream);
1736	}
1737	pRegs->lvi = u32Val % 32;
1738	LogFlowFunc(("LVI[%d] <- %#x\n", AC97_PORT2IDX(uPortIdx), u32Val));
1739	break;
1740	case PI_CR:
1741	case PO_CR:
1742	case MC_CR:
1743	{
1744	/* Control Register */
1745	if (u32Val & CR_RR) /* Busmaster reset */
1746	{
1747	ichac97StreamResetBMRegs(pThis, pStream);
1748	}
1749	else
1750	{
1751	pRegs->cr = u32Val & CR_VALID_MASK;
1752	if (!(pRegs->cr & CR_RPBM))
1753	{
1754	ichac97StreamSetActive(pThis, pStream, false /* fActive */);
1755	pRegs->sr \|= SR_DCH;
1756	}
1757	else
1758	{
1759	pRegs->civ = pRegs->piv;
1760	pRegs->piv = (pRegs->piv + 1) % 32;
1761
1762	ichac97StreamFetchBDLE(pThis, pStream);
1763
1764	pRegs->sr &= ~SR_DCH;
1765	ichac97StreamSetActive(pThis, pStream, true /* fActive */);
1766	}
1767	}
1768	LogFlowFunc(("CR[%d] <- %#x (cr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->cr));
1769	break;
1770	}
1771	case PI_SR:
1772	case PO_SR:
1773	case MC_SR:
1774	/* Status Register */
1775	pRegs->sr \|= u32Val & ~(SR_RO_MASK \| SR_WCLEAR_MASK);
1776	ichac97StreamUpdateStatus(pThis, pStream, pRegs->sr & ~(u32Val & SR_WCLEAR_MASK));
1777	LogFlowFunc(("SR[%d] <- %#x (sr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->sr));
1778	break;
1779	default:
1780	LogFlowFunc(("U nabm writeb %#x <- %#x\n", Port, u32Val));
1781	break;
1782	}
1783	break;
1784	}
1785
1786	case 2:
1787	{
1788	switch (uPortIdx)
1789	{
1790	case PI_SR:
1791	case PO_SR:
1792	case MC_SR:
1793	/* Status Register */
1794	pRegs->sr \|= u32Val & ~(SR_RO_MASK \| SR_WCLEAR_MASK);
1795	ichac97StreamUpdateStatus(pThis, pStream, pRegs->sr & ~(u32Val & SR_WCLEAR_MASK));
1796	LogFlowFunc(("SR[%d] <- %#x (sr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->sr));
1797	break;
1798	default:
1799	LogFlowFunc(("U nabm writew %#x <- %#x\n", Port, u32Val));
1800	break;
1801	}
1802	break;
1803	}
1804
1805	case 4:
1806	{
1807	switch (uPortIdx)
1808	{
1809	case PI_BDBAR:
1810	case PO_BDBAR:
1811	case MC_BDBAR:
1812	/* Buffer Descriptor list Base Address Register */
1813	pRegs->bdbar = u32Val & ~3;
1814	LogFlowFunc(("BDBAR[%d] <- %#x (bdbar %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->bdbar));
1815	break;
1816	case GLOB_CNT:
1817	/* Global Control */
1818	if (u32Val & GC_WR)
1819	ichac97WarmReset(pThis);
1820	if (u32Val & GC_CR)
1821	ichac97ColdReset(pThis);
1822	if (!(u32Val & (GC_WR \| GC_CR)))
1823	pThis->glob_cnt = u32Val & GC_VALID_MASK;
1824	LogFlowFunc(("glob_cnt <- %#x (glob_cnt %#x)\n", u32Val, pThis->glob_cnt));
1825	break;
1826	case GLOB_STA:
1827	/* Global Status */
1828	pThis->glob_sta &= ~(u32Val & GS_WCLEAR_MASK);
1829	pThis->glob_sta \|= (u32Val & ~(GS_WCLEAR_MASK \| GS_RO_MASK)) & GS_VALID_MASK;
1830	LogFlowFunc(("glob_sta <- %#x (glob_sta %#x)\n", u32Val, pThis->glob_sta));
1831	break;
1832	default:
1833	LogFlowFunc(("U nabm writel %#x <- %#x\n", Port, u32Val));
1834	break;
1835	}
1836	break;
1837	}
1838
1839	default:
1840	AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cbVal, u32Val));
1841	break;
1842	}
1843	return VINF_SUCCESS;
1844	}
1845
1846	/**
1847	* @callback_method_impl{FNIOMIOPORTIN}
1848	*/
1849	static DECLCALLBACK(int) ichac97IOPortNAMRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32Val, unsigned cbVal)
1850	{
1851	PAC97STATE pThis = (PAC97STATE)pvUser;
1852
1853	switch (cbVal)
1854	{
1855	case 1:
1856	{
1857	LogFlowFunc(("U nam readb %#x\n", Port));
1858	pThis->cas = 0;
1859	*pu32Val = UINT32_MAX;
1860	break;
1861	}
1862
1863	case 2:
1864	{
1865	uint32_t index = Port - pThis->IOPortBase[0];
1866	*pu32Val = UINT32_MAX;
1867	pThis->cas = 0;
1868	switch (index)
1869	{
1870	default:
1871	*pu32Val = ichac97MixerGet(pThis, index);
1872	LogFlowFunc(("nam readw %#x -> %#x\n", Port, *pu32Val));
1873	break;
1874	}
1875	break;
1876	}
1877
1878	case 4:
1879	{
1880	LogFlowFunc(("U nam readl %#x\n", Port));
1881	pThis->cas = 0;
1882	*pu32Val = UINT32_MAX;
1883	break;
1884	}
1885
1886	default:
1887	return VERR_IOM_IOPORT_UNUSED;
1888	}
1889	return VINF_SUCCESS;
1890	}
1891
1892	/**
1893	* @callback_method_impl{FNIOMIOPORTOUT}
1894	*/
1895	static DECLCALLBACK(int) ichac97IOPortNAMWrite(PPDMDEVINS pDevIns,
1896	void *pvUser, RTIOPORT Port, uint32_t u32Val, unsigned cbVal)
1897	{
1898	PAC97STATE pThis = (PAC97STATE)pvUser;
1899
1900	switch (cbVal)
1901	{
1902	case 1:
1903	{
1904	LogFlowFunc(("U nam writeb %#x <- %#x\n", Port, u32Val));
1905	pThis->cas = 0;
1906	break;
1907	}
1908
1909	case 2:
1910	{
1911	uint32_t index = Port - pThis->IOPortBase[0];
1912	pThis->cas = 0;
1913	switch (index)
1914	{
1915	case AC97_Reset:
1916	ichac97Reset(pThis->CTX_SUFF(pDevIns));
1917	break;
1918	case AC97_Powerdown_Ctrl_Stat:
1919	u32Val &= ~0xf;
1920	u32Val \|= ichac97MixerGet(pThis, index) & 0xf;
1921	ichac97MixerSet(pThis, index, u32Val);
1922	break;
1923	case AC97_Master_Volume_Mute:
1924	if (pThis->uCodecModel == Codec_AD1980)
1925	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AD_MISC_LOSEL)
1926	break; /* Register controls surround (rear), do nothing. */
1927	ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_VOLUME, u32Val);
1928	break;
1929	case AC97_Headphone_Volume_Mute:
1930	if (pThis->uCodecModel == Codec_AD1980)
1931	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AD_MISC_HPSEL)
1932	/* Register controls PCM (front) outputs. */
1933	ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_VOLUME, u32Val);
1934	break;
1935	case AC97_PCM_Out_Volume_Mute:
1936	ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_FRONT, u32Val);
1937	break;
1938	case AC97_Line_In_Volume_Mute:
1939	ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_LINE_IN, u32Val);
1940	break;
1941	case AC97_Record_Select:
1942	ichac97RecordSelect(pThis, u32Val);
1943	break;
1944	case AC97_Vendor_ID1:
1945	case AC97_Vendor_ID2:
1946	LogFlowFunc(("Attempt to write vendor ID to %#x\n", u32Val));
1947	break;
1948	case AC97_Extended_Audio_ID:
1949	LogFlowFunc(("Attempt to write extended audio ID to %#x\n", u32Val));
1950	break;
1951	case AC97_Extended_Audio_Ctrl_Stat:
1952	if (!(u32Val & EACS_VRA))
1953	{
1954	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 48000);
1955	ichac97StreamReInit(pThis, &pThis->StreamOut);
1956
1957	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 48000);
1958	ichac97StreamReInit(pThis, &pThis->StreamLineIn);
1959	}
1960	if (!(u32Val & EACS_VRM))
1961	{
1962	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 48000);
1963	ichac97StreamReInit(pThis, &pThis->StreamMicIn);
1964	}
1965	LogFlowFunc(("Setting extended audio control to %#x\n", u32Val));
1966	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32Val);
1967	break;
1968	case AC97_PCM_Front_DAC_Rate:
1969	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)
1970	{
1971	ichac97MixerSet(pThis, index, u32Val);
1972	LogFlowFunc(("Set front DAC rate to %RU32\n", u32Val));
1973	ichac97StreamReInit(pThis, &pThis->StreamOut);
1974	}
1975	else
1976	AssertMsgFailed(("Attempt to set front DAC rate to %RU32, but VRA is not set\n", u32Val));
1977	break;
1978	case AC97_MIC_ADC_Rate:
1979	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM)
1980	{
1981	ichac97MixerSet(pThis, index, u32Val);
1982	LogFlowFunc(("Set MIC ADC rate to %RU32\n", u32Val));
1983	ichac97StreamReInit(pThis, &pThis->StreamMicIn);
1984	}
1985	else
1986	AssertMsgFailed(("Attempt to set MIC ADC rate to %RU32, but VRM is not set\n", u32Val));
1987	break;
1988	case AC97_PCM_LR_ADC_Rate:
1989	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)
1990	{
1991	ichac97MixerSet(pThis, index, u32Val);
1992	LogFlowFunc(("Set front LR ADC rate to %RU32\n", u32Val));
1993	ichac97StreamReInit(pThis, &pThis->StreamLineIn);
1994	}
1995	else
1996	AssertMsgFailed(("Attempt to set LR ADC rate to %RU32, but VRA is not set\n", u32Val));
1997	break;
1998	default:
1999	LogFlowFunc(("U nam writew %#x <- %#x\n", Port, u32Val));
2000	ichac97MixerSet(pThis, index, u32Val);
2001	break;
2002	}
2003	break;
2004	}
2005
2006	case 4:
2007	{
2008	LogFlowFunc(("U nam writel %#x <- %#x\n", Port, u32Val));
2009	pThis->cas = 0;
2010	break;
2011	}
2012
2013	default:
2014	AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cbVal, u32Val));
2015	break;
2016	}
2017
2018	return VINF_SUCCESS;
2019	}
2020
2021
2022	/**
2023	* @callback_method_impl{FNPCIIOREGIONMAP}
2024	*/
2025	static DECLCALLBACK(int) ichac97IOPortMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
2026	PCIADDRESSSPACE enmType)
2027	{
2028	PPDMDEVINS pDevIns = pPciDev->pDevIns;
2029	PAC97STATE pThis = RT_FROM_MEMBER(pPciDev, AC97STATE, PciDev);
2030	RTIOPORT Port = (RTIOPORT)GCPhysAddress;
2031
2032	Assert(enmType == PCI_ADDRESS_SPACE_IO);
2033	Assert(cb >= 0x20);
2034
2035	if (iRegion < 0 \|\| iRegion > 1) /* We support 2 regions max. at the moment. */
2036	return VERR_INVALID_PARAMETER;
2037
2038	int rc;
2039	if (iRegion == 0)
2040	rc = PDMDevHlpIOPortRegister(pDevIns, Port, 256, pThis,
2041	ichac97IOPortNAMWrite, ichac97IOPortNAMRead,
2042	NULL, NULL, "ICHAC97 NAM");
2043	else
2044	rc = PDMDevHlpIOPortRegister(pDevIns, Port, 64, pThis,
2045	ichac97IOPortNABMWrite, ichac97IOPortNABMRead,
2046	NULL, NULL, "ICHAC97 NABM");
2047	if (RT_FAILURE(rc))
2048	return rc;
2049
2050	pThis->IOPortBase[iRegion] = Port;
2051	return VINF_SUCCESS;
2052	}
2053
2054	DECLINLINE(PAC97STREAM) ichac97GetStreamFromID(PAC97STATE pThis, uint32_t uID)
2055	{
2056	switch (uID)
2057	{
2058	case PI_INDEX: return &pThis->StreamLineIn;
2059	case MC_INDEX: return &pThis->StreamMicIn;
2060	case PO_INDEX: return &pThis->StreamOut;
2061	default: break;
2062	}
2063
2064	return NULL;
2065	}
2066
2067	#ifdef IN_RING3
2068	static int ichac97SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
2069	{
2070	PAC97BMREGS pRegs = &pStream->Regs;
2071
2072	SSMR3PutU32(pSSM, pRegs->bdbar);
2073	SSMR3PutU8( pSSM, pRegs->civ);
2074	SSMR3PutU8( pSSM, pRegs->lvi);
2075	SSMR3PutU16(pSSM, pRegs->sr);
2076	SSMR3PutU16(pSSM, pRegs->picb);
2077	SSMR3PutU8( pSSM, pRegs->piv);
2078	SSMR3PutU8( pSSM, pRegs->cr);
2079	SSMR3PutS32(pSSM, pRegs->bd_valid);
2080	SSMR3PutU32(pSSM, pRegs->bd.addr);
2081	SSMR3PutU32(pSSM, pRegs->bd.ctl_len);
2082
2083	return VINF_SUCCESS;
2084	}
2085
2086	/**
2087	* @callback_method_impl{FNSSMDEVSAVEEXEC}
2088	*/
2089	static DECLCALLBACK(int) ichac97SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2090	{
2091	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2092
2093	LogFlowFuncEnter();
2094
2095	SSMR3PutU32(pSSM, pThis->glob_cnt);
2096	SSMR3PutU32(pSSM, pThis->glob_sta);
2097	SSMR3PutU32(pSSM, pThis->cas);
2098
2099	/** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
2100	/* Note: The order the streams are saved here is critical, so don't touch. */
2101	int rc2 = ichac97SaveStream(pDevIns, pSSM, &pThis->StreamLineIn);
2102	AssertRC(rc2);
2103	rc2 = ichac97SaveStream(pDevIns, pSSM, &pThis->StreamOut);
2104	AssertRC(rc2);
2105	rc2 = ichac97SaveStream(pDevIns, pSSM, &pThis->StreamMicIn);
2106	AssertRC(rc2);
2107
2108	SSMR3PutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
2109
2110	uint8_t active[LAST_INDEX];
2111
2112	active[PI_INDEX] = ichac97StreamIsActive(pThis, &pThis->StreamLineIn) ? 1 : 0;
2113	active[PO_INDEX] = ichac97StreamIsActive(pThis, &pThis->StreamOut) ? 1 : 0;
2114	active[MC_INDEX] = ichac97StreamIsActive(pThis, &pThis->StreamMicIn) ? 1 : 0;
2115
2116	SSMR3PutMem(pSSM, active, sizeof(active));
2117
2118	LogFlowFuncLeaveRC(VINF_SUCCESS);
2119	return VINF_SUCCESS;
2120	}
2121
2122	static int ichac97LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
2123	{
2124	PAC97BMREGS pRegs = &pStream->Regs;
2125
2126	SSMR3GetU32(pSSM, &pRegs->bdbar);
2127	SSMR3GetU8( pSSM, &pRegs->civ);
2128	SSMR3GetU8( pSSM, &pRegs->lvi);
2129	SSMR3GetU16(pSSM, &pRegs->sr);
2130	SSMR3GetU16(pSSM, &pRegs->picb);
2131	SSMR3GetU8( pSSM, &pRegs->piv);
2132	SSMR3GetU8( pSSM, &pRegs->cr);
2133	SSMR3GetS32(pSSM, &pRegs->bd_valid);
2134	SSMR3GetU32(pSSM, &pRegs->bd.addr);
2135	SSMR3GetU32(pSSM, &pRegs->bd.ctl_len);
2136
2137	return VINF_SUCCESS;
2138	}
2139
2140	/**
2141	* @callback_method_impl{FNSSMDEVLOADEXEC}
2142	*/
2143	static DECLCALLBACK(int) ichac97LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2144	{
2145	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2146
2147	LogRel2(("ichac97LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
2148
2149	AssertMsgReturn (uVersion == AC97_SSM_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
2150	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2151
2152	SSMR3GetU32(pSSM, &pThis->glob_cnt);
2153	SSMR3GetU32(pSSM, &pThis->glob_sta);
2154	SSMR3GetU32(pSSM, &pThis->cas);
2155
2156	/** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
2157	/* Note: The order the streams are loaded here is critical, so don't touch. */
2158	int rc2 = ichac97LoadStream(pDevIns, pSSM, &pThis->StreamLineIn);
2159	AssertRC(rc2);
2160	rc2 = ichac97LoadStream(pDevIns, pSSM, &pThis->StreamOut);
2161	AssertRC(rc2);
2162	rc2 = ichac97LoadStream(pDevIns, pSSM, &pThis->StreamMicIn);
2163	AssertRC(rc2);
2164
2165	SSMR3GetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
2166
2167	/** @todo r=andy Stream IDs are hardcoded to certain streams. */
2168	uint8_t uaStrmsActive[LAST_INDEX];
2169	SSMR3GetMem(pSSM, uaStrmsActive, sizeof(uaStrmsActive));
2170
2171	ichac97RecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
2172	# define V_(a, b) ichac97MixerSetVolume(pThis, a, b, ichac97MixerGet(pThis, a))
2173	V_(AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME);
2174	V_(AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT);
2175	V_(AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN);
2176	# undef V_
2177	if (pThis->uCodecModel == Codec_AD1980)
2178	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AD_MISC_HPSEL)
2179	ichac97MixerSetVolume(pThis, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME,
2180	ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
2181
2182	int rc = ichac97StreamsInit(pThis);
2183	if (RT_SUCCESS(rc))
2184	{
2185	/** @todo r=andy Stream IDs are hardcoded to certain streams. */
2186	rc = ichac97StreamSetActive(pThis, &pThis->StreamLineIn, RT_BOOL(uaStrmsActive[PI_INDEX]));
2187	if (RT_SUCCESS(rc))
2188	rc = ichac97StreamSetActive(pThis, &pThis->StreamMicIn, RT_BOOL(uaStrmsActive[MC_INDEX]));
2189	if (RT_SUCCESS(rc))
2190	rc = ichac97StreamSetActive(pThis, &pThis->StreamOut, RT_BOOL(uaStrmsActive[PO_INDEX]));
2191	}
2192
2193	pThis->bup_flag = 0;
2194	pThis->last_samp = 0;
2195
2196	LogFlowFuncLeaveRC(rc);
2197	return rc;
2198	}
2199
2200
2201	/**
2202	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
2203	*/
2204	static DECLCALLBACK(void ) ichac97QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
2205	{
2206	PAC97STATE pThis = RT_FROM_MEMBER(pInterface, AC97STATE, IBase);
2207	Assert(&pThis->IBase == pInterface);
2208
2209	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2210	return NULL;
2211	}
2212
2213
2214	/**
2215	* Powers off the device.
2216	*
2217	* @param pDevIns Device instance to power off.
2218	*/
2219	static DECLCALLBACK(void) ichac97PowerOff(PPDMDEVINS pDevIns)
2220	{
2221	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2222
2223	LogRel2(("AC97: Powering off ...\n"));
2224
2225	/**
2226	* Note: Destroy the mixer while powering off and not in ichac97Destruct,
2227	* giving the mixer the chance to release any references held to
2228	* PDM audio streams it maintains.
2229	*/
2230	if (pThis->pMixer)
2231	{
2232	AudioMixerDestroy(pThis->pMixer);
2233	pThis->pMixer = NULL;
2234	}
2235	}
2236
2237
2238	/**
2239	* @interface_method_impl{PDMDEVREG,pfnReset}
2240	*
2241	* @remarks The original sources didn't install a reset handler, but it seems to
2242	* make sense to me so we'll do it.
2243	*/
2244	static DECLCALLBACK(void) ichac97Reset(PPDMDEVINS pDevIns)
2245	{
2246	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2247
2248	LogFlowFuncEnter();
2249
2250	/*
2251	* Reset the device state (will need pDrv later).
2252	*/
2253	ichac97StreamResetBMRegs(pThis, &pThis->StreamLineIn);
2254	ichac97StreamResetBMRegs(pThis, &pThis->StreamMicIn);
2255	ichac97StreamResetBMRegs(pThis, &pThis->StreamOut);
2256
2257	/*
2258	* Reset the mixer too. The Windows XP driver seems to rely on
2259	* this. At least it wants to read the vendor id before it resets
2260	* the codec manually.
2261	*/
2262	ichac97MixerReset(pThis);
2263
2264	/*
2265	* Stop any audio currently playing and/or recording.
2266	*/
2267	AudioMixerSinkCtl(pThis->pSinkOutput, AUDMIXSINKCMD_DISABLE);
2268	AudioMixerSinkCtl(pThis->pSinkMicIn, AUDMIXSINKCMD_DISABLE);
2269	AudioMixerSinkCtl(pThis->pSinkLineIn, AUDMIXSINKCMD_DISABLE);
2270
2271	/*
2272	* Reset all streams.
2273	*/
2274	ichac97StreamReset(pThis, &pThis->StreamLineIn);
2275	ichac97StreamReset(pThis, &pThis->StreamMicIn);
2276	ichac97StreamReset(pThis, &pThis->StreamOut);
2277
2278	LogRel(("AC97: Reset\n"));
2279	}
2280
2281
2282	/**
2283	* @interface_method_impl{PDMDEVREG,pfnDestruct}
2284	*/
2285	static DECLCALLBACK(int) ichac97Destruct(PPDMDEVINS pDevIns)
2286	{
2287	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2288
2289	LogFlowFuncEnter();
2290
2291	ichac97StreamDestroy(&pThis->StreamLineIn);
2292	ichac97StreamDestroy(&pThis->StreamMicIn);
2293	ichac97StreamDestroy(&pThis->StreamOut);
2294
2295	PAC97DRIVER pDrv, pDrvNext;
2296	RTListForEachSafe(&pThis->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
2297	{
2298	RTListNodeRemove(&pDrv->Node);
2299	RTMemFree(pDrv);
2300	}
2301
2302	/* Sanity. */
2303	Assert(RTListIsEmpty(&pThis->lstDrv));
2304
2305	LogFlowFuncLeave();
2306	return VINF_SUCCESS;
2307	}
2308
2309
2310	/**
2311	* Attach command, internal version.
2312	*
2313	* This is called to let the device attach to a driver for a specified LUN
2314	* during runtime. This is not called during VM construction, the device
2315	* constructor has to attach to all the available drivers.
2316	*
2317	* @returns VBox status code.
2318	* @param pDevIns The device instance.
2319	* @param pDrv Driver to (re-)use for (re-)attaching to.
2320	* If NULL is specified, a new driver will be created and appended
2321	* to the driver list.
2322	* @param uLUN The logical unit which is being detached.
2323	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
2324	*/
2325	static DECLCALLBACK(int) ichac97AttachInternal(PPDMDEVINS pDevIns, PAC97DRIVER pDrv, unsigned uLUN, uint32_t fFlags)
2326	{
2327	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2328
2329	/*
2330	* Attach driver.
2331	*/
2332	char *pszDesc = NULL;
2333	if (RTStrAPrintf(&pszDesc, "Audio driver port (AC'97) for LUN #%u", uLUN) <= 0)
2334	AssertReleaseMsgReturn(pszDesc,
2335	("Not enough memory for AC'97 driver port description of LUN #%u\n", uLUN),
2336	VERR_NO_MEMORY);
2337
2338	PPDMIBASE pDrvBase;
2339	int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
2340	&pThis->IBase, &pDrvBase, pszDesc);
2341	if (RT_SUCCESS(rc))
2342	{
2343	if (pDrv == NULL)
2344	pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
2345	if (pDrv)
2346	{
2347	pDrv->pDrvBase = pDrvBase;
2348	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
2349	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN #%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
2350	pDrv->pAC97State = pThis;
2351	pDrv->uLUN = uLUN;
2352
2353	/*
2354	* For now we always set the driver at LUN 0 as our primary
2355	* host backend. This might change in the future.
2356	*/
2357	if (pDrv->uLUN == 0)
2358	pDrv->Flags \|= PDMAUDIODRVFLAG_PRIMARY;
2359
2360	LogFunc(("LUN#%RU8: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
2361
2362	/* Attach to driver list if not attached yet. */
2363	if (!pDrv->fAttached)
2364	{
2365	RTListAppend(&pThis->lstDrv, &pDrv->Node);
2366	pDrv->fAttached = true;
2367	}
2368	}
2369	else
2370	rc = VERR_NO_MEMORY;
2371	}
2372	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2373	LogFunc(("No attached driver for LUN #%u\n", uLUN));
2374
2375	if (RT_FAILURE(rc))
2376	{
2377	/* Only free this string on failure;
2378	* must remain valid for the live of the driver instance. */
2379	RTStrFree(pszDesc);
2380	}
2381
2382	LogFunc(("iLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
2383	return rc;
2384	}
2385
2386
2387	/**
2388	* Attach command.
2389	*
2390	* This is called to let the device attach to a driver for a specified LUN
2391	* during runtime. This is not called during VM construction, the device
2392	* constructor has to attach to all the available drivers.
2393	*
2394	* @returns VBox status code.
2395	* @param pDevIns The device instance.
2396	* @param uLUN The logical unit which is being detached.
2397	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
2398	*/
2399	static DECLCALLBACK(int) ichac97Attach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
2400	{
2401	return ichac97AttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
2402	}
2403
2404	static DECLCALLBACK(void) ichac97Detach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
2405	{
2406	LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
2407	}
2408
2409	/**
2410	* Re-attach.
2411	*
2412	* @returns VBox status code.
2413	* @param pThis Device instance.
2414	* @param pDrv Driver instance used for attaching to.
2415	* If NULL is specified, a new driver will be created and appended
2416	* to the driver list.
2417	* @param uLUN The logical unit which is being re-detached.
2418	* @param pszDriver Driver name.
2419	*/
2420	static int ichac97Reattach(PAC97STATE pThis, PAC97DRIVER pDrv, uint8_t uLUN, const char *pszDriver)
2421	{
2422	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2423	AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
2424
2425	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2426	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
2427	PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/ichac97/0/");
2428
2429	/* Remove LUN branch. */
2430	CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
2431
2432	if (pDrv)
2433	{
2434	/* Re-use a driver instance => detach the driver before. */
2435	int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
2436	if (RT_FAILURE(rc))
2437	return rc;
2438	}
2439
2440	#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
2441
2442	int rc;
2443	do
2444	{
2445	PCFGMNODE pLunL0;
2446	rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
2447	rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
2448	rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
2449
2450	PCFGMNODE pLunL1, pLunL2;
2451	rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
2452	rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
2453	rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
2454
2455	rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
2456
2457	} while (0);
2458
2459	if (RT_SUCCESS(rc))
2460	rc = ichac97AttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
2461
2462	LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
2463
2464	#undef RC_CHECK
2465
2466	return rc;
2467	}
2468
2469	/**
2470	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2471	*/
2472	static DECLCALLBACK(int) ichac97Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2473	{
2474	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2475
2476	/* NB: This must be done before any possible failure (and running the destructor). */
2477	RTListInit(&pThis->lstDrv);
2478
2479	Assert(iInstance == 0);
2480	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2481
2482	/*
2483	* Validations.
2484	*/
2485	if (!CFGMR3AreValuesValid(pCfg,
2486	"Codec\0"
2487	"TimerHz\0"))
2488	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2489	N_("Invalid configuration for the AC'97 device"));
2490
2491	/*
2492	* Read config data.
2493	*/
2494	char szCodec[20];
2495	int rc = CFGMR3QueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
2496	if (RT_FAILURE(rc))
2497	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2498	N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
2499
2500	#ifndef VBOX_WITH_AUDIO_CALLBACKS
2501	uint16_t uTimerHz;
2502	rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, AC97_TIMER_HZ /* Default value, if not set. */);
2503	if (RT_FAILURE(rc))
2504	return PDMDEV_SET_ERROR(pDevIns, rc,
2505	N_("AC'97 configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
2506	#endif
2507
2508	/*
2509	* The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
2510	* in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
2511	* 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
2512	*/
2513	bool fChipAD1980 = false;
2514	if (!strcmp(szCodec, "STAC9700"))
2515	pThis->uCodecModel = Codec_STAC9700;
2516	else if (!strcmp(szCodec, "AD1980"))
2517	pThis->uCodecModel = Codec_AD1980;
2518	else if (!strcmp(szCodec, "AD1981B"))
2519	pThis->uCodecModel = Codec_AD1981B;
2520	else
2521	{
2522	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
2523	N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"),
2524	szCodec);
2525	}
2526
2527	/*
2528	* Initialize data (most of it anyway).
2529	*/
2530	pThis->pDevInsR3 = pDevIns;
2531	/* IBase */
2532	pThis->IBase.pfnQueryInterface = ichac97QueryInterface;
2533
2534	/* PCI Device (the assertions will be removed later) */
2535	PCIDevSetVendorId (&pThis->PciDev, 0x8086); /* 00 ro - intel. */ Assert(pThis->PciDev.config[0x00] == 0x86); Assert(pThis->PciDev.config[0x01] == 0x80);
2536	PCIDevSetDeviceId (&pThis->PciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pThis->PciDev.config[0x02] == 0x15); Assert(pThis->PciDev.config[0x03] == 0x24);
2537	PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pThis->PciDev.config[0x04] == 0x00); Assert(pThis->PciDev.config[0x05] == 0x00);
2538	PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM \| VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pThis->PciDev.config[0x06] == 0x80); Assert(pThis->PciDev.config[0x07] == 0x02);
2539	PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */ Assert(pThis->PciDev.config[0x08] == 0x01);
2540	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */ Assert(pThis->PciDev.config[0x09] == 0x00);
2541	PCIDevSetClassSub (&pThis->PciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pThis->PciDev.config[0x0a] == 0x01);
2542	PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */ Assert(pThis->PciDev.config[0x0b] == 0x04);
2543	PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */ Assert(pThis->PciDev.config[0x0e] == 0x00);
2544	PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - nambar - native audio mixer base. */
2545	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pThis->PciDev.config[0x10] == 0x01); Assert(pThis->PciDev.config[0x11] == 0x00); Assert(pThis->PciDev.config[0x12] == 0x00); Assert(pThis->PciDev.config[0x13] == 0x00);
2546	PCIDevSetBaseAddress (&pThis->PciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
2547	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pThis->PciDev.config[0x14] == 0x01); Assert(pThis->PciDev.config[0x15] == 0x00); Assert(pThis->PciDev.config[0x16] == 0x00); Assert(pThis->PciDev.config[0x17] == 0x00);
2548	PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */ Assert(pThis->PciDev.config[0x3c] == 0x00);
2549	PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */ Assert(pThis->PciDev.config[0x3d] == 0x01);
2550
2551	if (pThis->uCodecModel == Codec_AD1980)
2552	{
2553	PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x1028); /* 2c ro - Dell.) */
2554	PCIDevSetSubSystemId (&pThis->PciDev, 0x0177); /* 2e ro. */
2555	}
2556	else if (pThis->uCodecModel == Codec_AD1981B)
2557	{
2558	PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x1028); /* 2c ro - Dell.) */
2559	PCIDevSetSubSystemId (&pThis->PciDev, 0x01ad); /* 2e ro. */
2560	}
2561	else
2562	{
2563	PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x8086); /* 2c ro - Intel.) */
2564	PCIDevSetSubSystemId (&pThis->PciDev, 0x0000); /* 2e ro. */
2565	}
2566
2567	/*
2568	* Register the PCI device, it's I/O regions, the timer and the
2569	* saved state item.
2570	*/
2571	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
2572	if (RT_FAILURE(rc))
2573	return rc;
2574
2575	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 256, PCI_ADDRESS_SPACE_IO, ichac97IOPortMap);
2576	if (RT_FAILURE(rc))
2577	return rc;
2578
2579	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 64, PCI_ADDRESS_SPACE_IO, ichac97IOPortMap);
2580	if (RT_FAILURE(rc))
2581	return rc;
2582
2583	rc = PDMDevHlpSSMRegister(pDevIns, AC97_SSM_VERSION, sizeof(*pThis), ichac97SaveExec, ichac97LoadExec);
2584	if (RT_FAILURE(rc))
2585	return rc;
2586
2587	/*
2588	* Attach driver.
2589	*/
2590	uint8_t uLUN;
2591	for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
2592	{
2593	LogFunc(("Trying to attach driver for LUN #%RU8 ...\n", uLUN));
2594	rc = ichac97AttachInternal(pDevIns, NULL /* pDrv /, uLUN, 0 / fFlags */);
2595	if (RT_FAILURE(rc))
2596	{
2597	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2598	rc = VINF_SUCCESS;
2599	else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
2600	{
2601	ichac97Reattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
2602	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
2603	N_("No audio devices could be opened. Selecting the NULL audio backend "
2604	"with the consequence that no sound is audible"));
2605	/* attaching to the NULL audio backend will never fail */
2606	rc = VINF_SUCCESS;
2607	}
2608	break;
2609	}
2610	}
2611
2612	LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
2613
2614	if (RT_SUCCESS(rc))
2615	{
2616	rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThis->pMixer);
2617	if (RT_SUCCESS(rc))
2618	{
2619	/* Set a default audio format for our mixer. */
2620	PDMAUDIOSTREAMCFG streamCfg;
2621	streamCfg.uHz = 44100;
2622	streamCfg.cChannels = 2;
2623	streamCfg.enmFormat = PDMAUDIOFMT_S16;
2624	streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
2625
2626	rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
2627	AssertRC(rc);
2628
2629	/* Add all required audio sinks. */
2630	int rc2 = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output", AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
2631	AssertRC(rc2);
2632
2633	rc2 = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In", AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
2634	AssertRC(rc2);
2635
2636	rc2 = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In", AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
2637	AssertRC(rc2);
2638	}
2639	}
2640
2641	ichac97Reset(pDevIns);
2642
2643	if (RT_SUCCESS(rc))
2644	{
2645	ichac97StreamsInit(pThis);
2646
2647	PAC97DRIVER pDrv;
2648	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
2649	{
2650	/*
2651	* Only primary drivers are critical for the VM to run. Everything else
2652	* might not worth showing an own error message box in the GUI.
2653	*/
2654	if (!(pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY))
2655	continue;
2656
2657	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
2658	AssertPtr(pCon);
2659
2660	bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
2661	bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
2662	bool fValidOut = AudioMixerStreamIsValid(pDrv->Out.pMixStrm);
2663
2664	if ( !fValidLineIn
2665	&& !fValidMicIn
2666	&& !fValidOut)
2667	{
2668	LogRel(("AC97: Falling back to NULL backend (no sound audible)\n"));
2669
2670	/* Destroy the streams before re-attaching the NULL driver. */
2671	ichac97StreamsDestroy(pThis);
2672
2673	ichac97Reset(pDevIns);
2674	ichac97Reattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
2675
2676	ichac97StreamsInit(pThis);
2677
2678	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
2679	N_("No audio devices could be opened. Selecting the NULL audio backend "
2680	"with the consequence that no sound is audible"));
2681	}
2682	else
2683	{
2684	bool fWarn = false;
2685
2686	PDMAUDIOBACKENDCFG backendCfg;
2687	int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
2688	if (RT_SUCCESS(rc2))
2689	{
2690	if (backendCfg.cSources)
2691	{
2692	/* If the audio backend supports two or more input streams at once,
2693	* warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
2694	if (backendCfg.cMaxStreamsIn >= 2)
2695	fWarn = !fValidLineIn \|\| !fValidMicIn;
2696	/* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
2697	* not ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
2698	* One of the two simply is not in use then. */
2699	else if (backendCfg.cMaxStreamsIn == 1)
2700	fWarn = !fValidLineIn && !fValidMicIn;
2701	/* Don't warn if our backend is not able of supporting any input streams at all. */
2702	}
2703
2704	if ( !fWarn
2705	&& backendCfg.cSinks)
2706	{
2707	fWarn = !fValidOut;
2708	}
2709	}
2710	else
2711	AssertReleaseMsgFailed(("Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n",
2712	pDrv->uLUN, rc2));
2713
2714	if (fWarn)
2715	{
2716	char szMissingStreams[255];
2717	size_t len = 0;
2718	if (!fValidLineIn)
2719	{
2720	LogRel(("AC97: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
2721	len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
2722	}
2723	if (!fValidMicIn)
2724	{
2725	LogRel(("AC97: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
2726	len += RTStrPrintf(szMissingStreams + len,
2727	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
2728	}
2729	if (!fValidOut)
2730	{
2731	LogRel(("AC97: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
2732	len += RTStrPrintf(szMissingStreams + len,
2733	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
2734	}
2735
2736	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
2737	N_("Some AC'97 audio streams (%s) could not be opened. Guest applications generating audio "
2738	"output or depending on audio input may hang. Make sure your host audio device "
2739	"is working properly. Check the logfile for error messages of the audio "
2740	"subsystem"), szMissingStreams);
2741	}
2742	}
2743	}
2744	}
2745
2746	# ifndef VBOX_WITH_AUDIO_CALLBACKS
2747	if (RT_SUCCESS(rc))
2748	{
2749	/* Start the emulation timer. */
2750	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, ichac97Timer, pThis,
2751	TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchAc97", &pThis->pTimer);
2752	AssertRCReturn(rc, rc);
2753
2754	if (RT_SUCCESS(rc))
2755	{
2756	pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
2757	pThis->uTimerTS = TMTimerGet(pThis->pTimer);
2758	LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
2759
2760	ichac97TimerMaybeStart(pThis);
2761	}
2762	}
2763	# else
2764	if (RT_SUCCESS(rc))
2765	{
2766	PAC97DRIVER pDrv;
2767	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
2768	{
2769	/* Only register primary driver.
2770	* The device emulation does the output multiplexing then. */
2771	if (!(pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY))
2772	continue;
2773
2774	PDMAUDIOCALLBACK AudioCallbacks[2];
2775
2776	AC97CALLBACKCTX Ctx = { pThis, pDrv };
2777
2778	AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
2779	AudioCallbacks[0].pfnCallback = ac97CallbackInput;
2780	AudioCallbacks[0].pvCtx = &Ctx;
2781	AudioCallbacks[0].cbCtx = sizeof(AC97CALLBACKCTX);
2782
2783	AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
2784	AudioCallbacks[1].pfnCallback = ac97CallbackOutput;
2785	AudioCallbacks[1].pvCtx = &Ctx;
2786	AudioCallbacks[1].cbCtx = sizeof(AC97CALLBACKCTX);
2787
2788	rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
2789	if (RT_FAILURE(rc))
2790	break;
2791	}
2792	}
2793	# endif
2794
2795	# ifdef VBOX_WITH_STATISTICS
2796	if (RT_SUCCESS(rc))
2797	{
2798	/*
2799	* Register statistics.
2800	*/
2801	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/AC97/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
2802	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/AC97/BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
2803	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/AC97/BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
2804	}
2805	# endif
2806
2807	LogFlowFuncLeaveRC(rc);
2808	return rc;
2809	}
2810
2811	/**
2812	* The device registration structure.
2813	*/
2814	const PDMDEVREG g_DeviceICHAC97 =
2815	{
2816	/* u32Version */
2817	PDM_DEVREG_VERSION,
2818	/* szName */
2819	"ichac97",
2820	/* szRCMod */
2821	"",
2822	/* szR0Mod */
2823	"",
2824	/* pszDescription */
2825	"ICH AC'97 Audio Controller",
2826	/* fFlags */
2827	PDM_DEVREG_FLAGS_DEFAULT_BITS,
2828	/* fClass */
2829	PDM_DEVREG_CLASS_AUDIO,
2830	/* cMaxInstances */
2831	1,
2832	/* cbInstance */
2833	sizeof(AC97STATE),
2834	/* pfnConstruct */
2835	ichac97Construct,
2836	/* pfnDestruct */
2837	ichac97Destruct,
2838	/* pfnRelocate */
2839	NULL,
2840	/* pfnMemSetup */
2841	NULL,
2842	/* pfnPowerOn */
2843	NULL,
2844	/* pfnReset */
2845	ichac97Reset,
2846	/* pfnSuspend */
2847	NULL,
2848	/* pfnResume */
2849	NULL,
2850	/* pfnAttach */
2851	ichac97Attach,
2852	/* pfnDetach */
2853	ichac97Detach,
2854	/* pfnQueryInterface. */
2855	NULL,
2856	/* pfnInitComplete */
2857	NULL,
2858	/* pfnPowerOff */
2859	ichac97PowerOff,
2860	/* pfnSoftReset */
2861	NULL,
2862	/* u32VersionEnd */
2863	PDM_DEVREG_VERSION
2864	};
2865
2866	#endif /* !IN_RING3 */
2867	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 61523

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