DevIchAc97.cpp@ 61613

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1	/* $Id: DevIchAc97.cpp 61613 2016-06-09 10:33:54Z vboxsync $ */
2	/** @file
3	* DevIchAc97 - VBox ICH AC97 Audio Controller.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_AC97
23	#include <VBox/log.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/vmm/pdmaudioifs.h>
26
27	#include <iprt/assert.h>
28	#ifdef IN_RING3
29	# ifdef DEBUG
30	# include <iprt/file.h>
31	# endif
32	# include <iprt/mem.h>
33	# include <iprt/string.h>
34	# include <iprt/uuid.h>
35	#endif
36
37	#include "VBoxDD.h"
38
39	#include "AudioMixBuffer.h"
40	#include "AudioMixer.h"
41	#include "DrvAudio.h"
42
43
44	/*********************************************************************************************************************************
45	* Defined Constants And Macros *
46	*********************************************************************************************************************************/
47
48	#ifdef DEBUG_andy
49	/*
50	* AC97_DEBUG_DUMP_PCM_DATA enables dumping the raw PCM data
51	* to a file on the host. Be sure to adjust AC97_DEBUG_DUMP_PCM_DATA_PATH
52	* to your needs before using this!
53	*/
54	# define AC97_DEBUG_DUMP_PCM_DATA
55	# ifdef RT_OS_WINDOWS
56	# define AC97_DEBUG_DUMP_PCM_DATA_PATH "c:\\temp\\"
57	# else
58	# define AC97_DEBUG_DUMP_PCM_DATA_PATH "/tmp/"
59	# endif
60	#endif /* DEBUG_andy */
61
62	#define AC97_SSM_VERSION 1
63
64	#define AC97_TIMER_HZ 50
65
66	/** @todo Use AC97_ prefixes! */
67	#define SR_FIFOE RT_BIT(4) /* rwc, FIFO error. */
68	#define SR_BCIS RT_BIT(3) /* rwc, Buffer completion interrupt status. */
69	#define SR_LVBCI RT_BIT(2) /* rwc, Last valid buffer completion interrupt. */
70	#define SR_CELV RT_BIT(1) /* ro, Current equals last valid. */
71	#define SR_DCH RT_BIT(0) /* ro, Controller halted. */
72	#define SR_VALID_MASK (RT_BIT(5) - 1)
73	#define SR_WCLEAR_MASK (SR_FIFOE \| SR_BCIS \| SR_LVBCI)
74	#define SR_RO_MASK (SR_DCH \| SR_CELV)
75	#define SR_INT_MASK (SR_FIFOE \| SR_BCIS \| SR_LVBCI)
76
77	#define CR_IOCE RT_BIT(4) /* rw, Interrupt On Completion Enable. */
78	#define CR_FEIE RT_BIT(3) /* rw FIFO Error Interrupt Enable. */
79	#define CR_LVBIE RT_BIT(2) /* rw Last Valid Buffer Interrupt Enable. */
80	#define CR_RR RT_BIT(1) /* rw Reset Registers. */
81	#define CR_RPBM RT_BIT(0) /* rw Run/Pause Bus Master. */
82	#define CR_VALID_MASK (RT_BIT(5) - 1)
83	#define CR_DONT_CLEAR_MASK (CR_IOCE \| CR_FEIE \| CR_LVBIE)
84
85	#define GC_WR 4 /* rw */
86	#define GC_CR 2 /* rw */
87	#define GC_VALID_MASK (RT_BIT(6) - 1)
88
89	#define GS_MD3 RT_BIT(17) /* rw */
90	#define GS_AD3 RT_BIT(16) /* rw */
91	#define GS_RCS RT_BIT(15) /* rwc */
92	#define GS_B3S12 RT_BIT(14) /* ro */
93	#define GS_B2S12 RT_BIT(13) /* ro */
94	#define GS_B1S12 RT_BIT(12) /* ro */
95	#define GS_S1R1 RT_BIT(11) /* rwc */
96	#define GS_S0R1 RT_BIT(10) /* rwc */
97	#define GS_S1CR RT_BIT(9) /* ro */
98	#define GS_S0CR RT_BIT(8) /* ro */
99	#define GS_MINT RT_BIT(7) /* ro */
100	#define GS_POINT RT_BIT(6) /* ro */
101	#define GS_PIINT RT_BIT(5) /* ro */
102	#define GS_RSRVD (RT_BIT(4)\|RT_BIT(3))
103	#define GS_MOINT RT_BIT(2) /* ro */
104	#define GS_MIINT RT_BIT(1) /* ro */
105	#define GS_GSCI RT_BIT(0) /* rwc */
106	#define GS_RO_MASK (GS_B3S12 \| \
107	GS_B2S12 \| \
108	GS_B1S12 \| \
109	GS_S1CR \| \
110	GS_S0CR \| \
111	GS_MINT \| \
112	GS_POINT \| \
113	GS_PIINT \| \
114	GS_RSRVD \| \
115	GS_MOINT \| \
116	GS_MIINT)
117	#define GS_VALID_MASK (RT_BIT(18) - 1)
118	#define GS_WCLEAR_MASK (GS_RCS\|GS_S1R1\|GS_S0R1\|GS_GSCI)
119
120	/** @name Buffer Descriptor
121	* @{ */
122	#define BD_IOC RT_BIT(31) /*< Interrupt on Completion. /
123	#define BD_BUP RT_BIT(30) /*< Buffer Underrun Policy. /
124
125	#define BD_MAX_LEN_MASK 0xFFFE
126	/** @} */
127
128	/** @name Extended Audio Status and Control Register
129	* @{ */
130	#define EACS_VRA 1 /*< Variable Rate Audio (4.2.1.1). /
131	#define EACS_VRM 8 /*< Variable Rate Mic Audio (4.2.1.1). /
132	/** @} */
133
134	#define VOL_MASK 0x1f
135	#define MUTE_SHIFT 15
136
137	#define REC_MASK 7
138	enum
139	{
140	REC_MIC = 0,
141	REC_CD,
142	REC_VIDEO,
143	REC_AUX,
144	REC_LINE_IN,
145	REC_STEREO_MIX,
146	REC_MONO_MIX,
147	REC_PHONE
148	};
149
150	enum
151	{
152	AC97_Reset = 0x00,
153	AC97_Master_Volume_Mute = 0x02,
154	AC97_Headphone_Volume_Mute = 0x04, /** Also known as AUX, see table 16, section 5.7. */
155	AC97_Master_Volume_Mono_Mute = 0x06,
156	AC97_Master_Tone_RL = 0x08,
157	AC97_PC_BEEP_Volume_Mute = 0x0A,
158	AC97_Phone_Volume_Mute = 0x0C,
159	AC97_Mic_Volume_Mute = 0x0E,
160	AC97_Line_In_Volume_Mute = 0x10,
161	AC97_CD_Volume_Mute = 0x12,
162	AC97_Video_Volume_Mute = 0x14,
163	AC97_Aux_Volume_Mute = 0x16,
164	AC97_PCM_Out_Volume_Mute = 0x18,
165	AC97_Record_Select = 0x1A,
166	AC97_Record_Gain_Mute = 0x1C,
167	AC97_Record_Gain_Mic_Mute = 0x1E,
168	AC97_General_Purpose = 0x20,
169	AC97_3D_Control = 0x22,
170	AC97_AC_97_RESERVED = 0x24,
171	AC97_Powerdown_Ctrl_Stat = 0x26,
172	AC97_Extended_Audio_ID = 0x28,
173	AC97_Extended_Audio_Ctrl_Stat = 0x2A,
174	AC97_PCM_Front_DAC_Rate = 0x2C,
175	AC97_PCM_Surround_DAC_Rate = 0x2E,
176	AC97_PCM_LFE_DAC_Rate = 0x30,
177	AC97_PCM_LR_ADC_Rate = 0x32,
178	AC97_MIC_ADC_Rate = 0x34,
179	AC97_6Ch_Vol_C_LFE_Mute = 0x36,
180	AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
181	AC97_Vendor_Reserved = 0x58,
182	AC97_AD_Misc = 0x76,
183	AC97_Vendor_ID1 = 0x7c,
184	AC97_Vendor_ID2 = 0x7e
185	};
186
187	/* Codec models. */
188	enum {
189	Codec_STAC9700 = 0, /* SigmaTel STAC9700 */
190	Codec_AD1980, /* Analog Devices AD1980 */
191	Codec_AD1981B /* Analog Devices AD1981B */
192	};
193
194	/* Analog Devices miscellaneous regiter bits used in AD1980. */
195	#define AD_MISC_LOSEL RT_BIT(5) /* Surround (rear) goes to line out outputs. */
196	#define AD_MISC_HPSEL RT_BIT(10) /* PCM (front) goes to headphone outputs. */
197
198	#define ICHAC97STATE_2_DEVINS(a_pAC97) ((a_pAC97)->pDevInsR3)
199
200	enum
201	{
202	BUP_SET = RT_BIT(0),
203	BUP_LAST = RT_BIT(1)
204	};
205
206	/** Emits registers for a specific (Native Audio Bus Master BAR) NABMBAR. */
207	#define AC97_NABMBAR_REGS(prefix, off) \
208	enum { \
209	prefix ## _BDBAR = off, /* Buffer Descriptor Base Address */ \
210	prefix ## _CIV = off + 4, /* Current Index Value */ \
211	prefix ## _LVI = off + 5, /* Last Valid Index */ \
212	prefix ## _SR = off + 6, /* Status Register */ \
213	prefix ## _PICB = off + 8, /* Position in Current Buffer */ \
214	prefix ## _PIV = off + 10, /* Prefetched Index Value */ \
215	prefix ## _CR = off + 11 /* Control Register */ \
216	}
217
218	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
219	typedef enum
220	{
221	PI_INDEX = 0, /** PCM in */
222	PO_INDEX, /** PCM out */
223	MC_INDEX, /** Mic in */
224	LAST_INDEX
225	} AC97SOUNDSOURCE;
226
227	AC97_NABMBAR_REGS(PI, PI_INDEX * 16);
228	AC97_NABMBAR_REGS(PO, PO_INDEX * 16);
229	AC97_NABMBAR_REGS(MC, MC_INDEX * 16);
230	#endif
231
232	enum
233	{
234	/** NABMBAR: Global Control Register. */
235	GLOB_CNT = 0x2c,
236	/** NABMBAR Global Status. */
237	GLOB_STA = 0x30,
238	/** Codec Access Semaphore Register. */
239	CAS = 0x34
240	};
241
242	#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
243
244	/*********************************************************************************************************************************
245	* Structures and Typedefs *
246	*********************************************************************************************************************************/
247
248	/**
249	* Buffer Descriptor List Entry (BDLE).
250	*/
251	typedef struct AC97BDLE
252	{
253	uint32_t addr;
254	uint32_t ctl_len;
255	} AC97BDLE, *PAC97BDLE;
256
257	/**
258	* Bus master register set for an audio stream.
259	*/
260	typedef struct AC97BMREGS
261	{
262	uint32_t bdbar; /** rw 0, Buffer Descriptor List: BAR (Base Address Register). */
263	uint8_t civ; /** ro 0, Current index value. */
264	uint8_t lvi; /** rw 0, Last valid index. */
265	uint16_t sr; /** rw 1, Status register. */
266	uint16_t picb; /** ro 0, Position in current buffer (in samples). */
267	uint8_t piv; /** ro 0, Prefetched index value. */
268	uint8_t cr; /** rw 0, Control register. */
269	int bd_valid; /** Whether current BDLE is initialized or not. */
270	AC97BDLE bd; /** Current Buffer Descriptor List Entry (BDLE). */
271	} AC97BMREGS, *PAC97BMREGS;
272
273	/**
274	* Internal state of an AC97 stream.
275	*/
276	typedef struct AC97STREAMSTATE
277	{
278	/** Temporary FIFO write buffer. */
279	R3PTRTYPE(uint8_t *) au8FIFOW;
280	/** Size of the temporary FIFO write buffer. */
281	uint32_t cbFIFOW;
282	/** Current write offset in FIFO write buffer. */
283	uint32_t offFIFOW;
284	uint8_t Padding;
285	} AC97STREAMSTATE, *PAC97STREAMSTATE;
286
287	/**
288	* Structure for keeping an AC97 stream state.
289	*
290	* Contains only register values which do not change until a
291	* stream reset occurs.
292	*/
293	typedef struct AC97STREAM
294	{
295	/** Stream number (SDn). */
296	uint8_t u8Strm;
297	/** Bus master registers of this stream. */
298	AC97BMREGS Regs;
299	/** Internal state of this stream. */
300	AC97STREAMSTATE State;
301	} AC97STREAM, *PAC97STREAM;
302
303	typedef struct AC97INPUTSTREAM
304	{
305	/** Mixer handle for input stream. */
306	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
307	} AC97INPUTSTREAM, *PAC97INPUTSTREAM;
308
309	typedef struct AC97OUTPUTSTREAM
310	{
311	/** Mixer handle for output stream. */
312	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
313	} AC97OUTPUTSTREAM, *PAC97OUTPUTSTREAM;
314
315	/**
316	* Struct for maintaining a host backend driver.
317	*/
318	typedef struct AC97STATE *PAC97STATE;
319	typedef struct AC97DRIVER
320	{
321	/** Node for storing this driver in our device driver list of AC97STATE. */
322	RTLISTNODER3 Node;
323	/** Pointer to AC97 controller (state). */
324	R3PTRTYPE(PAC97STATE) pAC97State;
325	/** Driver flags. */
326	PDMAUDIODRVFLAGS Flags;
327	uint32_t PaddingFlags;
328	/** LUN # to which this driver has been assigned. */
329	uint8_t uLUN;
330	/** Whether this driver is in an attached state or not. */
331	bool fAttached;
332	uint8_t Padding[4];
333	/** Pointer to attached driver base interface. */
334	R3PTRTYPE(PPDMIBASE) pDrvBase;
335	/** Audio connector interface to the underlying host backend. */
336	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
337	/** Stream for line input. */
338	AC97INPUTSTREAM LineIn;
339	/** Stream for mic input. */
340	AC97INPUTSTREAM MicIn;
341	/** Stream for output. */
342	AC97OUTPUTSTREAM Out;
343	} AC97DRIVER, *PAC97DRIVER;
344
345	typedef struct AC97STATE
346	{
347	/** The PCI device state. */
348	PCIDevice PciDev;
349	/** R3 Pointer to the device instance. */
350	PPDMDEVINSR3 pDevInsR3;
351	/** Global Control (Bus Master Control Register). */
352	uint32_t glob_cnt;
353	/** Global Status (Bus Master Control Register). */
354	uint32_t glob_sta;
355	/** Codec Access Semaphore Register (Bus Master Control Register). */
356	uint32_t cas;
357	uint32_t last_samp;
358	uint8_t mixer_data[256];
359	/** Stream state for line-in. */
360	AC97STREAM StreamLineIn;
361	/** Stream state for microphone-in. */
362	AC97STREAM StreamMicIn;
363	/** Stream state for output. */
364	AC97STREAM StreamOut;
365	/** Number of active (running) SDn streams. */
366	uint8_t cStreamsActive;
367	#ifndef VBOX_WITH_AUDIO_CALLBACKS
368	/** The timer for pumping data thru the attached LUN drivers. */
369	PTMTIMERR3 pTimer;
370	# if HC_ARCH_BITS == 32
371	uint32_t Padding0;
372	# endif
373	/** Flag indicating whether the timer is active or not. */
374	bool fTimerActive;
375	uint8_t u8Padding1[7];
376	/** The timer interval for pumping data thru the LUN drivers in timer ticks. */
377	uint64_t cTimerTicks;
378	/** Timestamp of the last timer callback (ac97Timer).
379	* Used to calculate the time actually elapsed between two timer callbacks. */
380	uint64_t uTimerTS;
381	#endif
382	#ifdef VBOX_WITH_STATISTICS
383	uint8_t Padding1;
384	STAMPROFILE StatTimer;
385	STAMCOUNTER StatBytesRead;
386	STAMCOUNTER StatBytesWritten;
387	#endif
388	/** List of associated LUN drivers (AC97DRIVER). */
389	RTLISTANCHOR lstDrv;
390	/** The device's software mixer. */
391	R3PTRTYPE(PAUDIOMIXER) pMixer;
392	/** Audio sink for PCM output. */
393	R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
394	/** Audio sink for line input. */
395	R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
396	/** Audio sink for microphone input. */
397	R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
398	uint8_t silence[128];
399	int bup_flag;
400	/** The base interface for LUN\#0. */
401	PDMIBASE IBase;
402	/** Base port of the I/O space region. */
403	RTIOPORT IOPortBase[2];
404	/** Codec model. */
405	uint32_t uCodecModel;
406	} AC97STATE, *PAC97STATE;
407
408	#ifdef VBOX_WITH_STATISTICS
409	AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
410	AssertCompileMemberAlignment(AC97STATE, StatBytesRead, 8);
411	AssertCompileMemberAlignment(AC97STATE, StatBytesWritten, 8);
412	#endif
413
414	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
415
416	static void ichac97DestroyIn(PAC97STATE pThis, PDMAUDIORECSOURCE enmRecSource);
417	static void ichac97DestroyOut(PAC97STATE pThis);
418	DECLINLINE(PAC97STREAM) ichac97GetStreamFromID(PAC97STATE pThis, uint32_t uID);
419	static int ichac97StreamInit(PAC97STATE pThis, PAC97STREAM pStream, uint8_t u8Strm);
420	static DECLCALLBACK(void) ichac97Reset(PPDMDEVINS pDevIns);
421	#ifndef VBOX_WITH_AUDIO_CALLBACKS
422	static void ichac97TimerMaybeStart(PAC97STATE pThis);
423	static void ichac97TimerMaybeStop(PAC97STATE pThis);
424	static DECLCALLBACK(void) ichac97Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
425	#endif
426	static int ichac97TransferAudio(PAC97STATE pThis, PAC97STREAM pStream, uint32_t cbToProcess, uint32_t *pcbProcessed);
427
428	static void ichac97WarmReset(PAC97STATE pThis)
429	{
430	NOREF(pThis);
431	}
432
433	static void ichac97ColdReset(PAC97STATE pThis)
434	{
435	NOREF(pThis);
436	}
437
438	DECLINLINE(PAUDMIXSINK) ichac97IndexToSink(PAC97STATE pThis, uint8_t uIndex)
439	{
440	AssertPtrReturn(pThis, NULL);
441
442	switch (uIndex)
443	{
444	case PI_INDEX: return pThis->pSinkLineIn; break;
445	case PO_INDEX: return pThis->pSinkOutput; break;
446	case MC_INDEX: return pThis->pSinkMicIn; break;
447	default: break;
448	}
449
450	AssertMsgFailed(("Wrong index %RU8\n", uIndex));
451	return NULL;
452	}
453
454	/** Fetches the buffer descriptor at _CIV. */
455	static void ichac97StreamFetchBDLE(PAC97STATE pThis, PAC97STREAM pStream)
456	{
457	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
458	PAC97BMREGS pRegs = &pStream->Regs;
459
460	uint32_t u32[2];
461
462	PDMDevHlpPhysRead(pDevIns, pRegs->bdbar + pRegs->civ * 8, &u32[0], sizeof(u32));
463	pRegs->bd_valid = 1;
464	#if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)
465	# error Please adapt the code (audio buffers are little endian)!
466	#else
467	pRegs->bd.addr = RT_H2LE_U32(u32[0] & ~3);
468	pRegs->bd.ctl_len = RT_H2LE_U32(u32[1]);
469	#endif
470	pRegs->picb = pRegs->bd.ctl_len & BD_MAX_LEN_MASK;
471	LogFlowFunc(("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
472	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len >> 16,
473	pRegs->bd.ctl_len & BD_MAX_LEN_MASK,
474	(pRegs->bd.ctl_len & BD_MAX_LEN_MASK) << 1)); /** @todo r=andy Assumes 16bit samples. */
475	}
476
477	/**
478	* Update the BM status register
479	*/
480	static void ichac97StreamUpdateStatus(PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr)
481	{
482	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
483	PAC97BMREGS pRegs = &pStream->Regs;
484
485	bool fSignal = false;
486	int iIRQL;
487
488	uint32_t new_mask = new_sr & SR_INT_MASK;
489	uint32_t old_mask = pRegs->sr & SR_INT_MASK;
490
491	static uint32_t const masks[] = { GS_PIINT, GS_POINT, GS_MINT };
492
493	if (new_mask ^ old_mask)
494	{
495	/** @todo Is IRQ deasserted when only one of status bits is cleared? */
496	if (!new_mask)
497	{
498	fSignal = true;
499	iIRQL = 0;
500	}
501	else if ((new_mask & SR_LVBCI) && (pRegs->cr & CR_LVBIE))
502	{
503	fSignal = true;
504	iIRQL = 1;
505	}
506	else if ((new_mask & SR_BCIS) && (pRegs->cr & CR_IOCE))
507	{
508	fSignal = true;
509	iIRQL = 1;
510	}
511	}
512
513	pRegs->sr = new_sr;
514
515	LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n",
516	pRegs->sr & SR_BCIS, pRegs->sr & SR_LVBCI, pRegs->sr, fSignal, iIRQL));
517
518	if (fSignal)
519	{
520	if (iIRQL)
521	pThis->glob_sta \|= masks[pStream->u8Strm];
522	else
523	pThis->glob_sta &= ~masks[pStream->u8Strm];
524
525	LogFlowFunc(("Setting IRQ level=%d\n", iIRQL));
526	PDMDevHlpPCISetIrq(pDevIns, 0, iIRQL);
527	}
528	}
529
530	static bool ichac97StreamIsActive(PAC97STATE pThis, PAC97STREAM pStream)
531	{
532	AssertPtrReturn(pThis, false);
533	AssertPtrReturn(pStream, false);
534
535	PAUDMIXSINK pSink = ichac97IndexToSink(pThis, pStream->u8Strm);
536	bool fActive = RT_BOOL(AudioMixerSinkGetStatus(pSink) & AUDMIXSINK_STS_RUNNING);
537
538	LogFlowFunc(("SD=%RU8, fActive=%RTbool\n", pStream->u8Strm, fActive));
539	return fActive;
540	}
541
542	static int ichac97StreamSetActive(PAC97STATE pThis, PAC97STREAM pStream, bool fActive)
543	{
544	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
545	AssertPtrReturn(pStream, VERR_INVALID_POINTER);
546
547	if (!fActive)
548	{
549	if (pThis->cStreamsActive) /* Disable can be called mupltiple times. */
550	pThis->cStreamsActive--;
551
552	#ifndef VBOX_WITH_AUDIO_CALLBACKS
553	ichac97TimerMaybeStop(pThis);
554	#endif
555	}
556	else
557	{
558	pThis->cStreamsActive++;
559	#ifndef VBOX_WITH_AUDIO_CALLBACKS
560	ichac97TimerMaybeStart(pThis);
561	#endif
562	}
563
564	int rc = AudioMixerSinkCtl(ichac97IndexToSink(pThis, pStream->u8Strm),
565	fActive ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE);
566
567	LogFlowFunc(("SD=%RU8, fActive=%RTbool, cStreamsActive=%RU8, rc=%Rrc\n",
568	pStream->u8Strm, fActive, pThis->cStreamsActive, rc));
569
570	return rc;
571	}
572
573	static void ichac97StreamResetBMRegs(PAC97STATE pThis, PAC97STREAM pStream)
574	{
575	AssertPtrReturnVoid(pThis);
576	AssertPtrReturnVoid(pStream);
577
578	LogFlowFuncEnter();
579
580	PAC97BMREGS pRegs = &pStream->Regs;
581
582	pRegs->bdbar = 0;
583	pRegs->civ = 0;
584	pRegs->lvi = 0;
585
586	ichac97StreamUpdateStatus(pThis, pStream, SR_DCH); /** @todo Do we need to do that? */
587
588	pRegs->picb = 0;
589	pRegs->piv = 0;
590	pRegs->cr = pRegs->cr & CR_DONT_CLEAR_MASK;
591	pRegs->bd_valid = 0;
592
593	ichac97StreamSetActive(pThis, pStream, false /* fActive */);
594
595	RT_ZERO(pThis->silence);
596	}
597
598	static void ichac97StreamDestroy(PAC97STREAM pStream)
599	{
600	LogFlowFunc(("SD=%RU8\n", pStream->u8Strm));
601
602	if (pStream->State.au8FIFOW)
603	{
604	Assert(pStream->State.cbFIFOW);
605	RTMemFree(pStream->State.au8FIFOW);
606	pStream->State.au8FIFOW = NULL;
607	}
608
609	pStream->State.cbFIFOW = 0;
610	pStream->State.offFIFOW = 0;
611	}
612
613	static void ichac97StreamsDestroy(PAC97STATE pThis)
614	{
615	LogFlowFuncEnter();
616
617	ichac97DestroyIn(pThis, PDMAUDIORECSOURCE_LINE);
618	ichac97DestroyIn(pThis, PDMAUDIORECSOURCE_MIC);
619	ichac97DestroyOut(pThis);
620
621	ichac97StreamDestroy(&pThis->StreamLineIn);
622	ichac97StreamDestroy(&pThis->StreamMicIn);
623	ichac97StreamDestroy(&pThis->StreamOut);
624	}
625
626	static int ichac97StreamsInit(PAC97STATE pThis)
627	{
628	LogFlowFuncEnter();
629
630	ichac97StreamInit(pThis, &pThis->StreamLineIn, PI_INDEX);
631	ichac97StreamInit(pThis, &pThis->StreamMicIn, MC_INDEX);
632	ichac97StreamInit(pThis, &pThis->StreamOut, PO_INDEX);
633
634	return VINF_SUCCESS;
635	}
636
637	static void ichac97MixerSet(PAC97STATE pThis, uint32_t u8Idx, uint16_t v)
638	{
639	if (u8Idx + 2 > sizeof(pThis->mixer_data))
640	{
641	AssertMsgFailed(("Index %RU8 out of bounds(%zu)\n", u8Idx, sizeof(pThis->mixer_data)));
642	return;
643	}
644
645	pThis->mixer_data[u8Idx + 0] = RT_LO_U8(v);
646	pThis->mixer_data[u8Idx + 1] = RT_HI_U8(v);
647	}
648
649	static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t u8Idx)
650	{
651	uint16_t uVal;
652
653	if (u8Idx + 2 > sizeof(pThis->mixer_data))
654	{
655	AssertMsgFailed(("Index %RU8 out of bounds (%zu)\n", u8Idx, sizeof(pThis->mixer_data)));
656	uVal = UINT16_MAX;
657	}
658	else
659	uVal = RT_MAKE_U16(pThis->mixer_data[u8Idx + 0], pThis->mixer_data[u8Idx + 1]);
660
661	return uVal;
662	}
663
664	static void ichac97DestroyIn(PAC97STATE pThis, PDMAUDIORECSOURCE enmRecSource)
665	{
666	AssertPtrReturnVoid(pThis);
667
668	LogFlowFuncEnter();
669
670	PAUDMIXSINK pSink;
671	switch (enmRecSource)
672	{
673	case PDMAUDIORECSOURCE_MIC:
674	pSink = pThis->pSinkMicIn;
675	break;
676	case PDMAUDIORECSOURCE_LINE:
677	pSink = pThis->pSinkLineIn;
678	break;
679	default:
680	AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
681	return;
682	}
683
684	PAC97DRIVER pDrv;
685	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
686	{
687	PAC97INPUTSTREAM pStream;
688	if (enmRecSource == PDMAUDIORECSOURCE_MIC) /** @todo Refine this once we have more streams. */
689	pStream = &pDrv->MicIn;
690	else
691	pStream = &pDrv->LineIn;
692
693	if (pStream->pMixStrm)
694	{
695	AudioMixerSinkRemoveStream(pSink, pStream->pMixStrm);
696	AudioMixerStreamDestroy(pStream->pMixStrm);
697	}
698	pStream->pMixStrm = NULL;
699	}
700	}
701
702	static void ichac97DestroyOut(PAC97STATE pThis)
703	{
704	AssertPtrReturnVoid(pThis);
705
706	LogFlowFuncEnter();
707
708	PAC97DRIVER pDrv;
709	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
710	{
711	if (pDrv->Out.pMixStrm)
712	{
713	AudioMixerSinkRemoveStream(pThis->pSinkOutput, pDrv->Out.pMixStrm);
714	AudioMixerStreamDestroy(pDrv->Out.pMixStrm);
715
716	pDrv->Out.pMixStrm = NULL;
717	}
718	}
719	}
720
721	static int ichac97CreateIn(PAC97STATE pThis,
722	const char *pszName, PDMAUDIORECSOURCE enmRecSource, PPDMAUDIOSTREAMCFG pCfg)
723	{
724	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
725	AssertPtrReturn(pszName, VERR_INVALID_POINTER);
726	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
727
728	PAUDMIXSINK pSink;
729	switch (enmRecSource)
730	{
731	case PDMAUDIORECSOURCE_MIC:
732	pSink = pThis->pSinkMicIn;
733	break;
734	case PDMAUDIORECSOURCE_LINE:
735	pSink = pThis->pSinkLineIn;
736	break;
737	default:
738	AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
739	return VERR_NOT_SUPPORTED;
740	}
741
742	/* Update the sink's format. */
743	PDMPCMPROPS PCMProps;
744	int rc = DrvAudioHlpStreamCfgToProps(pCfg, &PCMProps);
745	if (RT_SUCCESS(rc))
746	rc = AudioMixerSinkSetFormat(pSink, &PCMProps);
747
748	if (RT_FAILURE(rc))
749	return rc;
750
751	PAC97DRIVER pDrv;
752	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
753	{
754	if (!RTStrPrintf(pCfg->szName, sizeof(pCfg->szName), "[LUN#%RU8] %s", pDrv->uLUN, pszName))
755	{
756	rc = VERR_BUFFER_OVERFLOW;
757	break;
758	}
759
760	PAC97INPUTSTREAM pStream;
761	if (enmRecSource == PDMAUDIORECSOURCE_MIC) /** @todo Refine this once we have more streams. */
762	pStream = &pDrv->MicIn;
763	else
764	pStream = &pDrv->LineIn;
765
766	AudioMixerSinkRemoveStream(pSink, pStream->pMixStrm);
767
768	AudioMixerStreamDestroy(pStream->pMixStrm);
769	pStream->pMixStrm = NULL;
770
771	int rc2 = AudioMixerSinkCreateStream(pSink, pDrv->pConnector, pCfg, 0 /* fFlags */ , &pStream->pMixStrm);
772	if (RT_SUCCESS(rc2))
773	{
774	rc2 = AudioMixerSinkAddStream(pSink, pStream->pMixStrm);
775	LogFlowFunc(("LUN#%RU8: Created input \"%s\", rc=%Rrc\n", pDrv->uLUN, pCfg->szName, rc2));
776	}
777
778	if (RT_SUCCESS(rc))
779	rc = rc2;
780	}
781
782	LogFlowFuncLeaveRC(rc);
783	return rc;
784	}
785
786	static int ichac97CreateOut(PAC97STATE pThis, const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
787	{
788	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
789	AssertPtrReturn(pszName, VERR_INVALID_POINTER);
790	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
791
792	/* Update the sink's format. */
793	PDMPCMPROPS PCMProps;
794	int rc = DrvAudioHlpStreamCfgToProps(pCfg, &PCMProps);
795	if (RT_SUCCESS(rc))
796	rc = AudioMixerSinkSetFormat(pThis->pSinkOutput, &PCMProps);
797
798	if (RT_FAILURE(rc))
799	return rc;
800
801	PAC97DRIVER pDrv;
802	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
803	{
804	if (!RTStrPrintf(pCfg->szName, sizeof(pCfg->szName), "[LUN#%RU8] %s (%RU32Hz, %RU8 %s)",
805	pDrv->uLUN, pszName, pCfg->uHz, pCfg->cChannels, pCfg->cChannels > 1 ? "Channels" : "Channel"))
806	{
807	rc = VERR_BUFFER_OVERFLOW;
808	break;
809	}
810
811	AudioMixerSinkRemoveStream(pThis->pSinkOutput, pDrv->Out.pMixStrm);
812
813	AudioMixerStreamDestroy(pDrv->Out.pMixStrm);
814	pDrv->Out.pMixStrm = NULL;
815
816	int rc2 = AudioMixerSinkCreateStream(pThis->pSinkOutput, pDrv->pConnector, pCfg, 0 /* fFlags */, &pDrv->Out.pMixStrm);
817	if (RT_SUCCESS(rc2))
818	{
819	rc2 = AudioMixerSinkAddStream(pThis->pSinkOutput, pDrv->Out.pMixStrm);
820	LogFlowFunc(("LUN#%RU8: Created output \"%s\", rc=%Rrc\n", pDrv->uLUN, pCfg->szName, rc2));
821	}
822
823	if (RT_SUCCESS(rc))
824	rc = rc2;
825	}
826
827	LogFlowFuncLeaveRC(rc);
828	return rc;
829	}
830
831	static int ichac97StreamInitEx(PAC97STATE pThis, PAC97STREAM pStream, uint8_t u8Strm, PPDMAUDIOSTREAMCFG pCfg)
832	{
833	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
834	AssertPtrReturn(pStream, VERR_INVALID_POINTER);
835	AssertReturn(u8Strm <= LAST_INDEX, VERR_INVALID_PARAMETER);
836	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
837
838	pStream->u8Strm = u8Strm;
839
840	LogFlowFunc(("u8Strm=%RU8, %RU32Hz, %RU8 %s\n",
841	pStream->u8Strm, pCfg->uHz, pCfg->cChannels, pCfg->cChannels > 1 ? "Channels" : "Channel"));
842
843	int rc;
844	switch (pStream->u8Strm)
845	{
846	case PI_INDEX:
847	rc = ichac97CreateIn(pThis, "ac97.pi", PDMAUDIORECSOURCE_LINE, pCfg);
848	break;
849
850	case MC_INDEX:
851	rc = ichac97CreateIn(pThis, "ac97.mc", PDMAUDIORECSOURCE_MIC, pCfg);
852	break;
853
854	case PO_INDEX:
855	rc = ichac97CreateOut(pThis, "ac97.po", pCfg);
856	break;
857
858	default:
859	rc = VERR_NOT_SUPPORTED;
860	break;
861	}
862
863	if (RT_FAILURE(rc))
864	LogRel2(("AC97: Error opening stream #%RU8, rc=%Rrc\n", pStream->u8Strm, rc));
865
866	LogFlowFuncLeaveRC(rc);
867	return rc;
868	}
869
870	static int ichac97StreamInit(PAC97STATE pThis, PAC97STREAM pStream, uint8_t u8Strm)
871	{
872	int rc = VINF_SUCCESS;
873
874	PDMAUDIOSTREAMCFG streamCfg;
875	RT_ZERO(streamCfg);
876
877	switch (u8Strm)
878	{
879	case PI_INDEX:
880	streamCfg.uHz = ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate);
881	streamCfg.enmDir = PDMAUDIODIR_IN;
882	streamCfg.DestSource.Source = PDMAUDIORECSOURCE_LINE;
883	break;
884
885	case MC_INDEX:
886	streamCfg.uHz = ichac97MixerGet(pThis, AC97_MIC_ADC_Rate);
887	streamCfg.enmDir = PDMAUDIODIR_IN;
888	streamCfg.DestSource.Source = PDMAUDIORECSOURCE_MIC;
889	break;
890
891	case PO_INDEX:
892	streamCfg.uHz = ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate);
893	streamCfg.enmDir = PDMAUDIODIR_OUT;
894	streamCfg.DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
895	break;
896
897	default:
898	rc = VERR_NOT_SUPPORTED;
899	break;
900	}
901
902	if (RT_SUCCESS(rc))
903	{
904	pStream->State.cbFIFOW = _4K; /** @todo Make FIFOW size configurable. */
905	pStream->State.offFIFOW = 0;
906	pStream->State.au8FIFOW = (uint8_t *)RTMemAllocZ(pStream->State.cbFIFOW);
907	if (!pStream->State.au8FIFOW)
908	rc = VERR_NO_MEMORY;
909	}
910
911	if (RT_SUCCESS(rc))
912	{
913	if (streamCfg.uHz)
914	{
915	streamCfg.cChannels = 2; /** @todo Handle mono channels? */
916	streamCfg.enmFormat = PDMAUDIOFMT_S16;
917	streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
918
919	rc = ichac97StreamInitEx(pThis, pStream, u8Strm, &streamCfg);
920	}
921	else
922	{
923	/* If no frequency is given, disable the stream. */
924	rc = ichac97StreamSetActive(pThis, pStream, false /* fActive */);
925	}
926	}
927
928	LogFlowFunc(("SD=%RU8, rc=%Rrc\n", u8Strm, rc));
929	return rc;
930	}
931
932	static int ichac97StreamReInit(PAC97STATE pThis, PAC97STREAM pStrm)
933	{
934	return ichac97StreamInit(pThis, pStrm, pStrm->u8Strm);
935	}
936
937	static void ichac97StreamReset(PAC97STATE pThis, PAC97STREAM pStrm)
938	{
939	AssertPtrReturnVoid(pThis);
940	AssertPtrReturnVoid(pStrm);
941
942	LogFlowFunc(("SD=%RU8\n", pStrm->u8Strm));
943
944	if (pStrm->State.au8FIFOW)
945	{
946	Assert(pStrm->State.cbFIFOW);
947	RT_BZERO(pStrm->State.au8FIFOW, pStrm->State.cbFIFOW);
948	}
949
950	pStrm->State.offFIFOW = 0;
951	}
952
953	static int ichac97MixerSetVolume(PAC97STATE pThis, int index, PDMAUDIOMIXERCTL mt, uint32_t val)
954	{
955	int mute = (val >> MUTE_SHIFT) & 1;
956	uint8_t rvol = val & VOL_MASK;
957	uint8_t lvol = (val >> 8) & VOL_MASK;
958
959	/* For the master volume, 0 corresponds to 0dB gain. But for the other
960	* volume controls, 0 corresponds to +12dB and 8 to 0dB. */
961	if (mt != PDMAUDIOMIXERCTL_VOLUME)
962	{
963	/* NB: Currently there is no gain support, only attenuation. */
964	lvol = lvol < 8 ? 0 : lvol - 8;
965	rvol = rvol < 8 ? 0 : rvol - 8;
966	}
967
968	/* AC'97 has 1.5dB steps; we use 0.375dB steps. */
969	rvol = 255 - rvol * 4;
970	lvol = 255 - lvol * 4;
971
972	LogFunc(("mt=%ld, val=%RX32, mute=%RTbool\n", mt, val, RT_BOOL(mute)));
973
974	int rc;
975
976	if (pThis->pMixer) /* Device can be in reset state, so no mixer available. */
977	{
978	PDMAUDIOVOLUME vol = { RT_BOOL(mute), lvol, rvol };
979	switch (mt)
980	{
981	case PDMAUDIOMIXERCTL_VOLUME:
982	rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
983	break;
984
985	case PDMAUDIOMIXERCTL_FRONT:
986	rc = AudioMixerSinkSetVolume(pThis->pSinkOutput, &vol);
987	break;
988
989	case PDMAUDIOMIXERCTL_MIC_IN:
990	rc = AudioMixerSinkSetVolume(pThis->pSinkMicIn, &vol);
991	break;
992
993	case PDMAUDIOMIXERCTL_LINE_IN:
994	rc = AudioMixerSinkSetVolume(pThis->pSinkLineIn, &vol);
995	break;
996
997	default:
998	rc = VERR_NOT_SUPPORTED;
999	break;
1000	}
1001	}
1002	else
1003	rc = VINF_SUCCESS;
1004
1005	rvol = VOL_MASK - ((VOL_MASK * rvol) / 255);
1006	lvol = VOL_MASK - ((VOL_MASK * lvol) / 255);
1007
1008	/*
1009	* From AC'97 SoundMax Codec AD1981A: "Because AC '97 defines 6-bit volume registers, to
1010	* maintain compatibility whenever the D5 or D13 bits are set to `1,' their respective
1011	* lower five volume bits are automatically set to `1' by the Codec logic. On readback,
1012	* all lower 5 bits will read ones whenever these bits are set to `1.'"
1013	*
1014	* Linux ALSA depends on this behavior.
1015	*/
1016	if (val & RT_BIT(5))
1017	val \|= RT_BIT(4) \| RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1) \| RT_BIT(0);
1018	if (val & RT_BIT(13))
1019	val \|= RT_BIT(12) \| RT_BIT(11) \| RT_BIT(10) \| RT_BIT(9) \| RT_BIT(8);
1020
1021	ichac97MixerSet(pThis, index, val);
1022
1023	if (RT_FAILURE(rc))
1024	LogFlowFunc(("Failed with %Rrc\n", rc));
1025
1026	return rc;
1027	}
1028
1029	static PDMAUDIORECSOURCE ichac97IndextoRecSource(uint8_t i)
1030	{
1031	switch (i)
1032	{
1033	case REC_MIC: return PDMAUDIORECSOURCE_MIC;
1034	case REC_CD: return PDMAUDIORECSOURCE_CD;
1035	case REC_VIDEO: return PDMAUDIORECSOURCE_VIDEO;
1036	case REC_AUX: return PDMAUDIORECSOURCE_AUX;
1037	case REC_LINE_IN: return PDMAUDIORECSOURCE_LINE;
1038	case REC_PHONE: return PDMAUDIORECSOURCE_PHONE;
1039	default:
1040	break;
1041	}
1042
1043	LogFlowFunc(("Unknown record source %d, using MIC\n", i));
1044	return PDMAUDIORECSOURCE_MIC;
1045	}
1046
1047	static uint8_t ichac97RecSourceToIndex(PDMAUDIORECSOURCE rs)
1048	{
1049	switch (rs)
1050	{
1051	case PDMAUDIORECSOURCE_MIC: return REC_MIC;
1052	case PDMAUDIORECSOURCE_CD: return REC_CD;
1053	case PDMAUDIORECSOURCE_VIDEO: return REC_VIDEO;
1054	case PDMAUDIORECSOURCE_AUX: return REC_AUX;
1055	case PDMAUDIORECSOURCE_LINE: return REC_LINE_IN;
1056	case PDMAUDIORECSOURCE_PHONE: return REC_PHONE;
1057	default:
1058	break;
1059	}
1060
1061	LogFlowFunc(("Unknown audio recording source %d using MIC\n", rs));
1062	return REC_MIC;
1063	}
1064
1065	static void ichac97RecordSelect(PAC97STATE pThis, uint32_t val)
1066	{
1067	uint8_t rs = val & REC_MASK;
1068	uint8_t ls = (val >> 8) & REC_MASK;
1069	PDMAUDIORECSOURCE ars = ichac97IndextoRecSource(rs);
1070	PDMAUDIORECSOURCE als = ichac97IndextoRecSource(ls);
1071	rs = ichac97RecSourceToIndex(ars);
1072	ls = ichac97RecSourceToIndex(als);
1073	ichac97MixerSet(pThis, AC97_Record_Select, rs \| (ls << 8));
1074	}
1075
1076	static int ichac97MixerReset(PAC97STATE pThis)
1077	{
1078	AssertPtrReturn(pThis, VERR_INVALID_PARAMETER);
1079
1080	LogFlowFuncEnter();
1081
1082	RT_ZERO(pThis->mixer_data);
1083
1084	/* Note: Make sure to reset all registers first before bailing out on error. */
1085
1086	ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
1087	ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
1088	ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
1089
1090	ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
1091	ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
1092	ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
1093	ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
1094	ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
1095	ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
1096	ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
1097	ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
1098
1099	ichac97MixerSet(pThis, AC97_Extended_Audio_ID , 0x0809);
1100	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
1101	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80);
1102	ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80);
1103	ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80);
1104	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80);
1105	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80);
1106
1107	if (pThis->uCodecModel == Codec_AD1980)
1108	{
1109	/* Analog Devices 1980 (AD1980) */
1110	ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
1111	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
1112	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
1113	ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
1114	}
1115	else if (pThis->uCodecModel == Codec_AD1981B)
1116	{
1117	/* Analog Devices 1981B (AD1981B) */
1118	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
1119	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
1120	}
1121	else
1122	{
1123	/* Sigmatel 9700 (STAC9700) */
1124	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
1125	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
1126	}
1127	ichac97RecordSelect(pThis, 0);
1128
1129	ichac97MixerSetVolume(pThis, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME, 0x8000);
1130	ichac97MixerSetVolume(pThis, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT, 0x8808);
1131	ichac97MixerSetVolume(pThis, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
1132
1133	return VINF_SUCCESS;
1134	}
1135
1136	/**
1137	* Writes data from the device to the host backends.
1138	*
1139	* @return IPRT status code.
1140	* @param pThis
1141	* @param pStream
1142	* @param cbMax
1143	* @param pcbWritten
1144	*/
1145	static int ichac97WriteAudio(PAC97STATE pThis, PAC97STREAM pStream, uint32_t cbToWrite, uint32_t *pcbWritten)
1146	{
1147	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1148	AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1149	AssertReturn(cbToWrite, VERR_INVALID_PARAMETER);
1150	/* pcbWritten is optional. */
1151
1152	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
1153	PAC97BMREGS pRegs = &pStream->Regs;
1154
1155	uint32_t addr = pRegs->bd.addr;
1156	uint32_t cbWrittenTotal = 0;
1157
1158	Log3Func(("PICB=%RU16, cbMax=%RU32\n", pRegs->picb, cbToWrite));
1159
1160	cbToWrite = RT_MIN((uint32_t)(pRegs->picb << 1), cbToWrite); /** @todo r=andy Assumes 16bit sample size. */
1161	if (!cbToWrite)
1162	{
1163	if (pcbWritten)
1164	*pcbWritten = 0;
1165	return VINF_EOF;
1166	}
1167
1168	int rc = VINF_SUCCESS;
1169
1170	LogFlowFunc(("pRegs=%p, cbMax=%RU32, cbToWrite=%RU32\n", pRegs, cbToWrite, cbToWrite));
1171
1172	Assert(pStream->State.offFIFOW <= pStream->State.cbFIFOW);
1173	uint32_t cbFIFOW = pStream->State.cbFIFOW - pStream->State.offFIFOW;
1174	uint8_t *pu8FIFOW = &pStream->State.au8FIFOW[pStream->State.offFIFOW];
1175
1176	uint32_t cbToRead;
1177	while (cbToWrite)
1178	{
1179	cbToRead = RT_MIN(cbToWrite, cbFIFOW);
1180	PDMDevHlpPhysRead(pDevIns, addr, pu8FIFOW, cbToRead); /** @todo r=andy Check rc? */
1181
1182	#ifdef AC97_DEBUG_DUMP_PCM_DATA
1183	RTFILE fh;
1184	RTFileOpen(&fh, AC97_DEBUG_DUMP_PCM_DATA_PATH "ac97WriteAudio.pcm",
1185	RTFILE_O_OPEN_CREATE \| RTFILE_O_APPEND \| RTFILE_O_WRITE \| RTFILE_O_DENY_NONE);
1186	RTFileWrite(fh, pu8FIFOW, cbToRead, NULL);
1187	RTFileClose(fh);
1188	#endif
1189	/*
1190	* Write data to the mixer sink.
1191	*/
1192	uint32_t cbWritten;
1193	rc = AudioMixerSinkWrite(pThis->pSinkOutput, AUDMIXOP_COPY, pu8FIFOW, cbToRead, &cbWritten);
1194
1195	LogFlowFunc(("\tcbToRead=%RU32, cbToWrite=%RU32, cbWritten=%RU32, cbLeft=%RU32, rc=%Rrc\n",
1196	cbToRead, cbToWrite, cbWritten, cbToWrite - cbWrittenTotal, rc));
1197
1198	if (RT_FAILURE(rc))
1199	break;
1200
1201	/* Advance. */
1202	Assert(cbToWrite >= cbToRead);
1203	cbToWrite -= cbToRead;
1204	addr += cbToRead;
1205	cbWrittenTotal += cbToRead;
1206	}
1207
1208	/* Set new buffer descriptor address. */
1209	pRegs->bd.addr = addr;
1210
1211	if (RT_SUCCESS(rc))
1212	{
1213	if (!cbToWrite) /* All data written? */
1214	{
1215	if (cbToRead < 4)
1216	{
1217	AssertMsgFailed(("Unable to save last written sample, cbToRead < 4 (is %RU32)\n", cbToRead));
1218	pThis->last_samp = 0;
1219	}
1220	else
1221	pThis->last_samp = (uint32_t )&pStream->State.au8FIFOW[pStream->State.offFIFOW + cbToRead - 4];
1222	}
1223
1224	if (pcbWritten)
1225	*pcbWritten = cbWrittenTotal;
1226	}
1227
1228	LogFlowFunc(("cbWrittenTotal=%RU32, rc=%Rrc\n", cbWrittenTotal, rc));
1229	return rc;
1230	}
1231
1232	static void ichac97WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
1233	{
1234	LogFlowFunc(("cbElapsed=%RU32\n", cbElapsed));
1235
1236	if (!(pThis->bup_flag & BUP_SET))
1237	{
1238	if (pThis->bup_flag & BUP_LAST)
1239	{
1240	unsigned int i;
1241	uint32_t p = (uint32_t)pThis->silence;
1242	for (i = 0; i < sizeof(pThis->silence) / 4; i++) /** @todo r=andy Assumes 16-bit samples, stereo. */
1243	*p++ = pThis->last_samp;
1244	}
1245	else
1246	RT_ZERO(pThis->silence);
1247
1248	pThis->bup_flag \|= BUP_SET;
1249	}
1250
1251	while (cbElapsed)
1252	{
1253	uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
1254	uint32_t cbWrittenToStream;
1255
1256	int rc2 = AudioMixerSinkWrite(pThis->pSinkOutput, AUDMIXOP_COPY,
1257	pThis->silence, cbToWrite, &cbWrittenToStream);
1258	if (RT_SUCCESS(rc2))
1259	{
1260	if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
1261	LogFlowFunc(("Warning: Only written %RU32 / %RU32 bytes, expect lags\n", cbWrittenToStream, cbToWrite));
1262	}
1263
1264	/* Always report all data as being written;
1265	* backends who were not able to catch up have to deal with it themselves. */
1266	Assert(cbElapsed >= cbToWrite);
1267	cbElapsed -= cbToWrite;
1268	}
1269	}
1270
1271	static int ichac97ReadAudio(PAC97STATE pThis, PAC97STREAM pStream, uint32_t cbToRead, uint32_t *pcbRead)
1272	{
1273	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1274	AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1275	AssertReturn(cbToRead, VERR_INVALID_PARAMETER);
1276	/* pcbRead is optional. */
1277
1278	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
1279	PAC97BMREGS pRegs = &pStream->Regs;
1280
1281	/* Select audio sink to process. */
1282	AssertMsg(pStream->u8Strm != PO_INDEX, ("Can't read from output\n"));
1283	PAUDMIXSINK pSink = pStream->u8Strm == MC_INDEX ? pThis->pSinkMicIn : pThis->pSinkLineIn;
1284	AssertPtr(pSink);
1285
1286	uint32_t cbRead = 0;
1287
1288	cbToRead = RT_MIN((uint32_t)(pRegs->picb << 1),
1289	RT_MIN(pStream->State.cbFIFOW, cbToRead)); /** @todo r=andy Assumes 16bit samples. */
1290
1291	if (!cbToRead)
1292	{
1293	if (pcbRead)
1294	*pcbRead = 0;
1295	return VINF_EOF;
1296	}
1297
1298	int rc;
1299
1300	rc = AudioMixerSinkRead(pSink, AUDMIXOP_BLEND, &pStream->State.au8FIFOW[pStream->State.offFIFOW], cbToRead, &cbRead);
1301	if ( RT_SUCCESS(rc)
1302	&& cbRead)
1303	{
1304	PDMDevHlpPCIPhysWrite(pDevIns, pRegs->bd.addr, &pStream->State.au8FIFOW[pStream->State.offFIFOW], cbRead);
1305	pRegs->bd.addr += cbRead;
1306	}
1307
1308	if (RT_SUCCESS(rc))
1309	{
1310	if (!cbRead)
1311	rc = VINF_EOF;
1312
1313	if (pcbRead)
1314	*pcbRead = cbRead;
1315	}
1316
1317	return rc;
1318	}
1319
1320	#ifndef VBOX_WITH_AUDIO_CALLBACKS
1321
1322	static void ichac97TimerMaybeStart(PAC97STATE pThis)
1323	{
1324	if (pThis->cStreamsActive == 0) /* Only start the timer if there are no active streams. */
1325	return;
1326
1327	if (!pThis->pTimer)
1328	return;
1329
1330	LogFlowFunc(("Starting timer\n"));
1331
1332	/* Set timer flag. */
1333	ASMAtomicXchgBool(&pThis->fTimerActive, true);
1334
1335	/* Update current time timestamp. */
1336	pThis->uTimerTS = TMTimerGet(pThis->pTimer);
1337
1338	/* Fire off timer. */
1339	TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
1340	}
1341
1342	static void ichac97TimerMaybeStop(PAC97STATE pThis)
1343	{
1344	if (pThis->cStreamsActive) /* Some streams still active? Bail out. */
1345	return;
1346
1347	if (!pThis->pTimer)
1348	return;
1349
1350	LogFlowFunc(("Stopping timer\n"));
1351
1352	/* Set timer flag. */
1353	ASMAtomicXchgBool(&pThis->fTimerActive, false);
1354	}
1355
1356	static DECLCALLBACK(void) ichac97Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1357	{
1358	PAC97STATE pThis = (PAC97STATE)pvUser;
1359	Assert(pThis == PDMINS_2_DATA(pDevIns, PAC97STATE));
1360	AssertPtr(pThis);
1361
1362	STAM_PROFILE_START(&pThis->StatTimer, a);
1363
1364	uint64_t cTicksNow = TMTimerGet(pTimer);
1365	uint64_t cTicksElapsed = cTicksNow - pThis->uTimerTS;
1366	uint64_t cTicksPerSec = TMTimerGetFreq(pTimer);
1367
1368	LogFlowFuncEnter();
1369
1370	/* Update current time timestamp. */
1371	pThis->uTimerTS = cTicksNow;
1372
1373	/* Flag indicating whether to kick the timer again for a
1374	* new data processing round. */
1375	bool fKickTimer = false;
1376
1377	uint32_t cbToProcess;
1378
1379	int rc = AudioMixerSinkUpdate(pThis->pSinkLineIn);
1380	if (RT_SUCCESS(rc))
1381	{
1382	cbToProcess = AudioMixerSinkGetReadable(pThis->pSinkLineIn);
1383	if (cbToProcess)
1384	{
1385	rc = ichac97TransferAudio(pThis, &pThis->StreamLineIn, cbToProcess, NULL /* pcbProcessed */);
1386	fKickTimer \|= RT_SUCCESS(rc);
1387	}
1388	}
1389
1390	rc = AudioMixerSinkUpdate(pThis->pSinkMicIn);
1391	if (RT_SUCCESS(rc))
1392	{
1393	cbToProcess = AudioMixerSinkGetReadable(pThis->pSinkMicIn);
1394	if (cbToProcess)
1395	{
1396	rc = ichac97TransferAudio(pThis, &pThis->StreamMicIn, cbToProcess, NULL /* pcbProcessed */);
1397	fKickTimer \|= RT_SUCCESS(rc);
1398	}
1399	}
1400
1401	rc = AudioMixerSinkUpdate(pThis->pSinkOutput);
1402	if (RT_SUCCESS(rc))
1403	{
1404	cbToProcess = AudioMixerSinkGetWritable(pThis->pSinkOutput);
1405	if (cbToProcess)
1406	{
1407	rc = ichac97TransferAudio(pThis, &pThis->StreamOut, cbToProcess, NULL /* pcbProcessed */);
1408	fKickTimer \|= RT_SUCCESS(rc);
1409	}
1410	}
1411
1412	if ( ASMAtomicReadBool(&pThis->fTimerActive)
1413	\|\| fKickTimer)
1414	{
1415	/* Kick the timer again. */
1416	uint64_t cTicks = pThis->cTimerTicks;
1417	/** @todo adjust cTicks down by now much cbOutMin represents. */
1418	TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
1419	}
1420
1421	STAM_PROFILE_STOP(&pThis->StatTimer, a);
1422	}
1423
1424	#endif /* !VBOX_WITH_AUDIO_CALLBACKS */
1425
1426	static int ichac97TransferAudio(PAC97STATE pThis, PAC97STREAM pStream, uint32_t cbToProcess, uint32_t *pcbProcessed)
1427	{
1428	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1429	AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1430	/* pcbProcessed is optional. */
1431
1432	Log3Func(("SD=%RU8\n", pStream->u8Strm));
1433
1434	PAC97BMREGS pRegs = &pStream->Regs;
1435
1436	if (pRegs->sr & SR_DCH) /* Controller halted? */
1437	{
1438	if (pRegs->cr & CR_RPBM) /* Bus master operation starts. */
1439	{
1440	switch (pStream->u8Strm)
1441	{
1442	case PO_INDEX:
1443	ichac97WriteBUP(pThis, cbToProcess);
1444	break;
1445
1446	default:
1447	break;
1448	}
1449	}
1450
1451	if (pcbProcessed)
1452	*pcbProcessed = 0;
1453	return VINF_SUCCESS;
1454	}
1455
1456	/* BCIS flag still set? Skip iteration. */
1457	if (pRegs->sr & SR_BCIS)
1458	{
1459	if (pcbProcessed)
1460	*pcbProcessed = 0;
1461	return VINF_SUCCESS;
1462	}
1463
1464	int rc = VINF_SUCCESS;
1465
1466	uint32_t cbLeft = cbToProcess;
1467	uint32_t cbTotal = 0;
1468
1469	while (cbLeft)
1470	{
1471	if (!pRegs->bd_valid)
1472	{
1473	LogFlowFunc(("Invalid buffer descriptor, fetching next one ...\n"));
1474	ichac97StreamFetchBDLE(pThis, pStream);
1475	}
1476
1477	if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
1478	{
1479	LogFlowFunc(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
1480	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
1481	if (pRegs->civ == pRegs->lvi)
1482	{
1483	pRegs->sr \|= SR_DCH; /** @todo r=andy Also set CELV? */
1484	pThis->bup_flag = 0;
1485
1486	rc = VINF_EOF;
1487	break;
1488	}
1489
1490	pRegs->sr &= ~SR_CELV;
1491	pRegs->civ = pRegs->piv;
1492	pRegs->piv = (pRegs->piv + 1) % 32; /** @todo r=andy Define for max BDLEs? */
1493
1494	ichac97StreamFetchBDLE(pThis, pStream);
1495	continue;
1496	}
1497
1498	uint32_t cbToTransfer, cbTransferred;
1499	switch (pStream->u8Strm)
1500	{
1501	case PO_INDEX:
1502	{
1503	cbToTransfer = (uint32_t)(pRegs->picb << 1);
1504
1505	rc = ichac97WriteAudio(pThis, pStream, cbToTransfer, &cbTransferred);
1506	if ( RT_SUCCESS(rc)
1507	&& cbTransferred)
1508	{
1509	cbTotal += cbTransferred;
1510	Assert(cbLeft >= cbTransferred);
1511	cbLeft -= cbTransferred;
1512	Assert((cbTransferred & 1) == 0); /* Else the following shift won't work */
1513	pRegs->picb -= (cbTransferred >> 1); /** @todo r=andy Assumes 16bit samples. */
1514	}
1515	break;
1516	}
1517
1518	case PI_INDEX:
1519	case MC_INDEX:
1520	{
1521	cbToTransfer = (uint32_t)(pRegs->picb << 1);
1522
1523	rc = ichac97ReadAudio(pThis, pStream, cbToTransfer, &cbTransferred);
1524	if ( RT_SUCCESS(rc)
1525	&& cbTransferred)
1526	{
1527	cbTotal += cbTransferred;
1528	Assert(cbLeft >= cbTransferred);
1529	cbLeft -= cbTransferred;
1530	Assert((cbTransferred & 1) == 0); /* Else the following shift won't work */
1531	pRegs->picb -= (cbTransferred >> 1); /** @todo r=andy Assumes 16bit samples. */
1532	}
1533	break;
1534	}
1535
1536	default:
1537	AssertMsgFailed(("Stream #%RU8 not supported\n", pStream->u8Strm));
1538	rc = VERR_NOT_SUPPORTED;
1539	break;
1540	}
1541
1542	LogFlowFunc(("[SD%RU8]: %RU32 / %RU32, rc=%Rrc\n", pStream->u8Strm, cbTotal, cbToProcess, rc));
1543
1544	if (!pRegs->picb)
1545	{
1546	uint32_t new_sr = pRegs->sr & ~SR_CELV;
1547
1548	if (pRegs->bd.ctl_len & BD_IOC)
1549	{
1550	new_sr \|= SR_BCIS;
1551	}
1552
1553	if (pRegs->civ == pRegs->lvi)
1554	{
1555	/* Did we run out of data? */
1556	LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pRegs->civ, pRegs->lvi));
1557
1558	new_sr \|= SR_LVBCI \| SR_DCH \| SR_CELV;
1559	pThis->bup_flag = (pRegs->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1560
1561	rc = VINF_EOF;
1562	}
1563	else
1564	{
1565	pRegs->civ = pRegs->piv;
1566	pRegs->piv = (pRegs->piv + 1) % 32; /** @todo r=andy Define for max BDLEs? */
1567	ichac97StreamFetchBDLE(pThis, pStream);
1568	}
1569
1570	ichac97StreamUpdateStatus(pThis, pStream, new_sr);
1571	}
1572
1573	if (rc == VINF_EOF) /* All data processed? */
1574	break;
1575	}
1576
1577	if (RT_SUCCESS(rc))
1578	{
1579	if (pcbProcessed)
1580	*pcbProcessed = cbTotal;
1581	}
1582
1583	LogFlowFuncLeaveRC(rc);
1584	return rc;
1585	}
1586
1587	/**
1588	* @callback_method_impl{FNIOMIOPORTIN}
1589	*/
1590	static DECLCALLBACK(int) ichac97IOPortNABMRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
1591	uint32_t *pu32Val, unsigned cbVal)
1592	{
1593	PAC97STATE pThis = (PAC97STATE)pvUser;
1594
1595	/* Get the index of the NABMBAR port. */
1596	const uint32_t uPortIdx = Port - pThis->IOPortBase[1];
1597
1598	PAC97STREAM pStream = ichac97GetStreamFromID(pThis, AC97_PORT2IDX(uPortIdx));
1599	PAC97BMREGS pRegs = pStream ? &pStream->Regs : NULL;
1600
1601	switch (cbVal)
1602	{
1603	case 1:
1604	{
1605	switch (uPortIdx)
1606	{
1607	case CAS:
1608	/* Codec Access Semaphore Register */
1609	LogFlowFunc(("CAS %d\n", pThis->cas));
1610	*pu32Val = pThis->cas;
1611	pThis->cas = 1;
1612	break;
1613	case PI_CIV:
1614	case PO_CIV:
1615	case MC_CIV:
1616	/* Current Index Value Register */
1617	*pu32Val = pRegs->civ;
1618	LogFlowFunc(("CIV[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1619	break;
1620	case PI_LVI:
1621	case PO_LVI:
1622	case MC_LVI:
1623	/* Last Valid Index Register */
1624	*pu32Val = pRegs->lvi;
1625	LogFlowFunc(("LVI[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1626	break;
1627	case PI_PIV:
1628	case PO_PIV:
1629	case MC_PIV:
1630	/* Prefetched Index Value Register */
1631	*pu32Val = pRegs->piv;
1632	LogFlowFunc(("PIV[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1633	break;
1634	case PI_CR:
1635	case PO_CR:
1636	case MC_CR:
1637	/* Control Register */
1638	*pu32Val = pRegs->cr;
1639	LogFlowFunc(("CR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1640	break;
1641	case PI_SR:
1642	case PO_SR:
1643	case MC_SR:
1644	/* Status Register (lower part) */
1645	pu32Val = pRegs->sr & 0xff; /* @todo r=andy Use RT_LO_U8. */
1646	LogFlowFunc(("SRb[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1647	break;
1648	default:
1649	*pu32Val = UINT32_MAX;
1650	LogFlowFunc(("U nabm readb %#x -> %#x\n", Port, *pu32Val));
1651	break;
1652	}
1653	break;
1654	}
1655
1656	case 2:
1657	{
1658	switch (uPortIdx)
1659	{
1660	case PI_SR:
1661	case PO_SR:
1662	case MC_SR:
1663	/* Status Register */
1664	*pu32Val = pRegs->sr;
1665	LogFlowFunc(("SR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1666	break;
1667	case PI_PICB:
1668	case PO_PICB:
1669	case MC_PICB:
1670	/* Position in Current Buffer */
1671	*pu32Val = pRegs->picb;
1672	LogFlowFunc(("PICB[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1673	break;
1674	default:
1675	*pu32Val = UINT32_MAX;
1676	LogFlowFunc(("U nabm readw %#x -> %#x\n", Port, *pu32Val));
1677	break;
1678	}
1679	break;
1680	}
1681
1682	case 4:
1683	{
1684	switch (uPortIdx)
1685	{
1686	case PI_BDBAR:
1687	case PO_BDBAR:
1688	case MC_BDBAR:
1689	/* Buffer Descriptor Base Address Register */
1690	*pu32Val = pRegs->bdbar;
1691	LogFlowFunc(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
1692	break;
1693	case PI_CIV:
1694	case PO_CIV:
1695	case MC_CIV:
1696	/* 32-bit access: Current Index Value Register +
1697	* Last Valid Index Register +
1698	* Status Register */
1699	pu32Val = pRegs->civ \| (pRegs->lvi << 8) \| (pRegs->sr << 16); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
1700	LogFlowFunc(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
1701	AC97_PORT2IDX(uPortIdx), pRegs->civ, pRegs->lvi, pRegs->sr));
1702	break;
1703	case PI_PICB:
1704	case PO_PICB:
1705	case MC_PICB:
1706	/* 32-bit access: Position in Current Buffer Register +
1707	* Prefetched Index Value Register +
1708	* Control Register */
1709	pu32Val = pRegs->picb \| (pRegs->piv << 16) \| (pRegs->cr << 24); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
1710	LogFlowFunc(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
1711	AC97_PORT2IDX(uPortIdx), *pu32Val, pRegs->picb, pRegs->piv, pRegs->cr));
1712	break;
1713	case GLOB_CNT:
1714	/* Global Control */
1715	*pu32Val = pThis->glob_cnt;
1716	LogFlowFunc(("glob_cnt -> %#x\n", *pu32Val));
1717	break;
1718	case GLOB_STA:
1719	/* Global Status */
1720	*pu32Val = pThis->glob_sta \| GS_S0CR;
1721	LogFlowFunc(("glob_sta -> %#x\n", *pu32Val));
1722	break;
1723	default:
1724	*pu32Val = UINT32_MAX;
1725	LogFlowFunc(("U nabm readl %#x -> %#x\n", Port, *pu32Val));
1726	break;
1727	}
1728	break;
1729	}
1730
1731	default:
1732	return VERR_IOM_IOPORT_UNUSED;
1733	}
1734	return VINF_SUCCESS;
1735	}
1736
1737	/**
1738	* @callback_method_impl{FNIOMIOPORTOUT}
1739	*/
1740	static DECLCALLBACK(int) ichac97IOPortNABMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
1741	uint32_t u32Val, unsigned cbVal)
1742	{
1743	PAC97STATE pThis = (PAC97STATE)pvUser;
1744
1745	/* Get the index of the NABMBAR register. */
1746	const uint32_t uPortIdx = Port - pThis->IOPortBase[1];
1747
1748	PAC97STREAM pStream = ichac97GetStreamFromID(pThis, AC97_PORT2IDX(uPortIdx));
1749	PAC97BMREGS pRegs = pStream ? &pStream->Regs : NULL;
1750
1751	switch (cbVal)
1752	{
1753	case 1:
1754	{
1755	switch (uPortIdx)
1756	{
1757	case PI_LVI:
1758	case PO_LVI:
1759	case MC_LVI:
1760	/* Last Valid Index */
1761	if ((pRegs->cr & CR_RPBM) && (pRegs->sr & SR_DCH))
1762	{
1763	pRegs->sr &= ~(SR_DCH \| SR_CELV);
1764	pRegs->civ = pRegs->piv;
1765	pRegs->piv = (pRegs->piv + 1) % 32;
1766
1767	ichac97StreamFetchBDLE(pThis, pStream);
1768	}
1769	pRegs->lvi = u32Val % 32;
1770	LogFlowFunc(("LVI[%d] <- %#x\n", AC97_PORT2IDX(uPortIdx), u32Val));
1771	break;
1772	case PI_CR:
1773	case PO_CR:
1774	case MC_CR:
1775	{
1776	/* Control Register */
1777	if (u32Val & CR_RR) /* Busmaster reset */
1778	{
1779	ichac97StreamResetBMRegs(pThis, pStream);
1780	}
1781	else
1782	{
1783	pRegs->cr = u32Val & CR_VALID_MASK;
1784	if (!(pRegs->cr & CR_RPBM))
1785	{
1786	ichac97StreamSetActive(pThis, pStream, false /* fActive */);
1787	pRegs->sr \|= SR_DCH;
1788	}
1789	else
1790	{
1791	pRegs->civ = pRegs->piv;
1792	pRegs->piv = (pRegs->piv + 1) % 32;
1793
1794	ichac97StreamFetchBDLE(pThis, pStream);
1795
1796	pRegs->sr &= ~SR_DCH;
1797	ichac97StreamSetActive(pThis, pStream, true /* fActive */);
1798	}
1799	}
1800	LogFlowFunc(("CR[%d] <- %#x (cr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->cr));
1801	break;
1802	}
1803	case PI_SR:
1804	case PO_SR:
1805	case MC_SR:
1806	/* Status Register */
1807	pRegs->sr \|= u32Val & ~(SR_RO_MASK \| SR_WCLEAR_MASK);
1808	ichac97StreamUpdateStatus(pThis, pStream, pRegs->sr & ~(u32Val & SR_WCLEAR_MASK));
1809	LogFlowFunc(("SR[%d] <- %#x (sr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->sr));
1810	break;
1811	default:
1812	LogFlowFunc(("U nabm writeb %#x <- %#x\n", Port, u32Val));
1813	break;
1814	}
1815	break;
1816	}
1817
1818	case 2:
1819	{
1820	switch (uPortIdx)
1821	{
1822	case PI_SR:
1823	case PO_SR:
1824	case MC_SR:
1825	/* Status Register */
1826	pRegs->sr \|= u32Val & ~(SR_RO_MASK \| SR_WCLEAR_MASK);
1827	ichac97StreamUpdateStatus(pThis, pStream, pRegs->sr & ~(u32Val & SR_WCLEAR_MASK));
1828	LogFlowFunc(("SR[%d] <- %#x (sr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->sr));
1829	break;
1830	default:
1831	LogFlowFunc(("U nabm writew %#x <- %#x\n", Port, u32Val));
1832	break;
1833	}
1834	break;
1835	}
1836
1837	case 4:
1838	{
1839	switch (uPortIdx)
1840	{
1841	case PI_BDBAR:
1842	case PO_BDBAR:
1843	case MC_BDBAR:
1844	/* Buffer Descriptor list Base Address Register */
1845	pRegs->bdbar = u32Val & ~3;
1846	LogFlowFunc(("BDBAR[%d] <- %#x (bdbar %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->bdbar));
1847	break;
1848	case GLOB_CNT:
1849	/* Global Control */
1850	if (u32Val & GC_WR)
1851	ichac97WarmReset(pThis);
1852	if (u32Val & GC_CR)
1853	ichac97ColdReset(pThis);
1854	if (!(u32Val & (GC_WR \| GC_CR)))
1855	pThis->glob_cnt = u32Val & GC_VALID_MASK;
1856	LogFlowFunc(("glob_cnt <- %#x (glob_cnt %#x)\n", u32Val, pThis->glob_cnt));
1857	break;
1858	case GLOB_STA:
1859	/* Global Status */
1860	pThis->glob_sta &= ~(u32Val & GS_WCLEAR_MASK);
1861	pThis->glob_sta \|= (u32Val & ~(GS_WCLEAR_MASK \| GS_RO_MASK)) & GS_VALID_MASK;
1862	LogFlowFunc(("glob_sta <- %#x (glob_sta %#x)\n", u32Val, pThis->glob_sta));
1863	break;
1864	default:
1865	LogFlowFunc(("U nabm writel %#x <- %#x\n", Port, u32Val));
1866	break;
1867	}
1868	break;
1869	}
1870
1871	default:
1872	AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cbVal, u32Val));
1873	break;
1874	}
1875	return VINF_SUCCESS;
1876	}
1877
1878	/**
1879	* @callback_method_impl{FNIOMIOPORTIN}
1880	*/
1881	static DECLCALLBACK(int) ichac97IOPortNAMRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32Val, unsigned cbVal)
1882	{
1883	PAC97STATE pThis = (PAC97STATE)pvUser;
1884
1885	switch (cbVal)
1886	{
1887	case 1:
1888	{
1889	LogFlowFunc(("U nam readb %#x\n", Port));
1890	pThis->cas = 0;
1891	*pu32Val = UINT32_MAX;
1892	break;
1893	}
1894
1895	case 2:
1896	{
1897	uint32_t index = Port - pThis->IOPortBase[0];
1898	*pu32Val = UINT32_MAX;
1899	pThis->cas = 0;
1900	switch (index)
1901	{
1902	default:
1903	*pu32Val = ichac97MixerGet(pThis, index);
1904	LogFlowFunc(("nam readw %#x -> %#x\n", Port, *pu32Val));
1905	break;
1906	}
1907	break;
1908	}
1909
1910	case 4:
1911	{
1912	LogFlowFunc(("U nam readl %#x\n", Port));
1913	pThis->cas = 0;
1914	*pu32Val = UINT32_MAX;
1915	break;
1916	}
1917
1918	default:
1919	return VERR_IOM_IOPORT_UNUSED;
1920	}
1921	return VINF_SUCCESS;
1922	}
1923
1924	/**
1925	* @callback_method_impl{FNIOMIOPORTOUT}
1926	*/
1927	static DECLCALLBACK(int) ichac97IOPortNAMWrite(PPDMDEVINS pDevIns,
1928	void *pvUser, RTIOPORT Port, uint32_t u32Val, unsigned cbVal)
1929	{
1930	PAC97STATE pThis = (PAC97STATE)pvUser;
1931
1932	switch (cbVal)
1933	{
1934	case 1:
1935	{
1936	LogFlowFunc(("U nam writeb %#x <- %#x\n", Port, u32Val));
1937	pThis->cas = 0;
1938	break;
1939	}
1940
1941	case 2:
1942	{
1943	uint32_t index = Port - pThis->IOPortBase[0];
1944	pThis->cas = 0;
1945	switch (index)
1946	{
1947	case AC97_Reset:
1948	ichac97Reset(pThis->CTX_SUFF(pDevIns));
1949	break;
1950	case AC97_Powerdown_Ctrl_Stat:
1951	u32Val &= ~0xf;
1952	u32Val \|= ichac97MixerGet(pThis, index) & 0xf;
1953	ichac97MixerSet(pThis, index, u32Val);
1954	break;
1955	case AC97_Master_Volume_Mute:
1956	if (pThis->uCodecModel == Codec_AD1980)
1957	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AD_MISC_LOSEL)
1958	break; /* Register controls surround (rear), do nothing. */
1959	ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_VOLUME, u32Val);
1960	break;
1961	case AC97_Headphone_Volume_Mute:
1962	if (pThis->uCodecModel == Codec_AD1980)
1963	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AD_MISC_HPSEL)
1964	/* Register controls PCM (front) outputs. */
1965	ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_VOLUME, u32Val);
1966	break;
1967	case AC97_PCM_Out_Volume_Mute:
1968	ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_FRONT, u32Val);
1969	break;
1970	case AC97_Line_In_Volume_Mute:
1971	ichac97MixerSetVolume(pThis, index, PDMAUDIOMIXERCTL_LINE_IN, u32Val);
1972	break;
1973	case AC97_Record_Select:
1974	ichac97RecordSelect(pThis, u32Val);
1975	break;
1976	case AC97_Vendor_ID1:
1977	case AC97_Vendor_ID2:
1978	LogFlowFunc(("Attempt to write vendor ID to %#x\n", u32Val));
1979	break;
1980	case AC97_Extended_Audio_ID:
1981	LogFlowFunc(("Attempt to write extended audio ID to %#x\n", u32Val));
1982	break;
1983	case AC97_Extended_Audio_Ctrl_Stat:
1984	if (!(u32Val & EACS_VRA))
1985	{
1986	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 48000);
1987	ichac97StreamReInit(pThis, &pThis->StreamOut);
1988
1989	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 48000);
1990	ichac97StreamReInit(pThis, &pThis->StreamLineIn);
1991	}
1992	if (!(u32Val & EACS_VRM))
1993	{
1994	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 48000);
1995	ichac97StreamReInit(pThis, &pThis->StreamMicIn);
1996	}
1997	LogFlowFunc(("Setting extended audio control to %#x\n", u32Val));
1998	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32Val);
1999	break;
2000	case AC97_PCM_Front_DAC_Rate:
2001	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)
2002	{
2003	ichac97MixerSet(pThis, index, u32Val);
2004	LogFlowFunc(("Set front DAC rate to %RU32\n", u32Val));
2005	ichac97StreamReInit(pThis, &pThis->StreamOut);
2006	}
2007	else
2008	AssertMsgFailed(("Attempt to set front DAC rate to %RU32, but VRA is not set\n", u32Val));
2009	break;
2010	case AC97_MIC_ADC_Rate:
2011	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM)
2012	{
2013	ichac97MixerSet(pThis, index, u32Val);
2014	LogFlowFunc(("Set MIC ADC rate to %RU32\n", u32Val));
2015	ichac97StreamReInit(pThis, &pThis->StreamMicIn);
2016	}
2017	else
2018	AssertMsgFailed(("Attempt to set MIC ADC rate to %RU32, but VRM is not set\n", u32Val));
2019	break;
2020	case AC97_PCM_LR_ADC_Rate:
2021	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)
2022	{
2023	ichac97MixerSet(pThis, index, u32Val);
2024	LogFlowFunc(("Set front LR ADC rate to %RU32\n", u32Val));
2025	ichac97StreamReInit(pThis, &pThis->StreamLineIn);
2026	}
2027	else
2028	AssertMsgFailed(("Attempt to set LR ADC rate to %RU32, but VRA is not set\n", u32Val));
2029	break;
2030	default:
2031	LogFlowFunc(("U nam writew %#x <- %#x\n", Port, u32Val));
2032	ichac97MixerSet(pThis, index, u32Val);
2033	break;
2034	}
2035	break;
2036	}
2037
2038	case 4:
2039	{
2040	LogFlowFunc(("U nam writel %#x <- %#x\n", Port, u32Val));
2041	pThis->cas = 0;
2042	break;
2043	}
2044
2045	default:
2046	AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cbVal, u32Val));
2047	break;
2048	}
2049
2050	return VINF_SUCCESS;
2051	}
2052
2053
2054	/**
2055	* @callback_method_impl{FNPCIIOREGIONMAP}
2056	*/
2057	static DECLCALLBACK(int) ichac97IOPortMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
2058	PCIADDRESSSPACE enmType)
2059	{
2060	PPDMDEVINS pDevIns = pPciDev->pDevIns;
2061	PAC97STATE pThis = RT_FROM_MEMBER(pPciDev, AC97STATE, PciDev);
2062	RTIOPORT Port = (RTIOPORT)GCPhysAddress;
2063
2064	Assert(enmType == PCI_ADDRESS_SPACE_IO);
2065	Assert(cb >= 0x20);
2066
2067	if (iRegion < 0 \|\| iRegion > 1) /* We support 2 regions max. at the moment. */
2068	return VERR_INVALID_PARAMETER;
2069
2070	int rc;
2071	if (iRegion == 0)
2072	rc = PDMDevHlpIOPortRegister(pDevIns, Port, 256, pThis,
2073	ichac97IOPortNAMWrite, ichac97IOPortNAMRead,
2074	NULL, NULL, "ICHAC97 NAM");
2075	else
2076	rc = PDMDevHlpIOPortRegister(pDevIns, Port, 64, pThis,
2077	ichac97IOPortNABMWrite, ichac97IOPortNABMRead,
2078	NULL, NULL, "ICHAC97 NABM");
2079	if (RT_FAILURE(rc))
2080	return rc;
2081
2082	pThis->IOPortBase[iRegion] = Port;
2083	return VINF_SUCCESS;
2084	}
2085
2086	DECLINLINE(PAC97STREAM) ichac97GetStreamFromID(PAC97STATE pThis, uint32_t uID)
2087	{
2088	switch (uID)
2089	{
2090	case PI_INDEX: return &pThis->StreamLineIn;
2091	case MC_INDEX: return &pThis->StreamMicIn;
2092	case PO_INDEX: return &pThis->StreamOut;
2093	default: break;
2094	}
2095
2096	return NULL;
2097	}
2098
2099	#ifdef IN_RING3
2100	static int ichac97SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
2101	{
2102	PAC97BMREGS pRegs = &pStream->Regs;
2103
2104	SSMR3PutU32(pSSM, pRegs->bdbar);
2105	SSMR3PutU8( pSSM, pRegs->civ);
2106	SSMR3PutU8( pSSM, pRegs->lvi);
2107	SSMR3PutU16(pSSM, pRegs->sr);
2108	SSMR3PutU16(pSSM, pRegs->picb);
2109	SSMR3PutU8( pSSM, pRegs->piv);
2110	SSMR3PutU8( pSSM, pRegs->cr);
2111	SSMR3PutS32(pSSM, pRegs->bd_valid);
2112	SSMR3PutU32(pSSM, pRegs->bd.addr);
2113	SSMR3PutU32(pSSM, pRegs->bd.ctl_len);
2114
2115	return VINF_SUCCESS;
2116	}
2117
2118	/**
2119	* @callback_method_impl{FNSSMDEVSAVEEXEC}
2120	*/
2121	static DECLCALLBACK(int) ichac97SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2122	{
2123	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2124
2125	LogFlowFuncEnter();
2126
2127	SSMR3PutU32(pSSM, pThis->glob_cnt);
2128	SSMR3PutU32(pSSM, pThis->glob_sta);
2129	SSMR3PutU32(pSSM, pThis->cas);
2130
2131	/** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
2132	/* Note: The order the streams are saved here is critical, so don't touch. */
2133	int rc2 = ichac97SaveStream(pDevIns, pSSM, &pThis->StreamLineIn);
2134	AssertRC(rc2);
2135	rc2 = ichac97SaveStream(pDevIns, pSSM, &pThis->StreamOut);
2136	AssertRC(rc2);
2137	rc2 = ichac97SaveStream(pDevIns, pSSM, &pThis->StreamMicIn);
2138	AssertRC(rc2);
2139
2140	SSMR3PutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
2141
2142	uint8_t active[LAST_INDEX];
2143
2144	active[PI_INDEX] = ichac97StreamIsActive(pThis, &pThis->StreamLineIn) ? 1 : 0;
2145	active[PO_INDEX] = ichac97StreamIsActive(pThis, &pThis->StreamOut) ? 1 : 0;
2146	active[MC_INDEX] = ichac97StreamIsActive(pThis, &pThis->StreamMicIn) ? 1 : 0;
2147
2148	SSMR3PutMem(pSSM, active, sizeof(active));
2149
2150	LogFlowFuncLeaveRC(VINF_SUCCESS);
2151	return VINF_SUCCESS;
2152	}
2153
2154	static int ichac97LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
2155	{
2156	PAC97BMREGS pRegs = &pStream->Regs;
2157
2158	SSMR3GetU32(pSSM, &pRegs->bdbar);
2159	SSMR3GetU8( pSSM, &pRegs->civ);
2160	SSMR3GetU8( pSSM, &pRegs->lvi);
2161	SSMR3GetU16(pSSM, &pRegs->sr);
2162	SSMR3GetU16(pSSM, &pRegs->picb);
2163	SSMR3GetU8( pSSM, &pRegs->piv);
2164	SSMR3GetU8( pSSM, &pRegs->cr);
2165	SSMR3GetS32(pSSM, &pRegs->bd_valid);
2166	SSMR3GetU32(pSSM, &pRegs->bd.addr);
2167	SSMR3GetU32(pSSM, &pRegs->bd.ctl_len);
2168
2169	return VINF_SUCCESS;
2170	}
2171
2172	/**
2173	* @callback_method_impl{FNSSMDEVLOADEXEC}
2174	*/
2175	static DECLCALLBACK(int) ichac97LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2176	{
2177	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2178
2179	LogRel2(("ichac97LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
2180
2181	AssertMsgReturn (uVersion == AC97_SSM_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
2182	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2183
2184	SSMR3GetU32(pSSM, &pThis->glob_cnt);
2185	SSMR3GetU32(pSSM, &pThis->glob_sta);
2186	SSMR3GetU32(pSSM, &pThis->cas);
2187
2188	/** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
2189	/* Note: The order the streams are loaded here is critical, so don't touch. */
2190	int rc2 = ichac97LoadStream(pDevIns, pSSM, &pThis->StreamLineIn);
2191	AssertRC(rc2);
2192	rc2 = ichac97LoadStream(pDevIns, pSSM, &pThis->StreamOut);
2193	AssertRC(rc2);
2194	rc2 = ichac97LoadStream(pDevIns, pSSM, &pThis->StreamMicIn);
2195	AssertRC(rc2);
2196
2197	SSMR3GetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
2198
2199	/** @todo r=andy Stream IDs are hardcoded to certain streams. */
2200	uint8_t uaStrmsActive[LAST_INDEX];
2201	SSMR3GetMem(pSSM, uaStrmsActive, sizeof(uaStrmsActive));
2202
2203	ichac97RecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
2204	# define V_(a, b) ichac97MixerSetVolume(pThis, a, b, ichac97MixerGet(pThis, a))
2205	V_(AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME);
2206	V_(AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT);
2207	V_(AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN);
2208	# undef V_
2209	if (pThis->uCodecModel == Codec_AD1980)
2210	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AD_MISC_HPSEL)
2211	ichac97MixerSetVolume(pThis, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME,
2212	ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
2213
2214	int rc = ichac97StreamsInit(pThis);
2215	if (RT_SUCCESS(rc))
2216	{
2217	/** @todo r=andy Stream IDs are hardcoded to certain streams. */
2218	rc = ichac97StreamSetActive(pThis, &pThis->StreamLineIn, RT_BOOL(uaStrmsActive[PI_INDEX]));
2219	if (RT_SUCCESS(rc))
2220	rc = ichac97StreamSetActive(pThis, &pThis->StreamMicIn, RT_BOOL(uaStrmsActive[MC_INDEX]));
2221	if (RT_SUCCESS(rc))
2222	rc = ichac97StreamSetActive(pThis, &pThis->StreamOut, RT_BOOL(uaStrmsActive[PO_INDEX]));
2223	}
2224
2225	pThis->bup_flag = 0;
2226	pThis->last_samp = 0;
2227
2228	LogFlowFuncLeaveRC(rc);
2229	return rc;
2230	}
2231
2232
2233	/**
2234	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
2235	*/
2236	static DECLCALLBACK(void ) ichac97QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
2237	{
2238	PAC97STATE pThis = RT_FROM_MEMBER(pInterface, AC97STATE, IBase);
2239	Assert(&pThis->IBase == pInterface);
2240
2241	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2242	return NULL;
2243	}
2244
2245
2246	/**
2247	* Powers off the device.
2248	*
2249	* @param pDevIns Device instance to power off.
2250	*/
2251	static DECLCALLBACK(void) ichac97PowerOff(PPDMDEVINS pDevIns)
2252	{
2253	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2254
2255	LogRel2(("AC97: Powering off ...\n"));
2256
2257	/**
2258	* Note: Destroy the mixer while powering off and not in ichac97Destruct,
2259	* giving the mixer the chance to release any references held to
2260	* PDM audio streams it maintains.
2261	*/
2262	if (pThis->pMixer)
2263	{
2264	AudioMixerDestroy(pThis->pMixer);
2265	pThis->pMixer = NULL;
2266	}
2267	}
2268
2269
2270	/**
2271	* @interface_method_impl{PDMDEVREG,pfnReset}
2272	*
2273	* @remarks The original sources didn't install a reset handler, but it seems to
2274	* make sense to me so we'll do it.
2275	*/
2276	static DECLCALLBACK(void) ichac97Reset(PPDMDEVINS pDevIns)
2277	{
2278	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2279
2280	LogFlowFuncEnter();
2281
2282	/*
2283	* Reset the device state (will need pDrv later).
2284	*/
2285	ichac97StreamResetBMRegs(pThis, &pThis->StreamLineIn);
2286	ichac97StreamResetBMRegs(pThis, &pThis->StreamMicIn);
2287	ichac97StreamResetBMRegs(pThis, &pThis->StreamOut);
2288
2289	/*
2290	* Reset the mixer too. The Windows XP driver seems to rely on
2291	* this. At least it wants to read the vendor id before it resets
2292	* the codec manually.
2293	*/
2294	ichac97MixerReset(pThis);
2295
2296	/*
2297	* Stop any audio currently playing and/or recording.
2298	*/
2299	AudioMixerSinkCtl(pThis->pSinkOutput, AUDMIXSINKCMD_DISABLE);
2300	AudioMixerSinkCtl(pThis->pSinkMicIn, AUDMIXSINKCMD_DISABLE);
2301	AudioMixerSinkCtl(pThis->pSinkLineIn, AUDMIXSINKCMD_DISABLE);
2302
2303	/*
2304	* Reset all streams.
2305	*/
2306	ichac97StreamReset(pThis, &pThis->StreamLineIn);
2307	ichac97StreamReset(pThis, &pThis->StreamMicIn);
2308	ichac97StreamReset(pThis, &pThis->StreamOut);
2309
2310	LogRel(("AC97: Reset\n"));
2311	}
2312
2313
2314	/**
2315	* @interface_method_impl{PDMDEVREG,pfnDestruct}
2316	*/
2317	static DECLCALLBACK(int) ichac97Destruct(PPDMDEVINS pDevIns)
2318	{
2319	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2320
2321	LogFlowFuncEnter();
2322
2323	ichac97StreamDestroy(&pThis->StreamLineIn);
2324	ichac97StreamDestroy(&pThis->StreamMicIn);
2325	ichac97StreamDestroy(&pThis->StreamOut);
2326
2327	PAC97DRIVER pDrv, pDrvNext;
2328	RTListForEachSafe(&pThis->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
2329	{
2330	RTListNodeRemove(&pDrv->Node);
2331	RTMemFree(pDrv);
2332	}
2333
2334	/* Sanity. */
2335	Assert(RTListIsEmpty(&pThis->lstDrv));
2336
2337	LogFlowFuncLeave();
2338	return VINF_SUCCESS;
2339	}
2340
2341
2342	/**
2343	* Attach command, internal version.
2344	*
2345	* This is called to let the device attach to a driver for a specified LUN
2346	* during runtime. This is not called during VM construction, the device
2347	* constructor has to attach to all the available drivers.
2348	*
2349	* @returns VBox status code.
2350	* @param pDevIns The device instance.
2351	* @param pDrv Driver to (re-)use for (re-)attaching to.
2352	* If NULL is specified, a new driver will be created and appended
2353	* to the driver list.
2354	* @param uLUN The logical unit which is being detached.
2355	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
2356	*/
2357	static DECLCALLBACK(int) ichac97AttachInternal(PPDMDEVINS pDevIns, PAC97DRIVER pDrv, unsigned uLUN, uint32_t fFlags)
2358	{
2359	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2360
2361	/*
2362	* Attach driver.
2363	*/
2364	char *pszDesc = NULL;
2365	if (RTStrAPrintf(&pszDesc, "Audio driver port (AC'97) for LUN #%u", uLUN) <= 0)
2366	AssertReleaseMsgReturn(pszDesc,
2367	("Not enough memory for AC'97 driver port description of LUN #%u\n", uLUN),
2368	VERR_NO_MEMORY);
2369
2370	PPDMIBASE pDrvBase;
2371	int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
2372	&pThis->IBase, &pDrvBase, pszDesc);
2373	if (RT_SUCCESS(rc))
2374	{
2375	if (pDrv == NULL)
2376	pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
2377	if (pDrv)
2378	{
2379	pDrv->pDrvBase = pDrvBase;
2380	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
2381	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN #%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
2382	pDrv->pAC97State = pThis;
2383	pDrv->uLUN = uLUN;
2384
2385	/*
2386	* For now we always set the driver at LUN 0 as our primary
2387	* host backend. This might change in the future.
2388	*/
2389	if (pDrv->uLUN == 0)
2390	pDrv->Flags \|= PDMAUDIODRVFLAG_PRIMARY;
2391
2392	LogFunc(("LUN#%RU8: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
2393
2394	/* Attach to driver list if not attached yet. */
2395	if (!pDrv->fAttached)
2396	{
2397	RTListAppend(&pThis->lstDrv, &pDrv->Node);
2398	pDrv->fAttached = true;
2399	}
2400	}
2401	else
2402	rc = VERR_NO_MEMORY;
2403	}
2404	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2405	LogFunc(("No attached driver for LUN #%u\n", uLUN));
2406
2407	if (RT_FAILURE(rc))
2408	{
2409	/* Only free this string on failure;
2410	* must remain valid for the live of the driver instance. */
2411	RTStrFree(pszDesc);
2412	}
2413
2414	LogFunc(("iLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
2415	return rc;
2416	}
2417
2418
2419	/**
2420	* Attach command.
2421	*
2422	* This is called to let the device attach to a driver for a specified LUN
2423	* during runtime. This is not called during VM construction, the device
2424	* constructor has to attach to all the available drivers.
2425	*
2426	* @returns VBox status code.
2427	* @param pDevIns The device instance.
2428	* @param uLUN The logical unit which is being detached.
2429	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
2430	*/
2431	static DECLCALLBACK(int) ichac97Attach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
2432	{
2433	return ichac97AttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
2434	}
2435
2436	static DECLCALLBACK(void) ichac97Detach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
2437	{
2438	LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
2439	}
2440
2441	/**
2442	* Re-attach.
2443	*
2444	* @returns VBox status code.
2445	* @param pThis Device instance.
2446	* @param pDrv Driver instance used for attaching to.
2447	* If NULL is specified, a new driver will be created and appended
2448	* to the driver list.
2449	* @param uLUN The logical unit which is being re-detached.
2450	* @param pszDriver Driver name.
2451	*/
2452	static int ichac97Reattach(PAC97STATE pThis, PAC97DRIVER pDrv, uint8_t uLUN, const char *pszDriver)
2453	{
2454	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2455	AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
2456
2457	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2458	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
2459	PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/ichac97/0/");
2460
2461	/* Remove LUN branch. */
2462	CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
2463
2464	if (pDrv)
2465	{
2466	/* Re-use a driver instance => detach the driver before. */
2467	int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
2468	if (RT_FAILURE(rc))
2469	return rc;
2470	}
2471
2472	#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
2473
2474	int rc;
2475	do
2476	{
2477	PCFGMNODE pLunL0;
2478	rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
2479	rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
2480	rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
2481
2482	PCFGMNODE pLunL1, pLunL2;
2483	rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
2484	rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
2485	rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
2486
2487	rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
2488
2489	} while (0);
2490
2491	if (RT_SUCCESS(rc))
2492	rc = ichac97AttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
2493
2494	LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
2495
2496	#undef RC_CHECK
2497
2498	return rc;
2499	}
2500
2501	/**
2502	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2503	*/
2504	static DECLCALLBACK(int) ichac97Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2505	{
2506	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2507
2508	/* NB: This must be done before any possible failure (and running the destructor). */
2509	RTListInit(&pThis->lstDrv);
2510
2511	Assert(iInstance == 0);
2512	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2513
2514	/*
2515	* Validations.
2516	*/
2517	if (!CFGMR3AreValuesValid(pCfg,
2518	"Codec\0"
2519	"TimerHz\0"))
2520	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2521	N_("Invalid configuration for the AC'97 device"));
2522
2523	/*
2524	* Read config data.
2525	*/
2526	char szCodec[20];
2527	int rc = CFGMR3QueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
2528	if (RT_FAILURE(rc))
2529	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2530	N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
2531
2532	#ifndef VBOX_WITH_AUDIO_CALLBACKS
2533	uint16_t uTimerHz;
2534	rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, AC97_TIMER_HZ /* Default value, if not set. */);
2535	if (RT_FAILURE(rc))
2536	return PDMDEV_SET_ERROR(pDevIns, rc,
2537	N_("AC'97 configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
2538	#endif
2539
2540	/*
2541	* The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
2542	* in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
2543	* 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
2544	*/
2545	bool fChipAD1980 = false;
2546	if (!strcmp(szCodec, "STAC9700"))
2547	pThis->uCodecModel = Codec_STAC9700;
2548	else if (!strcmp(szCodec, "AD1980"))
2549	pThis->uCodecModel = Codec_AD1980;
2550	else if (!strcmp(szCodec, "AD1981B"))
2551	pThis->uCodecModel = Codec_AD1981B;
2552	else
2553	{
2554	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
2555	N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"),
2556	szCodec);
2557	}
2558
2559	/*
2560	* Initialize data (most of it anyway).
2561	*/
2562	pThis->pDevInsR3 = pDevIns;
2563	/* IBase */
2564	pThis->IBase.pfnQueryInterface = ichac97QueryInterface;
2565
2566	/* PCI Device (the assertions will be removed later) */
2567	PCIDevSetVendorId (&pThis->PciDev, 0x8086); /* 00 ro - intel. */ Assert(pThis->PciDev.config[0x00] == 0x86); Assert(pThis->PciDev.config[0x01] == 0x80);
2568	PCIDevSetDeviceId (&pThis->PciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pThis->PciDev.config[0x02] == 0x15); Assert(pThis->PciDev.config[0x03] == 0x24);
2569	PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pThis->PciDev.config[0x04] == 0x00); Assert(pThis->PciDev.config[0x05] == 0x00);
2570	PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM \| VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pThis->PciDev.config[0x06] == 0x80); Assert(pThis->PciDev.config[0x07] == 0x02);
2571	PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */ Assert(pThis->PciDev.config[0x08] == 0x01);
2572	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */ Assert(pThis->PciDev.config[0x09] == 0x00);
2573	PCIDevSetClassSub (&pThis->PciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pThis->PciDev.config[0x0a] == 0x01);
2574	PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */ Assert(pThis->PciDev.config[0x0b] == 0x04);
2575	PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */ Assert(pThis->PciDev.config[0x0e] == 0x00);
2576	PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - nambar - native audio mixer base. */
2577	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pThis->PciDev.config[0x10] == 0x01); Assert(pThis->PciDev.config[0x11] == 0x00); Assert(pThis->PciDev.config[0x12] == 0x00); Assert(pThis->PciDev.config[0x13] == 0x00);
2578	PCIDevSetBaseAddress (&pThis->PciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
2579	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pThis->PciDev.config[0x14] == 0x01); Assert(pThis->PciDev.config[0x15] == 0x00); Assert(pThis->PciDev.config[0x16] == 0x00); Assert(pThis->PciDev.config[0x17] == 0x00);
2580	PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */ Assert(pThis->PciDev.config[0x3c] == 0x00);
2581	PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */ Assert(pThis->PciDev.config[0x3d] == 0x01);
2582
2583	if (pThis->uCodecModel == Codec_AD1980)
2584	{
2585	PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x1028); /* 2c ro - Dell.) */
2586	PCIDevSetSubSystemId (&pThis->PciDev, 0x0177); /* 2e ro. */
2587	}
2588	else if (pThis->uCodecModel == Codec_AD1981B)
2589	{
2590	PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x1028); /* 2c ro - Dell.) */
2591	PCIDevSetSubSystemId (&pThis->PciDev, 0x01ad); /* 2e ro. */
2592	}
2593	else
2594	{
2595	PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x8086); /* 2c ro - Intel.) */
2596	PCIDevSetSubSystemId (&pThis->PciDev, 0x0000); /* 2e ro. */
2597	}
2598
2599	/*
2600	* Register the PCI device, it's I/O regions, the timer and the
2601	* saved state item.
2602	*/
2603	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
2604	if (RT_FAILURE(rc))
2605	return rc;
2606
2607	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 256, PCI_ADDRESS_SPACE_IO, ichac97IOPortMap);
2608	if (RT_FAILURE(rc))
2609	return rc;
2610
2611	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 64, PCI_ADDRESS_SPACE_IO, ichac97IOPortMap);
2612	if (RT_FAILURE(rc))
2613	return rc;
2614
2615	rc = PDMDevHlpSSMRegister(pDevIns, AC97_SSM_VERSION, sizeof(*pThis), ichac97SaveExec, ichac97LoadExec);
2616	if (RT_FAILURE(rc))
2617	return rc;
2618
2619	/*
2620	* Attach driver.
2621	*/
2622	uint8_t uLUN;
2623	for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
2624	{
2625	LogFunc(("Trying to attach driver for LUN #%RU8 ...\n", uLUN));
2626	rc = ichac97AttachInternal(pDevIns, NULL /* pDrv /, uLUN, 0 / fFlags */);
2627	if (RT_FAILURE(rc))
2628	{
2629	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2630	rc = VINF_SUCCESS;
2631	else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
2632	{
2633	ichac97Reattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
2634	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
2635	N_("No audio devices could be opened. Selecting the NULL audio backend "
2636	"with the consequence that no sound is audible"));
2637	/* attaching to the NULL audio backend will never fail */
2638	rc = VINF_SUCCESS;
2639	}
2640	break;
2641	}
2642	}
2643
2644	LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
2645
2646	if (RT_SUCCESS(rc))
2647	{
2648	rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThis->pMixer);
2649	if (RT_SUCCESS(rc))
2650	{
2651	/* Set a default audio format for our mixer. */
2652	PDMAUDIOSTREAMCFG streamCfg;
2653	streamCfg.uHz = 44100;
2654	streamCfg.cChannels = 2;
2655	streamCfg.enmFormat = PDMAUDIOFMT_S16;
2656	streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
2657
2658	rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
2659	AssertRC(rc);
2660
2661	/* Add all required audio sinks. */
2662	int rc2 = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output", AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
2663	AssertRC(rc2);
2664
2665	rc2 = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In", AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
2666	AssertRC(rc2);
2667
2668	rc2 = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In", AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
2669	AssertRC(rc2);
2670	}
2671	}
2672
2673	ichac97Reset(pDevIns);
2674
2675	if (RT_SUCCESS(rc))
2676	{
2677	ichac97StreamsInit(pThis);
2678
2679	PAC97DRIVER pDrv;
2680	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
2681	{
2682	/*
2683	* Only primary drivers are critical for the VM to run. Everything else
2684	* might not worth showing an own error message box in the GUI.
2685	*/
2686	if (!(pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY))
2687	continue;
2688
2689	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
2690	AssertPtr(pCon);
2691
2692	bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
2693	bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
2694	bool fValidOut = AudioMixerStreamIsValid(pDrv->Out.pMixStrm);
2695
2696	if ( !fValidLineIn
2697	&& !fValidMicIn
2698	&& !fValidOut)
2699	{
2700	LogRel(("AC97: Falling back to NULL backend (no sound audible)\n"));
2701
2702	/* Destroy the streams before re-attaching the NULL driver. */
2703	ichac97StreamsDestroy(pThis);
2704
2705	ichac97Reset(pDevIns);
2706	ichac97Reattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
2707
2708	ichac97StreamsInit(pThis);
2709
2710	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
2711	N_("No audio devices could be opened. Selecting the NULL audio backend "
2712	"with the consequence that no sound is audible"));
2713	}
2714	else
2715	{
2716	bool fWarn = false;
2717
2718	PDMAUDIOBACKENDCFG backendCfg;
2719	int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
2720	if (RT_SUCCESS(rc2))
2721	{
2722	if (backendCfg.cSources)
2723	{
2724	/* If the audio backend supports two or more input streams at once,
2725	* warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
2726	if (backendCfg.cMaxStreamsIn >= 2)
2727	fWarn = !fValidLineIn \|\| !fValidMicIn;
2728	/* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
2729	* not ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
2730	* One of the two simply is not in use then. */
2731	else if (backendCfg.cMaxStreamsIn == 1)
2732	fWarn = !fValidLineIn && !fValidMicIn;
2733	/* Don't warn if our backend is not able of supporting any input streams at all. */
2734	}
2735
2736	if ( !fWarn
2737	&& backendCfg.cSinks)
2738	{
2739	fWarn = !fValidOut;
2740	}
2741	}
2742	else
2743	{
2744	LogRel(("AC97: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
2745	fWarn = true;
2746	}
2747
2748	if (fWarn)
2749	{
2750	char szMissingStreams[255];
2751	size_t len = 0;
2752	if (!fValidLineIn)
2753	{
2754	LogRel(("AC97: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
2755	len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
2756	}
2757	if (!fValidMicIn)
2758	{
2759	LogRel(("AC97: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
2760	len += RTStrPrintf(szMissingStreams + len,
2761	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
2762	}
2763	if (!fValidOut)
2764	{
2765	LogRel(("AC97: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
2766	len += RTStrPrintf(szMissingStreams + len,
2767	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
2768	}
2769
2770	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
2771	N_("Some AC'97 audio streams (%s) could not be opened. Guest applications generating audio "
2772	"output or depending on audio input may hang. Make sure your host audio device "
2773	"is working properly. Check the logfile for error messages of the audio "
2774	"subsystem"), szMissingStreams);
2775	}
2776	}
2777	}
2778	}
2779
2780	# ifndef VBOX_WITH_AUDIO_CALLBACKS
2781	if (RT_SUCCESS(rc))
2782	{
2783	/* Start the emulation timer. */
2784	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, ichac97Timer, pThis,
2785	TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchAc97", &pThis->pTimer);
2786	AssertRCReturn(rc, rc);
2787
2788	if (RT_SUCCESS(rc))
2789	{
2790	pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
2791	pThis->uTimerTS = TMTimerGet(pThis->pTimer);
2792	LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
2793
2794	ichac97TimerMaybeStart(pThis);
2795	}
2796	}
2797	# else
2798	if (RT_SUCCESS(rc))
2799	{
2800	PAC97DRIVER pDrv;
2801	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
2802	{
2803	/* Only register primary driver.
2804	* The device emulation does the output multiplexing then. */
2805	if (!(pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY))
2806	continue;
2807
2808	PDMAUDIOCALLBACK AudioCallbacks[2];
2809
2810	AC97CALLBACKCTX Ctx = { pThis, pDrv };
2811
2812	AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
2813	AudioCallbacks[0].pfnCallback = ac97CallbackInput;
2814	AudioCallbacks[0].pvCtx = &Ctx;
2815	AudioCallbacks[0].cbCtx = sizeof(AC97CALLBACKCTX);
2816
2817	AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
2818	AudioCallbacks[1].pfnCallback = ac97CallbackOutput;
2819	AudioCallbacks[1].pvCtx = &Ctx;
2820	AudioCallbacks[1].cbCtx = sizeof(AC97CALLBACKCTX);
2821
2822	rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
2823	if (RT_FAILURE(rc))
2824	break;
2825	}
2826	}
2827	# endif
2828
2829	# ifdef VBOX_WITH_STATISTICS
2830	if (RT_SUCCESS(rc))
2831	{
2832	/*
2833	* Register statistics.
2834	*/
2835	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/AC97/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
2836	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/AC97/BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
2837	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/AC97/BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
2838	}
2839	# endif
2840
2841	LogFlowFuncLeaveRC(rc);
2842	return rc;
2843	}
2844
2845	/**
2846	* The device registration structure.
2847	*/
2848	const PDMDEVREG g_DeviceICHAC97 =
2849	{
2850	/* u32Version */
2851	PDM_DEVREG_VERSION,
2852	/* szName */
2853	"ichac97",
2854	/* szRCMod */
2855	"",
2856	/* szR0Mod */
2857	"",
2858	/* pszDescription */
2859	"ICH AC'97 Audio Controller",
2860	/* fFlags */
2861	PDM_DEVREG_FLAGS_DEFAULT_BITS,
2862	/* fClass */
2863	PDM_DEVREG_CLASS_AUDIO,
2864	/* cMaxInstances */
2865	1,
2866	/* cbInstance */
2867	sizeof(AC97STATE),
2868	/* pfnConstruct */
2869	ichac97Construct,
2870	/* pfnDestruct */
2871	ichac97Destruct,
2872	/* pfnRelocate */
2873	NULL,
2874	/* pfnMemSetup */
2875	NULL,
2876	/* pfnPowerOn */
2877	NULL,
2878	/* pfnReset */
2879	ichac97Reset,
2880	/* pfnSuspend */
2881	NULL,
2882	/* pfnResume */
2883	NULL,
2884	/* pfnAttach */
2885	ichac97Attach,
2886	/* pfnDetach */
2887	ichac97Detach,
2888	/* pfnQueryInterface. */
2889	NULL,
2890	/* pfnInitComplete */
2891	NULL,
2892	/* pfnPowerOff */
2893	ichac97PowerOff,
2894	/* pfnSoftReset */
2895	NULL,
2896	/* u32VersionEnd */
2897	PDM_DEVREG_VERSION
2898	};
2899
2900	#endif /* !IN_RING3 */
2901	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 61613

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