DevIchAc97.cpp@ 74005

Last change on this file since 74005 was 73833, checked in by vboxsync, 6 years ago
Audio: Async I/O fixes for HDA + AC'97.
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1	/* $Id: DevIchAc97.cpp 73833 2018-08-22 15:40:27Z vboxsync $ */
2	/** @file
3	* DevIchAc97 - VBox ICH AC97 Audio Controller.
4	*/
5
6	/*
7	* Copyright (C) 2006-2018 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_AC97
23	#include <VBox/log.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/vmm/pdmaudioifs.h>
26
27	#include <iprt/assert.h>
28	#ifdef IN_RING3
29	# ifdef DEBUG
30	# include <iprt/file.h>
31	# endif
32	# include <iprt/mem.h>
33	# include <iprt/semaphore.h>
34	# include <iprt/string.h>
35	# include <iprt/uuid.h>
36	#endif
37
38	#include "VBoxDD.h"
39
40	#include "AudioMixBuffer.h"
41	#include "AudioMixer.h"
42	#include "DrvAudio.h"
43
44
45	/*********************************************************************************************************************************
46	* Defined Constants And Macros *
47	*********************************************************************************************************************************/
48
49	/** Current saved state version. */
50	#define AC97_SSM_VERSION 1
51
52	/** Default timer frequency (in Hz). */
53	#define AC97_TIMER_HZ 200
54
55	/** Maximum FIFO size (in bytes). */
56	#define AC97_FIFO_MAX 256
57
58	#define AC97_SR_FIFOE RT_BIT(4) /*< rwc, FIFO error. /
59	#define AC97_SR_BCIS RT_BIT(3) /*< rwc, Buffer completion interrupt status. /
60	#define AC97_SR_LVBCI RT_BIT(2) /*< rwc, Last valid buffer completion interrupt. /
61	#define AC97_SR_CELV RT_BIT(1) /*< ro, Current equals last valid. /
62	#define AC97_SR_DCH RT_BIT(0) /*< ro, Controller halted. /
63	#define AC97_SR_VALID_MASK (RT_BIT(5) - 1)
64	#define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE \| AC97_SR_BCIS \| AC97_SR_LVBCI)
65	#define AC97_SR_RO_MASK (AC97_SR_DCH \| AC97_SR_CELV)
66	#define AC97_SR_INT_MASK (AC97_SR_FIFOE \| AC97_SR_BCIS \| AC97_SR_LVBCI)
67
68	#define AC97_CR_IOCE RT_BIT(4) /*< rw, Interrupt On Completion Enable. /
69	#define AC97_CR_FEIE RT_BIT(3) /*< rw FIFO Error Interrupt Enable. /
70	#define AC97_CR_LVBIE RT_BIT(2) /*< rw Last Valid Buffer Interrupt Enable. /
71	#define AC97_CR_RR RT_BIT(1) /*< rw Reset Registers. /
72	#define AC97_CR_RPBM RT_BIT(0) /*< rw Run/Pause Bus Master. /
73	#define AC97_CR_VALID_MASK (RT_BIT(5) - 1)
74	#define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE \| AC97_CR_FEIE \| AC97_CR_LVBIE)
75
76	#define AC97_GC_WR 4 /*< rw Warm reset. /
77	#define AC97_GC_CR 2 /*< rw Cold reset. /
78	#define AC97_GC_VALID_MASK (RT_BIT(6) - 1)
79
80	#define AC97_GS_MD3 RT_BIT(17) /*< rw /
81	#define AC97_GS_AD3 RT_BIT(16) /*< rw /
82	#define AC97_GS_RCS RT_BIT(15) /*< rwc /
83	#define AC97_GS_B3S12 RT_BIT(14) /*< ro /
84	#define AC97_GS_B2S12 RT_BIT(13) /*< ro /
85	#define AC97_GS_B1S12 RT_BIT(12) /*< ro /
86	#define AC97_GS_S1R1 RT_BIT(11) /*< rwc /
87	#define AC97_GS_S0R1 RT_BIT(10) /*< rwc /
88	#define AC97_GS_S1CR RT_BIT(9) /*< ro /
89	#define AC97_GS_S0CR RT_BIT(8) /*< ro /
90	#define AC97_GS_MINT RT_BIT(7) /*< ro /
91	#define AC97_GS_POINT RT_BIT(6) /*< ro /
92	#define AC97_GS_PIINT RT_BIT(5) /*< ro /
93	#define AC97_GS_RSRVD (RT_BIT(4) \| RT_BIT(3))
94	#define AC97_GS_MOINT RT_BIT(2) /*< ro /
95	#define AC97_GS_MIINT RT_BIT(1) /*< ro /
96	#define AC97_GS_GSCI RT_BIT(0) /*< rwc /
97	#define AC97_GS_RO_MASK ( AC97_GS_B3S12 \
98	\| AC97_GS_B2S12 \
99	\| AC97_GS_B1S12 \
100	\| AC97_GS_S1CR \
101	\| AC97_GS_S0CR \
102	\| AC97_GS_MINT \
103	\| AC97_GS_POINT \
104	\| AC97_GS_PIINT \
105	\| AC97_GS_RSRVD \
106	\| AC97_GS_MOINT \
107	\| AC97_GS_MIINT)
108	#define AC97_GS_VALID_MASK (RT_BIT(18) - 1)
109	#define AC97_GS_WCLEAR_MASK (AC97_GS_RCS \| AC97_GS_S1R1 \| AC97_GS_S0R1 \| AC97_GS_GSCI)
110
111	/** @name Buffer Descriptor (BD).
112	* @{ */
113	#define AC97_BD_IOC RT_BIT(31) /*< Interrupt on Completion. /
114	#define AC97_BD_BUP RT_BIT(30) /*< Buffer Underrun Policy. /
115
116	#define AC97_BD_LEN_MASK 0xFFFF /*< Mask for the BDL buffer length. /
117
118	#define AC97_MAX_BDLE 32 /*< Maximum number of BDLEs. /
119	/** @} */
120
121	/** @name Extended Audio Status and Control Register (EACS).
122	* @{ */
123	#define AC97_EACS_VRA 1 /*< Variable Rate Audio (4.2.1.1). /
124	#define AC97_EACS_VRM 8 /*< Variable Rate Mic Audio (4.2.1.1). /
125	/** @} */
126
127	/** @name Baseline Audio Register Set (BARS).
128	* @{ */
129	#define AC97_BARS_VOL_MASK 0x1f /*< Volume mask for the Baseline Audio Register Set (5.7.2). /
130	#define AC97_BARS_VOL_STEPS 31 /*< Volume steps for the Baseline Audio Register Set (5.7.2). /
131	#define AC97_BARS_VOL_MUTE_SHIFT 15 /*< Mute bit shift for the Baseline Audio Register Set (5.7.2). /
132	/** @} */
133
134	/* AC'97 uses 1.5dB steps, we use 0.375dB steps: 1 AC'97 step equals 4 PDM steps. */
135	#define AC97_DB_FACTOR 4
136
137	#define AC97_REC_MASK 7
138	enum
139	{
140	AC97_REC_MIC = 0,
141	AC97_REC_CD,
142	AC97_REC_VIDEO,
143	AC97_REC_AUX,
144	AC97_REC_LINE_IN,
145	AC97_REC_STEREO_MIX,
146	AC97_REC_MONO_MIX,
147	AC97_REC_PHONE
148	};
149
150	enum
151	{
152	AC97_Reset = 0x00,
153	AC97_Master_Volume_Mute = 0x02,
154	AC97_Headphone_Volume_Mute = 0x04, /** Also known as AUX, see table 16, section 5.7. */
155	AC97_Master_Volume_Mono_Mute = 0x06,
156	AC97_Master_Tone_RL = 0x08,
157	AC97_PC_BEEP_Volume_Mute = 0x0A,
158	AC97_Phone_Volume_Mute = 0x0C,
159	AC97_Mic_Volume_Mute = 0x0E,
160	AC97_Line_In_Volume_Mute = 0x10,
161	AC97_CD_Volume_Mute = 0x12,
162	AC97_Video_Volume_Mute = 0x14,
163	AC97_Aux_Volume_Mute = 0x16,
164	AC97_PCM_Out_Volume_Mute = 0x18,
165	AC97_Record_Select = 0x1A,
166	AC97_Record_Gain_Mute = 0x1C,
167	AC97_Record_Gain_Mic_Mute = 0x1E,
168	AC97_General_Purpose = 0x20,
169	AC97_3D_Control = 0x22,
170	AC97_AC_97_RESERVED = 0x24,
171	AC97_Powerdown_Ctrl_Stat = 0x26,
172	AC97_Extended_Audio_ID = 0x28,
173	AC97_Extended_Audio_Ctrl_Stat = 0x2A,
174	AC97_PCM_Front_DAC_Rate = 0x2C,
175	AC97_PCM_Surround_DAC_Rate = 0x2E,
176	AC97_PCM_LFE_DAC_Rate = 0x30,
177	AC97_PCM_LR_ADC_Rate = 0x32,
178	AC97_MIC_ADC_Rate = 0x34,
179	AC97_6Ch_Vol_C_LFE_Mute = 0x36,
180	AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
181	AC97_Vendor_Reserved = 0x58,
182	AC97_AD_Misc = 0x76,
183	AC97_Vendor_ID1 = 0x7c,
184	AC97_Vendor_ID2 = 0x7e
185	};
186
187	/* Codec models. */
188	typedef enum
189	{
190	AC97_CODEC_STAC9700 = 0, /*< SigmaTel STAC9700 /
191	AC97_CODEC_AD1980, /*< Analog Devices AD1980 /
192	AC97_CODEC_AD1981B /*< Analog Devices AD1981B /
193	} AC97CODEC;
194
195	/* Analog Devices miscellaneous regiter bits used in AD1980. */
196	#define AC97_AD_MISC_LOSEL RT_BIT(5) /*< Surround (rear) goes to line out outputs. /
197	#define AC97_AD_MISC_HPSEL RT_BIT(10) /*< PCM (front) goes to headphone outputs. /
198
199	#define ICHAC97STATE_2_DEVINS(a_pAC97) ((a_pAC97)->CTX_SUFF(pDevIns))
200
201	enum
202	{
203	BUP_SET = RT_BIT(0),
204	BUP_LAST = RT_BIT(1)
205	};
206
207	/** Emits registers for a specific (Native Audio Bus Master BAR) NABMBAR.
208	* @todo This totally messes with grepping for identifiers and tagging. */
209	#define AC97_NABMBAR_REGS(prefix, off) \
210	enum { \
211	prefix ## _BDBAR = off, /* Buffer Descriptor Base Address */ \
212	prefix ## _CIV = off + 4, /* Current Index Value */ \
213	prefix ## _LVI = off + 5, /* Last Valid Index */ \
214	prefix ## _SR = off + 6, /* Status Register */ \
215	prefix ## _PICB = off + 8, /* Position in Current Buffer */ \
216	prefix ## _PIV = off + 10, /* Prefetched Index Value */ \
217	prefix ## _CR = off + 11 /* Control Register */ \
218	}
219
220	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
221	typedef enum
222	{
223	AC97SOUNDSOURCE_PI_INDEX = 0, /*< PCM in /
224	AC97SOUNDSOURCE_PO_INDEX, /*< PCM out /
225	AC97SOUNDSOURCE_MC_INDEX, /*< Mic in /
226	AC97SOUNDSOURCE_END_INDEX
227	} AC97SOUNDSOURCE;
228
229	AC97_NABMBAR_REGS(PI, AC97SOUNDSOURCE_PI_INDEX * 16);
230	AC97_NABMBAR_REGS(PO, AC97SOUNDSOURCE_PO_INDEX * 16);
231	AC97_NABMBAR_REGS(MC, AC97SOUNDSOURCE_MC_INDEX * 16);
232	#endif
233
234	enum
235	{
236	/** NABMBAR: Global Control Register. */
237	AC97_GLOB_CNT = 0x2c,
238	/** NABMBAR Global Status. */
239	AC97_GLOB_STA = 0x30,
240	/** Codec Access Semaphore Register. */
241	AC97_CAS = 0x34
242	};
243
244	#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
245
246
247	/*********************************************************************************************************************************
248	* Structures and Typedefs *
249	*********************************************************************************************************************************/
250
251	/**
252	* Buffer Descriptor List Entry (BDLE).
253	*/
254	typedef struct AC97BDLE
255	{
256	uint32_t addr;
257	uint32_t ctl_len;
258	} AC97BDLE, *PAC97BDLE;
259
260	/**
261	* Bus master register set for an audio stream.
262	*/
263	typedef struct AC97BMREGS
264	{
265	uint32_t bdbar; /** rw 0, Buffer Descriptor List: BAR (Base Address Register). */
266	uint8_t civ; /** ro 0, Current index value. */
267	uint8_t lvi; /** rw 0, Last valid index. */
268	uint16_t sr; /** rw 1, Status register. */
269	uint16_t picb; /** ro 0, Position in current buffer (in samples). */
270	uint8_t piv; /** ro 0, Prefetched index value. */
271	uint8_t cr; /** rw 0, Control register. */
272	int32_t bd_valid; /** Whether current BDLE is initialized or not. */
273	AC97BDLE bd; /** Current Buffer Descriptor List Entry (BDLE). */
274	} AC97BMREGS;
275	AssertCompileSizeAlignment(AC97BMREGS, 8);
276	/** Pointer to the BM registers of an audio stream. */
277	typedef AC97BMREGS *PAC97BMREGS;
278
279	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
280	/**
281	* Structure keeping the AC'97 stream's state for asynchronous I/O.
282	*/
283	typedef struct AC97STREAMSTATEAIO
284	{
285	/** Thread handle for the actual I/O thread. */
286	RTTHREAD Thread;
287	/** Event for letting the thread know there is some data to process. */
288	RTSEMEVENT Event;
289	/** Critical section for synchronizing access. */
290	RTCRITSECT CritSect;
291	/** Started indicator. */
292	volatile bool fStarted;
293	/** Shutdown indicator. */
294	volatile bool fShutdown;
295	/** Whether the thread should do any data processing or not. */
296	volatile bool fEnabled;
297	uint32_t Padding1;
298	} AC97STREAMSTATEAIO, *PAC97STREAMSTATEAIO;
299	#endif
300
301	/**
302	* Structure for keeping the internal state of an AC'97 stream.
303	*/
304	typedef struct AC97STREAMSTATE
305	{
306	/** Criticial section for this stream. */
307	RTCRITSECT CritSect;
308	/** Circular buffer (FIFO) for holding DMA'ed data. */
309	R3PTRTYPE(PRTCIRCBUF) pCircBuf;
310	#if HC_ARCH_BITS == 32
311	uint32_t Padding;
312	#endif
313	/** The stream's current configuration. */
314	PDMAUDIOSTREAMCFG Cfg; //+104
315	uint32_t Padding2;
316	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
317	/** Asynchronous I/O state members. */
318	AC97STREAMSTATEAIO AIO;
319	#endif
320	/** Timestamp (in ns) of last DMA transfer.
321	* For output streams this is the last DMA read,
322	* for input streams this is the last DMA write. */
323	uint64_t tsLastTransferNs;
324	/** Timestamp (in ns) of last DMA buffer read / write. */
325	uint64_t tsLastReadWriteNs;
326	/** Timestamp (in ns) of last stream update. */
327	uint64_t tsLastUpdateNs;
328	} AC97STREAMSTATE;
329	AssertCompileSizeAlignment(AC97STREAMSTATE, 8);
330	/** Pointer to internal state of an AC'97 stream. */
331	typedef AC97STREAMSTATE *PAC97STREAMSTATE;
332
333	/**
334	* Structure containing AC'97 stream debug stuff, configurable at runtime.
335	*/
336	typedef struct AC97STREAMDBGINFORT
337	{
338	/** Whether debugging is enabled or not. */
339	bool fEnabled;
340	uint8_t Padding[7];
341	/** File for dumping stream reads / writes.
342	* For input streams, this dumps data being written to the device FIFO,
343	* whereas for output streams this dumps data being read from the device FIFO. */
344	R3PTRTYPE(PPDMAUDIOFILE) pFileStream;
345	/** File for dumping DMA reads / writes.
346	* For input streams, this dumps data being written to the device DMA,
347	* whereas for output streams this dumps data being read from the device DMA. */
348	R3PTRTYPE(PPDMAUDIOFILE) pFileDMA;
349	} AC97STREAMDBGINFORT, *PAC97STREAMDBGINFORT;
350
351	/**
352	* Structure containing AC'97 stream debug information.
353	*/
354	typedef struct AC97STREAMDBGINFO
355	{
356	/** Runtime debug info. */
357	AC97STREAMDBGINFORT Runtime;
358	} AC97STREAMDBGINFO ,*PAC97STREAMDBGINFO;
359
360	/**
361	* Structure for an AC'97 stream.
362	*/
363	typedef struct AC97STREAM
364	{
365	/** Stream number (SDn). */
366	uint8_t u8SD;
367	uint8_t abPadding[7];
368	/** Bus master registers of this stream. */
369	AC97BMREGS Regs;
370	/** Internal state of this stream. */
371	AC97STREAMSTATE State;
372	/** Debug information. */
373	AC97STREAMDBGINFO Dbg;
374	} AC97STREAM, *PAC97STREAM;
375	AssertCompileSizeAlignment(AC97STREAM, 8);
376	/** Pointer to an AC'97 stream (registers + state). */
377	typedef AC97STREAM *PAC97STREAM;
378
379	typedef struct AC97STATE *PAC97STATE;
380	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
381	/**
382	* Structure for the async I/O thread context.
383	*/
384	typedef struct AC97STREAMTHREADCTX
385	{
386	PAC97STATE pThis;
387	PAC97STREAM pStream;
388	} AC97STREAMTHREADCTX, *PAC97STREAMTHREADCTX;
389	#endif
390
391	/**
392	* Structure defining a (host backend) driver stream.
393	* Each driver has its own instances of audio mixer streams, which then
394	* can go into the same (or even different) audio mixer sinks.
395	*/
396	typedef struct AC97DRIVERSTREAM
397	{
398	union
399	{
400	/** Desired playback destination (for an output stream). */
401	PDMAUDIOPLAYBACKDEST Dest;
402	/** Desired recording source (for an input stream). */
403	PDMAUDIORECSOURCE Source;
404	} DestSource;
405	uint8_t Padding1[4];
406	/** Associated mixer stream handle. */
407	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
408	} AC97DRIVERSTREAM, *PAC97DRIVERSTREAM;
409
410	/**
411	* Struct for maintaining a host backend driver.
412	*/
413	typedef struct AC97DRIVER
414	{
415	/** Node for storing this driver in our device driver list of AC97STATE. */
416	RTLISTNODER3 Node;
417	/** Pointer to AC97 controller (state). */
418	R3PTRTYPE(PAC97STATE) pAC97State;
419	/** Driver flags. */
420	PDMAUDIODRVFLAGS fFlags;
421	uint32_t PaddingFlags;
422	/** LUN # to which this driver has been assigned. */
423	uint8_t uLUN;
424	/** Whether this driver is in an attached state or not. */
425	bool fAttached;
426	uint8_t Padding[4];
427	/** Pointer to attached driver base interface. */
428	R3PTRTYPE(PPDMIBASE) pDrvBase;
429	/** Audio connector interface to the underlying host backend. */
430	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
431	/** Driver stream for line input. */
432	AC97DRIVERSTREAM LineIn;
433	/** Driver stream for mic input. */
434	AC97DRIVERSTREAM MicIn;
435	/** Driver stream for output. */
436	AC97DRIVERSTREAM Out;
437	} AC97DRIVER, *PAC97DRIVER;
438
439	typedef struct AC97STATEDBGINFO
440	{
441	/** Whether debugging is enabled or not. */
442	bool fEnabled;
443	/** Path where to dump the debug output to.
444	* Defaults to VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH. */
445	char szOutPath[RTPATH_MAX + 1];
446	} AC97STATEDBGINFO, *PAC97STATEDBGINFO;
447
448	/**
449	* Structure for maintaining an AC'97 device state.
450	*/
451	typedef struct AC97STATE
452	{
453	/** The PCI device state. */
454	PDMPCIDEV PciDev;
455	/** Critical section protecting the AC'97 state. */
456	PDMCRITSECT CritSect;
457	/** R3 pointer to the device instance. */
458	PPDMDEVINSR3 pDevInsR3;
459	/** R0 pointer to the device instance. */
460	PPDMDEVINSR0 pDevInsR0;
461	/** RC pointer to the device instance. */
462	PPDMDEVINSRC pDevInsRC;
463	/** Set if R0/RC is enabled. */
464	bool fRZEnabled;
465	bool afPadding0[3];
466	/** Global Control (Bus Master Control Register). */
467	uint32_t glob_cnt;
468	/** Global Status (Bus Master Control Register). */
469	uint32_t glob_sta;
470	/** Codec Access Semaphore Register (Bus Master Control Register). */
471	uint32_t cas;
472	uint32_t last_samp;
473	uint8_t mixer_data[256];
474	/** AC'97 stream for line-in. */
475	AC97STREAM StreamLineIn;
476	/** AC'97 stream for microphone-in. */
477	AC97STREAM StreamMicIn;
478	/** AC'97 stream for output. */
479	AC97STREAM StreamOut;
480	/** Number of active (running) SDn streams. */
481	uint8_t cStreamsActive;
482	#ifndef VBOX_WITH_AUDIO_AC97_CALLBACKS
483	/** Flag indicating whether the timer is active or not. */
484	bool fTimerActive;
485	uint8_t u8Padding1[2];
486	/** The timer for pumping data thru the attached LUN drivers - RCPtr. */
487	PTMTIMERRC pTimerRC;
488	/** The timer for pumping data thru the attached LUN drivers - R3Ptr. */
489	PTMTIMERR3 pTimerR3;
490	/** The timer for pumping data thru the attached LUN drivers - R0Ptr. */
491	PTMTIMERR0 pTimerR0;
492	/** The timer interval for pumping data thru the LUN drivers in timer ticks. */
493	uint64_t cTimerTicks;
494	/** Timestamp of the last timer callback (ac97Timer).
495	* Used to calculate the time actually elapsed between two timer callbacks. */
496	uint64_t uTimerTS;
497	#endif
498	#ifdef VBOX_WITH_STATISTICS
499	STAMPROFILE StatTimer;
500	STAMPROFILE StatIn;
501	STAMPROFILE StatOut;
502	STAMCOUNTER StatBytesRead;
503	STAMCOUNTER StatBytesWritten;
504	#endif
505	/** List of associated LUN drivers (AC97DRIVER). */
506	RTLISTANCHORR3 lstDrv;
507	/** The device's software mixer. */
508	R3PTRTYPE(PAUDIOMIXER) pMixer;
509	/** Audio sink for PCM output. */
510	R3PTRTYPE(PAUDMIXSINK) pSinkOut;
511	/** Audio sink for line input. */
512	R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
513	/** Audio sink for microphone input. */
514	R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
515	uint8_t silence[128];
516	int32_t bup_flag;
517	/** Base port of the I/O space region. */
518	RTIOPORT IOPortBase[2];
519	/** Codec model. */
520	uint32_t uCodecModel;
521	#if HC_ARCH_BITS == 64
522	uint32_t uPadding2;
523	#endif
524	/** The base interface for LUN\#0. */
525	PDMIBASE IBase;
526	AC97STATEDBGINFO Dbg;
527	} AC97STATE;
528	AssertCompileMemberAlignment(AC97STATE, StreamLineIn, 8);
529	/** Pointer to a AC'97 state. */
530	typedef AC97STATE *PAC97STATE;
531
532	/**
533	* Acquires the AC'97 lock.
534	*/
535	#define DEVAC97_LOCK(a_pThis) \
536	do { \
537	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
538	AssertRC(rcLock); \
539	} while (0)
540
541	/**
542	* Acquires the AC'97 lock or returns.
543	*/
544	# define DEVAC97_LOCK_RETURN(a_pThis, a_rcBusy) \
545	do { \
546	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, a_rcBusy); \
547	if (rcLock != VINF_SUCCESS) \
548	{ \
549	AssertRC(rcLock); \
550	return rcLock; \
551	} \
552	} while (0)
553
554	/**
555	* Acquires the AC'97 lock or returns.
556	*/
557	# define DEVAC97_LOCK_RETURN_VOID(a_pThis) \
558	do { \
559	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
560	if (rcLock != VINF_SUCCESS) \
561	{ \
562	AssertRC(rcLock); \
563	return; \
564	} \
565	} while (0)
566
567	/**
568	* Releases the AC'97 lock.
569	*/
570	#define DEVAC97_UNLOCK(a_pThis) \
571	do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
572
573	/**
574	* Acquires the TM lock and AC'97 lock, returns on failure.
575	*/
576	#define DEVAC97_LOCK_BOTH_RETURN_VOID(a_pThis) \
577	do { \
578	int rcLock = TMTimerLock((a_pThis)->CTX_SUFF(pTimer), VERR_IGNORED); \
579	if (rcLock != VINF_SUCCESS) \
580	{ \
581	AssertRC(rcLock); \
582	return; \
583	} \
584	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
585	if (rcLock != VINF_SUCCESS) \
586	{ \
587	AssertRC(rcLock); \
588	TMTimerUnlock((a_pThis)->CTX_SUFF(pTimer)); \
589	return; \
590	} \
591	} while (0)
592
593	/**
594	* Acquires the TM lock and AC'97 lock, returns on failure.
595	*/
596	#define DEVAC97_LOCK_BOTH_RETURN(a_pThis, a_rcBusy) \
597	do { \
598	int rcLock = TMTimerLock((a_pThis)->CTX_SUFF(pTimer), (a_rcBusy)); \
599	if (rcLock != VINF_SUCCESS) \
600	return rcLock; \
601	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
602	if (rcLock != VINF_SUCCESS) \
603	{ \
604	AssertRC(rcLock); \
605	TMTimerUnlock((a_pThis)->CTX_SUFF(pTimer)); \
606	return rcLock; \
607	} \
608	} while (0)
609
610	/**
611	* Releases the AC'97 lock and TM lock.
612	*/
613	#define DEVAC97_UNLOCK_BOTH(a_pThis) \
614	do { \
615	PDMCritSectLeave(&(a_pThis)->CritSect); \
616	TMTimerUnlock((a_pThis)->CTX_SUFF(pTimer)); \
617	} while (0)
618
619	#ifdef VBOX_WITH_STATISTICS
620	AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
621	AssertCompileMemberAlignment(AC97STATE, StatBytesRead, 8);
622	AssertCompileMemberAlignment(AC97STATE, StatBytesWritten, 8);
623	#endif
624
625	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
626
627
628	/*********************************************************************************************************************************
629	* Internal Functions *
630	*********************************************************************************************************************************/
631	#ifdef IN_RING3
632	static int ichac97R3StreamCreate(PAC97STATE pThis, PAC97STREAM pStream, uint8_t u8Strm);
633	static void ichac97R3StreamDestroy(PAC97STATE pThis, PAC97STREAM pStream);
634	static int ichac97R3StreamOpen(PAC97STATE pThis, PAC97STREAM pStream);
635	static int ichac97R3StreamReOpen(PAC97STATE pThis, PAC97STREAM pStream);
636	static int ichac97R3StreamClose(PAC97STATE pThis, PAC97STREAM pStream);
637	static void ichac97R3StreamReset(PAC97STATE pThis, PAC97STREAM pStream);
638	static void ichac97R3StreamLock(PAC97STREAM pStream);
639	static void ichac97R3StreamUnlock(PAC97STREAM pStream);
640	static uint32_t ichac97R3StreamGetUsed(PAC97STREAM pStream);
641	static uint32_t ichac97R3StreamGetFree(PAC97STREAM pStream);
642	static int ichac97R3StreamTransfer(PAC97STATE pThis, PAC97STREAM pStream, uint32_t cbToProcessMax);
643	static void ichac97R3StreamUpdate(PAC97STATE pThis, PAC97STREAM pStream, bool fInTimer);
644
645	static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns);
646	# ifndef VBOX_WITH_AUDIO_AC97_CALLBACKS
647	static int ichac97R3TimerStart(PAC97STATE pThis);
648	static int ichac97R3TimerMaybeStart(PAC97STATE pThis);
649	static int ichac97R3TimerStop(PAC97STATE pThis);
650	static int ichac97R3TimerMaybeStop(PAC97STATE pThis);
651	static void ichac97R3TimerMain(PAC97STATE pThis);
652	static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
653	# endif
654	static void ichac97R3DoTransfers(PAC97STATE pThis);
655
656	static int ichac97R3MixerAddDrvStream(PAC97STATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PAC97DRIVER pDrv);
657	static int ichac97R3MixerAddDrvStreams(PAC97STATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg);
658	static void ichac97R3MixerRemoveDrvStream(PAC97STATE pThis, PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir, PDMAUDIODESTSOURCE dstSrc, PAC97DRIVER pDrv);
659	static void ichac97R3MixerRemoveDrvStreams(PAC97STATE pThis, PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir, PDMAUDIODESTSOURCE dstSrc);
660
661	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
662	static DECLCALLBACK(int) ichac97R3StreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser);
663	static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STREAM pStream);
664	static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAM pStream);
665	static int ichac97R3StreamAsyncIONotify(PAC97STATE pThis, PAC97STREAM pStream);
666	static void ichac97R3StreamAsyncIOLock(PAC97STREAM pStream);
667	static void ichac97R3StreamAsyncIOUnlock(PAC97STREAM pStream);
668	static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable);
669	# endif
670
671	DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD);
672	#endif /* IN_RING3 */
673
674	static void ichac97WarmReset(PAC97STATE pThis)
675	{
676	NOREF(pThis);
677	}
678
679	static void ichac97ColdReset(PAC97STATE pThis)
680	{
681	NOREF(pThis);
682	}
683
684	#ifdef IN_RING3
685
686	/**
687	* Retrieves the audio mixer sink of a corresponding AC'97 stream index.
688	*
689	* @returns Pointer to audio mixer sink if found, or NULL if not found / invalid.
690	* @param pThis AC'97 state.
691	* @param uIndex Stream index to get audio mixer sink for.
692	*/
693	DECLINLINE(PAUDMIXSINK) ichac97R3IndexToSink(PAC97STATE pThis, uint8_t uIndex)
694	{
695	AssertPtrReturn(pThis, NULL);
696
697	switch (uIndex)
698	{
699	case AC97SOUNDSOURCE_PI_INDEX: return pThis->pSinkLineIn;
700	case AC97SOUNDSOURCE_PO_INDEX: return pThis->pSinkOut;
701	case AC97SOUNDSOURCE_MC_INDEX: return pThis->pSinkMicIn;
702	default: break;
703	}
704
705	AssertMsgFailed(("Wrong index %RU8\n", uIndex));
706	return NULL;
707	}
708
709	/**
710	* Fetches the current BDLE (Buffer Descriptor List Entry) of an AC'97 audio stream.
711	*
712	* @returns IPRT status code.
713	* @param pThis AC'97 state.
714	* @param pStream AC'97 stream to fetch BDLE for.
715	*
716	* @remark Uses CIV as BDLE index.
717	*/
718	static void ichac97R3StreamFetchBDLE(PAC97STATE pThis, PAC97STREAM pStream)
719	{
720	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
721	PAC97BMREGS pRegs = &pStream->Regs;
722
723	uint32_t u32[2];
724
725	PDMDevHlpPhysRead(pDevIns, pRegs->bdbar + pRegs->civ * 8, &u32[0], sizeof(u32));
726	pRegs->bd_valid = 1;
727	# ifndef RT_LITTLE_ENDIAN
728	# error "Please adapt the code (audio buffers are little endian)!"
729	# else
730	pRegs->bd.addr = RT_H2LE_U32(u32[0] & ~3);
731	pRegs->bd.ctl_len = RT_H2LE_U32(u32[1]);
732	# endif
733	pRegs->picb = pRegs->bd.ctl_len & AC97_BD_LEN_MASK;
734	LogFlowFunc(("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
735	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len >> 16,
736	pRegs->bd.ctl_len & AC97_BD_LEN_MASK,
737	(pRegs->bd.ctl_len & AC97_BD_LEN_MASK) << 1)); /** @todo r=andy Assumes 16bit samples. */
738	}
739
740	#endif /* IN_RING3 */
741
742	/**
743	* Updates the status register (SR) of an AC'97 audio stream.
744	*
745	* @param pThis AC'97 state.
746	* @param pStream AC'97 stream to update SR for.
747	* @param new_sr New value for status register (SR).
748	*/
749	static void ichac97StreamUpdateSR(PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr)
750	{
751	PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis);
752	PAC97BMREGS pRegs = &pStream->Regs;
753
754	bool fSignal = false;
755	int iIRQL = 0;
756
757	uint32_t new_mask = new_sr & AC97_SR_INT_MASK;
758	uint32_t old_mask = pRegs->sr & AC97_SR_INT_MASK;
759
760	if (new_mask ^ old_mask)
761	{
762	/** @todo Is IRQ deasserted when only one of status bits is cleared? */
763	if (!new_mask)
764	{
765	fSignal = true;
766	iIRQL = 0;
767	}
768	else if ((new_mask & AC97_SR_LVBCI) && (pRegs->cr & AC97_CR_LVBIE))
769	{
770	fSignal = true;
771	iIRQL = 1;
772	}
773	else if ((new_mask & AC97_SR_BCIS) && (pRegs->cr & AC97_CR_IOCE))
774	{
775	fSignal = true;
776	iIRQL = 1;
777	}
778	}
779
780	pRegs->sr = new_sr;
781
782	LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n",
783	pRegs->sr & AC97_SR_BCIS, pRegs->sr & AC97_SR_LVBCI, pRegs->sr, fSignal, iIRQL));
784
785	if (fSignal)
786	{
787	static uint32_t const s_aMasks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT };
788	if (iIRQL)
789	pThis->glob_sta \|= s_aMasks[pStream->u8SD];
790	else
791	pThis->glob_sta &= ~s_aMasks[pStream->u8SD];
792
793	LogFlowFunc(("Setting IRQ level=%d\n", iIRQL));
794	PDMDevHlpPCISetIrq(pDevIns, 0, iIRQL);
795	}
796	}
797
798	#ifdef IN_RING3
799
800	/**
801	* Returns whether an AC'97 stream is enabled or not.
802	*
803	* @returns IPRT status code.
804	* @param pThis AC'97 device state.
805	* @param pStream Stream to return status for.
806	*/
807	static bool ichac97R3StreamIsEnabled(PAC97STATE pThis, PAC97STREAM pStream)
808	{
809	AssertPtrReturn(pThis, false);
810	AssertPtrReturn(pStream, false);
811
812	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThis, pStream->u8SD);
813	bool fIsEnabled = RT_BOOL(AudioMixerSinkGetStatus(pSink) & AUDMIXSINK_STS_RUNNING);
814
815	LogFunc(("[SD%RU8] fIsEnabled=%RTbool\n", pStream->u8SD, fIsEnabled));
816	return fIsEnabled;
817	}
818
819	/**
820	* Enables or disables an AC'97 audio stream.
821	*
822	* @returns IPRT status code.
823	* @param pThis AC'97 state.
824	* @param pStream AC'97 stream to enable or disable.
825	* @param fEnable Whether to enable or disable the stream.
826	*
827	*/
828	static int ichac97R3StreamEnable(PAC97STATE pThis, PAC97STREAM pStream, bool fEnable)
829	{
830	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
831	AssertPtrReturn(pStream, VERR_INVALID_POINTER);
832
833	ichac97R3StreamLock(pStream);
834
835	int rc = VINF_SUCCESS;
836
837	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
838	if (fEnable)
839	rc = ichac97R3StreamAsyncIOCreate(pThis, pStream);
840	if (RT_SUCCESS(rc))
841	ichac97R3StreamAsyncIOLock(pStream);
842	# endif
843
844	if (fEnable)
845	{
846	if (pStream->State.pCircBuf)
847	RTCircBufReset(pStream->State.pCircBuf);
848
849	rc = ichac97R3StreamOpen(pThis, pStream);
850
851	if (pStream->Dbg.Runtime.fEnabled)
852	{
853	if (!DrvAudioHlpFileIsOpen(pStream->Dbg.Runtime.pFileStream))
854	{
855	int rc2 = DrvAudioHlpFileOpen(pStream->Dbg.Runtime.pFileStream, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
856	&pStream->State.Cfg.Props);
857	AssertRC(rc2);
858	}
859
860	if (!DrvAudioHlpFileIsOpen(pStream->Dbg.Runtime.pFileDMA))
861	{
862	int rc2 = DrvAudioHlpFileOpen(pStream->Dbg.Runtime.pFileDMA, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
863	&pStream->State.Cfg.Props);
864	AssertRC(rc2);
865	}
866	}
867	}
868	else
869	rc = ichac97R3StreamClose(pThis, pStream);
870
871	if (RT_SUCCESS(rc))
872	{
873	/* First, enable or disable the stream and the stream's sink, if any. */
874	rc = AudioMixerSinkCtl(ichac97R3IndexToSink(pThis, pStream->u8SD),
875	fEnable ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE);
876	}
877
878	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
879	ichac97R3StreamAsyncIOUnlock(pStream);
880	# endif
881
882	/* Make sure to leave the lock before (eventually) starting the timer. */
883	ichac97R3StreamUnlock(pStream);
884
885	# ifndef VBOX_WITH_AUDIO_AC97_CALLBACKS
886	/* Second, see if we need to start or stop the timer. */
887	if (!fEnable)
888	ichac97R3TimerMaybeStop(pThis);
889	else
890	ichac97R3TimerMaybeStart(pThis);
891	# endif
892
893	LogFunc(("[SD%RU8] cStreamsActive=%RU8, fEnable=%RTbool, rc=%Rrc\n", pStream->u8SD, pThis->cStreamsActive, fEnable, rc));
894	return rc;
895	}
896
897	/**
898	* Resets an AC'97 stream.
899	*
900	* @param pThis AC'97 state.
901	* @param pStream AC'97 stream to reset.
902	*
903	*/
904	static void ichac97R3StreamReset(PAC97STATE pThis, PAC97STREAM pStream)
905	{
906	AssertPtrReturnVoid(pThis);
907	AssertPtrReturnVoid(pStream);
908
909	ichac97R3StreamLock(pStream);
910
911	LogFunc(("[SD%RU8]\n", pStream->u8SD));
912
913	if (pStream->State.pCircBuf)
914	RTCircBufReset(pStream->State.pCircBuf);
915
916	PAC97BMREGS pRegs = &pStream->Regs;
917
918	pRegs->bdbar = 0;
919	pRegs->civ = 0;
920	pRegs->lvi = 0;
921
922	pRegs->picb = 0;
923	pRegs->piv = 0;
924	pRegs->cr = pRegs->cr & AC97_CR_DONT_CLEAR_MASK;
925	pRegs->bd_valid = 0;
926
927	RT_ZERO(pThis->silence);
928
929	ichac97R3StreamUnlock(pStream);
930	}
931
932	/**
933	* Creates an AC'97 audio stream.
934	*
935	* @returns IPRT status code.
936	* @param pThis AC'97 state.
937	* @param pStream AC'97 stream to create.
938	* @param u8Strm Stream ID to assign AC'97 stream to.
939	*/
940	static int ichac97R3StreamCreate(PAC97STATE pThis, PAC97STREAM pStream, uint8_t u8Strm)
941	{
942	RT_NOREF(pThis);
943	AssertPtrReturn(pStream, VERR_INVALID_PARAMETER);
944	/** @todo Validate u8Strm. */
945
946	LogFunc(("[SD%RU8] pStream=%p\n", u8Strm, pStream));
947
948	Assert(u8Strm < 3);
949	pStream->u8SD = u8Strm;
950
951	int rc = RTCritSectInit(&pStream->State.CritSect);
952
953	pStream->Dbg.Runtime.fEnabled = pThis->Dbg.fEnabled;
954
955	if (pStream->Dbg.Runtime.fEnabled)
956	{
957	char szFile[64];
958
959	if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
960	RTStrPrintf(szFile, sizeof(szFile), "ac97StreamWriteSD%RU8", pStream->u8SD);
961	else
962	RTStrPrintf(szFile, sizeof(szFile), "ac97StreamReadSD%RU8", pStream->u8SD);
963
964	char szPath[RTPATH_MAX + 1];
965	int rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThis->Dbg.szOutPath, szFile,
966	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAG_NONE);
967	AssertRC(rc2);
968	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAG_NONE, &pStream->Dbg.Runtime.pFileStream);
969	AssertRC(rc2);
970
971	if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
972	RTStrPrintf(szFile, sizeof(szFile), "ac97DMAWriteSD%RU8", pStream->u8SD);
973	else
974	RTStrPrintf(szFile, sizeof(szFile), "ac97DMAReadSD%RU8", pStream->u8SD);
975
976	rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThis->Dbg.szOutPath, szFile,
977	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAG_NONE);
978	AssertRC(rc2);
979
980	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAG_NONE, &pStream->Dbg.Runtime.pFileDMA);
981	AssertRC(rc2);
982
983	/* Delete stale debugging files from a former run. */
984	DrvAudioHlpFileDelete(pStream->Dbg.Runtime.pFileStream);
985	DrvAudioHlpFileDelete(pStream->Dbg.Runtime.pFileDMA);
986	}
987
988	return rc;
989	}
990
991	/**
992	* Destroys an AC'97 audio stream.
993	*
994	* @returns IPRT status code.
995	* @param pThis AC'97 state.
996	* @param pStream AC'97 stream to destroy.
997	*/
998	static void ichac97R3StreamDestroy(PAC97STATE pThis, PAC97STREAM pStream)
999	{
1000	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
1001
1002	ichac97R3StreamClose(pThis, pStream);
1003
1004	int rc2 = RTCritSectDelete(&pStream->State.CritSect);
1005	AssertRC(rc2);
1006
1007	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1008	rc2 = ichac97R3StreamAsyncIODestroy(pThis, pStream);
1009	AssertRC(rc2);
1010	# else
1011	RT_NOREF(pThis);
1012	# endif
1013
1014	if (pStream->Dbg.Runtime.fEnabled)
1015	{
1016	DrvAudioHlpFileDestroy(pStream->Dbg.Runtime.pFileStream);
1017	pStream->Dbg.Runtime.pFileStream = NULL;
1018
1019	DrvAudioHlpFileDestroy(pStream->Dbg.Runtime.pFileDMA);
1020	pStream->Dbg.Runtime.pFileDMA = NULL;
1021	}
1022
1023	if (pStream->State.pCircBuf)
1024	{
1025	RTCircBufDestroy(pStream->State.pCircBuf);
1026	pStream->State.pCircBuf = NULL;
1027	}
1028
1029	LogFlowFuncLeave();
1030	}
1031
1032	/**
1033	* Destroys all AC'97 audio streams of the device.
1034	*
1035	* @param pThis AC'97 state.
1036	*/
1037	static void ichac97R3StreamsDestroy(PAC97STATE pThis)
1038	{
1039	LogFlowFuncEnter();
1040
1041	/*
1042	* Destroy all AC'97 streams.
1043	*/
1044
1045	ichac97R3StreamDestroy(pThis, &pThis->StreamLineIn);
1046	ichac97R3StreamDestroy(pThis, &pThis->StreamMicIn);
1047	ichac97R3StreamDestroy(pThis, &pThis->StreamOut);
1048
1049	/*
1050	* Destroy all sinks.
1051	*/
1052
1053	PDMAUDIODESTSOURCE dstSrc;
1054	if (pThis->pSinkLineIn)
1055	{
1056	dstSrc.Source = PDMAUDIORECSOURCE_LINE;
1057	ichac97R3MixerRemoveDrvStreams(pThis, pThis->pSinkLineIn, PDMAUDIODIR_IN, dstSrc);
1058
1059	AudioMixerSinkDestroy(pThis->pSinkLineIn);
1060	pThis->pSinkLineIn = NULL;
1061	}
1062
1063	if (pThis->pSinkMicIn)
1064	{
1065	dstSrc.Source = PDMAUDIORECSOURCE_MIC;
1066	ichac97R3MixerRemoveDrvStreams(pThis, pThis->pSinkMicIn, PDMAUDIODIR_IN, dstSrc);
1067
1068	AudioMixerSinkDestroy(pThis->pSinkMicIn);
1069	pThis->pSinkMicIn = NULL;
1070	}
1071
1072	if (pThis->pSinkOut)
1073	{
1074	dstSrc.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
1075	ichac97R3MixerRemoveDrvStreams(pThis, pThis->pSinkOut, PDMAUDIODIR_OUT, dstSrc);
1076
1077	AudioMixerSinkDestroy(pThis->pSinkOut);
1078	pThis->pSinkOut = NULL;
1079	}
1080	}
1081
1082	/**
1083	* Writes audio data from a mixer sink into an AC'97 stream's DMA buffer.
1084	*
1085	* @returns IPRT status code.
1086	* @param pThis AC'97 state.
1087	* @param pDstStream AC'97 stream to write to.
1088	* @param pSrcMixSink Mixer sink to get audio data to write from.
1089	* @param cbToWrite Number of bytes to write.
1090	* @param pcbWritten Number of bytes written. Optional.
1091	*/
1092	static int ichac97R3StreamWrite(PAC97STATE pThis, PAC97STREAM pDstStream, PAUDMIXSINK pSrcMixSink, uint32_t cbToWrite,
1093	uint32_t *pcbWritten)
1094	{
1095	RT_NOREF(pThis);
1096	AssertPtrReturn(pDstStream, VERR_INVALID_POINTER);
1097	AssertPtrReturn(pSrcMixSink, VERR_INVALID_POINTER);
1098	AssertReturn(cbToWrite, VERR_INVALID_PARAMETER);
1099	/* pcbWritten is optional. */
1100
1101	PRTCIRCBUF pCircBuf = pDstStream->State.pCircBuf;
1102	AssertPtr(pCircBuf);
1103
1104	void *pvDst;
1105	size_t cbDst;
1106
1107	uint32_t cbRead = 0;
1108
1109	RTCircBufAcquireWriteBlock(pCircBuf, cbToWrite, &pvDst, &cbDst);
1110
1111	if (cbDst)
1112	{
1113	int rc2 = AudioMixerSinkRead(pSrcMixSink, AUDMIXOP_COPY, pvDst, (uint32_t)cbDst, &cbRead);
1114	AssertRC(rc2);
1115
1116	if (pDstStream->Dbg.Runtime.fEnabled)
1117	DrvAudioHlpFileWrite(pDstStream->Dbg.Runtime.pFileStream, pvDst, cbRead, 0 /* fFlags */);
1118	}
1119
1120	RTCircBufReleaseWriteBlock(pCircBuf, cbRead);
1121
1122	pDstStream->State.tsLastReadWriteNs = RTTimeNanoTS();
1123
1124	if (pcbWritten)
1125	*pcbWritten = cbRead;
1126
1127	return VINF_SUCCESS;
1128	}
1129
1130	/**
1131	* Reads audio data from an AC'97 stream's DMA buffer and writes into a specified mixer sink.
1132	*
1133	* @returns IPRT status code.
1134	* @param pThis AC'97 state.
1135	* @param pSrcStream AC'97 stream to read audio data from.
1136	* @param pDstMixSink Mixer sink to write audio data to.
1137	* @param cbToRead Number of bytes to read.
1138	* @param pcbRead Number of bytes read. Optional.
1139	*/
1140	static int ichac97R3StreamRead(PAC97STATE pThis, PAC97STREAM pSrcStream, PAUDMIXSINK pDstMixSink, uint32_t cbToRead,
1141	uint32_t *pcbRead)
1142	{
1143	RT_NOREF(pThis);
1144	AssertPtrReturn(pSrcStream, VERR_INVALID_POINTER);
1145	AssertPtrReturn(pDstMixSink, VERR_INVALID_POINTER);
1146	AssertReturn(cbToRead, VERR_INVALID_PARAMETER);
1147	/* pcbRead is optional. */
1148
1149	int rc = VINF_SUCCESS;
1150
1151	uint32_t cbReadTotal = 0;
1152
1153	PRTCIRCBUF pCircBuf = pSrcStream->State.pCircBuf;
1154	AssertPtr(pCircBuf);
1155
1156	void *pvSrc;
1157	size_t cbSrc;
1158
1159	while (cbToRead)
1160	{
1161	uint32_t cbWritten = 0;
1162
1163	RTCircBufAcquireReadBlock(pCircBuf, cbToRead, &pvSrc, &cbSrc);
1164
1165	if (cbSrc)
1166	{
1167	if (pSrcStream->Dbg.Runtime.fEnabled)
1168	DrvAudioHlpFileWrite(pSrcStream->Dbg.Runtime.pFileStream, pvSrc, cbSrc, 0 /* fFlags */);
1169
1170	rc = AudioMixerSinkWrite(pDstMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbWritten);
1171	if (RT_SUCCESS(rc))
1172	{
1173	Assert(cbWritten <= cbSrc);
1174
1175	cbReadTotal += cbWritten;
1176
1177	Assert(cbToRead >= cbWritten);
1178	cbToRead -= cbWritten;
1179	}
1180	}
1181
1182	RTCircBufReleaseReadBlock(pCircBuf, cbWritten);
1183
1184	if ( !cbWritten
1185	\|\| !RTCircBufUsed(pCircBuf))
1186	break;
1187
1188	if (RT_FAILURE(rc))
1189	break;
1190	}
1191
1192	pSrcStream->State.tsLastReadWriteNs = RTTimeNanoTS();
1193
1194	if (pcbRead)
1195	*pcbRead = cbReadTotal;
1196
1197	return rc;
1198	}
1199
1200	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1201
1202	/**
1203	* Asynchronous I/O thread for an AC'97 stream.
1204	* This will do the heavy lifting work for us as soon as it's getting notified by another thread.
1205	*
1206	* @returns IPRT status code.
1207	* @param hThreadSelf Thread handle.
1208	* @param pvUser User argument. Must be of type PAC97STREAMTHREADCTX.
1209	*/
1210	static DECLCALLBACK(int) ichac97R3StreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
1211	{
1212	PAC97STREAMTHREADCTX pCtx = (PAC97STREAMTHREADCTX)pvUser;
1213	AssertPtr(pCtx);
1214
1215	PAC97STATE pThis = pCtx->pThis;
1216	AssertPtr(pThis);
1217
1218	PAC97STREAM pStream = pCtx->pStream;
1219	AssertPtr(pStream);
1220
1221	PAC97STREAMSTATEAIO pAIO = &pCtx->pStream->State.AIO;
1222
1223	PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
1224	AssertPtr(pCircBuf);
1225
1226	PAUDMIXSINK pMixSink = ichac97R3IndexToSink(pThis, pStream->u8SD);
1227	AssertPtr(pMixSink);
1228
1229	ASMAtomicXchgBool(&pAIO->fStarted, true);
1230
1231	RTThreadUserSignal(hThreadSelf);
1232
1233	LogFunc(("[SD%RU8] Started\n", pStream->u8SD));
1234
1235	for (;;)
1236	{
1237	Log2Func(("[SD%RU8] Waiting ...\n", pStream->u8SD));
1238
1239	int rc2 = RTSemEventWait(pAIO->Event, RT_INDEFINITE_WAIT);
1240	if (RT_FAILURE(rc2))
1241	break;
1242
1243	if (ASMAtomicReadBool(&pAIO->fShutdown))
1244	break;
1245
1246	rc2 = RTCritSectEnter(&pAIO->CritSect);
1247	if (RT_SUCCESS(rc2))
1248	{
1249	if (!pAIO->fEnabled)
1250	{
1251	RTCritSectLeave(&pAIO->CritSect);
1252	continue;
1253	}
1254
1255	ichac97R3StreamUpdate(pThis, pStream, false /* fInTimer */);
1256
1257	int rc3 = RTCritSectLeave(&pAIO->CritSect);
1258	AssertRC(rc3);
1259	}
1260
1261	AssertRC(rc2);
1262	}
1263
1264	LogFunc(("[SD%RU8] Ended\n", pStream->u8SD));
1265
1266	ASMAtomicXchgBool(&pAIO->fStarted, false);
1267
1268	return VINF_SUCCESS;
1269	}
1270
1271	/**
1272	* Creates the async I/O thread for a specific AC'97 audio stream.
1273	*
1274	* @returns IPRT status code.
1275	* @param pThis AC'97 state.
1276	* @param pStream AC'97 audio stream to create the async I/O thread for.
1277	*/
1278	static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STREAM pStream)
1279	{
1280	PAC97STREAMSTATEAIO pAIO = &pStream->State.AIO;
1281
1282	int rc;
1283
1284	if (!ASMAtomicReadBool(&pAIO->fStarted))
1285	{
1286	pAIO->fShutdown = false;
1287	pAIO->fEnabled = true; /* Enabled by default. */
1288
1289	rc = RTSemEventCreate(&pAIO->Event);
1290	if (RT_SUCCESS(rc))
1291	{
1292	rc = RTCritSectInit(&pAIO->CritSect);
1293	if (RT_SUCCESS(rc))
1294	{
1295	AC97STREAMTHREADCTX Ctx = { pThis, pStream };
1296
1297	char szThreadName[64];
1298	RTStrPrintf2(szThreadName, sizeof(szThreadName), "ac97AIO%RU8", pStream->u8SD);
1299
1300	rc = RTThreadCreate(&pAIO->Thread, ichac97StreamAsyncIOThread, &Ctx,
1301	0, RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, szThreadName);
1302	if (RT_SUCCESS(rc))
1303	rc = RTThreadUserWait(pAIO->Thread, 10 * 1000 /* 10s timeout */);
1304	}
1305	}
1306	}
1307	else
1308	rc = VINF_SUCCESS;
1309
1310	LogFunc(("[SD%RU8] Returning %Rrc\n", pStream->u8SD, rc));
1311	return rc;
1312	}
1313
1314	/**
1315	* Destroys the async I/O thread of a specific AC'97 audio stream.
1316	*
1317	* @returns IPRT status code.
1318	* @param pThis AC'97 state.
1319	* @param pStream AC'97 audio stream to destroy the async I/O thread for.
1320	*/
1321	static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAM pStream)
1322	{
1323	PAC97STREAMSTATEAIO pAIO = &pStream->State.AIO;
1324
1325	if (!ASMAtomicReadBool(&pAIO->fStarted))
1326	return VINF_SUCCESS;
1327
1328	ASMAtomicWriteBool(&pAIO->fShutdown, true);
1329
1330	int rc = ichac97R3StreamAsyncIONotify(pThis, pStream);
1331	AssertRC(rc);
1332
1333	int rcThread;
1334	rc = RTThreadWait(pAIO->Thread, 30 * 1000 /* 30s timeout */, &rcThread);
1335	LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
1336
1337	if (RT_SUCCESS(rc))
1338	{
1339	rc = RTCritSectDelete(&pAIO->CritSect);
1340	AssertRC(rc);
1341
1342	rc = RTSemEventDestroy(pAIO->Event);
1343	AssertRC(rc);
1344
1345	pAIO->fStarted = false;
1346	pAIO->fShutdown = false;
1347	pAIO->fEnabled = false;
1348	}
1349
1350	LogFunc(("[SD%RU8] Returning %Rrc\n", pStream->u8SD, rc));
1351	return rc;
1352	}
1353
1354	/**
1355	* Lets the stream's async I/O thread know that there is some data to process.
1356	*
1357	* @returns IPRT status code.
1358	* @param pThis AC'97 state.
1359	* @param pStream AC'97 stream to notify async I/O thread for.
1360	*/
1361	static int ichac97R3StreamAsyncIONotify(PAC97STATE pThis, PAC97STREAM pStream)
1362	{
1363	RT_NOREF(pThis);
1364
1365	LogFunc(("[SD%RU8]\n", pStream->u8SD));
1366	return RTSemEventSignal(pStream->State.AIO.Event);
1367	}
1368
1369	/**
1370	* Locks the async I/O thread of a specific AC'97 audio stream.
1371	*
1372	* @param pStream AC'97 stream to lock async I/O thread for.
1373	*/
1374	static void ichac97R3StreamAsyncIOLock(PAC97STREAM pStream)
1375	{
1376	PAC97STREAMSTATEAIO pAIO = &pStream->State.AIO;
1377
1378	if (!ASMAtomicReadBool(&pAIO->fStarted))
1379	return;
1380
1381	int rc2 = RTCritSectEnter(&pAIO->CritSect);
1382	AssertRC(rc2);
1383	}
1384
1385	/**
1386	* Unlocks the async I/O thread of a specific AC'97 audio stream.
1387	*
1388	* @param pStream AC'97 stream to unlock async I/O thread for.
1389	*/
1390	static void ichac97R3StreamAsyncIOUnlock(PAC97STREAM pStream)
1391	{
1392	PAC97STREAMSTATEAIO pAIO = &pStream->State.AIO;
1393
1394	if (!ASMAtomicReadBool(&pAIO->fStarted))
1395	return;
1396
1397	int rc2 = RTCritSectLeave(&pAIO->CritSect);
1398	AssertRC(rc2);
1399	}
1400
1401	/**
1402	* Enables (resumes) or disables (pauses) the async I/O thread.
1403	*
1404	* @param pStream AC'97 stream to enable/disable async I/O thread for.
1405	* @param fEnable Whether to enable or disable the I/O thread.
1406	*
1407	* @remarks Does not do locking.
1408	*/
1409	static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable)
1410	{
1411	PAC97STREAMSTATEAIO pAIO = &pStream->State.AIO;
1412	ASMAtomicXchgBool(&pAIO->fEnabled, fEnable);
1413	}
1414
1415	# endif /* VBOX_WITH_AUDIO_AC97_ASYNC_IO */
1416
1417	/**
1418	* Updates an AC'97 stream by doing its required data transfers.
1419	* The host sink(s) set the overall pace.
1420	*
1421	* This routine is called by both, the synchronous and the asynchronous
1422	* (VBOX_WITH_AUDIO_AC97_ASYNC_IO), implementations.
1423	*
1424	* When running synchronously, the device DMA transfers and the mixer sink
1425	* processing is within the device timer.
1426	*
1427	* When running asynchronously, only the device DMA transfers are done in the
1428	* device timer, whereas the mixer sink processing then is done in the stream's
1429	* own async I/O thread. This thread also will call this function
1430	* (with fInTimer set to @c false).
1431	*
1432	* @param pThis AC'97 state.
1433	* @param pStream AC'97 stream to update.
1434	* @param fInTimer Whether to this function was called from the timer
1435	* context or an asynchronous I/O stream thread (if supported).
1436	*/
1437	static void ichac97R3StreamUpdate(PAC97STATE pThis, PAC97STREAM pStream, bool fInTimer)
1438	{
1439	RT_NOREF(fInTimer);
1440
1441	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThis, pStream->u8SD);
1442	AssertPtr(pSink);
1443
1444	if (!AudioMixerSinkIsActive(pSink)) /* No sink available? Bail out. */
1445	return;
1446
1447	int rc2;
1448
1449	if (pStream->u8SD == AC97SOUNDSOURCE_PO_INDEX) /* Output (SDO). */
1450	{
1451	/* How much (guest output) data is available at the moment for the AC'97 stream? */
1452	/* Only read from the AC'97 stream at the given scheduling rate. */
1453	bool fDoRead = false; /* Whether to read from the AC'97 stream or not. */
1454
1455	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1456	if (fInTimer)
1457	# endif
1458	{
1459	const uint32_t cbStreamFree = ichac97R3StreamGetFree(pStream);
1460	if (cbStreamFree)
1461	{
1462	/* Do the DMA transfer. */
1463	rc2 = ichac97R3StreamTransfer(pThis, pStream, cbStreamFree);
1464	AssertRC(rc2);
1465	}
1466
1467	/* Only read from the AC'97 stream at the given scheduling rate. */
1468	const uint64_t tsNowNs = RTTimeNanoTS();
1469	if (tsNowNs - pStream->State.tsLastUpdateNs >= pStream->State.Cfg.Device.uSchedulingHintMs * RT_NS_1MS)
1470	{
1471	fDoRead = true;
1472	pStream->State.tsLastUpdateNs = tsNowNs;
1473	}
1474	}
1475
1476	Log3Func(("[SD%RU8] fInTimer=%RTbool, fDoRead=%RTbool\n", pStream->u8SD, fInTimer, fDoRead));
1477
1478	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1479	if (fDoRead)
1480	{
1481	rc2 = ichac97R3StreamAsyncIONotify(pStream);
1482	AssertRC(rc2);
1483	}
1484	# endif
1485
1486	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1487	if (!fInTimer) /* In async I/O thread */
1488	{
1489	# else
1490	if (fDoRead)
1491	{
1492	# endif
1493	const uint32_t cbSinkWritable = AudioMixerSinkGetWritable(pSink);
1494	const uint32_t cbStreamReadable = ichac97R3StreamGetUsed(pStream);
1495	const uint32_t cbToReadFromStream = RT_MIN(cbStreamReadable, cbSinkWritable);
1496
1497	Log3Func(("[SD%RU8] cbSinkWritable=%RU32, cbStreamReadable=%RU32\n", pStream->u8SD, cbSinkWritable, cbStreamReadable));
1498
1499	if (cbToReadFromStream)
1500	{
1501	/* Read (guest output) data and write it to the stream's sink. */
1502	rc2 = ichac97R3StreamRead(pThis, pStream, pSink, cbToReadFromStream, NULL);
1503	AssertRC(rc2);
1504	}
1505	}
1506
1507	/* When running synchronously, update the associated sink here.
1508	* Otherwise this will be done in the async I/O thread. */
1509	rc2 = AudioMixerSinkUpdate(pSink);
1510	AssertRC(rc2);
1511	}
1512	else /* Input (SDI). */
1513	{
1514	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1515	if (fInTimer)
1516	{
1517	rc2 = ichac97R3StreamAsyncIONotify(pThis, pStream);
1518	AssertRC(rc2);
1519	}
1520	else
1521	# endif
1522	{
1523	rc2 = AudioMixerSinkUpdate(pSink);
1524	AssertRC(rc2);
1525
1526	/* Is the sink ready to be read (host input data) from? If so, by how much? */
1527	const uint32_t cbReadable = AudioMixerSinkGetReadable(pSink);
1528
1529	/* How much (guest input) data is free at the moment? */
1530	uint32_t cbToTransfer = ichac97R3StreamGetFree(pStream);
1531
1532	Log3Func(("[SD%RU8] cbReadable=%RU32, cbFree=%RU32\n", pStream->u8SD, cbReadable, cbToTransfer));
1533
1534	/* Do not read more than the sink can provide at the moment.
1535	* The host sets the overall pace. */
1536	if (cbToTransfer > cbReadable)
1537	cbToTransfer = cbReadable;
1538
1539	if (cbToTransfer)
1540	{
1541	/* Write (guest input) data to the stream which was read from stream's sink before. */
1542	rc2 = ichac97R3StreamWrite(pThis, pStream, pSink, cbToTransfer, NULL /* pcbWritten */);
1543	AssertRC(rc2);
1544	}
1545	}
1546
1547	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1548	if (fInTimer)
1549	# endif
1550	{
1551	const uint32_t cbToTransfer = ichac97R3StreamGetUsed(pStream);
1552	if (cbToTransfer)
1553	{
1554	/* When running synchronously, do the DMA data transfers here.
1555	* Otherwise this will be done in the stream's async I/O thread. */
1556	rc2 = ichac97R3StreamTransfer(pThis, pStream, cbToTransfer);
1557	AssertRC(rc2);
1558	}
1559	}
1560	}
1561	}
1562
1563	#endif /* IN_RING3 */
1564
1565	/**
1566	* Sets a AC'97 mixer control to a specific value.
1567	*
1568	* @returns IPRT status code.
1569	* @param pThis AC'97 state.
1570	* @param uMixerIdx Mixer control to set value for.
1571	* @param uVal Value to set.
1572	*/
1573	static void ichac97MixerSet(PAC97STATE pThis, uint8_t uMixerIdx, uint16_t uVal)
1574	{
1575	AssertMsgReturnVoid(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1576	("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)));
1577	pThis->mixer_data[uMixerIdx + 0] = RT_LO_U8(uVal);
1578	pThis->mixer_data[uMixerIdx + 1] = RT_HI_U8(uVal);
1579	}
1580
1581	/**
1582	* Gets a value from a specific AC'97 mixer control.
1583	*
1584	* @returns Retrieved mixer control value.
1585	* @param pThis AC'97 state.
1586	* @param uMixerIdx Mixer control to get value for.
1587	*/
1588	static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t uMixerIdx)
1589	{
1590	AssertMsgReturn(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1591	("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)),
1592	UINT16_MAX);
1593	return RT_MAKE_U16(pThis->mixer_data[uMixerIdx + 0], pThis->mixer_data[uMixerIdx + 1]);
1594	}
1595
1596	#ifdef IN_RING3
1597
1598	/**
1599	* Retrieves a specific driver stream of a AC'97 driver.
1600	*
1601	* @returns Pointer to driver stream if found, or NULL if not found.
1602	* @param pThis AC'97 state.
1603	* @param pDrv Driver to retrieve driver stream for.
1604	* @param enmDir Stream direction to retrieve.
1605	* @param dstSrc Stream destination / source to retrieve.
1606	*/
1607	static PAC97DRIVERSTREAM ichac97R3MixerGetDrvStream(PAC97STATE pThis, PAC97DRIVER pDrv,
1608	PDMAUDIODIR enmDir, PDMAUDIODESTSOURCE dstSrc)
1609	{
1610	RT_NOREF(pThis);
1611
1612	PAC97DRIVERSTREAM pDrvStream = NULL;
1613
1614	if (enmDir == PDMAUDIODIR_IN)
1615	{
1616	LogFunc(("enmRecSource=%d\n", dstSrc.Source));
1617
1618	switch (dstSrc.Source)
1619	{
1620	case PDMAUDIORECSOURCE_LINE:
1621	pDrvStream = &pDrv->LineIn;
1622	break;
1623	case PDMAUDIORECSOURCE_MIC:
1624	pDrvStream = &pDrv->MicIn;
1625	break;
1626	default:
1627	AssertFailed();
1628	break;
1629	}
1630	}
1631	else if (enmDir == PDMAUDIODIR_OUT)
1632	{
1633	LogFunc(("enmPlaybackDest=%d\n", dstSrc.Dest));
1634
1635	switch (dstSrc.Dest)
1636	{
1637	case PDMAUDIOPLAYBACKDEST_FRONT:
1638	pDrvStream = &pDrv->Out;
1639	break;
1640	default:
1641	AssertFailed();
1642	break;
1643	}
1644	}
1645	else
1646	AssertFailed();
1647
1648	return pDrvStream;
1649	}
1650
1651	/**
1652	* Adds a driver stream to a specific mixer sink.
1653	*
1654	* @returns IPRT status code.
1655	* @param pThis AC'97 state.
1656	* @param pMixSink Mixer sink to add driver stream to.
1657	* @param pCfg Stream configuration to use.
1658	* @param pDrv Driver stream to add.
1659	*/
1660	static int ichac97R3MixerAddDrvStream(PAC97STATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PAC97DRIVER pDrv)
1661	{
1662	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1663	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1664	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1665
1666	PPDMAUDIOSTREAMCFG pStreamCfg = DrvAudioHlpStreamCfgDup(pCfg);
1667	if (!pStreamCfg)
1668	return VERR_NO_MEMORY;
1669
1670	if (!RTStrPrintf(pStreamCfg->szName, sizeof(pStreamCfg->szName), "%s", pCfg->szName))
1671	{
1672	RTMemFree(pStreamCfg);
1673	return VERR_BUFFER_OVERFLOW;
1674	}
1675
1676	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
1677
1678	int rc;
1679
1680	PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pThis, pDrv, pStreamCfg->enmDir, pStreamCfg->DestSource);
1681	if (pDrvStream)
1682	{
1683	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
1684
1685	PAUDMIXSTREAM pMixStrm;
1686	rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
1687	LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1688	if (RT_SUCCESS(rc))
1689	{
1690	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
1691	LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1692	if (RT_SUCCESS(rc))
1693	{
1694	/* If this is an input stream, always set the latest (added) stream
1695	* as the recording source.
1696	* @todo Make the recording source dynamic (CFGM?). */
1697	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
1698	{
1699	PDMAUDIOBACKENDCFG Cfg;
1700	rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
1701	if ( RT_SUCCESS(rc)
1702	&& Cfg.cMaxStreamsIn) /* At least one input source available? */
1703	{
1704	rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
1705	LogFlowFunc(("LUN#%RU8: Recording source is now '%s', rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1706	LogRel2(("AC97: Set recording source to '%s'\n", pStreamCfg->szName));
1707	}
1708	else if (RT_FAILURE(rc))
1709	LogFunc(("LUN#%RU8: Unable to retrieve backend configuratio for '%s', rc=%Rrc\n",
1710	pDrv->uLUN, pStreamCfg->szName, rc));
1711	}
1712	}
1713	}
1714
1715	if (RT_SUCCESS(rc))
1716	pDrvStream->pMixStrm = pMixStrm;
1717	}
1718	else
1719	rc = VERR_INVALID_PARAMETER;
1720
1721	if (pStreamCfg)
1722	{
1723	RTMemFree(pStreamCfg);
1724	pStreamCfg = NULL;
1725	}
1726
1727	LogFlowFuncLeaveRC(rc);
1728	return rc;
1729	}
1730
1731	/**
1732	* Adds all current driver streams to a specific mixer sink.
1733	*
1734	* @returns IPRT status code.
1735	* @param pThis AC'97 state.
1736	* @param pMixSink Mixer sink to add stream to.
1737	* @param pCfg Stream configuration to use.
1738	*/
1739	static int ichac97R3MixerAddDrvStreams(PAC97STATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
1740	{
1741	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1742	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1743	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1744
1745	if (!DrvAudioHlpStreamCfgIsValid(pCfg))
1746	return VERR_INVALID_PARAMETER;
1747
1748	int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
1749	if (RT_FAILURE(rc))
1750	return rc;
1751
1752	PAC97DRIVER pDrv;
1753	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
1754	{
1755	int rc2 = ichac97R3MixerAddDrvStream(pThis, pMixSink, pCfg, pDrv);
1756	if (RT_FAILURE(rc2))
1757	LogFunc(("Attaching stream failed with %Rrc\n", rc2));
1758
1759	/* Do not pass failure to rc here, as there might be drivers which aren't
1760	* configured / ready yet. */
1761	}
1762
1763	LogFlowFuncLeaveRC(rc);
1764	return rc;
1765	}
1766
1767	/**
1768	* Removes a driver stream from a specific mixer sink.
1769	*
1770	* @param pThis AC'97 state.
1771	* @param pMixSink Mixer sink to remove audio streams from.
1772	* @param enmDir Stream direction to remove.
1773	* @param dstSrc Stream destination / source to remove.
1774	* @param pDrv Driver stream to remove.
1775	*/
1776	static void ichac97R3MixerRemoveDrvStream(PAC97STATE pThis, PAUDMIXSINK pMixSink,
1777	PDMAUDIODIR enmDir, PDMAUDIODESTSOURCE dstSrc, PAC97DRIVER pDrv)
1778	{
1779	AssertPtrReturnVoid(pThis);
1780	AssertPtrReturnVoid(pMixSink);
1781
1782	PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pThis, pDrv, enmDir, dstSrc);
1783	if (pDrvStream)
1784	{
1785	if (pDrvStream->pMixStrm)
1786	{
1787	AudioMixerSinkRemoveStream(pMixSink, pDrvStream->pMixStrm);
1788
1789	AudioMixerStreamDestroy(pDrvStream->pMixStrm);
1790	pDrvStream->pMixStrm = NULL;
1791	}
1792	}
1793	}
1794
1795	/**
1796	* Removes all driver streams from a specific mixer sink.
1797	*
1798	* @param pThis AC'97 state.
1799	* @param pMixSink Mixer sink to remove audio streams from.
1800	* @param enmDir Stream direction to remove.
1801	* @param dstSrc Stream destination / source to remove.
1802	*/
1803	static void ichac97R3MixerRemoveDrvStreams(PAC97STATE pThis, PAUDMIXSINK pMixSink,
1804	PDMAUDIODIR enmDir, PDMAUDIODESTSOURCE dstSrc)
1805	{
1806	AssertPtrReturnVoid(pThis);
1807	AssertPtrReturnVoid(pMixSink);
1808
1809	PAC97DRIVER pDrv;
1810	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
1811	{
1812	ichac97R3MixerRemoveDrvStream(pThis, pMixSink, enmDir, dstSrc, pDrv);
1813	}
1814	}
1815
1816	/**
1817	* Opens an AC'97 stream with its current mixer settings.
1818	*
1819	* This will open an AC'97 stream with 2 (stereo) channels, 16-bit samples and
1820	* the last set sample rate in the AC'97 mixer for this stream.
1821	*
1822	* @returns IPRT status code.
1823	* @param pThis AC'97 state.
1824	* @param pStream AC'97 Stream to open.
1825	*/
1826	static int ichac97R3StreamOpen(PAC97STATE pThis, PAC97STREAM pStream)
1827	{
1828	int rc = VINF_SUCCESS;
1829
1830	LogFunc(("[SD%RU8]\n", pStream->u8SD));
1831
1832	RT_ZERO(pStream->State.Cfg);
1833
1834	PPDMAUDIOSTREAMCFG pCfg = &pStream->State.Cfg;
1835	PAUDMIXSINK pMixSink = NULL;
1836	AssertCompile(sizeof(pCfg->szName) >= 8);
1837
1838	/* Set scheduling hint (if available). */
1839	if (pThis->cTimerTicks)
1840	pCfg->Device.uSchedulingHintMs = 1000 /* ms */ / (TMTimerGetFreq(pThis->pTimerR3) / pThis->cTimerTicks);
1841
1842	switch (pStream->u8SD)
1843	{
1844	case AC97SOUNDSOURCE_PI_INDEX:
1845	{
1846	pCfg->Props.uHz = ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate);
1847	pCfg->enmDir = PDMAUDIODIR_IN;
1848	pCfg->DestSource.Source = PDMAUDIORECSOURCE_LINE;
1849	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1850	strcpy(pCfg->szName, "Line-In");
1851
1852	pMixSink = pThis->pSinkLineIn;
1853	break;
1854	}
1855
1856	case AC97SOUNDSOURCE_MC_INDEX:
1857	{
1858	pCfg->Props.uHz = ichac97MixerGet(pThis, AC97_MIC_ADC_Rate);
1859	pCfg->enmDir = PDMAUDIODIR_IN;
1860	pCfg->DestSource.Source = PDMAUDIORECSOURCE_MIC;
1861	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1862	strcpy(pCfg->szName, "Mic-In");
1863
1864	pMixSink = pThis->pSinkMicIn;
1865	break;
1866	}
1867
1868	case AC97SOUNDSOURCE_PO_INDEX:
1869	{
1870	pCfg->Props.uHz = ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate);
1871	pCfg->enmDir = PDMAUDIODIR_OUT;
1872	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
1873	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1874	strcpy(pCfg->szName, "Output");
1875
1876	pMixSink = pThis->pSinkOut;
1877	break;
1878	}
1879
1880	default:
1881	rc = VERR_NOT_SUPPORTED;
1882	break;
1883	}
1884
1885	if (RT_SUCCESS(rc))
1886	{
1887	ichac97R3MixerRemoveDrvStreams(pThis, pMixSink, pCfg->enmDir, pCfg->DestSource);
1888
1889	if (pCfg->Props.uHz)
1890	{
1891	Assert(pCfg->enmDir != PDMAUDIODIR_UNKNOWN);
1892
1893	pCfg->Props.cChannels = 2;
1894	pCfg->Props.cBytes = 2 /* 16-bit */;
1895	pCfg->Props.fSigned = true;
1896	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBytes, pCfg->Props.cChannels);
1897
1898	if (pStream->State.pCircBuf)
1899	{
1900	RTCircBufDestroy(pStream->State.pCircBuf);
1901	pStream->State.pCircBuf = NULL;
1902	}
1903
1904	rc = RTCircBufCreate(&pStream->State.pCircBuf, DrvAudioHlpMilliToBytes(500 /* ms /, &pCfg->Props)); /* @todo Make this configurable. */
1905	if (RT_SUCCESS(rc))
1906	rc = ichac97R3MixerAddDrvStreams(pThis, pMixSink, pCfg);
1907	}
1908	}
1909
1910	LogFlowFunc(("[SD%RU8] rc=%Rrc\n", pStream->u8SD, rc));
1911	return rc;
1912	}
1913
1914	/**
1915	* Closes an AC'97 stream.
1916	*
1917	* @returns IPRT status code.
1918	* @param pThis AC'97 state.
1919	* @param pStream AC'97 stream to close.
1920	*/
1921	static int ichac97R3StreamClose(PAC97STATE pThis, PAC97STREAM pStream)
1922	{
1923	RT_NOREF(pThis, pStream);
1924
1925	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
1926
1927	return VINF_SUCCESS;
1928	}
1929
1930	/**
1931	* Re-opens (that is, closes and opens again) an AC'97 stream on the backend
1932	* side with the current AC'97 mixer settings for this stream.
1933	*
1934	* @returns IPRT status code.
1935	* @param pThis AC'97 device state.
1936	* @param pStream AC'97 stream to re-open.
1937	*/
1938	static int ichac97R3StreamReOpen(PAC97STATE pThis, PAC97STREAM pStream)
1939	{
1940	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
1941
1942	int rc = ichac97R3StreamClose(pThis, pStream);
1943	if (RT_SUCCESS(rc))
1944	rc = ichac97R3StreamOpen(pThis, pStream);
1945
1946	return rc;
1947	}
1948
1949	/**
1950	* Locks an AC'97 stream for serialized access.
1951	*
1952	* @returns IPRT status code.
1953	* @param pStream AC'97 stream to lock.
1954	*/
1955	static void ichac97R3StreamLock(PAC97STREAM pStream)
1956	{
1957	AssertPtrReturnVoid(pStream);
1958	int rc2 = RTCritSectEnter(&pStream->State.CritSect);
1959	AssertRC(rc2);
1960	}
1961
1962	/**
1963	* Unlocks a formerly locked AC'97 stream.
1964	*
1965	* @returns IPRT status code.
1966	* @param pStream AC'97 stream to unlock.
1967	*/
1968	static void ichac97R3StreamUnlock(PAC97STREAM pStream)
1969	{
1970	AssertPtrReturnVoid(pStream);
1971	int rc2 = RTCritSectLeave(&pStream->State.CritSect);
1972	AssertRC(rc2);
1973	}
1974
1975	/**
1976	* Retrieves the available size of (buffered) audio data (in bytes) of a given AC'97 stream.
1977	*
1978	* @returns Available data (in bytes).
1979	* @param pStream AC'97 stream to retrieve size for.
1980	*/
1981	static uint32_t ichac97R3StreamGetUsed(PAC97STREAM pStream)
1982	{
1983	AssertPtrReturn(pStream, 0);
1984
1985	if (!pStream->State.pCircBuf)
1986	return 0;
1987
1988	return (uint32_t)RTCircBufUsed(pStream->State.pCircBuf);
1989	}
1990
1991	/**
1992	* Retrieves the free size of audio data (in bytes) of a given AC'97 stream.
1993	*
1994	* @returns Free data (in bytes).
1995	* @param pStream AC'97 stream to retrieve size for.
1996	*/
1997	static uint32_t ichac97R3StreamGetFree(PAC97STREAM pStream)
1998	{
1999	AssertPtrReturn(pStream, 0);
2000
2001	if (!pStream->State.pCircBuf)
2002	return 0;
2003
2004	return (uint32_t)RTCircBufFree(pStream->State.pCircBuf);
2005	}
2006
2007	/**
2008	* Sets the volume of a specific AC'97 mixer control.
2009	*
2010	* This currently only supports attenuation -- gain support is currently not implemented.
2011	*
2012	* @returns IPRT status code.
2013	* @param pThis AC'97 state.
2014	* @param index AC'97 mixer index to set volume for.
2015	* @param enmMixerCtl Corresponding audio mixer sink.
2016	* @param uVal Volume value to set.
2017	*/
2018	static int ichac97R3MixerSetVolume(PAC97STATE pThis, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2019	{
2020	/*
2021	* From AC'97 SoundMax Codec AD1981A/AD1981B:
2022	* "Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the
2023	* D5 or D13 bits are set to 1, their respective lower five volume bits are automatically
2024	* set to 1 by the Codec logic. On readback, all lower 5 bits will read ones whenever
2025	* these bits are set to 1."
2026	*
2027	* Linux ALSA depends on this behavior.
2028	*/
2029	/// @todo Does this apply to anything other than the master volume control?
2030	if (uVal & RT_BIT(5)) /* D5 bit set? */
2031	uVal \|= RT_BIT(4) \| RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1) \| RT_BIT(0);
2032	if (uVal & RT_BIT(13)) /* D13 bit set? */
2033	uVal \|= RT_BIT(12) \| RT_BIT(11) \| RT_BIT(10) \| RT_BIT(9) \| RT_BIT(8);
2034
2035	const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2036	uint8_t uCtlAttLeft = (uVal >> 8) & AC97_BARS_VOL_MASK;
2037	uint8_t uCtlAttRight = uVal & AC97_BARS_VOL_MASK;
2038
2039	/* For the master and headphone volume, 0 corresponds to 0dB attenuation. For the other
2040	* volume controls, 0 means 12dB gain and 8 means unity gain.
2041	*/
2042	if (index != AC97_Master_Volume_Mute && index != AC97_Headphone_Volume_Mute)
2043	{
2044	# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2045	/* NB: Currently there is no gain support, only attenuation. */
2046	uCtlAttLeft = uCtlAttLeft < 8 ? 0 : uCtlAttLeft - 8;
2047	uCtlAttRight = uCtlAttRight < 8 ? 0 : uCtlAttRight - 8;
2048	# endif
2049	}
2050	Assert(uCtlAttLeft <= 255 / AC97_DB_FACTOR);
2051	Assert(uCtlAttRight <= 255 / AC97_DB_FACTOR);
2052
2053	LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2054	LogFunc(("uCtlAttLeft=%RU8, uCtlAttRight=%RU8 ", uCtlAttLeft, uCtlAttRight));
2055
2056	/*
2057	* For AC'97 volume controls, each additional step means -1.5dB attenuation with
2058	* zero being maximum. In contrast, we're internally using 255 (PDMAUDIO_VOLUME_MAX)
2059	* steps, each -0.375dB, where 0 corresponds to -96dB and 255 corresponds to 0dB.
2060	*/
2061	uint8_t lVol = PDMAUDIO_VOLUME_MAX - uCtlAttLeft * AC97_DB_FACTOR;
2062	uint8_t rVol = PDMAUDIO_VOLUME_MAX - uCtlAttRight * AC97_DB_FACTOR;
2063
2064	Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2065
2066	int rc = VINF_SUCCESS;
2067
2068	if (pThis->pMixer) /* Device can be in reset state, so no mixer available. */
2069	{
2070	PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2071	PAUDMIXSINK pSink = NULL;
2072
2073	switch (enmMixerCtl)
2074	{
2075	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2076	rc = AudioMixerSetMasterVolume(pThis->pMixer, &Vol);
2077	break;
2078
2079	case PDMAUDIOMIXERCTL_FRONT:
2080	pSink = pThis->pSinkOut;
2081	break;
2082
2083	case PDMAUDIOMIXERCTL_MIC_IN:
2084	pSink = pThis->pSinkMicIn;
2085	break;
2086
2087	case PDMAUDIOMIXERCTL_LINE_IN:
2088	pSink = pThis->pSinkLineIn;
2089	break;
2090
2091	default:
2092	AssertFailed();
2093	rc = VERR_NOT_SUPPORTED;
2094	break;
2095	}
2096
2097	if (pSink)
2098	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2099	}
2100
2101	ichac97MixerSet(pThis, index, uVal);
2102
2103	if (RT_FAILURE(rc))
2104	LogFlowFunc(("Failed with %Rrc\n", rc));
2105
2106	return rc;
2107	}
2108
2109	/**
2110	* Converts an AC'97 recording source index to a PDM audio recording source.
2111	*
2112	* @returns PDM audio recording source.
2113	* @param uIdx AC'97 index to convert.
2114	*/
2115	static PDMAUDIORECSOURCE ichac97R3IdxToRecSource(uint8_t uIdx)
2116	{
2117	switch (uIdx)
2118	{
2119	case AC97_REC_MIC: return PDMAUDIORECSOURCE_MIC;
2120	case AC97_REC_CD: return PDMAUDIORECSOURCE_CD;
2121	case AC97_REC_VIDEO: return PDMAUDIORECSOURCE_VIDEO;
2122	case AC97_REC_AUX: return PDMAUDIORECSOURCE_AUX;
2123	case AC97_REC_LINE_IN: return PDMAUDIORECSOURCE_LINE;
2124	case AC97_REC_PHONE: return PDMAUDIORECSOURCE_PHONE;
2125	default:
2126	break;
2127	}
2128
2129	LogFlowFunc(("Unknown record source %d, using MIC\n", uIdx));
2130	return PDMAUDIORECSOURCE_MIC;
2131	}
2132
2133	/**
2134	* Converts a PDM audio recording source to an AC'97 recording source index.
2135	*
2136	* @returns AC'97 recording source index.
2137	* @param enmRecSrc PDM audio recording source to convert.
2138	*/
2139	static uint8_t ichac97R3RecSourceToIdx(PDMAUDIORECSOURCE enmRecSrc)
2140	{
2141	switch (enmRecSrc)
2142	{
2143	case PDMAUDIORECSOURCE_MIC: return AC97_REC_MIC;
2144	case PDMAUDIORECSOURCE_CD: return AC97_REC_CD;
2145	case PDMAUDIORECSOURCE_VIDEO: return AC97_REC_VIDEO;
2146	case PDMAUDIORECSOURCE_AUX: return AC97_REC_AUX;
2147	case PDMAUDIORECSOURCE_LINE: return AC97_REC_LINE_IN;
2148	case PDMAUDIORECSOURCE_PHONE: return AC97_REC_PHONE;
2149	default:
2150	break;
2151	}
2152
2153	LogFlowFunc(("Unknown audio recording source %d using MIC\n", enmRecSrc));
2154	return AC97_REC_MIC;
2155	}
2156
2157	/**
2158	* Returns the audio direction of a specified stream descriptor.
2159	*
2160	* @return Audio direction.
2161	*/
2162	DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD)
2163	{
2164	switch (uSD)
2165	{
2166	case AC97SOUNDSOURCE_PI_INDEX: return PDMAUDIODIR_IN;
2167	case AC97SOUNDSOURCE_PO_INDEX: return PDMAUDIODIR_OUT;
2168	case AC97SOUNDSOURCE_MC_INDEX: return PDMAUDIODIR_IN;
2169	}
2170
2171	return PDMAUDIODIR_UNKNOWN;
2172	}
2173
2174	#endif /* IN_RING3 */
2175
2176	/**
2177	* Retrieves an AC'97 audio stream from an AC'97 stream index.
2178	*
2179	* @returns Pointer to AC'97 audio stream if found, or NULL if not found / invalid.
2180	* @param pThis AC'97 state.
2181	* @param uIdx AC'97 stream index to retrieve AC'97 audio stream for.
2182	*/
2183	DECLINLINE(PAC97STREAM) ichac97GetStreamFromIdx(PAC97STATE pThis, uint32_t uIdx)
2184	{
2185	switch (uIdx)
2186	{
2187	case AC97SOUNDSOURCE_PI_INDEX: return &pThis->StreamLineIn;
2188	case AC97SOUNDSOURCE_MC_INDEX: return &pThis->StreamMicIn;
2189	case AC97SOUNDSOURCE_PO_INDEX: return &pThis->StreamOut;
2190	default: return NULL;
2191	}
2192
2193	}
2194
2195	#ifdef IN_RING3
2196
2197	/**
2198	* Performs an AC'97 mixer record select to switch to a different recording
2199	* source.
2200	*
2201	* @param pThis AC'97 state.
2202	* @param val AC'97 recording source index to set.
2203	*/
2204	static void ichac97R3MixerRecordSelect(PAC97STATE pThis, uint32_t val)
2205	{
2206	uint8_t rs = val & AC97_REC_MASK;
2207	uint8_t ls = (val >> 8) & AC97_REC_MASK;
2208	PDMAUDIORECSOURCE ars = ichac97R3IdxToRecSource(rs);
2209	PDMAUDIORECSOURCE als = ichac97R3IdxToRecSource(ls);
2210	rs = ichac97R3RecSourceToIdx(ars);
2211	ls = ichac97R3RecSourceToIdx(als);
2212	ichac97MixerSet(pThis, AC97_Record_Select, rs \| (ls << 8));
2213	}
2214
2215	/**
2216	* Resets the AC'97 mixer.
2217	*
2218	* @returns IPRT status code.
2219	* @param pThis AC'97 state.
2220	*/
2221	static int ichac97R3MixerReset(PAC97STATE pThis)
2222	{
2223	AssertPtrReturn(pThis, VERR_INVALID_PARAMETER);
2224
2225	LogFlowFuncEnter();
2226
2227	RT_ZERO(pThis->mixer_data);
2228
2229	/* Note: Make sure to reset all registers first before bailing out on error. */
2230
2231	ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
2232	ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
2233	ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
2234
2235	ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
2236	ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
2237	ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
2238	ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
2239	ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
2240	ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
2241	ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
2242	ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
2243
2244	ichac97MixerSet(pThis, AC97_Extended_Audio_ID , 0x0809);
2245	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
2246	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80);
2247	ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80);
2248	ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80);
2249	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80);
2250	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80);
2251
2252	if (pThis->uCodecModel == AC97_CODEC_AD1980)
2253	{
2254	/* Analog Devices 1980 (AD1980) */
2255	ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
2256	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2257	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
2258	ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
2259	}
2260	else if (pThis->uCodecModel == AC97_CODEC_AD1981B)
2261	{
2262	/* Analog Devices 1981B (AD1981B) */
2263	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2264	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
2265	}
2266	else
2267	{
2268	/* Sigmatel 9700 (STAC9700) */
2269	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
2270	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
2271	}
2272	ichac97R3MixerRecordSelect(pThis, 0);
2273
2274	/* The default value is 8000h, which corresponds to 0 dB attenuation with mute on. */
2275	ichac97R3MixerSetVolume(pThis, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER, 0x8000);
2276
2277	/* The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on.*/
2278	ichac97R3MixerSetVolume(pThis, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT, 0x8808);
2279	ichac97R3MixerSetVolume(pThis, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
2280	ichac97R3MixerSetVolume(pThis, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8808);
2281
2282	return VINF_SUCCESS;
2283	}
2284
2285	# if 0 /* Unused */
2286	static void ichac97R3WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
2287	{
2288	LogFlowFunc(("cbElapsed=%RU32\n", cbElapsed));
2289
2290	if (!(pThis->bup_flag & BUP_SET))
2291	{
2292	if (pThis->bup_flag & BUP_LAST)
2293	{
2294	unsigned int i;
2295	uint32_t p = (uint32_t)pThis->silence;
2296	for (i = 0; i < sizeof(pThis->silence) / 4; i++) /** @todo r=andy Assumes 16-bit samples, stereo. */
2297	*p++ = pThis->last_samp;
2298	}
2299	else
2300	RT_ZERO(pThis->silence);
2301
2302	pThis->bup_flag \|= BUP_SET;
2303	}
2304
2305	while (cbElapsed)
2306	{
2307	uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
2308	uint32_t cbWrittenToStream;
2309
2310	int rc2 = AudioMixerSinkWrite(pThis->pSinkOut, AUDMIXOP_COPY,
2311	pThis->silence, cbToWrite, &cbWrittenToStream);
2312	if (RT_SUCCESS(rc2))
2313	{
2314	if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2315	LogFlowFunc(("Warning: Only written %RU32 / %RU32 bytes, expect lags\n", cbWrittenToStream, cbToWrite));
2316	}
2317
2318	/* Always report all data as being written;
2319	* backends who were not able to catch up have to deal with it themselves. */
2320	Assert(cbElapsed >= cbToWrite);
2321	cbElapsed -= cbToWrite;
2322	}
2323	}
2324	# endif /* Unused */
2325
2326	# ifndef VBOX_WITH_AUDIO_AC97_CALLBACKS
2327
2328	/**
2329	* Starts the internal audio device timer.
2330	*
2331	* @return IPRT status code.
2332	* @param pThis AC'97 state.
2333	*/
2334	static int ichac97R3TimerStart(PAC97STATE pThis)
2335	{
2336	LogFlowFuncEnter();
2337
2338	DEVAC97_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2339
2340	AssertPtr(pThis->CTX_SUFF(pTimer));
2341
2342	if (!pThis->fTimerActive)
2343	{
2344	LogRel2(("AC97: Starting transfers\n"));
2345
2346	pThis->fTimerActive = true;
2347
2348	/* Start transfers. */
2349	ichac97R3TimerMain(pThis);
2350	}
2351
2352	DEVAC97_UNLOCK_BOTH(pThis);
2353
2354	return VINF_SUCCESS;
2355	}
2356
2357	/**
2358	* Starts the internal audio device timer (if not started yet).
2359	*
2360	* @return IPRT status code.
2361	* @param pThis AC'97 state.
2362	*/
2363	static int ichac97R3TimerMaybeStart(PAC97STATE pThis)
2364	{
2365	LogFlowFuncEnter();
2366
2367	if (!pThis->CTX_SUFF(pTimer))
2368	return VERR_WRONG_ORDER;
2369
2370	pThis->cStreamsActive++;
2371
2372	/* Only start the timer at the first active stream. */
2373	if (pThis->cStreamsActive == 1)
2374	return ichac97R3TimerStart(pThis);
2375
2376	return VINF_SUCCESS;
2377	}
2378
2379	/**
2380	* Stops the internal audio device timer.
2381	*
2382	* @return IPRT status code.
2383	* @param pThis AC'97 state.
2384	*/
2385	static int ichac97R3TimerStop(PAC97STATE pThis)
2386	{
2387	LogFlowFuncEnter();
2388
2389	if (!pThis->CTX_SUFF(pTimer)) /* Only can happen on device construction time, so no locking needed here. */
2390	return VINF_SUCCESS;
2391
2392	DEVAC97_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2393
2394	if (pThis->fTimerActive)
2395	{
2396	LogRel2(("AC97: Stopping transfers ...\n"));
2397
2398	pThis->fTimerActive = false;
2399
2400	/* Note: Do not stop the timer via TMTimerStop() here, as there still might
2401	* be queued audio data which needs to be handled (e.g. played back) first
2402	* before actually stopping the timer for good. */
2403	}
2404
2405	DEVAC97_UNLOCK_BOTH(pThis);
2406
2407	return VINF_SUCCESS;
2408	}
2409
2410	/**
2411	* Decreases the active AC'97 streams count by one and
2412	* then checks if the internal audio device timer can be
2413	* stopped.
2414	*
2415	* @return IPRT status code.
2416	* @param pThis AC'97 state.
2417	*/
2418	static int ichac97R3TimerMaybeStop(PAC97STATE pThis)
2419	{
2420	LogFlowFuncEnter();
2421
2422	if (!pThis->CTX_SUFF(pTimer))
2423	return VERR_WRONG_ORDER;
2424
2425	if (pThis->cStreamsActive) /* Function can be called mupltiple times. */
2426	{
2427	pThis->cStreamsActive--;
2428
2429	if (pThis->cStreamsActive == 0)
2430	return ichac97R3TimerStop(pThis);
2431	}
2432
2433	return VINF_SUCCESS;
2434	}
2435
2436	/**
2437	* Main routine for the device timer.
2438	*
2439	* @param pThis AC'97 state.
2440	*/
2441	static void ichac97R3TimerMain(PAC97STATE pThis)
2442	{
2443	STAM_PROFILE_START(&pThis->StatTimer, a);
2444
2445	DEVAC97_LOCK_BOTH_RETURN_VOID(pThis);
2446
2447	uint64_t cTicksNow = TMTimerGet(pThis->CTX_SUFF(pTimer));
2448
2449	/* Update current time timestamp. */
2450	pThis->uTimerTS = cTicksNow;
2451
2452	/* Flag indicating whether to arm the timer again for the next DMA transfer or sink processing. */
2453	bool fArmTimer = false;
2454
2455	ichac97R3DoTransfers(pThis);
2456
2457	/* Do we need to arm the timer again? */
2458	if ( AudioMixerSinkIsActive(ichac97R3IndexToSink(pThis, pThis->StreamLineIn.u8SD))
2459	\|\| AudioMixerSinkIsActive(ichac97R3IndexToSink(pThis, pThis->StreamMicIn.u8SD))
2460	\|\| AudioMixerSinkIsActive(ichac97R3IndexToSink(pThis, pThis->StreamOut.u8SD)))
2461	{
2462	fArmTimer = true;
2463	}
2464
2465	if ( ASMAtomicReadBool(&pThis->fTimerActive) /** @todo r=bird: totally unnecessary to do atomic read here, isn't it? */
2466	\|\| fArmTimer)
2467	{
2468	/* Arm the timer again. */
2469	uint64_t cTicks = pThis->cTimerTicks;
2470	/** @todo adjust cTicks down by now much cbOutMin represents. */
2471	TMTimerSet(pThis->CTX_SUFF(pTimer), cTicksNow + cTicks);
2472	}
2473	else
2474	LogRel2(("AC97: Stopped transfers\n"));
2475
2476	DEVAC97_UNLOCK_BOTH(pThis);
2477
2478	STAM_PROFILE_STOP(&pThis->StatTimer, a);
2479	}
2480
2481	/**
2482	* Timer callback which handles the audio data transfers on a periodic basis.
2483	*
2484	* @param pDevIns Device instance.
2485	* @param pTimer Timer which was used when calling this.
2486	* @param pvUser User argument as PAC97STATE.
2487	*/
2488	static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2489	{
2490	RT_NOREF(pDevIns, pTimer);
2491
2492	PAC97STATE pThis = (PAC97STATE)pvUser;
2493	Assert(pThis == PDMINS_2_DATA(pDevIns, PAC97STATE));
2494
2495	ichac97R3TimerMain(pThis);
2496	}
2497
2498	# endif /* !VBOX_WITH_AUDIO_AC97_CALLBACKS */
2499
2500	/**
2501	* Main routine to perform the actual audio data transfers from the AC'97 streams
2502	* to the backend(s) and vice versa.
2503	*
2504	* @param pThis AC'97 state.
2505	*/
2506	static void ichac97R3DoTransfers(PAC97STATE pThis)
2507	{
2508	AssertPtrReturnVoid(pThis);
2509
2510	ichac97R3StreamUpdate(pThis, &pThis->StreamLineIn, true /* fInTimer */);
2511	ichac97R3StreamUpdate(pThis, &pThis->StreamMicIn, true /* fInTimer */);
2512	ichac97R3StreamUpdate(pThis, &pThis->StreamOut, true /* fInTimer */);
2513	}
2514
2515	/**
2516	* Transfers data of an AC'97 stream according to its usage (input / output).
2517	*
2518	* For an SDO (output) stream this means reading DMA data from the device to
2519	* the AC'97 stream's internal FIFO buffer.
2520	*
2521	* For an SDI (input) stream this is reading audio data from the AC'97 stream's
2522	* internal FIFO buffer and writing it as DMA data to the device.
2523	*
2524	* @returns IPRT status code.
2525	* @param pThis AC'97 state.
2526	* @param pStream AC'97 stream to update.
2527	* @param cbToProcessMax Maximum of data (in bytes) to process.
2528	*/
2529	static int ichac97R3StreamTransfer(PAC97STATE pThis, PAC97STREAM pStream, uint32_t cbToProcessMax)
2530	{
2531	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2532	AssertPtrReturn(pStream, VERR_INVALID_POINTER);
2533	AssertReturn(cbToProcessMax, VERR_INVALID_PARAMETER);
2534
2535	ichac97R3StreamLock(pStream);
2536
2537	PAC97BMREGS pRegs = &pStream->Regs;
2538
2539	if (pRegs->sr & AC97_SR_DCH) /* Controller halted? */
2540	{
2541	if (pRegs->cr & AC97_CR_RPBM) /* Bus master operation starts. */
2542	{
2543	switch (pStream->u8SD)
2544	{
2545	case AC97SOUNDSOURCE_PO_INDEX:
2546	/ichac97R3WriteBUP(pThis, cbToProcess);/
2547	break;
2548
2549	default:
2550	break;
2551	}
2552	}
2553
2554	ichac97R3StreamUnlock(pStream);
2555	return VINF_SUCCESS;
2556	}
2557
2558	/* BCIS flag still set? Skip iteration. */
2559	if (pRegs->sr & AC97_SR_BCIS)
2560	{
2561	Log3Func(("[SD%RU8] BCIS set\n", pStream->u8SD));
2562
2563	ichac97R3StreamUnlock(pStream);
2564	return VINF_SUCCESS;
2565	}
2566
2567	uint32_t cbLeft = RT_MIN((uint32_t)(pRegs->picb << 1), cbToProcessMax); /** @todo r=andy Assumes 16bit samples. */
2568	uint32_t cbProcessedTotal = 0;
2569
2570	PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
2571	AssertPtr(pCircBuf);
2572
2573	int rc = VINF_SUCCESS;
2574
2575	Log3Func(("[SD%RU8] cbToProcessMax=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcessMax, cbLeft));
2576
2577	while (cbLeft)
2578	{
2579	if (!pRegs->bd_valid)
2580	{
2581	Log3Func(("Invalid buffer descriptor, fetching next one ...\n"));
2582	ichac97R3StreamFetchBDLE(pThis, pStream);
2583	}
2584
2585	if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
2586	{
2587	Log3Func(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
2588	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
2589	if (pRegs->civ == pRegs->lvi)
2590	{
2591	pRegs->sr \|= AC97_SR_DCH; /** @todo r=andy Also set CELV? */
2592	pThis->bup_flag = 0;
2593
2594	rc = VINF_EOF;
2595	break;
2596	}
2597
2598	pRegs->sr &= ~AC97_SR_CELV;
2599	pRegs->civ = pRegs->piv;
2600	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2601
2602	ichac97R3StreamFetchBDLE(pThis, pStream);
2603	continue;
2604	}
2605
2606	uint32_t cbChunk = RT_MIN((uint32_t)(pRegs->picb << 1), cbLeft); /** @todo r=andy Assumes 16bit samples. */
2607	Assert(cbChunk);
2608
2609	switch (pStream->u8SD)
2610	{
2611	case AC97SOUNDSOURCE_PO_INDEX: /* Output */
2612	{
2613	void *pvDst;
2614	size_t cbDst;
2615
2616	RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvDst, &cbDst);
2617
2618	if (cbDst)
2619	{
2620	int rc2 = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pRegs->bd.addr, (uint8_t *)pvDst, cbDst);
2621	AssertRC(rc2);
2622
2623	if (pStream->Dbg.Runtime.fEnabled)
2624	DrvAudioHlpFileWrite(pStream->Dbg.Runtime.pFileDMA, pvDst, cbDst, 0 /* fFlags */);
2625	}
2626
2627	RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
2628
2629	cbChunk = (uint32_t)cbDst; /* Update the current chunk size to what really has been written. */
2630	break;
2631	}
2632
2633	case AC97SOUNDSOURCE_PI_INDEX: /* Input */
2634	case AC97SOUNDSOURCE_MC_INDEX: /* Input */
2635	{
2636	void *pvSrc;
2637	size_t cbSrc;
2638
2639	RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvSrc, &cbSrc);
2640
2641	if (cbSrc)
2642	{
2643	/** @todo r=bird: Just curious, DevHDA uses PDMDevHlpPCIPhysWrite here. So,
2644	* is AC97 not subject to PCI busmaster enable/disable? */
2645	int rc2 = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pRegs->bd.addr, (uint8_t *)pvSrc, cbSrc);
2646	AssertRC(rc2);
2647
2648	if (pStream->Dbg.Runtime.fEnabled)
2649	DrvAudioHlpFileWrite(pStream->Dbg.Runtime.pFileDMA, pvSrc, cbSrc, 0 /* fFlags */);
2650	}
2651
2652	RTCircBufReleaseReadBlock(pCircBuf, cbSrc);
2653
2654	cbChunk = (uint32_t)cbSrc; /* Update the current chunk size to what really has been read. */
2655	break;
2656	}
2657
2658	default:
2659	AssertMsgFailed(("Stream #%RU8 not supported\n", pStream->u8SD));
2660	rc = VERR_NOT_SUPPORTED;
2661	break;
2662	}
2663
2664	if (RT_FAILURE(rc))
2665	break;
2666
2667	if (cbChunk)
2668	{
2669	cbProcessedTotal += cbChunk;
2670	Assert(cbProcessedTotal <= cbToProcessMax);
2671	Assert(cbLeft >= cbChunk);
2672	cbLeft -= cbChunk;
2673	Assert((cbChunk & 1) == 0); /* Else the following shift won't work */
2674
2675	pRegs->picb -= (cbChunk >> 1); /** @todo r=andy Assumes 16bit samples. */
2676	pRegs->bd.addr += cbChunk;
2677	}
2678
2679	LogFlowFunc(("[SD%RU8] cbChunk=%RU32, cbLeft=%RU32, cbTotal=%RU32, rc=%Rrc\n",
2680	pStream->u8SD, cbChunk, cbLeft, cbProcessedTotal, rc));
2681
2682	if (!pRegs->picb)
2683	{
2684	uint32_t new_sr = pRegs->sr & ~AC97_SR_CELV;
2685
2686	if (pRegs->bd.ctl_len & AC97_BD_IOC)
2687	{
2688	new_sr \|= AC97_SR_BCIS;
2689	}
2690
2691	if (pRegs->civ == pRegs->lvi)
2692	{
2693	/* Did we run out of data? */
2694	LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pRegs->civ, pRegs->lvi));
2695
2696	new_sr \|= AC97_SR_LVBCI \| AC97_SR_DCH \| AC97_SR_CELV;
2697	pThis->bup_flag = (pRegs->bd.ctl_len & AC97_BD_BUP) ? BUP_LAST : 0;
2698
2699	rc = VINF_EOF;
2700	}
2701	else
2702	{
2703	pRegs->civ = pRegs->piv;
2704	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2705	ichac97R3StreamFetchBDLE(pThis, pStream);
2706	}
2707
2708	ichac97StreamUpdateSR(pThis, pStream, new_sr);
2709	}
2710
2711	if (/* All data processed? */
2712	rc == VINF_EOF
2713	/* ... or an error occurred? */
2714	\|\| RT_FAILURE(rc))
2715	{
2716	break;
2717	}
2718	}
2719
2720	pStream->State.tsLastTransferNs = RTTimeNanoTS();
2721
2722	ichac97R3StreamUnlock(pStream);
2723
2724	LogFlowFuncLeaveRC(rc);
2725	return rc;
2726	}
2727
2728	#endif /* IN_RING3 */
2729
2730
2731	/**
2732	* Port I/O Handler for IN operations.
2733	*
2734	* @returns VINF_SUCCESS or VINF_EM_*.
2735	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
2736	*
2737	* @param pDevIns The device instance.
2738	* @param pvUser User argument.
2739	* @param uPort Port number used for the IN operation.
2740	* @param pu32Val Where to store the result. This is always a 32-bit
2741	* variable regardless of what @a cbVal might say.
2742	* @param cbVal Number of bytes read.
2743	*/
2744	PDMBOTHCBDECL(int) ichac97IOPortNABMRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32Val, unsigned cbVal)
2745	{
2746	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2747	RT_NOREF(pvUser);
2748
2749	DEVAC97_LOCK_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
2750
2751	/* Get the index of the NABMBAR port. */
2752	const uint32_t uPortIdx = uPort - pThis->IOPortBase[1];
2753
2754	PAC97STREAM pStream = ichac97GetStreamFromIdx(pThis, AC97_PORT2IDX(uPortIdx));
2755	PAC97BMREGS pRegs = NULL;
2756
2757	if (pStream) /* Can be NULL, depending on the index (port). */
2758	pRegs = &pStream->Regs;
2759
2760	int rc = VINF_SUCCESS;
2761
2762	switch (cbVal)
2763	{
2764	case 1:
2765	{
2766	switch (uPortIdx)
2767	{
2768	case AC97_CAS:
2769	/* Codec Access Semaphore Register */
2770	Log3Func(("CAS %d\n", pThis->cas));
2771	*pu32Val = pThis->cas;
2772	pThis->cas = 1;
2773	break;
2774	case PI_CIV:
2775	case PO_CIV:
2776	case MC_CIV:
2777	/* Current Index Value Register */
2778	*pu32Val = pRegs->civ;
2779	Log3Func(("CIV[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
2780	break;
2781	case PI_LVI:
2782	case PO_LVI:
2783	case MC_LVI:
2784	/* Last Valid Index Register */
2785	*pu32Val = pRegs->lvi;
2786	Log3Func(("LVI[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
2787	break;
2788	case PI_PIV:
2789	case PO_PIV:
2790	case MC_PIV:
2791	/* Prefetched Index Value Register */
2792	*pu32Val = pRegs->piv;
2793	Log3Func(("PIV[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
2794	break;
2795	case PI_CR:
2796	case PO_CR:
2797	case MC_CR:
2798	/* Control Register */
2799	*pu32Val = pRegs->cr;
2800	Log3Func(("CR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
2801	break;
2802	case PI_SR:
2803	case PO_SR:
2804	case MC_SR:
2805	/* Status Register (lower part) */
2806	*pu32Val = RT_LO_U8(pRegs->sr);
2807	Log3Func(("SRb[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
2808	break;
2809	default:
2810	*pu32Val = UINT32_MAX;
2811	LogFunc(("U nabm readb %#x -> %#x\n", uPort, *pu32Val));
2812	break;
2813	}
2814	break;
2815	}
2816
2817	case 2:
2818	{
2819	switch (uPortIdx)
2820	{
2821	case PI_SR:
2822	case PO_SR:
2823	case MC_SR:
2824	/* Status Register */
2825	*pu32Val = pRegs->sr;
2826	Log3Func(("SR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
2827	break;
2828	case PI_PICB:
2829	case PO_PICB:
2830	case MC_PICB:
2831	/* Position in Current Buffer */
2832	*pu32Val = pRegs->picb;
2833	Log3Func(("PICB[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
2834	break;
2835	default:
2836	*pu32Val = UINT32_MAX;
2837	LogFunc(("U nabm readw %#x -> %#x\n", uPort, *pu32Val));
2838	break;
2839	}
2840	break;
2841	}
2842
2843	case 4:
2844	{
2845	switch (uPortIdx)
2846	{
2847	case PI_BDBAR:
2848	case PO_BDBAR:
2849	case MC_BDBAR:
2850	/* Buffer Descriptor Base Address Register */
2851	*pu32Val = pRegs->bdbar;
2852	Log3Func(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(uPortIdx), *pu32Val));
2853	break;
2854	case PI_CIV:
2855	case PO_CIV:
2856	case MC_CIV:
2857	/* 32-bit access: Current Index Value Register +
2858	* Last Valid Index Register +
2859	* Status Register */
2860	pu32Val = pRegs->civ \| (pRegs->lvi << 8) \| (pRegs->sr << 16); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
2861	Log3Func(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
2862	AC97_PORT2IDX(uPortIdx), pRegs->civ, pRegs->lvi, pRegs->sr));
2863	break;
2864	case PI_PICB:
2865	case PO_PICB:
2866	case MC_PICB:
2867	/* 32-bit access: Position in Current Buffer Register +
2868	* Prefetched Index Value Register +
2869	* Control Register */
2870	pu32Val = pRegs->picb \| (pRegs->piv << 16) \| (pRegs->cr << 24); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
2871	Log3Func(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
2872	AC97_PORT2IDX(uPortIdx), *pu32Val, pRegs->picb, pRegs->piv, pRegs->cr));
2873	break;
2874	case AC97_GLOB_CNT:
2875	/* Global Control */
2876	*pu32Val = pThis->glob_cnt;
2877	Log3Func(("glob_cnt -> %#x\n", *pu32Val));
2878	break;
2879	case AC97_GLOB_STA:
2880	/* Global Status */
2881	*pu32Val = pThis->glob_sta \| AC97_GS_S0CR;
2882	Log3Func(("glob_sta -> %#x\n", *pu32Val));
2883	break;
2884	default:
2885	*pu32Val = UINT32_MAX;
2886	LogFunc(("U nabm readl %#x -> %#x\n", uPort, *pu32Val));
2887	break;
2888	}
2889	break;
2890	}
2891
2892	default:
2893	{
2894	AssertFailed();
2895	rc = VERR_IOM_IOPORT_UNUSED;
2896	}
2897	}
2898
2899	DEVAC97_UNLOCK(pThis);
2900
2901	return rc;
2902	}
2903
2904	/**
2905	* Port I/O Handler for OUT operations.
2906	*
2907	* @returns VINF_SUCCESS or VINF_EM_*.
2908	*
2909	* @param pDevIns The device instance.
2910	* @param pvUser User argument.
2911	* @param uPort Port number used for the OUT operation.
2912	* @param u32Val The value to output.
2913	* @param cbVal The value size in bytes.
2914	*/
2915	PDMBOTHCBDECL(int) ichac97IOPortNABMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32Val, unsigned cbVal)
2916	{
2917	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
2918	RT_NOREF(pvUser);
2919
2920	DEVAC97_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
2921
2922	/* Get the index of the NABMBAR register. */
2923	const uint32_t uPortIdx = uPort - pThis->IOPortBase[1];
2924
2925	PAC97STREAM pStream = ichac97GetStreamFromIdx(pThis, AC97_PORT2IDX(uPortIdx));
2926	PAC97BMREGS pRegs = NULL;
2927
2928	if (pStream) /* Can be NULL, depending on the index (port). */
2929	pRegs = &pStream->Regs;
2930
2931	int rc = VINF_SUCCESS;
2932	switch (cbVal)
2933	{
2934	case 1:
2935	{
2936	switch (uPortIdx)
2937	{
2938	/*
2939	* Last Valid Index.
2940	*/
2941	case PI_LVI:
2942	case PO_LVI:
2943	case MC_LVI:
2944	{
2945	if ( (pRegs->cr & AC97_CR_RPBM)
2946	&& (pRegs->sr & AC97_SR_DCH))
2947	{
2948	#ifdef IN_RING3
2949	pRegs->sr &= ~(AC97_SR_DCH \| AC97_SR_CELV);
2950	pRegs->civ = pRegs->piv;
2951	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2952
2953	ichac97R3StreamFetchBDLE(pThis, pStream);
2954	#else
2955	rc = VINF_IOM_R3_IOPORT_WRITE;
2956	#endif
2957	}
2958	pRegs->lvi = u32Val % AC97_MAX_BDLE;
2959	Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32Val));
2960	break;
2961	}
2962
2963	/*
2964	* Control Registers.
2965	*/
2966	case PI_CR:
2967	case PO_CR:
2968	case MC_CR:
2969	{
2970	#ifdef IN_RING3
2971	Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32Val, pRegs->cr));
2972	if (u32Val & AC97_CR_RR) /* Busmaster reset. */
2973	{
2974	Log3Func(("[SD%RU8] Reset\n", pStream->u8SD));
2975
2976	/* Make sure that Run/Pause Bus Master bit (RPBM) is cleared (0). */
2977	Assert((pRegs->cr & AC97_CR_RPBM) == 0);
2978
2979	ichac97R3StreamEnable(pThis, pStream, false /* fEnable */);
2980	ichac97R3StreamReset(pThis, pStream);
2981
2982	ichac97StreamUpdateSR(pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */
2983	}
2984	else
2985	{
2986	pRegs->cr = u32Val & AC97_CR_VALID_MASK;
2987
2988	if (!(pRegs->cr & AC97_CR_RPBM))
2989	{
2990	Log3Func(("[SD%RU8] Disable\n", pStream->u8SD));
2991
2992	ichac97R3StreamEnable(pThis, pStream, false /* fEnable */);
2993
2994	pRegs->sr \|= AC97_SR_DCH;
2995	}
2996	else
2997	{
2998	Log3Func(("[SD%RU8] Enable\n", pStream->u8SD));
2999
3000	pRegs->civ = pRegs->piv;
3001	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3002
3003	pRegs->sr &= ~AC97_SR_DCH;
3004
3005	/* Fetch the initial BDLE descriptor. */
3006	ichac97R3StreamFetchBDLE(pThis, pStream);
3007
3008	ichac97R3StreamEnable(pThis, pStream, true /* fEnable */);
3009	}
3010	}
3011	#else /* !IN_RING3 */
3012	rc = VINF_IOM_R3_IOPORT_WRITE;
3013	#endif
3014	break;
3015	}
3016
3017	/*
3018	* Status Registers.
3019	*/
3020	case PI_SR:
3021	case PO_SR:
3022	case MC_SR:
3023	{
3024	pRegs->sr \|= u32Val & ~(AC97_SR_RO_MASK \| AC97_SR_WCLEAR_MASK);
3025	ichac97StreamUpdateSR(pThis, pStream, pRegs->sr & ~(u32Val & AC97_SR_WCLEAR_MASK));
3026	Log3Func(("[SD%RU8] SR <- %#x (sr %#x)\n", pStream->u8SD, u32Val, pRegs->sr));
3027	break;
3028	}
3029
3030	default:
3031	LogRel2(("AC97: Warning: Unimplemented NABMWrite (%u byte) portIdx=%#x <- %#x\n", cbVal, uPortIdx, u32Val));
3032	break;
3033	}
3034	break;
3035	}
3036
3037	case 2:
3038	{
3039	switch (uPortIdx)
3040	{
3041	case PI_SR:
3042	case PO_SR:
3043	case MC_SR:
3044	/* Status Register */
3045	pRegs->sr \|= u32Val & ~(AC97_SR_RO_MASK \| AC97_SR_WCLEAR_MASK);
3046	ichac97StreamUpdateSR(pThis, pStream, pRegs->sr & ~(u32Val & AC97_SR_WCLEAR_MASK));
3047	Log3Func(("[SD%RU8] SR <- %#x (sr %#x)\n", pStream->u8SD, u32Val, pRegs->sr));
3048	break;
3049	default:
3050	LogRel2(("AC97: Warning: Unimplemented NABMWrite (%u byte) portIdx=%#x <- %#x\n", cbVal, uPortIdx, u32Val));
3051	break;
3052	}
3053	break;
3054	}
3055
3056	case 4:
3057	{
3058	switch (uPortIdx)
3059	{
3060	case PI_BDBAR:
3061	case PO_BDBAR:
3062	case MC_BDBAR:
3063	/* Buffer Descriptor list Base Address Register */
3064	pRegs->bdbar = u32Val & ~3;
3065	Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->bdbar));
3066	break;
3067	case AC97_GLOB_CNT:
3068	/* Global Control */
3069	if (u32Val & AC97_GC_WR)
3070	ichac97WarmReset(pThis);
3071	if (u32Val & AC97_GC_CR)
3072	ichac97ColdReset(pThis);
3073	if (!(u32Val & (AC97_GC_WR \| AC97_GC_CR)))
3074	pThis->glob_cnt = u32Val & AC97_GC_VALID_MASK;
3075	Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32Val, pThis->glob_cnt));
3076	break;
3077	case AC97_GLOB_STA:
3078	/* Global Status */
3079	pThis->glob_sta &= ~(u32Val & AC97_GS_WCLEAR_MASK);
3080	pThis->glob_sta \|= (u32Val & ~(AC97_GS_WCLEAR_MASK \| AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK;
3081	Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32Val, pThis->glob_sta));
3082	break;
3083	default:
3084	LogRel2(("AC97: Warning: Unimplemented NABMWrite (%u byte) portIdx=%#x <- %#x\n", cbVal, uPortIdx, u32Val));
3085	break;
3086	}
3087	break;
3088	}
3089
3090	default:
3091	LogRel2(("AC97: Warning: Unimplemented NABMWrite (%u byte) portIdx=%#x <- %#x\n", cbVal, uPortIdx, u32Val));
3092	break;
3093	}
3094
3095	DEVAC97_UNLOCK_BOTH(pThis);
3096
3097	return rc;
3098	}
3099
3100	/**
3101	* Port I/O Handler for IN operations.
3102	*
3103	* @returns VINF_SUCCESS or VINF_EM_*.
3104	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
3105	*
3106	* @param pDevIns The device instance.
3107	* @param pvUser User argument.
3108	* @param uPort Port number used for the IN operation.
3109	* @param pu32Val Where to store the result. This is always a 32-bit
3110	* variable regardless of what @a cbVal might say.
3111	* @param cbVal Number of bytes read.
3112	*/
3113	PDMBOTHCBDECL(int) ichac97IOPortNAMRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32Val, unsigned cbVal)
3114	{
3115	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
3116	RT_NOREF(pvUser);
3117
3118	DEVAC97_LOCK_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
3119
3120	int rc = VINF_SUCCESS;
3121
3122	uint32_t index = uPort - pThis->IOPortBase[0];
3123	Assert(index < 256);
3124
3125	switch (cbVal)
3126	{
3127	case 1:
3128	{
3129	LogRel2(("AC97: Warning: Unimplemented read (%u byte) port=%#x, idx=%RU32\n", cbVal, uPort, index));
3130	pThis->cas = 0;
3131	*pu32Val = UINT32_MAX;
3132	break;
3133	}
3134
3135	case 2:
3136	{
3137	pThis->cas = 0;
3138	*pu32Val = ichac97MixerGet(pThis, index);
3139	break;
3140	}
3141
3142	case 4:
3143	{
3144	LogRel2(("AC97: Warning: Unimplemented read (%u byte) port=%#x, idx=%RU32\n", cbVal, uPort, index));
3145	pThis->cas = 0;
3146	*pu32Val = UINT32_MAX;
3147	break;
3148	}
3149
3150	default:
3151	{
3152	AssertFailed();
3153	rc = VERR_IOM_IOPORT_UNUSED;
3154	}
3155	}
3156
3157	DEVAC97_UNLOCK(pThis);
3158
3159	return rc;
3160	}
3161
3162	/**
3163	* Port I/O Handler for OUT operations.
3164	*
3165	* @returns VINF_SUCCESS or VINF_EM_*.
3166	*
3167	* @param pDevIns The device instance.
3168	* @param pvUser User argument.
3169	* @param uPort Port number used for the OUT operation.
3170	* @param u32Val The value to output.
3171	* @param cbVal The value size in bytes.
3172	* @remarks Caller enters the device critical section.
3173	*/
3174	PDMBOTHCBDECL(int) ichac97IOPortNAMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32Val, unsigned cbVal)
3175	{
3176	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
3177	RT_NOREF(pvUser);
3178
3179	DEVAC97_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
3180
3181	uint32_t uPortIdx = uPort - pThis->IOPortBase[0];
3182	int rc = VINF_SUCCESS;
3183	switch (cbVal)
3184	{
3185	case 1:
3186	{
3187	LogRel2(("AC97: Warning: Unimplemented NAMWrite (%u byte) port=%#x, idx=0x%x <- %#x\n", cbVal, uPort, uPortIdx, u32Val));
3188	pThis->cas = 0;
3189	break;
3190	}
3191
3192	case 2:
3193	{
3194	pThis->cas = 0;
3195	switch (uPortIdx)
3196	{
3197	case AC97_Reset:
3198	#ifdef IN_RING3
3199	ichac97R3Reset(pThis->CTX_SUFF(pDevIns));
3200	#else
3201	rc = VINF_IOM_R3_IOPORT_WRITE;
3202	#endif
3203	break;
3204	case AC97_Powerdown_Ctrl_Stat:
3205	u32Val &= ~0xf;
3206	u32Val \|= ichac97MixerGet(pThis, uPortIdx) & 0xf;
3207	ichac97MixerSet(pThis, uPortIdx, u32Val);
3208	break;
3209	case AC97_Master_Volume_Mute:
3210	if (pThis->uCodecModel == AC97_CODEC_AD1980)
3211	{
3212	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_LOSEL)
3213	break; /* Register controls surround (rear), do nothing. */
3214	}
3215	#ifdef IN_RING3
3216	ichac97R3MixerSetVolume(pThis, uPortIdx, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32Val);
3217	#else
3218	rc = VINF_IOM_R3_IOPORT_WRITE;
3219	#endif
3220	break;
3221	case AC97_Headphone_Volume_Mute:
3222	if (pThis->uCodecModel == AC97_CODEC_AD1980)
3223	{
3224	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3225	{
3226	/* Register controls PCM (front) outputs. */
3227	#ifdef IN_RING3
3228	ichac97R3MixerSetVolume(pThis, uPortIdx, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32Val);
3229	#else
3230	rc = VINF_IOM_R3_IOPORT_WRITE;
3231	#endif
3232	}
3233	}
3234	break;
3235	case AC97_PCM_Out_Volume_Mute:
3236	#ifdef IN_RING3
3237	ichac97R3MixerSetVolume(pThis, uPortIdx, PDMAUDIOMIXERCTL_FRONT, u32Val);
3238	#else
3239	rc = VINF_IOM_R3_IOPORT_WRITE;
3240	#endif
3241	break;
3242	case AC97_Line_In_Volume_Mute:
3243	#ifdef IN_RING3
3244	ichac97R3MixerSetVolume(pThis, uPortIdx, PDMAUDIOMIXERCTL_LINE_IN, u32Val);
3245	#else
3246	rc = VINF_IOM_R3_IOPORT_WRITE;
3247	#endif
3248	break;
3249	case AC97_Record_Select:
3250	#ifdef IN_RING3
3251	ichac97R3MixerRecordSelect(pThis, u32Val);
3252	#else
3253	rc = VINF_IOM_R3_IOPORT_WRITE;
3254	#endif
3255	break;
3256	case AC97_Record_Gain_Mute:
3257	#ifdef IN_RING3
3258	/* Newer Ubuntu guests rely on that when controlling gain and muting
3259	* the recording (capturing) levels. */
3260	ichac97R3MixerSetVolume(pThis, uPortIdx, PDMAUDIOMIXERCTL_LINE_IN, u32Val);
3261	#else
3262	rc = VINF_IOM_R3_IOPORT_WRITE;
3263	#endif
3264	break;
3265	case AC97_Record_Gain_Mic_Mute:
3266	#ifdef IN_RING3
3267	/* Ditto; see note above. */
3268	ichac97R3MixerSetVolume(pThis, uPortIdx, PDMAUDIOMIXERCTL_MIC_IN, u32Val);
3269	#else
3270	rc = VINF_IOM_R3_IOPORT_WRITE;
3271	#endif
3272	break;
3273	case AC97_Vendor_ID1:
3274	case AC97_Vendor_ID2:
3275	LogFunc(("Attempt to write vendor ID to %#x\n", u32Val));
3276	break;
3277	case AC97_Extended_Audio_ID:
3278	LogFunc(("Attempt to write extended audio ID to %#x\n", u32Val));
3279	break;
3280	case AC97_Extended_Audio_Ctrl_Stat:
3281	#ifdef IN_RING3
3282	if (!(u32Val & AC97_EACS_VRA))
3283	{
3284	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 48000);
3285	ichac97R3StreamReOpen(pThis, &pThis->StreamOut);
3286
3287	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 48000);
3288	ichac97R3StreamReOpen(pThis, &pThis->StreamLineIn);
3289	}
3290	else
3291	LogRel2(("AC97: Variable rate audio (VRA) is not supported\n"));
3292
3293	if (!(u32Val & AC97_EACS_VRM))
3294	{
3295	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 48000);
3296	ichac97R3StreamReOpen(pThis, &pThis->StreamMicIn);
3297	}
3298	else
3299	LogRel2(("AC97: Variable rate microphone audio (VRM) is not supported\n"));
3300
3301	LogFunc(("Setting extended audio control to %#x\n", u32Val));
3302	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32Val);
3303	#else
3304	rc = VINF_IOM_R3_IOPORT_WRITE;
3305	#endif
3306	break;
3307	case AC97_PCM_Front_DAC_Rate:
3308	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3309	{
3310	#ifdef IN_RING3
3311	ichac97MixerSet(pThis, uPortIdx, u32Val);
3312	LogFunc(("Set front DAC rate to %RU32\n", u32Val));
3313	ichac97R3StreamReOpen(pThis, &pThis->StreamOut);
3314	#else
3315	rc = VINF_IOM_R3_IOPORT_WRITE;
3316	#endif
3317	}
3318	else
3319	AssertMsgFailed(("Attempt to set front DAC rate to %RU32, but VRA is not set\n", u32Val));
3320	break;
3321	case AC97_MIC_ADC_Rate:
3322	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRM)
3323	{
3324	#ifdef IN_RING3
3325	ichac97MixerSet(pThis, uPortIdx, u32Val);
3326	LogFunc(("Set MIC ADC rate to %RU32\n", u32Val));
3327	ichac97R3StreamReOpen(pThis, &pThis->StreamMicIn);
3328	#else
3329	rc = VINF_IOM_R3_IOPORT_WRITE;
3330	#endif
3331	}
3332	else
3333	AssertMsgFailed(("Attempt to set MIC ADC rate to %RU32, but VRM is not set\n", u32Val));
3334	break;
3335	case AC97_PCM_LR_ADC_Rate:
3336	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3337	{
3338	#ifdef IN_RING3
3339	ichac97MixerSet(pThis, uPortIdx, u32Val);
3340	LogFunc(("Set front LR ADC rate to %RU32\n", u32Val));
3341	ichac97R3StreamReOpen(pThis, &pThis->StreamLineIn);
3342	#else
3343	rc = VINF_IOM_R3_IOPORT_WRITE;
3344	#endif
3345	}
3346	else
3347	AssertMsgFailed(("Attempt to set LR ADC rate to %RU32, but VRA is not set\n", u32Val));
3348	break;
3349	default:
3350	LogRel2(("AC97: Warning: Unimplemented NAMWrite (%u byte) port=%#x, idx=0x%x <- %#x\n", cbVal, uPort, uPortIdx, u32Val));
3351	ichac97MixerSet(pThis, uPortIdx, u32Val);
3352	break;
3353	}
3354	break;
3355	}
3356
3357	case 4:
3358	{
3359	LogRel2(("AC97: Warning: Unimplemented NAMWrite (%u byte) port=%#x, idx=0x%x <- %#x\n", cbVal, uPort, uPortIdx, u32Val));
3360	pThis->cas = 0;
3361	break;
3362	}
3363
3364	default:
3365	AssertMsgFailed(("Unhandled NAMWrite port=%#x, cbVal=%u u32Val=%#x\n", uPort, cbVal, u32Val));
3366	break;
3367	}
3368
3369	DEVAC97_UNLOCK_BOTH(pThis);
3370
3371	return rc;
3372	}
3373
3374	#ifdef IN_RING3
3375
3376	/**
3377	* @callback_method_impl{FNPCIIOREGIONMAP}
3378	*/
3379	static DECLCALLBACK(int) ichac97R3IOPortMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3380	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
3381	{
3382	RT_NOREF(cb, enmType);
3383
3384	Assert(enmType == PCI_ADDRESS_SPACE_IO);
3385	Assert(cb >= 0x20);
3386
3387	if (iRegion > 1) /* We support 2 regions max. at the moment. */
3388	return VERR_INVALID_PARAMETER;
3389
3390	PAC97STATE pThis = RT_FROM_MEMBER(pPciDev, AC97STATE, PciDev);
3391	RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3392
3393	int rc;
3394	if (iRegion == 0)
3395	{
3396	rc = PDMDevHlpIOPortRegister(pDevIns, Port, 256, NULL, ichac97IOPortNAMWrite, ichac97IOPortNAMRead,
3397	NULL, NULL, "ICHAC97 NAM");
3398	AssertRCReturn(rc, rc);
3399	if (pThis->fRZEnabled)
3400	{
3401	rc = PDMDevHlpIOPortRegisterR0(pDevIns, Port, 256, NIL_RTR0PTR, "ichac97IOPortNAMWrite", "ichac97IOPortNAMRead",
3402	NULL, NULL, "ICHAC97 NAM");
3403	AssertRCReturn(rc, rc);
3404	rc = PDMDevHlpIOPortRegisterRC(pDevIns, Port, 256, NIL_RTRCPTR, "ichac97IOPortNAMWrite", "ichac97IOPortNAMRead",
3405	NULL, NULL, "ICHAC97 NAM");
3406	AssertRCReturn(rc, rc);
3407	}
3408	}
3409	else
3410	{
3411	rc = PDMDevHlpIOPortRegister(pDevIns, Port, 64, NULL, ichac97IOPortNABMWrite, ichac97IOPortNABMRead,
3412	NULL, NULL, "ICHAC97 NABM");
3413	AssertRCReturn(rc, rc);
3414	if (pThis->fRZEnabled)
3415	{
3416	rc = PDMDevHlpIOPortRegisterR0(pDevIns, Port, 64, NIL_RTR0PTR, "ichac97IOPortNABMWrite", "ichac97IOPortNABMRead",
3417	NULL, NULL, "ICHAC97 NABM");
3418	AssertRCReturn(rc, rc);
3419	rc = PDMDevHlpIOPortRegisterRC(pDevIns, Port, 64, NIL_RTRCPTR, "ichac97IOPortNABMWrite", "ichac97IOPortNABMRead",
3420	NULL, NULL, "ICHAC97 NABM");
3421	AssertRCReturn(rc, rc);
3422
3423	}
3424	}
3425
3426	pThis->IOPortBase[iRegion] = Port;
3427	return VINF_SUCCESS;
3428	}
3429
3430
3431	/**
3432	* Saves (serializes) an AC'97 stream using SSM.
3433	*
3434	* @returns IPRT status code.
3435	* @param pDevIns Device instance.
3436	* @param pSSM Saved state manager (SSM) handle to use.
3437	* @param pStream AC'97 stream to save.
3438	*/
3439	static int ichac97R3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3440	{
3441	RT_NOREF(pDevIns);
3442	PAC97BMREGS pRegs = &pStream->Regs;
3443
3444	SSMR3PutU32(pSSM, pRegs->bdbar);
3445	SSMR3PutU8( pSSM, pRegs->civ);
3446	SSMR3PutU8( pSSM, pRegs->lvi);
3447	SSMR3PutU16(pSSM, pRegs->sr);
3448	SSMR3PutU16(pSSM, pRegs->picb);
3449	SSMR3PutU8( pSSM, pRegs->piv);
3450	SSMR3PutU8( pSSM, pRegs->cr);
3451	SSMR3PutS32(pSSM, pRegs->bd_valid);
3452	SSMR3PutU32(pSSM, pRegs->bd.addr);
3453	SSMR3PutU32(pSSM, pRegs->bd.ctl_len);
3454
3455	return VINF_SUCCESS;
3456	}
3457
3458	/**
3459	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3460	*/
3461	static DECLCALLBACK(int) ichac97R3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3462	{
3463	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
3464
3465	LogFlowFuncEnter();
3466
3467	SSMR3PutU32(pSSM, pThis->glob_cnt);
3468	SSMR3PutU32(pSSM, pThis->glob_sta);
3469	SSMR3PutU32(pSSM, pThis->cas);
3470
3471	/** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
3472	/* Note: The order the streams are saved here is critical, so don't touch. */
3473	int rc2 = ichac97R3SaveStream(pDevIns, pSSM, &pThis->StreamLineIn);
3474	AssertRC(rc2);
3475	rc2 = ichac97R3SaveStream(pDevIns, pSSM, &pThis->StreamOut);
3476	AssertRC(rc2);
3477	rc2 = ichac97R3SaveStream(pDevIns, pSSM, &pThis->StreamMicIn);
3478	AssertRC(rc2);
3479
3480	SSMR3PutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3481
3482	uint8_t active[AC97SOUNDSOURCE_END_INDEX];
3483
3484	active[AC97SOUNDSOURCE_PI_INDEX] = ichac97R3StreamIsEnabled(pThis, &pThis->StreamLineIn) ? 1 : 0;
3485	active[AC97SOUNDSOURCE_PO_INDEX] = ichac97R3StreamIsEnabled(pThis, &pThis->StreamOut) ? 1 : 0;
3486	active[AC97SOUNDSOURCE_MC_INDEX] = ichac97R3StreamIsEnabled(pThis, &pThis->StreamMicIn) ? 1 : 0;
3487
3488	SSMR3PutMem(pSSM, active, sizeof(active));
3489
3490	LogFlowFuncLeaveRC(VINF_SUCCESS);
3491	return VINF_SUCCESS;
3492	}
3493
3494	/**
3495	* Loads an AC'97 stream from SSM.
3496	*
3497	* @returns IPRT status code.
3498	* @param pSSM Saved state manager (SSM) handle to use.
3499	* @param pStream AC'97 stream to load.
3500	*/
3501	static int ichac97R3LoadStream(PSSMHANDLE pSSM, PAC97STREAM pStream)
3502	{
3503	PAC97BMREGS pRegs = &pStream->Regs;
3504
3505	SSMR3GetU32(pSSM, &pRegs->bdbar);
3506	SSMR3GetU8( pSSM, &pRegs->civ);
3507	SSMR3GetU8( pSSM, &pRegs->lvi);
3508	SSMR3GetU16(pSSM, &pRegs->sr);
3509	SSMR3GetU16(pSSM, &pRegs->picb);
3510	SSMR3GetU8( pSSM, &pRegs->piv);
3511	SSMR3GetU8( pSSM, &pRegs->cr);
3512	SSMR3GetS32(pSSM, &pRegs->bd_valid);
3513	SSMR3GetU32(pSSM, &pRegs->bd.addr);
3514	return SSMR3GetU32(pSSM, &pRegs->bd.ctl_len);
3515	}
3516
3517	/**
3518	* @callback_method_impl{FNSSMDEVLOADEXEC}
3519	*/
3520	static DECLCALLBACK(int) ichac97R3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3521	{
3522	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
3523
3524	LogRel2(("ichac97LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3525
3526	AssertMsgReturn (uVersion == AC97_SSM_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3527	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3528
3529	SSMR3GetU32(pSSM, &pThis->glob_cnt);
3530	SSMR3GetU32(pSSM, &pThis->glob_sta);
3531	SSMR3GetU32(pSSM, &pThis->cas);
3532
3533	/** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
3534	/* Note: The order the streams are loaded here is critical, so don't touch. */
3535	int rc2 = ichac97R3LoadStream(pSSM, &pThis->StreamLineIn);
3536	AssertRCReturn(rc2, rc2);
3537	rc2 = ichac97R3LoadStream(pSSM, &pThis->StreamOut);
3538	AssertRCReturn(rc2, rc2);
3539	rc2 = ichac97R3LoadStream(pSSM, &pThis->StreamMicIn);
3540	AssertRCReturn(rc2, rc2);
3541
3542	SSMR3GetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3543
3544	/** @todo r=andy Stream IDs are hardcoded to certain streams. */
3545	uint8_t uaStrmsActive[AC97SOUNDSOURCE_END_INDEX];
3546	rc2 = SSMR3GetMem(pSSM, uaStrmsActive, sizeof(uaStrmsActive));
3547	AssertRCReturn(rc2, rc2);
3548
3549	ichac97R3MixerRecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
3550	# define V_(a, b) ichac97R3MixerSetVolume(pThis, a, b, ichac97MixerGet(pThis, a))
3551	V_(AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER);
3552	V_(AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT);
3553	V_(AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN);
3554	V_(AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN);
3555	# undef V_
3556	if (pThis->uCodecModel == AC97_CODEC_AD1980)
3557	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3558	ichac97R3MixerSetVolume(pThis, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3559	ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
3560
3561	/** @todo r=andy Stream IDs are hardcoded to certain streams. */
3562	rc2 = ichac97R3StreamEnable(pThis, &pThis->StreamLineIn, RT_BOOL(uaStrmsActive[AC97SOUNDSOURCE_PI_INDEX]));
3563	if (RT_SUCCESS(rc2))
3564	rc2 = ichac97R3StreamEnable(pThis, &pThis->StreamMicIn, RT_BOOL(uaStrmsActive[AC97SOUNDSOURCE_MC_INDEX]));
3565	if (RT_SUCCESS(rc2))
3566	rc2 = ichac97R3StreamEnable(pThis, &pThis->StreamOut, RT_BOOL(uaStrmsActive[AC97SOUNDSOURCE_PO_INDEX]));
3567
3568	pThis->bup_flag = 0;
3569	pThis->last_samp = 0;
3570
3571	return VINF_SUCCESS;
3572	}
3573
3574
3575	/**
3576	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3577	*/
3578	static DECLCALLBACK(void ) ichac97R3QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
3579	{
3580	PAC97STATE pThis = RT_FROM_MEMBER(pInterface, AC97STATE, IBase);
3581	Assert(&pThis->IBase == pInterface);
3582
3583	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3584	return NULL;
3585	}
3586
3587
3588	/**
3589	* Powers off the device.
3590	*
3591	* @param pDevIns Device instance to power off.
3592	*/
3593	static DECLCALLBACK(void) ichac97R3PowerOff(PPDMDEVINS pDevIns)
3594	{
3595	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
3596
3597	LogRel2(("AC97: Powering off ...\n"));
3598
3599	/* Note: Involves mixer stream / sink destruction, so also do this here
3600	* instead of in ichac97R3Destruct(). */
3601	ichac97R3StreamsDestroy(pThis);
3602
3603	/**
3604	* Note: Destroy the mixer while powering off and not in ichac97R3Destruct,
3605	* giving the mixer the chance to release any references held to
3606	* PDM audio streams it maintains.
3607	*/
3608	if (pThis->pMixer)
3609	{
3610	AudioMixerDestroy(pThis->pMixer);
3611	pThis->pMixer = NULL;
3612	}
3613	}
3614
3615
3616	/**
3617	* @interface_method_impl{PDMDEVREG,pfnReset}
3618	*
3619	* @remarks The original sources didn't install a reset handler, but it seems to
3620	* make sense to me so we'll do it.
3621	*/
3622	static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns)
3623	{
3624	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
3625
3626	LogRel(("AC97: Reset\n"));
3627
3628	/*
3629	* Reset the mixer too. The Windows XP driver seems to rely on
3630	* this. At least it wants to read the vendor id before it resets
3631	* the codec manually.
3632	*/
3633	ichac97R3MixerReset(pThis);
3634
3635	/*
3636	* Reset all streams.
3637	*/
3638	ichac97R3StreamEnable(pThis, &pThis->StreamLineIn, false /* fEnable */);
3639	ichac97R3StreamReset(pThis, &pThis->StreamLineIn);
3640
3641	ichac97R3StreamEnable(pThis, &pThis->StreamMicIn, false /* fEnable */);
3642	ichac97R3StreamReset(pThis, &pThis->StreamMicIn);
3643
3644	ichac97R3StreamEnable(pThis, &pThis->StreamOut, false /* fEnable */);
3645	ichac97R3StreamReset(pThis, &pThis->StreamOut);
3646
3647	/*
3648	* Reset mixer sinks.
3649	*
3650	* Do the reset here instead of in ichac97R3StreamReset();
3651	* the mixer sink(s) might still have data to be processed when an audio stream gets reset.
3652	*/
3653	AudioMixerSinkReset(pThis->pSinkLineIn);
3654	AudioMixerSinkReset(pThis->pSinkMicIn);
3655	AudioMixerSinkReset(pThis->pSinkOut);
3656
3657	# ifndef VBOX_WITH_AUDIO_AC97_CALLBACKS
3658	/*
3659	* Stop the timer, if any.
3660	*/
3661	ichac97R3TimerStop(pThis);
3662
3663	pThis->cStreamsActive = 0;
3664	# endif
3665	}
3666
3667
3668	/**
3669	* Attach command, internal version.
3670	*
3671	* This is called to let the device attach to a driver for a specified LUN
3672	* during runtime. This is not called during VM construction, the device
3673	* constructor has to attach to all the available drivers.
3674	*
3675	* @returns VBox status code.
3676	* @param pThis AC'97 state.
3677	* @param uLUN The logical unit which is being detached.
3678	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3679	* @param ppDrv Attached driver instance on success. Optional.
3680	*/
3681	static int ichac97R3AttachInternal(PAC97STATE pThis, unsigned uLUN, uint32_t fFlags, PAC97DRIVER *ppDrv)
3682	{
3683	RT_NOREF(fFlags);
3684
3685	/*
3686	* Attach driver.
3687	*/
3688	char *pszDesc;
3689	if (RTStrAPrintf(&pszDesc, "Audio driver port (AC'97) for LUN #%u", uLUN) <= 0)
3690	AssertLogRelFailedReturn(VERR_NO_MEMORY);
3691
3692	PPDMIBASE pDrvBase;
3693	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, uLUN,
3694	&pThis->IBase, &pDrvBase, pszDesc);
3695	if (RT_SUCCESS(rc))
3696	{
3697	PAC97DRIVER pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
3698	if (pDrv)
3699	{
3700	pDrv->pDrvBase = pDrvBase;
3701	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
3702	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN #%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
3703	pDrv->pAC97State = pThis;
3704	pDrv->uLUN = uLUN;
3705
3706	/*
3707	* For now we always set the driver at LUN 0 as our primary
3708	* host backend. This might change in the future.
3709	*/
3710	if (pDrv->uLUN == 0)
3711	pDrv->fFlags \|= PDMAUDIODRVFLAGS_PRIMARY;
3712
3713	LogFunc(("LUN#%RU8: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->fFlags));
3714
3715	/* Attach to driver list if not attached yet. */
3716	if (!pDrv->fAttached)
3717	{
3718	RTListAppend(&pThis->lstDrv, &pDrv->Node);
3719	pDrv->fAttached = true;
3720	}
3721
3722	if (ppDrv)
3723	*ppDrv = pDrv;
3724	}
3725	else
3726	rc = VERR_NO_MEMORY;
3727	}
3728	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3729	LogFunc(("No attached driver for LUN #%u\n", uLUN));
3730
3731	if (RT_FAILURE(rc))
3732	{
3733	/* Only free this string on failure;
3734	* must remain valid for the live of the driver instance. */
3735	RTStrFree(pszDesc);
3736	}
3737
3738	LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
3739	return rc;
3740	}
3741
3742	/**
3743	* Detach command, internal version.
3744	*
3745	* This is called to let the device detach from a driver for a specified LUN
3746	* during runtime.
3747	*
3748	* @returns VBox status code.
3749	* @param pThis AC'97 state.
3750	* @param pDrv Driver to detach device from.
3751	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3752	*/
3753	static int ichac97R3DetachInternal(PAC97STATE pThis, PAC97DRIVER pDrv, uint32_t fFlags)
3754	{
3755	RT_NOREF(fFlags);
3756
3757	AudioMixerSinkRemoveStream(pThis->pSinkMicIn, pDrv->MicIn.pMixStrm);
3758	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm);
3759	pDrv->MicIn.pMixStrm = NULL;
3760
3761	AudioMixerSinkRemoveStream(pThis->pSinkLineIn, pDrv->LineIn.pMixStrm);
3762	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm);
3763	pDrv->LineIn.pMixStrm = NULL;
3764
3765	AudioMixerSinkRemoveStream(pThis->pSinkOut, pDrv->Out.pMixStrm);
3766	AudioMixerStreamDestroy(pDrv->Out.pMixStrm);
3767	pDrv->Out.pMixStrm = NULL;
3768
3769	RTListNodeRemove(&pDrv->Node);
3770
3771	LogFunc(("uLUN=%u, fFlags=0x%x\n", pDrv->uLUN, fFlags));
3772	return VINF_SUCCESS;
3773	}
3774
3775	/**
3776	* @interface_method_impl{PDMDEVREG,pfnAttach}
3777	*/
3778	static DECLCALLBACK(int) ichac97R3Attach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
3779	{
3780	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
3781
3782	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
3783
3784	DEVAC97_LOCK(pThis);
3785
3786	PAC97DRIVER pDrv;
3787	int rc2 = ichac97R3AttachInternal(pThis, uLUN, fFlags, &pDrv);
3788	if (RT_SUCCESS(rc2))
3789	{
3790	if (DrvAudioHlpStreamCfgIsValid(&pThis->StreamLineIn.State.Cfg))
3791	ichac97R3MixerAddDrvStream(pThis, pThis->pSinkLineIn, &pThis->StreamLineIn.State.Cfg, pDrv);
3792
3793	if (DrvAudioHlpStreamCfgIsValid(&pThis->StreamMicIn.State.Cfg))
3794	ichac97R3MixerAddDrvStream(pThis, pThis->pSinkMicIn, &pThis->StreamMicIn.State.Cfg, pDrv);
3795
3796	if (DrvAudioHlpStreamCfgIsValid(&pThis->StreamOut.State.Cfg))
3797	ichac97R3MixerAddDrvStream(pThis, pThis->pSinkOut, &pThis->StreamOut.State.Cfg, pDrv);
3798	}
3799
3800	DEVAC97_UNLOCK(pThis);
3801
3802	return VINF_SUCCESS;
3803	}
3804
3805	/**
3806	* @interface_method_impl{PDMDEVREG,pfnDetach}
3807	*/
3808	static DECLCALLBACK(void) ichac97R3Detach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
3809	{
3810	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
3811
3812	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
3813
3814	DEVAC97_LOCK(pThis);
3815
3816	PAC97DRIVER pDrv, pDrvNext;
3817	RTListForEachSafe(&pThis->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
3818	{
3819	if (pDrv->uLUN == uLUN)
3820	{
3821	int rc2 = ichac97R3DetachInternal(pThis, pDrv, fFlags);
3822	if (RT_SUCCESS(rc2))
3823	{
3824	RTMemFree(pDrv);
3825	pDrv = NULL;
3826	}
3827
3828	break;
3829	}
3830	}
3831
3832	DEVAC97_UNLOCK(pThis);
3833	}
3834
3835	/**
3836	* Re-attaches (replaces) a driver with a new driver.
3837	*
3838	* @returns VBox status code.
3839	* @param pThis Device instance.
3840	* @param pDrv Driver instance used for attaching to.
3841	* If NULL is specified, a new driver will be created and appended
3842	* to the driver list.
3843	* @param uLUN The logical unit which is being re-detached.
3844	* @param pszDriver New driver name to attach.
3845	*/
3846	static int ichac97R3ReattachInternal(PAC97STATE pThis, PAC97DRIVER pDrv, uint8_t uLUN, const char *pszDriver)
3847	{
3848	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3849	AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
3850
3851	int rc;
3852
3853	if (pDrv)
3854	{
3855	rc = ichac97R3DetachInternal(pThis, pDrv, 0 /* fFlags */);
3856	if (RT_SUCCESS(rc))
3857	rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
3858
3859	if (RT_FAILURE(rc))
3860	return rc;
3861
3862	pDrv = NULL;
3863	}
3864
3865	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3866	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
3867	PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/ichac97/0/");
3868
3869	/* Remove LUN branch. */
3870	CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
3871
3872	# define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
3873
3874	do
3875	{
3876	PCFGMNODE pLunL0;
3877	rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
3878	rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
3879	rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
3880
3881	PCFGMNODE pLunL1, pLunL2;
3882	rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
3883	rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
3884	rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
3885
3886	rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
3887
3888	} while (0);
3889
3890	if (RT_SUCCESS(rc))
3891	rc = ichac97R3AttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
3892
3893	LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
3894
3895	# undef RC_CHECK
3896
3897	return rc;
3898	}
3899
3900	/**
3901	* @interface_method_impl{PDMDEVREG,pfnRelocate}
3902	*/
3903	static DECLCALLBACK(void) ichac97R3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
3904	{
3905	NOREF(offDelta);
3906	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
3907	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3908	# ifndef VBOX_WITH_AUDIO_AC97_CALLBACKS
3909	pThis->pTimerRC = TMTimerRCPtr(pThis->pTimerR3);
3910	# endif
3911	}
3912
3913	/**
3914	* @interface_method_impl{PDMDEVREG,pfnDestruct}
3915	*/
3916	static DECLCALLBACK(int) ichac97R3Destruct(PPDMDEVINS pDevIns)
3917	{
3918	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
3919	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
3920
3921	LogFlowFuncEnter();
3922
3923	PAC97DRIVER pDrv, pDrvNext;
3924	RTListForEachSafe(&pThis->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
3925	{
3926	RTListNodeRemove(&pDrv->Node);
3927	RTMemFree(pDrv);
3928	}
3929
3930	/* Sanity. */
3931	Assert(RTListIsEmpty(&pThis->lstDrv));
3932
3933	return VINF_SUCCESS;
3934	}
3935
3936	/**
3937	* @interface_method_impl{PDMDEVREG,pfnConstruct}
3938	*/
3939	static DECLCALLBACK(int) ichac97R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3940	{
3941	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
3942	PAC97STATE pThis = PDMINS_2_DATA(pDevIns, PAC97STATE);
3943	Assert(iInstance == 0); RT_NOREF(iInstance);
3944
3945	/*
3946	* Initialize data so we can run the destructor without scewing up.
3947	*/
3948	pThis->pDevInsR3 = pDevIns;
3949	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3950	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3951	pThis->IBase.pfnQueryInterface = ichac97R3QueryInterface;
3952	RTListInit(&pThis->lstDrv);
3953
3954	/*
3955	* Validations.
3956	*/
3957	if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
3958	"Codec\0"
3959	"TimerHz\0"
3960	"DebugEnabled\0"
3961	"DebugPathOut\0"))
3962	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3963	N_("Invalid configuration for the AC'97 device"));
3964
3965	/*
3966	* Read config data.
3967	*/
3968	int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
3969	if (RT_FAILURE(rc))
3970	return PDMDEV_SET_ERROR(pDevIns, rc,
3971	N_("AC'97 configuration error: failed to read RCEnabled as boolean"));
3972
3973	char szCodec[20];
3974	rc = CFGMR3QueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
3975	if (RT_FAILURE(rc))
3976	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3977	N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
3978
3979	# ifndef VBOX_WITH_AUDIO_AC97_CALLBACKS
3980	uint16_t uTimerHz;
3981	rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, AC97_TIMER_HZ /* Default value, if not set. */);
3982	if (RT_FAILURE(rc))
3983	return PDMDEV_SET_ERROR(pDevIns, rc,
3984	N_("AC'97 configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
3985
3986	if (uTimerHz != AC97_TIMER_HZ)
3987	LogRel(("AC97: Using custom device timer rate (%RU16Hz)\n", uTimerHz));
3988	# endif
3989
3990	rc = CFGMR3QueryBoolDef(pCfg, "DebugEnabled", &pThis->Dbg.fEnabled, false);
3991	if (RT_FAILURE(rc))
3992	return PDMDEV_SET_ERROR(pDevIns, rc,
3993	N_("AC97 configuration error: failed to read debugging enabled flag as boolean"));
3994
3995	rc = CFGMR3QueryStringDef(pCfg, "DebugPathOut", pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath),
3996	VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
3997	if (RT_FAILURE(rc))
3998	return PDMDEV_SET_ERROR(pDevIns, rc,
3999	N_("AC97 configuration error: failed to read debugging output path flag as string"));
4000
4001	if (!strlen(pThis->Dbg.szOutPath))
4002	RTStrPrintf(pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath), VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4003
4004	if (pThis->Dbg.fEnabled)
4005	LogRel2(("AC97: Debug output will be saved to '%s'\n", pThis->Dbg.szOutPath));
4006
4007	/*
4008	* The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
4009	* in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
4010	* 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
4011	*/
4012	if (!strcmp(szCodec, "STAC9700"))
4013	pThis->uCodecModel = AC97_CODEC_STAC9700;
4014	else if (!strcmp(szCodec, "AD1980"))
4015	pThis->uCodecModel = AC97_CODEC_AD1980;
4016	else if (!strcmp(szCodec, "AD1981B"))
4017	pThis->uCodecModel = AC97_CODEC_AD1981B;
4018	else
4019	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
4020	N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"), szCodec);
4021
4022	/*
4023	* Use an own critical section for the device instead of the default
4024	* one provided by PDM. This allows fine-grained locking in combination
4025	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4026	*/
4027	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "AC'97");
4028	AssertRCReturn(rc, rc);
4029
4030	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4031	AssertRCReturn(rc, rc);
4032
4033	/*
4034	* Initialize data (most of it anyway).
4035	*/
4036	/* PCI Device */
4037	PCIDevSetVendorId (&pThis->PciDev, 0x8086); /* 00 ro - intel. */ Assert(pThis->PciDev.abConfig[0x00] == 0x86); Assert(pThis->PciDev.abConfig[0x01] == 0x80);
4038	PCIDevSetDeviceId (&pThis->PciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pThis->PciDev.abConfig[0x02] == 0x15); Assert(pThis->PciDev.abConfig[0x03] == 0x24);
4039	PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pThis->PciDev.abConfig[0x04] == 0x00); Assert(pThis->PciDev.abConfig[0x05] == 0x00);
4040	PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM \| VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pThis->PciDev.abConfig[0x06] == 0x80); Assert(pThis->PciDev.abConfig[0x07] == 0x02);
4041	PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */ Assert(pThis->PciDev.abConfig[0x08] == 0x01);
4042	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */ Assert(pThis->PciDev.abConfig[0x09] == 0x00);
4043	PCIDevSetClassSub (&pThis->PciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pThis->PciDev.abConfig[0x0a] == 0x01);
4044	PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia.*/Assert(pThis->PciDev.abConfig[0x0b] == 0x04);
4045	PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */ Assert(pThis->PciDev.abConfig[0x0e] == 0x00);
4046	PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - nambar - native audio mixer base. */
4047	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pThis->PciDev.abConfig[0x10] == 0x01); Assert(pThis->PciDev.abConfig[0x11] == 0x00); Assert(pThis->PciDev.abConfig[0x12] == 0x00); Assert(pThis->PciDev.abConfig[0x13] == 0x00);
4048	PCIDevSetBaseAddress (&pThis->PciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
4049	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pThis->PciDev.abConfig[0x14] == 0x01); Assert(pThis->PciDev.abConfig[0x15] == 0x00); Assert(pThis->PciDev.abConfig[0x16] == 0x00); Assert(pThis->PciDev.abConfig[0x17] == 0x00);
4050	PCIDevSetInterruptLine(&pThis->PciDev, 0x00); /* 3c rw. */ Assert(pThis->PciDev.abConfig[0x3c] == 0x00);
4051	PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */ Assert(pThis->PciDev.abConfig[0x3d] == 0x01);
4052
4053	if (pThis->uCodecModel == AC97_CODEC_AD1980)
4054	{
4055	PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x1028); /* 2c ro - Dell.) */
4056	PCIDevSetSubSystemId (&pThis->PciDev, 0x0177); /* 2e ro. */
4057	}
4058	else if (pThis->uCodecModel == AC97_CODEC_AD1981B)
4059	{
4060	PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x1028); /* 2c ro - Dell.) */
4061	PCIDevSetSubSystemId (&pThis->PciDev, 0x01ad); /* 2e ro. */
4062	}
4063	else
4064	{
4065	PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x8086); /* 2c ro - Intel.) */
4066	PCIDevSetSubSystemId (&pThis->PciDev, 0x0000); /* 2e ro. */
4067	}
4068
4069	/*
4070	* Register the PCI device, it's I/O regions, the timer and the
4071	* saved state item.
4072	*/
4073	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
4074	if (RT_FAILURE(rc))
4075	return rc;
4076
4077	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 256, PCI_ADDRESS_SPACE_IO, ichac97R3IOPortMap);
4078	if (RT_FAILURE(rc))
4079	return rc;
4080
4081	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 64, PCI_ADDRESS_SPACE_IO, ichac97R3IOPortMap);
4082	if (RT_FAILURE(rc))
4083	return rc;
4084
4085	rc = PDMDevHlpSSMRegister(pDevIns, AC97_SSM_VERSION, sizeof(*pThis), ichac97R3SaveExec, ichac97R3LoadExec);
4086	if (RT_FAILURE(rc))
4087	return rc;
4088
4089	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
4090	LogRel(("AC97: Asynchronous I/O enabled\n"));
4091	# endif
4092
4093	/*
4094	* Attach driver.
4095	*/
4096	uint8_t uLUN;
4097	for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
4098	{
4099	LogFunc(("Trying to attach driver for LUN #%RU8 ...\n", uLUN));
4100	rc = ichac97R3AttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
4101	if (RT_FAILURE(rc))
4102	{
4103	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4104	rc = VINF_SUCCESS;
4105	else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
4106	{
4107	ichac97R3ReattachInternal(pThis, NULL /* pDrv */, uLUN, "NullAudio");
4108	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4109	N_("Host audio backend initialization has failed. Selecting the NULL audio backend "
4110	"with the consequence that no sound is audible"));
4111	/* Attaching to the NULL audio backend will never fail. */
4112	rc = VINF_SUCCESS;
4113	}
4114	break;
4115	}
4116	}
4117
4118	LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
4119
4120	if (RT_SUCCESS(rc))
4121	{
4122	rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThis->pMixer);
4123	if (RT_SUCCESS(rc))
4124	{
4125	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In", AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
4126	AssertRC(rc);
4127	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In", AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
4128	AssertRC(rc);
4129	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output", AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOut);
4130	AssertRC(rc);
4131	}
4132	}
4133
4134	if (RT_SUCCESS(rc))
4135	{
4136	/*
4137	* Create all hardware streams.
4138	*/
4139	rc = ichac97R3StreamCreate(pThis, &pThis->StreamLineIn, AC97SOUNDSOURCE_PI_INDEX);
4140	if (RT_SUCCESS(rc))
4141	{
4142	rc = ichac97R3StreamCreate(pThis, &pThis->StreamMicIn, AC97SOUNDSOURCE_MC_INDEX);
4143	if (RT_SUCCESS(rc))
4144	rc = ichac97R3StreamCreate(pThis, &pThis->StreamOut, AC97SOUNDSOURCE_PO_INDEX);
4145	}
4146
4147	# ifdef VBOX_WITH_AUDIO_AC97_ONETIME_INIT
4148	PAC97DRIVER pDrv;
4149	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
4150	{
4151	/*
4152	* Only primary drivers are critical for the VM to run. Everything else
4153	* might not worth showing an own error message box in the GUI.
4154	*/
4155	if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
4156	continue;
4157
4158	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
4159	AssertPtr(pCon);
4160
4161	bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
4162	bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
4163	bool fValidOut = AudioMixerStreamIsValid(pDrv->Out.pMixStrm);
4164
4165	if ( !fValidLineIn
4166	&& !fValidMicIn
4167	&& !fValidOut)
4168	{
4169	LogRel(("AC97: Falling back to NULL backend (no sound audible)\n"));
4170
4171	ichac97R3Reset(pDevIns);
4172	ichac97R3ReattachInternal(pThis, pDrv, pDrv->uLUN, "NullAudio");
4173
4174	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4175	N_("No audio devices could be opened. Selecting the NULL audio backend "
4176	"with the consequence that no sound is audible"));
4177	}
4178	else
4179	{
4180	bool fWarn = false;
4181
4182	PDMAUDIOBACKENDCFG backendCfg;
4183	int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
4184	if (RT_SUCCESS(rc2))
4185	{
4186	if (backendCfg.cMaxStreamsIn)
4187	{
4188	/* If the audio backend supports two or more input streams at once,
4189	* warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
4190	if (backendCfg.cMaxStreamsIn >= 2)
4191	fWarn = !fValidLineIn \|\| !fValidMicIn;
4192	/* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
4193	* not ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
4194	* One of the two simply is not in use then. */
4195	else if (backendCfg.cMaxStreamsIn == 1)
4196	fWarn = !fValidLineIn && !fValidMicIn;
4197	/* Don't warn if our backend is not able of supporting any input streams at all. */
4198	}
4199
4200	if ( !fWarn
4201	&& backendCfg.cMaxStreamsOut)
4202	{
4203	fWarn = !fValidOut;
4204	}
4205	}
4206	else
4207	{
4208	LogRel(("AC97: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
4209	fWarn = true;
4210	}
4211
4212	if (fWarn)
4213	{
4214	char szMissingStreams[255] = "";
4215	size_t len = 0;
4216	if (!fValidLineIn)
4217	{
4218	LogRel(("AC97: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
4219	len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
4220	}
4221	if (!fValidMicIn)
4222	{
4223	LogRel(("AC97: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
4224	len += RTStrPrintf(szMissingStreams + len,
4225	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
4226	}
4227	if (!fValidOut)
4228	{
4229	LogRel(("AC97: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
4230	len += RTStrPrintf(szMissingStreams + len,
4231	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
4232	}
4233
4234	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4235	N_("Some AC'97 audio streams (%s) could not be opened. Guest applications generating audio "
4236	"output or depending on audio input may hang. Make sure your host audio device "
4237	"is working properly. Check the logfile for error messages of the audio "
4238	"subsystem"), szMissingStreams);
4239	}
4240	}
4241	}
4242	# endif /* VBOX_WITH_AUDIO_AC97_ONETIME_INIT */
4243	}
4244
4245	if (RT_SUCCESS(rc))
4246	ichac97R3Reset(pDevIns);
4247
4248	# ifndef VBOX_WITH_AUDIO_AC97_CALLBACKS
4249	if (RT_SUCCESS(rc))
4250	{
4251	/* Create the emulation timer.
4252	*
4253	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's AC'97 driver
4254	* relies on exact (virtual) DMA timing and uses DMA Position Buffers
4255	* instead of the LPIB registers.
4256	*/
4257	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, ichac97R3Timer, pThis,
4258	TMTIMER_FLAGS_NO_CRIT_SECT, "AC'97 Timer", &pThis->pTimerR3);
4259	AssertRCReturn(rc, rc);
4260	pThis->pTimerR0 = TMTimerR0Ptr(pThis->pTimerR3);
4261	pThis->pTimerRC = TMTimerRCPtr(pThis->pTimerR3);
4262
4263	/* Use our own critcal section for the device timer.
4264	* That way we can control more fine-grained when to lock what. */
4265	rc = TMR3TimerSetCritSect(pThis->pTimerR3, &pThis->CritSect);
4266	AssertRCReturn(rc, rc);
4267
4268	pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimerR3) / uTimerHz;
4269	pThis->uTimerTS = TMTimerGet(pThis->pTimerR3);
4270	LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
4271	}
4272	# else /* !VBOX_WITH_AUDIO_AC97_CALLBACKS */
4273	if (RT_SUCCESS(rc))
4274	{
4275	PAC97DRIVER pDrv;
4276	RTListForEach(&pThis->lstDrv, pDrv, AC97DRIVER, Node)
4277	{
4278	/* Only register primary driver.
4279	* The device emulation does the output multiplexing then. */
4280	if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
4281	continue;
4282
4283	PDMAUDIOCBRECORD AudioCallbacks[2];
4284
4285	AC97CALLBACKCTX Ctx = { pThis, pDrv };
4286
4287	AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
4288	AudioCallbacks[0].pfnCallback = ac97CallbackInput;
4289	AudioCallbacks[0].pvCtx = &Ctx;
4290	AudioCallbacks[0].cbCtx = sizeof(AC97CALLBACKCTX);
4291
4292	AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
4293	AudioCallbacks[1].pfnCallback = ac97CallbackOutput;
4294	AudioCallbacks[1].pvCtx = &Ctx;
4295	AudioCallbacks[1].cbCtx = sizeof(AC97CALLBACKCTX);
4296
4297	rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
4298	if (RT_FAILURE(rc))
4299	break;
4300	}
4301	}
4302	# endif /* VBOX_WITH_AUDIO_AC97_CALLBACKS */
4303
4304	# ifdef VBOX_WITH_STATISTICS
4305	if (RT_SUCCESS(rc))
4306	{
4307	/*
4308	* Register statistics.
4309	*/
4310	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/AC97/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
4311	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "/Devices/AC97/Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
4312	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "/Devices/AC97/Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
4313	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/AC97/BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
4314	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/AC97/BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
4315	}
4316	# endif
4317
4318	LogFlowFuncLeaveRC(rc);
4319	return rc;
4320	}
4321
4322	/**
4323	* The device registration structure.
4324	*/
4325	const PDMDEVREG g_DeviceICHAC97 =
4326	{
4327	/* u32Version */
4328	PDM_DEVREG_VERSION,
4329	/* szName */
4330	"ichac97",
4331	/* szRCMod */
4332	"VBoxDDRC.rc",
4333	/* szR0Mod */
4334	"VBoxDDR0.r0",
4335	/* pszDescription */
4336	"ICH AC'97 Audio Controller",
4337	/* fFlags */
4338	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
4339	/* fClass */
4340	PDM_DEVREG_CLASS_AUDIO,
4341	/* cMaxInstances */
4342	1,
4343	/* cbInstance */
4344	sizeof(AC97STATE),
4345	/* pfnConstruct */
4346	ichac97R3Construct,
4347	/* pfnDestruct */
4348	ichac97R3Destruct,
4349	/* pfnRelocate */
4350	ichac97R3Relocate,
4351	/* pfnMemSetup */
4352	NULL,
4353	/* pfnPowerOn */
4354	NULL,
4355	/* pfnReset */
4356	ichac97R3Reset,
4357	/* pfnSuspend */
4358	NULL,
4359	/* pfnResume */
4360	NULL,
4361	/* pfnAttach */
4362	ichac97R3Attach,
4363	/* pfnDetach */
4364	ichac97R3Detach,
4365	/* pfnQueryInterface. */
4366	NULL,
4367	/* pfnInitComplete */
4368	NULL,
4369	/* pfnPowerOff */
4370	ichac97R3PowerOff,
4371	/* pfnSoftReset */
4372	NULL,
4373	/* u32VersionEnd */
4374	PDM_DEVREG_VERSION
4375	};
4376
4377	#endif /* !IN_RING3 */
4378	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4379

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source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 74005

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