VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 86223

Last change on this file since 86223 was 84815, checked in by vboxsync, 5 years ago

Devices/Audio/DevIchAc97: Workaround a hang upon resume when a NetBSD guest is used, see bugref:9759
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File size: 171.8 KB
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1/* $Id: DevIchAc97.cpp 84815 2020-06-12 12:52:16Z vboxsync $ */
2/** @file
3 * DevIchAc97 - VBox ICH AC97 Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_AC97
23#include <VBox/log.h>
24#include <VBox/vmm/pdmdev.h>
25#include <VBox/vmm/pdmaudioifs.h>
26
27#include <iprt/assert.h>
28#ifdef IN_RING3
29# ifdef DEBUG
30# include <iprt/file.h>
31# endif
32# include <iprt/mem.h>
33# include <iprt/semaphore.h>
34# include <iprt/string.h>
35# include <iprt/uuid.h>
36#endif
37
38#include "VBoxDD.h"
39
40#include "AudioMixBuffer.h"
41#include "AudioMixer.h"
42#include "DrvAudio.h"
43
44
45/*********************************************************************************************************************************
46* Defined Constants And Macros *
47*********************************************************************************************************************************/
48
49/** Current saved state version. */
50#define AC97_SAVED_STATE_VERSION 1
51
52/** Default timer frequency (in Hz). */
53#define AC97_TIMER_HZ_DEFAULT 100
54
55/** Maximum number of streams we support. */
56#define AC97_MAX_STREAMS 3
57
58/** Maximum FIFO size (in bytes). */
59#define AC97_FIFO_MAX 256
60
61#define AC97_SR_FIFOE RT_BIT(4) /**< rwc, FIFO error. */
62#define AC97_SR_BCIS RT_BIT(3) /**< rwc, Buffer completion interrupt status. */
63#define AC97_SR_LVBCI RT_BIT(2) /**< rwc, Last valid buffer completion interrupt. */
64#define AC97_SR_CELV RT_BIT(1) /**< ro, Current equals last valid. */
65#define AC97_SR_DCH RT_BIT(0) /**< ro, Controller halted. */
66#define AC97_SR_VALID_MASK (RT_BIT(5) - 1)
67#define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)
68#define AC97_SR_RO_MASK (AC97_SR_DCH | AC97_SR_CELV)
69#define AC97_SR_INT_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)
70
71#define AC97_CR_IOCE RT_BIT(4) /**< rw, Interrupt On Completion Enable. */
72#define AC97_CR_FEIE RT_BIT(3) /**< rw FIFO Error Interrupt Enable. */
73#define AC97_CR_LVBIE RT_BIT(2) /**< rw Last Valid Buffer Interrupt Enable. */
74#define AC97_CR_RR RT_BIT(1) /**< rw Reset Registers. */
75#define AC97_CR_RPBM RT_BIT(0) /**< rw Run/Pause Bus Master. */
76#define AC97_CR_VALID_MASK (RT_BIT(5) - 1)
77#define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE | AC97_CR_FEIE | AC97_CR_LVBIE)
78
79#define AC97_GC_WR 4 /**< rw Warm reset. */
80#define AC97_GC_CR 2 /**< rw Cold reset. */
81#define AC97_GC_VALID_MASK (RT_BIT(6) - 1)
82
83#define AC97_GS_MD3 RT_BIT(17) /**< rw */
84#define AC97_GS_AD3 RT_BIT(16) /**< rw */
85#define AC97_GS_RCS RT_BIT(15) /**< rwc */
86#define AC97_GS_B3S12 RT_BIT(14) /**< ro */
87#define AC97_GS_B2S12 RT_BIT(13) /**< ro */
88#define AC97_GS_B1S12 RT_BIT(12) /**< ro */
89#define AC97_GS_S1R1 RT_BIT(11) /**< rwc */
90#define AC97_GS_S0R1 RT_BIT(10) /**< rwc */
91#define AC97_GS_S1CR RT_BIT(9) /**< ro */
92#define AC97_GS_S0CR RT_BIT(8) /**< ro */
93#define AC97_GS_MINT RT_BIT(7) /**< ro */
94#define AC97_GS_POINT RT_BIT(6) /**< ro */
95#define AC97_GS_PIINT RT_BIT(5) /**< ro */
96#define AC97_GS_RSRVD (RT_BIT(4) | RT_BIT(3))
97#define AC97_GS_MOINT RT_BIT(2) /**< ro */
98#define AC97_GS_MIINT RT_BIT(1) /**< ro */
99#define AC97_GS_GSCI RT_BIT(0) /**< rwc */
100#define AC97_GS_RO_MASK ( AC97_GS_B3S12 \
101 | AC97_GS_B2S12 \
102 | AC97_GS_B1S12 \
103 | AC97_GS_S1CR \
104 | AC97_GS_S0CR \
105 | AC97_GS_MINT \
106 | AC97_GS_POINT \
107 | AC97_GS_PIINT \
108 | AC97_GS_RSRVD \
109 | AC97_GS_MOINT \
110 | AC97_GS_MIINT)
111#define AC97_GS_VALID_MASK (RT_BIT(18) - 1)
112#define AC97_GS_WCLEAR_MASK (AC97_GS_RCS | AC97_GS_S1R1 | AC97_GS_S0R1 | AC97_GS_GSCI)
113
114/** @name Buffer Descriptor (BD).
115 * @{ */
116#define AC97_BD_IOC RT_BIT(31) /**< Interrupt on Completion. */
117#define AC97_BD_BUP RT_BIT(30) /**< Buffer Underrun Policy. */
118
119#define AC97_BD_LEN_MASK 0xFFFF /**< Mask for the BDL buffer length. */
120
121#define AC97_MAX_BDLE 32 /**< Maximum number of BDLEs. */
122/** @} */
123
124/** @name Extended Audio ID Register (EAID).
125 * @{ */
126#define AC97_EAID_VRA RT_BIT(0) /**< Variable Rate Audio. */
127#define AC97_EAID_VRM RT_BIT(3) /**< Variable Rate Mic Audio. */
128#define AC97_EAID_REV0 RT_BIT(10) /**< AC'97 revision compliance. */
129#define AC97_EAID_REV1 RT_BIT(11) /**< AC'97 revision compliance. */
130/** @} */
131
132/** @name Extended Audio Control and Status Register (EACS).
133 * @{ */
134#define AC97_EACS_VRA RT_BIT(0) /**< Variable Rate Audio (4.2.1.1). */
135#define AC97_EACS_VRM RT_BIT(3) /**< Variable Rate Mic Audio (4.2.1.1). */
136/** @} */
137
138/** @name Baseline Audio Register Set (BARS).
139 * @{ */
140#define AC97_BARS_VOL_MASK 0x1f /**< Volume mask for the Baseline Audio Register Set (5.7.2). */
141#define AC97_BARS_GAIN_MASK 0x0f /**< Gain mask for the Baseline Audio Register Set. */
142#define AC97_BARS_VOL_MUTE_SHIFT 15 /**< Mute bit shift for the Baseline Audio Register Set (5.7.2). */
143/** @} */
144
145/** AC'97 uses 1.5dB steps, we use 0.375dB steps: 1 AC'97 step equals 4 PDM steps. */
146#define AC97_DB_FACTOR 4
147
148/** @name Recording inputs?
149 * @{ */
150#define AC97_REC_MIC UINT8_C(0)
151#define AC97_REC_CD UINT8_C(1)
152#define AC97_REC_VIDEO UINT8_C(2)
153#define AC97_REC_AUX UINT8_C(3)
154#define AC97_REC_LINE_IN UINT8_C(4)
155#define AC97_REC_STEREO_MIX UINT8_C(5)
156#define AC97_REC_MONO_MIX UINT8_C(6)
157#define AC97_REC_PHONE UINT8_C(7)
158#define AC97_REC_MASK UINT8_C(7)
159/** @} */
160
161/** @name Mixer registers / NAM BAR registers?
162 * @{ */
163#define AC97_Reset 0x00
164#define AC97_Master_Volume_Mute 0x02
165#define AC97_Headphone_Volume_Mute 0x04 /**< Also known as AUX, see table 16, section 5.7. */
166#define AC97_Master_Volume_Mono_Mute 0x06
167#define AC97_Master_Tone_RL 0x08
168#define AC97_PC_BEEP_Volume_Mute 0x0a
169#define AC97_Phone_Volume_Mute 0x0c
170#define AC97_Mic_Volume_Mute 0x0e
171#define AC97_Line_In_Volume_Mute 0x10
172#define AC97_CD_Volume_Mute 0x12
173#define AC97_Video_Volume_Mute 0x14
174#define AC97_Aux_Volume_Mute 0x16
175#define AC97_PCM_Out_Volume_Mute 0x18
176#define AC97_Record_Select 0x1a
177#define AC97_Record_Gain_Mute 0x1c
178#define AC97_Record_Gain_Mic_Mute 0x1e
179#define AC97_General_Purpose 0x20
180#define AC97_3D_Control 0x22
181#define AC97_AC_97_RESERVED 0x24
182#define AC97_Powerdown_Ctrl_Stat 0x26
183#define AC97_Extended_Audio_ID 0x28
184#define AC97_Extended_Audio_Ctrl_Stat 0x2a
185#define AC97_PCM_Front_DAC_Rate 0x2c
186#define AC97_PCM_Surround_DAC_Rate 0x2e
187#define AC97_PCM_LFE_DAC_Rate 0x30
188#define AC97_PCM_LR_ADC_Rate 0x32
189#define AC97_MIC_ADC_Rate 0x34
190#define AC97_6Ch_Vol_C_LFE_Mute 0x36
191#define AC97_6Ch_Vol_L_R_Surround_Mute 0x38
192#define AC97_Vendor_Reserved 0x58
193#define AC97_AD_Misc 0x76
194#define AC97_Vendor_ID1 0x7c
195#define AC97_Vendor_ID2 0x7e
196/** @} */
197
198/** @name Analog Devices miscellaneous regiter bits used in AD1980.
199 * @{ */
200#define AC97_AD_MISC_LOSEL RT_BIT(5) /**< Surround (rear) goes to line out outputs. */
201#define AC97_AD_MISC_HPSEL RT_BIT(10) /**< PCM (front) goes to headphone outputs. */
202/** @} */
203
204
205/** @name BUP flag values.
206 * @{ */
207#define BUP_SET RT_BIT_32(0)
208#define BUP_LAST RT_BIT_32(1)
209/** @} */
210
211/** @name AC'97 source indices.
212 * @note The order of these indices is fixed (also applies for saved states) for
213 * the moment. So make sure you know what you're done when altering this!
214 * @{
215 */
216#define AC97SOUNDSOURCE_PI_INDEX 0 /**< PCM in */
217#define AC97SOUNDSOURCE_PO_INDEX 1 /**< PCM out */
218#define AC97SOUNDSOURCE_MC_INDEX 2 /**< Mic in */
219#define AC97SOUNDSOURCE_MAX 3 /**< Max sound sources. */
220/** @} */
221
222/** Port number (offset into NABM BAR) to stream index. */
223#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
224/** Port number (offset into NABM BAR) to stream index, but no masking. */
225#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
226
227/** @name Stream offsets
228 * @{ */
229#define AC97_NABM_OFF_BDBAR 0x0 /**< Buffer Descriptor Base Address */
230#define AC97_NABM_OFF_CIV 0x4 /**< Current Index Value */
231#define AC97_NABM_OFF_LVI 0x5 /**< Last Valid Index */
232#define AC97_NABM_OFF_SR 0x6 /**< Status Register */
233#define AC97_NABM_OFF_PICB 0x8 /**< Position in Current Buffer */
234#define AC97_NABM_OFF_PIV 0xa /**< Prefetched Index Value */
235#define AC97_NABM_OFF_CR 0xb /**< Control Register */
236#define AC97_NABM_OFF_MASK 0xf /**< Mask for getting the the per-stream register. */
237/** @} */
238
239
240/** @name PCM in NABM BAR registers (0x00..0x0f).
241 * @{ */
242#define PI_BDBAR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x0) /**< PCM in: Buffer Descriptor Base Address */
243#define PI_CIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x4) /**< PCM in: Current Index Value */
244#define PI_LVI (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x5) /**< PCM in: Last Valid Index */
245#define PI_SR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x6) /**< PCM in: Status Register */
246#define PI_PICB (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x8) /**< PCM in: Position in Current Buffer */
247#define PI_PIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xa) /**< PCM in: Prefetched Index Value */
248#define PI_CR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xb) /**< PCM in: Control Register */
249/** @} */
250
251/** @name PCM out NABM BAR registers (0x10..0x1f).
252 * @{ */
253#define PO_BDBAR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x0) /**< PCM out: Buffer Descriptor Base Address */
254#define PO_CIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x4) /**< PCM out: Current Index Value */
255#define PO_LVI (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x5) /**< PCM out: Last Valid Index */
256#define PO_SR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x6) /**< PCM out: Status Register */
257#define PO_PICB (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x8) /**< PCM out: Position in Current Buffer */
258#define PO_PIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xa) /**< PCM out: Prefetched Index Value */
259#define PO_CR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xb) /**< PCM out: Control Register */
260/** @} */
261
262/** @name Mic in NABM BAR registers (0x20..0x2f).
263 * @{ */
264#define MC_BDBAR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x0) /**< PCM in: Buffer Descriptor Base Address */
265#define MC_CIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x4) /**< PCM in: Current Index Value */
266#define MC_LVI (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x5) /**< PCM in: Last Valid Index */
267#define MC_SR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x6) /**< PCM in: Status Register */
268#define MC_PICB (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x8) /**< PCM in: Position in Current Buffer */
269#define MC_PIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xa) /**< PCM in: Prefetched Index Value */
270#define MC_CR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xb) /**< PCM in: Control Register */
271/** @} */
272
273/** @name Misc NABM BAR registers.
274 * @{ */
275/** NABMBAR: Global Control Register.
276 * @note This is kind of in the MIC IN area. */
277#define AC97_GLOB_CNT 0x2c
278/** NABMBAR: Global Status. */
279#define AC97_GLOB_STA 0x30
280/** Codec Access Semaphore Register. */
281#define AC97_CAS 0x34
282/** @} */
283
284
285/*********************************************************************************************************************************
286* Structures and Typedefs *
287*********************************************************************************************************************************/
288/** The ICH AC'97 (Intel) controller (shared). */
289typedef struct AC97STATE *PAC97STATE;
290/** The ICH AC'97 (Intel) controller (ring-3). */
291typedef struct AC97STATER3 *PAC97STATER3;
292
293/**
294 * Buffer Descriptor List Entry (BDLE).
295 */
296typedef struct AC97BDLE
297{
298 /** Location of data buffer (bits 31:1). */
299 uint32_t addr;
300 /** Flags (bits 31 + 30) and length (bits 15:0) of data buffer (in audio samples). */
301 uint32_t ctl_len;
302} AC97BDLE;
303AssertCompileSize(AC97BDLE, 8);
304/** Pointer to BDLE. */
305typedef AC97BDLE *PAC97BDLE;
306
307/**
308 * Bus master register set for an audio stream.
309 */
310typedef struct AC97BMREGS
311{
312 uint32_t bdbar; /**< rw 0, Buffer Descriptor List: BAR (Base Address Register). */
313 uint8_t civ; /**< ro 0, Current index value. */
314 uint8_t lvi; /**< rw 0, Last valid index. */
315 uint16_t sr; /**< rw 1, Status register. */
316 uint16_t picb; /**< ro 0, Position in current buffer (in samples). */
317 uint8_t piv; /**< ro 0, Prefetched index value. */
318 uint8_t cr; /**< rw 0, Control register. */
319 int32_t bd_valid; /**< Whether current BDLE is initialized or not. */
320 AC97BDLE bd; /**< Current Buffer Descriptor List Entry (BDLE). */
321} AC97BMREGS;
322AssertCompileSizeAlignment(AC97BMREGS, 8);
323/** Pointer to the BM registers of an audio stream. */
324typedef AC97BMREGS *PAC97BMREGS;
325
326#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
327/**
328 * Asynchronous I/O state for an AC'97 stream.
329 */
330typedef struct AC97STREAMSTATEAIO
331{
332 /** Thread handle for the actual I/O thread. */
333 RTTHREAD Thread;
334 /** Event for letting the thread know there is some data to process. */
335 RTSEMEVENT Event;
336 /** Critical section for synchronizing access. */
337 RTCRITSECT CritSect;
338 /** Started indicator. */
339 volatile bool fStarted;
340 /** Shutdown indicator. */
341 volatile bool fShutdown;
342 /** Whether the thread should do any data processing or not. */
343 volatile bool fEnabled;
344 bool afPadding[5];
345} AC97STREAMSTATEAIO;
346/** Pointer to the async I/O state for an AC'97 stream. */
347typedef AC97STREAMSTATEAIO *PAC97STREAMSTATEAIO;
348#endif
349
350
351/**
352 * The internal state of an AC'97 stream.
353 */
354typedef struct AC97STREAMSTATE
355{
356 /** Criticial section for this stream. */
357 RTCRITSECT CritSect;
358 /** Circular buffer (FIFO) for holding DMA'ed data. */
359 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
360#if HC_ARCH_BITS == 32
361 uint32_t Padding;
362#endif
363 /** The stream's current configuration. */
364 PDMAUDIOSTREAMCFG Cfg; //+108
365#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
366 /** Asynchronous I/O state members. */
367 AC97STREAMSTATEAIO AIO;
368#endif
369 /** Timestamp of the last DMA data transfer. */
370 uint64_t tsTransferLast;
371 /** Timestamp of the next DMA data transfer.
372 * Next for determining the next scheduling window.
373 * Can be 0 if no next transfer is scheduled. */
374 uint64_t tsTransferNext;
375 /** Transfer chunk size (in bytes) of a transfer period. */
376 uint32_t cbTransferChunk;
377 /** The stream's timer Hz rate.
378 * This value can can be different from the device's default Hz rate,
379 * depending on the rate the stream expects (e.g. for 5.1 speaker setups).
380 * Set in R3StreamInit(). */
381 uint16_t uTimerHz;
382 uint8_t Padding3[2];
383 /** (Virtual) clock ticks per transfer. */
384 uint64_t cTransferTicks;
385 /** Timestamp (in ns) of last stream update. */
386 uint64_t tsLastUpdateNs;
387} AC97STREAMSTATE;
388AssertCompileSizeAlignment(AC97STREAMSTATE, 8);
389/** Pointer to internal state of an AC'97 stream. */
390typedef AC97STREAMSTATE *PAC97STREAMSTATE;
391
392/**
393 * Runtime configurable debug stuff for an AC'97 stream.
394 */
395typedef struct AC97STREAMDEBUGRT
396{
397 /** Whether debugging is enabled or not. */
398 bool fEnabled;
399 uint8_t Padding[7];
400 /** File for dumping stream reads / writes.
401 * For input streams, this dumps data being written to the device FIFO,
402 * whereas for output streams this dumps data being read from the device FIFO. */
403 R3PTRTYPE(PPDMAUDIOFILE) pFileStream;
404 /** File for dumping DMA reads / writes.
405 * For input streams, this dumps data being written to the device DMA,
406 * whereas for output streams this dumps data being read from the device DMA. */
407 R3PTRTYPE(PPDMAUDIOFILE) pFileDMA;
408} AC97STREAMDEBUGRT;
409
410/**
411 * Debug stuff for an AC'97 stream.
412 */
413typedef struct AC97STREAMDEBUG
414{
415 /** Runtime debug stuff. */
416 AC97STREAMDEBUGRT Runtime;
417} AC97STREAMDEBUG;
418
419/**
420 * The shared AC'97 stream state.
421 */
422typedef struct AC97STREAM
423{
424 /** Stream number (SDn). */
425 uint8_t u8SD;
426 uint8_t abPadding0[7];
427 /** Bus master registers of this stream. */
428 AC97BMREGS Regs;
429 /** The timer for pumping data thru the attached LUN drivers. */
430 TMTIMERHANDLE hTimer;
431} AC97STREAM;
432AssertCompileSizeAlignment(AC97STREAM, 8);
433/** Pointer to a shared AC'97 stream state. */
434typedef AC97STREAM *PAC97STREAM;
435
436
437/**
438 * The ring-3 AC'97 stream state.
439 */
440typedef struct AC97STREAMR3
441{
442 /** Stream number (SDn). */
443 uint8_t u8SD;
444 uint8_t abPadding0[7];
445 /** Internal state of this stream. */
446 AC97STREAMSTATE State;
447 /** Debug stuff. */
448 AC97STREAMDEBUG Dbg;
449} AC97STREAMR3;
450AssertCompileSizeAlignment(AC97STREAMR3, 8);
451/** Pointer to an AC'97 stream state for ring-3. */
452typedef AC97STREAMR3 *PAC97STREAMR3;
453
454
455#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
456/**
457 * Asynchronous I/O thread context (arguments).
458 */
459typedef struct AC97STREAMTHREADCTX
460{
461 /** The AC'97 device state (shared). */
462 PAC97STATE pThis;
463 /** The AC'97 device state (ring-3). */
464 PAC97STATER3 pThisCC;
465 /** The AC'97 stream state (shared). */
466 PAC97STREAM pStream;
467 /** The AC'97 stream state (ring-3). */
468 PAC97STREAMR3 pStreamCC;
469} AC97STREAMTHREADCTX;
470/** Pointer to the context for an async I/O thread. */
471typedef AC97STREAMTHREADCTX *PAC97STREAMTHREADCTX;
472#endif
473
474/**
475 * A driver stream (host backend).
476 *
477 * Each driver has its own instances of audio mixer streams, which then
478 * can go into the same (or even different) audio mixer sinks.
479 */
480typedef struct AC97DRIVERSTREAM
481{
482 /** Associated mixer stream handle. */
483 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
484} AC97DRIVERSTREAM;
485/** Pointer to a driver stream. */
486typedef AC97DRIVERSTREAM *PAC97DRIVERSTREAM;
487
488/**
489 * A host backend driver (LUN).
490 */
491typedef struct AC97DRIVER
492{
493 /** Node for storing this driver in our device driver list of AC97STATE. */
494 RTLISTNODER3 Node;
495 /** Driver flags. */
496 PDMAUDIODRVFLAGS fFlags;
497 /** LUN # to which this driver has been assigned. */
498 uint8_t uLUN;
499 /** Whether this driver is in an attached state or not. */
500 bool fAttached;
501 uint8_t abPadding[2];
502 /** Pointer to the description string passed to PDMDevHlpDriverAttach(). */
503 R3PTRTYPE(char *) pszDesc;
504 /** Pointer to attached driver base interface. */
505 R3PTRTYPE(PPDMIBASE) pDrvBase;
506 /** Audio connector interface to the underlying host backend. */
507 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
508 /** Driver stream for line input. */
509 AC97DRIVERSTREAM LineIn;
510 /** Driver stream for mic input. */
511 AC97DRIVERSTREAM MicIn;
512 /** Driver stream for output. */
513 AC97DRIVERSTREAM Out;
514} AC97DRIVER;
515/** Pointer to a host backend driver (LUN). */
516typedef AC97DRIVER *PAC97DRIVER;
517
518/**
519 * Debug settings.
520 */
521typedef struct AC97STATEDEBUG
522{
523 /** Whether debugging is enabled or not. */
524 bool fEnabled;
525 bool afAlignment[7];
526 /** Path where to dump the debug output to.
527 * Defaults to VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH. */
528 R3PTRTYPE(char *) pszOutPath;
529} AC97STATEDEBUG;
530
531
532/* Codec models. */
533typedef enum AC97CODEC
534{
535 AC97CODEC_INVALID = 0, /**< Customary illegal zero value. */
536 AC97CODEC_STAC9700, /**< SigmaTel STAC9700 */
537 AC97CODEC_AD1980, /**< Analog Devices AD1980 */
538 AC97CODEC_AD1981B, /**< Analog Devices AD1981B */
539 AC97CODEC_32BIT_HACK = 0x7fffffff
540} AC97CODEC;
541
542
543/**
544 * The shared AC'97 device state.
545 */
546typedef struct AC97STATE
547{
548 /** Critical section protecting the AC'97 state. */
549 PDMCRITSECT CritSect;
550 /** Global Control (Bus Master Control Register). */
551 uint32_t glob_cnt;
552 /** Global Status (Bus Master Control Register). */
553 uint32_t glob_sta;
554 /** Codec Access Semaphore Register (Bus Master Control Register). */
555 uint32_t cas;
556 uint32_t last_samp;
557 uint8_t mixer_data[256];
558 /** Array of AC'97 streams (parallel to AC97STATER3::aStreams). */
559 AC97STREAM aStreams[AC97_MAX_STREAMS];
560 /** The device timer Hz rate. Defaults to AC97_TIMER_HZ_DEFAULT_DEFAULT. */
561 uint16_t uTimerHz;
562 uint16_t au16Padding1[3];
563 uint8_t silence[128];
564 uint32_t bup_flag;
565 /** Codec model. */
566 AC97CODEC enmCodecModel;
567
568 /** PCI region \#0: NAM I/O ports. */
569 IOMIOPORTHANDLE hIoPortsNam;
570 /** PCI region \#0: NANM I/O ports. */
571 IOMIOPORTHANDLE hIoPortsNabm;
572
573 STAMCOUNTER StatUnimplementedNabmReads;
574 STAMCOUNTER StatUnimplementedNabmWrites;
575#ifdef VBOX_WITH_STATISTICS
576 STAMPROFILE StatTimer;
577 STAMPROFILE StatIn;
578 STAMPROFILE StatOut;
579 STAMCOUNTER StatBytesRead;
580 STAMCOUNTER StatBytesWritten;
581#endif
582} AC97STATE;
583AssertCompileMemberAlignment(AC97STATE, aStreams, 8);
584AssertCompileMemberAlignment(AC97STATE, StatUnimplementedNabmReads, 8);
585#ifdef VBOX_WITH_STATISTICS
586AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
587AssertCompileMemberAlignment(AC97STATE, StatBytesRead, 8);
588AssertCompileMemberAlignment(AC97STATE, StatBytesWritten, 8);
589#endif
590
591
592/**
593 * The ring-3 AC'97 device state.
594 */
595typedef struct AC97STATER3
596{
597 /** Array of AC'97 streams (parallel to AC97STATE:aStreams). */
598 AC97STREAMR3 aStreams[AC97_MAX_STREAMS];
599 /** R3 pointer to the device instance. */
600 PPDMDEVINSR3 pDevIns;
601 /** List of associated LUN drivers (AC97DRIVER). */
602 RTLISTANCHORR3 lstDrv;
603 /** The device's software mixer. */
604 R3PTRTYPE(PAUDIOMIXER) pMixer;
605 /** Audio sink for PCM output. */
606 R3PTRTYPE(PAUDMIXSINK) pSinkOut;
607 /** Audio sink for line input. */
608 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
609 /** Audio sink for microphone input. */
610 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
611 /** The base interface for LUN\#0. */
612 PDMIBASE IBase;
613 /** Debug settings. */
614 AC97STATEDEBUG Dbg;
615} AC97STATER3;
616AssertCompileMemberAlignment(AC97STATER3, aStreams, 8);
617/** Pointer to the ring-3 AC'97 device state. */
618typedef AC97STATER3 *PAC97STATER3;
619
620
621/**
622 * Acquires the AC'97 lock.
623 */
624#define DEVAC97_LOCK(a_pDevIns, a_pThis) \
625 do { \
626 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
627 AssertRC(rcLock); \
628 } while (0)
629
630/**
631 * Acquires the AC'97 lock or returns.
632 */
633# define DEVAC97_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
634 do { \
635 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, a_rcBusy); \
636 if (rcLock == VINF_SUCCESS) \
637 break; \
638 AssertRC(rcLock); \
639 return rcLock; \
640 } while (0)
641
642/** Retrieves an attribute from a specific audio stream in RC. */
643#define DEVAC97_CTX_SUFF_SD(a_Var, a_SD) CTX_SUFF(a_Var)[a_SD]
644
645/**
646 * Releases the AC'97 lock.
647 */
648#define DEVAC97_UNLOCK(a_pDevIns, a_pThis) \
649 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
650
651/**
652 * Acquires the TM lock and AC'97 lock, returns on failure.
653 */
654#define DEVAC97_LOCK_BOTH_RETURN(a_pDevIns, a_pThis, a_pStream, a_rcBusy) \
655 do { \
656 VBOXSTRICTRC rcLock = PDMDevHlpTimerLockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect, (a_rcBusy)); \
657 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
658 { /* likely */ } \
659 else \
660 { \
661 AssertRC(VBOXSTRICTRC_VAL(rcLock)); \
662 return rcLock; \
663 } \
664 } while (0)
665
666/**
667 * Releases the AC'97 lock and TM lock.
668 */
669#define DEVAC97_UNLOCK_BOTH(a_pDevIns, a_pThis, a_pStream) \
670 PDMDevHlpTimerUnlockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect)
671
672#ifndef VBOX_DEVICE_STRUCT_TESTCASE
673
674
675/*********************************************************************************************************************************
676* Internal Functions *
677*********************************************************************************************************************************/
678#ifdef IN_RING3
679static int ichac97R3StreamOpen(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce);
680static int ichac97R3StreamClose(PAC97STREAM pStream);
681static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC);
682static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC);
683static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC);
684static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC);
685static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
686 PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax);
687static void ichac97R3StreamUpdate(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
688 PAC97STREAMR3 pStreamCC, bool fInTimer);
689
690static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns);
691
692static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
693
694static void ichac97R3MixerRemoveDrvStreams(PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir,
695 PDMAUDIODSTSRCUNION dstSrc);
696
697# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
698static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC);
699static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAMR3 pStreamCC);
700static void ichac97R3StreamAsyncIOLock(PAC97STREAMR3 pStreamCC);
701static void ichac97R3StreamAsyncIOUnlock(PAC97STREAMR3 pStreamCC);
702/*static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable); Unused */
703# endif
704
705DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD);
706DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline);
707#endif /* IN_RING3 */
708
709
710/*********************************************************************************************************************************
711* Global Variables *
712*********************************************************************************************************************************/
713#ifdef IN_RING3
714/** NABM I/O port descriptions. */
715static const IOMIOPORTDESC g_aNabmPorts[] =
716{
717 { "PCM IN - BDBAR", "PCM IN - BDBAR", NULL, NULL },
718 { "", NULL, NULL, NULL },
719 { "", NULL, NULL, NULL },
720 { "", NULL, NULL, NULL },
721 { "PCM IN - CIV", "PCM IN - CIV", NULL, NULL },
722 { "PCM IN - LVI", "PCM IN - LIV", NULL, NULL },
723 { "PCM IN - SR", "PCM IN - SR", NULL, NULL },
724 { "", NULL, NULL, NULL },
725 { "PCM IN - PICB", "PCM IN - PICB", NULL, NULL },
726 { "", NULL, NULL, NULL },
727 { "PCM IN - PIV", "PCM IN - PIV", NULL, NULL },
728 { "PCM IN - CR", "PCM IN - CR", NULL, NULL },
729 { "", NULL, NULL, NULL },
730 { "", NULL, NULL, NULL },
731 { "", NULL, NULL, NULL },
732 { "", NULL, NULL, NULL },
733
734 { "PCM OUT - BDBAR", "PCM OUT - BDBAR", NULL, NULL },
735 { "", NULL, NULL, NULL },
736 { "", NULL, NULL, NULL },
737 { "", NULL, NULL, NULL },
738 { "PCM OUT - CIV", "PCM OUT - CIV", NULL, NULL },
739 { "PCM OUT - LVI", "PCM OUT - LIV", NULL, NULL },
740 { "PCM OUT - SR", "PCM OUT - SR", NULL, NULL },
741 { "", NULL, NULL, NULL },
742 { "PCM OUT - PICB", "PCM OUT - PICB", NULL, NULL },
743 { "", NULL, NULL, NULL },
744 { "PCM OUT - PIV", "PCM OUT - PIV", NULL, NULL },
745 { "PCM OUT - CR", "PCM IN - CR", NULL, NULL },
746 { "", NULL, NULL, NULL },
747 { "", NULL, NULL, NULL },
748 { "", NULL, NULL, NULL },
749 { "", NULL, NULL, NULL },
750
751 { "MIC IN - BDBAR", "MIC IN - BDBAR", NULL, NULL },
752 { "", NULL, NULL, NULL },
753 { "", NULL, NULL, NULL },
754 { "", NULL, NULL, NULL },
755 { "MIC IN - CIV", "MIC IN - CIV", NULL, NULL },
756 { "MIC IN - LVI", "MIC IN - LIV", NULL, NULL },
757 { "MIC IN - SR", "MIC IN - SR", NULL, NULL },
758 { "", NULL, NULL, NULL },
759 { "MIC IN - PICB", "MIC IN - PICB", NULL, NULL },
760 { "", NULL, NULL, NULL },
761 { "MIC IN - PIV", "MIC IN - PIV", NULL, NULL },
762 { "MIC IN - CR", "MIC IN - CR", NULL, NULL },
763 { "GLOB CNT", "GLOB CNT", NULL, NULL },
764 { "", NULL, NULL, NULL },
765 { "", NULL, NULL, NULL },
766 { "", NULL, NULL, NULL },
767
768 { "GLOB STA", "GLOB STA", NULL, NULL },
769 { "", NULL, NULL, NULL },
770 { "", NULL, NULL, NULL },
771 { "", NULL, NULL, NULL },
772 { "CAS", "CAS", NULL, NULL },
773 { NULL, NULL, NULL, NULL },
774};
775
776#define AC97SOUNDSOURCE_PI_INDEX 0 /**< PCM in */
777#define AC97SOUNDSOURCE_PO_INDEX 1 /**< PCM out */
778#define AC97SOUNDSOURCE_MC_INDEX 2 /**< Mic in */
779#define AC97SOUNDSOURCE_MAX 3 /**< Max sound sources. */
780/** @} */
781
782/** Port number (offset into NABM BAR) to stream index. */
783#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
784/** Port number (offset into NABM BAR) to stream index, but no masking. */
785#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
786
787/** @name Stream offsets
788 * @{ */
789#define AC97_NABM_OFF_BDBAR 0x0 /**< Buffer Descriptor Base Address */
790#define AC97_NABM_OFF_CIV 0x4 /**< Current Index Value */
791#define AC97_NABM_OFF_LVI 0x5 /**< Last Valid Index */
792#define AC97_NABM_OFF_SR 0x6 /**< Status Register */
793#define AC97_NABM_OFF_PICB 0x8 /**< Position in Current Buffer */
794#define AC97_NABM_OFF_PIV 0xa /**< Prefetched Index Value */
795#define AC97_NABM_OFF_CR 0xb /**< Control Register */
796#define AC97_NABM_OFF_MASK 0xf /**< Mask for getting the the per-stream register. */
797
798#endif
799
800
801
802static void ichac97WarmReset(PAC97STATE pThis)
803{
804 NOREF(pThis);
805}
806
807static void ichac97ColdReset(PAC97STATE pThis)
808{
809 NOREF(pThis);
810}
811
812
813#ifdef IN_RING3
814
815/**
816 * Retrieves the audio mixer sink of a corresponding AC'97 stream index.
817 *
818 * @returns Pointer to audio mixer sink if found, or NULL if not found / invalid.
819 * @param pThisCC The ring-3 AC'97 state.
820 * @param uIndex Stream index to get audio mixer sink for.
821 */
822DECLINLINE(PAUDMIXSINK) ichac97R3IndexToSink(PAC97STATER3 pThisCC, uint8_t uIndex)
823{
824 switch (uIndex)
825 {
826 case AC97SOUNDSOURCE_PI_INDEX: return pThisCC->pSinkLineIn;
827 case AC97SOUNDSOURCE_PO_INDEX: return pThisCC->pSinkOut;
828 case AC97SOUNDSOURCE_MC_INDEX: return pThisCC->pSinkMicIn;
829 default:
830 AssertMsgFailedReturn(("Wrong index %RU8\n", uIndex), NULL);
831 }
832}
833
834/**
835 * Fetches the current BDLE (Buffer Descriptor List Entry) of an AC'97 audio stream.
836 *
837 * @returns IPRT status code.
838 * @param pDevIns The device instance.
839 * @param pStream AC'97 stream to fetch BDLE for.
840 *
841 * @remark Uses CIV as BDLE index.
842 */
843static void ichac97R3StreamFetchBDLE(PPDMDEVINS pDevIns, PAC97STREAM pStream)
844{
845 PAC97BMREGS pRegs = &pStream->Regs;
846
847 AC97BDLE BDLE;
848 PDMDevHlpPhysRead(pDevIns, pRegs->bdbar + pRegs->civ * sizeof(AC97BDLE), &BDLE, sizeof(AC97BDLE));
849 pRegs->bd_valid = 1;
850# ifndef RT_LITTLE_ENDIAN
851# error "Please adapt the code (audio buffers are little endian)!"
852# else
853 pRegs->bd.addr = RT_H2LE_U32(BDLE.addr & ~3);
854 pRegs->bd.ctl_len = RT_H2LE_U32(BDLE.ctl_len);
855# endif
856 pRegs->picb = pRegs->bd.ctl_len & AC97_BD_LEN_MASK;
857 LogFlowFunc(("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes), bup=%RTbool, ioc=%RTbool\n",
858 pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len >> 16,
859 pRegs->bd.ctl_len & AC97_BD_LEN_MASK,
860 (pRegs->bd.ctl_len & AC97_BD_LEN_MASK) << 1, /** @todo r=andy Assumes 16bit samples. */
861 RT_BOOL(pRegs->bd.ctl_len & AC97_BD_BUP),
862 RT_BOOL(pRegs->bd.ctl_len & AC97_BD_IOC)));
863}
864
865#endif /* IN_RING3 */
866
867/**
868 * Updates the status register (SR) of an AC'97 audio stream.
869 *
870 * @param pDevIns The device instance.
871 * @param pThis The shared AC'97 state.
872 * @param pStream AC'97 stream to update SR for.
873 * @param new_sr New value for status register (SR).
874 */
875static void ichac97StreamUpdateSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr)
876{
877 PAC97BMREGS pRegs = &pStream->Regs;
878
879 bool fSignal = false;
880 int iIRQL = 0;
881
882 uint32_t new_mask = new_sr & AC97_SR_INT_MASK;
883 uint32_t old_mask = pRegs->sr & AC97_SR_INT_MASK;
884
885 if (new_mask ^ old_mask)
886 {
887 /** @todo Is IRQ deasserted when only one of status bits is cleared? */
888 if (!new_mask)
889 {
890 fSignal = true;
891 iIRQL = 0;
892 }
893 else if ((new_mask & AC97_SR_LVBCI) && (pRegs->cr & AC97_CR_LVBIE))
894 {
895 fSignal = true;
896 iIRQL = 1;
897 }
898 else if ((new_mask & AC97_SR_BCIS) && (pRegs->cr & AC97_CR_IOCE))
899 {
900 fSignal = true;
901 iIRQL = 1;
902 }
903 }
904
905 pRegs->sr = new_sr;
906
907 LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n",
908 pRegs->sr & AC97_SR_BCIS, pRegs->sr & AC97_SR_LVBCI, pRegs->sr, fSignal, iIRQL));
909
910 if (fSignal)
911 {
912 static uint32_t const s_aMasks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT };
913 Assert(pStream->u8SD < AC97_MAX_STREAMS);
914 if (iIRQL)
915 pThis->glob_sta |= s_aMasks[pStream->u8SD];
916 else
917 pThis->glob_sta &= ~s_aMasks[pStream->u8SD];
918
919 LogFlowFunc(("Setting IRQ level=%d\n", iIRQL));
920 PDMDevHlpPCISetIrq(pDevIns, 0, iIRQL);
921 }
922}
923
924/**
925 * Writes a new value to a stream's status register (SR).
926 *
927 * @param pDevIns The device instance.
928 * @param pThis The shared AC'97 device state.
929 * @param pStream Stream to update SR for.
930 * @param u32Val New value to set the stream's SR to.
931 */
932static void ichac97StreamWriteSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t u32Val)
933{
934 PAC97BMREGS pRegs = &pStream->Regs;
935
936 Log3Func(("[SD%RU8] SR <- %#x (sr %#x)\n", pStream->u8SD, u32Val, pRegs->sr));
937
938 pRegs->sr |= u32Val & ~(AC97_SR_RO_MASK | AC97_SR_WCLEAR_MASK);
939 ichac97StreamUpdateSR(pDevIns, pThis, pStream, pRegs->sr & ~(u32Val & AC97_SR_WCLEAR_MASK));
940}
941
942#ifdef IN_RING3
943
944/**
945 * Returns whether an AC'97 stream is enabled or not.
946 *
947 * @returns IPRT status code.
948 * @param pThisCC The ring-3 AC'97 device state.
949 * @param pStream Stream to return status for.
950 */
951static bool ichac97R3StreamIsEnabled(PAC97STATER3 pThisCC, PAC97STREAM pStream)
952{
953 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
954 bool fIsEnabled = RT_BOOL(AudioMixerSinkGetStatus(pSink) & AUDMIXSINK_STS_RUNNING);
955
956 LogFunc(("[SD%RU8] fIsEnabled=%RTbool\n", pStream->u8SD, fIsEnabled));
957 return fIsEnabled;
958}
959
960/**
961 * Enables or disables an AC'97 audio stream.
962 *
963 * @returns IPRT status code.
964 * @param pThis The shared AC'97 state.
965 * @param pThisCC The ring-3 AC'97 state.
966 * @param pStream The AC'97 stream to enable or disable (shared
967 * state).
968 * @param pStreamCC The ring-3 stream state (matching to @a pStream).
969 * @param fEnable Whether to enable or disable the stream.
970 *
971 */
972static int ichac97R3StreamEnable(PAC97STATE pThis, PAC97STATER3 pThisCC,
973 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fEnable)
974{
975 ichac97R3StreamLock(pStreamCC);
976
977 int rc = VINF_SUCCESS;
978
979# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
980 if (fEnable)
981 rc = ichac97R3StreamAsyncIOCreate(pThis, pThisCC, pStream, pStreamCC);
982 if (RT_SUCCESS(rc))
983 ichac97R3StreamAsyncIOLock(pStreamCC);
984# endif
985
986 if (fEnable)
987 {
988 if (pStreamCC->State.pCircBuf)
989 RTCircBufReset(pStreamCC->State.pCircBuf);
990
991 rc = ichac97R3StreamOpen(pThis, pThisCC, pStream, pStreamCC, false /* fForce */);
992
993 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
994 { /* likely */ }
995 else
996 {
997 if (!DrvAudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileStream))
998 {
999 int rc2 = DrvAudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileStream, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
1000 &pStreamCC->State.Cfg.Props);
1001 AssertRC(rc2);
1002 }
1003
1004 if (!DrvAudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileDMA))
1005 {
1006 int rc2 = DrvAudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileDMA, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
1007 &pStreamCC->State.Cfg.Props);
1008 AssertRC(rc2);
1009 }
1010 }
1011 }
1012 else
1013 rc = ichac97R3StreamClose(pStream);
1014
1015 if (RT_SUCCESS(rc))
1016 {
1017 /* First, enable or disable the stream and the stream's sink, if any. */
1018 rc = AudioMixerSinkCtl(ichac97R3IndexToSink(pThisCC, pStream->u8SD),
1019 fEnable ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE);
1020 }
1021
1022# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1023 ichac97R3StreamAsyncIOUnlock(pStreamCC);
1024# endif
1025
1026 /* Make sure to leave the lock before (eventually) starting the timer. */
1027 ichac97R3StreamUnlock(pStreamCC);
1028
1029 LogFunc(("[SD%RU8] fEnable=%RTbool, rc=%Rrc\n", pStream->u8SD, fEnable, rc));
1030 return rc;
1031}
1032
1033/**
1034 * Resets an AC'97 stream.
1035 *
1036 * @param pThis The shared AC'97 state.
1037 * @param pStream The AC'97 stream to reset (shared).
1038 * @param pStreamCC The AC'97 stream to reset (ring-3).
1039 */
1040static void ichac97R3StreamReset(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1041{
1042 ichac97R3StreamLock(pStreamCC);
1043
1044 LogFunc(("[SD%RU8]\n", pStream->u8SD));
1045
1046 if (pStreamCC->State.pCircBuf)
1047 RTCircBufReset(pStreamCC->State.pCircBuf);
1048
1049 PAC97BMREGS pRegs = &pStream->Regs;
1050
1051 pRegs->bdbar = 0;
1052 pRegs->civ = 0;
1053 pRegs->lvi = 0;
1054
1055 pRegs->picb = 0;
1056 pRegs->piv = 0;
1057 pRegs->cr = pRegs->cr & AC97_CR_DONT_CLEAR_MASK;
1058 pRegs->bd_valid = 0;
1059
1060 RT_ZERO(pThis->silence);
1061
1062 ichac97R3StreamUnlock(pStreamCC);
1063}
1064
1065/**
1066 * Creates an AC'97 audio stream.
1067 *
1068 * @returns IPRT status code.
1069 * @param pThisCC The ring-3 AC'97 state.
1070 * @param pStream The AC'97 stream to create (shared).
1071 * @param pStreamCC The AC'97 stream to create (ring-3).
1072 * @param u8SD Stream descriptor number to assign.
1073 */
1074static int ichac97R3StreamCreate(PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint8_t u8SD)
1075{
1076 LogFunc(("[SD%RU8] pStream=%p\n", u8SD, pStream));
1077
1078 AssertReturn(u8SD < AC97_MAX_STREAMS, VERR_INVALID_PARAMETER);
1079 pStream->u8SD = u8SD;
1080 pStreamCC->u8SD = u8SD;
1081
1082 int rc = RTCritSectInit(&pStreamCC->State.CritSect);
1083 AssertRCReturn(rc, rc);
1084
1085 pStreamCC->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
1086
1087 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1088 { /* likely */ }
1089 else
1090 {
1091 char szFile[64];
1092
1093 if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1094 RTStrPrintf(szFile, sizeof(szFile), "ac97StreamWriteSD%RU8", pStream->u8SD);
1095 else
1096 RTStrPrintf(szFile, sizeof(szFile), "ac97StreamReadSD%RU8", pStream->u8SD);
1097
1098 char szPath[RTPATH_MAX];
1099 int rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1100 0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
1101 AssertRC(rc2);
1102 rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileStream);
1103 AssertRC(rc2);
1104
1105 if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1106 RTStrPrintf(szFile, sizeof(szFile), "ac97DMAWriteSD%RU8", pStream->u8SD);
1107 else
1108 RTStrPrintf(szFile, sizeof(szFile), "ac97DMAReadSD%RU8", pStream->u8SD);
1109
1110 rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1111 0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
1112 AssertRC(rc2);
1113
1114 rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileDMA);
1115 AssertRC(rc2);
1116
1117 /* Delete stale debugging files from a former run. */
1118 DrvAudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileStream);
1119 DrvAudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileDMA);
1120 }
1121
1122 return rc;
1123}
1124
1125/**
1126 * Destroys an AC'97 audio stream.
1127 *
1128 * @returns IPRT status code.
1129 * @param pThis The shared AC'97 state.
1130 * @param pStream The AC'97 stream to destroy (shared).
1131 * @param pStreamCC The AC'97 stream to destroy (ring-3).
1132 */
1133static void ichac97R3StreamDestroy(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1134{
1135 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
1136
1137 ichac97R3StreamClose(pStream);
1138
1139 int rc2 = RTCritSectDelete(&pStreamCC->State.CritSect);
1140 AssertRC(rc2);
1141
1142# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1143 rc2 = ichac97R3StreamAsyncIODestroy(pThis, pStreamCC);
1144 AssertRC(rc2);
1145# else
1146 RT_NOREF(pThis);
1147# endif
1148
1149 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1150 { /* likely */ }
1151 else
1152 {
1153 DrvAudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileStream);
1154 pStreamCC->Dbg.Runtime.pFileStream = NULL;
1155
1156 DrvAudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileDMA);
1157 pStreamCC->Dbg.Runtime.pFileDMA = NULL;
1158 }
1159
1160 if (pStreamCC->State.pCircBuf)
1161 {
1162 RTCircBufDestroy(pStreamCC->State.pCircBuf);
1163 pStreamCC->State.pCircBuf = NULL;
1164 }
1165
1166 LogFlowFuncLeave();
1167}
1168
1169/**
1170 * Destroys all AC'97 audio streams of the device.
1171 *
1172 * @param pThis The shared AC'97 state.
1173 * @param pThisCC The ring-3 AC'97 state.
1174 */
1175static void ichac97R3StreamsDestroy(PAC97STATE pThis, PAC97STATER3 pThisCC)
1176{
1177 LogFlowFuncEnter();
1178
1179 /*
1180 * Destroy all AC'97 streams.
1181 */
1182 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
1183 ichac97R3StreamDestroy(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
1184
1185 /*
1186 * Destroy all sinks.
1187 */
1188
1189 PDMAUDIODSTSRCUNION dstSrc;
1190 if (pThisCC->pSinkLineIn)
1191 {
1192 dstSrc.enmSrc = PDMAUDIORECSRC_LINE;
1193 ichac97R3MixerRemoveDrvStreams(pThisCC, pThisCC->pSinkLineIn, PDMAUDIODIR_IN, dstSrc);
1194
1195 AudioMixerSinkDestroy(pThisCC->pSinkLineIn);
1196 pThisCC->pSinkLineIn = NULL;
1197 }
1198
1199 if (pThisCC->pSinkMicIn)
1200 {
1201 dstSrc.enmSrc = PDMAUDIORECSRC_MIC;
1202 ichac97R3MixerRemoveDrvStreams(pThisCC, pThisCC->pSinkMicIn, PDMAUDIODIR_IN, dstSrc);
1203
1204 AudioMixerSinkDestroy(pThisCC->pSinkMicIn);
1205 pThisCC->pSinkMicIn = NULL;
1206 }
1207
1208 if (pThisCC->pSinkOut)
1209 {
1210 dstSrc.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
1211 ichac97R3MixerRemoveDrvStreams(pThisCC, pThisCC->pSinkOut, PDMAUDIODIR_OUT, dstSrc);
1212
1213 AudioMixerSinkDestroy(pThisCC->pSinkOut);
1214 pThisCC->pSinkOut = NULL;
1215 }
1216}
1217
1218/**
1219 * Writes audio data from a mixer sink into an AC'97 stream's DMA buffer.
1220 *
1221 * @returns IPRT status code.
1222 * @param pDstStreamCC The AC'97 stream to write to (ring-3).
1223 * @param pSrcMixSink Mixer sink to get audio data to write from.
1224 * @param cbToWrite Number of bytes to write.
1225 * @param pcbWritten Number of bytes written. Optional.
1226 */
1227static int ichac97R3StreamWrite(PAC97STREAMR3 pDstStreamCC, PAUDMIXSINK pSrcMixSink, uint32_t cbToWrite, uint32_t *pcbWritten)
1228{
1229 AssertPtrReturn(pSrcMixSink, VERR_INVALID_POINTER);
1230 AssertReturn(cbToWrite > 0, VERR_INVALID_PARAMETER);
1231 /* pcbWritten is optional. */
1232
1233 PRTCIRCBUF pCircBuf = pDstStreamCC->State.pCircBuf;
1234 AssertPtr(pCircBuf);
1235
1236 uint32_t cbRead = 0;
1237
1238 void *pvDst;
1239 size_t cbDst;
1240 RTCircBufAcquireWriteBlock(pCircBuf, cbToWrite, &pvDst, &cbDst);
1241
1242 if (cbDst)
1243 {
1244 int rc2 = AudioMixerSinkRead(pSrcMixSink, AUDMIXOP_COPY, pvDst, (uint32_t)cbDst, &cbRead);
1245 AssertRC(rc2);
1246
1247 if (RT_LIKELY(!pDstStreamCC->Dbg.Runtime.fEnabled))
1248 { /* likely */ }
1249 else
1250 DrvAudioHlpFileWrite(pDstStreamCC->Dbg.Runtime.pFileStream, pvDst, cbRead, 0 /* fFlags */);
1251 }
1252
1253 RTCircBufReleaseWriteBlock(pCircBuf, cbRead);
1254
1255 if (pcbWritten)
1256 *pcbWritten = cbRead;
1257
1258 return VINF_SUCCESS;
1259}
1260
1261/**
1262 * Reads audio data from an AC'97 stream's DMA buffer and writes into a specified mixer sink.
1263 *
1264 * @returns IPRT status code.
1265 * @param pSrcStreamCC AC'97 stream to read audio data from (ring-3).
1266 * @param pDstMixSink Mixer sink to write audio data to.
1267 * @param cbToRead Number of bytes to read.
1268 * @param pcbRead Number of bytes read. Optional.
1269 */
1270static int ichac97R3StreamRead(PAC97STREAMR3 pSrcStreamCC, PAUDMIXSINK pDstMixSink, uint32_t cbToRead, uint32_t *pcbRead)
1271{
1272 AssertPtrReturn(pDstMixSink, VERR_INVALID_POINTER);
1273 AssertReturn(cbToRead > 0, VERR_INVALID_PARAMETER);
1274 /* pcbRead is optional. */
1275
1276 PRTCIRCBUF pCircBuf = pSrcStreamCC->State.pCircBuf;
1277 AssertPtr(pCircBuf);
1278
1279 void *pvSrc;
1280 size_t cbSrc;
1281
1282 int rc = VINF_SUCCESS;
1283
1284 uint32_t cbReadTotal = 0;
1285 uint32_t cbLeft = RT_MIN(cbToRead, (uint32_t)RTCircBufUsed(pCircBuf));
1286
1287 while (cbLeft)
1288 {
1289 uint32_t cbWritten = 0;
1290
1291 RTCircBufAcquireReadBlock(pCircBuf, cbLeft, &pvSrc, &cbSrc);
1292
1293 if (cbSrc)
1294 {
1295 if (RT_LIKELY(!pSrcStreamCC->Dbg.Runtime.fEnabled))
1296 { /* likely */ }
1297 else
1298 DrvAudioHlpFileWrite(pSrcStreamCC->Dbg.Runtime.pFileStream, pvSrc, cbSrc, 0 /* fFlags */);
1299
1300 rc = AudioMixerSinkWrite(pDstMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbWritten);
1301 AssertRC(rc);
1302
1303 Assert(cbSrc >= cbWritten);
1304 Log3Func(("[SD%RU8] %RU32/%zu bytes read\n", pSrcStreamCC->u8SD, cbWritten, cbSrc));
1305 }
1306
1307 RTCircBufReleaseReadBlock(pCircBuf, cbWritten);
1308
1309 if ( !cbWritten /* Nothing written? */
1310 || RT_FAILURE(rc))
1311 break;
1312
1313 Assert(cbLeft >= cbWritten);
1314 cbLeft -= cbWritten;
1315
1316 cbReadTotal += cbWritten;
1317 }
1318
1319 if (pcbRead)
1320 *pcbRead = cbReadTotal;
1321
1322 return rc;
1323}
1324
1325# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1326
1327/**
1328 * Asynchronous I/O thread for an AC'97 stream.
1329 * This will do the heavy lifting work for us as soon as it's getting notified by another thread.
1330 *
1331 * @returns IPRT status code.
1332 * @param hThreadSelf Thread handle.
1333 * @param pvUser User argument. Must be of type PAC97STREAMTHREADCTX.
1334 */
1335static DECLCALLBACK(int) ichac97R3StreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
1336{
1337 PAC97STREAMTHREADCTX pCtx = (PAC97STREAMTHREADCTX)pvUser;
1338 AssertPtr(pCtx);
1339
1340 PAC97STATE pThis = pCtx->pThis;
1341 AssertPtr(pThis);
1342
1343 PAC97STATER3 pThisCC = pCtx->pThisCC;
1344 AssertPtr(pThisCC);
1345
1346 PAC97STREAM pStream = pCtx->pStream;
1347 AssertPtr(pStream);
1348
1349 PAC97STREAMR3 pStreamCC = pCtx->pStreamCC;
1350 AssertPtr(pStreamCC);
1351
1352 PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1353
1354 ASMAtomicXchgBool(&pAIO->fStarted, true);
1355
1356 RTThreadUserSignal(hThreadSelf);
1357
1358 LogFunc(("[SD%RU8] Started\n", pStream->u8SD));
1359
1360 for (;;)
1361 {
1362 Log2Func(("[SD%RU8] Waiting ...\n", pStream->u8SD));
1363
1364 int rc2 = RTSemEventWait(pAIO->Event, RT_INDEFINITE_WAIT);
1365 if (RT_FAILURE(rc2))
1366 break;
1367
1368 if (ASMAtomicReadBool(&pAIO->fShutdown))
1369 break;
1370
1371 rc2 = RTCritSectEnter(&pAIO->CritSect);
1372 if (RT_SUCCESS(rc2))
1373 {
1374 if (!pAIO->fEnabled)
1375 {
1376 RTCritSectLeave(&pAIO->CritSect);
1377 continue;
1378 }
1379
1380 ichac97R3StreamUpdate(pThisCC->pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fInTimer */);
1381
1382 int rc3 = RTCritSectLeave(&pAIO->CritSect);
1383 AssertRC(rc3);
1384 }
1385
1386 AssertRC(rc2);
1387 }
1388
1389 LogFunc(("[SD%RU8] Ended\n", pStream->u8SD));
1390
1391 ASMAtomicXchgBool(&pAIO->fStarted, false);
1392
1393 RTMemFree(pCtx);
1394 pCtx = NULL;
1395
1396 return VINF_SUCCESS;
1397}
1398
1399/**
1400 * Creates the async I/O thread for a specific AC'97 audio stream.
1401 *
1402 * @returns IPRT status code.
1403 * @param pThis The shared AC'97 state (shared).
1404 * @param pThisCC The shared AC'97 state (ring-3).
1405 * @param pStream AC'97 audio stream to create the async I/O thread for (shared).
1406 * @param pStreamCC AC'97 audio stream to create the async I/O thread for (ring-3).
1407 */
1408static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1409{
1410 PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1411
1412 int rc;
1413
1414 if (!ASMAtomicReadBool(&pAIO->fStarted))
1415 {
1416 pAIO->fShutdown = false;
1417 pAIO->fEnabled = true; /* Enabled by default. */
1418
1419 rc = RTSemEventCreate(&pAIO->Event);
1420 if (RT_SUCCESS(rc))
1421 {
1422 rc = RTCritSectInit(&pAIO->CritSect);
1423 if (RT_SUCCESS(rc))
1424 {
1425/** @todo r=bird:
1426 * Why aren't this code using the PDM threads (PDMDevHlpThreadCreate)?
1427 * They would help you with managing stuff like VM suspending, resuming
1428 * and powering off.
1429 *
1430 * Finally, just create the threads at construction time. */
1431 PAC97STREAMTHREADCTX pCtx = (PAC97STREAMTHREADCTX)RTMemAllocZ(sizeof(AC97STREAMTHREADCTX));
1432 if (pCtx)
1433 {
1434 pCtx->pStream = pStream;
1435 pCtx->pStreamCC = pStreamCC;
1436 pCtx->pThis = pThis;
1437 pCtx->pThisCC = pThisCC;
1438
1439 rc = RTThreadCreateF(&pAIO->Thread, ichac97R3StreamAsyncIOThread, pCtx,
1440 0, RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, "ac97AIO%RU8", pStreamCC->u8SD);
1441 if (RT_SUCCESS(rc))
1442 rc = RTThreadUserWait(pAIO->Thread, 30 * 1000 /* 30s timeout */);
1443 }
1444 else
1445 rc = VERR_NO_MEMORY;
1446 }
1447 }
1448 }
1449 else
1450 rc = VINF_SUCCESS;
1451
1452 LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamCC->u8SD, rc));
1453 return rc;
1454}
1455
1456/**
1457 * Lets the stream's async I/O thread know that there is some data to process.
1458 *
1459 * @returns IPRT status code.
1460 * @param pStreamCC The AC'97 stream to notify async I/O thread
1461 * for (ring-3).
1462 */
1463static int ichac97R3StreamAsyncIONotify(PAC97STREAMR3 pStreamCC)
1464{
1465 LogFunc(("[SD%RU8]\n", pStreamCC->u8SD));
1466 return RTSemEventSignal(pStreamCC->State.AIO.Event);
1467}
1468
1469/**
1470 * Destroys the async I/O thread of a specific AC'97 audio stream.
1471 *
1472 * @returns IPRT status code.
1473 * @param pThis The shared AC'97 state.
1474 * @param pStreamCC AC'97 audio stream to destroy the async I/O thread for.
1475 */
1476static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAMR3 pStreamR3)
1477{
1478 RT_NOREF(pThis);
1479
1480 PAC97STREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
1481
1482 if (!ASMAtomicReadBool(&pAIO->fStarted))
1483 return VINF_SUCCESS;
1484
1485 ASMAtomicWriteBool(&pAIO->fShutdown, true);
1486
1487 int rc = ichac97R3StreamAsyncIONotify(pStreamR3);
1488 AssertRC(rc);
1489
1490 int rcThread;
1491 rc = RTThreadWait(pAIO->Thread, 30 * 1000 /* 30s timeout */, &rcThread);
1492 LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
1493
1494 if (RT_SUCCESS(rc))
1495 {
1496 rc = RTCritSectDelete(&pAIO->CritSect);
1497 AssertRC(rc);
1498
1499 rc = RTSemEventDestroy(pAIO->Event);
1500 AssertRC(rc);
1501
1502 pAIO->fStarted = false;
1503 pAIO->fShutdown = false;
1504 pAIO->fEnabled = false;
1505 }
1506
1507 LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamR3->u8SD, rc));
1508 return rc;
1509}
1510
1511/**
1512 * Locks the async I/O thread of a specific AC'97 audio stream.
1513 *
1514 * @param pStreamCC AC'97 stream to lock async I/O thread for.
1515 */
1516static void ichac97R3StreamAsyncIOLock(PAC97STREAMR3 pStreamCC)
1517{
1518 PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1519
1520 if (!ASMAtomicReadBool(&pAIO->fStarted))
1521 return;
1522
1523 int rc2 = RTCritSectEnter(&pAIO->CritSect);
1524 AssertRC(rc2);
1525}
1526
1527/**
1528 * Unlocks the async I/O thread of a specific AC'97 audio stream.
1529 *
1530 * @param pStreamCC AC'97 stream to unlock async I/O thread for.
1531 */
1532static void ichac97R3StreamAsyncIOUnlock(PAC97STREAMR3 pStreamCC)
1533{
1534 PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1535
1536 if (!ASMAtomicReadBool(&pAIO->fStarted))
1537 return;
1538
1539 int rc2 = RTCritSectLeave(&pAIO->CritSect);
1540 AssertRC(rc2);
1541}
1542
1543#if 0 /* Unused */
1544/**
1545 * Enables (resumes) or disables (pauses) the async I/O thread.
1546 *
1547 * @param pStream AC'97 stream to enable/disable async I/O thread for.
1548 * @param fEnable Whether to enable or disable the I/O thread.
1549 *
1550 * @remarks Does not do locking.
1551 */
1552static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable)
1553{
1554 PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1555 ASMAtomicXchgBool(&pAIO->fEnabled, fEnable);
1556}
1557#endif
1558# endif /* VBOX_WITH_AUDIO_AC97_ASYNC_IO */
1559
1560# ifdef LOG_ENABLED
1561static void ichac97R3BDLEDumpAll(PPDMDEVINS pDevIns, uint64_t u64BDLBase, uint16_t cBDLE)
1562{
1563 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
1564 if (!u64BDLBase)
1565 return;
1566
1567 uint32_t cbBDLE = 0;
1568 for (uint16_t i = 0; i < cBDLE; i++)
1569 {
1570 AC97BDLE BDLE;
1571 PDMDevHlpPhysRead(pDevIns, u64BDLBase + i * sizeof(AC97BDLE), &BDLE, sizeof(AC97BDLE));
1572
1573# ifndef RT_LITTLE_ENDIAN
1574# error "Please adapt the code (audio buffers are little endian)!"
1575# else
1576 BDLE.addr = RT_H2LE_U32(BDLE.addr & ~3);
1577 BDLE.ctl_len = RT_H2LE_U32(BDLE.ctl_len);
1578#endif
1579 LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32 [%RU32 bytes], bup:%RTbool, ioc:%RTbool)\n",
1580 i, BDLE.addr,
1581 BDLE.ctl_len & AC97_BD_LEN_MASK,
1582 (BDLE.ctl_len & AC97_BD_LEN_MASK) << 1, /** @todo r=andy Assumes 16bit samples. */
1583 RT_BOOL(BDLE.ctl_len & AC97_BD_BUP),
1584 RT_BOOL(BDLE.ctl_len & AC97_BD_IOC)));
1585
1586 cbBDLE += (BDLE.ctl_len & AC97_BD_LEN_MASK) << 1; /** @todo r=andy Ditto. */
1587 }
1588
1589 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
1590}
1591# endif /* LOG_ENABLED */
1592
1593/**
1594 * Updates an AC'97 stream by doing its required data transfers.
1595 * The host sink(s) set the overall pace.
1596 *
1597 * This routine is called by both, the synchronous and the asynchronous
1598 * (VBOX_WITH_AUDIO_AC97_ASYNC_IO), implementations.
1599 *
1600 * When running synchronously, the device DMA transfers *and* the mixer sink
1601 * processing is within the device timer.
1602 *
1603 * When running asynchronously, only the device DMA transfers are done in the
1604 * device timer, whereas the mixer sink processing then is done in the stream's
1605 * own async I/O thread. This thread also will call this function
1606 * (with fInTimer set to @c false).
1607 *
1608 * @param pDevIns The device instance.
1609 * @param pThis The shared AC'97 state.
1610 * @param pThisCC The ring-3 AC'97 state.
1611 * @param pStream The AC'97 stream to update (shared).
1612 * @param pStreamCC The AC'97 stream to update (ring-3).
1613 * @param fInTimer Whether to this function was called from the timer
1614 * context or an asynchronous I/O stream thread (if supported).
1615 */
1616static void ichac97R3StreamUpdate(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
1617 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fInTimer)
1618{
1619 RT_NOREF(fInTimer);
1620
1621 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
1622 AssertPtr(pSink);
1623
1624 if (!AudioMixerSinkIsActive(pSink)) /* No sink available? Bail out. */
1625 return;
1626
1627 int rc2;
1628
1629 if (pStreamCC->State.Cfg.enmDir == PDMAUDIODIR_OUT) /* Output (SDO). */
1630 {
1631# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1632 if (fInTimer)
1633# endif
1634 {
1635 const uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1636 if (cbStreamFree)
1637 {
1638 Log3Func(("[SD%RU8] PICB=%zu (%RU64ms), cbFree=%zu (%RU64ms), cbTransferChunk=%zu (%RU64ms)\n",
1639 pStream->u8SD,
1640 (pStream->Regs.picb << 1), DrvAudioHlpBytesToMilli((pStream->Regs.picb << 1), &pStreamCC->State.Cfg.Props),
1641 cbStreamFree, DrvAudioHlpBytesToMilli(cbStreamFree, &pStreamCC->State.Cfg.Props),
1642 pStreamCC->State.cbTransferChunk, DrvAudioHlpBytesToMilli(pStreamCC->State.cbTransferChunk, &pStreamCC->State.Cfg.Props)));
1643
1644 /* Do the DMA transfer. */
1645 rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC,
1646 RT_MIN(pStreamCC->State.cbTransferChunk, cbStreamFree));
1647 AssertRC(rc2);
1648
1649 pStreamCC->State.tsLastUpdateNs = RTTimeNanoTS();
1650 }
1651 }
1652
1653 Log3Func(("[SD%RU8] fInTimer=%RTbool\n", pStream->u8SD, fInTimer));
1654
1655# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1656 rc2 = ichac97R3StreamAsyncIONotify(pStreamCC);
1657 AssertRC(rc2);
1658# endif
1659
1660# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1661 if (!fInTimer) /* In async I/O thread */
1662 {
1663# endif
1664 const uint32_t cbSinkWritable = AudioMixerSinkGetWritable(pSink);
1665 const uint32_t cbStreamReadable = ichac97R3StreamGetUsed(pStreamCC);
1666 const uint32_t cbToReadFromStream = RT_MIN(cbStreamReadable, cbSinkWritable);
1667
1668 Log3Func(("[SD%RU8] cbSinkWritable=%RU32, cbStreamReadable=%RU32\n", pStream->u8SD, cbSinkWritable, cbStreamReadable));
1669
1670 if (cbToReadFromStream)
1671 {
1672 /* Read (guest output) data and write it to the stream's sink. */
1673 rc2 = ichac97R3StreamRead(pStreamCC, pSink, cbToReadFromStream, NULL /* pcbRead */);
1674 AssertRC(rc2);
1675 }
1676# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1677 }
1678#endif
1679 /* When running synchronously, update the associated sink here.
1680 * Otherwise this will be done in the async I/O thread. */
1681 rc2 = AudioMixerSinkUpdate(pSink);
1682 AssertRC(rc2);
1683 }
1684 else /* Input (SDI). */
1685 {
1686# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1687 if (!fInTimer)
1688 {
1689# endif
1690 rc2 = AudioMixerSinkUpdate(pSink);
1691 AssertRC(rc2);
1692
1693 /* Is the sink ready to be read (host input data) from? If so, by how much? */
1694 uint32_t cbSinkReadable = AudioMixerSinkGetReadable(pSink);
1695
1696 /* How much (guest input) data is available for writing at the moment for the AC'97 stream? */
1697 uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1698
1699 Log3Func(("[SD%RU8] cbSinkReadable=%RU32, cbStreamFree=%RU32\n", pStream->u8SD, cbSinkReadable, cbStreamFree));
1700
1701 /* Do not read more than the sink can provide at the moment.
1702 * The host sets the overall pace. */
1703 if (cbSinkReadable > cbStreamFree)
1704 cbSinkReadable = cbStreamFree;
1705
1706 if (cbSinkReadable)
1707 {
1708 /* Write (guest input) data to the stream which was read from stream's sink before. */
1709 rc2 = ichac97R3StreamWrite(pStreamCC, pSink, cbSinkReadable, NULL /* pcbWritten */);
1710 AssertRC(rc2);
1711 }
1712# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1713 }
1714 else /* fInTimer */
1715 {
1716# endif
1717
1718# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1719 const uint64_t tsNowNs = RTTimeNanoTS();
1720 if (tsNowNs - pStreamCC->State.tsLastUpdateNs >= pStreamCC->State.Cfg.Device.cMsSchedulingHint * RT_NS_1MS)
1721 {
1722 rc2 = ichac97R3StreamAsyncIONotify(pStreamCC);
1723 AssertRC(rc2);
1724
1725 pStreamCC->State.tsLastUpdateNs = tsNowNs;
1726 }
1727# endif
1728
1729 const uint32_t cbStreamUsed = ichac97R3StreamGetUsed(pStreamCC);
1730 if (cbStreamUsed)
1731 {
1732 /* When running synchronously, do the DMA data transfers here.
1733 * Otherwise this will be done in the stream's async I/O thread. */
1734 rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC, cbStreamUsed);
1735 AssertRC(rc2);
1736 }
1737# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1738 }
1739# endif
1740 }
1741}
1742
1743#endif /* IN_RING3 */
1744
1745/**
1746 * Sets a AC'97 mixer control to a specific value.
1747 *
1748 * @returns IPRT status code.
1749 * @param pThis The shared AC'97 state.
1750 * @param uMixerIdx Mixer control to set value for.
1751 * @param uVal Value to set.
1752 */
1753static void ichac97MixerSet(PAC97STATE pThis, uint8_t uMixerIdx, uint16_t uVal)
1754{
1755 AssertMsgReturnVoid(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1756 ("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)));
1757
1758 LogRel2(("AC97: Setting mixer index #%RU8 to %RU16 (%RU8 %RU8)\n",
1759 uMixerIdx, uVal, RT_HI_U8(uVal), RT_LO_U8(uVal)));
1760
1761 pThis->mixer_data[uMixerIdx + 0] = RT_LO_U8(uVal);
1762 pThis->mixer_data[uMixerIdx + 1] = RT_HI_U8(uVal);
1763}
1764
1765/**
1766 * Gets a value from a specific AC'97 mixer control.
1767 *
1768 * @returns Retrieved mixer control value.
1769 * @param pThis The shared AC'97 state.
1770 * @param uMixerIdx Mixer control to get value for.
1771 */
1772static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t uMixerIdx)
1773{
1774 AssertMsgReturn(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1775 ("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)),
1776 UINT16_MAX);
1777 return RT_MAKE_U16(pThis->mixer_data[uMixerIdx + 0], pThis->mixer_data[uMixerIdx + 1]);
1778}
1779
1780#ifdef IN_RING3
1781
1782/**
1783 * Retrieves a specific driver stream of a AC'97 driver.
1784 *
1785 * @returns Pointer to driver stream if found, or NULL if not found.
1786 * @param pDrv Driver to retrieve driver stream for.
1787 * @param enmDir Stream direction to retrieve.
1788 * @param dstSrc Stream destination / source to retrieve.
1789 */
1790static PAC97DRIVERSTREAM ichac97R3MixerGetDrvStream(PAC97DRIVER pDrv, PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc)
1791{
1792 PAC97DRIVERSTREAM pDrvStream = NULL;
1793
1794 if (enmDir == PDMAUDIODIR_IN)
1795 {
1796 LogFunc(("enmRecSource=%d\n", dstSrc.enmSrc));
1797
1798 switch (dstSrc.enmSrc)
1799 {
1800 case PDMAUDIORECSRC_LINE:
1801 pDrvStream = &pDrv->LineIn;
1802 break;
1803 case PDMAUDIORECSRC_MIC:
1804 pDrvStream = &pDrv->MicIn;
1805 break;
1806 default:
1807 AssertFailed();
1808 break;
1809 }
1810 }
1811 else if (enmDir == PDMAUDIODIR_OUT)
1812 {
1813 LogFunc(("enmPlaybackDest=%d\n", dstSrc.enmDst));
1814
1815 switch (dstSrc.enmDst)
1816 {
1817 case PDMAUDIOPLAYBACKDST_FRONT:
1818 pDrvStream = &pDrv->Out;
1819 break;
1820 default:
1821 AssertFailed();
1822 break;
1823 }
1824 }
1825 else
1826 AssertFailed();
1827
1828 return pDrvStream;
1829}
1830
1831/**
1832 * Adds a driver stream to a specific mixer sink.
1833 *
1834 * @returns IPRT status code.
1835 * @param pMixSink Mixer sink to add driver stream to.
1836 * @param pCfg Stream configuration to use.
1837 * @param pDrv Driver stream to add.
1838 */
1839static int ichac97R3MixerAddDrvStream(PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PAC97DRIVER pDrv)
1840{
1841 AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1842
1843 PPDMAUDIOSTREAMCFG pStreamCfg = DrvAudioHlpStreamCfgDup(pCfg);
1844 if (!pStreamCfg)
1845 return VERR_NO_MEMORY;
1846
1847 if (!RTStrPrintf(pStreamCfg->szName, sizeof(pStreamCfg->szName), "%s", pCfg->szName))
1848 {
1849 DrvAudioHlpStreamCfgFree(pStreamCfg);
1850 return VERR_BUFFER_OVERFLOW;
1851 }
1852
1853 LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
1854
1855 int rc;
1856
1857 PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, pStreamCfg->enmDir, pStreamCfg->u);
1858 if (pDrvStream)
1859 {
1860 AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
1861
1862 PAUDMIXSTREAM pMixStrm;
1863 rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
1864 LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1865 if (RT_SUCCESS(rc))
1866 {
1867 rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
1868 LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1869 if (RT_SUCCESS(rc))
1870 {
1871 /* If this is an input stream, always set the latest (added) stream
1872 * as the recording source. */
1873 /** @todo Make the recording source dynamic (CFGM?). */
1874 if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
1875 {
1876 PDMAUDIOBACKENDCFG Cfg;
1877 rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
1878 if (RT_SUCCESS(rc))
1879 {
1880 if (Cfg.cMaxStreamsIn) /* At least one input source available? */
1881 {
1882 rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
1883 LogFlowFunc(("LUN#%RU8: Recording source for '%s' -> '%s', rc=%Rrc\n",
1884 pDrv->uLUN, pStreamCfg->szName, Cfg.szName, rc));
1885
1886 if (RT_SUCCESS(rc))
1887 LogRel2(("AC97: Set recording source for '%s' to '%s'\n", pStreamCfg->szName, Cfg.szName));
1888 }
1889 else
1890 LogRel(("AC97: Backend '%s' currently is not offering any recording source for '%s'\n",
1891 Cfg.szName, pStreamCfg->szName));
1892 }
1893 else if (RT_FAILURE(rc))
1894 LogFunc(("LUN#%RU8: Unable to retrieve backend configuratio for '%s', rc=%Rrc\n",
1895 pDrv->uLUN, pStreamCfg->szName, rc));
1896 }
1897 /** @todo r=bird: see below. */
1898 if (RT_FAILURE(rc))
1899 AudioMixerSinkRemoveStream(pMixSink, pMixStrm);
1900 }
1901 /** @todo r=bird: I've added this destroy stuff here, because if it looks as if
1902 * you just drop the stream if the AudioMixerSinkAddStream fails for some
1903 * reason. This is definitely true if AudioMixerSinkSetRecordingSource fails
1904 * above, because it leads to duplicate statistics when starting XP with ICH97
1905 * and VRDP enabled. Looks like the VRDP line-in fails with
1906 * VERR_AUDIO_STREAM_NOT_READY when configured for 8000HZ, then it asserts in
1907 * STAM when 48000Hz is configured right afterwards. */
1908 if (RT_FAILURE(rc))
1909 AudioMixerStreamDestroy(pMixStrm);
1910 }
1911
1912 if (RT_SUCCESS(rc))
1913 pDrvStream->pMixStrm = pMixStrm;
1914 }
1915 else
1916 rc = VERR_INVALID_PARAMETER;
1917
1918 DrvAudioHlpStreamCfgFree(pStreamCfg);
1919
1920 LogFlowFuncLeaveRC(rc);
1921 return rc;
1922}
1923
1924/**
1925 * Adds all current driver streams to a specific mixer sink.
1926 *
1927 * @returns IPRT status code.
1928 * @param pThisCC The ring-3 AC'97 state.
1929 * @param pMixSink Mixer sink to add stream to.
1930 * @param pCfg Stream configuration to use.
1931 */
1932static int ichac97R3MixerAddDrvStreams(PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
1933{
1934 AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1935
1936 if (!DrvAudioHlpStreamCfgIsValid(pCfg))
1937 return VERR_INVALID_PARAMETER;
1938
1939 int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
1940 if (RT_FAILURE(rc))
1941 return rc;
1942
1943 PAC97DRIVER pDrv;
1944 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
1945 {
1946 int rc2 = ichac97R3MixerAddDrvStream(pMixSink, pCfg, pDrv);
1947 if (RT_FAILURE(rc2))
1948 LogFunc(("Attaching stream failed with %Rrc\n", rc2));
1949
1950 /* Do not pass failure to rc here, as there might be drivers which aren't
1951 * configured / ready yet. */
1952 }
1953
1954 LogFlowFuncLeaveRC(rc);
1955 return rc;
1956}
1957
1958/**
1959 * Adds a specific AC'97 driver to the driver chain.
1960 *
1961 * @return IPRT status code.
1962 * @param pThisCC The ring-3 AC'97 device state.
1963 * @param pDrv The AC'97 driver to add.
1964 */
1965static int ichac97R3MixerAddDrv(PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
1966{
1967 int rc = VINF_SUCCESS;
1968
1969 if (DrvAudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg))
1970 rc = ichac97R3MixerAddDrvStream(pThisCC->pSinkLineIn, &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg, pDrv);
1971
1972 if (DrvAudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg))
1973 {
1974 int rc2 = ichac97R3MixerAddDrvStream(pThisCC->pSinkOut, &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg, pDrv);
1975 if (RT_SUCCESS(rc))
1976 rc = rc2;
1977 }
1978
1979 if (DrvAudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg))
1980 {
1981 int rc2 = ichac97R3MixerAddDrvStream(pThisCC->pSinkMicIn, &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg, pDrv);
1982 if (RT_SUCCESS(rc))
1983 rc = rc2;
1984 }
1985
1986 return rc;
1987}
1988
1989/**
1990 * Removes a specific AC'97 driver from the driver chain and destroys its
1991 * associated streams.
1992 *
1993 * @param pThisCC The ring-3 AC'97 device state.
1994 * @param pDrv AC'97 driver to remove.
1995 */
1996static void ichac97R3MixerRemoveDrv(PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
1997{
1998 if (pDrv->MicIn.pMixStrm)
1999 {
2000 if (AudioMixerSinkGetRecordingSource(pThisCC->pSinkMicIn) == pDrv->MicIn.pMixStrm)
2001 AudioMixerSinkSetRecordingSource(pThisCC->pSinkMicIn, NULL);
2002
2003 AudioMixerSinkRemoveStream(pThisCC->pSinkMicIn, pDrv->MicIn.pMixStrm);
2004 AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm);
2005 pDrv->MicIn.pMixStrm = NULL;
2006 }
2007
2008 if (pDrv->LineIn.pMixStrm)
2009 {
2010 if (AudioMixerSinkGetRecordingSource(pThisCC->pSinkLineIn) == pDrv->LineIn.pMixStrm)
2011 AudioMixerSinkSetRecordingSource(pThisCC->pSinkLineIn, NULL);
2012
2013 AudioMixerSinkRemoveStream(pThisCC->pSinkLineIn, pDrv->LineIn.pMixStrm);
2014 AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm);
2015 pDrv->LineIn.pMixStrm = NULL;
2016 }
2017
2018 if (pDrv->Out.pMixStrm)
2019 {
2020 AudioMixerSinkRemoveStream(pThisCC->pSinkOut, pDrv->Out.pMixStrm);
2021 AudioMixerStreamDestroy(pDrv->Out.pMixStrm);
2022 pDrv->Out.pMixStrm = NULL;
2023 }
2024
2025 RTListNodeRemove(&pDrv->Node);
2026}
2027
2028/**
2029 * Removes a driver stream from a specific mixer sink.
2030 *
2031 * @param pMixSink Mixer sink to remove audio streams from.
2032 * @param enmDir Stream direction to remove.
2033 * @param dstSrc Stream destination / source to remove.
2034 * @param pDrv Driver stream to remove.
2035 */
2036static void ichac97R3MixerRemoveDrvStream(PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc, PAC97DRIVER pDrv)
2037{
2038 PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, enmDir, dstSrc);
2039 if (pDrvStream)
2040 {
2041 if (pDrvStream->pMixStrm)
2042 {
2043 AudioMixerSinkRemoveStream(pMixSink, pDrvStream->pMixStrm);
2044
2045 AudioMixerStreamDestroy(pDrvStream->pMixStrm);
2046 pDrvStream->pMixStrm = NULL;
2047 }
2048 }
2049}
2050
2051/**
2052 * Removes all driver streams from a specific mixer sink.
2053 *
2054 * @param pThisCC The ring-3 AC'97 state.
2055 * @param pMixSink Mixer sink to remove audio streams from.
2056 * @param enmDir Stream direction to remove.
2057 * @param dstSrc Stream destination / source to remove.
2058 */
2059static void ichac97R3MixerRemoveDrvStreams(PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
2060 PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc)
2061{
2062 AssertPtrReturnVoid(pMixSink);
2063
2064 PAC97DRIVER pDrv;
2065 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
2066 {
2067 ichac97R3MixerRemoveDrvStream(pMixSink, enmDir, dstSrc, pDrv);
2068 }
2069}
2070
2071/**
2072 * Calculates and returns the ticks for a specified amount of bytes.
2073 *
2074 * @returns Calculated ticks
2075 * @param pDevIns The device instance.
2076 * @param pStream AC'97 stream to calculate ticks for (shared).
2077 * @param pStreamCC AC'97 stream to calculate ticks for (ring-3).
2078 * @param cbBytes Bytes to calculate ticks for.
2079 */
2080static uint64_t ichac97R3StreamTransferCalcNext(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint32_t cbBytes)
2081{
2082 if (!cbBytes)
2083 return 0;
2084
2085 const uint64_t usBytes = DrvAudioHlpBytesToMicro(cbBytes, &pStreamCC->State.Cfg.Props);
2086 const uint64_t cTransferTicks = PDMDevHlpTimerFromMicro(pDevIns, pStream->hTimer, usBytes);
2087
2088 Log3Func(("[SD%RU8] Timer %uHz, cbBytes=%RU32 -> usBytes=%RU64, cTransferTicks=%RU64\n",
2089 pStream->u8SD, pStreamCC->State.uTimerHz, cbBytes, usBytes, cTransferTicks));
2090
2091 return cTransferTicks;
2092}
2093
2094/**
2095 * Updates the next transfer based on a specific amount of bytes.
2096 *
2097 * @param pDevIns The device instance.
2098 * @param pStream The AC'97 stream to update (shared).
2099 * @param pStreamCC The AC'97 stream to update (ring-3).
2100 * @param cbBytes Bytes to update next transfer for.
2101 */
2102static void ichac97R3StreamTransferUpdate(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint32_t cbBytes)
2103{
2104 if (!cbBytes)
2105 return;
2106
2107 /* Calculate the bytes we need to transfer to / from the stream's DMA per iteration.
2108 * This is bound to the device's Hz rate and thus to the (virtual) timing the device expects. */
2109 pStreamCC->State.cbTransferChunk = cbBytes;
2110
2111 /* Update the transfer ticks. */
2112 pStreamCC->State.cTransferTicks = ichac97R3StreamTransferCalcNext(pDevIns, pStream, pStreamCC,
2113 pStreamCC->State.cbTransferChunk);
2114 Assert(pStreamCC->State.cTransferTicks); /* Paranoia. */
2115}
2116
2117/**
2118 * Opens an AC'97 stream with its current mixer settings.
2119 *
2120 * This will open an AC'97 stream with 2 (stereo) channels, 16-bit samples and
2121 * the last set sample rate in the AC'97 mixer for this stream.
2122 *
2123 * @returns IPRT status code.
2124 * @param pThis The shared AC'97 device state (shared).
2125 * @param pThisCC The shared AC'97 device state (ring-3).
2126 * @param pStream The AC'97 stream to open (shared).
2127 * @param pStreamCC The AC'97 stream to open (ring-3).
2128 * @param fForce Whether to force re-opening the stream or not.
2129 * Otherwise re-opening only will happen if the PCM properties have changed.
2130 */
2131static int ichac97R3StreamOpen(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2132{
2133 PDMAUDIOSTREAMCFG Cfg;
2134 RT_ZERO(Cfg);
2135 Cfg.Props.cChannels = 2;
2136 Cfg.Props.cbSample = 2 /* 16-bit */;
2137 Cfg.Props.fSigned = true;
2138 Cfg.Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(Cfg.Props.cbSample, Cfg.Props.cChannels);
2139
2140 int rc = VINF_SUCCESS;
2141 PAUDMIXSINK pMixSink;
2142 switch (pStream->u8SD)
2143 {
2144 case AC97SOUNDSOURCE_PI_INDEX:
2145 {
2146 Cfg.Props.uHz = ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate);
2147 Cfg.enmDir = PDMAUDIODIR_IN;
2148 Cfg.u.enmSrc = PDMAUDIORECSRC_LINE;
2149 Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2150 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Line-In");
2151
2152 pMixSink = pThisCC->pSinkLineIn;
2153 break;
2154 }
2155
2156 case AC97SOUNDSOURCE_MC_INDEX:
2157 {
2158 Cfg.Props.uHz = ichac97MixerGet(pThis, AC97_MIC_ADC_Rate);
2159 Cfg.enmDir = PDMAUDIODIR_IN;
2160 Cfg.u.enmSrc = PDMAUDIORECSRC_MIC;
2161 Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2162 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Mic-In");
2163
2164 pMixSink = pThisCC->pSinkMicIn;
2165 break;
2166 }
2167
2168 case AC97SOUNDSOURCE_PO_INDEX:
2169 {
2170 Cfg.Props.uHz = ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate);
2171 Cfg.enmDir = PDMAUDIODIR_OUT;
2172 Cfg.u.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
2173 Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2174 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Output");
2175
2176 pMixSink = pThisCC->pSinkOut;
2177 break;
2178 }
2179
2180 default:
2181 rc = VERR_NOT_SUPPORTED;
2182 pMixSink = NULL;
2183 break;
2184 }
2185
2186 if (RT_SUCCESS(rc))
2187 {
2188 /* Only (re-)create the stream (and driver chain) if we really have to.
2189 * Otherwise avoid this and just reuse it, as this costs performance. */
2190 if ( !DrvAudioHlpPCMPropsAreEqual(&Cfg.Props, &pStreamCC->State.Cfg.Props)
2191 || fForce)
2192 {
2193 LogRel2(("AC97: (Re-)Opening stream '%s' (%RU32Hz, %RU8 channels, %s%RU8)\n",
2194 Cfg.szName, Cfg.Props.uHz, Cfg.Props.cChannels, Cfg.Props.fSigned ? "S" : "U", Cfg.Props.cbSample * 8));
2195
2196 LogFlowFunc(("[SD%RU8] uHz=%RU32\n", pStream->u8SD, Cfg.Props.uHz));
2197
2198 if (Cfg.Props.uHz)
2199 {
2200 Assert(Cfg.enmDir != PDMAUDIODIR_UNKNOWN);
2201
2202 /*
2203 * Set the stream's timer Hz rate, based on the PCM properties Hz rate.
2204 */
2205 if (pThis->uTimerHz == AC97_TIMER_HZ_DEFAULT) /* Make sure that we don't have any custom Hz rate set we want to enforce */
2206 {
2207 if (Cfg.Props.uHz > 44100) /* E.g. 48000 Hz. */
2208 pStreamCC->State.uTimerHz = 200;
2209 else /* Just take the global Hz rate otherwise. */
2210 pStreamCC->State.uTimerHz = pThis->uTimerHz;
2211 }
2212 else
2213 pStreamCC->State.uTimerHz = pThis->uTimerHz;
2214
2215 /* Set scheduling hint (if available). */
2216 if (pStreamCC->State.uTimerHz)
2217 Cfg.Device.cMsSchedulingHint = 1000 /* ms */ / pStreamCC->State.uTimerHz;
2218
2219 if (pStreamCC->State.pCircBuf)
2220 {
2221 RTCircBufDestroy(pStreamCC->State.pCircBuf);
2222 pStreamCC->State.pCircBuf = NULL;
2223 }
2224
2225 rc = RTCircBufCreate(&pStreamCC->State.pCircBuf, DrvAudioHlpMilliToBytes(100 /* ms */, &Cfg.Props)); /** @todo Make this configurable. */
2226 if (RT_SUCCESS(rc))
2227 {
2228 ichac97R3MixerRemoveDrvStreams(pThisCC, pMixSink, Cfg.enmDir, Cfg.u);
2229
2230 rc = ichac97R3MixerAddDrvStreams(pThisCC, pMixSink, &Cfg);
2231 if (RT_SUCCESS(rc))
2232 rc = DrvAudioHlpStreamCfgCopy(&pStreamCC->State.Cfg, &Cfg);
2233 }
2234 }
2235 }
2236 else
2237 LogFlowFunc(("[SD%RU8] Skipping (re-)creation\n", pStream->u8SD));
2238 }
2239
2240 LogFlowFunc(("[SD%RU8] rc=%Rrc\n", pStream->u8SD, rc));
2241 return rc;
2242}
2243
2244/**
2245 * Closes an AC'97 stream.
2246 *
2247 * @returns IPRT status code.
2248 * @param pStream The AC'97 stream to close (shared).
2249 */
2250static int ichac97R3StreamClose(PAC97STREAM pStream)
2251{
2252 RT_NOREF(pStream);
2253 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2254 return VINF_SUCCESS;
2255}
2256
2257/**
2258 * Re-opens (that is, closes and opens again) an AC'97 stream on the backend
2259 * side with the current AC'97 mixer settings for this stream.
2260 *
2261 * @returns IPRT status code.
2262 * @param pThis The shared AC'97 device state.
2263 * @param pThisCC The ring-3 AC'97 device state.
2264 * @param pStream The AC'97 stream to re-open (shared).
2265 * @param pStreamCC The AC'97 stream to re-open (ring-3).
2266 * @param fForce Whether to force re-opening the stream or not.
2267 * Otherwise re-opening only will happen if the PCM properties have changed.
2268 */
2269static int ichac97R3StreamReOpen(PAC97STATE pThis, PAC97STATER3 pThisCC,
2270 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2271{
2272 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2273 Assert(pStream->u8SD == pStreamCC->u8SD);
2274 Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2275 Assert(pStreamCC - &pThisCC->aStreams[0] == pStream->u8SD);
2276
2277 int rc = ichac97R3StreamClose(pStream);
2278 if (RT_SUCCESS(rc))
2279 rc = ichac97R3StreamOpen(pThis, pThisCC, pStream, pStreamCC, fForce);
2280
2281 return rc;
2282}
2283
2284/**
2285 * Locks an AC'97 stream for serialized access.
2286 *
2287 * @returns IPRT status code.
2288 * @param pStreamCC The AC'97 stream to lock (ring-3).
2289 */
2290static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC)
2291{
2292 int rc2 = RTCritSectEnter(&pStreamCC->State.CritSect);
2293 AssertRC(rc2);
2294}
2295
2296/**
2297 * Unlocks a formerly locked AC'97 stream.
2298 *
2299 * @returns IPRT status code.
2300 * @param pStreamCC The AC'97 stream to unlock (ring-3).
2301 */
2302static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC)
2303{
2304 int rc2 = RTCritSectLeave(&pStreamCC->State.CritSect);
2305 AssertRC(rc2);
2306}
2307
2308/**
2309 * Retrieves the available size of (buffered) audio data (in bytes) of a given AC'97 stream.
2310 *
2311 * @returns Available data (in bytes).
2312 * @param pStreamCC The AC'97 stream to retrieve size for (ring-3).
2313 */
2314static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC)
2315{
2316 if (!pStreamCC->State.pCircBuf)
2317 return 0;
2318
2319 return (uint32_t)RTCircBufUsed(pStreamCC->State.pCircBuf);
2320}
2321
2322/**
2323 * Retrieves the free size of audio data (in bytes) of a given AC'97 stream.
2324 *
2325 * @returns Free data (in bytes).
2326 * @param pStreamCC AC'97 stream to retrieve size for (ring-3).
2327 */
2328static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC)
2329{
2330 if (!pStreamCC->State.pCircBuf)
2331 return 0;
2332
2333 return (uint32_t)RTCircBufFree(pStreamCC->State.pCircBuf);
2334}
2335
2336/**
2337 * Sets the volume of a specific AC'97 mixer control.
2338 *
2339 * This currently only supports attenuation -- gain support is currently not implemented.
2340 *
2341 * @returns IPRT status code.
2342 * @param pThis The shared AC'97 state.
2343 * @param pThisCC The ring-3 AC'97 state.
2344 * @param index AC'97 mixer index to set volume for.
2345 * @param enmMixerCtl Corresponding audio mixer sink.
2346 * @param uVal Volume value to set.
2347 */
2348static int ichac97R3MixerSetVolume(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2349{
2350 /*
2351 * From AC'97 SoundMax Codec AD1981A/AD1981B:
2352 * "Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the
2353 * D5 or D13 bits are set to 1, their respective lower five volume bits are automatically
2354 * set to 1 by the Codec logic. On readback, all lower 5 bits will read ones whenever
2355 * these bits are set to 1."
2356 *
2357 * Linux ALSA depends on this behavior to detect that only 5 bits are used for volume
2358 * control and the optional 6th bit is not used. Note that this logic only applies to the
2359 * master volume controls.
2360 */
2361 if (index == AC97_Master_Volume_Mute || index == AC97_Headphone_Volume_Mute || index == AC97_Master_Volume_Mono_Mute)
2362 {
2363 if (uVal & RT_BIT(5)) /* D5 bit set? */
2364 uVal |= RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0);
2365 if (uVal & RT_BIT(13)) /* D13 bit set? */
2366 uVal |= RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8);
2367 }
2368
2369 const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2370 uint8_t uCtlAttLeft = (uVal >> 8) & AC97_BARS_VOL_MASK;
2371 uint8_t uCtlAttRight = uVal & AC97_BARS_VOL_MASK;
2372
2373 /* For the master and headphone volume, 0 corresponds to 0dB attenuation. For the other
2374 * volume controls, 0 means 12dB gain and 8 means unity gain.
2375 */
2376 if (index != AC97_Master_Volume_Mute && index != AC97_Headphone_Volume_Mute)
2377 {
2378# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2379 /* NB: Currently there is no gain support, only attenuation. */
2380 uCtlAttLeft = uCtlAttLeft < 8 ? 0 : uCtlAttLeft - 8;
2381 uCtlAttRight = uCtlAttRight < 8 ? 0 : uCtlAttRight - 8;
2382# endif
2383 }
2384 Assert(uCtlAttLeft <= 255 / AC97_DB_FACTOR);
2385 Assert(uCtlAttRight <= 255 / AC97_DB_FACTOR);
2386
2387 LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2388 LogFunc(("uCtlAttLeft=%RU8, uCtlAttRight=%RU8 ", uCtlAttLeft, uCtlAttRight));
2389
2390 /*
2391 * For AC'97 volume controls, each additional step means -1.5dB attenuation with
2392 * zero being maximum. In contrast, we're internally using 255 (PDMAUDIO_VOLUME_MAX)
2393 * steps, each -0.375dB, where 0 corresponds to -96dB and 255 corresponds to 0dB.
2394 */
2395 uint8_t lVol = PDMAUDIO_VOLUME_MAX - uCtlAttLeft * AC97_DB_FACTOR;
2396 uint8_t rVol = PDMAUDIO_VOLUME_MAX - uCtlAttRight * AC97_DB_FACTOR;
2397
2398 Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2399
2400 int rc = VINF_SUCCESS;
2401
2402 if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2403 {
2404 PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2405 PAUDMIXSINK pSink = NULL;
2406
2407 switch (enmMixerCtl)
2408 {
2409 case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2410 rc = AudioMixerSetMasterVolume(pThisCC->pMixer, &Vol);
2411 break;
2412
2413 case PDMAUDIOMIXERCTL_FRONT:
2414 pSink = pThisCC->pSinkOut;
2415 break;
2416
2417 case PDMAUDIOMIXERCTL_MIC_IN:
2418 case PDMAUDIOMIXERCTL_LINE_IN:
2419 /* These are recognized but do nothing. */
2420 break;
2421
2422 default:
2423 AssertFailed();
2424 rc = VERR_NOT_SUPPORTED;
2425 break;
2426 }
2427
2428 if (pSink)
2429 rc = AudioMixerSinkSetVolume(pSink, &Vol);
2430 }
2431
2432 ichac97MixerSet(pThis, index, uVal);
2433
2434 if (RT_FAILURE(rc))
2435 LogFlowFunc(("Failed with %Rrc\n", rc));
2436
2437 return rc;
2438}
2439
2440/**
2441 * Sets the gain of a specific AC'97 recording control.
2442 *
2443 * NB: gain support is currently not implemented in PDM audio.
2444 *
2445 * @returns IPRT status code.
2446 * @param pThis The shared AC'97 state.
2447 * @param pThisCC The ring-3 AC'97 state.
2448 * @param index AC'97 mixer index to set volume for.
2449 * @param enmMixerCtl Corresponding audio mixer sink.
2450 * @param uVal Volume value to set.
2451 */
2452static int ichac97R3MixerSetGain(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2453{
2454 /*
2455 * For AC'97 recording controls, each additional step means +1.5dB gain with
2456 * zero being 0dB gain and 15 being +22.5dB gain.
2457 */
2458 const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2459 uint8_t uCtlGainLeft = (uVal >> 8) & AC97_BARS_GAIN_MASK;
2460 uint8_t uCtlGainRight = uVal & AC97_BARS_GAIN_MASK;
2461
2462 Assert(uCtlGainLeft <= 255 / AC97_DB_FACTOR);
2463 Assert(uCtlGainRight <= 255 / AC97_DB_FACTOR);
2464
2465 LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2466 LogFunc(("uCtlGainLeft=%RU8, uCtlGainRight=%RU8 ", uCtlGainLeft, uCtlGainRight));
2467
2468 uint8_t lVol = PDMAUDIO_VOLUME_MAX + uCtlGainLeft * AC97_DB_FACTOR;
2469 uint8_t rVol = PDMAUDIO_VOLUME_MAX + uCtlGainRight * AC97_DB_FACTOR;
2470
2471 /* We do not currently support gain. Since AC'97 does not support attenuation
2472 * for the recording input, the best we can do is set the maximum volume.
2473 */
2474# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2475 /* NB: Currently there is no gain support, only attenuation. Since AC'97 does not
2476 * support attenuation for the recording inputs, the best we can do is set the
2477 * maximum volume.
2478 */
2479 lVol = rVol = PDMAUDIO_VOLUME_MAX;
2480# endif
2481
2482 Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2483
2484 int rc = VINF_SUCCESS;
2485
2486 if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2487 {
2488 PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2489 PAUDMIXSINK pSink = NULL;
2490
2491 switch (enmMixerCtl)
2492 {
2493 case PDMAUDIOMIXERCTL_MIC_IN:
2494 pSink = pThisCC->pSinkMicIn;
2495 break;
2496
2497 case PDMAUDIOMIXERCTL_LINE_IN:
2498 pSink = pThisCC->pSinkLineIn;
2499 break;
2500
2501 default:
2502 AssertFailed();
2503 rc = VERR_NOT_SUPPORTED;
2504 break;
2505 }
2506
2507 if (pSink) {
2508 rc = AudioMixerSinkSetVolume(pSink, &Vol);
2509 /* There is only one AC'97 recording gain control. If line in
2510 * is changed, also update the microphone. If the optional dedicated
2511 * microphone is changed, only change that.
2512 * NB: The codecs we support do not have the dedicated microphone control.
2513 */
2514 if ((pSink == pThisCC->pSinkLineIn) && pThisCC->pSinkMicIn)
2515 rc = AudioMixerSinkSetVolume(pSink, &Vol);
2516 }
2517 }
2518
2519 ichac97MixerSet(pThis, index, uVal);
2520
2521 if (RT_FAILURE(rc))
2522 LogFlowFunc(("Failed with %Rrc\n", rc));
2523
2524 return rc;
2525}
2526
2527/**
2528 * Converts an AC'97 recording source index to a PDM audio recording source.
2529 *
2530 * @returns PDM audio recording source.
2531 * @param uIdx AC'97 index to convert.
2532 */
2533static PDMAUDIORECSRC ichac97R3IdxToRecSource(uint8_t uIdx)
2534{
2535 switch (uIdx)
2536 {
2537 case AC97_REC_MIC: return PDMAUDIORECSRC_MIC;
2538 case AC97_REC_CD: return PDMAUDIORECSRC_CD;
2539 case AC97_REC_VIDEO: return PDMAUDIORECSRC_VIDEO;
2540 case AC97_REC_AUX: return PDMAUDIORECSRC_AUX;
2541 case AC97_REC_LINE_IN: return PDMAUDIORECSRC_LINE;
2542 case AC97_REC_PHONE: return PDMAUDIORECSRC_PHONE;
2543 default:
2544 break;
2545 }
2546
2547 LogFlowFunc(("Unknown record source %d, using MIC\n", uIdx));
2548 return PDMAUDIORECSRC_MIC;
2549}
2550
2551/**
2552 * Converts a PDM audio recording source to an AC'97 recording source index.
2553 *
2554 * @returns AC'97 recording source index.
2555 * @param enmRecSrc PDM audio recording source to convert.
2556 */
2557static uint8_t ichac97R3RecSourceToIdx(PDMAUDIORECSRC enmRecSrc)
2558{
2559 switch (enmRecSrc)
2560 {
2561 case PDMAUDIORECSRC_MIC: return AC97_REC_MIC;
2562 case PDMAUDIORECSRC_CD: return AC97_REC_CD;
2563 case PDMAUDIORECSRC_VIDEO: return AC97_REC_VIDEO;
2564 case PDMAUDIORECSRC_AUX: return AC97_REC_AUX;
2565 case PDMAUDIORECSRC_LINE: return AC97_REC_LINE_IN;
2566 case PDMAUDIORECSRC_PHONE: return AC97_REC_PHONE;
2567 default:
2568 break;
2569 }
2570
2571 LogFlowFunc(("Unknown audio recording source %d using MIC\n", enmRecSrc));
2572 return AC97_REC_MIC;
2573}
2574
2575/**
2576 * Returns the audio direction of a specified stream descriptor.
2577 *
2578 * @return Audio direction.
2579 */
2580DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD)
2581{
2582 switch (uSD)
2583 {
2584 case AC97SOUNDSOURCE_PI_INDEX: return PDMAUDIODIR_IN;
2585 case AC97SOUNDSOURCE_PO_INDEX: return PDMAUDIODIR_OUT;
2586 case AC97SOUNDSOURCE_MC_INDEX: return PDMAUDIODIR_IN;
2587 }
2588
2589 AssertFailed();
2590 return PDMAUDIODIR_UNKNOWN;
2591}
2592
2593#endif /* IN_RING3 */
2594
2595#ifdef IN_RING3
2596
2597/**
2598 * Performs an AC'97 mixer record select to switch to a different recording
2599 * source.
2600 *
2601 * @param pThis The shared AC'97 state.
2602 * @param val AC'97 recording source index to set.
2603 */
2604static void ichac97R3MixerRecordSelect(PAC97STATE pThis, uint32_t val)
2605{
2606 uint8_t rs = val & AC97_REC_MASK;
2607 uint8_t ls = (val >> 8) & AC97_REC_MASK;
2608
2609 const PDMAUDIORECSRC ars = ichac97R3IdxToRecSource(rs);
2610 const PDMAUDIORECSRC als = ichac97R3IdxToRecSource(ls);
2611
2612 rs = ichac97R3RecSourceToIdx(ars);
2613 ls = ichac97R3RecSourceToIdx(als);
2614
2615 LogRel(("AC97: Record select to left=%s, right=%s\n", DrvAudioHlpRecSrcToStr(ars), DrvAudioHlpRecSrcToStr(als)));
2616
2617 ichac97MixerSet(pThis, AC97_Record_Select, rs | (ls << 8));
2618}
2619
2620/**
2621 * Resets the AC'97 mixer.
2622 *
2623 * @returns IPRT status code.
2624 * @param pThis The shared AC'97 state.
2625 * @param pThisCC The ring-3 AC'97 state.
2626 */
2627static int ichac97R3MixerReset(PAC97STATE pThis, PAC97STATER3 pThisCC)
2628{
2629 LogFlowFuncEnter();
2630
2631 RT_ZERO(pThis->mixer_data);
2632
2633 /* Note: Make sure to reset all registers first before bailing out on error. */
2634
2635 ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
2636 ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
2637 ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
2638
2639 ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
2640 ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
2641 ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
2642 ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
2643 ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
2644 ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
2645 ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
2646 ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
2647
2648 /* Configure Extended Audio ID (EAID) + Control & Status (EACS) registers. */
2649 const uint16_t fEAID = AC97_EAID_REV1 | AC97_EACS_VRA | AC97_EACS_VRM; /* Our hardware is AC'97 rev2.3 compliant. */
2650 const uint16_t fEACS = AC97_EACS_VRA | AC97_EACS_VRM; /* Variable Rate PCM Audio (VRA) + Mic-In (VRM) capable. */
2651
2652 LogRel(("AC97: Mixer reset (EAID=0x%x, EACS=0x%x)\n", fEAID, fEACS));
2653
2654 ichac97MixerSet(pThis, AC97_Extended_Audio_ID, fEAID);
2655 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, fEACS);
2656 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2657 ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2658 ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2659 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2660 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2661
2662 if (pThis->enmCodecModel == AC97CODEC_AD1980)
2663 {
2664 /* Analog Devices 1980 (AD1980) */
2665 ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
2666 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2667 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
2668 ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
2669 }
2670 else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
2671 {
2672 /* Analog Devices 1981B (AD1981B) */
2673 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2674 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
2675 }
2676 else
2677 {
2678 /* Sigmatel 9700 (STAC9700) */
2679 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
2680 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
2681 }
2682 ichac97R3MixerRecordSelect(pThis, 0);
2683
2684 /* The default value is 8000h, which corresponds to 0 dB attenuation with mute on. */
2685 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER, 0x8000);
2686
2687 /* The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on.*/
2688 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT, 0x8808);
2689 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
2690 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8008);
2691
2692 /* The default for record controls is 0 dB gain with mute on. */
2693 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8000);
2694 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8000);
2695
2696 return VINF_SUCCESS;
2697}
2698
2699# if 0 /* Unused */
2700static void ichac97R3WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
2701{
2702 LogFlowFunc(("cbElapsed=%RU32\n", cbElapsed));
2703
2704 if (!(pThis->bup_flag & BUP_SET))
2705 {
2706 if (pThis->bup_flag & BUP_LAST)
2707 {
2708 unsigned int i;
2709 uint32_t *p = (uint32_t*)pThis->silence;
2710 for (i = 0; i < sizeof(pThis->silence) / 4; i++) /** @todo r=andy Assumes 16-bit samples, stereo. */
2711 *p++ = pThis->last_samp;
2712 }
2713 else
2714 RT_ZERO(pThis->silence);
2715
2716 pThis->bup_flag |= BUP_SET;
2717 }
2718
2719 while (cbElapsed)
2720 {
2721 uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
2722 uint32_t cbWrittenToStream;
2723
2724 int rc2 = AudioMixerSinkWrite(pThisCC->pSinkOut, AUDMIXOP_COPY,
2725 pThis->silence, cbToWrite, &cbWrittenToStream);
2726 if (RT_SUCCESS(rc2))
2727 {
2728 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2729 LogFlowFunc(("Warning: Only written %RU32 / %RU32 bytes, expect lags\n", cbWrittenToStream, cbToWrite));
2730 }
2731
2732 /* Always report all data as being written;
2733 * backends who were not able to catch up have to deal with it themselves. */
2734 Assert(cbElapsed >= cbToWrite);
2735 cbElapsed -= cbToWrite;
2736 }
2737}
2738# endif /* Unused */
2739
2740/**
2741 * @callback_method_impl{FNTMTIMERDEV,
2742 * Timer callback which handles the audio data transfers on a periodic basis.}
2743 */
2744static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2745{
2746 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2747 STAM_PROFILE_START(&pThis->StatTimer, a);
2748 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
2749 PAC97STREAM pStream = (PAC97STREAM)pvUser;
2750 PAC97STREAMR3 pStreamCC = &RT_SAFE_SUBSCRIPT8(pThisCC->aStreams, pStream->u8SD);
2751 RT_NOREF(pTimer);
2752
2753 Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2754 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2755 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStream->hTimer));
2756
2757 ichac97R3StreamUpdate(pDevIns, pThis, pThisCC, pStream, pStreamCC, true /* fInTimer */);
2758
2759 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
2760 if (pSink && AudioMixerSinkIsActive(pSink))
2761 {
2762 ichac97R3StreamTransferUpdate(pDevIns, pStream, pStreamCC, pStream->Regs.picb << 1); /** @todo r=andy Assumes 16-bit samples. */
2763 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
2764 }
2765
2766 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2767}
2768
2769
2770/**
2771 * Sets the virtual device timer to a new expiration time.
2772 *
2773 * @param pDevIns The device instance.
2774 * @param pStream AC'97 stream to set timer for.
2775 * @param cTicksToDeadline The number of ticks to the new deadline.
2776 *
2777 * @remarks This used to be more complicated a long time ago...
2778 */
2779DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline)
2780{
2781 int rc = PDMDevHlpTimerSetRelative(pDevIns, pStream->hTimer, cTicksToDeadline, NULL /*pu64Now*/);
2782 AssertRC(rc);
2783}
2784
2785
2786/**
2787 * Transfers data of an AC'97 stream according to its usage (input / output).
2788 *
2789 * For an SDO (output) stream this means reading DMA data from the device to
2790 * the AC'97 stream's internal FIFO buffer.
2791 *
2792 * For an SDI (input) stream this is reading audio data from the AC'97 stream's
2793 * internal FIFO buffer and writing it as DMA data to the device.
2794 *
2795 * @returns IPRT status code.
2796 * @param pDevIns The device instance.
2797 * @param pThis The shared AC'97 state.
2798 * @param pStream The AC'97 stream to update (shared).
2799 * @param pStreamCC The AC'97 stream to update (ring-3).
2800 * @param cbToProcessMax Maximum of data (in bytes) to process.
2801 */
2802static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
2803 PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax)
2804{
2805 if (!cbToProcessMax)
2806 return VINF_SUCCESS;
2807
2808#ifdef VBOX_STRICT
2809 const unsigned cbFrame = DrvAudioHlpPCMPropsBytesPerFrame(&pStreamCC->State.Cfg.Props);
2810#endif
2811
2812 /* Make sure to only process an integer number of audio frames. */
2813 Assert(cbToProcessMax % cbFrame == 0);
2814
2815 ichac97R3StreamLock(pStreamCC);
2816
2817 PAC97BMREGS pRegs = &pStream->Regs;
2818
2819 if (pRegs->sr & AC97_SR_DCH) /* Controller halted? */
2820 {
2821 if (pRegs->cr & AC97_CR_RPBM) /* Bus master operation starts. */
2822 {
2823 switch (pStream->u8SD)
2824 {
2825 case AC97SOUNDSOURCE_PO_INDEX:
2826 /*ichac97R3WriteBUP(pThis, cbToProcess);*/
2827 break;
2828
2829 default:
2830 break;
2831 }
2832 }
2833
2834 ichac97R3StreamUnlock(pStreamCC);
2835 return VINF_SUCCESS;
2836 }
2837
2838 /* BCIS flag still set? Skip iteration. */
2839 if (pRegs->sr & AC97_SR_BCIS)
2840 {
2841 Log3Func(("[SD%RU8] BCIS set\n", pStream->u8SD));
2842
2843 ichac97R3StreamUnlock(pStreamCC);
2844 return VINF_SUCCESS;
2845 }
2846
2847 uint32_t cbLeft = RT_MIN((uint32_t)(pRegs->picb << 1), cbToProcessMax); /** @todo r=andy Assumes 16bit samples. */
2848 uint32_t cbProcessedTotal = 0;
2849
2850 PRTCIRCBUF pCircBuf = pStreamCC->State.pCircBuf;
2851 AssertPtr(pCircBuf);
2852
2853 int rc = VINF_SUCCESS;
2854
2855 Log3Func(("[SD%RU8] cbToProcessMax=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcessMax, cbLeft));
2856
2857 while (cbLeft)
2858 {
2859 if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
2860 {
2861 Log3Func(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
2862 pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
2863 if (pRegs->civ == pRegs->lvi)
2864 {
2865 pRegs->sr |= AC97_SR_DCH; /** @todo r=andy Also set CELV? */
2866 pThis->bup_flag = 0;
2867
2868 rc = VINF_EOF;
2869 break;
2870 }
2871
2872 pRegs->sr &= ~AC97_SR_CELV;
2873 pRegs->civ = pRegs->piv;
2874 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2875
2876 ichac97R3StreamFetchBDLE(pDevIns, pStream);
2877 continue;
2878 }
2879
2880 uint32_t cbChunk = cbLeft;
2881
2882 switch (pStream->u8SD)
2883 {
2884 case AC97SOUNDSOURCE_PO_INDEX: /* Output */
2885 {
2886 void *pvDst;
2887 size_t cbDst;
2888
2889 RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvDst, &cbDst);
2890
2891 if (cbDst)
2892 {
2893 int rc2 = PDMDevHlpPhysRead(pDevIns, pRegs->bd.addr, (uint8_t *)pvDst, cbDst);
2894 AssertRC(rc2);
2895
2896 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2897 { /* likely */ }
2898 else
2899 DrvAudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvDst, cbDst, 0 /* fFlags */);
2900 }
2901
2902 RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
2903
2904 cbChunk = (uint32_t)cbDst; /* Update the current chunk size to what really has been written. */
2905 break;
2906 }
2907
2908 case AC97SOUNDSOURCE_PI_INDEX: /* Input */
2909 case AC97SOUNDSOURCE_MC_INDEX: /* Input */
2910 {
2911 void *pvSrc;
2912 size_t cbSrc;
2913
2914 RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvSrc, &cbSrc);
2915
2916 if (cbSrc)
2917 {
2918/** @todo r=bird: Just curious, DevHDA uses PDMDevHlpPCIPhysWrite here. So,
2919 * is AC97 not subject to PCI busmaster enable/disable? */
2920 int rc2 = PDMDevHlpPhysWrite(pDevIns, pRegs->bd.addr, (uint8_t *)pvSrc, cbSrc);
2921 AssertRC(rc2);
2922
2923 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2924 { /* likely */ }
2925 else
2926 DrvAudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvSrc, cbSrc, 0 /* fFlags */);
2927 }
2928
2929 RTCircBufReleaseReadBlock(pCircBuf, cbSrc);
2930
2931 cbChunk = (uint32_t)cbSrc; /* Update the current chunk size to what really has been read. */
2932 break;
2933 }
2934
2935 default:
2936 AssertMsgFailed(("Stream #%RU8 not supported\n", pStream->u8SD));
2937 rc = VERR_NOT_SUPPORTED;
2938 break;
2939 }
2940
2941 if (RT_FAILURE(rc))
2942 break;
2943
2944 if (cbChunk)
2945 {
2946 cbProcessedTotal += cbChunk;
2947 Assert(cbProcessedTotal <= cbToProcessMax);
2948 Assert(cbLeft >= cbChunk);
2949 cbLeft -= cbChunk;
2950 Assert((cbChunk & 1) == 0); /* Else the following shift won't work */
2951
2952 pRegs->picb -= (cbChunk >> 1); /** @todo r=andy Assumes 16bit samples. */
2953 pRegs->bd.addr += cbChunk;
2954 }
2955
2956 LogFlowFunc(("[SD%RU8] cbChunk=%RU32, cbLeft=%RU32, cbTotal=%RU32, rc=%Rrc\n",
2957 pStream->u8SD, cbChunk, cbLeft, cbProcessedTotal, rc));
2958
2959 if (!pRegs->picb)
2960 {
2961 uint32_t new_sr = pRegs->sr & ~AC97_SR_CELV;
2962
2963 if (pRegs->bd.ctl_len & AC97_BD_IOC)
2964 {
2965 new_sr |= AC97_SR_BCIS;
2966 }
2967
2968 if (pRegs->civ == pRegs->lvi)
2969 {
2970 /* Did we run out of data? */
2971 LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pRegs->civ, pRegs->lvi));
2972
2973 new_sr |= AC97_SR_LVBCI | AC97_SR_DCH | AC97_SR_CELV;
2974 pThis->bup_flag = (pRegs->bd.ctl_len & AC97_BD_BUP) ? BUP_LAST : 0;
2975
2976 rc = VINF_EOF;
2977 }
2978 else
2979 {
2980 pRegs->civ = pRegs->piv;
2981 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2982 ichac97R3StreamFetchBDLE(pDevIns, pStream);
2983 }
2984
2985 ichac97StreamUpdateSR(pDevIns, pThis, pStream, new_sr);
2986 }
2987
2988 if (/* All data processed? */
2989 rc == VINF_EOF
2990 /* ... or an error occurred? */
2991 || RT_FAILURE(rc))
2992 {
2993 break;
2994 }
2995 }
2996
2997 ichac97R3StreamUnlock(pStreamCC);
2998
2999 LogFlowFuncLeaveRC(rc);
3000 return rc;
3001}
3002
3003#endif /* IN_RING3 */
3004
3005
3006/**
3007 * @callback_method_impl{FNIOMIOPORTNEWIN}
3008 */
3009static DECLCALLBACK(VBOXSTRICTRC)
3010ichac97IoPortNabmRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
3011{
3012 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3013 RT_NOREF(pvUser);
3014
3015 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3016
3017 /* Get the index of the NABMBAR port. */
3018 if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
3019 && offPort != AC97_GLOB_CNT)
3020 {
3021 PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
3022 PAC97BMREGS pRegs = &pStream->Regs;
3023
3024 switch (cb)
3025 {
3026 case 1:
3027 switch (offPort & AC97_NABM_OFF_MASK)
3028 {
3029 case AC97_NABM_OFF_CIV:
3030 /* Current Index Value Register */
3031 *pu32 = pRegs->civ;
3032 Log3Func(("CIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3033 break;
3034 case AC97_NABM_OFF_LVI:
3035 /* Last Valid Index Register */
3036 *pu32 = pRegs->lvi;
3037 Log3Func(("LVI[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3038 break;
3039 case AC97_NABM_OFF_PIV:
3040 /* Prefetched Index Value Register */
3041 *pu32 = pRegs->piv;
3042 Log3Func(("PIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3043 break;
3044 case AC97_NABM_OFF_CR:
3045 /* Control Register */
3046 *pu32 = pRegs->cr;
3047 Log3Func(("CR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3048 break;
3049 case AC97_NABM_OFF_SR:
3050 /* Status Register (lower part) */
3051 *pu32 = RT_LO_U8(pRegs->sr);
3052 Log3Func(("SRb[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3053 break;
3054 default:
3055 *pu32 = UINT32_MAX;
3056 LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
3057 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3058 break;
3059 }
3060 break;
3061
3062 case 2:
3063 switch (offPort & AC97_NABM_OFF_MASK)
3064 {
3065 case AC97_NABM_OFF_SR:
3066 /* Status Register */
3067 *pu32 = pRegs->sr;
3068 Log3Func(("SR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3069 break;
3070 case AC97_NABM_OFF_PICB:
3071 /* Position in Current Buffer */
3072 *pu32 = pRegs->picb;
3073 Log3Func(("PICB[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3074 break;
3075 default:
3076 *pu32 = UINT32_MAX;
3077 LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
3078 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3079 break;
3080 }
3081 break;
3082
3083 case 4:
3084 switch (offPort & AC97_NABM_OFF_MASK)
3085 {
3086 case AC97_NABM_OFF_BDBAR:
3087 /* Buffer Descriptor Base Address Register */
3088 *pu32 = pRegs->bdbar;
3089 Log3Func(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3090 break;
3091 case AC97_NABM_OFF_CIV:
3092 /* 32-bit access: Current Index Value Register +
3093 * Last Valid Index Register +
3094 * Status Register */
3095 *pu32 = pRegs->civ | (pRegs->lvi << 8) | (pRegs->sr << 16); /** @todo r=andy Use RT_MAKE_U32_FROM_U8. */
3096 Log3Func(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
3097 AC97_PORT2IDX(offPort), pRegs->civ, pRegs->lvi, pRegs->sr));
3098 break;
3099 case AC97_NABM_OFF_PICB:
3100 /* 32-bit access: Position in Current Buffer Register +
3101 * Prefetched Index Value Register +
3102 * Control Register */
3103 *pu32 = pRegs->picb | (pRegs->piv << 16) | (pRegs->cr << 24); /** @todo r=andy Use RT_MAKE_U32_FROM_U8. */
3104 Log3Func(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
3105 AC97_PORT2IDX(offPort), *pu32, pRegs->picb, pRegs->piv, pRegs->cr));
3106 break;
3107
3108 default:
3109 *pu32 = UINT32_MAX;
3110 LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
3111 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3112 break;
3113 }
3114 break;
3115
3116 default:
3117 DEVAC97_UNLOCK(pDevIns, pThis);
3118 AssertFailed();
3119 return VERR_IOM_IOPORT_UNUSED;
3120 }
3121 }
3122 else
3123 {
3124 switch (cb)
3125 {
3126 case 1:
3127 switch (offPort)
3128 {
3129 case AC97_CAS:
3130 /* Codec Access Semaphore Register */
3131 Log3Func(("CAS %d\n", pThis->cas));
3132 *pu32 = pThis->cas;
3133 pThis->cas = 1;
3134 break;
3135 default:
3136 *pu32 = UINT32_MAX;
3137 LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
3138 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3139 break;
3140 }
3141 break;
3142
3143 case 2:
3144 *pu32 = UINT32_MAX;
3145 LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
3146 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3147 break;
3148
3149 case 4:
3150 switch (offPort)
3151 {
3152 case AC97_GLOB_CNT:
3153 /* Global Control */
3154 *pu32 = pThis->glob_cnt;
3155 Log3Func(("glob_cnt -> %#x\n", *pu32));
3156 break;
3157 case AC97_GLOB_STA:
3158 /* Global Status */
3159 *pu32 = pThis->glob_sta | AC97_GS_S0CR;
3160 Log3Func(("glob_sta -> %#x\n", *pu32));
3161 break;
3162 default:
3163 *pu32 = UINT32_MAX;
3164 LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
3165 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3166 break;
3167 }
3168 break;
3169
3170 default:
3171 DEVAC97_UNLOCK(pDevIns, pThis);
3172 AssertFailed();
3173 return VERR_IOM_IOPORT_UNUSED;
3174 }
3175 }
3176
3177 DEVAC97_UNLOCK(pDevIns, pThis);
3178 return VINF_SUCCESS;
3179}
3180
3181/**
3182 * @callback_method_impl{FNIOMIOPORTNEWOUT}
3183 */
3184static DECLCALLBACK(VBOXSTRICTRC)
3185ichac97IoPortNabmWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3186{
3187 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3188#ifdef IN_RING3
3189 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3190#endif
3191 RT_NOREF(pvUser);
3192
3193 VBOXSTRICTRC rc = VINF_SUCCESS;
3194 if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
3195 && offPort != AC97_GLOB_CNT)
3196 {
3197#ifdef IN_RING3
3198 PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[AC97_PORT2IDX(offPort)];
3199#endif
3200 PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
3201 PAC97BMREGS pRegs = &pStream->Regs;
3202
3203 DEVAC97_LOCK_BOTH_RETURN(pDevIns, pThis, pStream, VINF_IOM_R3_IOPORT_WRITE);
3204 switch (cb)
3205 {
3206 case 1:
3207 switch (offPort & AC97_NABM_OFF_MASK)
3208 {
3209 /*
3210 * Last Valid Index.
3211 */
3212 case AC97_NABM_OFF_LVI:
3213 if ( (pRegs->cr & AC97_CR_RPBM)
3214 && (pRegs->sr & AC97_SR_DCH))
3215 {
3216#ifdef IN_RING3
3217 pRegs->sr &= ~(AC97_SR_DCH | AC97_SR_CELV);
3218 pRegs->civ = pRegs->piv;
3219 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3220#else
3221 rc = VINF_IOM_R3_IOPORT_WRITE;
3222#endif
3223 }
3224 pRegs->lvi = u32 % AC97_MAX_BDLE;
3225 Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32));
3226 break;
3227
3228 /*
3229 * Control Registers.
3230 */
3231 case AC97_NABM_OFF_CR:
3232#ifdef IN_RING3
3233 Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32, pRegs->cr));
3234 if (u32 & AC97_CR_RR) /* Busmaster reset. */
3235 {
3236 Log3Func(("[SD%RU8] Reset\n", pStream->u8SD));
3237
3238 /* Make sure that Run/Pause Bus Master bit (RPBM) is cleared (0). */
3239 Assert((pRegs->cr & AC97_CR_RPBM) == 0);
3240
3241 ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3242 ichac97R3StreamReset(pThis, pStream, pStreamCC);
3243
3244 ichac97StreamUpdateSR(pDevIns, pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */
3245 }
3246 else
3247 {
3248 pRegs->cr = u32 & AC97_CR_VALID_MASK;
3249
3250 if (!(pRegs->cr & AC97_CR_RPBM))
3251 {
3252 Log3Func(("[SD%RU8] Disable\n", pStream->u8SD));
3253
3254 ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3255
3256 pRegs->sr |= AC97_SR_DCH;
3257 }
3258 else
3259 {
3260 Log3Func(("[SD%RU8] Enable\n", pStream->u8SD));
3261
3262 pRegs->civ = pRegs->piv;
3263 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3264
3265 pRegs->sr &= ~AC97_SR_DCH;
3266
3267 /* Fetch the initial BDLE descriptor. */
3268 ichac97R3StreamFetchBDLE(pDevIns, pStream);
3269# ifdef LOG_ENABLED
3270 ichac97R3BDLEDumpAll(pDevIns, pStream->Regs.bdbar, pStream->Regs.lvi + 1);
3271# endif
3272 ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, true /* fEnable */);
3273
3274 /* Arm the timer for this stream. */
3275 /** @todo r=bird: This function returns bool, not VBox status! */
3276 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3277 }
3278 }
3279#else /* !IN_RING3 */
3280 rc = VINF_IOM_R3_IOPORT_WRITE;
3281#endif
3282 break;
3283
3284 /*
3285 * Status Registers.
3286 */
3287 case AC97_NABM_OFF_SR:
3288 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3289 break;
3290
3291 default:
3292 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3293 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3294 break;
3295 }
3296 break;
3297
3298 case 2:
3299 switch (offPort & AC97_NABM_OFF_MASK)
3300 {
3301 case AC97_NABM_OFF_SR:
3302 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3303 break;
3304 default:
3305 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3306 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3307 break;
3308 }
3309 break;
3310
3311 case 4:
3312 switch (offPort & AC97_NABM_OFF_MASK)
3313 {
3314 case AC97_NABM_OFF_BDBAR:
3315 /* Buffer Descriptor list Base Address Register */
3316 pRegs->bdbar = u32 & ~3;
3317 Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(offPort), u32, pRegs->bdbar));
3318 break;
3319 default:
3320 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3321 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3322 break;
3323 }
3324 break;
3325
3326 default:
3327 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3328 break;
3329 }
3330 DEVAC97_UNLOCK_BOTH(pDevIns, pThis, pStream);
3331 }
3332 else
3333 {
3334 switch (cb)
3335 {
3336 case 1:
3337 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3338 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3339 break;
3340
3341 case 2:
3342 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3343 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3344 break;
3345
3346 case 4:
3347 switch (offPort)
3348 {
3349 case AC97_GLOB_CNT:
3350 /* Global Control */
3351 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3352 if (u32 & AC97_GC_WR)
3353 ichac97WarmReset(pThis);
3354 if (u32 & AC97_GC_CR)
3355 ichac97ColdReset(pThis);
3356 if (!(u32 & (AC97_GC_WR | AC97_GC_CR)))
3357 pThis->glob_cnt = u32 & AC97_GC_VALID_MASK;
3358 Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt));
3359 DEVAC97_UNLOCK(pDevIns, pThis);
3360 break;
3361 case AC97_GLOB_STA:
3362 /* Global Status */
3363 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3364 pThis->glob_sta &= ~(u32 & AC97_GS_WCLEAR_MASK);
3365 pThis->glob_sta |= (u32 & ~(AC97_GS_WCLEAR_MASK | AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK;
3366 Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta));
3367 DEVAC97_UNLOCK(pDevIns, pThis);
3368 break;
3369 default:
3370 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3371 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3372 break;
3373 }
3374 break;
3375
3376 default:
3377 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3378 break;
3379 }
3380 }
3381
3382 return rc;
3383}
3384
3385/**
3386 * @callback_method_impl{FNIOMIOPORTNEWIN}
3387 */
3388static DECLCALLBACK(VBOXSTRICTRC)
3389ichac97IoPortNamRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
3390{
3391 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3392 RT_NOREF(pvUser);
3393 Assert(offPort < 256);
3394
3395 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3396
3397 VBOXSTRICTRC rc = VINF_SUCCESS;
3398 switch (cb)
3399 {
3400 case 1:
3401 {
3402 LogRel2(("AC97: Warning: Unimplemented read (1 byte) offPort=%#x\n", offPort));
3403 pThis->cas = 0;
3404 *pu32 = UINT32_MAX;
3405 break;
3406 }
3407
3408 case 2:
3409 {
3410 pThis->cas = 0;
3411 *pu32 = ichac97MixerGet(pThis, offPort);
3412 break;
3413 }
3414
3415 case 4:
3416 {
3417 LogRel2(("AC97: Warning: Unimplemented read (4 bytes) offPort=%#x\n", offPort));
3418 pThis->cas = 0;
3419 *pu32 = UINT32_MAX;
3420 break;
3421 }
3422
3423 default:
3424 {
3425 AssertFailed();
3426 rc = VERR_IOM_IOPORT_UNUSED;
3427 }
3428 }
3429
3430 DEVAC97_UNLOCK(pDevIns, pThis);
3431 return rc;
3432}
3433
3434/**
3435 * @callback_method_impl{FNIOMIOPORTNEWOUT}
3436 */
3437static DECLCALLBACK(VBOXSTRICTRC)
3438ichac97IoPortNamWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3439{
3440 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3441#ifdef IN_RING3
3442 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3443#endif
3444 RT_NOREF(pvUser);
3445
3446 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3447
3448 VBOXSTRICTRC rc = VINF_SUCCESS;
3449 switch (cb)
3450 {
3451 case 1:
3452 {
3453 LogRel2(("AC97: Warning: Unimplemented NAMWrite (1 byte) offPort=%#x <- %#x\n", offPort, u32));
3454 pThis->cas = 0;
3455 break;
3456 }
3457
3458 case 2:
3459 {
3460 pThis->cas = 0;
3461 switch (offPort)
3462 {
3463 case AC97_Reset:
3464#ifdef IN_RING3
3465 ichac97R3Reset(pDevIns);
3466#else
3467 rc = VINF_IOM_R3_IOPORT_WRITE;
3468#endif
3469 break;
3470 case AC97_Powerdown_Ctrl_Stat:
3471 u32 &= ~0xf;
3472 u32 |= ichac97MixerGet(pThis, offPort) & 0xf;
3473 ichac97MixerSet(pThis, offPort, u32);
3474 break;
3475 case AC97_Master_Volume_Mute:
3476 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3477 {
3478 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_LOSEL)
3479 break; /* Register controls surround (rear), do nothing. */
3480 }
3481#ifdef IN_RING3
3482 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3483#else
3484 rc = VINF_IOM_R3_IOPORT_WRITE;
3485#endif
3486 break;
3487 case AC97_Headphone_Volume_Mute:
3488 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3489 {
3490 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3491 {
3492 /* Register controls PCM (front) outputs. */
3493#ifdef IN_RING3
3494 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3495#else
3496 rc = VINF_IOM_R3_IOPORT_WRITE;
3497#endif
3498 }
3499 }
3500 break;
3501 case AC97_PCM_Out_Volume_Mute:
3502#ifdef IN_RING3
3503 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_FRONT, u32);
3504#else
3505 rc = VINF_IOM_R3_IOPORT_WRITE;
3506#endif
3507 break;
3508 case AC97_Line_In_Volume_Mute:
3509#ifdef IN_RING3
3510 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3511#else
3512 rc = VINF_IOM_R3_IOPORT_WRITE;
3513#endif
3514 break;
3515 case AC97_Record_Select:
3516#ifdef IN_RING3
3517 ichac97R3MixerRecordSelect(pThis, u32);
3518#else
3519 rc = VINF_IOM_R3_IOPORT_WRITE;
3520#endif
3521 break;
3522 case AC97_Record_Gain_Mute:
3523#ifdef IN_RING3
3524 /* Newer Ubuntu guests rely on that when controlling gain and muting
3525 * the recording (capturing) levels. */
3526 ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3527#else
3528 rc = VINF_IOM_R3_IOPORT_WRITE;
3529#endif
3530 break;
3531 case AC97_Record_Gain_Mic_Mute:
3532#ifdef IN_RING3
3533 /* Ditto; see note above. */
3534 ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_MIC_IN, u32);
3535#else
3536 rc = VINF_IOM_R3_IOPORT_WRITE;
3537#endif
3538 break;
3539 case AC97_Vendor_ID1:
3540 case AC97_Vendor_ID2:
3541 LogFunc(("Attempt to write vendor ID to %#x\n", u32));
3542 break;
3543 case AC97_Extended_Audio_ID:
3544 LogFunc(("Attempt to write extended audio ID to %#x\n", u32));
3545 break;
3546 case AC97_Extended_Audio_Ctrl_Stat:
3547#ifdef IN_RING3
3548 /*
3549 * Handle VRA bits.
3550 */
3551 if (!(u32 & AC97_EACS_VRA)) /* Check if VRA bit is not set. */
3552 {
3553 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 0xbb80); /* Set default (48000 Hz). */
3554 ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3555 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3556
3557 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3558 ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3559 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3560 }
3561 else
3562 LogRel2(("AC97: Variable rate audio (VRA) is not supported\n"));
3563
3564 /*
3565 * Handle VRM bits.
3566 */
3567 if (!(u32 & AC97_EACS_VRM)) /* Check if VRM bit is not set. */
3568 {
3569 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3570 ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3571 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3572 }
3573 else
3574 LogRel2(("AC97: Variable rate microphone audio (VRM) is not supported\n"));
3575
3576 LogRel2(("AC97: Setting extended audio control to %#x\n", u32));
3577 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32);
3578#else /* !IN_RING3 */
3579 rc = VINF_IOM_R3_IOPORT_WRITE;
3580#endif
3581 break;
3582 case AC97_PCM_Front_DAC_Rate: /* Output slots 3, 4, 6. */
3583#ifdef IN_RING3
3584 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3585 {
3586 LogRel2(("AC97: Setting front DAC rate to 0x%x\n", u32));
3587 ichac97MixerSet(pThis, offPort, u32);
3588 ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3589 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3590 }
3591 else
3592 LogRel2(("AC97: Setting front DAC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3593#else
3594 rc = VINF_IOM_R3_IOPORT_WRITE;
3595#endif
3596 break;
3597 case AC97_MIC_ADC_Rate: /* Input slot 6. */
3598#ifdef IN_RING3
3599 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRM)
3600 {
3601 LogRel2(("AC97: Setting microphone ADC rate to 0x%x\n", u32));
3602 ichac97MixerSet(pThis, offPort, u32);
3603 ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3604 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3605 }
3606 else
3607 LogRel2(("AC97: Setting microphone ADC rate (0x%x) when VRM is not set is forbidden, ignoring\n", u32));
3608#else
3609 rc = VINF_IOM_R3_IOPORT_WRITE;
3610#endif
3611 break;
3612 case AC97_PCM_LR_ADC_Rate: /* Input slots 3, 4. */
3613#ifdef IN_RING3
3614 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3615 {
3616 LogRel2(("AC97: Setting line-in ADC rate to 0x%x\n", u32));
3617 ichac97MixerSet(pThis, offPort, u32);
3618 ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3619 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3620 }
3621 else
3622 LogRel2(("AC97: Setting line-in ADC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3623#else
3624 rc = VINF_IOM_R3_IOPORT_WRITE;
3625#endif
3626 break;
3627 default:
3628 LogRel2(("AC97: Warning: Unimplemented NAMWrite (2 bytes) offPort=%#x <- %#x\n", offPort, u32));
3629 ichac97MixerSet(pThis, offPort, u32);
3630 break;
3631 }
3632 break;
3633 }
3634
3635 case 4:
3636 {
3637 LogRel2(("AC97: Warning: Unimplemented 4 byte NAMWrite: offPort=%#x <- %#x\n", offPort, u32));
3638 pThis->cas = 0;
3639 break;
3640 }
3641
3642 default:
3643 AssertMsgFailed(("Unhandled NAMWrite offPort=%#x, cb=%u u32=%#x\n", offPort, cb, u32));
3644 break;
3645 }
3646
3647 DEVAC97_UNLOCK(pDevIns, pThis);
3648 return rc;
3649}
3650
3651#ifdef IN_RING3
3652
3653/**
3654 * Saves (serializes) an AC'97 stream using SSM.
3655 *
3656 * @param pDevIns Device instance.
3657 * @param pSSM Saved state manager (SSM) handle to use.
3658 * @param pStream AC'97 stream to save.
3659 */
3660static void ichac97R3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3661{
3662 PAC97BMREGS pRegs = &pStream->Regs;
3663 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3664
3665 pHlp->pfnSSMPutU32(pSSM, pRegs->bdbar);
3666 pHlp->pfnSSMPutU8( pSSM, pRegs->civ);
3667 pHlp->pfnSSMPutU8( pSSM, pRegs->lvi);
3668 pHlp->pfnSSMPutU16(pSSM, pRegs->sr);
3669 pHlp->pfnSSMPutU16(pSSM, pRegs->picb);
3670 pHlp->pfnSSMPutU8( pSSM, pRegs->piv);
3671 pHlp->pfnSSMPutU8( pSSM, pRegs->cr);
3672 pHlp->pfnSSMPutS32(pSSM, pRegs->bd_valid);
3673 pHlp->pfnSSMPutU32(pSSM, pRegs->bd.addr);
3674 pHlp->pfnSSMPutU32(pSSM, pRegs->bd.ctl_len);
3675}
3676
3677/**
3678 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3679 */
3680static DECLCALLBACK(int) ichac97R3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3681{
3682 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3683 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3684 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3685 LogFlowFuncEnter();
3686
3687 pHlp->pfnSSMPutU32(pSSM, pThis->glob_cnt);
3688 pHlp->pfnSSMPutU32(pSSM, pThis->glob_sta);
3689 pHlp->pfnSSMPutU32(pSSM, pThis->cas);
3690
3691 /*
3692 * The order that the streams are saved here is fixed, so don't change.
3693 */
3694 /** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
3695 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3696 ichac97R3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3697
3698 pHlp->pfnSSMPutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3699
3700 /* The stream order is against fixed and set in stone. */
3701 uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3702 afActiveStrms[AC97SOUNDSOURCE_PI_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX]);
3703 afActiveStrms[AC97SOUNDSOURCE_PO_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX]);
3704 afActiveStrms[AC97SOUNDSOURCE_MC_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX]);
3705 AssertCompile(RT_ELEMENTS(afActiveStrms) == 3);
3706 pHlp->pfnSSMPutMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3707
3708 LogFlowFuncLeaveRC(VINF_SUCCESS);
3709 return VINF_SUCCESS;
3710}
3711
3712/**
3713 * Loads an AC'97 stream from SSM.
3714 *
3715 * @returns IPRT status code.
3716 * @param pDevIns The device instance.
3717 * @param pSSM Saved state manager (SSM) handle to use.
3718 * @param pStream AC'97 stream to load.
3719 */
3720static int ichac97R3LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3721{
3722 PAC97BMREGS pRegs = &pStream->Regs;
3723 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3724
3725 pHlp->pfnSSMGetU32(pSSM, &pRegs->bdbar);
3726 pHlp->pfnSSMGetU8( pSSM, &pRegs->civ);
3727 pHlp->pfnSSMGetU8( pSSM, &pRegs->lvi);
3728 pHlp->pfnSSMGetU16(pSSM, &pRegs->sr);
3729 pHlp->pfnSSMGetU16(pSSM, &pRegs->picb);
3730 pHlp->pfnSSMGetU8( pSSM, &pRegs->piv);
3731 pHlp->pfnSSMGetU8( pSSM, &pRegs->cr);
3732 pHlp->pfnSSMGetS32(pSSM, &pRegs->bd_valid);
3733 pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.addr);
3734 return pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.ctl_len);
3735}
3736
3737/**
3738 * @callback_method_impl{FNSSMDEVLOADEXEC}
3739 */
3740static DECLCALLBACK(int) ichac97R3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3741{
3742 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3743 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3744 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3745
3746 LogRel2(("ichac97LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3747
3748 AssertMsgReturn (uVersion == AC97_SAVED_STATE_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3749 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3750
3751 pHlp->pfnSSMGetU32(pSSM, &pThis->glob_cnt);
3752 pHlp->pfnSSMGetU32(pSSM, &pThis->glob_sta);
3753 pHlp->pfnSSMGetU32(pSSM, &pThis->cas);
3754
3755 /*
3756 * The order the streams are loaded here is critical (defined by
3757 * AC97SOUNDSOURCE_XX_INDEX), so don't touch!
3758 */
3759 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3760 {
3761 int rc2 = ichac97R3LoadStream(pDevIns, pSSM, &pThis->aStreams[i]);
3762 AssertRCReturn(rc2, rc2);
3763 }
3764
3765 pHlp->pfnSSMGetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3766
3767 ichac97R3MixerRecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
3768 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3769 ichac97MixerGet(pThis, AC97_Master_Volume_Mute));
3770 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT,
3771 ichac97MixerGet(pThis, AC97_PCM_Out_Volume_Mute));
3772 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3773 ichac97MixerGet(pThis, AC97_Line_In_Volume_Mute));
3774 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3775 ichac97MixerGet(pThis, AC97_Mic_Volume_Mute));
3776 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3777 ichac97MixerGet(pThis, AC97_Record_Gain_Mic_Mute));
3778 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3779 ichac97MixerGet(pThis, AC97_Record_Gain_Mute));
3780 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3781 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3782 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3783 ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
3784
3785 /*
3786 * Again the stream order is set is stone.
3787 */
3788 uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3789 int rc2 = pHlp->pfnSSMGetMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3790 AssertRCReturn(rc2, rc2);
3791
3792 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3793 {
3794 const bool fEnable = RT_BOOL(afActiveStrms[i]);
3795 const PAC97STREAM pStream = &pThis->aStreams[i];
3796 const PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[i];
3797
3798 rc2 = ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, fEnable);
3799 AssertRC(rc2);
3800 if ( fEnable
3801 && RT_SUCCESS(rc2))
3802 {
3803 /* Re-arm the timer for this stream. */
3804 /** @todo r=aeichner This causes a VM hang upon saved state resume when NetBSD is used as a guest
3805 * Stopping the timer if cTransferTicks is 0 is a workaround but needs further investigation,
3806 * see @bugref{9759} for more information. */
3807 if (pStreamCC->State.cTransferTicks)
3808 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3809 else
3810 PDMDevHlpTimerStop(pDevIns, pStream->hTimer);
3811 }
3812
3813 /* Keep going. */
3814 }
3815
3816 pThis->bup_flag = 0;
3817 pThis->last_samp = 0;
3818
3819 return VINF_SUCCESS;
3820}
3821
3822
3823/**
3824 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3825 */
3826static DECLCALLBACK(void *) ichac97R3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3827{
3828 PAC97STATER3 pThisCC = RT_FROM_MEMBER(pInterface, AC97STATER3, IBase);
3829 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
3830 return NULL;
3831}
3832
3833
3834/**
3835 * Powers off the device.
3836 *
3837 * @param pDevIns Device instance to power off.
3838 */
3839static DECLCALLBACK(void) ichac97R3PowerOff(PPDMDEVINS pDevIns)
3840{
3841 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3842 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3843
3844 LogRel2(("AC97: Powering off ...\n"));
3845
3846 /* Note: Involves mixer stream / sink destruction, so also do this here
3847 * instead of in ichac97R3Destruct(). */
3848 ichac97R3StreamsDestroy(pThis, pThisCC);
3849
3850 /*
3851 * Note: Destroy the mixer while powering off and *not* in ichac97R3Destruct,
3852 * giving the mixer the chance to release any references held to
3853 * PDM audio streams it maintains.
3854 */
3855 if (pThisCC->pMixer)
3856 {
3857 AudioMixerDestroy(pThisCC->pMixer);
3858 pThisCC->pMixer = NULL;
3859 }
3860}
3861
3862
3863/**
3864 * @interface_method_impl{PDMDEVREG,pfnReset}
3865 *
3866 * @remarks The original sources didn't install a reset handler, but it seems to
3867 * make sense to me so we'll do it.
3868 */
3869static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns)
3870{
3871 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3872 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3873
3874 LogRel(("AC97: Reset\n"));
3875
3876 /*
3877 * Reset the mixer too. The Windows XP driver seems to rely on
3878 * this. At least it wants to read the vendor id before it resets
3879 * the codec manually.
3880 */
3881 ichac97R3MixerReset(pThis, pThisCC);
3882
3883 /*
3884 * Reset all streams.
3885 */
3886 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3887 {
3888 ichac97R3StreamEnable(pThis, pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], false /* fEnable */);
3889 ichac97R3StreamReset(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
3890 }
3891
3892 /*
3893 * Reset mixer sinks.
3894 *
3895 * Do the reset here instead of in ichac97R3StreamReset();
3896 * the mixer sink(s) might still have data to be processed when an audio stream gets reset.
3897 */
3898 AudioMixerSinkReset(pThisCC->pSinkLineIn);
3899 AudioMixerSinkReset(pThisCC->pSinkMicIn);
3900 AudioMixerSinkReset(pThisCC->pSinkOut);
3901}
3902
3903
3904/**
3905 * Attach command, internal version.
3906 *
3907 * This is called to let the device attach to a driver for a specified LUN
3908 * during runtime. This is not called during VM construction, the device
3909 * constructor has to attach to all the available drivers.
3910 *
3911 * @returns VBox status code.
3912 * @param pDevIns The device instance.
3913 * @param pThisCC The ring-3 AC'97 device state.
3914 * @param iLun The logical unit which is being attached.
3915 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3916 * @param ppDrv Attached driver instance on success. Optional.
3917 */
3918static int ichac97R3AttachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned iLun, uint32_t fFlags, PAC97DRIVER *ppDrv)
3919{
3920 RT_NOREF(fFlags);
3921
3922 /*
3923 * Attach driver.
3924 */
3925 char *pszDesc;
3926 if (RTStrAPrintf(&pszDesc, "Audio driver port (AC'97) for LUN #%u", iLun) <= 0)
3927 AssertLogRelFailedReturn(VERR_NO_MEMORY);
3928
3929 PPDMIBASE pDrvBase;
3930 int rc = PDMDevHlpDriverAttach(pDevIns, iLun, &pThisCC->IBase, &pDrvBase, pszDesc);
3931 if (RT_SUCCESS(rc))
3932 {
3933 PAC97DRIVER pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
3934 if (pDrv)
3935 {
3936 pDrv->pDrvBase = pDrvBase;
3937 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
3938 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN #%u has no host audio interface, rc=%Rrc\n", iLun, rc));
3939 pDrv->uLUN = iLun;
3940 pDrv->pszDesc = pszDesc;
3941
3942 /*
3943 * For now we always set the driver at LUN 0 as our primary
3944 * host backend. This might change in the future.
3945 */
3946 if (iLun == 0)
3947 pDrv->fFlags |= PDMAUDIODRVFLAGS_PRIMARY;
3948
3949 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", iLun, pDrv->pConnector, pDrv->fFlags));
3950
3951 /* Attach to driver list if not attached yet. */
3952 if (!pDrv->fAttached)
3953 {
3954 RTListAppend(&pThisCC->lstDrv, &pDrv->Node);
3955 pDrv->fAttached = true;
3956 }
3957
3958 if (ppDrv)
3959 *ppDrv = pDrv;
3960 }
3961 else
3962 rc = VERR_NO_MEMORY;
3963 }
3964 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3965 LogFunc(("No attached driver for LUN #%u\n", iLun));
3966
3967 if (RT_FAILURE(rc))
3968 {
3969 /* Only free this string on failure;
3970 * must remain valid for the live of the driver instance. */
3971 RTStrFree(pszDesc);
3972 }
3973
3974 LogFunc(("iLun=%u, fFlags=0x%x, rc=%Rrc\n", iLun, fFlags, rc));
3975 return rc;
3976}
3977
3978/**
3979 * Detach command, internal version.
3980 *
3981 * This is called to let the device detach from a driver for a specified LUN
3982 * during runtime.
3983 *
3984 * @returns VBox status code.
3985 * @param pThisCC The ring-3 AC'97 device state.
3986 * @param pDrv Driver to detach from device.
3987 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3988 */
3989static int ichac97R3DetachInternal(PAC97STATER3 pThisCC, PAC97DRIVER pDrv, uint32_t fFlags)
3990{
3991 RT_NOREF(fFlags);
3992
3993 /* First, remove the driver from our list and destory it's associated streams.
3994 * This also will un-set the driver as a recording source (if associated). */
3995 ichac97R3MixerRemoveDrv(pThisCC, pDrv);
3996
3997 /* Next, search backwards for a capable (attached) driver which now will be the
3998 * new recording source. */
3999 PDMAUDIODSTSRCUNION dstSrc;
4000 PAC97DRIVER pDrvCur;
4001 RTListForEachReverse(&pThisCC->lstDrv, pDrvCur, AC97DRIVER, Node)
4002 {
4003 if (!pDrvCur->pConnector)
4004 continue;
4005
4006 PDMAUDIOBACKENDCFG Cfg;
4007 int rc2 = pDrvCur->pConnector->pfnGetConfig(pDrvCur->pConnector, &Cfg);
4008 if (RT_FAILURE(rc2))
4009 continue;
4010
4011 dstSrc.enmSrc = PDMAUDIORECSRC_MIC;
4012 PAC97DRIVERSTREAM pDrvStrm = ichac97R3MixerGetDrvStream(pDrvCur, PDMAUDIODIR_IN, dstSrc);
4013 if ( pDrvStrm
4014 && pDrvStrm->pMixStrm)
4015 {
4016 rc2 = AudioMixerSinkSetRecordingSource(pThisCC->pSinkMicIn, pDrvStrm->pMixStrm);
4017 if (RT_SUCCESS(rc2))
4018 LogRel2(("AC97: Set new recording source for 'Mic In' to '%s'\n", Cfg.szName));
4019 }
4020
4021 dstSrc.enmSrc = PDMAUDIORECSRC_LINE;
4022 pDrvStrm = ichac97R3MixerGetDrvStream(pDrvCur, PDMAUDIODIR_IN, dstSrc);
4023 if ( pDrvStrm
4024 && pDrvStrm->pMixStrm)
4025 {
4026 rc2 = AudioMixerSinkSetRecordingSource(pThisCC->pSinkLineIn, pDrvStrm->pMixStrm);
4027 if (RT_SUCCESS(rc2))
4028 LogRel2(("AC97: Set new recording source for 'Line In' to '%s'\n", Cfg.szName));
4029 }
4030 }
4031
4032 LogFunc(("uLUN=%u, fFlags=0x%x\n", pDrv->uLUN, fFlags));
4033 return VINF_SUCCESS;
4034}
4035
4036/**
4037 * @interface_method_impl{PDMDEVREGR3,pfnAttach}
4038 */
4039static DECLCALLBACK(int) ichac97R3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4040{
4041 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4042 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4043
4044 LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
4045
4046 DEVAC97_LOCK(pDevIns, pThis);
4047
4048 PAC97DRIVER pDrv;
4049 int rc2 = ichac97R3AttachInternal(pDevIns, pThisCC, iLUN, fFlags, &pDrv);
4050 if (RT_SUCCESS(rc2))
4051 rc2 = ichac97R3MixerAddDrv(pThisCC, pDrv);
4052
4053 if (RT_FAILURE(rc2))
4054 LogFunc(("Failed with %Rrc\n", rc2));
4055
4056 DEVAC97_UNLOCK(pDevIns, pThis);
4057
4058 return VINF_SUCCESS;
4059}
4060
4061/**
4062 * @interface_method_impl{PDMDEVREG,pfnDetach}
4063 */
4064static DECLCALLBACK(void) ichac97R3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4065{
4066 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4067 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4068
4069 LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
4070
4071 DEVAC97_LOCK(pDevIns, pThis);
4072
4073 PAC97DRIVER pDrv, pDrvNext;
4074 RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
4075 {
4076 if (pDrv->uLUN == iLUN)
4077 {
4078 int rc2 = ichac97R3DetachInternal(pThisCC, pDrv, fFlags);
4079 if (RT_SUCCESS(rc2))
4080 {
4081 RTStrFree(pDrv->pszDesc);
4082 RTMemFree(pDrv);
4083 pDrv = NULL;
4084 }
4085
4086 break;
4087 }
4088 }
4089
4090 DEVAC97_UNLOCK(pDevIns, pThis);
4091}
4092
4093/**
4094 * Replaces a driver with a the NullAudio drivers.
4095 *
4096 * @returns VBox status code.
4097 * @param pDevIns The device instance.
4098 * @param pThisCC The ring-3 AC'97 device state.
4099 * @param iLun The logical unit which is being replaced.
4100 */
4101static int ichac97R3ReconfigLunWithNullAudio(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned iLun)
4102{
4103 int rc = PDMDevHlpDriverReconfigure2(pDevIns, iLun, "AUDIO", "NullAudio");
4104 if (RT_SUCCESS(rc))
4105 rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, 0 /* fFlags */, NULL /* ppDrv */);
4106 LogFunc(("pThisCC=%p, iLun=%u, rc=%Rrc\n", pThisCC, iLun, rc));
4107 return rc;
4108}
4109
4110/**
4111 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4112 */
4113static DECLCALLBACK(int) ichac97R3Destruct(PPDMDEVINS pDevIns)
4114{
4115 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4116 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4117
4118 LogFlowFuncEnter();
4119
4120 PAC97DRIVER pDrv, pDrvNext;
4121 RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
4122 {
4123 RTListNodeRemove(&pDrv->Node);
4124 RTMemFree(pDrv->pszDesc);
4125 RTMemFree(pDrv);
4126 }
4127
4128 /* Sanity. */
4129 Assert(RTListIsEmpty(&pThisCC->lstDrv));
4130
4131 return VINF_SUCCESS;
4132}
4133
4134/**
4135 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4136 */
4137static DECLCALLBACK(int) ichac97R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4138{
4139 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4140 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4141 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4142 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4143 Assert(iInstance == 0); RT_NOREF(iInstance);
4144
4145 /*
4146 * Initialize data so we can run the destructor without scewing up.
4147 */
4148 pThisCC->pDevIns = pDevIns;
4149 pThisCC->IBase.pfnQueryInterface = ichac97R3QueryInterface;
4150 RTListInit(&pThisCC->lstDrv);
4151
4152 /*
4153 * Validate and read configuration.
4154 */
4155 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Codec|TimerHz|DebugEnabled|DebugPathOut", "");
4156
4157 char szCodec[20];
4158 int rc = pHlp->pfnCFGMQueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
4159 if (RT_FAILURE(rc))
4160 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4161 N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
4162
4163 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, AC97_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4164 if (RT_FAILURE(rc))
4165 return PDMDEV_SET_ERROR(pDevIns, rc,
4166 N_("AC'97 configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4167
4168 if (pThis->uTimerHz != AC97_TIMER_HZ_DEFAULT)
4169 LogRel(("AC97: Using custom device timer rate (%RU16Hz)\n", pThis->uTimerHz));
4170
4171 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "DebugEnabled", &pThisCC->Dbg.fEnabled, false);
4172 if (RT_FAILURE(rc))
4173 return PDMDEV_SET_ERROR(pDevIns, rc,
4174 N_("AC97 configuration error: failed to read debugging enabled flag as boolean"));
4175
4176 rc = pHlp->pfnCFGMQueryStringAllocDef(pCfg, "DebugPathOut", &pThisCC->Dbg.pszOutPath, VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4177 if (RT_FAILURE(rc))
4178 return PDMDEV_SET_ERROR(pDevIns, rc,
4179 N_("AC97 configuration error: failed to read debugging output path flag as string"));
4180
4181 if (pThisCC->Dbg.fEnabled)
4182 LogRel2(("AC97: Debug output will be saved to '%s'\n", pThisCC->Dbg.pszOutPath));
4183
4184 /*
4185 * The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
4186 * in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
4187 * 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
4188 */
4189 if (!strcmp(szCodec, "STAC9700"))
4190 pThis->enmCodecModel = AC97CODEC_STAC9700;
4191 else if (!strcmp(szCodec, "AD1980"))
4192 pThis->enmCodecModel = AC97CODEC_AD1980;
4193 else if (!strcmp(szCodec, "AD1981B"))
4194 pThis->enmCodecModel = AC97CODEC_AD1981B;
4195 else
4196 return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
4197 N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"), szCodec);
4198
4199 LogRel(("AC97: Using codec '%s'\n", szCodec));
4200
4201 /*
4202 * Use an own critical section for the device instead of the default
4203 * one provided by PDM. This allows fine-grained locking in combination
4204 * with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4205 */
4206 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "AC'97");
4207 AssertRCReturn(rc, rc);
4208
4209 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4210 AssertRCReturn(rc, rc);
4211
4212 /*
4213 * Initialize data (most of it anyway).
4214 */
4215 /* PCI Device */
4216 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4217 PCIDevSetVendorId(pPciDev, 0x8086); /* 00 ro - intel. */ Assert(pPciDev->abConfig[0x00] == 0x86); Assert(pPciDev->abConfig[0x01] == 0x80);
4218 PCIDevSetDeviceId(pPciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pPciDev->abConfig[0x02] == 0x15); Assert(pPciDev->abConfig[0x03] == 0x24);
4219 PCIDevSetCommand(pPciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pPciDev->abConfig[0x04] == 0x00); Assert(pPciDev->abConfig[0x05] == 0x00);
4220 PCIDevSetStatus(pPciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pPciDev->abConfig[0x06] == 0x80); Assert(pPciDev->abConfig[0x07] == 0x02);
4221 PCIDevSetRevisionId(pPciDev, 0x01); /* 08 ro - rid. */ Assert(pPciDev->abConfig[0x08] == 0x01);
4222 PCIDevSetClassProg(pPciDev, 0x00); /* 09 ro - pi. */ Assert(pPciDev->abConfig[0x09] == 0x00);
4223 PCIDevSetClassSub(pPciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pPciDev->abConfig[0x0a] == 0x01);
4224 PCIDevSetClassBase(pPciDev, 0x04); /* 0b ro - bcc; 04 == multimedia.*/Assert(pPciDev->abConfig[0x0b] == 0x04);
4225 PCIDevSetHeaderType(pPciDev, 0x00); /* 0e ro - headtyp. */ Assert(pPciDev->abConfig[0x0e] == 0x00);
4226 PCIDevSetBaseAddress(pPciDev, 0, /* 10 rw - nambar - native audio mixer base. */
4227 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x10] == 0x01); Assert(pPciDev->abConfig[0x11] == 0x00); Assert(pPciDev->abConfig[0x12] == 0x00); Assert(pPciDev->abConfig[0x13] == 0x00);
4228 PCIDevSetBaseAddress(pPciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
4229 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x14] == 0x01); Assert(pPciDev->abConfig[0x15] == 0x00); Assert(pPciDev->abConfig[0x16] == 0x00); Assert(pPciDev->abConfig[0x17] == 0x00);
4230 PCIDevSetInterruptLine(pPciDev, 0x00); /* 3c rw. */ Assert(pPciDev->abConfig[0x3c] == 0x00);
4231 PCIDevSetInterruptPin(pPciDev, 0x01); /* 3d ro - INTA#. */ Assert(pPciDev->abConfig[0x3d] == 0x01);
4232
4233 if (pThis->enmCodecModel == AC97CODEC_AD1980)
4234 {
4235 PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4236 PCIDevSetSubSystemId(pPciDev, 0x0177); /* 2e ro. */
4237 }
4238 else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
4239 {
4240 PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4241 PCIDevSetSubSystemId(pPciDev, 0x01ad); /* 2e ro. */
4242 }
4243 else
4244 {
4245 PCIDevSetSubSystemVendorId(pPciDev, 0x8086); /* 2c ro - Intel.) */
4246 PCIDevSetSubSystemId(pPciDev, 0x0000); /* 2e ro. */
4247 }
4248
4249 /*
4250 * Register the PCI device and associated I/O regions.
4251 */
4252 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4253 if (RT_FAILURE(rc))
4254 return rc;
4255
4256 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 0 /*iPciRegion*/, 256 /*cPorts*/,
4257 ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /*pvUser*/,
4258 "ICHAC97 NAM", NULL /*paExtDescs*/, &pThis->hIoPortsNam);
4259 AssertRCReturn(rc, rc);
4260
4261 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 1 /*iPciRegion*/, 64 /*cPorts*/,
4262 ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /*pvUser*/,
4263 "ICHAC97 NABM", g_aNabmPorts, &pThis->hIoPortsNabm);
4264 AssertRCReturn(rc, rc);
4265
4266 /*
4267 * Saved state.
4268 */
4269 rc = PDMDevHlpSSMRegister(pDevIns, AC97_SAVED_STATE_VERSION, sizeof(*pThis), ichac97R3SaveExec, ichac97R3LoadExec);
4270 if (RT_FAILURE(rc))
4271 return rc;
4272
4273# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
4274 LogRel(("AC97: Asynchronous I/O enabled\n"));
4275# endif
4276
4277 /*
4278 * Attach drivers. We ASSUME they are configured consecutively without any
4279 * gaps, so we stop when we hit the first LUN w/o a driver configured.
4280 */
4281 for (unsigned iLun = 0; ; iLun++)
4282 {
4283 AssertBreak(iLun < UINT8_MAX);
4284 LogFunc(("Trying to attach driver for LUN#%u ...\n", iLun));
4285 rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, 0 /* fFlags */, NULL /* ppDrv */);
4286 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4287 {
4288 LogFunc(("cLUNs=%u\n", iLun));
4289 break;
4290 }
4291 if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
4292 {
4293 ichac97R3ReconfigLunWithNullAudio(pDevIns, pThisCC, iLun); /* Pretend attaching to the NULL audio backend will never fail. */
4294 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
4295 N_("Host audio backend initialization has failed. "
4296 "Selecting the NULL audio backend with the consequence that no sound is audible"));
4297 }
4298 else
4299 AssertLogRelMsgReturn(RT_SUCCESS(rc), ("LUN#%u: rc=%Rrc\n", iLun, rc), rc);
4300 }
4301
4302 rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThisCC->pMixer);
4303 AssertRCReturn(rc, rc);
4304 rc = AudioMixerCreateSink(pThisCC->pMixer, "[Recording] Line In", AUDMIXSINKDIR_INPUT, &pThisCC->pSinkLineIn);
4305 AssertRCReturn(rc, rc);
4306 rc = AudioMixerCreateSink(pThisCC->pMixer, "[Recording] Microphone In", AUDMIXSINKDIR_INPUT, &pThisCC->pSinkMicIn);
4307 AssertRCReturn(rc, rc);
4308 rc = AudioMixerCreateSink(pThisCC->pMixer, "[Playback] PCM Output", AUDMIXSINKDIR_OUTPUT, &pThisCC->pSinkOut);
4309 AssertRCReturn(rc, rc);
4310
4311 /*
4312 * Create all hardware streams.
4313 */
4314 AssertCompile(RT_ELEMENTS(pThis->aStreams) == AC97_MAX_STREAMS);
4315 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4316 {
4317 rc = ichac97R3StreamCreate(pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], i /* SD# */);
4318 AssertRCReturn(rc, rc);
4319 }
4320
4321 /*
4322 * Create the emulation timers (one per stream).
4323 *
4324 * We must the critical section for the timers as the device has a
4325 * noop section associated with it.
4326 *
4327 * Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's AC'97 driver
4328 * relies on exact (virtual) DMA timing and uses DMA Position Buffers
4329 * instead of the LPIB registers.
4330 */
4331 static const char * const s_apszNames[] = { "AC97 PI", "AC97 PO", "AC97 MC" };
4332 AssertCompile(RT_ELEMENTS(s_apszNames) == AC97_MAX_STREAMS);
4333 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4334 {
4335 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, ichac97R3Timer, &pThis->aStreams[i],
4336 TMTIMER_FLAGS_NO_CRIT_SECT, s_apszNames[i], &pThis->aStreams[i].hTimer);
4337 AssertRCReturn(rc, rc);
4338
4339 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->aStreams[i].hTimer, &pThis->CritSect);
4340 AssertRCReturn(rc, rc);
4341 }
4342
4343
4344# ifdef VBOX_WITH_AUDIO_AC97_ONETIME_INIT
4345 PAC97DRIVER pDrv;
4346 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
4347 {
4348 /*
4349 * Only primary drivers are critical for the VM to run. Everything else
4350 * might not worth showing an own error message box in the GUI.
4351 */
4352 if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
4353 continue;
4354
4355 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
4356 AssertPtr(pCon);
4357
4358 bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
4359 bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
4360 bool fValidOut = AudioMixerStreamIsValid(pDrv->Out.pMixStrm);
4361
4362 if ( !fValidLineIn
4363 && !fValidMicIn
4364 && !fValidOut)
4365 {
4366 LogRel(("AC97: Falling back to NULL backend (no sound audible)\n"));
4367 ichac97R3Reset(pDevIns);
4368 ichac97R3ReconfigLunWithNullAudio(pdEvIns, pThsiCC, iLun);
4369 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
4370 N_("No audio devices could be opened. "
4371 "Selecting the NULL audio backend with the consequence that no sound is audible"));
4372 }
4373 else
4374 {
4375 bool fWarn = false;
4376
4377 PDMAUDIOBACKENDCFG backendCfg;
4378 int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
4379 if (RT_SUCCESS(rc2))
4380 {
4381 if (backendCfg.cMaxStreamsIn)
4382 {
4383 /* If the audio backend supports two or more input streams at once,
4384 * warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
4385 if (backendCfg.cMaxStreamsIn >= 2)
4386 fWarn = !fValidLineIn || !fValidMicIn;
4387 /* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
4388 * *not* ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
4389 * One of the two simply is not in use then. */
4390 else if (backendCfg.cMaxStreamsIn == 1)
4391 fWarn = !fValidLineIn && !fValidMicIn;
4392 /* Don't warn if our backend is not able of supporting any input streams at all. */
4393 }
4394
4395 if ( !fWarn
4396 && backendCfg.cMaxStreamsOut)
4397 {
4398 fWarn = !fValidOut;
4399 }
4400 }
4401 else
4402 {
4403 LogRel(("AC97: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
4404 fWarn = true;
4405 }
4406
4407 if (fWarn)
4408 {
4409 char szMissingStreams[255] = "";
4410 size_t len = 0;
4411 if (!fValidLineIn)
4412 {
4413 LogRel(("AC97: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
4414 len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
4415 }
4416 if (!fValidMicIn)
4417 {
4418 LogRel(("AC97: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
4419 len += RTStrPrintf(szMissingStreams + len,
4420 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
4421 }
4422 if (!fValidOut)
4423 {
4424 LogRel(("AC97: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
4425 len += RTStrPrintf(szMissingStreams + len,
4426 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
4427 }
4428
4429 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
4430 N_("Some AC'97 audio streams (%s) could not be opened. Guest applications generating audio "
4431 "output or depending on audio input may hang. Make sure your host audio device "
4432 "is working properly. Check the logfile for error messages of the audio "
4433 "subsystem"), szMissingStreams);
4434 }
4435 }
4436 }
4437# endif /* VBOX_WITH_AUDIO_AC97_ONETIME_INIT */
4438
4439 ichac97R3Reset(pDevIns);
4440
4441 /*
4442 * Register statistics.
4443 */
4444 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmReads, STAMTYPE_COUNTER, "UnimplementedNabmReads", STAMUNIT_OCCURENCES, "Unimplemented NABM register reads.");
4445 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmWrites, STAMTYPE_COUNTER, "UnimplementedNabmWrites", STAMUNIT_OCCURENCES, "Unimplemented NABM register writes.");
4446# ifdef VBOX_WITH_STATISTICS
4447 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
4448 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
4449 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
4450 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
4451 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
4452# endif
4453
4454 LogFlowFuncLeaveRC(VINF_SUCCESS);
4455 return VINF_SUCCESS;
4456}
4457
4458#else /* !IN_RING3 */
4459
4460/**
4461 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4462 */
4463static DECLCALLBACK(int) ichac97RZConstruct(PPDMDEVINS pDevIns)
4464{
4465 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4466 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4467
4468 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4469 AssertRCReturn(rc, rc);
4470
4471 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNam, ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /*pvUser*/);
4472 AssertRCReturn(rc, rc);
4473 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNabm, ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /*pvUser*/);
4474 AssertRCReturn(rc, rc);
4475
4476 return VINF_SUCCESS;
4477}
4478
4479#endif /* !IN_RING3 */
4480
4481/**
4482 * The device registration structure.
4483 */
4484const PDMDEVREG g_DeviceICHAC97 =
4485{
4486 /* .u32Version = */ PDM_DEVREG_VERSION,
4487 /* .uReserved0 = */ 0,
4488 /* .szName = */ "ichac97",
4489 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4490 /* .fClass = */ PDM_DEVREG_CLASS_AUDIO,
4491 /* .cMaxInstances = */ 1,
4492 /* .uSharedVersion = */ 42,
4493 /* .cbInstanceShared = */ sizeof(AC97STATE),
4494 /* .cbInstanceCC = */ CTX_EXPR(sizeof(AC97STATER3), 0, 0),
4495 /* .cbInstanceRC = */ 0,
4496 /* .cMaxPciDevices = */ 1,
4497 /* .cMaxMsixVectors = */ 0,
4498 /* .pszDescription = */ "ICH AC'97 Audio Controller",
4499#if defined(IN_RING3)
4500 /* .pszRCMod = */ "VBoxDDRC.rc",
4501 /* .pszR0Mod = */ "VBoxDDR0.r0",
4502 /* .pfnConstruct = */ ichac97R3Construct,
4503 /* .pfnDestruct = */ ichac97R3Destruct,
4504 /* .pfnRelocate = */ NULL,
4505 /* .pfnMemSetup = */ NULL,
4506 /* .pfnPowerOn = */ NULL,
4507 /* .pfnReset = */ ichac97R3Reset,
4508 /* .pfnSuspend = */ NULL,
4509 /* .pfnResume = */ NULL,
4510 /* .pfnAttach = */ ichac97R3Attach,
4511 /* .pfnDetach = */ ichac97R3Detach,
4512 /* .pfnQueryInterface = */ NULL,
4513 /* .pfnInitComplete = */ NULL,
4514 /* .pfnPowerOff = */ ichac97R3PowerOff,
4515 /* .pfnSoftReset = */ NULL,
4516 /* .pfnReserved0 = */ NULL,
4517 /* .pfnReserved1 = */ NULL,
4518 /* .pfnReserved2 = */ NULL,
4519 /* .pfnReserved3 = */ NULL,
4520 /* .pfnReserved4 = */ NULL,
4521 /* .pfnReserved5 = */ NULL,
4522 /* .pfnReserved6 = */ NULL,
4523 /* .pfnReserved7 = */ NULL,
4524#elif defined(IN_RING0)
4525 /* .pfnEarlyConstruct = */ NULL,
4526 /* .pfnConstruct = */ ichac97RZConstruct,
4527 /* .pfnDestruct = */ NULL,
4528 /* .pfnFinalDestruct = */ NULL,
4529 /* .pfnRequest = */ NULL,
4530 /* .pfnReserved0 = */ NULL,
4531 /* .pfnReserved1 = */ NULL,
4532 /* .pfnReserved2 = */ NULL,
4533 /* .pfnReserved3 = */ NULL,
4534 /* .pfnReserved4 = */ NULL,
4535 /* .pfnReserved5 = */ NULL,
4536 /* .pfnReserved6 = */ NULL,
4537 /* .pfnReserved7 = */ NULL,
4538#elif defined(IN_RC)
4539 /* .pfnConstruct = */ ichac97RZConstruct,
4540 /* .pfnReserved0 = */ NULL,
4541 /* .pfnReserved1 = */ NULL,
4542 /* .pfnReserved2 = */ NULL,
4543 /* .pfnReserved3 = */ NULL,
4544 /* .pfnReserved4 = */ NULL,
4545 /* .pfnReserved5 = */ NULL,
4546 /* .pfnReserved6 = */ NULL,
4547 /* .pfnReserved7 = */ NULL,
4548#else
4549# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4550#endif
4551 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4552};
4553
4554#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4555
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