DevIchAc97.cpp@ 87760

Last change on this file since 87760 was 87760, checked in by vboxsync, 4 years ago
VMM/TM,VMM/DevHlp: Require flag on timers that are to be used in ring-0 (and while refactoring a counte flag to check that all timers have been checked). Removed obsolete timer device helpers. bugref:9943
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 172.2 KB

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1	/* $Id: DevIchAc97.cpp 87760 2021-02-15 22:45:27Z vboxsync $ */
2	/** @file
3	* DevIchAc97 - VBox ICH AC97 Audio Controller.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_AC97
23	#include <VBox/log.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/vmm/pdmaudioifs.h>
26
27	#include <iprt/assert.h>
28	#ifdef IN_RING3
29	# ifdef DEBUG
30	# include <iprt/file.h>
31	# endif
32	# include <iprt/mem.h>
33	# include <iprt/semaphore.h>
34	# include <iprt/string.h>
35	# include <iprt/uuid.h>
36	#endif
37
38	#include "VBoxDD.h"
39
40	#include "AudioMixBuffer.h"
41	#include "AudioMixer.h"
42	#include "DrvAudio.h"
43
44
45	/*********************************************************************************************************************************
46	* Defined Constants And Macros *
47	*********************************************************************************************************************************/
48
49	/** Current saved state version. */
50	#define AC97_SAVED_STATE_VERSION 1
51
52	/** Default timer frequency (in Hz). */
53	#define AC97_TIMER_HZ_DEFAULT 100
54
55	/** Maximum number of streams we support. */
56	#define AC97_MAX_STREAMS 3
57
58	/** Maximum FIFO size (in bytes). */
59	#define AC97_FIFO_MAX 256
60
61	#define AC97_SR_FIFOE RT_BIT(4) /*< rwc, FIFO error. /
62	#define AC97_SR_BCIS RT_BIT(3) /*< rwc, Buffer completion interrupt status. /
63	#define AC97_SR_LVBCI RT_BIT(2) /*< rwc, Last valid buffer completion interrupt. /
64	#define AC97_SR_CELV RT_BIT(1) /*< ro, Current equals last valid. /
65	#define AC97_SR_DCH RT_BIT(0) /*< ro, Controller halted. /
66	#define AC97_SR_VALID_MASK (RT_BIT(5) - 1)
67	#define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE \| AC97_SR_BCIS \| AC97_SR_LVBCI)
68	#define AC97_SR_RO_MASK (AC97_SR_DCH \| AC97_SR_CELV)
69	#define AC97_SR_INT_MASK (AC97_SR_FIFOE \| AC97_SR_BCIS \| AC97_SR_LVBCI)
70
71	#define AC97_CR_IOCE RT_BIT(4) /*< rw, Interrupt On Completion Enable. /
72	#define AC97_CR_FEIE RT_BIT(3) /*< rw FIFO Error Interrupt Enable. /
73	#define AC97_CR_LVBIE RT_BIT(2) /*< rw Last Valid Buffer Interrupt Enable. /
74	#define AC97_CR_RR RT_BIT(1) /*< rw Reset Registers. /
75	#define AC97_CR_RPBM RT_BIT(0) /*< rw Run/Pause Bus Master. /
76	#define AC97_CR_VALID_MASK (RT_BIT(5) - 1)
77	#define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE \| AC97_CR_FEIE \| AC97_CR_LVBIE)
78
79	#define AC97_GC_WR 4 /*< rw Warm reset. /
80	#define AC97_GC_CR 2 /*< rw Cold reset. /
81	#define AC97_GC_VALID_MASK (RT_BIT(6) - 1)
82
83	#define AC97_GS_MD3 RT_BIT(17) /*< rw /
84	#define AC97_GS_AD3 RT_BIT(16) /*< rw /
85	#define AC97_GS_RCS RT_BIT(15) /*< rwc /
86	#define AC97_GS_B3S12 RT_BIT(14) /*< ro /
87	#define AC97_GS_B2S12 RT_BIT(13) /*< ro /
88	#define AC97_GS_B1S12 RT_BIT(12) /*< ro /
89	#define AC97_GS_S1R1 RT_BIT(11) /*< rwc /
90	#define AC97_GS_S0R1 RT_BIT(10) /*< rwc /
91	#define AC97_GS_S1CR RT_BIT(9) /*< ro /
92	#define AC97_GS_S0CR RT_BIT(8) /*< ro /
93	#define AC97_GS_MINT RT_BIT(7) /*< ro /
94	#define AC97_GS_POINT RT_BIT(6) /*< ro /
95	#define AC97_GS_PIINT RT_BIT(5) /*< ro /
96	#define AC97_GS_RSRVD (RT_BIT(4) \| RT_BIT(3))
97	#define AC97_GS_MOINT RT_BIT(2) /*< ro /
98	#define AC97_GS_MIINT RT_BIT(1) /*< ro /
99	#define AC97_GS_GSCI RT_BIT(0) /*< rwc /
100	#define AC97_GS_RO_MASK ( AC97_GS_B3S12 \
101	\| AC97_GS_B2S12 \
102	\| AC97_GS_B1S12 \
103	\| AC97_GS_S1CR \
104	\| AC97_GS_S0CR \
105	\| AC97_GS_MINT \
106	\| AC97_GS_POINT \
107	\| AC97_GS_PIINT \
108	\| AC97_GS_RSRVD \
109	\| AC97_GS_MOINT \
110	\| AC97_GS_MIINT)
111	#define AC97_GS_VALID_MASK (RT_BIT(18) - 1)
112	#define AC97_GS_WCLEAR_MASK (AC97_GS_RCS \| AC97_GS_S1R1 \| AC97_GS_S0R1 \| AC97_GS_GSCI)
113
114	/** @name Buffer Descriptor (BD).
115	* @{ */
116	#define AC97_BD_IOC RT_BIT(31) /*< Interrupt on Completion. /
117	#define AC97_BD_BUP RT_BIT(30) /*< Buffer Underrun Policy. /
118
119	#define AC97_BD_LEN_MASK 0xFFFF /*< Mask for the BDL buffer length. /
120
121	#define AC97_MAX_BDLE 32 /*< Maximum number of BDLEs. /
122	/** @} */
123
124	/** @name Extended Audio ID Register (EAID).
125	* @{ */
126	#define AC97_EAID_VRA RT_BIT(0) /*< Variable Rate Audio. /
127	#define AC97_EAID_VRM RT_BIT(3) /*< Variable Rate Mic Audio. /
128	#define AC97_EAID_REV0 RT_BIT(10) /*< AC'97 revision compliance. /
129	#define AC97_EAID_REV1 RT_BIT(11) /*< AC'97 revision compliance. /
130	/** @} */
131
132	/** @name Extended Audio Control and Status Register (EACS).
133	* @{ */
134	#define AC97_EACS_VRA RT_BIT(0) /*< Variable Rate Audio (4.2.1.1). /
135	#define AC97_EACS_VRM RT_BIT(3) /*< Variable Rate Mic Audio (4.2.1.1). /
136	/** @} */
137
138	/** @name Baseline Audio Register Set (BARS).
139	* @{ */
140	#define AC97_BARS_VOL_MASK 0x1f /*< Volume mask for the Baseline Audio Register Set (5.7.2). /
141	#define AC97_BARS_GAIN_MASK 0x0f /*< Gain mask for the Baseline Audio Register Set. /
142	#define AC97_BARS_VOL_MUTE_SHIFT 15 /*< Mute bit shift for the Baseline Audio Register Set (5.7.2). /
143	/** @} */
144
145	/** AC'97 uses 1.5dB steps, we use 0.375dB steps: 1 AC'97 step equals 4 PDM steps. */
146	#define AC97_DB_FACTOR 4
147
148	/** @name Recording inputs?
149	* @{ */
150	#define AC97_REC_MIC UINT8_C(0)
151	#define AC97_REC_CD UINT8_C(1)
152	#define AC97_REC_VIDEO UINT8_C(2)
153	#define AC97_REC_AUX UINT8_C(3)
154	#define AC97_REC_LINE_IN UINT8_C(4)
155	#define AC97_REC_STEREO_MIX UINT8_C(5)
156	#define AC97_REC_MONO_MIX UINT8_C(6)
157	#define AC97_REC_PHONE UINT8_C(7)
158	#define AC97_REC_MASK UINT8_C(7)
159	/** @} */
160
161	/** @name Mixer registers / NAM BAR registers?
162	* @{ */
163	#define AC97_Reset 0x00
164	#define AC97_Master_Volume_Mute 0x02
165	#define AC97_Headphone_Volume_Mute 0x04 /*< Also known as AUX, see table 16, section 5.7. /
166	#define AC97_Master_Volume_Mono_Mute 0x06
167	#define AC97_Master_Tone_RL 0x08
168	#define AC97_PC_BEEP_Volume_Mute 0x0a
169	#define AC97_Phone_Volume_Mute 0x0c
170	#define AC97_Mic_Volume_Mute 0x0e
171	#define AC97_Line_In_Volume_Mute 0x10
172	#define AC97_CD_Volume_Mute 0x12
173	#define AC97_Video_Volume_Mute 0x14
174	#define AC97_Aux_Volume_Mute 0x16
175	#define AC97_PCM_Out_Volume_Mute 0x18
176	#define AC97_Record_Select 0x1a
177	#define AC97_Record_Gain_Mute 0x1c
178	#define AC97_Record_Gain_Mic_Mute 0x1e
179	#define AC97_General_Purpose 0x20
180	#define AC97_3D_Control 0x22
181	#define AC97_AC_97_RESERVED 0x24
182	#define AC97_Powerdown_Ctrl_Stat 0x26
183	#define AC97_Extended_Audio_ID 0x28
184	#define AC97_Extended_Audio_Ctrl_Stat 0x2a
185	#define AC97_PCM_Front_DAC_Rate 0x2c
186	#define AC97_PCM_Surround_DAC_Rate 0x2e
187	#define AC97_PCM_LFE_DAC_Rate 0x30
188	#define AC97_PCM_LR_ADC_Rate 0x32
189	#define AC97_MIC_ADC_Rate 0x34
190	#define AC97_6Ch_Vol_C_LFE_Mute 0x36
191	#define AC97_6Ch_Vol_L_R_Surround_Mute 0x38
192	#define AC97_Vendor_Reserved 0x58
193	#define AC97_AD_Misc 0x76
194	#define AC97_Vendor_ID1 0x7c
195	#define AC97_Vendor_ID2 0x7e
196	/** @} */
197
198	/** @name Analog Devices miscellaneous regiter bits used in AD1980.
199	* @{ */
200	#define AC97_AD_MISC_LOSEL RT_BIT(5) /*< Surround (rear) goes to line out outputs. /
201	#define AC97_AD_MISC_HPSEL RT_BIT(10) /*< PCM (front) goes to headphone outputs. /
202	/** @} */
203
204
205	/** @name BUP flag values.
206	* @{ */
207	#define BUP_SET RT_BIT_32(0)
208	#define BUP_LAST RT_BIT_32(1)
209	/** @} */
210
211	/** @name AC'97 source indices.
212	* @note The order of these indices is fixed (also applies for saved states) for
213	* the moment. So make sure you know what you're done when altering this!
214	* @{
215	*/
216	#define AC97SOUNDSOURCE_PI_INDEX 0 /*< PCM in /
217	#define AC97SOUNDSOURCE_PO_INDEX 1 /*< PCM out /
218	#define AC97SOUNDSOURCE_MC_INDEX 2 /*< Mic in /
219	#define AC97SOUNDSOURCE_MAX 3 /*< Max sound sources. /
220	/** @} */
221
222	/** Port number (offset into NABM BAR) to stream index. */
223	#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
224	/** Port number (offset into NABM BAR) to stream index, but no masking. */
225	#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
226
227	/** @name Stream offsets
228	* @{ */
229	#define AC97_NABM_OFF_BDBAR 0x0 /*< Buffer Descriptor Base Address /
230	#define AC97_NABM_OFF_CIV 0x4 /*< Current Index Value /
231	#define AC97_NABM_OFF_LVI 0x5 /*< Last Valid Index /
232	#define AC97_NABM_OFF_SR 0x6 /*< Status Register /
233	#define AC97_NABM_OFF_PICB 0x8 /*< Position in Current Buffer /
234	#define AC97_NABM_OFF_PIV 0xa /*< Prefetched Index Value /
235	#define AC97_NABM_OFF_CR 0xb /*< Control Register /
236	#define AC97_NABM_OFF_MASK 0xf /*< Mask for getting the the per-stream register. /
237	/** @} */
238
239
240	/** @name PCM in NABM BAR registers (0x00..0x0f).
241	* @{ */
242	#define PI_BDBAR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x0) /*< PCM in: Buffer Descriptor Base Address /
243	#define PI_CIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x4) /*< PCM in: Current Index Value /
244	#define PI_LVI (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x5) /*< PCM in: Last Valid Index /
245	#define PI_SR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x6) /*< PCM in: Status Register /
246	#define PI_PICB (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x8) /*< PCM in: Position in Current Buffer /
247	#define PI_PIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xa) /*< PCM in: Prefetched Index Value /
248	#define PI_CR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xb) /*< PCM in: Control Register /
249	/** @} */
250
251	/** @name PCM out NABM BAR registers (0x10..0x1f).
252	* @{ */
253	#define PO_BDBAR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x0) /*< PCM out: Buffer Descriptor Base Address /
254	#define PO_CIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x4) /*< PCM out: Current Index Value /
255	#define PO_LVI (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x5) /*< PCM out: Last Valid Index /
256	#define PO_SR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x6) /*< PCM out: Status Register /
257	#define PO_PICB (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x8) /*< PCM out: Position in Current Buffer /
258	#define PO_PIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xa) /*< PCM out: Prefetched Index Value /
259	#define PO_CR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xb) /*< PCM out: Control Register /
260	/** @} */
261
262	/** @name Mic in NABM BAR registers (0x20..0x2f).
263	* @{ */
264	#define MC_BDBAR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x0) /*< PCM in: Buffer Descriptor Base Address /
265	#define MC_CIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x4) /*< PCM in: Current Index Value /
266	#define MC_LVI (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x5) /*< PCM in: Last Valid Index /
267	#define MC_SR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x6) /*< PCM in: Status Register /
268	#define MC_PICB (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x8) /*< PCM in: Position in Current Buffer /
269	#define MC_PIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xa) /*< PCM in: Prefetched Index Value /
270	#define MC_CR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xb) /*< PCM in: Control Register /
271	/** @} */
272
273	/** @name Misc NABM BAR registers.
274	* @{ */
275	/** NABMBAR: Global Control Register.
276	* @note This is kind of in the MIC IN area. */
277	#define AC97_GLOB_CNT 0x2c
278	/** NABMBAR: Global Status. */
279	#define AC97_GLOB_STA 0x30
280	/** Codec Access Semaphore Register. */
281	#define AC97_CAS 0x34
282	/** @} */
283
284
285	/*********************************************************************************************************************************
286	* Structures and Typedefs *
287	*********************************************************************************************************************************/
288	/** The ICH AC'97 (Intel) controller (shared). */
289	typedef struct AC97STATE *PAC97STATE;
290	/** The ICH AC'97 (Intel) controller (ring-3). */
291	typedef struct AC97STATER3 *PAC97STATER3;
292
293	/**
294	* Buffer Descriptor List Entry (BDLE).
295	*/
296	typedef struct AC97BDLE
297	{
298	/** Location of data buffer (bits 31:1). */
299	uint32_t addr;
300	/** Flags (bits 31 + 30) and length (bits 15:0) of data buffer (in audio samples). */
301	uint32_t ctl_len;
302	} AC97BDLE;
303	AssertCompileSize(AC97BDLE, 8);
304	/** Pointer to BDLE. */
305	typedef AC97BDLE *PAC97BDLE;
306
307	/**
308	* Bus master register set for an audio stream.
309	*/
310	typedef struct AC97BMREGS
311	{
312	uint32_t bdbar; /*< rw 0, Buffer Descriptor List: BAR (Base Address Register). /
313	uint8_t civ; /*< ro 0, Current index value. /
314	uint8_t lvi; /*< rw 0, Last valid index. /
315	uint16_t sr; /*< rw 1, Status register. /
316	uint16_t picb; /*< ro 0, Position in current buffer (in samples). /
317	uint8_t piv; /*< ro 0, Prefetched index value. /
318	uint8_t cr; /*< rw 0, Control register. /
319	int32_t bd_valid; /*< Whether current BDLE is initialized or not. /
320	AC97BDLE bd; /*< Current Buffer Descriptor List Entry (BDLE). /
321	} AC97BMREGS;
322	AssertCompileSizeAlignment(AC97BMREGS, 8);
323	/** Pointer to the BM registers of an audio stream. */
324	typedef AC97BMREGS *PAC97BMREGS;
325
326	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
327	/**
328	* Asynchronous I/O state for an AC'97 stream.
329	*/
330	typedef struct AC97STREAMSTATEAIO
331	{
332	/** Thread handle for the actual I/O thread. */
333	RTTHREAD Thread;
334	/** Event for letting the thread know there is some data to process. */
335	RTSEMEVENT Event;
336	/** Critical section for synchronizing access. */
337	RTCRITSECT CritSect;
338	/** Started indicator. */
339	volatile bool fStarted;
340	/** Shutdown indicator. */
341	volatile bool fShutdown;
342	/** Whether the thread should do any data processing or not. */
343	volatile bool fEnabled;
344	bool afPadding[5];
345	} AC97STREAMSTATEAIO;
346	/** Pointer to the async I/O state for an AC'97 stream. */
347	typedef AC97STREAMSTATEAIO *PAC97STREAMSTATEAIO;
348	#endif
349
350
351	/**
352	* The internal state of an AC'97 stream.
353	*/
354	typedef struct AC97STREAMSTATE
355	{
356	/** Criticial section for this stream. */
357	RTCRITSECT CritSect;
358	/** Circular buffer (FIFO) for holding DMA'ed data. */
359	R3PTRTYPE(PRTCIRCBUF) pCircBuf;
360	#if HC_ARCH_BITS == 32
361	uint32_t Padding;
362	#endif
363	/** The stream's current configuration. */
364	PDMAUDIOSTREAMCFG Cfg; //+108
365	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
366	/** Asynchronous I/O state members. */
367	AC97STREAMSTATEAIO AIO;
368	#endif
369	/** Timestamp of the last DMA data transfer. */
370	uint64_t tsTransferLast;
371	/** Timestamp of the next DMA data transfer.
372	* Next for determining the next scheduling window.
373	* Can be 0 if no next transfer is scheduled. */
374	uint64_t tsTransferNext;
375	/** Transfer chunk size (in bytes) of a transfer period. */
376	uint32_t cbTransferChunk;
377	/** The stream's timer Hz rate.
378	* This value can can be different from the device's default Hz rate,
379	* depending on the rate the stream expects (e.g. for 5.1 speaker setups).
380	* Set in R3StreamInit(). */
381	uint16_t uTimerHz;
382	uint8_t Padding3[2];
383	/** (Virtual) clock ticks per transfer. */
384	uint64_t cTransferTicks;
385	/** Timestamp (in ns) of last stream update. */
386	uint64_t tsLastUpdateNs;
387	} AC97STREAMSTATE;
388	AssertCompileSizeAlignment(AC97STREAMSTATE, 8);
389	/** Pointer to internal state of an AC'97 stream. */
390	typedef AC97STREAMSTATE *PAC97STREAMSTATE;
391
392	/**
393	* Runtime configurable debug stuff for an AC'97 stream.
394	*/
395	typedef struct AC97STREAMDEBUGRT
396	{
397	/** Whether debugging is enabled or not. */
398	bool fEnabled;
399	uint8_t Padding[7];
400	/** File for dumping stream reads / writes.
401	* For input streams, this dumps data being written to the device FIFO,
402	* whereas for output streams this dumps data being read from the device FIFO. */
403	R3PTRTYPE(PPDMAUDIOFILE) pFileStream;
404	/** File for dumping DMA reads / writes.
405	* For input streams, this dumps data being written to the device DMA,
406	* whereas for output streams this dumps data being read from the device DMA. */
407	R3PTRTYPE(PPDMAUDIOFILE) pFileDMA;
408	} AC97STREAMDEBUGRT;
409
410	/**
411	* Debug stuff for an AC'97 stream.
412	*/
413	typedef struct AC97STREAMDEBUG
414	{
415	/** Runtime debug stuff. */
416	AC97STREAMDEBUGRT Runtime;
417	} AC97STREAMDEBUG;
418
419	/**
420	* The shared AC'97 stream state.
421	*/
422	typedef struct AC97STREAM
423	{
424	/** Stream number (SDn). */
425	uint8_t u8SD;
426	uint8_t abPadding0[7];
427	/** Bus master registers of this stream. */
428	AC97BMREGS Regs;
429	/** The timer for pumping data thru the attached LUN drivers. */
430	TMTIMERHANDLE hTimer;
431	} AC97STREAM;
432	AssertCompileSizeAlignment(AC97STREAM, 8);
433	/** Pointer to a shared AC'97 stream state. */
434	typedef AC97STREAM *PAC97STREAM;
435
436
437	/**
438	* The ring-3 AC'97 stream state.
439	*/
440	typedef struct AC97STREAMR3
441	{
442	/** Stream number (SDn). */
443	uint8_t u8SD;
444	uint8_t abPadding0[7];
445	/** Internal state of this stream. */
446	AC97STREAMSTATE State;
447	/** Debug stuff. */
448	AC97STREAMDEBUG Dbg;
449	} AC97STREAMR3;
450	AssertCompileSizeAlignment(AC97STREAMR3, 8);
451	/** Pointer to an AC'97 stream state for ring-3. */
452	typedef AC97STREAMR3 *PAC97STREAMR3;
453
454
455	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
456	/**
457	* Asynchronous I/O thread context (arguments).
458	*/
459	typedef struct AC97STREAMTHREADCTX
460	{
461	/** The AC'97 device state (shared). */
462	PAC97STATE pThis;
463	/** The AC'97 device state (ring-3). */
464	PAC97STATER3 pThisCC;
465	/** The AC'97 stream state (shared). */
466	PAC97STREAM pStream;
467	/** The AC'97 stream state (ring-3). */
468	PAC97STREAMR3 pStreamCC;
469	} AC97STREAMTHREADCTX;
470	/** Pointer to the context for an async I/O thread. */
471	typedef AC97STREAMTHREADCTX *PAC97STREAMTHREADCTX;
472	#endif
473
474	/**
475	* A driver stream (host backend).
476	*
477	* Each driver has its own instances of audio mixer streams, which then
478	* can go into the same (or even different) audio mixer sinks.
479	*/
480	typedef struct AC97DRIVERSTREAM
481	{
482	/** Associated mixer stream handle. */
483	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
484	} AC97DRIVERSTREAM;
485	/** Pointer to a driver stream. */
486	typedef AC97DRIVERSTREAM *PAC97DRIVERSTREAM;
487
488	/**
489	* A host backend driver (LUN).
490	*/
491	typedef struct AC97DRIVER
492	{
493	/** Node for storing this driver in our device driver list of AC97STATE. */
494	RTLISTNODER3 Node;
495	/** Driver flags. */
496	PDMAUDIODRVFLAGS fFlags;
497	/** LUN # to which this driver has been assigned. */
498	uint8_t uLUN;
499	/** Whether this driver is in an attached state or not. */
500	bool fAttached;
501	uint8_t abPadding[2];
502	/** Pointer to the description string passed to PDMDevHlpDriverAttach(). */
503	R3PTRTYPE(char *) pszDesc;
504	/** Pointer to attached driver base interface. */
505	R3PTRTYPE(PPDMIBASE) pDrvBase;
506	/** Audio connector interface to the underlying host backend. */
507	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
508	/** Driver stream for line input. */
509	AC97DRIVERSTREAM LineIn;
510	/** Driver stream for mic input. */
511	AC97DRIVERSTREAM MicIn;
512	/** Driver stream for output. */
513	AC97DRIVERSTREAM Out;
514	} AC97DRIVER;
515	/** Pointer to a host backend driver (LUN). */
516	typedef AC97DRIVER *PAC97DRIVER;
517
518	/**
519	* Debug settings.
520	*/
521	typedef struct AC97STATEDEBUG
522	{
523	/** Whether debugging is enabled or not. */
524	bool fEnabled;
525	bool afAlignment[7];
526	/** Path where to dump the debug output to.
527	* Defaults to VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH. */
528	R3PTRTYPE(char *) pszOutPath;
529	} AC97STATEDEBUG;
530
531
532	/* Codec models. */
533	typedef enum AC97CODEC
534	{
535	AC97CODEC_INVALID = 0, /*< Customary illegal zero value. /
536	AC97CODEC_STAC9700, /*< SigmaTel STAC9700 /
537	AC97CODEC_AD1980, /*< Analog Devices AD1980 /
538	AC97CODEC_AD1981B, /*< Analog Devices AD1981B /
539	AC97CODEC_32BIT_HACK = 0x7fffffff
540	} AC97CODEC;
541
542
543	/**
544	* The shared AC'97 device state.
545	*/
546	typedef struct AC97STATE
547	{
548	/** Critical section protecting the AC'97 state. */
549	PDMCRITSECT CritSect;
550	/** Global Control (Bus Master Control Register). */
551	uint32_t glob_cnt;
552	/** Global Status (Bus Master Control Register). */
553	uint32_t glob_sta;
554	/** Codec Access Semaphore Register (Bus Master Control Register). */
555	uint32_t cas;
556	uint32_t last_samp;
557	uint8_t mixer_data[256];
558	/** Array of AC'97 streams (parallel to AC97STATER3::aStreams). */
559	AC97STREAM aStreams[AC97_MAX_STREAMS];
560	/** The device timer Hz rate. Defaults to AC97_TIMER_HZ_DEFAULT_DEFAULT. */
561	uint16_t uTimerHz;
562	uint16_t au16Padding1[3];
563	uint8_t silence[128];
564	uint32_t bup_flag;
565	/** Codec model. */
566	AC97CODEC enmCodecModel;
567
568	/** PCI region \#0: NAM I/O ports. */
569	IOMIOPORTHANDLE hIoPortsNam;
570	/** PCI region \#0: NANM I/O ports. */
571	IOMIOPORTHANDLE hIoPortsNabm;
572
573	STAMCOUNTER StatUnimplementedNabmReads;
574	STAMCOUNTER StatUnimplementedNabmWrites;
575	#ifdef VBOX_WITH_STATISTICS
576	STAMPROFILE StatTimer;
577	STAMPROFILE StatIn;
578	STAMPROFILE StatOut;
579	STAMCOUNTER StatBytesRead;
580	STAMCOUNTER StatBytesWritten;
581	#endif
582	} AC97STATE;
583	AssertCompileMemberAlignment(AC97STATE, aStreams, 8);
584	AssertCompileMemberAlignment(AC97STATE, StatUnimplementedNabmReads, 8);
585	#ifdef VBOX_WITH_STATISTICS
586	AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
587	AssertCompileMemberAlignment(AC97STATE, StatBytesRead, 8);
588	AssertCompileMemberAlignment(AC97STATE, StatBytesWritten, 8);
589	#endif
590
591
592	/**
593	* The ring-3 AC'97 device state.
594	*/
595	typedef struct AC97STATER3
596	{
597	/** Array of AC'97 streams (parallel to AC97STATE:aStreams). */
598	AC97STREAMR3 aStreams[AC97_MAX_STREAMS];
599	/** R3 pointer to the device instance. */
600	PPDMDEVINSR3 pDevIns;
601	/** List of associated LUN drivers (AC97DRIVER). */
602	RTLISTANCHORR3 lstDrv;
603	/** The device's software mixer. */
604	R3PTRTYPE(PAUDIOMIXER) pMixer;
605	/** Audio sink for PCM output. */
606	R3PTRTYPE(PAUDMIXSINK) pSinkOut;
607	/** Audio sink for line input. */
608	R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
609	/** Audio sink for microphone input. */
610	R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
611	/** The base interface for LUN\#0. */
612	PDMIBASE IBase;
613	/** Debug settings. */
614	AC97STATEDEBUG Dbg;
615	} AC97STATER3;
616	AssertCompileMemberAlignment(AC97STATER3, aStreams, 8);
617	/** Pointer to the ring-3 AC'97 device state. */
618	typedef AC97STATER3 *PAC97STATER3;
619
620
621	/**
622	* Acquires the AC'97 lock.
623	*/
624	#define DEVAC97_LOCK(a_pDevIns, a_pThis) \
625	do { \
626	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
627	AssertRC(rcLock); \
628	} while (0)
629
630	/**
631	* Acquires the AC'97 lock or returns.
632	*/
633	# define DEVAC97_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
634	do { \
635	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, a_rcBusy); \
636	if (rcLock == VINF_SUCCESS) \
637	break; \
638	AssertRC(rcLock); \
639	return rcLock; \
640	} while (0)
641
642	/** Retrieves an attribute from a specific audio stream in RC. */
643	#define DEVAC97_CTX_SUFF_SD(a_Var, a_SD) CTX_SUFF(a_Var)[a_SD]
644
645	/**
646	* Releases the AC'97 lock.
647	*/
648	#define DEVAC97_UNLOCK(a_pDevIns, a_pThis) \
649	do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
650
651	/**
652	* Acquires the TM lock and AC'97 lock, returns on failure.
653	*
654	* @todo r=bird: Isn't this overkill for ring-0, only ring-3 access the timer
655	* from what I can tell (ichac97R3StreamTransferCalcNext,
656	* ichac97R3TimerSet, timer callback and state load).
657	*/
658	#define DEVAC97_LOCK_BOTH_RETURN(a_pDevIns, a_pThis, a_pStream, a_rcBusy) \
659	do { \
660	VBOXSTRICTRC rcLock = PDMDevHlpTimerLockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect, (a_rcBusy)); \
661	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
662	{ /* likely */ } \
663	else \
664	{ \
665	AssertRC(VBOXSTRICTRC_VAL(rcLock)); \
666	return rcLock; \
667	} \
668	} while (0)
669
670	/**
671	* Releases the AC'97 lock and TM lock.
672	*/
673	#define DEVAC97_UNLOCK_BOTH(a_pDevIns, a_pThis, a_pStream) \
674	PDMDevHlpTimerUnlockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect)
675
676	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
677
678
679	/*********************************************************************************************************************************
680	* Internal Functions *
681	*********************************************************************************************************************************/
682	#ifdef IN_RING3
683	static int ichac97R3StreamOpen(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce);
684	static int ichac97R3StreamClose(PAC97STREAM pStream);
685	static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC);
686	static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC);
687	static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC);
688	static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC);
689	static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
690	PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax);
691	static void ichac97R3StreamUpdate(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
692	PAC97STREAMR3 pStreamCC, bool fInTimer);
693
694	static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns);
695
696	static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
697
698	static void ichac97R3MixerRemoveDrvStreams(PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir,
699	PDMAUDIODSTSRCUNION dstSrc);
700
701	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
702	static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC);
703	static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAMR3 pStreamCC);
704	static void ichac97R3StreamAsyncIOLock(PAC97STREAMR3 pStreamCC);
705	static void ichac97R3StreamAsyncIOUnlock(PAC97STREAMR3 pStreamCC);
706	/static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable); Unused /
707	# endif
708
709	DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD);
710	DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline);
711	#endif /* IN_RING3 */
712
713
714	/*********************************************************************************************************************************
715	* Global Variables *
716	*********************************************************************************************************************************/
717	#ifdef IN_RING3
718	/** NABM I/O port descriptions. */
719	static const IOMIOPORTDESC g_aNabmPorts[] =
720	{
721	{ "PCM IN - BDBAR", "PCM IN - BDBAR", NULL, NULL },
722	{ "", NULL, NULL, NULL },
723	{ "", NULL, NULL, NULL },
724	{ "", NULL, NULL, NULL },
725	{ "PCM IN - CIV", "PCM IN - CIV", NULL, NULL },
726	{ "PCM IN - LVI", "PCM IN - LIV", NULL, NULL },
727	{ "PCM IN - SR", "PCM IN - SR", NULL, NULL },
728	{ "", NULL, NULL, NULL },
729	{ "PCM IN - PICB", "PCM IN - PICB", NULL, NULL },
730	{ "", NULL, NULL, NULL },
731	{ "PCM IN - PIV", "PCM IN - PIV", NULL, NULL },
732	{ "PCM IN - CR", "PCM IN - CR", NULL, NULL },
733	{ "", NULL, NULL, NULL },
734	{ "", NULL, NULL, NULL },
735	{ "", NULL, NULL, NULL },
736	{ "", NULL, NULL, NULL },
737
738	{ "PCM OUT - BDBAR", "PCM OUT - BDBAR", NULL, NULL },
739	{ "", NULL, NULL, NULL },
740	{ "", NULL, NULL, NULL },
741	{ "", NULL, NULL, NULL },
742	{ "PCM OUT - CIV", "PCM OUT - CIV", NULL, NULL },
743	{ "PCM OUT - LVI", "PCM OUT - LIV", NULL, NULL },
744	{ "PCM OUT - SR", "PCM OUT - SR", NULL, NULL },
745	{ "", NULL, NULL, NULL },
746	{ "PCM OUT - PICB", "PCM OUT - PICB", NULL, NULL },
747	{ "", NULL, NULL, NULL },
748	{ "PCM OUT - PIV", "PCM OUT - PIV", NULL, NULL },
749	{ "PCM OUT - CR", "PCM IN - CR", NULL, NULL },
750	{ "", NULL, NULL, NULL },
751	{ "", NULL, NULL, NULL },
752	{ "", NULL, NULL, NULL },
753	{ "", NULL, NULL, NULL },
754
755	{ "MIC IN - BDBAR", "MIC IN - BDBAR", NULL, NULL },
756	{ "", NULL, NULL, NULL },
757	{ "", NULL, NULL, NULL },
758	{ "", NULL, NULL, NULL },
759	{ "MIC IN - CIV", "MIC IN - CIV", NULL, NULL },
760	{ "MIC IN - LVI", "MIC IN - LIV", NULL, NULL },
761	{ "MIC IN - SR", "MIC IN - SR", NULL, NULL },
762	{ "", NULL, NULL, NULL },
763	{ "MIC IN - PICB", "MIC IN - PICB", NULL, NULL },
764	{ "", NULL, NULL, NULL },
765	{ "MIC IN - PIV", "MIC IN - PIV", NULL, NULL },
766	{ "MIC IN - CR", "MIC IN - CR", NULL, NULL },
767	{ "GLOB CNT", "GLOB CNT", NULL, NULL },
768	{ "", NULL, NULL, NULL },
769	{ "", NULL, NULL, NULL },
770	{ "", NULL, NULL, NULL },
771
772	{ "GLOB STA", "GLOB STA", NULL, NULL },
773	{ "", NULL, NULL, NULL },
774	{ "", NULL, NULL, NULL },
775	{ "", NULL, NULL, NULL },
776	{ "CAS", "CAS", NULL, NULL },
777	{ NULL, NULL, NULL, NULL },
778	};
779
780	/** @name Source indices
781	* @{ */
782	#define AC97SOUNDSOURCE_PI_INDEX 0 /*< PCM in /
783	#define AC97SOUNDSOURCE_PO_INDEX 1 /*< PCM out /
784	#define AC97SOUNDSOURCE_MC_INDEX 2 /*< Mic in /
785	#define AC97SOUNDSOURCE_MAX 3 /*< Max sound sources. /
786	/** @} */
787
788	/** Port number (offset into NABM BAR) to stream index. */
789	#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
790	/** Port number (offset into NABM BAR) to stream index, but no masking. */
791	#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
792
793	/** @name Stream offsets
794	* @{ */
795	#define AC97_NABM_OFF_BDBAR 0x0 /*< Buffer Descriptor Base Address /
796	#define AC97_NABM_OFF_CIV 0x4 /*< Current Index Value /
797	#define AC97_NABM_OFF_LVI 0x5 /*< Last Valid Index /
798	#define AC97_NABM_OFF_SR 0x6 /*< Status Register /
799	#define AC97_NABM_OFF_PICB 0x8 /*< Position in Current Buffer /
800	#define AC97_NABM_OFF_PIV 0xa /*< Prefetched Index Value /
801	#define AC97_NABM_OFF_CR 0xb /*< Control Register /
802	#define AC97_NABM_OFF_MASK 0xf /*< Mask for getting the the per-stream register. /
803	/** @} */
804
805	#endif
806
807
808
809	static void ichac97WarmReset(PAC97STATE pThis)
810	{
811	NOREF(pThis);
812	}
813
814	static void ichac97ColdReset(PAC97STATE pThis)
815	{
816	NOREF(pThis);
817	}
818
819
820	#ifdef IN_RING3
821
822	/**
823	* Retrieves the audio mixer sink of a corresponding AC'97 stream index.
824	*
825	* @returns Pointer to audio mixer sink if found, or NULL if not found / invalid.
826	* @param pThisCC The ring-3 AC'97 state.
827	* @param uIndex Stream index to get audio mixer sink for.
828	*/
829	DECLINLINE(PAUDMIXSINK) ichac97R3IndexToSink(PAC97STATER3 pThisCC, uint8_t uIndex)
830	{
831	switch (uIndex)
832	{
833	case AC97SOUNDSOURCE_PI_INDEX: return pThisCC->pSinkLineIn;
834	case AC97SOUNDSOURCE_PO_INDEX: return pThisCC->pSinkOut;
835	case AC97SOUNDSOURCE_MC_INDEX: return pThisCC->pSinkMicIn;
836	default:
837	AssertMsgFailedReturn(("Wrong index %RU8\n", uIndex), NULL);
838	}
839	}
840
841	/**
842	* Fetches the current BDLE (Buffer Descriptor List Entry) of an AC'97 audio stream.
843	*
844	* @returns IPRT status code.
845	* @param pDevIns The device instance.
846	* @param pStream AC'97 stream to fetch BDLE for.
847	*
848	* @remark Uses CIV as BDLE index.
849	*/
850	static void ichac97R3StreamFetchBDLE(PPDMDEVINS pDevIns, PAC97STREAM pStream)
851	{
852	PAC97BMREGS pRegs = &pStream->Regs;
853
854	AC97BDLE BDLE;
855	PDMDevHlpPCIPhysRead(pDevIns, pRegs->bdbar + pRegs->civ * sizeof(AC97BDLE), &BDLE, sizeof(AC97BDLE));
856	pRegs->bd_valid = 1;
857	# ifndef RT_LITTLE_ENDIAN
858	# error "Please adapt the code (audio buffers are little endian)!"
859	# else
860	pRegs->bd.addr = RT_H2LE_U32(BDLE.addr & ~3);
861	pRegs->bd.ctl_len = RT_H2LE_U32(BDLE.ctl_len);
862	# endif
863	pRegs->picb = pRegs->bd.ctl_len & AC97_BD_LEN_MASK;
864	LogFlowFunc(("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes), bup=%RTbool, ioc=%RTbool\n",
865	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len >> 16,
866	pRegs->bd.ctl_len & AC97_BD_LEN_MASK,
867	(pRegs->bd.ctl_len & AC97_BD_LEN_MASK) << 1, /** @todo r=andy Assumes 16bit samples. */
868	RT_BOOL(pRegs->bd.ctl_len & AC97_BD_BUP),
869	RT_BOOL(pRegs->bd.ctl_len & AC97_BD_IOC)));
870	}
871
872	#endif /* IN_RING3 */
873
874	/**
875	* Updates the status register (SR) of an AC'97 audio stream.
876	*
877	* @param pDevIns The device instance.
878	* @param pThis The shared AC'97 state.
879	* @param pStream AC'97 stream to update SR for.
880	* @param new_sr New value for status register (SR).
881	*/
882	static void ichac97StreamUpdateSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr)
883	{
884	PAC97BMREGS pRegs = &pStream->Regs;
885
886	bool fSignal = false;
887	int iIRQL = 0;
888
889	uint32_t new_mask = new_sr & AC97_SR_INT_MASK;
890	uint32_t old_mask = pRegs->sr & AC97_SR_INT_MASK;
891
892	if (new_mask ^ old_mask)
893	{
894	/** @todo Is IRQ deasserted when only one of status bits is cleared? */
895	if (!new_mask)
896	{
897	fSignal = true;
898	iIRQL = 0;
899	}
900	else if ((new_mask & AC97_SR_LVBCI) && (pRegs->cr & AC97_CR_LVBIE))
901	{
902	fSignal = true;
903	iIRQL = 1;
904	}
905	else if ((new_mask & AC97_SR_BCIS) && (pRegs->cr & AC97_CR_IOCE))
906	{
907	fSignal = true;
908	iIRQL = 1;
909	}
910	}
911
912	pRegs->sr = new_sr;
913
914	LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n",
915	pRegs->sr & AC97_SR_BCIS, pRegs->sr & AC97_SR_LVBCI, pRegs->sr, fSignal, iIRQL));
916
917	if (fSignal)
918	{
919	static uint32_t const s_aMasks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT };
920	Assert(pStream->u8SD < AC97_MAX_STREAMS);
921	if (iIRQL)
922	pThis->glob_sta \|= s_aMasks[pStream->u8SD];
923	else
924	pThis->glob_sta &= ~s_aMasks[pStream->u8SD];
925
926	LogFlowFunc(("Setting IRQ level=%d\n", iIRQL));
927	PDMDevHlpPCISetIrq(pDevIns, 0, iIRQL);
928	}
929	}
930
931	/**
932	* Writes a new value to a stream's status register (SR).
933	*
934	* @param pDevIns The device instance.
935	* @param pThis The shared AC'97 device state.
936	* @param pStream Stream to update SR for.
937	* @param u32Val New value to set the stream's SR to.
938	*/
939	static void ichac97StreamWriteSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t u32Val)
940	{
941	PAC97BMREGS pRegs = &pStream->Regs;
942
943	Log3Func(("[SD%RU8] SR <- %#x (sr %#x)\n", pStream->u8SD, u32Val, pRegs->sr));
944
945	pRegs->sr \|= u32Val & ~(AC97_SR_RO_MASK \| AC97_SR_WCLEAR_MASK);
946	ichac97StreamUpdateSR(pDevIns, pThis, pStream, pRegs->sr & ~(u32Val & AC97_SR_WCLEAR_MASK));
947	}
948
949	#ifdef IN_RING3
950
951	/**
952	* Returns whether an AC'97 stream is enabled or not.
953	*
954	* @returns IPRT status code.
955	* @param pThisCC The ring-3 AC'97 device state.
956	* @param pStream Stream to return status for.
957	*/
958	static bool ichac97R3StreamIsEnabled(PAC97STATER3 pThisCC, PAC97STREAM pStream)
959	{
960	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
961	bool fIsEnabled = RT_BOOL(AudioMixerSinkGetStatus(pSink) & AUDMIXSINK_STS_RUNNING);
962
963	LogFunc(("[SD%RU8] fIsEnabled=%RTbool\n", pStream->u8SD, fIsEnabled));
964	return fIsEnabled;
965	}
966
967	/**
968	* Enables or disables an AC'97 audio stream.
969	*
970	* @returns IPRT status code.
971	* @param pThis The shared AC'97 state.
972	* @param pThisCC The ring-3 AC'97 state.
973	* @param pStream The AC'97 stream to enable or disable (shared
974	* state).
975	* @param pStreamCC The ring-3 stream state (matching to @a pStream).
976	* @param fEnable Whether to enable or disable the stream.
977	*
978	*/
979	static int ichac97R3StreamEnable(PAC97STATE pThis, PAC97STATER3 pThisCC,
980	PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fEnable)
981	{
982	ichac97R3StreamLock(pStreamCC);
983
984	int rc = VINF_SUCCESS;
985
986	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
987	if (fEnable)
988	rc = ichac97R3StreamAsyncIOCreate(pThis, pThisCC, pStream, pStreamCC);
989	if (RT_SUCCESS(rc))
990	ichac97R3StreamAsyncIOLock(pStreamCC);
991	# endif
992
993	if (fEnable)
994	{
995	if (pStreamCC->State.pCircBuf)
996	RTCircBufReset(pStreamCC->State.pCircBuf);
997
998	rc = ichac97R3StreamOpen(pThis, pThisCC, pStream, pStreamCC, false /* fForce */);
999
1000	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1001	{ /* likely */ }
1002	else
1003	{
1004	if (!DrvAudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileStream))
1005	{
1006	int rc2 = DrvAudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileStream, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
1007	&pStreamCC->State.Cfg.Props);
1008	AssertRC(rc2);
1009	}
1010
1011	if (!DrvAudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileDMA))
1012	{
1013	int rc2 = DrvAudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileDMA, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
1014	&pStreamCC->State.Cfg.Props);
1015	AssertRC(rc2);
1016	}
1017	}
1018	}
1019	else
1020	rc = ichac97R3StreamClose(pStream);
1021
1022	if (RT_SUCCESS(rc))
1023	{
1024	/* First, enable or disable the stream and the stream's sink, if any. */
1025	rc = AudioMixerSinkCtl(ichac97R3IndexToSink(pThisCC, pStream->u8SD),
1026	fEnable ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE);
1027	}
1028
1029	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1030	ichac97R3StreamAsyncIOUnlock(pStreamCC);
1031	# endif
1032
1033	/* Make sure to leave the lock before (eventually) starting the timer. */
1034	ichac97R3StreamUnlock(pStreamCC);
1035
1036	LogFunc(("[SD%RU8] fEnable=%RTbool, rc=%Rrc\n", pStream->u8SD, fEnable, rc));
1037	return rc;
1038	}
1039
1040	/**
1041	* Resets an AC'97 stream.
1042	*
1043	* @param pThis The shared AC'97 state.
1044	* @param pStream The AC'97 stream to reset (shared).
1045	* @param pStreamCC The AC'97 stream to reset (ring-3).
1046	*/
1047	static void ichac97R3StreamReset(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1048	{
1049	ichac97R3StreamLock(pStreamCC);
1050
1051	LogFunc(("[SD%RU8]\n", pStream->u8SD));
1052
1053	if (pStreamCC->State.pCircBuf)
1054	RTCircBufReset(pStreamCC->State.pCircBuf);
1055
1056	PAC97BMREGS pRegs = &pStream->Regs;
1057
1058	pRegs->bdbar = 0;
1059	pRegs->civ = 0;
1060	pRegs->lvi = 0;
1061
1062	pRegs->picb = 0;
1063	pRegs->piv = 0;
1064	pRegs->cr = pRegs->cr & AC97_CR_DONT_CLEAR_MASK;
1065	pRegs->bd_valid = 0;
1066
1067	RT_ZERO(pThis->silence);
1068
1069	ichac97R3StreamUnlock(pStreamCC);
1070	}
1071
1072	/**
1073	* Creates an AC'97 audio stream.
1074	*
1075	* @returns IPRT status code.
1076	* @param pThisCC The ring-3 AC'97 state.
1077	* @param pStream The AC'97 stream to create (shared).
1078	* @param pStreamCC The AC'97 stream to create (ring-3).
1079	* @param u8SD Stream descriptor number to assign.
1080	*/
1081	static int ichac97R3StreamCreate(PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint8_t u8SD)
1082	{
1083	LogFunc(("[SD%RU8] pStream=%p\n", u8SD, pStream));
1084
1085	AssertReturn(u8SD < AC97_MAX_STREAMS, VERR_INVALID_PARAMETER);
1086	pStream->u8SD = u8SD;
1087	pStreamCC->u8SD = u8SD;
1088
1089	int rc = RTCritSectInit(&pStreamCC->State.CritSect);
1090	AssertRCReturn(rc, rc);
1091
1092	pStreamCC->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
1093
1094	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1095	{ /* likely */ }
1096	else
1097	{
1098	char szFile[64];
1099
1100	if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1101	RTStrPrintf(szFile, sizeof(szFile), "ac97StreamWriteSD%RU8", pStream->u8SD);
1102	else
1103	RTStrPrintf(szFile, sizeof(szFile), "ac97StreamReadSD%RU8", pStream->u8SD);
1104
1105	char szPath[RTPATH_MAX];
1106	int rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1107	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
1108	AssertRC(rc2);
1109	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileStream);
1110	AssertRC(rc2);
1111
1112	if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1113	RTStrPrintf(szFile, sizeof(szFile), "ac97DMAWriteSD%RU8", pStream->u8SD);
1114	else
1115	RTStrPrintf(szFile, sizeof(szFile), "ac97DMAReadSD%RU8", pStream->u8SD);
1116
1117	rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1118	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
1119	AssertRC(rc2);
1120
1121	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileDMA);
1122	AssertRC(rc2);
1123
1124	/* Delete stale debugging files from a former run. */
1125	DrvAudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileStream);
1126	DrvAudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileDMA);
1127	}
1128
1129	return rc;
1130	}
1131
1132	/**
1133	* Destroys an AC'97 audio stream.
1134	*
1135	* @returns IPRT status code.
1136	* @param pThis The shared AC'97 state.
1137	* @param pStream The AC'97 stream to destroy (shared).
1138	* @param pStreamCC The AC'97 stream to destroy (ring-3).
1139	*/
1140	static void ichac97R3StreamDestroy(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1141	{
1142	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
1143
1144	ichac97R3StreamClose(pStream);
1145
1146	int rc2 = RTCritSectDelete(&pStreamCC->State.CritSect);
1147	AssertRC(rc2);
1148
1149	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1150	rc2 = ichac97R3StreamAsyncIODestroy(pThis, pStreamCC);
1151	AssertRC(rc2);
1152	# else
1153	RT_NOREF(pThis);
1154	# endif
1155
1156	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1157	{ /* likely */ }
1158	else
1159	{
1160	DrvAudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileStream);
1161	pStreamCC->Dbg.Runtime.pFileStream = NULL;
1162
1163	DrvAudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileDMA);
1164	pStreamCC->Dbg.Runtime.pFileDMA = NULL;
1165	}
1166
1167	if (pStreamCC->State.pCircBuf)
1168	{
1169	RTCircBufDestroy(pStreamCC->State.pCircBuf);
1170	pStreamCC->State.pCircBuf = NULL;
1171	}
1172
1173	LogFlowFuncLeave();
1174	}
1175
1176	/**
1177	* Destroys all AC'97 audio streams of the device.
1178	*
1179	* @param pThis The shared AC'97 state.
1180	* @param pThisCC The ring-3 AC'97 state.
1181	*/
1182	static void ichac97R3StreamsDestroy(PAC97STATE pThis, PAC97STATER3 pThisCC)
1183	{
1184	LogFlowFuncEnter();
1185
1186	/*
1187	* Destroy all AC'97 streams.
1188	*/
1189	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
1190	ichac97R3StreamDestroy(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
1191
1192	/*
1193	* Destroy all sinks.
1194	*/
1195
1196	PDMAUDIODSTSRCUNION dstSrc;
1197	if (pThisCC->pSinkLineIn)
1198	{
1199	dstSrc.enmSrc = PDMAUDIORECSRC_LINE;
1200	ichac97R3MixerRemoveDrvStreams(pThisCC, pThisCC->pSinkLineIn, PDMAUDIODIR_IN, dstSrc);
1201
1202	AudioMixerSinkDestroy(pThisCC->pSinkLineIn);
1203	pThisCC->pSinkLineIn = NULL;
1204	}
1205
1206	if (pThisCC->pSinkMicIn)
1207	{
1208	dstSrc.enmSrc = PDMAUDIORECSRC_MIC;
1209	ichac97R3MixerRemoveDrvStreams(pThisCC, pThisCC->pSinkMicIn, PDMAUDIODIR_IN, dstSrc);
1210
1211	AudioMixerSinkDestroy(pThisCC->pSinkMicIn);
1212	pThisCC->pSinkMicIn = NULL;
1213	}
1214
1215	if (pThisCC->pSinkOut)
1216	{
1217	dstSrc.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
1218	ichac97R3MixerRemoveDrvStreams(pThisCC, pThisCC->pSinkOut, PDMAUDIODIR_OUT, dstSrc);
1219
1220	AudioMixerSinkDestroy(pThisCC->pSinkOut);
1221	pThisCC->pSinkOut = NULL;
1222	}
1223	}
1224
1225	/**
1226	* Writes audio data from a mixer sink into an AC'97 stream's DMA buffer.
1227	*
1228	* @returns IPRT status code.
1229	* @param pDstStreamCC The AC'97 stream to write to (ring-3).
1230	* @param pSrcMixSink Mixer sink to get audio data to write from.
1231	* @param cbToWrite Number of bytes to write.
1232	* @param pcbWritten Number of bytes written. Optional.
1233	*/
1234	static int ichac97R3StreamWrite(PAC97STREAMR3 pDstStreamCC, PAUDMIXSINK pSrcMixSink, uint32_t cbToWrite, uint32_t *pcbWritten)
1235	{
1236	AssertPtrReturn(pSrcMixSink, VERR_INVALID_POINTER);
1237	AssertReturn(cbToWrite > 0, VERR_INVALID_PARAMETER);
1238	/* pcbWritten is optional. */
1239
1240	PRTCIRCBUF pCircBuf = pDstStreamCC->State.pCircBuf;
1241	AssertPtr(pCircBuf);
1242
1243	uint32_t cbRead = 0;
1244
1245	void *pvDst;
1246	size_t cbDst;
1247	RTCircBufAcquireWriteBlock(pCircBuf, cbToWrite, &pvDst, &cbDst);
1248
1249	if (cbDst)
1250	{
1251	int rc2 = AudioMixerSinkRead(pSrcMixSink, AUDMIXOP_COPY, pvDst, (uint32_t)cbDst, &cbRead);
1252	AssertRC(rc2);
1253
1254	if (RT_LIKELY(!pDstStreamCC->Dbg.Runtime.fEnabled))
1255	{ /* likely */ }
1256	else
1257	DrvAudioHlpFileWrite(pDstStreamCC->Dbg.Runtime.pFileStream, pvDst, cbRead, 0 /* fFlags */);
1258	}
1259
1260	RTCircBufReleaseWriteBlock(pCircBuf, cbRead);
1261
1262	if (pcbWritten)
1263	*pcbWritten = cbRead;
1264
1265	return VINF_SUCCESS;
1266	}
1267
1268	/**
1269	* Reads audio data from an AC'97 stream's DMA buffer and writes into a specified mixer sink.
1270	*
1271	* @returns IPRT status code.
1272	* @param pSrcStreamCC AC'97 stream to read audio data from (ring-3).
1273	* @param pDstMixSink Mixer sink to write audio data to.
1274	* @param cbToRead Number of bytes to read.
1275	* @param pcbRead Number of bytes read. Optional.
1276	*/
1277	static int ichac97R3StreamRead(PAC97STREAMR3 pSrcStreamCC, PAUDMIXSINK pDstMixSink, uint32_t cbToRead, uint32_t *pcbRead)
1278	{
1279	AssertPtrReturn(pDstMixSink, VERR_INVALID_POINTER);
1280	AssertReturn(cbToRead > 0, VERR_INVALID_PARAMETER);
1281	/* pcbRead is optional. */
1282
1283	PRTCIRCBUF pCircBuf = pSrcStreamCC->State.pCircBuf;
1284	AssertPtr(pCircBuf);
1285
1286	void *pvSrc;
1287	size_t cbSrc;
1288
1289	int rc = VINF_SUCCESS;
1290
1291	uint32_t cbReadTotal = 0;
1292	uint32_t cbLeft = RT_MIN(cbToRead, (uint32_t)RTCircBufUsed(pCircBuf));
1293
1294	while (cbLeft)
1295	{
1296	uint32_t cbWritten = 0;
1297
1298	RTCircBufAcquireReadBlock(pCircBuf, cbLeft, &pvSrc, &cbSrc);
1299
1300	if (cbSrc)
1301	{
1302	if (RT_LIKELY(!pSrcStreamCC->Dbg.Runtime.fEnabled))
1303	{ /* likely */ }
1304	else
1305	DrvAudioHlpFileWrite(pSrcStreamCC->Dbg.Runtime.pFileStream, pvSrc, cbSrc, 0 /* fFlags */);
1306
1307	rc = AudioMixerSinkWrite(pDstMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbWritten);
1308	AssertRC(rc);
1309
1310	Assert(cbSrc >= cbWritten);
1311	Log3Func(("[SD%RU8] %RU32/%zu bytes read\n", pSrcStreamCC->u8SD, cbWritten, cbSrc));
1312	}
1313
1314	RTCircBufReleaseReadBlock(pCircBuf, cbWritten);
1315
1316	if ( !cbWritten /* Nothing written? */
1317	\|\| RT_FAILURE(rc))
1318	break;
1319
1320	Assert(cbLeft >= cbWritten);
1321	cbLeft -= cbWritten;
1322
1323	cbReadTotal += cbWritten;
1324	}
1325
1326	if (pcbRead)
1327	*pcbRead = cbReadTotal;
1328
1329	return rc;
1330	}
1331
1332	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1333
1334	/**
1335	* Asynchronous I/O thread for an AC'97 stream.
1336	* This will do the heavy lifting work for us as soon as it's getting notified by another thread.
1337	*
1338	* @returns IPRT status code.
1339	* @param hThreadSelf Thread handle.
1340	* @param pvUser User argument. Must be of type PAC97STREAMTHREADCTX.
1341	*/
1342	static DECLCALLBACK(int) ichac97R3StreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
1343	{
1344	PAC97STREAMTHREADCTX pCtx = (PAC97STREAMTHREADCTX)pvUser;
1345	AssertPtr(pCtx);
1346
1347	PAC97STATE pThis = pCtx->pThis;
1348	AssertPtr(pThis);
1349
1350	PAC97STATER3 pThisCC = pCtx->pThisCC;
1351	AssertPtr(pThisCC);
1352
1353	PAC97STREAM pStream = pCtx->pStream;
1354	AssertPtr(pStream);
1355
1356	PAC97STREAMR3 pStreamCC = pCtx->pStreamCC;
1357	AssertPtr(pStreamCC);
1358
1359	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1360
1361	ASMAtomicXchgBool(&pAIO->fStarted, true);
1362
1363	RTThreadUserSignal(hThreadSelf);
1364
1365	LogFunc(("[SD%RU8] Started\n", pStream->u8SD));
1366
1367	for (;;)
1368	{
1369	Log2Func(("[SD%RU8] Waiting ...\n", pStream->u8SD));
1370
1371	int rc2 = RTSemEventWait(pAIO->Event, RT_INDEFINITE_WAIT);
1372	if (RT_FAILURE(rc2))
1373	break;
1374
1375	if (ASMAtomicReadBool(&pAIO->fShutdown))
1376	break;
1377
1378	rc2 = RTCritSectEnter(&pAIO->CritSect);
1379	if (RT_SUCCESS(rc2))
1380	{
1381	if (!pAIO->fEnabled)
1382	{
1383	RTCritSectLeave(&pAIO->CritSect);
1384	continue;
1385	}
1386
1387	ichac97R3StreamUpdate(pThisCC->pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fInTimer */);
1388
1389	int rc3 = RTCritSectLeave(&pAIO->CritSect);
1390	AssertRC(rc3);
1391	}
1392
1393	AssertRC(rc2);
1394	}
1395
1396	LogFunc(("[SD%RU8] Ended\n", pStream->u8SD));
1397
1398	ASMAtomicXchgBool(&pAIO->fStarted, false);
1399
1400	RTMemFree(pCtx);
1401	pCtx = NULL;
1402
1403	return VINF_SUCCESS;
1404	}
1405
1406	/**
1407	* Creates the async I/O thread for a specific AC'97 audio stream.
1408	*
1409	* @returns IPRT status code.
1410	* @param pThis The shared AC'97 state (shared).
1411	* @param pThisCC The shared AC'97 state (ring-3).
1412	* @param pStream AC'97 audio stream to create the async I/O thread for (shared).
1413	* @param pStreamCC AC'97 audio stream to create the async I/O thread for (ring-3).
1414	*/
1415	static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1416	{
1417	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1418
1419	int rc;
1420
1421	if (!ASMAtomicReadBool(&pAIO->fStarted))
1422	{
1423	pAIO->fShutdown = false;
1424	pAIO->fEnabled = true; /* Enabled by default. */
1425
1426	rc = RTSemEventCreate(&pAIO->Event);
1427	if (RT_SUCCESS(rc))
1428	{
1429	rc = RTCritSectInit(&pAIO->CritSect);
1430	if (RT_SUCCESS(rc))
1431	{
1432	/** @todo r=bird:
1433	* Why aren't this code using the PDM threads (PDMDevHlpThreadCreate)?
1434	* They would help you with managing stuff like VM suspending, resuming
1435	* and powering off.
1436	*
1437	* Finally, just create the threads at construction time. */
1438	PAC97STREAMTHREADCTX pCtx = (PAC97STREAMTHREADCTX)RTMemAllocZ(sizeof(AC97STREAMTHREADCTX));
1439	if (pCtx)
1440	{
1441	pCtx->pStream = pStream;
1442	pCtx->pStreamCC = pStreamCC;
1443	pCtx->pThis = pThis;
1444	pCtx->pThisCC = pThisCC;
1445
1446	rc = RTThreadCreateF(&pAIO->Thread, ichac97R3StreamAsyncIOThread, pCtx,
1447	0, RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, "ac97AIO%RU8", pStreamCC->u8SD);
1448	if (RT_SUCCESS(rc))
1449	rc = RTThreadUserWait(pAIO->Thread, 30 * 1000 /* 30s timeout */);
1450	}
1451	else
1452	rc = VERR_NO_MEMORY;
1453	}
1454	}
1455	}
1456	else
1457	rc = VINF_SUCCESS;
1458
1459	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamCC->u8SD, rc));
1460	return rc;
1461	}
1462
1463	/**
1464	* Lets the stream's async I/O thread know that there is some data to process.
1465	*
1466	* @returns IPRT status code.
1467	* @param pStreamCC The AC'97 stream to notify async I/O thread
1468	* for (ring-3).
1469	*/
1470	static int ichac97R3StreamAsyncIONotify(PAC97STREAMR3 pStreamCC)
1471	{
1472	LogFunc(("[SD%RU8]\n", pStreamCC->u8SD));
1473	return RTSemEventSignal(pStreamCC->State.AIO.Event);
1474	}
1475
1476	/**
1477	* Destroys the async I/O thread of a specific AC'97 audio stream.
1478	*
1479	* @returns IPRT status code.
1480	* @param pThis The shared AC'97 state.
1481	* @param pStreamCC AC'97 audio stream to destroy the async I/O thread for.
1482	*/
1483	static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAMR3 pStreamR3)
1484	{
1485	RT_NOREF(pThis);
1486
1487	PAC97STREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
1488
1489	if (!ASMAtomicReadBool(&pAIO->fStarted))
1490	return VINF_SUCCESS;
1491
1492	ASMAtomicWriteBool(&pAIO->fShutdown, true);
1493
1494	int rc = ichac97R3StreamAsyncIONotify(pStreamR3);
1495	AssertRC(rc);
1496
1497	int rcThread;
1498	rc = RTThreadWait(pAIO->Thread, 30 * 1000 /* 30s timeout */, &rcThread);
1499	LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
1500
1501	if (RT_SUCCESS(rc))
1502	{
1503	rc = RTCritSectDelete(&pAIO->CritSect);
1504	AssertRC(rc);
1505
1506	rc = RTSemEventDestroy(pAIO->Event);
1507	AssertRC(rc);
1508
1509	pAIO->fStarted = false;
1510	pAIO->fShutdown = false;
1511	pAIO->fEnabled = false;
1512	}
1513
1514	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamR3->u8SD, rc));
1515	return rc;
1516	}
1517
1518	/**
1519	* Locks the async I/O thread of a specific AC'97 audio stream.
1520	*
1521	* @param pStreamCC AC'97 stream to lock async I/O thread for.
1522	*/
1523	static void ichac97R3StreamAsyncIOLock(PAC97STREAMR3 pStreamCC)
1524	{
1525	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1526
1527	if (!ASMAtomicReadBool(&pAIO->fStarted))
1528	return;
1529
1530	int rc2 = RTCritSectEnter(&pAIO->CritSect);
1531	AssertRC(rc2);
1532	}
1533
1534	/**
1535	* Unlocks the async I/O thread of a specific AC'97 audio stream.
1536	*
1537	* @param pStreamCC AC'97 stream to unlock async I/O thread for.
1538	*/
1539	static void ichac97R3StreamAsyncIOUnlock(PAC97STREAMR3 pStreamCC)
1540	{
1541	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1542
1543	if (!ASMAtomicReadBool(&pAIO->fStarted))
1544	return;
1545
1546	int rc2 = RTCritSectLeave(&pAIO->CritSect);
1547	AssertRC(rc2);
1548	}
1549
1550	#if 0 /* Unused */
1551	/**
1552	* Enables (resumes) or disables (pauses) the async I/O thread.
1553	*
1554	* @param pStream AC'97 stream to enable/disable async I/O thread for.
1555	* @param fEnable Whether to enable or disable the I/O thread.
1556	*
1557	* @remarks Does not do locking.
1558	*/
1559	static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable)
1560	{
1561	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1562	ASMAtomicXchgBool(&pAIO->fEnabled, fEnable);
1563	}
1564	#endif
1565	# endif /* VBOX_WITH_AUDIO_AC97_ASYNC_IO */
1566
1567	# ifdef LOG_ENABLED
1568	static void ichac97R3BDLEDumpAll(PPDMDEVINS pDevIns, uint64_t u64BDLBase, uint16_t cBDLE)
1569	{
1570	LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
1571	if (!u64BDLBase)
1572	return;
1573
1574	uint32_t cbBDLE = 0;
1575	for (uint16_t i = 0; i < cBDLE; i++)
1576	{
1577	AC97BDLE BDLE;
1578	PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase + i * sizeof(AC97BDLE), &BDLE, sizeof(AC97BDLE));
1579
1580	# ifndef RT_LITTLE_ENDIAN
1581	# error "Please adapt the code (audio buffers are little endian)!"
1582	# else
1583	BDLE.addr = RT_H2LE_U32(BDLE.addr & ~3);
1584	BDLE.ctl_len = RT_H2LE_U32(BDLE.ctl_len);
1585	#endif
1586	LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32 [%RU32 bytes], bup:%RTbool, ioc:%RTbool)\n",
1587	i, BDLE.addr,
1588	BDLE.ctl_len & AC97_BD_LEN_MASK,
1589	(BDLE.ctl_len & AC97_BD_LEN_MASK) << 1, /** @todo r=andy Assumes 16bit samples. */
1590	RT_BOOL(BDLE.ctl_len & AC97_BD_BUP),
1591	RT_BOOL(BDLE.ctl_len & AC97_BD_IOC)));
1592
1593	cbBDLE += (BDLE.ctl_len & AC97_BD_LEN_MASK) << 1; /** @todo r=andy Ditto. */
1594	}
1595
1596	LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
1597	}
1598	# endif /* LOG_ENABLED */
1599
1600	/**
1601	* Updates an AC'97 stream by doing its required data transfers.
1602	* The host sink(s) set the overall pace.
1603	*
1604	* This routine is called by both, the synchronous and the asynchronous
1605	* (VBOX_WITH_AUDIO_AC97_ASYNC_IO), implementations.
1606	*
1607	* When running synchronously, the device DMA transfers and the mixer sink
1608	* processing is within the device timer.
1609	*
1610	* When running asynchronously, only the device DMA transfers are done in the
1611	* device timer, whereas the mixer sink processing then is done in the stream's
1612	* own async I/O thread. This thread also will call this function
1613	* (with fInTimer set to @c false).
1614	*
1615	* @param pDevIns The device instance.
1616	* @param pThis The shared AC'97 state.
1617	* @param pThisCC The ring-3 AC'97 state.
1618	* @param pStream The AC'97 stream to update (shared).
1619	* @param pStreamCC The AC'97 stream to update (ring-3).
1620	* @param fInTimer Whether to this function was called from the timer
1621	* context or an asynchronous I/O stream thread (if supported).
1622	*/
1623	static void ichac97R3StreamUpdate(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
1624	PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fInTimer)
1625	{
1626	RT_NOREF(fInTimer);
1627
1628	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
1629	AssertPtr(pSink);
1630
1631	if (!AudioMixerSinkIsActive(pSink)) /* No sink available? Bail out. */
1632	return;
1633
1634	int rc2;
1635
1636	if (pStreamCC->State.Cfg.enmDir == PDMAUDIODIR_OUT) /* Output (SDO). */
1637	{
1638	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1639	if (fInTimer)
1640	# endif
1641	{
1642	const uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1643	if (cbStreamFree)
1644	{
1645	Log3Func(("[SD%RU8] PICB=%zu (%RU64ms), cbFree=%zu (%RU64ms), cbTransferChunk=%zu (%RU64ms)\n",
1646	pStream->u8SD,
1647	(pStream->Regs.picb << 1), DrvAudioHlpBytesToMilli((pStream->Regs.picb << 1), &pStreamCC->State.Cfg.Props),
1648	cbStreamFree, DrvAudioHlpBytesToMilli(cbStreamFree, &pStreamCC->State.Cfg.Props),
1649	pStreamCC->State.cbTransferChunk, DrvAudioHlpBytesToMilli(pStreamCC->State.cbTransferChunk, &pStreamCC->State.Cfg.Props)));
1650
1651	/* Do the DMA transfer. */
1652	rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC,
1653	RT_MIN(pStreamCC->State.cbTransferChunk, cbStreamFree));
1654	AssertRC(rc2);
1655
1656	pStreamCC->State.tsLastUpdateNs = RTTimeNanoTS();
1657	}
1658	}
1659
1660	Log3Func(("[SD%RU8] fInTimer=%RTbool\n", pStream->u8SD, fInTimer));
1661
1662	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1663	rc2 = ichac97R3StreamAsyncIONotify(pStreamCC);
1664	AssertRC(rc2);
1665	# endif
1666
1667	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1668	if (!fInTimer) /* In async I/O thread */
1669	{
1670	# endif
1671	const uint32_t cbSinkWritable = AudioMixerSinkGetWritable(pSink);
1672	const uint32_t cbStreamReadable = ichac97R3StreamGetUsed(pStreamCC);
1673	const uint32_t cbToReadFromStream = RT_MIN(cbStreamReadable, cbSinkWritable);
1674
1675	Log3Func(("[SD%RU8] cbSinkWritable=%RU32, cbStreamReadable=%RU32\n", pStream->u8SD, cbSinkWritable, cbStreamReadable));
1676
1677	if (cbToReadFromStream)
1678	{
1679	/* Read (guest output) data and write it to the stream's sink. */
1680	rc2 = ichac97R3StreamRead(pStreamCC, pSink, cbToReadFromStream, NULL /* pcbRead */);
1681	AssertRC(rc2);
1682	}
1683	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1684	}
1685	#endif
1686	/* When running synchronously, update the associated sink here.
1687	* Otherwise this will be done in the async I/O thread. */
1688	rc2 = AudioMixerSinkUpdate(pSink);
1689	AssertRC(rc2);
1690	}
1691	else /* Input (SDI). */
1692	{
1693	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1694	if (!fInTimer)
1695	{
1696	# endif
1697	rc2 = AudioMixerSinkUpdate(pSink);
1698	AssertRC(rc2);
1699
1700	/* Is the sink ready to be read (host input data) from? If so, by how much? */
1701	uint32_t cbSinkReadable = AudioMixerSinkGetReadable(pSink);
1702
1703	/* How much (guest input) data is available for writing at the moment for the AC'97 stream? */
1704	uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1705
1706	Log3Func(("[SD%RU8] cbSinkReadable=%RU32, cbStreamFree=%RU32\n", pStream->u8SD, cbSinkReadable, cbStreamFree));
1707
1708	/* Do not read more than the sink can provide at the moment.
1709	* The host sets the overall pace. */
1710	if (cbSinkReadable > cbStreamFree)
1711	cbSinkReadable = cbStreamFree;
1712
1713	if (cbSinkReadable)
1714	{
1715	/* Write (guest input) data to the stream which was read from stream's sink before. */
1716	rc2 = ichac97R3StreamWrite(pStreamCC, pSink, cbSinkReadable, NULL /* pcbWritten */);
1717	AssertRC(rc2);
1718	}
1719	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1720	}
1721	else /* fInTimer */
1722	{
1723	# endif
1724
1725	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1726	const uint64_t tsNowNs = RTTimeNanoTS();
1727	if (tsNowNs - pStreamCC->State.tsLastUpdateNs >= pStreamCC->State.Cfg.Device.cMsSchedulingHint * RT_NS_1MS)
1728	{
1729	rc2 = ichac97R3StreamAsyncIONotify(pStreamCC);
1730	AssertRC(rc2);
1731
1732	pStreamCC->State.tsLastUpdateNs = tsNowNs;
1733	}
1734	# endif
1735
1736	const uint32_t cbStreamUsed = ichac97R3StreamGetUsed(pStreamCC);
1737	if (cbStreamUsed)
1738	{
1739	/* When running synchronously, do the DMA data transfers here.
1740	* Otherwise this will be done in the stream's async I/O thread. */
1741	rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC, cbStreamUsed);
1742	AssertRC(rc2);
1743	}
1744	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1745	}
1746	# endif
1747	}
1748	}
1749
1750	#endif /* IN_RING3 */
1751
1752	/**
1753	* Sets a AC'97 mixer control to a specific value.
1754	*
1755	* @returns IPRT status code.
1756	* @param pThis The shared AC'97 state.
1757	* @param uMixerIdx Mixer control to set value for.
1758	* @param uVal Value to set.
1759	*/
1760	static void ichac97MixerSet(PAC97STATE pThis, uint8_t uMixerIdx, uint16_t uVal)
1761	{
1762	AssertMsgReturnVoid(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1763	("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)));
1764
1765	LogRel2(("AC97: Setting mixer index #%RU8 to %RU16 (%RU8 %RU8)\n",
1766	uMixerIdx, uVal, RT_HI_U8(uVal), RT_LO_U8(uVal)));
1767
1768	pThis->mixer_data[uMixerIdx + 0] = RT_LO_U8(uVal);
1769	pThis->mixer_data[uMixerIdx + 1] = RT_HI_U8(uVal);
1770	}
1771
1772	/**
1773	* Gets a value from a specific AC'97 mixer control.
1774	*
1775	* @returns Retrieved mixer control value.
1776	* @param pThis The shared AC'97 state.
1777	* @param uMixerIdx Mixer control to get value for.
1778	*/
1779	static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t uMixerIdx)
1780	{
1781	AssertMsgReturn(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1782	("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)),
1783	UINT16_MAX);
1784	return RT_MAKE_U16(pThis->mixer_data[uMixerIdx + 0], pThis->mixer_data[uMixerIdx + 1]);
1785	}
1786
1787	#ifdef IN_RING3
1788
1789	/**
1790	* Retrieves a specific driver stream of a AC'97 driver.
1791	*
1792	* @returns Pointer to driver stream if found, or NULL if not found.
1793	* @param pDrv Driver to retrieve driver stream for.
1794	* @param enmDir Stream direction to retrieve.
1795	* @param dstSrc Stream destination / source to retrieve.
1796	*/
1797	static PAC97DRIVERSTREAM ichac97R3MixerGetDrvStream(PAC97DRIVER pDrv, PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc)
1798	{
1799	PAC97DRIVERSTREAM pDrvStream = NULL;
1800
1801	if (enmDir == PDMAUDIODIR_IN)
1802	{
1803	LogFunc(("enmRecSource=%d\n", dstSrc.enmSrc));
1804
1805	switch (dstSrc.enmSrc)
1806	{
1807	case PDMAUDIORECSRC_LINE:
1808	pDrvStream = &pDrv->LineIn;
1809	break;
1810	case PDMAUDIORECSRC_MIC:
1811	pDrvStream = &pDrv->MicIn;
1812	break;
1813	default:
1814	AssertFailed();
1815	break;
1816	}
1817	}
1818	else if (enmDir == PDMAUDIODIR_OUT)
1819	{
1820	LogFunc(("enmPlaybackDest=%d\n", dstSrc.enmDst));
1821
1822	switch (dstSrc.enmDst)
1823	{
1824	case PDMAUDIOPLAYBACKDST_FRONT:
1825	pDrvStream = &pDrv->Out;
1826	break;
1827	default:
1828	AssertFailed();
1829	break;
1830	}
1831	}
1832	else
1833	AssertFailed();
1834
1835	return pDrvStream;
1836	}
1837
1838	/**
1839	* Adds a driver stream to a specific mixer sink.
1840	*
1841	* @returns IPRT status code.
1842	* @param pMixSink Mixer sink to add driver stream to.
1843	* @param pCfg Stream configuration to use.
1844	* @param pDrv Driver stream to add.
1845	*/
1846	static int ichac97R3MixerAddDrvStream(PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PAC97DRIVER pDrv)
1847	{
1848	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1849
1850	PPDMAUDIOSTREAMCFG pStreamCfg = DrvAudioHlpStreamCfgDup(pCfg);
1851	if (!pStreamCfg)
1852	return VERR_NO_MEMORY;
1853
1854	if (!RTStrPrintf(pStreamCfg->szName, sizeof(pStreamCfg->szName), "%s", pCfg->szName))
1855	{
1856	DrvAudioHlpStreamCfgFree(pStreamCfg);
1857	return VERR_BUFFER_OVERFLOW;
1858	}
1859
1860	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
1861
1862	int rc;
1863
1864	PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, pStreamCfg->enmDir, pStreamCfg->u);
1865	if (pDrvStream)
1866	{
1867	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
1868
1869	PAUDMIXSTREAM pMixStrm;
1870	rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
1871	LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1872	if (RT_SUCCESS(rc))
1873	{
1874	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
1875	LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1876	if (RT_SUCCESS(rc))
1877	{
1878	/* If this is an input stream, always set the latest (added) stream
1879	* as the recording source. */
1880	/** @todo Make the recording source dynamic (CFGM?). */
1881	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
1882	{
1883	PDMAUDIOBACKENDCFG Cfg;
1884	rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
1885	if (RT_SUCCESS(rc))
1886	{
1887	if (Cfg.cMaxStreamsIn) /* At least one input source available? */
1888	{
1889	rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
1890	LogFlowFunc(("LUN#%RU8: Recording source for '%s' -> '%s', rc=%Rrc\n",
1891	pDrv->uLUN, pStreamCfg->szName, Cfg.szName, rc));
1892
1893	if (RT_SUCCESS(rc))
1894	LogRel2(("AC97: Set recording source for '%s' to '%s'\n", pStreamCfg->szName, Cfg.szName));
1895	}
1896	else
1897	LogRel(("AC97: Backend '%s' currently is not offering any recording source for '%s'\n",
1898	Cfg.szName, pStreamCfg->szName));
1899	}
1900	else if (RT_FAILURE(rc))
1901	LogFunc(("LUN#%RU8: Unable to retrieve backend configuratio for '%s', rc=%Rrc\n",
1902	pDrv->uLUN, pStreamCfg->szName, rc));
1903	}
1904	/** @todo r=bird: see below. */
1905	if (RT_FAILURE(rc))
1906	AudioMixerSinkRemoveStream(pMixSink, pMixStrm);
1907	}
1908	/** @todo r=bird: I've added this destroy stuff here, because if it looks as if
1909	* you just drop the stream if the AudioMixerSinkAddStream fails for some
1910	* reason. This is definitely true if AudioMixerSinkSetRecordingSource fails
1911	* above, because it leads to duplicate statistics when starting XP with ICH97
1912	* and VRDP enabled. Looks like the VRDP line-in fails with
1913	* VERR_AUDIO_STREAM_NOT_READY when configured for 8000HZ, then it asserts in
1914	* STAM when 48000Hz is configured right afterwards. */
1915	if (RT_FAILURE(rc))
1916	AudioMixerStreamDestroy(pMixStrm);
1917	}
1918
1919	if (RT_SUCCESS(rc))
1920	pDrvStream->pMixStrm = pMixStrm;
1921	}
1922	else
1923	rc = VERR_INVALID_PARAMETER;
1924
1925	DrvAudioHlpStreamCfgFree(pStreamCfg);
1926
1927	LogFlowFuncLeaveRC(rc);
1928	return rc;
1929	}
1930
1931	/**
1932	* Adds all current driver streams to a specific mixer sink.
1933	*
1934	* @returns IPRT status code.
1935	* @param pThisCC The ring-3 AC'97 state.
1936	* @param pMixSink Mixer sink to add stream to.
1937	* @param pCfg Stream configuration to use.
1938	*/
1939	static int ichac97R3MixerAddDrvStreams(PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
1940	{
1941	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1942
1943	if (!DrvAudioHlpStreamCfgIsValid(pCfg))
1944	return VERR_INVALID_PARAMETER;
1945
1946	int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
1947	if (RT_FAILURE(rc))
1948	return rc;
1949
1950	PAC97DRIVER pDrv;
1951	RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
1952	{
1953	int rc2 = ichac97R3MixerAddDrvStream(pMixSink, pCfg, pDrv);
1954	if (RT_FAILURE(rc2))
1955	LogFunc(("Attaching stream failed with %Rrc\n", rc2));
1956
1957	/* Do not pass failure to rc here, as there might be drivers which aren't
1958	* configured / ready yet. */
1959	}
1960
1961	LogFlowFuncLeaveRC(rc);
1962	return rc;
1963	}
1964
1965	/**
1966	* Adds a specific AC'97 driver to the driver chain.
1967	*
1968	* @return IPRT status code.
1969	* @param pThisCC The ring-3 AC'97 device state.
1970	* @param pDrv The AC'97 driver to add.
1971	*/
1972	static int ichac97R3MixerAddDrv(PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
1973	{
1974	int rc = VINF_SUCCESS;
1975
1976	if (DrvAudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg))
1977	rc = ichac97R3MixerAddDrvStream(pThisCC->pSinkLineIn, &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg, pDrv);
1978
1979	if (DrvAudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg))
1980	{
1981	int rc2 = ichac97R3MixerAddDrvStream(pThisCC->pSinkOut, &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg, pDrv);
1982	if (RT_SUCCESS(rc))
1983	rc = rc2;
1984	}
1985
1986	if (DrvAudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg))
1987	{
1988	int rc2 = ichac97R3MixerAddDrvStream(pThisCC->pSinkMicIn, &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg, pDrv);
1989	if (RT_SUCCESS(rc))
1990	rc = rc2;
1991	}
1992
1993	return rc;
1994	}
1995
1996	/**
1997	* Removes a specific AC'97 driver from the driver chain and destroys its
1998	* associated streams.
1999	*
2000	* @param pThisCC The ring-3 AC'97 device state.
2001	* @param pDrv AC'97 driver to remove.
2002	*/
2003	static void ichac97R3MixerRemoveDrv(PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
2004	{
2005	if (pDrv->MicIn.pMixStrm)
2006	{
2007	if (AudioMixerSinkGetRecordingSource(pThisCC->pSinkMicIn) == pDrv->MicIn.pMixStrm)
2008	AudioMixerSinkSetRecordingSource(pThisCC->pSinkMicIn, NULL);
2009
2010	AudioMixerSinkRemoveStream(pThisCC->pSinkMicIn, pDrv->MicIn.pMixStrm);
2011	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm);
2012	pDrv->MicIn.pMixStrm = NULL;
2013	}
2014
2015	if (pDrv->LineIn.pMixStrm)
2016	{
2017	if (AudioMixerSinkGetRecordingSource(pThisCC->pSinkLineIn) == pDrv->LineIn.pMixStrm)
2018	AudioMixerSinkSetRecordingSource(pThisCC->pSinkLineIn, NULL);
2019
2020	AudioMixerSinkRemoveStream(pThisCC->pSinkLineIn, pDrv->LineIn.pMixStrm);
2021	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm);
2022	pDrv->LineIn.pMixStrm = NULL;
2023	}
2024
2025	if (pDrv->Out.pMixStrm)
2026	{
2027	AudioMixerSinkRemoveStream(pThisCC->pSinkOut, pDrv->Out.pMixStrm);
2028	AudioMixerStreamDestroy(pDrv->Out.pMixStrm);
2029	pDrv->Out.pMixStrm = NULL;
2030	}
2031
2032	RTListNodeRemove(&pDrv->Node);
2033	}
2034
2035	/**
2036	* Removes a driver stream from a specific mixer sink.
2037	*
2038	* @param pMixSink Mixer sink to remove audio streams from.
2039	* @param enmDir Stream direction to remove.
2040	* @param dstSrc Stream destination / source to remove.
2041	* @param pDrv Driver stream to remove.
2042	*/
2043	static void ichac97R3MixerRemoveDrvStream(PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc, PAC97DRIVER pDrv)
2044	{
2045	PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, enmDir, dstSrc);
2046	if (pDrvStream)
2047	{
2048	if (pDrvStream->pMixStrm)
2049	{
2050	AudioMixerSinkRemoveStream(pMixSink, pDrvStream->pMixStrm);
2051
2052	AudioMixerStreamDestroy(pDrvStream->pMixStrm);
2053	pDrvStream->pMixStrm = NULL;
2054	}
2055	}
2056	}
2057
2058	/**
2059	* Removes all driver streams from a specific mixer sink.
2060	*
2061	* @param pThisCC The ring-3 AC'97 state.
2062	* @param pMixSink Mixer sink to remove audio streams from.
2063	* @param enmDir Stream direction to remove.
2064	* @param dstSrc Stream destination / source to remove.
2065	*/
2066	static void ichac97R3MixerRemoveDrvStreams(PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
2067	PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc)
2068	{
2069	AssertPtrReturnVoid(pMixSink);
2070
2071	PAC97DRIVER pDrv;
2072	RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
2073	{
2074	ichac97R3MixerRemoveDrvStream(pMixSink, enmDir, dstSrc, pDrv);
2075	}
2076	}
2077
2078	/**
2079	* Calculates and returns the ticks for a specified amount of bytes.
2080	*
2081	* @returns Calculated ticks
2082	* @param pDevIns The device instance.
2083	* @param pStream AC'97 stream to calculate ticks for (shared).
2084	* @param pStreamCC AC'97 stream to calculate ticks for (ring-3).
2085	* @param cbBytes Bytes to calculate ticks for.
2086	*/
2087	static uint64_t ichac97R3StreamTransferCalcNext(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint32_t cbBytes)
2088	{
2089	if (!cbBytes)
2090	return 0;
2091
2092	const uint64_t usBytes = DrvAudioHlpBytesToMicro(cbBytes, &pStreamCC->State.Cfg.Props);
2093	const uint64_t cTransferTicks = PDMDevHlpTimerFromMicro(pDevIns, pStream->hTimer, usBytes);
2094
2095	Log3Func(("[SD%RU8] Timer %uHz, cbBytes=%RU32 -> usBytes=%RU64, cTransferTicks=%RU64\n",
2096	pStream->u8SD, pStreamCC->State.uTimerHz, cbBytes, usBytes, cTransferTicks));
2097
2098	return cTransferTicks;
2099	}
2100
2101	/**
2102	* Updates the next transfer based on a specific amount of bytes.
2103	*
2104	* @param pDevIns The device instance.
2105	* @param pStream The AC'97 stream to update (shared).
2106	* @param pStreamCC The AC'97 stream to update (ring-3).
2107	* @param cbBytes Bytes to update next transfer for.
2108	*/
2109	static void ichac97R3StreamTransferUpdate(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint32_t cbBytes)
2110	{
2111	if (!cbBytes)
2112	return;
2113
2114	/* Calculate the bytes we need to transfer to / from the stream's DMA per iteration.
2115	* This is bound to the device's Hz rate and thus to the (virtual) timing the device expects. */
2116	pStreamCC->State.cbTransferChunk = cbBytes;
2117
2118	/* Update the transfer ticks. */
2119	pStreamCC->State.cTransferTicks = ichac97R3StreamTransferCalcNext(pDevIns, pStream, pStreamCC,
2120	pStreamCC->State.cbTransferChunk);
2121	Assert(pStreamCC->State.cTransferTicks); /* Paranoia. */
2122	}
2123
2124	/**
2125	* Opens an AC'97 stream with its current mixer settings.
2126	*
2127	* This will open an AC'97 stream with 2 (stereo) channels, 16-bit samples and
2128	* the last set sample rate in the AC'97 mixer for this stream.
2129	*
2130	* @returns IPRT status code.
2131	* @param pThis The shared AC'97 device state (shared).
2132	* @param pThisCC The shared AC'97 device state (ring-3).
2133	* @param pStream The AC'97 stream to open (shared).
2134	* @param pStreamCC The AC'97 stream to open (ring-3).
2135	* @param fForce Whether to force re-opening the stream or not.
2136	* Otherwise re-opening only will happen if the PCM properties have changed.
2137	*/
2138	static int ichac97R3StreamOpen(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2139	{
2140	PDMAUDIOSTREAMCFG Cfg;
2141	RT_ZERO(Cfg);
2142	Cfg.Props.cChannels = 2;
2143	Cfg.Props.cbSample = 2 /* 16-bit */;
2144	Cfg.Props.fSigned = true;
2145	Cfg.Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(Cfg.Props.cbSample, Cfg.Props.cChannels);
2146
2147	int rc = VINF_SUCCESS;
2148	PAUDMIXSINK pMixSink;
2149	switch (pStream->u8SD)
2150	{
2151	case AC97SOUNDSOURCE_PI_INDEX:
2152	{
2153	Cfg.Props.uHz = ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate);
2154	Cfg.enmDir = PDMAUDIODIR_IN;
2155	Cfg.u.enmSrc = PDMAUDIORECSRC_LINE;
2156	Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2157	RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Line-In");
2158
2159	pMixSink = pThisCC->pSinkLineIn;
2160	break;
2161	}
2162
2163	case AC97SOUNDSOURCE_MC_INDEX:
2164	{
2165	Cfg.Props.uHz = ichac97MixerGet(pThis, AC97_MIC_ADC_Rate);
2166	Cfg.enmDir = PDMAUDIODIR_IN;
2167	Cfg.u.enmSrc = PDMAUDIORECSRC_MIC;
2168	Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2169	RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Mic-In");
2170
2171	pMixSink = pThisCC->pSinkMicIn;
2172	break;
2173	}
2174
2175	case AC97SOUNDSOURCE_PO_INDEX:
2176	{
2177	Cfg.Props.uHz = ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate);
2178	Cfg.enmDir = PDMAUDIODIR_OUT;
2179	Cfg.u.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
2180	Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2181	RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Output");
2182
2183	pMixSink = pThisCC->pSinkOut;
2184	break;
2185	}
2186
2187	default:
2188	rc = VERR_NOT_SUPPORTED;
2189	pMixSink = NULL;
2190	break;
2191	}
2192
2193	if (RT_SUCCESS(rc))
2194	{
2195	/* Only (re-)create the stream (and driver chain) if we really have to.
2196	* Otherwise avoid this and just reuse it, as this costs performance. */
2197	if ( !DrvAudioHlpPCMPropsAreEqual(&Cfg.Props, &pStreamCC->State.Cfg.Props)
2198	\|\| fForce)
2199	{
2200	LogRel2(("AC97: (Re-)Opening stream '%s' (%RU32Hz, %RU8 channels, %s%RU8)\n",
2201	Cfg.szName, Cfg.Props.uHz, Cfg.Props.cChannels, Cfg.Props.fSigned ? "S" : "U", Cfg.Props.cbSample * 8));
2202
2203	LogFlowFunc(("[SD%RU8] uHz=%RU32\n", pStream->u8SD, Cfg.Props.uHz));
2204
2205	if (Cfg.Props.uHz)
2206	{
2207	Assert(Cfg.enmDir != PDMAUDIODIR_UNKNOWN);
2208
2209	/*
2210	* Set the stream's timer Hz rate, based on the PCM properties Hz rate.
2211	*/
2212	if (pThis->uTimerHz == AC97_TIMER_HZ_DEFAULT) /* Make sure that we don't have any custom Hz rate set we want to enforce */
2213	{
2214	if (Cfg.Props.uHz > 44100) /* E.g. 48000 Hz. */
2215	pStreamCC->State.uTimerHz = 200;
2216	else /* Just take the global Hz rate otherwise. */
2217	pStreamCC->State.uTimerHz = pThis->uTimerHz;
2218	}
2219	else
2220	pStreamCC->State.uTimerHz = pThis->uTimerHz;
2221
2222	/* Set scheduling hint (if available). */
2223	if (pStreamCC->State.uTimerHz)
2224	Cfg.Device.cMsSchedulingHint = 1000 /* ms */ / pStreamCC->State.uTimerHz;
2225
2226	if (pStreamCC->State.pCircBuf)
2227	{
2228	RTCircBufDestroy(pStreamCC->State.pCircBuf);
2229	pStreamCC->State.pCircBuf = NULL;
2230	}
2231
2232	rc = RTCircBufCreate(&pStreamCC->State.pCircBuf, DrvAudioHlpMilliToBytes(100 /* ms /, &Cfg.Props)); /* @todo Make this configurable. */
2233	if (RT_SUCCESS(rc))
2234	{
2235	ichac97R3MixerRemoveDrvStreams(pThisCC, pMixSink, Cfg.enmDir, Cfg.u);
2236
2237	rc = ichac97R3MixerAddDrvStreams(pThisCC, pMixSink, &Cfg);
2238	if (RT_SUCCESS(rc))
2239	rc = DrvAudioHlpStreamCfgCopy(&pStreamCC->State.Cfg, &Cfg);
2240	}
2241	}
2242	}
2243	else
2244	LogFlowFunc(("[SD%RU8] Skipping (re-)creation\n", pStream->u8SD));
2245	}
2246
2247	LogFlowFunc(("[SD%RU8] rc=%Rrc\n", pStream->u8SD, rc));
2248	return rc;
2249	}
2250
2251	/**
2252	* Closes an AC'97 stream.
2253	*
2254	* @returns IPRT status code.
2255	* @param pStream The AC'97 stream to close (shared).
2256	*/
2257	static int ichac97R3StreamClose(PAC97STREAM pStream)
2258	{
2259	RT_NOREF(pStream);
2260	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2261	return VINF_SUCCESS;
2262	}
2263
2264	/**
2265	* Re-opens (that is, closes and opens again) an AC'97 stream on the backend
2266	* side with the current AC'97 mixer settings for this stream.
2267	*
2268	* @returns IPRT status code.
2269	* @param pThis The shared AC'97 device state.
2270	* @param pThisCC The ring-3 AC'97 device state.
2271	* @param pStream The AC'97 stream to re-open (shared).
2272	* @param pStreamCC The AC'97 stream to re-open (ring-3).
2273	* @param fForce Whether to force re-opening the stream or not.
2274	* Otherwise re-opening only will happen if the PCM properties have changed.
2275	*/
2276	static int ichac97R3StreamReOpen(PAC97STATE pThis, PAC97STATER3 pThisCC,
2277	PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2278	{
2279	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2280	Assert(pStream->u8SD == pStreamCC->u8SD);
2281	Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2282	Assert(pStreamCC - &pThisCC->aStreams[0] == pStream->u8SD);
2283
2284	int rc = ichac97R3StreamClose(pStream);
2285	if (RT_SUCCESS(rc))
2286	rc = ichac97R3StreamOpen(pThis, pThisCC, pStream, pStreamCC, fForce);
2287
2288	return rc;
2289	}
2290
2291	/**
2292	* Locks an AC'97 stream for serialized access.
2293	*
2294	* @returns IPRT status code.
2295	* @param pStreamCC The AC'97 stream to lock (ring-3).
2296	*/
2297	static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC)
2298	{
2299	int rc2 = RTCritSectEnter(&pStreamCC->State.CritSect);
2300	AssertRC(rc2);
2301	}
2302
2303	/**
2304	* Unlocks a formerly locked AC'97 stream.
2305	*
2306	* @returns IPRT status code.
2307	* @param pStreamCC The AC'97 stream to unlock (ring-3).
2308	*/
2309	static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC)
2310	{
2311	int rc2 = RTCritSectLeave(&pStreamCC->State.CritSect);
2312	AssertRC(rc2);
2313	}
2314
2315	/**
2316	* Retrieves the available size of (buffered) audio data (in bytes) of a given AC'97 stream.
2317	*
2318	* @returns Available data (in bytes).
2319	* @param pStreamCC The AC'97 stream to retrieve size for (ring-3).
2320	*/
2321	static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC)
2322	{
2323	if (!pStreamCC->State.pCircBuf)
2324	return 0;
2325
2326	return (uint32_t)RTCircBufUsed(pStreamCC->State.pCircBuf);
2327	}
2328
2329	/**
2330	* Retrieves the free size of audio data (in bytes) of a given AC'97 stream.
2331	*
2332	* @returns Free data (in bytes).
2333	* @param pStreamCC AC'97 stream to retrieve size for (ring-3).
2334	*/
2335	static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC)
2336	{
2337	if (!pStreamCC->State.pCircBuf)
2338	return 0;
2339
2340	return (uint32_t)RTCircBufFree(pStreamCC->State.pCircBuf);
2341	}
2342
2343	/**
2344	* Sets the volume of a specific AC'97 mixer control.
2345	*
2346	* This currently only supports attenuation -- gain support is currently not implemented.
2347	*
2348	* @returns IPRT status code.
2349	* @param pThis The shared AC'97 state.
2350	* @param pThisCC The ring-3 AC'97 state.
2351	* @param index AC'97 mixer index to set volume for.
2352	* @param enmMixerCtl Corresponding audio mixer sink.
2353	* @param uVal Volume value to set.
2354	*/
2355	static int ichac97R3MixerSetVolume(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2356	{
2357	/*
2358	* From AC'97 SoundMax Codec AD1981A/AD1981B:
2359	* "Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the
2360	* D5 or D13 bits are set to 1, their respective lower five volume bits are automatically
2361	* set to 1 by the Codec logic. On readback, all lower 5 bits will read ones whenever
2362	* these bits are set to 1."
2363	*
2364	* Linux ALSA depends on this behavior to detect that only 5 bits are used for volume
2365	* control and the optional 6th bit is not used. Note that this logic only applies to the
2366	* master volume controls.
2367	*/
2368	if (index == AC97_Master_Volume_Mute \|\| index == AC97_Headphone_Volume_Mute \|\| index == AC97_Master_Volume_Mono_Mute)
2369	{
2370	if (uVal & RT_BIT(5)) /* D5 bit set? */
2371	uVal \|= RT_BIT(4) \| RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1) \| RT_BIT(0);
2372	if (uVal & RT_BIT(13)) /* D13 bit set? */
2373	uVal \|= RT_BIT(12) \| RT_BIT(11) \| RT_BIT(10) \| RT_BIT(9) \| RT_BIT(8);
2374	}
2375
2376	const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2377	uint8_t uCtlAttLeft = (uVal >> 8) & AC97_BARS_VOL_MASK;
2378	uint8_t uCtlAttRight = uVal & AC97_BARS_VOL_MASK;
2379
2380	/* For the master and headphone volume, 0 corresponds to 0dB attenuation. For the other
2381	* volume controls, 0 means 12dB gain and 8 means unity gain.
2382	*/
2383	if (index != AC97_Master_Volume_Mute && index != AC97_Headphone_Volume_Mute)
2384	{
2385	# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2386	/* NB: Currently there is no gain support, only attenuation. */
2387	uCtlAttLeft = uCtlAttLeft < 8 ? 0 : uCtlAttLeft - 8;
2388	uCtlAttRight = uCtlAttRight < 8 ? 0 : uCtlAttRight - 8;
2389	# endif
2390	}
2391	Assert(uCtlAttLeft <= 255 / AC97_DB_FACTOR);
2392	Assert(uCtlAttRight <= 255 / AC97_DB_FACTOR);
2393
2394	LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2395	LogFunc(("uCtlAttLeft=%RU8, uCtlAttRight=%RU8 ", uCtlAttLeft, uCtlAttRight));
2396
2397	/*
2398	* For AC'97 volume controls, each additional step means -1.5dB attenuation with
2399	* zero being maximum. In contrast, we're internally using 255 (PDMAUDIO_VOLUME_MAX)
2400	* steps, each -0.375dB, where 0 corresponds to -96dB and 255 corresponds to 0dB.
2401	*/
2402	uint8_t lVol = PDMAUDIO_VOLUME_MAX - uCtlAttLeft * AC97_DB_FACTOR;
2403	uint8_t rVol = PDMAUDIO_VOLUME_MAX - uCtlAttRight * AC97_DB_FACTOR;
2404
2405	Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2406
2407	int rc = VINF_SUCCESS;
2408
2409	if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2410	{
2411	PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2412	PAUDMIXSINK pSink = NULL;
2413
2414	switch (enmMixerCtl)
2415	{
2416	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2417	rc = AudioMixerSetMasterVolume(pThisCC->pMixer, &Vol);
2418	break;
2419
2420	case PDMAUDIOMIXERCTL_FRONT:
2421	pSink = pThisCC->pSinkOut;
2422	break;
2423
2424	case PDMAUDIOMIXERCTL_MIC_IN:
2425	case PDMAUDIOMIXERCTL_LINE_IN:
2426	/* These are recognized but do nothing. */
2427	break;
2428
2429	default:
2430	AssertFailed();
2431	rc = VERR_NOT_SUPPORTED;
2432	break;
2433	}
2434
2435	if (pSink)
2436	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2437	}
2438
2439	ichac97MixerSet(pThis, index, uVal);
2440
2441	if (RT_FAILURE(rc))
2442	LogFlowFunc(("Failed with %Rrc\n", rc));
2443
2444	return rc;
2445	}
2446
2447	/**
2448	* Sets the gain of a specific AC'97 recording control.
2449	*
2450	* NB: gain support is currently not implemented in PDM audio.
2451	*
2452	* @returns IPRT status code.
2453	* @param pThis The shared AC'97 state.
2454	* @param pThisCC The ring-3 AC'97 state.
2455	* @param index AC'97 mixer index to set volume for.
2456	* @param enmMixerCtl Corresponding audio mixer sink.
2457	* @param uVal Volume value to set.
2458	*/
2459	static int ichac97R3MixerSetGain(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2460	{
2461	/*
2462	* For AC'97 recording controls, each additional step means +1.5dB gain with
2463	* zero being 0dB gain and 15 being +22.5dB gain.
2464	*/
2465	const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2466	uint8_t uCtlGainLeft = (uVal >> 8) & AC97_BARS_GAIN_MASK;
2467	uint8_t uCtlGainRight = uVal & AC97_BARS_GAIN_MASK;
2468
2469	Assert(uCtlGainLeft <= 255 / AC97_DB_FACTOR);
2470	Assert(uCtlGainRight <= 255 / AC97_DB_FACTOR);
2471
2472	LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2473	LogFunc(("uCtlGainLeft=%RU8, uCtlGainRight=%RU8 ", uCtlGainLeft, uCtlGainRight));
2474
2475	uint8_t lVol = PDMAUDIO_VOLUME_MAX + uCtlGainLeft * AC97_DB_FACTOR;
2476	uint8_t rVol = PDMAUDIO_VOLUME_MAX + uCtlGainRight * AC97_DB_FACTOR;
2477
2478	/* We do not currently support gain. Since AC'97 does not support attenuation
2479	* for the recording input, the best we can do is set the maximum volume.
2480	*/
2481	# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2482	/* NB: Currently there is no gain support, only attenuation. Since AC'97 does not
2483	* support attenuation for the recording inputs, the best we can do is set the
2484	* maximum volume.
2485	*/
2486	lVol = rVol = PDMAUDIO_VOLUME_MAX;
2487	# endif
2488
2489	Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2490
2491	int rc = VINF_SUCCESS;
2492
2493	if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2494	{
2495	PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2496	PAUDMIXSINK pSink = NULL;
2497
2498	switch (enmMixerCtl)
2499	{
2500	case PDMAUDIOMIXERCTL_MIC_IN:
2501	pSink = pThisCC->pSinkMicIn;
2502	break;
2503
2504	case PDMAUDIOMIXERCTL_LINE_IN:
2505	pSink = pThisCC->pSinkLineIn;
2506	break;
2507
2508	default:
2509	AssertFailed();
2510	rc = VERR_NOT_SUPPORTED;
2511	break;
2512	}
2513
2514	if (pSink) {
2515	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2516	/* There is only one AC'97 recording gain control. If line in
2517	* is changed, also update the microphone. If the optional dedicated
2518	* microphone is changed, only change that.
2519	* NB: The codecs we support do not have the dedicated microphone control.
2520	*/
2521	if ((pSink == pThisCC->pSinkLineIn) && pThisCC->pSinkMicIn)
2522	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2523	}
2524	}
2525
2526	ichac97MixerSet(pThis, index, uVal);
2527
2528	if (RT_FAILURE(rc))
2529	LogFlowFunc(("Failed with %Rrc\n", rc));
2530
2531	return rc;
2532	}
2533
2534	/**
2535	* Converts an AC'97 recording source index to a PDM audio recording source.
2536	*
2537	* @returns PDM audio recording source.
2538	* @param uIdx AC'97 index to convert.
2539	*/
2540	static PDMAUDIORECSRC ichac97R3IdxToRecSource(uint8_t uIdx)
2541	{
2542	switch (uIdx)
2543	{
2544	case AC97_REC_MIC: return PDMAUDIORECSRC_MIC;
2545	case AC97_REC_CD: return PDMAUDIORECSRC_CD;
2546	case AC97_REC_VIDEO: return PDMAUDIORECSRC_VIDEO;
2547	case AC97_REC_AUX: return PDMAUDIORECSRC_AUX;
2548	case AC97_REC_LINE_IN: return PDMAUDIORECSRC_LINE;
2549	case AC97_REC_PHONE: return PDMAUDIORECSRC_PHONE;
2550	default:
2551	break;
2552	}
2553
2554	LogFlowFunc(("Unknown record source %d, using MIC\n", uIdx));
2555	return PDMAUDIORECSRC_MIC;
2556	}
2557
2558	/**
2559	* Converts a PDM audio recording source to an AC'97 recording source index.
2560	*
2561	* @returns AC'97 recording source index.
2562	* @param enmRecSrc PDM audio recording source to convert.
2563	*/
2564	static uint8_t ichac97R3RecSourceToIdx(PDMAUDIORECSRC enmRecSrc)
2565	{
2566	switch (enmRecSrc)
2567	{
2568	case PDMAUDIORECSRC_MIC: return AC97_REC_MIC;
2569	case PDMAUDIORECSRC_CD: return AC97_REC_CD;
2570	case PDMAUDIORECSRC_VIDEO: return AC97_REC_VIDEO;
2571	case PDMAUDIORECSRC_AUX: return AC97_REC_AUX;
2572	case PDMAUDIORECSRC_LINE: return AC97_REC_LINE_IN;
2573	case PDMAUDIORECSRC_PHONE: return AC97_REC_PHONE;
2574	default:
2575	break;
2576	}
2577
2578	LogFlowFunc(("Unknown audio recording source %d using MIC\n", enmRecSrc));
2579	return AC97_REC_MIC;
2580	}
2581
2582	/**
2583	* Returns the audio direction of a specified stream descriptor.
2584	*
2585	* @return Audio direction.
2586	*/
2587	DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD)
2588	{
2589	switch (uSD)
2590	{
2591	case AC97SOUNDSOURCE_PI_INDEX: return PDMAUDIODIR_IN;
2592	case AC97SOUNDSOURCE_PO_INDEX: return PDMAUDIODIR_OUT;
2593	case AC97SOUNDSOURCE_MC_INDEX: return PDMAUDIODIR_IN;
2594	}
2595
2596	AssertFailed();
2597	return PDMAUDIODIR_UNKNOWN;
2598	}
2599
2600	#endif /* IN_RING3 */
2601
2602	#ifdef IN_RING3
2603
2604	/**
2605	* Performs an AC'97 mixer record select to switch to a different recording
2606	* source.
2607	*
2608	* @param pThis The shared AC'97 state.
2609	* @param val AC'97 recording source index to set.
2610	*/
2611	static void ichac97R3MixerRecordSelect(PAC97STATE pThis, uint32_t val)
2612	{
2613	uint8_t rs = val & AC97_REC_MASK;
2614	uint8_t ls = (val >> 8) & AC97_REC_MASK;
2615
2616	const PDMAUDIORECSRC ars = ichac97R3IdxToRecSource(rs);
2617	const PDMAUDIORECSRC als = ichac97R3IdxToRecSource(ls);
2618
2619	rs = ichac97R3RecSourceToIdx(ars);
2620	ls = ichac97R3RecSourceToIdx(als);
2621
2622	LogRel(("AC97: Record select to left=%s, right=%s\n", DrvAudioHlpRecSrcToStr(ars), DrvAudioHlpRecSrcToStr(als)));
2623
2624	ichac97MixerSet(pThis, AC97_Record_Select, rs \| (ls << 8));
2625	}
2626
2627	/**
2628	* Resets the AC'97 mixer.
2629	*
2630	* @returns IPRT status code.
2631	* @param pThis The shared AC'97 state.
2632	* @param pThisCC The ring-3 AC'97 state.
2633	*/
2634	static int ichac97R3MixerReset(PAC97STATE pThis, PAC97STATER3 pThisCC)
2635	{
2636	LogFlowFuncEnter();
2637
2638	RT_ZERO(pThis->mixer_data);
2639
2640	/* Note: Make sure to reset all registers first before bailing out on error. */
2641
2642	ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
2643	ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
2644	ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
2645
2646	ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
2647	ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
2648	ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
2649	ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
2650	ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
2651	ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
2652	ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
2653	ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
2654
2655	/* Configure Extended Audio ID (EAID) + Control & Status (EACS) registers. */
2656	const uint16_t fEAID = AC97_EAID_REV1 \| AC97_EACS_VRA \| AC97_EACS_VRM; /* Our hardware is AC'97 rev2.3 compliant. */
2657	const uint16_t fEACS = AC97_EACS_VRA \| AC97_EACS_VRM; /* Variable Rate PCM Audio (VRA) + Mic-In (VRM) capable. */
2658
2659	LogRel(("AC97: Mixer reset (EAID=0x%x, EACS=0x%x)\n", fEAID, fEACS));
2660
2661	ichac97MixerSet(pThis, AC97_Extended_Audio_ID, fEAID);
2662	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, fEACS);
2663	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2664	ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2665	ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2666	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2667	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2668
2669	if (pThis->enmCodecModel == AC97CODEC_AD1980)
2670	{
2671	/* Analog Devices 1980 (AD1980) */
2672	ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
2673	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2674	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
2675	ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
2676	}
2677	else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
2678	{
2679	/* Analog Devices 1981B (AD1981B) */
2680	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2681	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
2682	}
2683	else
2684	{
2685	/* Sigmatel 9700 (STAC9700) */
2686	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
2687	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
2688	}
2689	ichac97R3MixerRecordSelect(pThis, 0);
2690
2691	/* The default value is 8000h, which corresponds to 0 dB attenuation with mute on. */
2692	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER, 0x8000);
2693
2694	/* The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on.*/
2695	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT, 0x8808);
2696	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
2697	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8008);
2698
2699	/* The default for record controls is 0 dB gain with mute on. */
2700	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8000);
2701	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8000);
2702
2703	return VINF_SUCCESS;
2704	}
2705
2706	# if 0 /* Unused */
2707	static void ichac97R3WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
2708	{
2709	LogFlowFunc(("cbElapsed=%RU32\n", cbElapsed));
2710
2711	if (!(pThis->bup_flag & BUP_SET))
2712	{
2713	if (pThis->bup_flag & BUP_LAST)
2714	{
2715	unsigned int i;
2716	uint32_t p = (uint32_t)pThis->silence;
2717	for (i = 0; i < sizeof(pThis->silence) / 4; i++) /** @todo r=andy Assumes 16-bit samples, stereo. */
2718	*p++ = pThis->last_samp;
2719	}
2720	else
2721	RT_ZERO(pThis->silence);
2722
2723	pThis->bup_flag \|= BUP_SET;
2724	}
2725
2726	while (cbElapsed)
2727	{
2728	uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
2729	uint32_t cbWrittenToStream;
2730
2731	int rc2 = AudioMixerSinkWrite(pThisCC->pSinkOut, AUDMIXOP_COPY,
2732	pThis->silence, cbToWrite, &cbWrittenToStream);
2733	if (RT_SUCCESS(rc2))
2734	{
2735	if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2736	LogFlowFunc(("Warning: Only written %RU32 / %RU32 bytes, expect lags\n", cbWrittenToStream, cbToWrite));
2737	}
2738
2739	/* Always report all data as being written;
2740	* backends who were not able to catch up have to deal with it themselves. */
2741	Assert(cbElapsed >= cbToWrite);
2742	cbElapsed -= cbToWrite;
2743	}
2744	}
2745	# endif /* Unused */
2746
2747	/**
2748	* @callback_method_impl{FNTMTIMERDEV,
2749	* Timer callback which handles the audio data transfers on a periodic basis.}
2750	*/
2751	static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2752	{
2753	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2754	STAM_PROFILE_START(&pThis->StatTimer, a);
2755	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
2756	PAC97STREAM pStream = (PAC97STREAM)pvUser;
2757	PAC97STREAMR3 pStreamCC = &RT_SAFE_SUBSCRIPT8(pThisCC->aStreams, pStream->u8SD);
2758	RT_NOREF(pTimer);
2759
2760	Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2761	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2762	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStream->hTimer));
2763
2764	ichac97R3StreamUpdate(pDevIns, pThis, pThisCC, pStream, pStreamCC, true /* fInTimer */);
2765
2766	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
2767	if (pSink && AudioMixerSinkIsActive(pSink))
2768	{
2769	ichac97R3StreamTransferUpdate(pDevIns, pStream, pStreamCC, pStream->Regs.picb << 1); /** @todo r=andy Assumes 16-bit samples. */
2770	ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
2771	}
2772
2773	STAM_PROFILE_STOP(&pThis->StatTimer, a);
2774	}
2775
2776
2777	/**
2778	* Sets the virtual device timer to a new expiration time.
2779	*
2780	* @param pDevIns The device instance.
2781	* @param pStream AC'97 stream to set timer for.
2782	* @param cTicksToDeadline The number of ticks to the new deadline.
2783	*
2784	* @remarks This used to be more complicated a long time ago...
2785	*/
2786	DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline)
2787	{
2788	int rc = PDMDevHlpTimerSetRelative(pDevIns, pStream->hTimer, cTicksToDeadline, NULL /pu64Now/);
2789	AssertRC(rc);
2790	}
2791
2792
2793	/**
2794	* Transfers data of an AC'97 stream according to its usage (input / output).
2795	*
2796	* For an SDO (output) stream this means reading DMA data from the device to
2797	* the AC'97 stream's internal FIFO buffer.
2798	*
2799	* For an SDI (input) stream this is reading audio data from the AC'97 stream's
2800	* internal FIFO buffer and writing it as DMA data to the device.
2801	*
2802	* @returns IPRT status code.
2803	* @param pDevIns The device instance.
2804	* @param pThis The shared AC'97 state.
2805	* @param pStream The AC'97 stream to update (shared).
2806	* @param pStreamCC The AC'97 stream to update (ring-3).
2807	* @param cbToProcessMax Maximum of data (in bytes) to process.
2808	*/
2809	static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
2810	PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax)
2811	{
2812	if (!cbToProcessMax)
2813	return VINF_SUCCESS;
2814
2815	#ifdef VBOX_STRICT
2816	const unsigned cbFrame = DrvAudioHlpPCMPropsBytesPerFrame(&pStreamCC->State.Cfg.Props);
2817	#endif
2818
2819	/* Make sure to only process an integer number of audio frames. */
2820	Assert(cbToProcessMax % cbFrame == 0);
2821
2822	ichac97R3StreamLock(pStreamCC);
2823
2824	PAC97BMREGS pRegs = &pStream->Regs;
2825
2826	if (pRegs->sr & AC97_SR_DCH) /* Controller halted? */
2827	{
2828	if (pRegs->cr & AC97_CR_RPBM) /* Bus master operation starts. */
2829	{
2830	switch (pStream->u8SD)
2831	{
2832	case AC97SOUNDSOURCE_PO_INDEX:
2833	/ichac97R3WriteBUP(pThis, cbToProcess);/
2834	break;
2835
2836	default:
2837	break;
2838	}
2839	}
2840
2841	ichac97R3StreamUnlock(pStreamCC);
2842	return VINF_SUCCESS;
2843	}
2844
2845	/* BCIS flag still set? Skip iteration. */
2846	if (pRegs->sr & AC97_SR_BCIS)
2847	{
2848	Log3Func(("[SD%RU8] BCIS set\n", pStream->u8SD));
2849
2850	ichac97R3StreamUnlock(pStreamCC);
2851	return VINF_SUCCESS;
2852	}
2853
2854	uint32_t cbLeft = RT_MIN((uint32_t)(pRegs->picb << 1), cbToProcessMax); /** @todo r=andy Assumes 16bit samples. */
2855	uint32_t cbProcessedTotal = 0;
2856
2857	PRTCIRCBUF pCircBuf = pStreamCC->State.pCircBuf;
2858	AssertPtr(pCircBuf);
2859
2860	int rc = VINF_SUCCESS;
2861
2862	Log3Func(("[SD%RU8] cbToProcessMax=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcessMax, cbLeft));
2863
2864	while (cbLeft)
2865	{
2866	if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
2867	{
2868	Log3Func(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
2869	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
2870	if (pRegs->civ == pRegs->lvi)
2871	{
2872	pRegs->sr \|= AC97_SR_DCH; /** @todo r=andy Also set CELV? */
2873	pThis->bup_flag = 0;
2874
2875	rc = VINF_EOF;
2876	break;
2877	}
2878
2879	pRegs->sr &= ~AC97_SR_CELV;
2880	pRegs->civ = pRegs->piv;
2881	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2882
2883	ichac97R3StreamFetchBDLE(pDevIns, pStream);
2884	continue;
2885	}
2886
2887	uint32_t cbChunk = cbLeft;
2888
2889	switch (pStream->u8SD)
2890	{
2891	case AC97SOUNDSOURCE_PO_INDEX: /* Output */
2892	{
2893	void *pvDst;
2894	size_t cbDst;
2895
2896	RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvDst, &cbDst);
2897
2898	if (cbDst)
2899	{
2900	int rc2 = PDMDevHlpPCIPhysRead(pDevIns, pRegs->bd.addr, (uint8_t *)pvDst, cbDst);
2901	AssertRC(rc2);
2902
2903	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2904	{ /* likely */ }
2905	else
2906	DrvAudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvDst, cbDst, 0 /* fFlags */);
2907	}
2908
2909	RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
2910
2911	cbChunk = (uint32_t)cbDst; /* Update the current chunk size to what really has been written. */
2912	break;
2913	}
2914
2915	case AC97SOUNDSOURCE_PI_INDEX: /* Input */
2916	case AC97SOUNDSOURCE_MC_INDEX: /* Input */
2917	{
2918	void *pvSrc;
2919	size_t cbSrc;
2920
2921	RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvSrc, &cbSrc);
2922
2923	if (cbSrc)
2924	{
2925	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, pRegs->bd.addr, (uint8_t *)pvSrc, cbSrc);
2926	AssertRC(rc2);
2927
2928	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2929	{ /* likely */ }
2930	else
2931	DrvAudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvSrc, cbSrc, 0 /* fFlags */);
2932	}
2933
2934	RTCircBufReleaseReadBlock(pCircBuf, cbSrc);
2935
2936	cbChunk = (uint32_t)cbSrc; /* Update the current chunk size to what really has been read. */
2937	break;
2938	}
2939
2940	default:
2941	AssertMsgFailed(("Stream #%RU8 not supported\n", pStream->u8SD));
2942	rc = VERR_NOT_SUPPORTED;
2943	break;
2944	}
2945
2946	if (RT_FAILURE(rc))
2947	break;
2948
2949	if (cbChunk)
2950	{
2951	cbProcessedTotal += cbChunk;
2952	Assert(cbProcessedTotal <= cbToProcessMax);
2953	Assert(cbLeft >= cbChunk);
2954	cbLeft -= cbChunk;
2955	Assert((cbChunk & 1) == 0); /* Else the following shift won't work */
2956
2957	pRegs->picb -= (cbChunk >> 1); /** @todo r=andy Assumes 16bit samples. */
2958	pRegs->bd.addr += cbChunk;
2959	}
2960
2961	LogFlowFunc(("[SD%RU8] cbChunk=%RU32, cbLeft=%RU32, cbTotal=%RU32, rc=%Rrc\n",
2962	pStream->u8SD, cbChunk, cbLeft, cbProcessedTotal, rc));
2963
2964	if (!pRegs->picb)
2965	{
2966	uint32_t new_sr = pRegs->sr & ~AC97_SR_CELV;
2967
2968	if (pRegs->bd.ctl_len & AC97_BD_IOC)
2969	{
2970	new_sr \|= AC97_SR_BCIS;
2971	}
2972
2973	if (pRegs->civ == pRegs->lvi)
2974	{
2975	/* Did we run out of data? */
2976	LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pRegs->civ, pRegs->lvi));
2977
2978	new_sr \|= AC97_SR_LVBCI \| AC97_SR_DCH \| AC97_SR_CELV;
2979	pThis->bup_flag = (pRegs->bd.ctl_len & AC97_BD_BUP) ? BUP_LAST : 0;
2980
2981	rc = VINF_EOF;
2982	}
2983	else
2984	{
2985	pRegs->civ = pRegs->piv;
2986	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2987	ichac97R3StreamFetchBDLE(pDevIns, pStream);
2988	}
2989
2990	ichac97StreamUpdateSR(pDevIns, pThis, pStream, new_sr);
2991	}
2992
2993	if (/* All data processed? */
2994	rc == VINF_EOF
2995	/* ... or an error occurred? */
2996	\|\| RT_FAILURE(rc))
2997	{
2998	break;
2999	}
3000	}
3001
3002	ichac97R3StreamUnlock(pStreamCC);
3003
3004	LogFlowFuncLeaveRC(rc);
3005	return rc;
3006	}
3007
3008	#endif /* IN_RING3 */
3009
3010
3011	/**
3012	* @callback_method_impl{FNIOMIOPORTNEWIN}
3013	*/
3014	static DECLCALLBACK(VBOXSTRICTRC)
3015	ichac97IoPortNabmRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3016	{
3017	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3018	RT_NOREF(pvUser);
3019
3020	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3021
3022	/* Get the index of the NABMBAR port. */
3023	if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
3024	&& offPort != AC97_GLOB_CNT)
3025	{
3026	PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
3027	PAC97BMREGS pRegs = &pStream->Regs;
3028
3029	switch (cb)
3030	{
3031	case 1:
3032	switch (offPort & AC97_NABM_OFF_MASK)
3033	{
3034	case AC97_NABM_OFF_CIV:
3035	/* Current Index Value Register */
3036	*pu32 = pRegs->civ;
3037	Log3Func(("CIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3038	break;
3039	case AC97_NABM_OFF_LVI:
3040	/* Last Valid Index Register */
3041	*pu32 = pRegs->lvi;
3042	Log3Func(("LVI[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3043	break;
3044	case AC97_NABM_OFF_PIV:
3045	/* Prefetched Index Value Register */
3046	*pu32 = pRegs->piv;
3047	Log3Func(("PIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3048	break;
3049	case AC97_NABM_OFF_CR:
3050	/* Control Register */
3051	*pu32 = pRegs->cr;
3052	Log3Func(("CR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3053	break;
3054	case AC97_NABM_OFF_SR:
3055	/* Status Register (lower part) */
3056	*pu32 = RT_LO_U8(pRegs->sr);
3057	Log3Func(("SRb[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3058	break;
3059	default:
3060	*pu32 = UINT32_MAX;
3061	LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
3062	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3063	break;
3064	}
3065	break;
3066
3067	case 2:
3068	switch (offPort & AC97_NABM_OFF_MASK)
3069	{
3070	case AC97_NABM_OFF_SR:
3071	/* Status Register */
3072	*pu32 = pRegs->sr;
3073	Log3Func(("SR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3074	break;
3075	case AC97_NABM_OFF_PICB:
3076	/* Position in Current Buffer */
3077	*pu32 = pRegs->picb;
3078	Log3Func(("PICB[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3079	break;
3080	default:
3081	*pu32 = UINT32_MAX;
3082	LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
3083	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3084	break;
3085	}
3086	break;
3087
3088	case 4:
3089	switch (offPort & AC97_NABM_OFF_MASK)
3090	{
3091	case AC97_NABM_OFF_BDBAR:
3092	/* Buffer Descriptor Base Address Register */
3093	*pu32 = pRegs->bdbar;
3094	Log3Func(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3095	break;
3096	case AC97_NABM_OFF_CIV:
3097	/* 32-bit access: Current Index Value Register +
3098	* Last Valid Index Register +
3099	* Status Register */
3100	pu32 = pRegs->civ \| (pRegs->lvi << 8) \| (pRegs->sr << 16); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
3101	Log3Func(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
3102	AC97_PORT2IDX(offPort), pRegs->civ, pRegs->lvi, pRegs->sr));
3103	break;
3104	case AC97_NABM_OFF_PICB:
3105	/* 32-bit access: Position in Current Buffer Register +
3106	* Prefetched Index Value Register +
3107	* Control Register */
3108	pu32 = pRegs->picb \| (pRegs->piv << 16) \| (pRegs->cr << 24); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
3109	Log3Func(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
3110	AC97_PORT2IDX(offPort), *pu32, pRegs->picb, pRegs->piv, pRegs->cr));
3111	break;
3112
3113	default:
3114	*pu32 = UINT32_MAX;
3115	LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
3116	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3117	break;
3118	}
3119	break;
3120
3121	default:
3122	DEVAC97_UNLOCK(pDevIns, pThis);
3123	AssertFailed();
3124	return VERR_IOM_IOPORT_UNUSED;
3125	}
3126	}
3127	else
3128	{
3129	switch (cb)
3130	{
3131	case 1:
3132	switch (offPort)
3133	{
3134	case AC97_CAS:
3135	/* Codec Access Semaphore Register */
3136	Log3Func(("CAS %d\n", pThis->cas));
3137	*pu32 = pThis->cas;
3138	pThis->cas = 1;
3139	break;
3140	default:
3141	*pu32 = UINT32_MAX;
3142	LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
3143	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3144	break;
3145	}
3146	break;
3147
3148	case 2:
3149	*pu32 = UINT32_MAX;
3150	LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
3151	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3152	break;
3153
3154	case 4:
3155	switch (offPort)
3156	{
3157	case AC97_GLOB_CNT:
3158	/* Global Control */
3159	*pu32 = pThis->glob_cnt;
3160	Log3Func(("glob_cnt -> %#x\n", *pu32));
3161	break;
3162	case AC97_GLOB_STA:
3163	/* Global Status */
3164	*pu32 = pThis->glob_sta \| AC97_GS_S0CR;
3165	Log3Func(("glob_sta -> %#x\n", *pu32));
3166	break;
3167	default:
3168	*pu32 = UINT32_MAX;
3169	LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
3170	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3171	break;
3172	}
3173	break;
3174
3175	default:
3176	DEVAC97_UNLOCK(pDevIns, pThis);
3177	AssertFailed();
3178	return VERR_IOM_IOPORT_UNUSED;
3179	}
3180	}
3181
3182	DEVAC97_UNLOCK(pDevIns, pThis);
3183	return VINF_SUCCESS;
3184	}
3185
3186	/**
3187	* @callback_method_impl{FNIOMIOPORTNEWOUT}
3188	*/
3189	static DECLCALLBACK(VBOXSTRICTRC)
3190	ichac97IoPortNabmWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3191	{
3192	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3193	#ifdef IN_RING3
3194	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3195	#endif
3196	RT_NOREF(pvUser);
3197
3198	VBOXSTRICTRC rc = VINF_SUCCESS;
3199	if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
3200	&& offPort != AC97_GLOB_CNT)
3201	{
3202	#ifdef IN_RING3
3203	PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[AC97_PORT2IDX(offPort)];
3204	#endif
3205	PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
3206	PAC97BMREGS pRegs = &pStream->Regs;
3207
3208	DEVAC97_LOCK_BOTH_RETURN(pDevIns, pThis, pStream, VINF_IOM_R3_IOPORT_WRITE);
3209	switch (cb)
3210	{
3211	case 1:
3212	switch (offPort & AC97_NABM_OFF_MASK)
3213	{
3214	/*
3215	* Last Valid Index.
3216	*/
3217	case AC97_NABM_OFF_LVI:
3218	if ( (pRegs->cr & AC97_CR_RPBM)
3219	&& (pRegs->sr & AC97_SR_DCH))
3220	{
3221	#ifdef IN_RING3
3222	pRegs->sr &= ~(AC97_SR_DCH \| AC97_SR_CELV);
3223	pRegs->civ = pRegs->piv;
3224	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3225	#else
3226	rc = VINF_IOM_R3_IOPORT_WRITE;
3227	#endif
3228	}
3229	pRegs->lvi = u32 % AC97_MAX_BDLE;
3230	Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32));
3231	break;
3232
3233	/*
3234	* Control Registers.
3235	*/
3236	case AC97_NABM_OFF_CR:
3237	#ifdef IN_RING3
3238	Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32, pRegs->cr));
3239	if (u32 & AC97_CR_RR) /* Busmaster reset. */
3240	{
3241	Log3Func(("[SD%RU8] Reset\n", pStream->u8SD));
3242
3243	/* Make sure that Run/Pause Bus Master bit (RPBM) is cleared (0). */
3244	Assert((pRegs->cr & AC97_CR_RPBM) == 0);
3245
3246	ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3247	ichac97R3StreamReset(pThis, pStream, pStreamCC);
3248
3249	ichac97StreamUpdateSR(pDevIns, pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */
3250	}
3251	else
3252	{
3253	pRegs->cr = u32 & AC97_CR_VALID_MASK;
3254
3255	if (!(pRegs->cr & AC97_CR_RPBM))
3256	{
3257	Log3Func(("[SD%RU8] Disable\n", pStream->u8SD));
3258
3259	ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3260
3261	pRegs->sr \|= AC97_SR_DCH;
3262	}
3263	else
3264	{
3265	Log3Func(("[SD%RU8] Enable\n", pStream->u8SD));
3266
3267	pRegs->civ = pRegs->piv;
3268	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3269
3270	pRegs->sr &= ~AC97_SR_DCH;
3271
3272	/* Fetch the initial BDLE descriptor. */
3273	ichac97R3StreamFetchBDLE(pDevIns, pStream);
3274	# ifdef LOG_ENABLED
3275	ichac97R3BDLEDumpAll(pDevIns, pStream->Regs.bdbar, pStream->Regs.lvi + 1);
3276	# endif
3277	ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, true /* fEnable */);
3278
3279	/* Arm the timer for this stream. */
3280	/** @todo r=bird: This function returns bool, not VBox status! */
3281	ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3282	}
3283	}
3284	#else /* !IN_RING3 */
3285	rc = VINF_IOM_R3_IOPORT_WRITE;
3286	#endif
3287	break;
3288
3289	/*
3290	* Status Registers.
3291	*/
3292	case AC97_NABM_OFF_SR:
3293	ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3294	break;
3295
3296	default:
3297	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3298	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3299	break;
3300	}
3301	break;
3302
3303	case 2:
3304	switch (offPort & AC97_NABM_OFF_MASK)
3305	{
3306	case AC97_NABM_OFF_SR:
3307	ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3308	break;
3309	default:
3310	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3311	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3312	break;
3313	}
3314	break;
3315
3316	case 4:
3317	switch (offPort & AC97_NABM_OFF_MASK)
3318	{
3319	case AC97_NABM_OFF_BDBAR:
3320	/* Buffer Descriptor list Base Address Register */
3321	pRegs->bdbar = u32 & ~3;
3322	Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(offPort), u32, pRegs->bdbar));
3323	break;
3324	default:
3325	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3326	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3327	break;
3328	}
3329	break;
3330
3331	default:
3332	AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3333	break;
3334	}
3335	DEVAC97_UNLOCK_BOTH(pDevIns, pThis, pStream);
3336	}
3337	else
3338	{
3339	switch (cb)
3340	{
3341	case 1:
3342	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3343	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3344	break;
3345
3346	case 2:
3347	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3348	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3349	break;
3350
3351	case 4:
3352	switch (offPort)
3353	{
3354	case AC97_GLOB_CNT:
3355	/* Global Control */
3356	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3357	if (u32 & AC97_GC_WR)
3358	ichac97WarmReset(pThis);
3359	if (u32 & AC97_GC_CR)
3360	ichac97ColdReset(pThis);
3361	if (!(u32 & (AC97_GC_WR \| AC97_GC_CR)))
3362	pThis->glob_cnt = u32 & AC97_GC_VALID_MASK;
3363	Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt));
3364	DEVAC97_UNLOCK(pDevIns, pThis);
3365	break;
3366	case AC97_GLOB_STA:
3367	/* Global Status */
3368	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3369	pThis->glob_sta &= ~(u32 & AC97_GS_WCLEAR_MASK);
3370	pThis->glob_sta \|= (u32 & ~(AC97_GS_WCLEAR_MASK \| AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK;
3371	Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta));
3372	DEVAC97_UNLOCK(pDevIns, pThis);
3373	break;
3374	default:
3375	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3376	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3377	break;
3378	}
3379	break;
3380
3381	default:
3382	AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3383	break;
3384	}
3385	}
3386
3387	return rc;
3388	}
3389
3390	/**
3391	* @callback_method_impl{FNIOMIOPORTNEWIN}
3392	*/
3393	static DECLCALLBACK(VBOXSTRICTRC)
3394	ichac97IoPortNamRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3395	{
3396	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3397	RT_NOREF(pvUser);
3398	Assert(offPort < 256);
3399
3400	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3401
3402	VBOXSTRICTRC rc = VINF_SUCCESS;
3403	switch (cb)
3404	{
3405	case 1:
3406	{
3407	LogRel2(("AC97: Warning: Unimplemented read (1 byte) offPort=%#x\n", offPort));
3408	pThis->cas = 0;
3409	*pu32 = UINT32_MAX;
3410	break;
3411	}
3412
3413	case 2:
3414	{
3415	pThis->cas = 0;
3416	*pu32 = ichac97MixerGet(pThis, offPort);
3417	break;
3418	}
3419
3420	case 4:
3421	{
3422	LogRel2(("AC97: Warning: Unimplemented read (4 bytes) offPort=%#x\n", offPort));
3423	pThis->cas = 0;
3424	*pu32 = UINT32_MAX;
3425	break;
3426	}
3427
3428	default:
3429	{
3430	AssertFailed();
3431	rc = VERR_IOM_IOPORT_UNUSED;
3432	}
3433	}
3434
3435	DEVAC97_UNLOCK(pDevIns, pThis);
3436	return rc;
3437	}
3438
3439	/**
3440	* @callback_method_impl{FNIOMIOPORTNEWOUT}
3441	*/
3442	static DECLCALLBACK(VBOXSTRICTRC)
3443	ichac97IoPortNamWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3444	{
3445	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3446	#ifdef IN_RING3
3447	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3448	#endif
3449	RT_NOREF(pvUser);
3450
3451	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3452
3453	VBOXSTRICTRC rc = VINF_SUCCESS;
3454	switch (cb)
3455	{
3456	case 1:
3457	{
3458	LogRel2(("AC97: Warning: Unimplemented NAMWrite (1 byte) offPort=%#x <- %#x\n", offPort, u32));
3459	pThis->cas = 0;
3460	break;
3461	}
3462
3463	case 2:
3464	{
3465	pThis->cas = 0;
3466	switch (offPort)
3467	{
3468	case AC97_Reset:
3469	#ifdef IN_RING3
3470	ichac97R3Reset(pDevIns);
3471	#else
3472	rc = VINF_IOM_R3_IOPORT_WRITE;
3473	#endif
3474	break;
3475	case AC97_Powerdown_Ctrl_Stat:
3476	u32 &= ~0xf;
3477	u32 \|= ichac97MixerGet(pThis, offPort) & 0xf;
3478	ichac97MixerSet(pThis, offPort, u32);
3479	break;
3480	case AC97_Master_Volume_Mute:
3481	if (pThis->enmCodecModel == AC97CODEC_AD1980)
3482	{
3483	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_LOSEL)
3484	break; /* Register controls surround (rear), do nothing. */
3485	}
3486	#ifdef IN_RING3
3487	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3488	#else
3489	rc = VINF_IOM_R3_IOPORT_WRITE;
3490	#endif
3491	break;
3492	case AC97_Headphone_Volume_Mute:
3493	if (pThis->enmCodecModel == AC97CODEC_AD1980)
3494	{
3495	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3496	{
3497	/* Register controls PCM (front) outputs. */
3498	#ifdef IN_RING3
3499	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3500	#else
3501	rc = VINF_IOM_R3_IOPORT_WRITE;
3502	#endif
3503	}
3504	}
3505	break;
3506	case AC97_PCM_Out_Volume_Mute:
3507	#ifdef IN_RING3
3508	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_FRONT, u32);
3509	#else
3510	rc = VINF_IOM_R3_IOPORT_WRITE;
3511	#endif
3512	break;
3513	case AC97_Line_In_Volume_Mute:
3514	#ifdef IN_RING3
3515	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3516	#else
3517	rc = VINF_IOM_R3_IOPORT_WRITE;
3518	#endif
3519	break;
3520	case AC97_Record_Select:
3521	#ifdef IN_RING3
3522	ichac97R3MixerRecordSelect(pThis, u32);
3523	#else
3524	rc = VINF_IOM_R3_IOPORT_WRITE;
3525	#endif
3526	break;
3527	case AC97_Record_Gain_Mute:
3528	#ifdef IN_RING3
3529	/* Newer Ubuntu guests rely on that when controlling gain and muting
3530	* the recording (capturing) levels. */
3531	ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3532	#else
3533	rc = VINF_IOM_R3_IOPORT_WRITE;
3534	#endif
3535	break;
3536	case AC97_Record_Gain_Mic_Mute:
3537	#ifdef IN_RING3
3538	/* Ditto; see note above. */
3539	ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_MIC_IN, u32);
3540	#else
3541	rc = VINF_IOM_R3_IOPORT_WRITE;
3542	#endif
3543	break;
3544	case AC97_Vendor_ID1:
3545	case AC97_Vendor_ID2:
3546	LogFunc(("Attempt to write vendor ID to %#x\n", u32));
3547	break;
3548	case AC97_Extended_Audio_ID:
3549	LogFunc(("Attempt to write extended audio ID to %#x\n", u32));
3550	break;
3551	case AC97_Extended_Audio_Ctrl_Stat:
3552	#ifdef IN_RING3
3553	/*
3554	* Handle VRA bits.
3555	*/
3556	if (!(u32 & AC97_EACS_VRA)) /* Check if VRA bit is not set. */
3557	{
3558	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 0xbb80); /* Set default (48000 Hz). */
3559	ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3560	&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3561
3562	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3563	ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3564	&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3565	}
3566	else
3567	LogRel2(("AC97: Variable rate audio (VRA) is not supported\n"));
3568
3569	/*
3570	* Handle VRM bits.
3571	*/
3572	if (!(u32 & AC97_EACS_VRM)) /* Check if VRM bit is not set. */
3573	{
3574	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3575	ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3576	&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3577	}
3578	else
3579	LogRel2(("AC97: Variable rate microphone audio (VRM) is not supported\n"));
3580
3581	LogRel2(("AC97: Setting extended audio control to %#x\n", u32));
3582	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32);
3583	#else /* !IN_RING3 */
3584	rc = VINF_IOM_R3_IOPORT_WRITE;
3585	#endif
3586	break;
3587	case AC97_PCM_Front_DAC_Rate: /* Output slots 3, 4, 6. */
3588	#ifdef IN_RING3
3589	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3590	{
3591	LogRel2(("AC97: Setting front DAC rate to 0x%x\n", u32));
3592	ichac97MixerSet(pThis, offPort, u32);
3593	ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3594	&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3595	}
3596	else
3597	LogRel2(("AC97: Setting front DAC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3598	#else
3599	rc = VINF_IOM_R3_IOPORT_WRITE;
3600	#endif
3601	break;
3602	case AC97_MIC_ADC_Rate: /* Input slot 6. */
3603	#ifdef IN_RING3
3604	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRM)
3605	{
3606	LogRel2(("AC97: Setting microphone ADC rate to 0x%x\n", u32));
3607	ichac97MixerSet(pThis, offPort, u32);
3608	ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3609	&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3610	}
3611	else
3612	LogRel2(("AC97: Setting microphone ADC rate (0x%x) when VRM is not set is forbidden, ignoring\n", u32));
3613	#else
3614	rc = VINF_IOM_R3_IOPORT_WRITE;
3615	#endif
3616	break;
3617	case AC97_PCM_LR_ADC_Rate: /* Input slots 3, 4. */
3618	#ifdef IN_RING3
3619	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3620	{
3621	LogRel2(("AC97: Setting line-in ADC rate to 0x%x\n", u32));
3622	ichac97MixerSet(pThis, offPort, u32);
3623	ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3624	&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3625	}
3626	else
3627	LogRel2(("AC97: Setting line-in ADC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3628	#else
3629	rc = VINF_IOM_R3_IOPORT_WRITE;
3630	#endif
3631	break;
3632	default:
3633	LogRel2(("AC97: Warning: Unimplemented NAMWrite (2 bytes) offPort=%#x <- %#x\n", offPort, u32));
3634	ichac97MixerSet(pThis, offPort, u32);
3635	break;
3636	}
3637	break;
3638	}
3639
3640	case 4:
3641	{
3642	LogRel2(("AC97: Warning: Unimplemented 4 byte NAMWrite: offPort=%#x <- %#x\n", offPort, u32));
3643	pThis->cas = 0;
3644	break;
3645	}
3646
3647	default:
3648	AssertMsgFailed(("Unhandled NAMWrite offPort=%#x, cb=%u u32=%#x\n", offPort, cb, u32));
3649	break;
3650	}
3651
3652	DEVAC97_UNLOCK(pDevIns, pThis);
3653	return rc;
3654	}
3655
3656	#ifdef IN_RING3
3657
3658	/**
3659	* Saves (serializes) an AC'97 stream using SSM.
3660	*
3661	* @param pDevIns Device instance.
3662	* @param pSSM Saved state manager (SSM) handle to use.
3663	* @param pStream AC'97 stream to save.
3664	*/
3665	static void ichac97R3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3666	{
3667	PAC97BMREGS pRegs = &pStream->Regs;
3668	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3669
3670	pHlp->pfnSSMPutU32(pSSM, pRegs->bdbar);
3671	pHlp->pfnSSMPutU8( pSSM, pRegs->civ);
3672	pHlp->pfnSSMPutU8( pSSM, pRegs->lvi);
3673	pHlp->pfnSSMPutU16(pSSM, pRegs->sr);
3674	pHlp->pfnSSMPutU16(pSSM, pRegs->picb);
3675	pHlp->pfnSSMPutU8( pSSM, pRegs->piv);
3676	pHlp->pfnSSMPutU8( pSSM, pRegs->cr);
3677	pHlp->pfnSSMPutS32(pSSM, pRegs->bd_valid);
3678	pHlp->pfnSSMPutU32(pSSM, pRegs->bd.addr);
3679	pHlp->pfnSSMPutU32(pSSM, pRegs->bd.ctl_len);
3680	}
3681
3682	/**
3683	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3684	*/
3685	static DECLCALLBACK(int) ichac97R3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3686	{
3687	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3688	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3689	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3690	LogFlowFuncEnter();
3691
3692	pHlp->pfnSSMPutU32(pSSM, pThis->glob_cnt);
3693	pHlp->pfnSSMPutU32(pSSM, pThis->glob_sta);
3694	pHlp->pfnSSMPutU32(pSSM, pThis->cas);
3695
3696	/*
3697	* The order that the streams are saved here is fixed, so don't change.
3698	*/
3699	/** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
3700	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3701	ichac97R3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3702
3703	pHlp->pfnSSMPutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3704
3705	/* The stream order is against fixed and set in stone. */
3706	uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3707	afActiveStrms[AC97SOUNDSOURCE_PI_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX]);
3708	afActiveStrms[AC97SOUNDSOURCE_PO_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX]);
3709	afActiveStrms[AC97SOUNDSOURCE_MC_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX]);
3710	AssertCompile(RT_ELEMENTS(afActiveStrms) == 3);
3711	pHlp->pfnSSMPutMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3712
3713	LogFlowFuncLeaveRC(VINF_SUCCESS);
3714	return VINF_SUCCESS;
3715	}
3716
3717	/**
3718	* Loads an AC'97 stream from SSM.
3719	*
3720	* @returns IPRT status code.
3721	* @param pDevIns The device instance.
3722	* @param pSSM Saved state manager (SSM) handle to use.
3723	* @param pStream AC'97 stream to load.
3724	*/
3725	static int ichac97R3LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3726	{
3727	PAC97BMREGS pRegs = &pStream->Regs;
3728	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3729
3730	pHlp->pfnSSMGetU32(pSSM, &pRegs->bdbar);
3731	pHlp->pfnSSMGetU8( pSSM, &pRegs->civ);
3732	pHlp->pfnSSMGetU8( pSSM, &pRegs->lvi);
3733	pHlp->pfnSSMGetU16(pSSM, &pRegs->sr);
3734	pHlp->pfnSSMGetU16(pSSM, &pRegs->picb);
3735	pHlp->pfnSSMGetU8( pSSM, &pRegs->piv);
3736	pHlp->pfnSSMGetU8( pSSM, &pRegs->cr);
3737	pHlp->pfnSSMGetS32(pSSM, &pRegs->bd_valid);
3738	pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.addr);
3739	return pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.ctl_len);
3740	}
3741
3742	/**
3743	* @callback_method_impl{FNSSMDEVLOADEXEC}
3744	*/
3745	static DECLCALLBACK(int) ichac97R3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3746	{
3747	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3748	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3749	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3750
3751	LogRel2(("ichac97LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3752
3753	AssertMsgReturn (uVersion == AC97_SAVED_STATE_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3754	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3755
3756	pHlp->pfnSSMGetU32(pSSM, &pThis->glob_cnt);
3757	pHlp->pfnSSMGetU32(pSSM, &pThis->glob_sta);
3758	pHlp->pfnSSMGetU32(pSSM, &pThis->cas);
3759
3760	/*
3761	* The order the streams are loaded here is critical (defined by
3762	* AC97SOUNDSOURCE_XX_INDEX), so don't touch!
3763	*/
3764	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3765	{
3766	int rc2 = ichac97R3LoadStream(pDevIns, pSSM, &pThis->aStreams[i]);
3767	AssertRCReturn(rc2, rc2);
3768	}
3769
3770	pHlp->pfnSSMGetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3771
3772	ichac97R3MixerRecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
3773	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3774	ichac97MixerGet(pThis, AC97_Master_Volume_Mute));
3775	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT,
3776	ichac97MixerGet(pThis, AC97_PCM_Out_Volume_Mute));
3777	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3778	ichac97MixerGet(pThis, AC97_Line_In_Volume_Mute));
3779	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3780	ichac97MixerGet(pThis, AC97_Mic_Volume_Mute));
3781	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3782	ichac97MixerGet(pThis, AC97_Record_Gain_Mic_Mute));
3783	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3784	ichac97MixerGet(pThis, AC97_Record_Gain_Mute));
3785	if (pThis->enmCodecModel == AC97CODEC_AD1980)
3786	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3787	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3788	ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
3789
3790	/*
3791	* Again the stream order is set is stone.
3792	*/
3793	uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3794	int rc2 = pHlp->pfnSSMGetMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3795	AssertRCReturn(rc2, rc2);
3796
3797	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3798	{
3799	const bool fEnable = RT_BOOL(afActiveStrms[i]);
3800	const PAC97STREAM pStream = &pThis->aStreams[i];
3801	const PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[i];
3802
3803	rc2 = ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, fEnable);
3804	AssertRC(rc2);
3805	if ( fEnable
3806	&& RT_SUCCESS(rc2))
3807	{
3808	/* Re-arm the timer for this stream. */
3809	/** @todo r=aeichner This causes a VM hang upon saved state resume when NetBSD is used as a guest
3810	* Stopping the timer if cTransferTicks is 0 is a workaround but needs further investigation,
3811	* see @bugref{9759} for more information. */
3812	if (pStreamCC->State.cTransferTicks)
3813	ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3814	else
3815	PDMDevHlpTimerStop(pDevIns, pStream->hTimer);
3816	}
3817
3818	/* Keep going. */
3819	}
3820
3821	pThis->bup_flag = 0;
3822	pThis->last_samp = 0;
3823
3824	return VINF_SUCCESS;
3825	}
3826
3827
3828	/**
3829	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3830	*/
3831	static DECLCALLBACK(void ) ichac97R3QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
3832	{
3833	PAC97STATER3 pThisCC = RT_FROM_MEMBER(pInterface, AC97STATER3, IBase);
3834	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
3835	return NULL;
3836	}
3837
3838
3839	/**
3840	* Powers off the device.
3841	*
3842	* @param pDevIns Device instance to power off.
3843	*/
3844	static DECLCALLBACK(void) ichac97R3PowerOff(PPDMDEVINS pDevIns)
3845	{
3846	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3847	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3848
3849	LogRel2(("AC97: Powering off ...\n"));
3850
3851	/* Note: Involves mixer stream / sink destruction, so also do this here
3852	* instead of in ichac97R3Destruct(). */
3853	ichac97R3StreamsDestroy(pThis, pThisCC);
3854
3855	/*
3856	* Note: Destroy the mixer while powering off and not in ichac97R3Destruct,
3857	* giving the mixer the chance to release any references held to
3858	* PDM audio streams it maintains.
3859	*/
3860	if (pThisCC->pMixer)
3861	{
3862	AudioMixerDestroy(pThisCC->pMixer);
3863	pThisCC->pMixer = NULL;
3864	}
3865	}
3866
3867
3868	/**
3869	* @interface_method_impl{PDMDEVREG,pfnReset}
3870	*
3871	* @remarks The original sources didn't install a reset handler, but it seems to
3872	* make sense to me so we'll do it.
3873	*/
3874	static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns)
3875	{
3876	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3877	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3878
3879	LogRel(("AC97: Reset\n"));
3880
3881	/*
3882	* Reset the mixer too. The Windows XP driver seems to rely on
3883	* this. At least it wants to read the vendor id before it resets
3884	* the codec manually.
3885	*/
3886	ichac97R3MixerReset(pThis, pThisCC);
3887
3888	/*
3889	* Reset all streams.
3890	*/
3891	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3892	{
3893	ichac97R3StreamEnable(pThis, pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], false /* fEnable */);
3894	ichac97R3StreamReset(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
3895	}
3896
3897	/*
3898	* Reset mixer sinks.
3899	*
3900	* Do the reset here instead of in ichac97R3StreamReset();
3901	* the mixer sink(s) might still have data to be processed when an audio stream gets reset.
3902	*/
3903	AudioMixerSinkReset(pThisCC->pSinkLineIn);
3904	AudioMixerSinkReset(pThisCC->pSinkMicIn);
3905	AudioMixerSinkReset(pThisCC->pSinkOut);
3906	}
3907
3908
3909	/**
3910	* Attach command, internal version.
3911	*
3912	* This is called to let the device attach to a driver for a specified LUN
3913	* during runtime. This is not called during VM construction, the device
3914	* constructor has to attach to all the available drivers.
3915	*
3916	* @returns VBox status code.
3917	* @param pDevIns The device instance.
3918	* @param pThisCC The ring-3 AC'97 device state.
3919	* @param iLun The logical unit which is being attached.
3920	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3921	* @param ppDrv Attached driver instance on success. Optional.
3922	*/
3923	static int ichac97R3AttachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned iLun, uint32_t fFlags, PAC97DRIVER *ppDrv)
3924	{
3925	RT_NOREF(fFlags);
3926
3927	/*
3928	* Attach driver.
3929	*/
3930	char *pszDesc;
3931	if (RTStrAPrintf(&pszDesc, "Audio driver port (AC'97) for LUN #%u", iLun) <= 0)
3932	AssertLogRelFailedReturn(VERR_NO_MEMORY);
3933
3934	PPDMIBASE pDrvBase;
3935	int rc = PDMDevHlpDriverAttach(pDevIns, iLun, &pThisCC->IBase, &pDrvBase, pszDesc);
3936	if (RT_SUCCESS(rc))
3937	{
3938	PAC97DRIVER pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
3939	if (pDrv)
3940	{
3941	pDrv->pDrvBase = pDrvBase;
3942	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
3943	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN #%u has no host audio interface, rc=%Rrc\n", iLun, rc));
3944	pDrv->uLUN = iLun;
3945	pDrv->pszDesc = pszDesc;
3946
3947	/*
3948	* For now we always set the driver at LUN 0 as our primary
3949	* host backend. This might change in the future.
3950	*/
3951	if (iLun == 0)
3952	pDrv->fFlags \|= PDMAUDIODRVFLAGS_PRIMARY;
3953
3954	LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", iLun, pDrv->pConnector, pDrv->fFlags));
3955
3956	/* Attach to driver list if not attached yet. */
3957	if (!pDrv->fAttached)
3958	{
3959	RTListAppend(&pThisCC->lstDrv, &pDrv->Node);
3960	pDrv->fAttached = true;
3961	}
3962
3963	if (ppDrv)
3964	*ppDrv = pDrv;
3965	}
3966	else
3967	rc = VERR_NO_MEMORY;
3968	}
3969	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3970	LogFunc(("No attached driver for LUN #%u\n", iLun));
3971
3972	if (RT_FAILURE(rc))
3973	{
3974	/* Only free this string on failure;
3975	* must remain valid for the live of the driver instance. */
3976	RTStrFree(pszDesc);
3977	}
3978
3979	LogFunc(("iLun=%u, fFlags=0x%x, rc=%Rrc\n", iLun, fFlags, rc));
3980	return rc;
3981	}
3982
3983	/**
3984	* Detach command, internal version.
3985	*
3986	* This is called to let the device detach from a driver for a specified LUN
3987	* during runtime.
3988	*
3989	* @returns VBox status code.
3990	* @param pThisCC The ring-3 AC'97 device state.
3991	* @param pDrv Driver to detach from device.
3992	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3993	*/
3994	static int ichac97R3DetachInternal(PAC97STATER3 pThisCC, PAC97DRIVER pDrv, uint32_t fFlags)
3995	{
3996	RT_NOREF(fFlags);
3997
3998	/* First, remove the driver from our list and destory it's associated streams.
3999	* This also will un-set the driver as a recording source (if associated). */
4000	ichac97R3MixerRemoveDrv(pThisCC, pDrv);
4001
4002	/* Next, search backwards for a capable (attached) driver which now will be the
4003	* new recording source. */
4004	PDMAUDIODSTSRCUNION dstSrc;
4005	PAC97DRIVER pDrvCur;
4006	RTListForEachReverse(&pThisCC->lstDrv, pDrvCur, AC97DRIVER, Node)
4007	{
4008	if (!pDrvCur->pConnector)
4009	continue;
4010
4011	PDMAUDIOBACKENDCFG Cfg;
4012	int rc2 = pDrvCur->pConnector->pfnGetConfig(pDrvCur->pConnector, &Cfg);
4013	if (RT_FAILURE(rc2))
4014	continue;
4015
4016	dstSrc.enmSrc = PDMAUDIORECSRC_MIC;
4017	PAC97DRIVERSTREAM pDrvStrm = ichac97R3MixerGetDrvStream(pDrvCur, PDMAUDIODIR_IN, dstSrc);
4018	if ( pDrvStrm
4019	&& pDrvStrm->pMixStrm)
4020	{
4021	rc2 = AudioMixerSinkSetRecordingSource(pThisCC->pSinkMicIn, pDrvStrm->pMixStrm);
4022	if (RT_SUCCESS(rc2))
4023	LogRel2(("AC97: Set new recording source for 'Mic In' to '%s'\n", Cfg.szName));
4024	}
4025
4026	dstSrc.enmSrc = PDMAUDIORECSRC_LINE;
4027	pDrvStrm = ichac97R3MixerGetDrvStream(pDrvCur, PDMAUDIODIR_IN, dstSrc);
4028	if ( pDrvStrm
4029	&& pDrvStrm->pMixStrm)
4030	{
4031	rc2 = AudioMixerSinkSetRecordingSource(pThisCC->pSinkLineIn, pDrvStrm->pMixStrm);
4032	if (RT_SUCCESS(rc2))
4033	LogRel2(("AC97: Set new recording source for 'Line In' to '%s'\n", Cfg.szName));
4034	}
4035	}
4036
4037	LogFunc(("uLUN=%u, fFlags=0x%x\n", pDrv->uLUN, fFlags));
4038	return VINF_SUCCESS;
4039	}
4040
4041	/**
4042	* @interface_method_impl{PDMDEVREGR3,pfnAttach}
4043	*/
4044	static DECLCALLBACK(int) ichac97R3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4045	{
4046	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4047	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4048
4049	LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
4050
4051	DEVAC97_LOCK(pDevIns, pThis);
4052
4053	PAC97DRIVER pDrv;
4054	int rc2 = ichac97R3AttachInternal(pDevIns, pThisCC, iLUN, fFlags, &pDrv);
4055	if (RT_SUCCESS(rc2))
4056	rc2 = ichac97R3MixerAddDrv(pThisCC, pDrv);
4057
4058	if (RT_FAILURE(rc2))
4059	LogFunc(("Failed with %Rrc\n", rc2));
4060
4061	DEVAC97_UNLOCK(pDevIns, pThis);
4062
4063	return VINF_SUCCESS;
4064	}
4065
4066	/**
4067	* @interface_method_impl{PDMDEVREG,pfnDetach}
4068	*/
4069	static DECLCALLBACK(void) ichac97R3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4070	{
4071	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4072	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4073
4074	LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
4075
4076	DEVAC97_LOCK(pDevIns, pThis);
4077
4078	PAC97DRIVER pDrv, pDrvNext;
4079	RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
4080	{
4081	if (pDrv->uLUN == iLUN)
4082	{
4083	int rc2 = ichac97R3DetachInternal(pThisCC, pDrv, fFlags);
4084	if (RT_SUCCESS(rc2))
4085	{
4086	RTStrFree(pDrv->pszDesc);
4087	RTMemFree(pDrv);
4088	pDrv = NULL;
4089	}
4090
4091	break;
4092	}
4093	}
4094
4095	DEVAC97_UNLOCK(pDevIns, pThis);
4096	}
4097
4098	/**
4099	* Replaces a driver with a the NullAudio drivers.
4100	*
4101	* @returns VBox status code.
4102	* @param pDevIns The device instance.
4103	* @param pThisCC The ring-3 AC'97 device state.
4104	* @param iLun The logical unit which is being replaced.
4105	*/
4106	static int ichac97R3ReconfigLunWithNullAudio(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned iLun)
4107	{
4108	int rc = PDMDevHlpDriverReconfigure2(pDevIns, iLun, "AUDIO", "NullAudio");
4109	if (RT_SUCCESS(rc))
4110	rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, 0 /* fFlags /, NULL / ppDrv */);
4111	LogFunc(("pThisCC=%p, iLun=%u, rc=%Rrc\n", pThisCC, iLun, rc));
4112	return rc;
4113	}
4114
4115	/**
4116	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4117	*/
4118	static DECLCALLBACK(int) ichac97R3Destruct(PPDMDEVINS pDevIns)
4119	{
4120	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4121	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4122
4123	LogFlowFuncEnter();
4124
4125	PAC97DRIVER pDrv, pDrvNext;
4126	RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
4127	{
4128	RTListNodeRemove(&pDrv->Node);
4129	RTMemFree(pDrv->pszDesc);
4130	RTMemFree(pDrv);
4131	}
4132
4133	/* Sanity. */
4134	Assert(RTListIsEmpty(&pThisCC->lstDrv));
4135
4136	return VINF_SUCCESS;
4137	}
4138
4139	/**
4140	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4141	*/
4142	static DECLCALLBACK(int) ichac97R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4143	{
4144	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4145	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4146	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4147	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4148	Assert(iInstance == 0); RT_NOREF(iInstance);
4149
4150	/*
4151	* Initialize data so we can run the destructor without scewing up.
4152	*/
4153	pThisCC->pDevIns = pDevIns;
4154	pThisCC->IBase.pfnQueryInterface = ichac97R3QueryInterface;
4155	RTListInit(&pThisCC->lstDrv);
4156
4157	/*
4158	* Validate and read configuration.
4159	*/
4160	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Codec\|TimerHz\|DebugEnabled\|DebugPathOut", "");
4161
4162	char szCodec[20];
4163	int rc = pHlp->pfnCFGMQueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
4164	if (RT_FAILURE(rc))
4165	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4166	N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
4167
4168	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, AC97_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4169	if (RT_FAILURE(rc))
4170	return PDMDEV_SET_ERROR(pDevIns, rc,
4171	N_("AC'97 configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4172
4173	if (pThis->uTimerHz != AC97_TIMER_HZ_DEFAULT)
4174	LogRel(("AC97: Using custom device timer rate (%RU16Hz)\n", pThis->uTimerHz));
4175
4176	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "DebugEnabled", &pThisCC->Dbg.fEnabled, false);
4177	if (RT_FAILURE(rc))
4178	return PDMDEV_SET_ERROR(pDevIns, rc,
4179	N_("AC97 configuration error: failed to read debugging enabled flag as boolean"));
4180
4181	rc = pHlp->pfnCFGMQueryStringAllocDef(pCfg, "DebugPathOut", &pThisCC->Dbg.pszOutPath, VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4182	if (RT_FAILURE(rc))
4183	return PDMDEV_SET_ERROR(pDevIns, rc,
4184	N_("AC97 configuration error: failed to read debugging output path flag as string"));
4185
4186	if (pThisCC->Dbg.fEnabled)
4187	LogRel2(("AC97: Debug output will be saved to '%s'\n", pThisCC->Dbg.pszOutPath));
4188
4189	/*
4190	* The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
4191	* in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
4192	* 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
4193	*/
4194	if (!strcmp(szCodec, "STAC9700"))
4195	pThis->enmCodecModel = AC97CODEC_STAC9700;
4196	else if (!strcmp(szCodec, "AD1980"))
4197	pThis->enmCodecModel = AC97CODEC_AD1980;
4198	else if (!strcmp(szCodec, "AD1981B"))
4199	pThis->enmCodecModel = AC97CODEC_AD1981B;
4200	else
4201	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
4202	N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"), szCodec);
4203
4204	LogRel(("AC97: Using codec '%s'\n", szCodec));
4205
4206	/*
4207	* Use an own critical section for the device instead of the default
4208	* one provided by PDM. This allows fine-grained locking in combination
4209	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4210	*/
4211	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "AC'97");
4212	AssertRCReturn(rc, rc);
4213
4214	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4215	AssertRCReturn(rc, rc);
4216
4217	/*
4218	* Initialize data (most of it anyway).
4219	*/
4220	/* PCI Device */
4221	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4222	PCIDevSetVendorId(pPciDev, 0x8086); /* 00 ro - intel. */ Assert(pPciDev->abConfig[0x00] == 0x86); Assert(pPciDev->abConfig[0x01] == 0x80);
4223	PCIDevSetDeviceId(pPciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pPciDev->abConfig[0x02] == 0x15); Assert(pPciDev->abConfig[0x03] == 0x24);
4224	PCIDevSetCommand(pPciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pPciDev->abConfig[0x04] == 0x00); Assert(pPciDev->abConfig[0x05] == 0x00);
4225	PCIDevSetStatus(pPciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM \| VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pPciDev->abConfig[0x06] == 0x80); Assert(pPciDev->abConfig[0x07] == 0x02);
4226	PCIDevSetRevisionId(pPciDev, 0x01); /* 08 ro - rid. */ Assert(pPciDev->abConfig[0x08] == 0x01);
4227	PCIDevSetClassProg(pPciDev, 0x00); /* 09 ro - pi. */ Assert(pPciDev->abConfig[0x09] == 0x00);
4228	PCIDevSetClassSub(pPciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pPciDev->abConfig[0x0a] == 0x01);
4229	PCIDevSetClassBase(pPciDev, 0x04); /* 0b ro - bcc; 04 == multimedia.*/Assert(pPciDev->abConfig[0x0b] == 0x04);
4230	PCIDevSetHeaderType(pPciDev, 0x00); /* 0e ro - headtyp. */ Assert(pPciDev->abConfig[0x0e] == 0x00);
4231	PCIDevSetBaseAddress(pPciDev, 0, /* 10 rw - nambar - native audio mixer base. */
4232	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x10] == 0x01); Assert(pPciDev->abConfig[0x11] == 0x00); Assert(pPciDev->abConfig[0x12] == 0x00); Assert(pPciDev->abConfig[0x13] == 0x00);
4233	PCIDevSetBaseAddress(pPciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
4234	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x14] == 0x01); Assert(pPciDev->abConfig[0x15] == 0x00); Assert(pPciDev->abConfig[0x16] == 0x00); Assert(pPciDev->abConfig[0x17] == 0x00);
4235	PCIDevSetInterruptLine(pPciDev, 0x00); /* 3c rw. */ Assert(pPciDev->abConfig[0x3c] == 0x00);
4236	PCIDevSetInterruptPin(pPciDev, 0x01); /* 3d ro - INTA#. */ Assert(pPciDev->abConfig[0x3d] == 0x01);
4237
4238	if (pThis->enmCodecModel == AC97CODEC_AD1980)
4239	{
4240	PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4241	PCIDevSetSubSystemId(pPciDev, 0x0177); /* 2e ro. */
4242	}
4243	else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
4244	{
4245	PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4246	PCIDevSetSubSystemId(pPciDev, 0x01ad); /* 2e ro. */
4247	}
4248	else
4249	{
4250	PCIDevSetSubSystemVendorId(pPciDev, 0x8086); /* 2c ro - Intel.) */
4251	PCIDevSetSubSystemId(pPciDev, 0x0000); /* 2e ro. */
4252	}
4253
4254	/*
4255	* Register the PCI device and associated I/O regions.
4256	*/
4257	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4258	if (RT_FAILURE(rc))
4259	return rc;
4260
4261	rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 0 /iPciRegion/, 256 /cPorts/,
4262	ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /pvUser/,
4263	"ICHAC97 NAM", NULL /paExtDescs/, &pThis->hIoPortsNam);
4264	AssertRCReturn(rc, rc);
4265
4266	rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 1 /iPciRegion/, 64 /cPorts/,
4267	ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /pvUser/,
4268	"ICHAC97 NABM", g_aNabmPorts, &pThis->hIoPortsNabm);
4269	AssertRCReturn(rc, rc);
4270
4271	/*
4272	* Saved state.
4273	*/
4274	rc = PDMDevHlpSSMRegister(pDevIns, AC97_SAVED_STATE_VERSION, sizeof(*pThis), ichac97R3SaveExec, ichac97R3LoadExec);
4275	if (RT_FAILURE(rc))
4276	return rc;
4277
4278	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
4279	LogRel(("AC97: Asynchronous I/O enabled\n"));
4280	# endif
4281
4282	/*
4283	* Attach drivers. We ASSUME they are configured consecutively without any
4284	* gaps, so we stop when we hit the first LUN w/o a driver configured.
4285	*/
4286	for (unsigned iLun = 0; ; iLun++)
4287	{
4288	AssertBreak(iLun < UINT8_MAX);
4289	LogFunc(("Trying to attach driver for LUN#%u ...\n", iLun));
4290	rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, 0 /* fFlags /, NULL / ppDrv */);
4291	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4292	{
4293	LogFunc(("cLUNs=%u\n", iLun));
4294	break;
4295	}
4296	if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
4297	{
4298	ichac97R3ReconfigLunWithNullAudio(pDevIns, pThisCC, iLun); /* Pretend attaching to the NULL audio backend will never fail. */
4299	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4300	N_("Host audio backend initialization has failed. "
4301	"Selecting the NULL audio backend with the consequence that no sound is audible"));
4302	}
4303	else
4304	AssertLogRelMsgReturn(RT_SUCCESS(rc), ("LUN#%u: rc=%Rrc\n", iLun, rc), rc);
4305	}
4306
4307	rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThisCC->pMixer);
4308	AssertRCReturn(rc, rc);
4309	rc = AudioMixerCreateSink(pThisCC->pMixer, "[Recording] Line In", AUDMIXSINKDIR_INPUT, &pThisCC->pSinkLineIn);
4310	AssertRCReturn(rc, rc);
4311	rc = AudioMixerCreateSink(pThisCC->pMixer, "[Recording] Microphone In", AUDMIXSINKDIR_INPUT, &pThisCC->pSinkMicIn);
4312	AssertRCReturn(rc, rc);
4313	rc = AudioMixerCreateSink(pThisCC->pMixer, "[Playback] PCM Output", AUDMIXSINKDIR_OUTPUT, &pThisCC->pSinkOut);
4314	AssertRCReturn(rc, rc);
4315
4316	/*
4317	* Create all hardware streams.
4318	*/
4319	AssertCompile(RT_ELEMENTS(pThis->aStreams) == AC97_MAX_STREAMS);
4320	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4321	{
4322	rc = ichac97R3StreamCreate(pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], i /* SD# */);
4323	AssertRCReturn(rc, rc);
4324	}
4325
4326	/*
4327	* Create the emulation timers (one per stream).
4328	*
4329	* We must the critical section for the timers as the device has a
4330	* noop section associated with it.
4331	*
4332	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's AC'97 driver
4333	* relies on exact (virtual) DMA timing and uses DMA Position Buffers
4334	* instead of the LPIB registers.
4335	*/
4336	/** @todo r=bird: The need to use virtual sync is perhaps because TM
4337	* doesn't schedule regular TMCLOCK_VIRTUAL timers as accurately as it
4338	* should (VT-x preemption timer, etc). Hope to address that before
4339	* long. @bugref{9943}. */
4340	static const char * const s_apszNames[] = { "AC97 PI", "AC97 PO", "AC97 MC" };
4341	AssertCompile(RT_ELEMENTS(s_apszNames) == AC97_MAX_STREAMS);
4342	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4343	{
4344	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, ichac97R3Timer, &pThis->aStreams[i],
4345	TMTIMER_FLAGS_NO_CRIT_SECT \| TMTIMER_FLAGS_RING0, s_apszNames[i], &pThis->aStreams[i].hTimer);
4346	AssertRCReturn(rc, rc);
4347
4348	rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->aStreams[i].hTimer, &pThis->CritSect);
4349	AssertRCReturn(rc, rc);
4350	}
4351
4352
4353	# ifdef VBOX_WITH_AUDIO_AC97_ONETIME_INIT
4354	PAC97DRIVER pDrv;
4355	RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
4356	{
4357	/*
4358	* Only primary drivers are critical for the VM to run. Everything else
4359	* might not worth showing an own error message box in the GUI.
4360	*/
4361	if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
4362	continue;
4363
4364	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
4365	AssertPtr(pCon);
4366
4367	bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
4368	bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
4369	bool fValidOut = AudioMixerStreamIsValid(pDrv->Out.pMixStrm);
4370
4371	if ( !fValidLineIn
4372	&& !fValidMicIn
4373	&& !fValidOut)
4374	{
4375	LogRel(("AC97: Falling back to NULL backend (no sound audible)\n"));
4376	ichac97R3Reset(pDevIns);
4377	ichac97R3ReconfigLunWithNullAudio(pdEvIns, pThsiCC, iLun);
4378	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4379	N_("No audio devices could be opened. "
4380	"Selecting the NULL audio backend with the consequence that no sound is audible"));
4381	}
4382	else
4383	{
4384	bool fWarn = false;
4385
4386	PDMAUDIOBACKENDCFG backendCfg;
4387	int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
4388	if (RT_SUCCESS(rc2))
4389	{
4390	if (backendCfg.cMaxStreamsIn)
4391	{
4392	/* If the audio backend supports two or more input streams at once,
4393	* warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
4394	if (backendCfg.cMaxStreamsIn >= 2)
4395	fWarn = !fValidLineIn \|\| !fValidMicIn;
4396	/* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
4397	* not ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
4398	* One of the two simply is not in use then. */
4399	else if (backendCfg.cMaxStreamsIn == 1)
4400	fWarn = !fValidLineIn && !fValidMicIn;
4401	/* Don't warn if our backend is not able of supporting any input streams at all. */
4402	}
4403
4404	if ( !fWarn
4405	&& backendCfg.cMaxStreamsOut)
4406	{
4407	fWarn = !fValidOut;
4408	}
4409	}
4410	else
4411	{
4412	LogRel(("AC97: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
4413	fWarn = true;
4414	}
4415
4416	if (fWarn)
4417	{
4418	char szMissingStreams[255] = "";
4419	size_t len = 0;
4420	if (!fValidLineIn)
4421	{
4422	LogRel(("AC97: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
4423	len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
4424	}
4425	if (!fValidMicIn)
4426	{
4427	LogRel(("AC97: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
4428	len += RTStrPrintf(szMissingStreams + len,
4429	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
4430	}
4431	if (!fValidOut)
4432	{
4433	LogRel(("AC97: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
4434	len += RTStrPrintf(szMissingStreams + len,
4435	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
4436	}
4437
4438	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4439	N_("Some AC'97 audio streams (%s) could not be opened. Guest applications generating audio "
4440	"output or depending on audio input may hang. Make sure your host audio device "
4441	"is working properly. Check the logfile for error messages of the audio "
4442	"subsystem"), szMissingStreams);
4443	}
4444	}
4445	}
4446	# endif /* VBOX_WITH_AUDIO_AC97_ONETIME_INIT */
4447
4448	ichac97R3Reset(pDevIns);
4449
4450	/*
4451	* Register statistics.
4452	*/
4453	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmReads, STAMTYPE_COUNTER, "UnimplementedNabmReads", STAMUNIT_OCCURENCES, "Unimplemented NABM register reads.");
4454	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmWrites, STAMTYPE_COUNTER, "UnimplementedNabmWrites", STAMUNIT_OCCURENCES, "Unimplemented NABM register writes.");
4455	# ifdef VBOX_WITH_STATISTICS
4456	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
4457	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
4458	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
4459	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
4460	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
4461	# endif
4462
4463	LogFlowFuncLeaveRC(VINF_SUCCESS);
4464	return VINF_SUCCESS;
4465	}
4466
4467	#else /* !IN_RING3 */
4468
4469	/**
4470	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4471	*/
4472	static DECLCALLBACK(int) ichac97RZConstruct(PPDMDEVINS pDevIns)
4473	{
4474	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4475	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4476
4477	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4478	AssertRCReturn(rc, rc);
4479
4480	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNam, ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /pvUser/);
4481	AssertRCReturn(rc, rc);
4482	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNabm, ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /pvUser/);
4483	AssertRCReturn(rc, rc);
4484
4485	return VINF_SUCCESS;
4486	}
4487
4488	#endif /* !IN_RING3 */
4489
4490	/**
4491	* The device registration structure.
4492	*/
4493	const PDMDEVREG g_DeviceICHAC97 =
4494	{
4495	/* .u32Version = */ PDM_DEVREG_VERSION,
4496	/* .uReserved0 = */ 0,
4497	/* .szName = */ "ichac97",
4498	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
4499	/* .fClass = */ PDM_DEVREG_CLASS_AUDIO,
4500	/* .cMaxInstances = */ 1,
4501	/* .uSharedVersion = */ 42,
4502	/* .cbInstanceShared = */ sizeof(AC97STATE),
4503	/* .cbInstanceCC = */ CTX_EXPR(sizeof(AC97STATER3), 0, 0),
4504	/* .cbInstanceRC = */ 0,
4505	/* .cMaxPciDevices = */ 1,
4506	/* .cMaxMsixVectors = */ 0,
4507	/* .pszDescription = */ "ICH AC'97 Audio Controller",
4508	#if defined(IN_RING3)
4509	/* .pszRCMod = */ "VBoxDDRC.rc",
4510	/* .pszR0Mod = */ "VBoxDDR0.r0",
4511	/* .pfnConstruct = */ ichac97R3Construct,
4512	/* .pfnDestruct = */ ichac97R3Destruct,
4513	/* .pfnRelocate = */ NULL,
4514	/* .pfnMemSetup = */ NULL,
4515	/* .pfnPowerOn = */ NULL,
4516	/* .pfnReset = */ ichac97R3Reset,
4517	/* .pfnSuspend = */ NULL,
4518	/* .pfnResume = */ NULL,
4519	/* .pfnAttach = */ ichac97R3Attach,
4520	/* .pfnDetach = */ ichac97R3Detach,
4521	/* .pfnQueryInterface = */ NULL,
4522	/* .pfnInitComplete = */ NULL,
4523	/* .pfnPowerOff = */ ichac97R3PowerOff,
4524	/* .pfnSoftReset = */ NULL,
4525	/* .pfnReserved0 = */ NULL,
4526	/* .pfnReserved1 = */ NULL,
4527	/* .pfnReserved2 = */ NULL,
4528	/* .pfnReserved3 = */ NULL,
4529	/* .pfnReserved4 = */ NULL,
4530	/* .pfnReserved5 = */ NULL,
4531	/* .pfnReserved6 = */ NULL,
4532	/* .pfnReserved7 = */ NULL,
4533	#elif defined(IN_RING0)
4534	/* .pfnEarlyConstruct = */ NULL,
4535	/* .pfnConstruct = */ ichac97RZConstruct,
4536	/* .pfnDestruct = */ NULL,
4537	/* .pfnFinalDestruct = */ NULL,
4538	/* .pfnRequest = */ NULL,
4539	/* .pfnReserved0 = */ NULL,
4540	/* .pfnReserved1 = */ NULL,
4541	/* .pfnReserved2 = */ NULL,
4542	/* .pfnReserved3 = */ NULL,
4543	/* .pfnReserved4 = */ NULL,
4544	/* .pfnReserved5 = */ NULL,
4545	/* .pfnReserved6 = */ NULL,
4546	/* .pfnReserved7 = */ NULL,
4547	#elif defined(IN_RC)
4548	/* .pfnConstruct = */ ichac97RZConstruct,
4549	/* .pfnReserved0 = */ NULL,
4550	/* .pfnReserved1 = */ NULL,
4551	/* .pfnReserved2 = */ NULL,
4552	/* .pfnReserved3 = */ NULL,
4553	/* .pfnReserved4 = */ NULL,
4554	/* .pfnReserved5 = */ NULL,
4555	/* .pfnReserved6 = */ NULL,
4556	/* .pfnReserved7 = */ NULL,
4557	#else
4558	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4559	#endif
4560	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
4561	};
4562
4563	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4564

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source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 87760

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