DevIchAc97.cpp@ 88023

Last change on this file since 88023 was 88023, checked in by vboxsync, 4 years ago
Audio: Preparing to move some of the DrvAudio.h stuff into PDM. bugref:9890
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1	/* $Id: DevIchAc97.cpp 88023 2021-03-08 18:01:15Z vboxsync $ */
2	/** @file
3	* DevIchAc97 - VBox ICH AC97 Audio Controller.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_AC97
23	#include <VBox/log.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/vmm/pdmaudioifs.h>
26
27	#include <iprt/assert.h>
28	#ifdef IN_RING3
29	# ifdef DEBUG
30	# include <iprt/file.h>
31	# endif
32	# include <iprt/mem.h>
33	# include <iprt/semaphore.h>
34	# include <iprt/string.h>
35	# include <iprt/uuid.h>
36	#endif
37
38	#include "VBoxDD.h"
39
40	#include "AudioMixBuffer.h"
41	#include "AudioMixer.h"
42	#include "DrvAudio.h"
43
44
45	/*********************************************************************************************************************************
46	* Defined Constants And Macros *
47	*********************************************************************************************************************************/
48
49	/** Current saved state version. */
50	#define AC97_SAVED_STATE_VERSION 1
51
52	/** Default timer frequency (in Hz). */
53	#define AC97_TIMER_HZ_DEFAULT 100
54
55	/** Maximum number of streams we support. */
56	#define AC97_MAX_STREAMS 3
57
58	/** Maximum FIFO size (in bytes). */
59	#define AC97_FIFO_MAX 256
60
61	#define AC97_SR_FIFOE RT_BIT(4) /*< rwc, FIFO error. /
62	#define AC97_SR_BCIS RT_BIT(3) /*< rwc, Buffer completion interrupt status. /
63	#define AC97_SR_LVBCI RT_BIT(2) /*< rwc, Last valid buffer completion interrupt. /
64	#define AC97_SR_CELV RT_BIT(1) /*< ro, Current equals last valid. /
65	#define AC97_SR_DCH RT_BIT(0) /*< ro, Controller halted. /
66	#define AC97_SR_VALID_MASK (RT_BIT(5) - 1)
67	#define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE \| AC97_SR_BCIS \| AC97_SR_LVBCI)
68	#define AC97_SR_RO_MASK (AC97_SR_DCH \| AC97_SR_CELV)
69	#define AC97_SR_INT_MASK (AC97_SR_FIFOE \| AC97_SR_BCIS \| AC97_SR_LVBCI)
70
71	#define AC97_CR_IOCE RT_BIT(4) /*< rw, Interrupt On Completion Enable. /
72	#define AC97_CR_FEIE RT_BIT(3) /*< rw FIFO Error Interrupt Enable. /
73	#define AC97_CR_LVBIE RT_BIT(2) /*< rw Last Valid Buffer Interrupt Enable. /
74	#define AC97_CR_RR RT_BIT(1) /*< rw Reset Registers. /
75	#define AC97_CR_RPBM RT_BIT(0) /*< rw Run/Pause Bus Master. /
76	#define AC97_CR_VALID_MASK (RT_BIT(5) - 1)
77	#define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE \| AC97_CR_FEIE \| AC97_CR_LVBIE)
78
79	#define AC97_GC_WR 4 /*< rw Warm reset. /
80	#define AC97_GC_CR 2 /*< rw Cold reset. /
81	#define AC97_GC_VALID_MASK (RT_BIT(6) - 1)
82
83	#define AC97_GS_MD3 RT_BIT(17) /*< rw /
84	#define AC97_GS_AD3 RT_BIT(16) /*< rw /
85	#define AC97_GS_RCS RT_BIT(15) /*< rwc /
86	#define AC97_GS_B3S12 RT_BIT(14) /*< ro /
87	#define AC97_GS_B2S12 RT_BIT(13) /*< ro /
88	#define AC97_GS_B1S12 RT_BIT(12) /*< ro /
89	#define AC97_GS_S1R1 RT_BIT(11) /*< rwc /
90	#define AC97_GS_S0R1 RT_BIT(10) /*< rwc /
91	#define AC97_GS_S1CR RT_BIT(9) /*< ro /
92	#define AC97_GS_S0CR RT_BIT(8) /*< ro /
93	#define AC97_GS_MINT RT_BIT(7) /*< ro /
94	#define AC97_GS_POINT RT_BIT(6) /*< ro /
95	#define AC97_GS_PIINT RT_BIT(5) /*< ro /
96	#define AC97_GS_RSRVD (RT_BIT(4) \| RT_BIT(3))
97	#define AC97_GS_MOINT RT_BIT(2) /*< ro /
98	#define AC97_GS_MIINT RT_BIT(1) /*< ro /
99	#define AC97_GS_GSCI RT_BIT(0) /*< rwc /
100	#define AC97_GS_RO_MASK ( AC97_GS_B3S12 \
101	\| AC97_GS_B2S12 \
102	\| AC97_GS_B1S12 \
103	\| AC97_GS_S1CR \
104	\| AC97_GS_S0CR \
105	\| AC97_GS_MINT \
106	\| AC97_GS_POINT \
107	\| AC97_GS_PIINT \
108	\| AC97_GS_RSRVD \
109	\| AC97_GS_MOINT \
110	\| AC97_GS_MIINT)
111	#define AC97_GS_VALID_MASK (RT_BIT(18) - 1)
112	#define AC97_GS_WCLEAR_MASK (AC97_GS_RCS \| AC97_GS_S1R1 \| AC97_GS_S0R1 \| AC97_GS_GSCI)
113
114	/** @name Buffer Descriptor (BD).
115	* @{ */
116	#define AC97_BD_IOC RT_BIT(31) /*< Interrupt on Completion. /
117	#define AC97_BD_BUP RT_BIT(30) /*< Buffer Underrun Policy. /
118
119	#define AC97_BD_LEN_MASK 0xFFFF /*< Mask for the BDL buffer length. /
120
121	#define AC97_MAX_BDLE 32 /*< Maximum number of BDLEs. /
122	/** @} */
123
124	/** @name Extended Audio ID Register (EAID).
125	* @{ */
126	#define AC97_EAID_VRA RT_BIT(0) /*< Variable Rate Audio. /
127	#define AC97_EAID_VRM RT_BIT(3) /*< Variable Rate Mic Audio. /
128	#define AC97_EAID_REV0 RT_BIT(10) /*< AC'97 revision compliance. /
129	#define AC97_EAID_REV1 RT_BIT(11) /*< AC'97 revision compliance. /
130	/** @} */
131
132	/** @name Extended Audio Control and Status Register (EACS).
133	* @{ */
134	#define AC97_EACS_VRA RT_BIT(0) /*< Variable Rate Audio (4.2.1.1). /
135	#define AC97_EACS_VRM RT_BIT(3) /*< Variable Rate Mic Audio (4.2.1.1). /
136	/** @} */
137
138	/** @name Baseline Audio Register Set (BARS).
139	* @{ */
140	#define AC97_BARS_VOL_MASK 0x1f /*< Volume mask for the Baseline Audio Register Set (5.7.2). /
141	#define AC97_BARS_GAIN_MASK 0x0f /*< Gain mask for the Baseline Audio Register Set. /
142	#define AC97_BARS_VOL_MUTE_SHIFT 15 /*< Mute bit shift for the Baseline Audio Register Set (5.7.2). /
143	/** @} */
144
145	/** AC'97 uses 1.5dB steps, we use 0.375dB steps: 1 AC'97 step equals 4 PDM steps. */
146	#define AC97_DB_FACTOR 4
147
148	/** @name Recording inputs?
149	* @{ */
150	#define AC97_REC_MIC UINT8_C(0)
151	#define AC97_REC_CD UINT8_C(1)
152	#define AC97_REC_VIDEO UINT8_C(2)
153	#define AC97_REC_AUX UINT8_C(3)
154	#define AC97_REC_LINE_IN UINT8_C(4)
155	#define AC97_REC_STEREO_MIX UINT8_C(5)
156	#define AC97_REC_MONO_MIX UINT8_C(6)
157	#define AC97_REC_PHONE UINT8_C(7)
158	#define AC97_REC_MASK UINT8_C(7)
159	/** @} */
160
161	/** @name Mixer registers / NAM BAR registers?
162	* @{ */
163	#define AC97_Reset 0x00
164	#define AC97_Master_Volume_Mute 0x02
165	#define AC97_Headphone_Volume_Mute 0x04 /*< Also known as AUX, see table 16, section 5.7. /
166	#define AC97_Master_Volume_Mono_Mute 0x06
167	#define AC97_Master_Tone_RL 0x08
168	#define AC97_PC_BEEP_Volume_Mute 0x0a
169	#define AC97_Phone_Volume_Mute 0x0c
170	#define AC97_Mic_Volume_Mute 0x0e
171	#define AC97_Line_In_Volume_Mute 0x10
172	#define AC97_CD_Volume_Mute 0x12
173	#define AC97_Video_Volume_Mute 0x14
174	#define AC97_Aux_Volume_Mute 0x16
175	#define AC97_PCM_Out_Volume_Mute 0x18
176	#define AC97_Record_Select 0x1a
177	#define AC97_Record_Gain_Mute 0x1c
178	#define AC97_Record_Gain_Mic_Mute 0x1e
179	#define AC97_General_Purpose 0x20
180	#define AC97_3D_Control 0x22
181	#define AC97_AC_97_RESERVED 0x24
182	#define AC97_Powerdown_Ctrl_Stat 0x26
183	#define AC97_Extended_Audio_ID 0x28
184	#define AC97_Extended_Audio_Ctrl_Stat 0x2a
185	#define AC97_PCM_Front_DAC_Rate 0x2c
186	#define AC97_PCM_Surround_DAC_Rate 0x2e
187	#define AC97_PCM_LFE_DAC_Rate 0x30
188	#define AC97_PCM_LR_ADC_Rate 0x32
189	#define AC97_MIC_ADC_Rate 0x34
190	#define AC97_6Ch_Vol_C_LFE_Mute 0x36
191	#define AC97_6Ch_Vol_L_R_Surround_Mute 0x38
192	#define AC97_Vendor_Reserved 0x58
193	#define AC97_AD_Misc 0x76
194	#define AC97_Vendor_ID1 0x7c
195	#define AC97_Vendor_ID2 0x7e
196	/** @} */
197
198	/** @name Analog Devices miscellaneous regiter bits used in AD1980.
199	* @{ */
200	#define AC97_AD_MISC_LOSEL RT_BIT(5) /*< Surround (rear) goes to line out outputs. /
201	#define AC97_AD_MISC_HPSEL RT_BIT(10) /*< PCM (front) goes to headphone outputs. /
202	/** @} */
203
204
205	/** @name BUP flag values.
206	* @{ */
207	#define BUP_SET RT_BIT_32(0)
208	#define BUP_LAST RT_BIT_32(1)
209	/** @} */
210
211	/** @name AC'97 source indices.
212	* @note The order of these indices is fixed (also applies for saved states) for
213	* the moment. So make sure you know what you're done when altering this!
214	* @{
215	*/
216	#define AC97SOUNDSOURCE_PI_INDEX 0 /*< PCM in /
217	#define AC97SOUNDSOURCE_PO_INDEX 1 /*< PCM out /
218	#define AC97SOUNDSOURCE_MC_INDEX 2 /*< Mic in /
219	#define AC97SOUNDSOURCE_MAX 3 /*< Max sound sources. /
220	/** @} */
221
222	/** Port number (offset into NABM BAR) to stream index. */
223	#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
224	/** Port number (offset into NABM BAR) to stream index, but no masking. */
225	#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
226
227	/** @name Stream offsets
228	* @{ */
229	#define AC97_NABM_OFF_BDBAR 0x0 /*< Buffer Descriptor Base Address /
230	#define AC97_NABM_OFF_CIV 0x4 /*< Current Index Value /
231	#define AC97_NABM_OFF_LVI 0x5 /*< Last Valid Index /
232	#define AC97_NABM_OFF_SR 0x6 /*< Status Register /
233	#define AC97_NABM_OFF_PICB 0x8 /*< Position in Current Buffer /
234	#define AC97_NABM_OFF_PIV 0xa /*< Prefetched Index Value /
235	#define AC97_NABM_OFF_CR 0xb /*< Control Register /
236	#define AC97_NABM_OFF_MASK 0xf /*< Mask for getting the the per-stream register. /
237	/** @} */
238
239
240	/** @name PCM in NABM BAR registers (0x00..0x0f).
241	* @{ */
242	#define PI_BDBAR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x0) /*< PCM in: Buffer Descriptor Base Address /
243	#define PI_CIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x4) /*< PCM in: Current Index Value /
244	#define PI_LVI (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x5) /*< PCM in: Last Valid Index /
245	#define PI_SR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x6) /*< PCM in: Status Register /
246	#define PI_PICB (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x8) /*< PCM in: Position in Current Buffer /
247	#define PI_PIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xa) /*< PCM in: Prefetched Index Value /
248	#define PI_CR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xb) /*< PCM in: Control Register /
249	/** @} */
250
251	/** @name PCM out NABM BAR registers (0x10..0x1f).
252	* @{ */
253	#define PO_BDBAR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x0) /*< PCM out: Buffer Descriptor Base Address /
254	#define PO_CIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x4) /*< PCM out: Current Index Value /
255	#define PO_LVI (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x5) /*< PCM out: Last Valid Index /
256	#define PO_SR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x6) /*< PCM out: Status Register /
257	#define PO_PICB (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x8) /*< PCM out: Position in Current Buffer /
258	#define PO_PIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xa) /*< PCM out: Prefetched Index Value /
259	#define PO_CR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xb) /*< PCM out: Control Register /
260	/** @} */
261
262	/** @name Mic in NABM BAR registers (0x20..0x2f).
263	* @{ */
264	#define MC_BDBAR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x0) /*< PCM in: Buffer Descriptor Base Address /
265	#define MC_CIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x4) /*< PCM in: Current Index Value /
266	#define MC_LVI (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x5) /*< PCM in: Last Valid Index /
267	#define MC_SR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x6) /*< PCM in: Status Register /
268	#define MC_PICB (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x8) /*< PCM in: Position in Current Buffer /
269	#define MC_PIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xa) /*< PCM in: Prefetched Index Value /
270	#define MC_CR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xb) /*< PCM in: Control Register /
271	/** @} */
272
273	/** @name Misc NABM BAR registers.
274	* @{ */
275	/** NABMBAR: Global Control Register.
276	* @note This is kind of in the MIC IN area. */
277	#define AC97_GLOB_CNT 0x2c
278	/** NABMBAR: Global Status. */
279	#define AC97_GLOB_STA 0x30
280	/** Codec Access Semaphore Register. */
281	#define AC97_CAS 0x34
282	/** @} */
283
284
285	/*********************************************************************************************************************************
286	* Structures and Typedefs *
287	*********************************************************************************************************************************/
288	/** The ICH AC'97 (Intel) controller (shared). */
289	typedef struct AC97STATE *PAC97STATE;
290	/** The ICH AC'97 (Intel) controller (ring-3). */
291	typedef struct AC97STATER3 *PAC97STATER3;
292
293	/**
294	* Buffer Descriptor List Entry (BDLE).
295	*/
296	typedef struct AC97BDLE
297	{
298	/** Location of data buffer (bits 31:1). */
299	uint32_t addr;
300	/** Flags (bits 31 + 30) and length (bits 15:0) of data buffer (in audio samples). */
301	uint32_t ctl_len;
302	} AC97BDLE;
303	AssertCompileSize(AC97BDLE, 8);
304	/** Pointer to BDLE. */
305	typedef AC97BDLE *PAC97BDLE;
306
307	/**
308	* Bus master register set for an audio stream.
309	*/
310	typedef struct AC97BMREGS
311	{
312	uint32_t bdbar; /*< rw 0, Buffer Descriptor List: BAR (Base Address Register). /
313	uint8_t civ; /*< ro 0, Current index value. /
314	uint8_t lvi; /*< rw 0, Last valid index. /
315	uint16_t sr; /*< rw 1, Status register. /
316	uint16_t picb; /*< ro 0, Position in current buffer (in samples). /
317	uint8_t piv; /*< ro 0, Prefetched index value. /
318	uint8_t cr; /*< rw 0, Control register. /
319	int32_t bd_valid; /*< Whether current BDLE is initialized or not. /
320	AC97BDLE bd; /*< Current Buffer Descriptor List Entry (BDLE). /
321	} AC97BMREGS;
322	AssertCompileSizeAlignment(AC97BMREGS, 8);
323	/** Pointer to the BM registers of an audio stream. */
324	typedef AC97BMREGS *PAC97BMREGS;
325
326	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
327	/**
328	* Asynchronous I/O state for an AC'97 stream.
329	*/
330	typedef struct AC97STREAMSTATEAIO
331	{
332	/** Thread handle for the actual I/O thread. */
333	RTTHREAD Thread;
334	/** Event for letting the thread know there is some data to process. */
335	RTSEMEVENT Event;
336	/** Critical section for synchronizing access. */
337	RTCRITSECT CritSect;
338	/** Started indicator. */
339	volatile bool fStarted;
340	/** Shutdown indicator. */
341	volatile bool fShutdown;
342	/** Whether the thread should do any data processing or not. */
343	volatile bool fEnabled;
344	bool afPadding[5];
345	} AC97STREAMSTATEAIO;
346	/** Pointer to the async I/O state for an AC'97 stream. */
347	typedef AC97STREAMSTATEAIO *PAC97STREAMSTATEAIO;
348	#endif
349
350
351	/**
352	* The internal state of an AC'97 stream.
353	*/
354	typedef struct AC97STREAMSTATE
355	{
356	/** Criticial section for this stream. */
357	RTCRITSECT CritSect;
358	/** Circular buffer (FIFO) for holding DMA'ed data. */
359	R3PTRTYPE(PRTCIRCBUF) pCircBuf;
360	#if HC_ARCH_BITS == 32
361	uint32_t Padding;
362	#endif
363	/** The stream's current configuration. */
364	PDMAUDIOSTREAMCFG Cfg; //+108
365	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
366	/** Asynchronous I/O state members. */
367	AC97STREAMSTATEAIO AIO;
368	#endif
369	/** Timestamp of the last DMA data transfer. */
370	uint64_t tsTransferLast;
371	/** Timestamp of the next DMA data transfer.
372	* Next for determining the next scheduling window.
373	* Can be 0 if no next transfer is scheduled. */
374	uint64_t tsTransferNext;
375	/** Transfer chunk size (in bytes) of a transfer period. */
376	uint32_t cbTransferChunk;
377	/** The stream's timer Hz rate.
378	* This value can can be different from the device's default Hz rate,
379	* depending on the rate the stream expects (e.g. for 5.1 speaker setups).
380	* Set in R3StreamInit(). */
381	uint16_t uTimerHz;
382	uint8_t Padding3[2];
383	/** (Virtual) clock ticks per transfer. */
384	uint64_t cTransferTicks;
385	/** Timestamp (in ns) of last stream update. */
386	uint64_t tsLastUpdateNs;
387	} AC97STREAMSTATE;
388	AssertCompileSizeAlignment(AC97STREAMSTATE, 8);
389	/** Pointer to internal state of an AC'97 stream. */
390	typedef AC97STREAMSTATE *PAC97STREAMSTATE;
391
392	/**
393	* Runtime configurable debug stuff for an AC'97 stream.
394	*/
395	typedef struct AC97STREAMDEBUGRT
396	{
397	/** Whether debugging is enabled or not. */
398	bool fEnabled;
399	uint8_t Padding[7];
400	/** File for dumping stream reads / writes.
401	* For input streams, this dumps data being written to the device FIFO,
402	* whereas for output streams this dumps data being read from the device FIFO. */
403	R3PTRTYPE(PPDMAUDIOFILE) pFileStream;
404	/** File for dumping DMA reads / writes.
405	* For input streams, this dumps data being written to the device DMA,
406	* whereas for output streams this dumps data being read from the device DMA. */
407	R3PTRTYPE(PPDMAUDIOFILE) pFileDMA;
408	} AC97STREAMDEBUGRT;
409
410	/**
411	* Debug stuff for an AC'97 stream.
412	*/
413	typedef struct AC97STREAMDEBUG
414	{
415	/** Runtime debug stuff. */
416	AC97STREAMDEBUGRT Runtime;
417	} AC97STREAMDEBUG;
418
419	/**
420	* The shared AC'97 stream state.
421	*/
422	typedef struct AC97STREAM
423	{
424	/** Stream number (SDn). */
425	uint8_t u8SD;
426	uint8_t abPadding0[7];
427	/** Bus master registers of this stream. */
428	AC97BMREGS Regs;
429	/** The timer for pumping data thru the attached LUN drivers. */
430	TMTIMERHANDLE hTimer;
431	} AC97STREAM;
432	AssertCompileSizeAlignment(AC97STREAM, 8);
433	/** Pointer to a shared AC'97 stream state. */
434	typedef AC97STREAM *PAC97STREAM;
435
436
437	/**
438	* The ring-3 AC'97 stream state.
439	*/
440	typedef struct AC97STREAMR3
441	{
442	/** Stream number (SDn). */
443	uint8_t u8SD;
444	uint8_t abPadding0[7];
445	/** Internal state of this stream. */
446	AC97STREAMSTATE State;
447	/** Debug stuff. */
448	AC97STREAMDEBUG Dbg;
449	} AC97STREAMR3;
450	AssertCompileSizeAlignment(AC97STREAMR3, 8);
451	/** Pointer to an AC'97 stream state for ring-3. */
452	typedef AC97STREAMR3 *PAC97STREAMR3;
453
454
455	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
456	/**
457	* Asynchronous I/O thread context (arguments).
458	*/
459	typedef struct AC97STREAMTHREADCTX
460	{
461	/** The AC'97 device state (shared). */
462	PAC97STATE pThis;
463	/** The AC'97 device state (ring-3). */
464	PAC97STATER3 pThisCC;
465	/** The AC'97 stream state (shared). */
466	PAC97STREAM pStream;
467	/** The AC'97 stream state (ring-3). */
468	PAC97STREAMR3 pStreamCC;
469	} AC97STREAMTHREADCTX;
470	/** Pointer to the context for an async I/O thread. */
471	typedef AC97STREAMTHREADCTX *PAC97STREAMTHREADCTX;
472	#endif
473
474	/**
475	* A driver stream (host backend).
476	*
477	* Each driver has its own instances of audio mixer streams, which then
478	* can go into the same (or even different) audio mixer sinks.
479	*/
480	typedef struct AC97DRIVERSTREAM
481	{
482	/** Associated mixer stream handle. */
483	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
484	} AC97DRIVERSTREAM;
485	/** Pointer to a driver stream. */
486	typedef AC97DRIVERSTREAM *PAC97DRIVERSTREAM;
487
488	/**
489	* A host backend driver (LUN).
490	*/
491	typedef struct AC97DRIVER
492	{
493	/** Node for storing this driver in our device driver list of AC97STATE. */
494	RTLISTNODER3 Node;
495	/** Driver flags. */
496	PDMAUDIODRVFLAGS fFlags;
497	/** LUN # to which this driver has been assigned. */
498	uint8_t uLUN;
499	/** Whether this driver is in an attached state or not. */
500	bool fAttached;
501	uint8_t abPadding[2];
502	/** Pointer to the description string passed to PDMDevHlpDriverAttach(). */
503	R3PTRTYPE(char *) pszDesc;
504	/** Pointer to attached driver base interface. */
505	R3PTRTYPE(PPDMIBASE) pDrvBase;
506	/** Audio connector interface to the underlying host backend. */
507	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
508	/** Driver stream for line input. */
509	AC97DRIVERSTREAM LineIn;
510	/** Driver stream for mic input. */
511	AC97DRIVERSTREAM MicIn;
512	/** Driver stream for output. */
513	AC97DRIVERSTREAM Out;
514	} AC97DRIVER;
515	/** Pointer to a host backend driver (LUN). */
516	typedef AC97DRIVER *PAC97DRIVER;
517
518	/**
519	* Debug settings.
520	*/
521	typedef struct AC97STATEDEBUG
522	{
523	/** Whether debugging is enabled or not. */
524	bool fEnabled;
525	bool afAlignment[7];
526	/** Path where to dump the debug output to.
527	* Can be NULL, in which the system's temporary directory will be used then. */
528	R3PTRTYPE(char *) pszOutPath;
529	} AC97STATEDEBUG;
530
531
532	/* Codec models. */
533	typedef enum AC97CODEC
534	{
535	AC97CODEC_INVALID = 0, /*< Customary illegal zero value. /
536	AC97CODEC_STAC9700, /*< SigmaTel STAC9700 /
537	AC97CODEC_AD1980, /*< Analog Devices AD1980 /
538	AC97CODEC_AD1981B, /*< Analog Devices AD1981B /
539	AC97CODEC_32BIT_HACK = 0x7fffffff
540	} AC97CODEC;
541
542
543	/**
544	* The shared AC'97 device state.
545	*/
546	typedef struct AC97STATE
547	{
548	/** Critical section protecting the AC'97 state. */
549	PDMCRITSECT CritSect;
550	/** Global Control (Bus Master Control Register). */
551	uint32_t glob_cnt;
552	/** Global Status (Bus Master Control Register). */
553	uint32_t glob_sta;
554	/** Codec Access Semaphore Register (Bus Master Control Register). */
555	uint32_t cas;
556	uint32_t last_samp;
557	uint8_t mixer_data[256];
558	/** Array of AC'97 streams (parallel to AC97STATER3::aStreams). */
559	AC97STREAM aStreams[AC97_MAX_STREAMS];
560	/** The device timer Hz rate. Defaults to AC97_TIMER_HZ_DEFAULT_DEFAULT. */
561	uint16_t uTimerHz;
562	uint16_t au16Padding1[3];
563	uint8_t silence[128];
564	uint32_t bup_flag;
565	/** Codec model. */
566	AC97CODEC enmCodecModel;
567
568	/** PCI region \#0: NAM I/O ports. */
569	IOMIOPORTHANDLE hIoPortsNam;
570	/** PCI region \#0: NANM I/O ports. */
571	IOMIOPORTHANDLE hIoPortsNabm;
572
573	STAMCOUNTER StatUnimplementedNabmReads;
574	STAMCOUNTER StatUnimplementedNabmWrites;
575	#ifdef VBOX_WITH_STATISTICS
576	STAMPROFILE StatTimer;
577	STAMPROFILE StatIn;
578	STAMPROFILE StatOut;
579	STAMCOUNTER StatBytesRead;
580	STAMCOUNTER StatBytesWritten;
581	#endif
582	} AC97STATE;
583	AssertCompileMemberAlignment(AC97STATE, aStreams, 8);
584	AssertCompileMemberAlignment(AC97STATE, StatUnimplementedNabmReads, 8);
585	#ifdef VBOX_WITH_STATISTICS
586	AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
587	AssertCompileMemberAlignment(AC97STATE, StatBytesRead, 8);
588	AssertCompileMemberAlignment(AC97STATE, StatBytesWritten, 8);
589	#endif
590
591
592	/**
593	* The ring-3 AC'97 device state.
594	*/
595	typedef struct AC97STATER3
596	{
597	/** Array of AC'97 streams (parallel to AC97STATE:aStreams). */
598	AC97STREAMR3 aStreams[AC97_MAX_STREAMS];
599	/** R3 pointer to the device instance. */
600	PPDMDEVINSR3 pDevIns;
601	/** List of associated LUN drivers (AC97DRIVER). */
602	RTLISTANCHORR3 lstDrv;
603	/** The device's software mixer. */
604	R3PTRTYPE(PAUDIOMIXER) pMixer;
605	/** Audio sink for PCM output. */
606	R3PTRTYPE(PAUDMIXSINK) pSinkOut;
607	/** Audio sink for line input. */
608	R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
609	/** Audio sink for microphone input. */
610	R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
611	/** The base interface for LUN\#0. */
612	PDMIBASE IBase;
613	/** Debug settings. */
614	AC97STATEDEBUG Dbg;
615	} AC97STATER3;
616	AssertCompileMemberAlignment(AC97STATER3, aStreams, 8);
617	/** Pointer to the ring-3 AC'97 device state. */
618	typedef AC97STATER3 *PAC97STATER3;
619
620
621	/**
622	* Acquires the AC'97 lock.
623	*/
624	#define DEVAC97_LOCK(a_pDevIns, a_pThis) \
625	do { \
626	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
627	AssertRC(rcLock); \
628	} while (0)
629
630	/**
631	* Acquires the AC'97 lock or returns.
632	*/
633	# define DEVAC97_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
634	do { \
635	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, a_rcBusy); \
636	if (rcLock == VINF_SUCCESS) \
637	break; \
638	AssertRC(rcLock); \
639	return rcLock; \
640	} while (0)
641
642	/** Retrieves an attribute from a specific audio stream in RC. */
643	#define DEVAC97_CTX_SUFF_SD(a_Var, a_SD) CTX_SUFF(a_Var)[a_SD]
644
645	/**
646	* Releases the AC'97 lock.
647	*/
648	#define DEVAC97_UNLOCK(a_pDevIns, a_pThis) \
649	do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
650
651	/**
652	* Acquires the TM lock and AC'97 lock, returns on failure.
653	*
654	* @todo r=bird: Isn't this overkill for ring-0, only ring-3 access the timer
655	* from what I can tell (ichac97R3StreamTransferCalcNext,
656	* ichac97R3TimerSet, timer callback and state load).
657	*/
658	#define DEVAC97_LOCK_BOTH_RETURN(a_pDevIns, a_pThis, a_pStream, a_rcBusy) \
659	do { \
660	VBOXSTRICTRC rcLock = PDMDevHlpTimerLockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect, (a_rcBusy)); \
661	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
662	{ /* likely */ } \
663	else \
664	{ \
665	AssertRC(VBOXSTRICTRC_VAL(rcLock)); \
666	return rcLock; \
667	} \
668	} while (0)
669
670	/**
671	* Releases the AC'97 lock and TM lock.
672	*/
673	#define DEVAC97_UNLOCK_BOTH(a_pDevIns, a_pThis, a_pStream) \
674	PDMDevHlpTimerUnlockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect)
675
676	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
677
678
679	/*********************************************************************************************************************************
680	* Internal Functions *
681	*********************************************************************************************************************************/
682	#ifdef IN_RING3
683	static int ichac97R3StreamOpen(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce);
684	static int ichac97R3StreamClose(PAC97STREAM pStream);
685	static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC);
686	static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC);
687	static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC);
688	static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC);
689	static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
690	PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax);
691	static void ichac97R3StreamUpdate(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
692	PAC97STREAMR3 pStreamCC, bool fInTimer);
693
694	static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns);
695
696	static void ichac97R3MixerRemoveDrvStreams(PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir,
697	PDMAUDIODSTSRCUNION dstSrc);
698
699	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
700	static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC);
701	static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAMR3 pStreamCC);
702	static void ichac97R3StreamAsyncIOLock(PAC97STREAMR3 pStreamCC);
703	static void ichac97R3StreamAsyncIOUnlock(PAC97STREAMR3 pStreamCC);
704	/static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable); Unused /
705	# endif
706
707	DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD);
708	DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline);
709	#endif /* IN_RING3 */
710
711
712	/*********************************************************************************************************************************
713	* Global Variables *
714	*********************************************************************************************************************************/
715	#ifdef IN_RING3
716	/** NABM I/O port descriptions. */
717	static const IOMIOPORTDESC g_aNabmPorts[] =
718	{
719	{ "PCM IN - BDBAR", "PCM IN - BDBAR", NULL, NULL },
720	{ "", NULL, NULL, NULL },
721	{ "", NULL, NULL, NULL },
722	{ "", NULL, NULL, NULL },
723	{ "PCM IN - CIV", "PCM IN - CIV", NULL, NULL },
724	{ "PCM IN - LVI", "PCM IN - LIV", NULL, NULL },
725	{ "PCM IN - SR", "PCM IN - SR", NULL, NULL },
726	{ "", NULL, NULL, NULL },
727	{ "PCM IN - PICB", "PCM IN - PICB", NULL, NULL },
728	{ "", NULL, NULL, NULL },
729	{ "PCM IN - PIV", "PCM IN - PIV", NULL, NULL },
730	{ "PCM IN - CR", "PCM IN - CR", NULL, NULL },
731	{ "", NULL, NULL, NULL },
732	{ "", NULL, NULL, NULL },
733	{ "", NULL, NULL, NULL },
734	{ "", NULL, NULL, NULL },
735
736	{ "PCM OUT - BDBAR", "PCM OUT - BDBAR", NULL, NULL },
737	{ "", NULL, NULL, NULL },
738	{ "", NULL, NULL, NULL },
739	{ "", NULL, NULL, NULL },
740	{ "PCM OUT - CIV", "PCM OUT - CIV", NULL, NULL },
741	{ "PCM OUT - LVI", "PCM OUT - LIV", NULL, NULL },
742	{ "PCM OUT - SR", "PCM OUT - SR", NULL, NULL },
743	{ "", NULL, NULL, NULL },
744	{ "PCM OUT - PICB", "PCM OUT - PICB", NULL, NULL },
745	{ "", NULL, NULL, NULL },
746	{ "PCM OUT - PIV", "PCM OUT - PIV", NULL, NULL },
747	{ "PCM OUT - CR", "PCM IN - CR", NULL, NULL },
748	{ "", NULL, NULL, NULL },
749	{ "", NULL, NULL, NULL },
750	{ "", NULL, NULL, NULL },
751	{ "", NULL, NULL, NULL },
752
753	{ "MIC IN - BDBAR", "MIC IN - BDBAR", NULL, NULL },
754	{ "", NULL, NULL, NULL },
755	{ "", NULL, NULL, NULL },
756	{ "", NULL, NULL, NULL },
757	{ "MIC IN - CIV", "MIC IN - CIV", NULL, NULL },
758	{ "MIC IN - LVI", "MIC IN - LIV", NULL, NULL },
759	{ "MIC IN - SR", "MIC IN - SR", NULL, NULL },
760	{ "", NULL, NULL, NULL },
761	{ "MIC IN - PICB", "MIC IN - PICB", NULL, NULL },
762	{ "", NULL, NULL, NULL },
763	{ "MIC IN - PIV", "MIC IN - PIV", NULL, NULL },
764	{ "MIC IN - CR", "MIC IN - CR", NULL, NULL },
765	{ "GLOB CNT", "GLOB CNT", NULL, NULL },
766	{ "", NULL, NULL, NULL },
767	{ "", NULL, NULL, NULL },
768	{ "", NULL, NULL, NULL },
769
770	{ "GLOB STA", "GLOB STA", NULL, NULL },
771	{ "", NULL, NULL, NULL },
772	{ "", NULL, NULL, NULL },
773	{ "", NULL, NULL, NULL },
774	{ "CAS", "CAS", NULL, NULL },
775	{ NULL, NULL, NULL, NULL },
776	};
777
778	/** @name Source indices
779	* @{ */
780	#define AC97SOUNDSOURCE_PI_INDEX 0 /*< PCM in /
781	#define AC97SOUNDSOURCE_PO_INDEX 1 /*< PCM out /
782	#define AC97SOUNDSOURCE_MC_INDEX 2 /*< Mic in /
783	#define AC97SOUNDSOURCE_MAX 3 /*< Max sound sources. /
784	/** @} */
785
786	/** Port number (offset into NABM BAR) to stream index. */
787	#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
788	/** Port number (offset into NABM BAR) to stream index, but no masking. */
789	#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
790
791	/** @name Stream offsets
792	* @{ */
793	#define AC97_NABM_OFF_BDBAR 0x0 /*< Buffer Descriptor Base Address /
794	#define AC97_NABM_OFF_CIV 0x4 /*< Current Index Value /
795	#define AC97_NABM_OFF_LVI 0x5 /*< Last Valid Index /
796	#define AC97_NABM_OFF_SR 0x6 /*< Status Register /
797	#define AC97_NABM_OFF_PICB 0x8 /*< Position in Current Buffer /
798	#define AC97_NABM_OFF_PIV 0xa /*< Prefetched Index Value /
799	#define AC97_NABM_OFF_CR 0xb /*< Control Register /
800	#define AC97_NABM_OFF_MASK 0xf /*< Mask for getting the the per-stream register. /
801	/** @} */
802
803	#endif
804
805
806
807	static void ichac97WarmReset(PAC97STATE pThis)
808	{
809	NOREF(pThis);
810	}
811
812	static void ichac97ColdReset(PAC97STATE pThis)
813	{
814	NOREF(pThis);
815	}
816
817
818	#ifdef IN_RING3
819
820	/**
821	* Retrieves the audio mixer sink of a corresponding AC'97 stream index.
822	*
823	* @returns Pointer to audio mixer sink if found, or NULL if not found / invalid.
824	* @param pThisCC The ring-3 AC'97 state.
825	* @param uIndex Stream index to get audio mixer sink for.
826	*/
827	DECLINLINE(PAUDMIXSINK) ichac97R3IndexToSink(PAC97STATER3 pThisCC, uint8_t uIndex)
828	{
829	switch (uIndex)
830	{
831	case AC97SOUNDSOURCE_PI_INDEX: return pThisCC->pSinkLineIn;
832	case AC97SOUNDSOURCE_PO_INDEX: return pThisCC->pSinkOut;
833	case AC97SOUNDSOURCE_MC_INDEX: return pThisCC->pSinkMicIn;
834	default:
835	AssertMsgFailedReturn(("Wrong index %RU8\n", uIndex), NULL);
836	}
837	}
838
839	/**
840	* Fetches the current BDLE (Buffer Descriptor List Entry) of an AC'97 audio stream.
841	*
842	* @returns IPRT status code.
843	* @param pDevIns The device instance.
844	* @param pStream AC'97 stream to fetch BDLE for.
845	*
846	* @remark Uses CIV as BDLE index.
847	*/
848	static void ichac97R3StreamFetchBDLE(PPDMDEVINS pDevIns, PAC97STREAM pStream)
849	{
850	PAC97BMREGS pRegs = &pStream->Regs;
851
852	AC97BDLE BDLE;
853	PDMDevHlpPCIPhysRead(pDevIns, pRegs->bdbar + pRegs->civ * sizeof(AC97BDLE), &BDLE, sizeof(AC97BDLE));
854	pRegs->bd_valid = 1;
855	# ifndef RT_LITTLE_ENDIAN
856	# error "Please adapt the code (audio buffers are little endian)!"
857	# else
858	pRegs->bd.addr = RT_H2LE_U32(BDLE.addr & ~3);
859	pRegs->bd.ctl_len = RT_H2LE_U32(BDLE.ctl_len);
860	# endif
861	pRegs->picb = pRegs->bd.ctl_len & AC97_BD_LEN_MASK;
862	LogFlowFunc(("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes), bup=%RTbool, ioc=%RTbool\n",
863	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len >> 16,
864	pRegs->bd.ctl_len & AC97_BD_LEN_MASK,
865	(pRegs->bd.ctl_len & AC97_BD_LEN_MASK) << 1, /** @todo r=andy Assumes 16bit samples. */
866	RT_BOOL(pRegs->bd.ctl_len & AC97_BD_BUP),
867	RT_BOOL(pRegs->bd.ctl_len & AC97_BD_IOC)));
868	}
869
870	#endif /* IN_RING3 */
871
872	/**
873	* Updates the status register (SR) of an AC'97 audio stream.
874	*
875	* @param pDevIns The device instance.
876	* @param pThis The shared AC'97 state.
877	* @param pStream AC'97 stream to update SR for.
878	* @param new_sr New value for status register (SR).
879	*/
880	static void ichac97StreamUpdateSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr)
881	{
882	PAC97BMREGS pRegs = &pStream->Regs;
883
884	bool fSignal = false;
885	int iIRQL = 0;
886
887	uint32_t new_mask = new_sr & AC97_SR_INT_MASK;
888	uint32_t old_mask = pRegs->sr & AC97_SR_INT_MASK;
889
890	if (new_mask ^ old_mask)
891	{
892	/** @todo Is IRQ deasserted when only one of status bits is cleared? */
893	if (!new_mask)
894	{
895	fSignal = true;
896	iIRQL = 0;
897	}
898	else if ((new_mask & AC97_SR_LVBCI) && (pRegs->cr & AC97_CR_LVBIE))
899	{
900	fSignal = true;
901	iIRQL = 1;
902	}
903	else if ((new_mask & AC97_SR_BCIS) && (pRegs->cr & AC97_CR_IOCE))
904	{
905	fSignal = true;
906	iIRQL = 1;
907	}
908	}
909
910	pRegs->sr = new_sr;
911
912	LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n",
913	pRegs->sr & AC97_SR_BCIS, pRegs->sr & AC97_SR_LVBCI, pRegs->sr, fSignal, iIRQL));
914
915	if (fSignal)
916	{
917	static uint32_t const s_aMasks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT };
918	Assert(pStream->u8SD < AC97_MAX_STREAMS);
919	if (iIRQL)
920	pThis->glob_sta \|= s_aMasks[pStream->u8SD];
921	else
922	pThis->glob_sta &= ~s_aMasks[pStream->u8SD];
923
924	LogFlowFunc(("Setting IRQ level=%d\n", iIRQL));
925	PDMDevHlpPCISetIrq(pDevIns, 0, iIRQL);
926	}
927	}
928
929	/**
930	* Writes a new value to a stream's status register (SR).
931	*
932	* @param pDevIns The device instance.
933	* @param pThis The shared AC'97 device state.
934	* @param pStream Stream to update SR for.
935	* @param u32Val New value to set the stream's SR to.
936	*/
937	static void ichac97StreamWriteSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t u32Val)
938	{
939	PAC97BMREGS pRegs = &pStream->Regs;
940
941	Log3Func(("[SD%RU8] SR <- %#x (sr %#x)\n", pStream->u8SD, u32Val, pRegs->sr));
942
943	pRegs->sr \|= u32Val & ~(AC97_SR_RO_MASK \| AC97_SR_WCLEAR_MASK);
944	ichac97StreamUpdateSR(pDevIns, pThis, pStream, pRegs->sr & ~(u32Val & AC97_SR_WCLEAR_MASK));
945	}
946
947	#ifdef IN_RING3
948
949	/**
950	* Returns whether an AC'97 stream is enabled or not.
951	*
952	* @returns IPRT status code.
953	* @param pThisCC The ring-3 AC'97 device state.
954	* @param pStream Stream to return status for.
955	*/
956	static bool ichac97R3StreamIsEnabled(PAC97STATER3 pThisCC, PAC97STREAM pStream)
957	{
958	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
959	bool fIsEnabled = RT_BOOL(AudioMixerSinkGetStatus(pSink) & AUDMIXSINK_STS_RUNNING);
960
961	LogFunc(("[SD%RU8] fIsEnabled=%RTbool\n", pStream->u8SD, fIsEnabled));
962	return fIsEnabled;
963	}
964
965	/**
966	* Enables or disables an AC'97 audio stream.
967	*
968	* @returns IPRT status code.
969	* @param pThis The shared AC'97 state.
970	* @param pThisCC The ring-3 AC'97 state.
971	* @param pStream The AC'97 stream to enable or disable (shared
972	* state).
973	* @param pStreamCC The ring-3 stream state (matching to @a pStream).
974	* @param fEnable Whether to enable or disable the stream.
975	*
976	*/
977	static int ichac97R3StreamEnable(PAC97STATE pThis, PAC97STATER3 pThisCC,
978	PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fEnable)
979	{
980	ichac97R3StreamLock(pStreamCC);
981
982	int rc = VINF_SUCCESS;
983
984	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
985	if (fEnable)
986	rc = ichac97R3StreamAsyncIOCreate(pThis, pThisCC, pStream, pStreamCC);
987	if (RT_SUCCESS(rc))
988	ichac97R3StreamAsyncIOLock(pStreamCC);
989	# endif
990
991	if (fEnable)
992	{
993	if (pStreamCC->State.pCircBuf)
994	RTCircBufReset(pStreamCC->State.pCircBuf);
995
996	rc = ichac97R3StreamOpen(pThis, pThisCC, pStream, pStreamCC, false /* fForce */);
997
998	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
999	{ /* likely */ }
1000	else
1001	{
1002	if (!DrvAudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileStream))
1003	{
1004	int rc2 = DrvAudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileStream, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
1005	&pStreamCC->State.Cfg.Props);
1006	AssertRC(rc2);
1007	}
1008
1009	if (!DrvAudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileDMA))
1010	{
1011	int rc2 = DrvAudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileDMA, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
1012	&pStreamCC->State.Cfg.Props);
1013	AssertRC(rc2);
1014	}
1015	}
1016	}
1017	else
1018	rc = ichac97R3StreamClose(pStream);
1019
1020	if (RT_SUCCESS(rc))
1021	{
1022	/* First, enable or disable the stream and the stream's sink, if any. */
1023	rc = AudioMixerSinkCtl(ichac97R3IndexToSink(pThisCC, pStream->u8SD),
1024	fEnable ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE);
1025	}
1026
1027	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1028	ichac97R3StreamAsyncIOUnlock(pStreamCC);
1029	# endif
1030
1031	/* Make sure to leave the lock before (eventually) starting the timer. */
1032	ichac97R3StreamUnlock(pStreamCC);
1033
1034	LogFunc(("[SD%RU8] fEnable=%RTbool, rc=%Rrc\n", pStream->u8SD, fEnable, rc));
1035	return rc;
1036	}
1037
1038	/**
1039	* Resets an AC'97 stream.
1040	*
1041	* @param pThis The shared AC'97 state.
1042	* @param pStream The AC'97 stream to reset (shared).
1043	* @param pStreamCC The AC'97 stream to reset (ring-3).
1044	*/
1045	static void ichac97R3StreamReset(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1046	{
1047	ichac97R3StreamLock(pStreamCC);
1048
1049	LogFunc(("[SD%RU8]\n", pStream->u8SD));
1050
1051	if (pStreamCC->State.pCircBuf)
1052	RTCircBufReset(pStreamCC->State.pCircBuf);
1053
1054	PAC97BMREGS pRegs = &pStream->Regs;
1055
1056	pRegs->bdbar = 0;
1057	pRegs->civ = 0;
1058	pRegs->lvi = 0;
1059
1060	pRegs->picb = 0;
1061	pRegs->piv = 0;
1062	pRegs->cr = pRegs->cr & AC97_CR_DONT_CLEAR_MASK;
1063	pRegs->bd_valid = 0;
1064
1065	RT_ZERO(pThis->silence);
1066
1067	ichac97R3StreamUnlock(pStreamCC);
1068	}
1069
1070	/**
1071	* Creates an AC'97 audio stream.
1072	*
1073	* @returns IPRT status code.
1074	* @param pThisCC The ring-3 AC'97 state.
1075	* @param pStream The AC'97 stream to create (shared).
1076	* @param pStreamCC The AC'97 stream to create (ring-3).
1077	* @param u8SD Stream descriptor number to assign.
1078	*/
1079	static int ichac97R3StreamCreate(PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint8_t u8SD)
1080	{
1081	LogFunc(("[SD%RU8] pStream=%p\n", u8SD, pStream));
1082
1083	AssertReturn(u8SD < AC97_MAX_STREAMS, VERR_INVALID_PARAMETER);
1084	pStream->u8SD = u8SD;
1085	pStreamCC->u8SD = u8SD;
1086
1087	int rc = RTCritSectInit(&pStreamCC->State.CritSect);
1088	AssertRCReturn(rc, rc);
1089
1090	pStreamCC->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
1091
1092	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1093	{ /* likely */ }
1094	else
1095	{
1096	char szFile[64];
1097
1098	if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1099	RTStrPrintf(szFile, sizeof(szFile), "ac97StreamWriteSD%RU8", pStream->u8SD);
1100	else
1101	RTStrPrintf(szFile, sizeof(szFile), "ac97StreamReadSD%RU8", pStream->u8SD);
1102
1103	char szPath[RTPATH_MAX];
1104	int rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1105	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
1106	AssertRC(rc2);
1107	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileStream);
1108	AssertRC(rc2);
1109
1110	if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1111	RTStrPrintf(szFile, sizeof(szFile), "ac97DMAWriteSD%RU8", pStream->u8SD);
1112	else
1113	RTStrPrintf(szFile, sizeof(szFile), "ac97DMAReadSD%RU8", pStream->u8SD);
1114
1115	rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1116	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
1117	AssertRC(rc2);
1118
1119	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileDMA);
1120	AssertRC(rc2);
1121
1122	/* Delete stale debugging files from a former run. */
1123	DrvAudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileStream);
1124	DrvAudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileDMA);
1125	}
1126
1127	return rc;
1128	}
1129
1130	/**
1131	* Destroys an AC'97 audio stream.
1132	*
1133	* @returns IPRT status code.
1134	* @param pThis The shared AC'97 state.
1135	* @param pStream The AC'97 stream to destroy (shared).
1136	* @param pStreamCC The AC'97 stream to destroy (ring-3).
1137	*/
1138	static void ichac97R3StreamDestroy(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1139	{
1140	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
1141
1142	ichac97R3StreamClose(pStream);
1143
1144	int rc2 = RTCritSectDelete(&pStreamCC->State.CritSect);
1145	AssertRC(rc2);
1146
1147	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1148	rc2 = ichac97R3StreamAsyncIODestroy(pThis, pStreamCC);
1149	AssertRC(rc2);
1150	# else
1151	RT_NOREF(pThis);
1152	# endif
1153
1154	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1155	{ /* likely */ }
1156	else
1157	{
1158	DrvAudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileStream);
1159	pStreamCC->Dbg.Runtime.pFileStream = NULL;
1160
1161	DrvAudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileDMA);
1162	pStreamCC->Dbg.Runtime.pFileDMA = NULL;
1163	}
1164
1165	if (pStreamCC->State.pCircBuf)
1166	{
1167	RTCircBufDestroy(pStreamCC->State.pCircBuf);
1168	pStreamCC->State.pCircBuf = NULL;
1169	}
1170
1171	LogFlowFuncLeave();
1172	}
1173
1174	/**
1175	* Destroys all AC'97 audio streams of the device.
1176	*
1177	* @param pThis The shared AC'97 state.
1178	* @param pThisCC The ring-3 AC'97 state.
1179	*/
1180	static void ichac97R3StreamsDestroy(PAC97STATE pThis, PAC97STATER3 pThisCC)
1181	{
1182	LogFlowFuncEnter();
1183
1184	/*
1185	* Destroy all AC'97 streams.
1186	*/
1187	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
1188	ichac97R3StreamDestroy(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
1189
1190	/*
1191	* Destroy all sinks.
1192	*/
1193
1194	PDMAUDIODSTSRCUNION dstSrc;
1195	if (pThisCC->pSinkLineIn)
1196	{
1197	dstSrc.enmSrc = PDMAUDIORECSRC_LINE;
1198	ichac97R3MixerRemoveDrvStreams(pThisCC, pThisCC->pSinkLineIn, PDMAUDIODIR_IN, dstSrc);
1199
1200	AudioMixerSinkDestroy(pThisCC->pSinkLineIn);
1201	pThisCC->pSinkLineIn = NULL;
1202	}
1203
1204	if (pThisCC->pSinkMicIn)
1205	{
1206	dstSrc.enmSrc = PDMAUDIORECSRC_MIC;
1207	ichac97R3MixerRemoveDrvStreams(pThisCC, pThisCC->pSinkMicIn, PDMAUDIODIR_IN, dstSrc);
1208
1209	AudioMixerSinkDestroy(pThisCC->pSinkMicIn);
1210	pThisCC->pSinkMicIn = NULL;
1211	}
1212
1213	if (pThisCC->pSinkOut)
1214	{
1215	dstSrc.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
1216	ichac97R3MixerRemoveDrvStreams(pThisCC, pThisCC->pSinkOut, PDMAUDIODIR_OUT, dstSrc);
1217
1218	AudioMixerSinkDestroy(pThisCC->pSinkOut);
1219	pThisCC->pSinkOut = NULL;
1220	}
1221	}
1222
1223	/**
1224	* Writes audio data from a mixer sink into an AC'97 stream's DMA buffer.
1225	*
1226	* @returns IPRT status code.
1227	* @param pDstStreamCC The AC'97 stream to write to (ring-3).
1228	* @param pSrcMixSink Mixer sink to get audio data to write from.
1229	* @param cbToWrite Number of bytes to write.
1230	* @param pcbWritten Number of bytes written. Optional.
1231	*/
1232	static int ichac97R3StreamWrite(PAC97STREAMR3 pDstStreamCC, PAUDMIXSINK pSrcMixSink, uint32_t cbToWrite, uint32_t *pcbWritten)
1233	{
1234	AssertPtrReturn(pSrcMixSink, VERR_INVALID_POINTER);
1235	AssertReturn(cbToWrite > 0, VERR_INVALID_PARAMETER);
1236	/* pcbWritten is optional. */
1237
1238	PRTCIRCBUF pCircBuf = pDstStreamCC->State.pCircBuf;
1239	AssertPtr(pCircBuf);
1240
1241	uint32_t cbRead = 0;
1242
1243	void *pvDst;
1244	size_t cbDst;
1245	RTCircBufAcquireWriteBlock(pCircBuf, cbToWrite, &pvDst, &cbDst);
1246
1247	if (cbDst)
1248	{
1249	int rc2 = AudioMixerSinkRead(pSrcMixSink, AUDMIXOP_COPY, pvDst, (uint32_t)cbDst, &cbRead);
1250	AssertRC(rc2);
1251
1252	if (RT_LIKELY(!pDstStreamCC->Dbg.Runtime.fEnabled))
1253	{ /* likely */ }
1254	else
1255	DrvAudioHlpFileWrite(pDstStreamCC->Dbg.Runtime.pFileStream, pvDst, cbRead, 0 /* fFlags */);
1256	}
1257
1258	RTCircBufReleaseWriteBlock(pCircBuf, cbRead);
1259
1260	if (pcbWritten)
1261	*pcbWritten = cbRead;
1262
1263	return VINF_SUCCESS;
1264	}
1265
1266	/**
1267	* Reads audio data from an AC'97 stream's DMA buffer and writes into a specified mixer sink.
1268	*
1269	* @returns IPRT status code.
1270	* @param pSrcStreamCC AC'97 stream to read audio data from (ring-3).
1271	* @param pDstMixSink Mixer sink to write audio data to.
1272	* @param cbToRead Number of bytes to read.
1273	* @param pcbRead Number of bytes read. Optional.
1274	*/
1275	static int ichac97R3StreamRead(PAC97STREAMR3 pSrcStreamCC, PAUDMIXSINK pDstMixSink, uint32_t cbToRead, uint32_t *pcbRead)
1276	{
1277	AssertPtrReturn(pDstMixSink, VERR_INVALID_POINTER);
1278	AssertReturn(cbToRead > 0, VERR_INVALID_PARAMETER);
1279	/* pcbRead is optional. */
1280
1281	PRTCIRCBUF pCircBuf = pSrcStreamCC->State.pCircBuf;
1282	AssertPtr(pCircBuf);
1283
1284	void *pvSrc;
1285	size_t cbSrc;
1286
1287	int rc = VINF_SUCCESS;
1288
1289	uint32_t cbReadTotal = 0;
1290	uint32_t cbLeft = RT_MIN(cbToRead, (uint32_t)RTCircBufUsed(pCircBuf));
1291
1292	while (cbLeft)
1293	{
1294	uint32_t cbWritten = 0;
1295
1296	RTCircBufAcquireReadBlock(pCircBuf, cbLeft, &pvSrc, &cbSrc);
1297
1298	if (cbSrc)
1299	{
1300	if (RT_LIKELY(!pSrcStreamCC->Dbg.Runtime.fEnabled))
1301	{ /* likely */ }
1302	else
1303	DrvAudioHlpFileWrite(pSrcStreamCC->Dbg.Runtime.pFileStream, pvSrc, cbSrc, 0 /* fFlags */);
1304
1305	rc = AudioMixerSinkWrite(pDstMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbWritten);
1306	AssertRC(rc);
1307
1308	Assert(cbSrc >= cbWritten);
1309	Log3Func(("[SD%RU8] %RU32/%zu bytes read\n", pSrcStreamCC->u8SD, cbWritten, cbSrc));
1310	}
1311
1312	RTCircBufReleaseReadBlock(pCircBuf, cbWritten);
1313
1314	if ( !cbWritten /* Nothing written? */
1315	\|\| RT_FAILURE(rc))
1316	break;
1317
1318	Assert(cbLeft >= cbWritten);
1319	cbLeft -= cbWritten;
1320
1321	cbReadTotal += cbWritten;
1322	}
1323
1324	if (pcbRead)
1325	*pcbRead = cbReadTotal;
1326
1327	return rc;
1328	}
1329
1330	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1331
1332	/**
1333	* Asynchronous I/O thread for an AC'97 stream.
1334	* This will do the heavy lifting work for us as soon as it's getting notified by another thread.
1335	*
1336	* @returns IPRT status code.
1337	* @param hThreadSelf Thread handle.
1338	* @param pvUser User argument. Must be of type PAC97STREAMTHREADCTX.
1339	*/
1340	static DECLCALLBACK(int) ichac97R3StreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
1341	{
1342	PAC97STREAMTHREADCTX pCtx = (PAC97STREAMTHREADCTX)pvUser;
1343	AssertPtr(pCtx);
1344
1345	PAC97STATE pThis = pCtx->pThis;
1346	AssertPtr(pThis);
1347
1348	PAC97STATER3 pThisCC = pCtx->pThisCC;
1349	AssertPtr(pThisCC);
1350
1351	PAC97STREAM pStream = pCtx->pStream;
1352	AssertPtr(pStream);
1353
1354	PAC97STREAMR3 pStreamCC = pCtx->pStreamCC;
1355	AssertPtr(pStreamCC);
1356
1357	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1358
1359	ASMAtomicXchgBool(&pAIO->fStarted, true);
1360
1361	RTThreadUserSignal(hThreadSelf);
1362
1363	LogFunc(("[SD%RU8] Started\n", pStream->u8SD));
1364
1365	for (;;)
1366	{
1367	Log2Func(("[SD%RU8] Waiting ...\n", pStream->u8SD));
1368
1369	int rc2 = RTSemEventWait(pAIO->Event, RT_INDEFINITE_WAIT);
1370	if (RT_FAILURE(rc2))
1371	break;
1372
1373	if (ASMAtomicReadBool(&pAIO->fShutdown))
1374	break;
1375
1376	rc2 = RTCritSectEnter(&pAIO->CritSect);
1377	if (RT_SUCCESS(rc2))
1378	{
1379	if (!pAIO->fEnabled)
1380	{
1381	RTCritSectLeave(&pAIO->CritSect);
1382	continue;
1383	}
1384
1385	ichac97R3StreamUpdate(pThisCC->pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fInTimer */);
1386
1387	int rc3 = RTCritSectLeave(&pAIO->CritSect);
1388	AssertRC(rc3);
1389	}
1390
1391	AssertRC(rc2);
1392	}
1393
1394	LogFunc(("[SD%RU8] Ended\n", pStream->u8SD));
1395
1396	ASMAtomicXchgBool(&pAIO->fStarted, false);
1397
1398	RTMemFree(pCtx);
1399	pCtx = NULL;
1400
1401	return VINF_SUCCESS;
1402	}
1403
1404	/**
1405	* Creates the async I/O thread for a specific AC'97 audio stream.
1406	*
1407	* @returns IPRT status code.
1408	* @param pThis The shared AC'97 state (shared).
1409	* @param pThisCC The shared AC'97 state (ring-3).
1410	* @param pStream AC'97 audio stream to create the async I/O thread for (shared).
1411	* @param pStreamCC AC'97 audio stream to create the async I/O thread for (ring-3).
1412	*/
1413	static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1414	{
1415	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1416
1417	int rc;
1418
1419	if (!ASMAtomicReadBool(&pAIO->fStarted))
1420	{
1421	pAIO->fShutdown = false;
1422	pAIO->fEnabled = true; /* Enabled by default. */
1423
1424	rc = RTSemEventCreate(&pAIO->Event);
1425	if (RT_SUCCESS(rc))
1426	{
1427	rc = RTCritSectInit(&pAIO->CritSect);
1428	if (RT_SUCCESS(rc))
1429	{
1430	/** @todo r=bird:
1431	* Why aren't this code using the PDM threads (PDMDevHlpThreadCreate)?
1432	* They would help you with managing stuff like VM suspending, resuming
1433	* and powering off.
1434	*
1435	* Finally, just create the threads at construction time. */
1436	PAC97STREAMTHREADCTX pCtx = (PAC97STREAMTHREADCTX)RTMemAllocZ(sizeof(AC97STREAMTHREADCTX));
1437	if (pCtx)
1438	{
1439	pCtx->pStream = pStream;
1440	pCtx->pStreamCC = pStreamCC;
1441	pCtx->pThis = pThis;
1442	pCtx->pThisCC = pThisCC;
1443
1444	rc = RTThreadCreateF(&pAIO->Thread, ichac97R3StreamAsyncIOThread, pCtx,
1445	0, RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, "ac97AIO%RU8", pStreamCC->u8SD);
1446	if (RT_SUCCESS(rc))
1447	rc = RTThreadUserWait(pAIO->Thread, 30 * 1000 /* 30s timeout */);
1448	}
1449	else
1450	rc = VERR_NO_MEMORY;
1451	}
1452	}
1453	}
1454	else
1455	rc = VINF_SUCCESS;
1456
1457	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamCC->u8SD, rc));
1458	return rc;
1459	}
1460
1461	/**
1462	* Lets the stream's async I/O thread know that there is some data to process.
1463	*
1464	* @returns IPRT status code.
1465	* @param pStreamCC The AC'97 stream to notify async I/O thread
1466	* for (ring-3).
1467	*/
1468	static int ichac97R3StreamAsyncIONotify(PAC97STREAMR3 pStreamCC)
1469	{
1470	LogFunc(("[SD%RU8]\n", pStreamCC->u8SD));
1471	return RTSemEventSignal(pStreamCC->State.AIO.Event);
1472	}
1473
1474	/**
1475	* Destroys the async I/O thread of a specific AC'97 audio stream.
1476	*
1477	* @returns IPRT status code.
1478	* @param pThis The shared AC'97 state.
1479	* @param pStreamCC AC'97 audio stream to destroy the async I/O thread for.
1480	*/
1481	static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAMR3 pStreamR3)
1482	{
1483	RT_NOREF(pThis);
1484
1485	PAC97STREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
1486
1487	if (!ASMAtomicReadBool(&pAIO->fStarted))
1488	return VINF_SUCCESS;
1489
1490	ASMAtomicWriteBool(&pAIO->fShutdown, true);
1491
1492	int rc = ichac97R3StreamAsyncIONotify(pStreamR3);
1493	AssertRC(rc);
1494
1495	int rcThread;
1496	rc = RTThreadWait(pAIO->Thread, 30 * 1000 /* 30s timeout */, &rcThread);
1497	LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
1498
1499	if (RT_SUCCESS(rc))
1500	{
1501	rc = RTCritSectDelete(&pAIO->CritSect);
1502	AssertRC(rc);
1503
1504	rc = RTSemEventDestroy(pAIO->Event);
1505	AssertRC(rc);
1506
1507	pAIO->fStarted = false;
1508	pAIO->fShutdown = false;
1509	pAIO->fEnabled = false;
1510	}
1511
1512	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamR3->u8SD, rc));
1513	return rc;
1514	}
1515
1516	/**
1517	* Locks the async I/O thread of a specific AC'97 audio stream.
1518	*
1519	* @param pStreamCC AC'97 stream to lock async I/O thread for.
1520	*/
1521	static void ichac97R3StreamAsyncIOLock(PAC97STREAMR3 pStreamCC)
1522	{
1523	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1524
1525	if (!ASMAtomicReadBool(&pAIO->fStarted))
1526	return;
1527
1528	int rc2 = RTCritSectEnter(&pAIO->CritSect);
1529	AssertRC(rc2);
1530	}
1531
1532	/**
1533	* Unlocks the async I/O thread of a specific AC'97 audio stream.
1534	*
1535	* @param pStreamCC AC'97 stream to unlock async I/O thread for.
1536	*/
1537	static void ichac97R3StreamAsyncIOUnlock(PAC97STREAMR3 pStreamCC)
1538	{
1539	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1540
1541	if (!ASMAtomicReadBool(&pAIO->fStarted))
1542	return;
1543
1544	int rc2 = RTCritSectLeave(&pAIO->CritSect);
1545	AssertRC(rc2);
1546	}
1547
1548	#if 0 /* Unused */
1549	/**
1550	* Enables (resumes) or disables (pauses) the async I/O thread.
1551	*
1552	* @param pStream AC'97 stream to enable/disable async I/O thread for.
1553	* @param fEnable Whether to enable or disable the I/O thread.
1554	*
1555	* @remarks Does not do locking.
1556	*/
1557	static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable)
1558	{
1559	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1560	ASMAtomicXchgBool(&pAIO->fEnabled, fEnable);
1561	}
1562	#endif
1563	# endif /* VBOX_WITH_AUDIO_AC97_ASYNC_IO */
1564
1565	# ifdef LOG_ENABLED
1566	static void ichac97R3BDLEDumpAll(PPDMDEVINS pDevIns, uint64_t u64BDLBase, uint16_t cBDLE)
1567	{
1568	LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
1569	if (!u64BDLBase)
1570	return;
1571
1572	uint32_t cbBDLE = 0;
1573	for (uint16_t i = 0; i < cBDLE; i++)
1574	{
1575	AC97BDLE BDLE;
1576	PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase + i * sizeof(AC97BDLE), &BDLE, sizeof(AC97BDLE));
1577
1578	# ifndef RT_LITTLE_ENDIAN
1579	# error "Please adapt the code (audio buffers are little endian)!"
1580	# else
1581	BDLE.addr = RT_H2LE_U32(BDLE.addr & ~3);
1582	BDLE.ctl_len = RT_H2LE_U32(BDLE.ctl_len);
1583	#endif
1584	LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32 [%RU32 bytes], bup:%RTbool, ioc:%RTbool)\n",
1585	i, BDLE.addr,
1586	BDLE.ctl_len & AC97_BD_LEN_MASK,
1587	(BDLE.ctl_len & AC97_BD_LEN_MASK) << 1, /** @todo r=andy Assumes 16bit samples. */
1588	RT_BOOL(BDLE.ctl_len & AC97_BD_BUP),
1589	RT_BOOL(BDLE.ctl_len & AC97_BD_IOC)));
1590
1591	cbBDLE += (BDLE.ctl_len & AC97_BD_LEN_MASK) << 1; /** @todo r=andy Ditto. */
1592	}
1593
1594	LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
1595	}
1596	# endif /* LOG_ENABLED */
1597
1598	/**
1599	* Updates an AC'97 stream by doing its required data transfers.
1600	* The host sink(s) set the overall pace.
1601	*
1602	* This routine is called by both, the synchronous and the asynchronous
1603	* (VBOX_WITH_AUDIO_AC97_ASYNC_IO), implementations.
1604	*
1605	* When running synchronously, the device DMA transfers and the mixer sink
1606	* processing is within the device timer.
1607	*
1608	* When running asynchronously, only the device DMA transfers are done in the
1609	* device timer, whereas the mixer sink processing then is done in the stream's
1610	* own async I/O thread. This thread also will call this function
1611	* (with fInTimer set to @c false).
1612	*
1613	* @param pDevIns The device instance.
1614	* @param pThis The shared AC'97 state.
1615	* @param pThisCC The ring-3 AC'97 state.
1616	* @param pStream The AC'97 stream to update (shared).
1617	* @param pStreamCC The AC'97 stream to update (ring-3).
1618	* @param fInTimer Whether to this function was called from the timer
1619	* context or an asynchronous I/O stream thread (if supported).
1620	*/
1621	static void ichac97R3StreamUpdate(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
1622	PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fInTimer)
1623	{
1624	RT_NOREF(fInTimer);
1625
1626	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
1627	AssertPtr(pSink);
1628
1629	if (!AudioMixerSinkIsActive(pSink)) /* No sink available? Bail out. */
1630	return;
1631
1632	int rc2;
1633
1634	if (pStreamCC->State.Cfg.enmDir == PDMAUDIODIR_OUT) /* Output (SDO). */
1635	{
1636	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1637	if (fInTimer)
1638	# endif
1639	{
1640	const uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1641	if (cbStreamFree)
1642	{
1643	Log3Func(("[SD%RU8] PICB=%zu (%RU64ms), cbFree=%zu (%RU64ms), cbTransferChunk=%zu (%RU64ms)\n",
1644	pStream->u8SD,
1645	(pStream->Regs.picb << 1), PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, pStream->Regs.picb << 1),
1646	cbStreamFree, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, cbStreamFree),
1647	pStreamCC->State.cbTransferChunk, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, pStreamCC->State.cbTransferChunk)));
1648
1649	/* Do the DMA transfer. */
1650	rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC,
1651	RT_MIN(pStreamCC->State.cbTransferChunk, cbStreamFree));
1652	AssertRC(rc2);
1653
1654	pStreamCC->State.tsLastUpdateNs = RTTimeNanoTS();
1655	}
1656	}
1657
1658	Log3Func(("[SD%RU8] fInTimer=%RTbool\n", pStream->u8SD, fInTimer));
1659
1660	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1661	rc2 = ichac97R3StreamAsyncIONotify(pStreamCC);
1662	AssertRC(rc2);
1663	# endif
1664
1665	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1666	if (!fInTimer) /* In async I/O thread */
1667	{
1668	# endif
1669	const uint32_t cbSinkWritable = AudioMixerSinkGetWritable(pSink);
1670	const uint32_t cbStreamReadable = ichac97R3StreamGetUsed(pStreamCC);
1671	const uint32_t cbToReadFromStream = RT_MIN(cbStreamReadable, cbSinkWritable);
1672
1673	Log3Func(("[SD%RU8] cbSinkWritable=%RU32, cbStreamReadable=%RU32\n", pStream->u8SD, cbSinkWritable, cbStreamReadable));
1674
1675	if (cbToReadFromStream)
1676	{
1677	/* Read (guest output) data and write it to the stream's sink. */
1678	rc2 = ichac97R3StreamRead(pStreamCC, pSink, cbToReadFromStream, NULL /* pcbRead */);
1679	AssertRC(rc2);
1680	}
1681	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1682	}
1683	#endif
1684	/* When running synchronously, update the associated sink here.
1685	* Otherwise this will be done in the async I/O thread. */
1686	rc2 = AudioMixerSinkUpdate(pSink);
1687	AssertRC(rc2);
1688	}
1689	else /* Input (SDI). */
1690	{
1691	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1692	if (!fInTimer)
1693	{
1694	# endif
1695	rc2 = AudioMixerSinkUpdate(pSink);
1696	AssertRC(rc2);
1697
1698	/* Is the sink ready to be read (host input data) from? If so, by how much? */
1699	uint32_t cbSinkReadable = AudioMixerSinkGetReadable(pSink);
1700
1701	/* How much (guest input) data is available for writing at the moment for the AC'97 stream? */
1702	uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1703
1704	Log3Func(("[SD%RU8] cbSinkReadable=%RU32, cbStreamFree=%RU32\n", pStream->u8SD, cbSinkReadable, cbStreamFree));
1705
1706	/* Do not read more than the sink can provide at the moment.
1707	* The host sets the overall pace. */
1708	if (cbSinkReadable > cbStreamFree)
1709	cbSinkReadable = cbStreamFree;
1710
1711	if (cbSinkReadable)
1712	{
1713	/* Write (guest input) data to the stream which was read from stream's sink before. */
1714	rc2 = ichac97R3StreamWrite(pStreamCC, pSink, cbSinkReadable, NULL /* pcbWritten */);
1715	AssertRC(rc2);
1716	}
1717	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1718	}
1719	else /* fInTimer */
1720	{
1721	# endif
1722
1723	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1724	const uint64_t tsNowNs = RTTimeNanoTS();
1725	if (tsNowNs - pStreamCC->State.tsLastUpdateNs >= pStreamCC->State.Cfg.Device.cMsSchedulingHint * RT_NS_1MS)
1726	{
1727	rc2 = ichac97R3StreamAsyncIONotify(pStreamCC);
1728	AssertRC(rc2);
1729
1730	pStreamCC->State.tsLastUpdateNs = tsNowNs;
1731	}
1732	# endif
1733
1734	const uint32_t cbStreamUsed = ichac97R3StreamGetUsed(pStreamCC);
1735	if (cbStreamUsed)
1736	{
1737	/* When running synchronously, do the DMA data transfers here.
1738	* Otherwise this will be done in the stream's async I/O thread. */
1739	rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC, cbStreamUsed);
1740	AssertRC(rc2);
1741	}
1742	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1743	}
1744	# endif
1745	}
1746	}
1747
1748	#endif /* IN_RING3 */
1749
1750	/**
1751	* Sets a AC'97 mixer control to a specific value.
1752	*
1753	* @returns IPRT status code.
1754	* @param pThis The shared AC'97 state.
1755	* @param uMixerIdx Mixer control to set value for.
1756	* @param uVal Value to set.
1757	*/
1758	static void ichac97MixerSet(PAC97STATE pThis, uint8_t uMixerIdx, uint16_t uVal)
1759	{
1760	AssertMsgReturnVoid(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1761	("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)));
1762
1763	LogRel2(("AC97: Setting mixer index #%RU8 to %RU16 (%RU8 %RU8)\n",
1764	uMixerIdx, uVal, RT_HI_U8(uVal), RT_LO_U8(uVal)));
1765
1766	pThis->mixer_data[uMixerIdx + 0] = RT_LO_U8(uVal);
1767	pThis->mixer_data[uMixerIdx + 1] = RT_HI_U8(uVal);
1768	}
1769
1770	/**
1771	* Gets a value from a specific AC'97 mixer control.
1772	*
1773	* @returns Retrieved mixer control value.
1774	* @param pThis The shared AC'97 state.
1775	* @param uMixerIdx Mixer control to get value for.
1776	*/
1777	static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t uMixerIdx)
1778	{
1779	AssertMsgReturn(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1780	("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)),
1781	UINT16_MAX);
1782	return RT_MAKE_U16(pThis->mixer_data[uMixerIdx + 0], pThis->mixer_data[uMixerIdx + 1]);
1783	}
1784
1785	#ifdef IN_RING3
1786
1787	/**
1788	* Retrieves a specific driver stream of a AC'97 driver.
1789	*
1790	* @returns Pointer to driver stream if found, or NULL if not found.
1791	* @param pDrv Driver to retrieve driver stream for.
1792	* @param enmDir Stream direction to retrieve.
1793	* @param dstSrc Stream destination / source to retrieve.
1794	*/
1795	static PAC97DRIVERSTREAM ichac97R3MixerGetDrvStream(PAC97DRIVER pDrv, PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc)
1796	{
1797	PAC97DRIVERSTREAM pDrvStream = NULL;
1798
1799	if (enmDir == PDMAUDIODIR_IN)
1800	{
1801	LogFunc(("enmRecSource=%d\n", dstSrc.enmSrc));
1802
1803	switch (dstSrc.enmSrc)
1804	{
1805	case PDMAUDIORECSRC_LINE:
1806	pDrvStream = &pDrv->LineIn;
1807	break;
1808	case PDMAUDIORECSRC_MIC:
1809	pDrvStream = &pDrv->MicIn;
1810	break;
1811	default:
1812	AssertFailed();
1813	break;
1814	}
1815	}
1816	else if (enmDir == PDMAUDIODIR_OUT)
1817	{
1818	LogFunc(("enmPlaybackDest=%d\n", dstSrc.enmDst));
1819
1820	switch (dstSrc.enmDst)
1821	{
1822	case PDMAUDIOPLAYBACKDST_FRONT:
1823	pDrvStream = &pDrv->Out;
1824	break;
1825	default:
1826	AssertFailed();
1827	break;
1828	}
1829	}
1830	else
1831	AssertFailed();
1832
1833	return pDrvStream;
1834	}
1835
1836	/**
1837	* Adds a driver stream to a specific mixer sink.
1838	*
1839	* @returns IPRT status code.
1840	* @param pMixSink Mixer sink to add driver stream to.
1841	* @param pCfg Stream configuration to use.
1842	* @param pDrv Driver stream to add.
1843	*/
1844	static int ichac97R3MixerAddDrvStream(PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PAC97DRIVER pDrv)
1845	{
1846	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1847
1848	PPDMAUDIOSTREAMCFG pStreamCfg = PDMAudioStrmCfgDup(pCfg);
1849	if (!pStreamCfg)
1850	return VERR_NO_MEMORY;
1851
1852	if (!RTStrPrintf(pStreamCfg->szName, sizeof(pStreamCfg->szName), "%s", pCfg->szName))
1853	{
1854	PDMAudioStrmCfgFree(pStreamCfg);
1855	return VERR_BUFFER_OVERFLOW;
1856	}
1857
1858	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
1859
1860	int rc;
1861
1862	PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, pStreamCfg->enmDir, pStreamCfg->u);
1863	if (pDrvStream)
1864	{
1865	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
1866
1867	PAUDMIXSTREAM pMixStrm;
1868	rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
1869	LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1870	if (RT_SUCCESS(rc))
1871	{
1872	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
1873	LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1874	if (RT_SUCCESS(rc))
1875	{
1876	/* If this is an input stream, always set the latest (added) stream
1877	* as the recording source. */
1878	/** @todo Make the recording source dynamic (CFGM?). */
1879	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
1880	{
1881	PDMAUDIOBACKENDCFG Cfg;
1882	rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
1883	if (RT_SUCCESS(rc))
1884	{
1885	if (Cfg.cMaxStreamsIn) /* At least one input source available? */
1886	{
1887	rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
1888	LogFlowFunc(("LUN#%RU8: Recording source for '%s' -> '%s', rc=%Rrc\n",
1889	pDrv->uLUN, pStreamCfg->szName, Cfg.szName, rc));
1890
1891	if (RT_SUCCESS(rc))
1892	LogRel2(("AC97: Set recording source for '%s' to '%s'\n", pStreamCfg->szName, Cfg.szName));
1893	}
1894	else
1895	LogRel(("AC97: Backend '%s' currently is not offering any recording source for '%s'\n",
1896	Cfg.szName, pStreamCfg->szName));
1897	}
1898	else if (RT_FAILURE(rc))
1899	LogFunc(("LUN#%RU8: Unable to retrieve backend configuratio for '%s', rc=%Rrc\n",
1900	pDrv->uLUN, pStreamCfg->szName, rc));
1901	}
1902	/** @todo r=bird: see below. */
1903	if (RT_FAILURE(rc))
1904	AudioMixerSinkRemoveStream(pMixSink, pMixStrm);
1905	}
1906	/** @todo r=bird: I've added this destroy stuff here, because if it looks as if
1907	* you just drop the stream if the AudioMixerSinkAddStream fails for some
1908	* reason. This is definitely true if AudioMixerSinkSetRecordingSource fails
1909	* above, because it leads to duplicate statistics when starting XP with ICH97
1910	* and VRDP enabled. Looks like the VRDP line-in fails with
1911	* VERR_AUDIO_STREAM_NOT_READY when configured for 8000HZ, then it asserts in
1912	* STAM when 48000Hz is configured right afterwards. */
1913	if (RT_FAILURE(rc))
1914	AudioMixerStreamDestroy(pMixStrm);
1915	}
1916
1917	if (RT_SUCCESS(rc))
1918	pDrvStream->pMixStrm = pMixStrm;
1919	}
1920	else
1921	rc = VERR_INVALID_PARAMETER;
1922
1923	PDMAudioStrmCfgFree(pStreamCfg);
1924
1925	LogFlowFuncLeaveRC(rc);
1926	return rc;
1927	}
1928
1929	/**
1930	* Adds all current driver streams to a specific mixer sink.
1931	*
1932	* @returns IPRT status code.
1933	* @param pThisCC The ring-3 AC'97 state.
1934	* @param pMixSink Mixer sink to add stream to.
1935	* @param pCfg Stream configuration to use.
1936	*/
1937	static int ichac97R3MixerAddDrvStreams(PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
1938	{
1939	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1940
1941	if (!DrvAudioHlpStreamCfgIsValid(pCfg))
1942	return VERR_INVALID_PARAMETER;
1943
1944	int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
1945	if (RT_FAILURE(rc))
1946	return rc;
1947
1948	PAC97DRIVER pDrv;
1949	RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
1950	{
1951	int rc2 = ichac97R3MixerAddDrvStream(pMixSink, pCfg, pDrv);
1952	if (RT_FAILURE(rc2))
1953	LogFunc(("Attaching stream failed with %Rrc\n", rc2));
1954
1955	/* Do not pass failure to rc here, as there might be drivers which aren't
1956	* configured / ready yet. */
1957	}
1958
1959	LogFlowFuncLeaveRC(rc);
1960	return rc;
1961	}
1962
1963	/**
1964	* Adds a specific AC'97 driver to the driver chain.
1965	*
1966	* @return IPRT status code.
1967	* @param pThisCC The ring-3 AC'97 device state.
1968	* @param pDrv The AC'97 driver to add.
1969	*/
1970	static int ichac97R3MixerAddDrv(PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
1971	{
1972	int rc = VINF_SUCCESS;
1973
1974	if (DrvAudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg))
1975	rc = ichac97R3MixerAddDrvStream(pThisCC->pSinkLineIn, &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg, pDrv);
1976
1977	if (DrvAudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg))
1978	{
1979	int rc2 = ichac97R3MixerAddDrvStream(pThisCC->pSinkOut, &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg, pDrv);
1980	if (RT_SUCCESS(rc))
1981	rc = rc2;
1982	}
1983
1984	if (DrvAudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg))
1985	{
1986	int rc2 = ichac97R3MixerAddDrvStream(pThisCC->pSinkMicIn, &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg, pDrv);
1987	if (RT_SUCCESS(rc))
1988	rc = rc2;
1989	}
1990
1991	return rc;
1992	}
1993
1994	/**
1995	* Removes a specific AC'97 driver from the driver chain and destroys its
1996	* associated streams.
1997	*
1998	* @param pThisCC The ring-3 AC'97 device state.
1999	* @param pDrv AC'97 driver to remove.
2000	*/
2001	static void ichac97R3MixerRemoveDrv(PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
2002	{
2003	if (pDrv->MicIn.pMixStrm)
2004	{
2005	if (AudioMixerSinkGetRecordingSource(pThisCC->pSinkMicIn) == pDrv->MicIn.pMixStrm)
2006	AudioMixerSinkSetRecordingSource(pThisCC->pSinkMicIn, NULL);
2007
2008	AudioMixerSinkRemoveStream(pThisCC->pSinkMicIn, pDrv->MicIn.pMixStrm);
2009	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm);
2010	pDrv->MicIn.pMixStrm = NULL;
2011	}
2012
2013	if (pDrv->LineIn.pMixStrm)
2014	{
2015	if (AudioMixerSinkGetRecordingSource(pThisCC->pSinkLineIn) == pDrv->LineIn.pMixStrm)
2016	AudioMixerSinkSetRecordingSource(pThisCC->pSinkLineIn, NULL);
2017
2018	AudioMixerSinkRemoveStream(pThisCC->pSinkLineIn, pDrv->LineIn.pMixStrm);
2019	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm);
2020	pDrv->LineIn.pMixStrm = NULL;
2021	}
2022
2023	if (pDrv->Out.pMixStrm)
2024	{
2025	AudioMixerSinkRemoveStream(pThisCC->pSinkOut, pDrv->Out.pMixStrm);
2026	AudioMixerStreamDestroy(pDrv->Out.pMixStrm);
2027	pDrv->Out.pMixStrm = NULL;
2028	}
2029
2030	RTListNodeRemove(&pDrv->Node);
2031	}
2032
2033	/**
2034	* Removes a driver stream from a specific mixer sink.
2035	*
2036	* @param pMixSink Mixer sink to remove audio streams from.
2037	* @param enmDir Stream direction to remove.
2038	* @param dstSrc Stream destination / source to remove.
2039	* @param pDrv Driver stream to remove.
2040	*/
2041	static void ichac97R3MixerRemoveDrvStream(PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc, PAC97DRIVER pDrv)
2042	{
2043	PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, enmDir, dstSrc);
2044	if (pDrvStream)
2045	{
2046	if (pDrvStream->pMixStrm)
2047	{
2048	AudioMixerSinkRemoveStream(pMixSink, pDrvStream->pMixStrm);
2049
2050	AudioMixerStreamDestroy(pDrvStream->pMixStrm);
2051	pDrvStream->pMixStrm = NULL;
2052	}
2053	}
2054	}
2055
2056	/**
2057	* Removes all driver streams from a specific mixer sink.
2058	*
2059	* @param pThisCC The ring-3 AC'97 state.
2060	* @param pMixSink Mixer sink to remove audio streams from.
2061	* @param enmDir Stream direction to remove.
2062	* @param dstSrc Stream destination / source to remove.
2063	*/
2064	static void ichac97R3MixerRemoveDrvStreams(PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
2065	PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc)
2066	{
2067	AssertPtrReturnVoid(pMixSink);
2068
2069	PAC97DRIVER pDrv;
2070	RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
2071	{
2072	ichac97R3MixerRemoveDrvStream(pMixSink, enmDir, dstSrc, pDrv);
2073	}
2074	}
2075
2076	/**
2077	* Calculates and returns the ticks for a specified amount of bytes.
2078	*
2079	* @returns Calculated ticks
2080	* @param pDevIns The device instance.
2081	* @param pStream AC'97 stream to calculate ticks for (shared).
2082	* @param pStreamCC AC'97 stream to calculate ticks for (ring-3).
2083	* @param cbBytes Bytes to calculate ticks for.
2084	*/
2085	static uint64_t ichac97R3StreamTransferCalcNext(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint32_t cbBytes)
2086	{
2087	if (!cbBytes)
2088	return 0;
2089
2090	const uint64_t usBytes = PDMAudioPropsBytesToMicro(&pStreamCC->State.Cfg.Props, cbBytes);
2091	const uint64_t cTransferTicks = PDMDevHlpTimerFromMicro(pDevIns, pStream->hTimer, usBytes);
2092
2093	Log3Func(("[SD%RU8] Timer %uHz, cbBytes=%RU32 -> usBytes=%RU64, cTransferTicks=%RU64\n",
2094	pStream->u8SD, pStreamCC->State.uTimerHz, cbBytes, usBytes, cTransferTicks));
2095
2096	return cTransferTicks;
2097	}
2098
2099	/**
2100	* Updates the next transfer based on a specific amount of bytes.
2101	*
2102	* @param pDevIns The device instance.
2103	* @param pStream The AC'97 stream to update (shared).
2104	* @param pStreamCC The AC'97 stream to update (ring-3).
2105	* @param cbBytes Bytes to update next transfer for.
2106	*/
2107	static void ichac97R3StreamTransferUpdate(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint32_t cbBytes)
2108	{
2109	if (!cbBytes)
2110	return;
2111
2112	/* Calculate the bytes we need to transfer to / from the stream's DMA per iteration.
2113	* This is bound to the device's Hz rate and thus to the (virtual) timing the device expects. */
2114	pStreamCC->State.cbTransferChunk = cbBytes;
2115
2116	/* Update the transfer ticks. */
2117	pStreamCC->State.cTransferTicks = ichac97R3StreamTransferCalcNext(pDevIns, pStream, pStreamCC,
2118	pStreamCC->State.cbTransferChunk);
2119	Assert(pStreamCC->State.cTransferTicks); /* Paranoia. */
2120	}
2121
2122	/**
2123	* Opens an AC'97 stream with its current mixer settings.
2124	*
2125	* This will open an AC'97 stream with 2 (stereo) channels, 16-bit samples and
2126	* the last set sample rate in the AC'97 mixer for this stream.
2127	*
2128	* @returns IPRT status code.
2129	* @param pThis The shared AC'97 device state (shared).
2130	* @param pThisCC The shared AC'97 device state (ring-3).
2131	* @param pStream The AC'97 stream to open (shared).
2132	* @param pStreamCC The AC'97 stream to open (ring-3).
2133	* @param fForce Whether to force re-opening the stream or not.
2134	* Otherwise re-opening only will happen if the PCM properties have changed.
2135	*/
2136	static int ichac97R3StreamOpen(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2137	{
2138	PDMAUDIOSTREAMCFG Cfg;
2139	RT_ZERO(Cfg);
2140	Cfg.Props.cChannels = 2;
2141	Cfg.Props.cbSample = 2 /* 16-bit */;
2142	Cfg.Props.fSigned = true;
2143	Cfg.Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(Cfg.Props.cbSample, Cfg.Props.cChannels);
2144
2145	int rc = VINF_SUCCESS;
2146	PAUDMIXSINK pMixSink;
2147	switch (pStream->u8SD)
2148	{
2149	case AC97SOUNDSOURCE_PI_INDEX:
2150	{
2151	Cfg.Props.uHz = ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate);
2152	Cfg.enmDir = PDMAUDIODIR_IN;
2153	Cfg.u.enmSrc = PDMAUDIORECSRC_LINE;
2154	Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2155	RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Line-In");
2156
2157	pMixSink = pThisCC->pSinkLineIn;
2158	break;
2159	}
2160
2161	case AC97SOUNDSOURCE_MC_INDEX:
2162	{
2163	Cfg.Props.uHz = ichac97MixerGet(pThis, AC97_MIC_ADC_Rate);
2164	Cfg.enmDir = PDMAUDIODIR_IN;
2165	Cfg.u.enmSrc = PDMAUDIORECSRC_MIC;
2166	Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2167	RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Mic-In");
2168
2169	pMixSink = pThisCC->pSinkMicIn;
2170	break;
2171	}
2172
2173	case AC97SOUNDSOURCE_PO_INDEX:
2174	{
2175	Cfg.Props.uHz = ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate);
2176	Cfg.enmDir = PDMAUDIODIR_OUT;
2177	Cfg.u.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
2178	Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2179	RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Output");
2180
2181	pMixSink = pThisCC->pSinkOut;
2182	break;
2183	}
2184
2185	default:
2186	rc = VERR_NOT_SUPPORTED;
2187	pMixSink = NULL;
2188	break;
2189	}
2190
2191	if (RT_SUCCESS(rc))
2192	{
2193	/* Only (re-)create the stream (and driver chain) if we really have to.
2194	* Otherwise avoid this and just reuse it, as this costs performance. */
2195	if ( !PDMAudioStrmCfgMatchesProps(&Cfg, &pStreamCC->State.Cfg.Props)
2196	\|\| fForce)
2197	{
2198	LogRel2(("AC97: (Re-)Opening stream '%s' (%RU32Hz, %RU8 channels, %s%RU8)\n",
2199	Cfg.szName, Cfg.Props.uHz, Cfg.Props.cChannels, Cfg.Props.fSigned ? "S" : "U", Cfg.Props.cbSample * 8));
2200
2201	LogFlowFunc(("[SD%RU8] uHz=%RU32\n", pStream->u8SD, Cfg.Props.uHz));
2202
2203	if (Cfg.Props.uHz)
2204	{
2205	Assert(Cfg.enmDir != PDMAUDIODIR_UNKNOWN);
2206
2207	/*
2208	* Set the stream's timer Hz rate, based on the PCM properties Hz rate.
2209	*/
2210	if (pThis->uTimerHz == AC97_TIMER_HZ_DEFAULT) /* Make sure that we don't have any custom Hz rate set we want to enforce */
2211	{
2212	if (Cfg.Props.uHz > 44100) /* E.g. 48000 Hz. */
2213	pStreamCC->State.uTimerHz = 200;
2214	else /* Just take the global Hz rate otherwise. */
2215	pStreamCC->State.uTimerHz = pThis->uTimerHz;
2216	}
2217	else
2218	pStreamCC->State.uTimerHz = pThis->uTimerHz;
2219
2220	/* Set scheduling hint (if available). */
2221	if (pStreamCC->State.uTimerHz)
2222	Cfg.Device.cMsSchedulingHint = 1000 /* ms */ / pStreamCC->State.uTimerHz;
2223
2224	if (pStreamCC->State.pCircBuf)
2225	{
2226	RTCircBufDestroy(pStreamCC->State.pCircBuf);
2227	pStreamCC->State.pCircBuf = NULL;
2228	}
2229
2230	rc = RTCircBufCreate(&pStreamCC->State.pCircBuf, PDMAudioPropsMilliToBytes(&Cfg.Props, 100 /ms/)); /** @todo Make this configurable. */
2231	if (RT_SUCCESS(rc))
2232	{
2233	ichac97R3MixerRemoveDrvStreams(pThisCC, pMixSink, Cfg.enmDir, Cfg.u);
2234
2235	rc = ichac97R3MixerAddDrvStreams(pThisCC, pMixSink, &Cfg);
2236	if (RT_SUCCESS(rc))
2237	rc = PDMAudioStrmCfgCopy(&pStreamCC->State.Cfg, &Cfg);
2238	}
2239	}
2240	}
2241	else
2242	LogFlowFunc(("[SD%RU8] Skipping (re-)creation\n", pStream->u8SD));
2243	}
2244
2245	LogFlowFunc(("[SD%RU8] rc=%Rrc\n", pStream->u8SD, rc));
2246	return rc;
2247	}
2248
2249	/**
2250	* Closes an AC'97 stream.
2251	*
2252	* @returns IPRT status code.
2253	* @param pStream The AC'97 stream to close (shared).
2254	*/
2255	static int ichac97R3StreamClose(PAC97STREAM pStream)
2256	{
2257	RT_NOREF(pStream);
2258	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2259	return VINF_SUCCESS;
2260	}
2261
2262	/**
2263	* Re-opens (that is, closes and opens again) an AC'97 stream on the backend
2264	* side with the current AC'97 mixer settings for this stream.
2265	*
2266	* @returns IPRT status code.
2267	* @param pThis The shared AC'97 device state.
2268	* @param pThisCC The ring-3 AC'97 device state.
2269	* @param pStream The AC'97 stream to re-open (shared).
2270	* @param pStreamCC The AC'97 stream to re-open (ring-3).
2271	* @param fForce Whether to force re-opening the stream or not.
2272	* Otherwise re-opening only will happen if the PCM properties have changed.
2273	*/
2274	static int ichac97R3StreamReOpen(PAC97STATE pThis, PAC97STATER3 pThisCC,
2275	PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2276	{
2277	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2278	Assert(pStream->u8SD == pStreamCC->u8SD);
2279	Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2280	Assert(pStreamCC - &pThisCC->aStreams[0] == pStream->u8SD);
2281
2282	int rc = ichac97R3StreamClose(pStream);
2283	if (RT_SUCCESS(rc))
2284	rc = ichac97R3StreamOpen(pThis, pThisCC, pStream, pStreamCC, fForce);
2285
2286	return rc;
2287	}
2288
2289	/**
2290	* Locks an AC'97 stream for serialized access.
2291	*
2292	* @returns IPRT status code.
2293	* @param pStreamCC The AC'97 stream to lock (ring-3).
2294	*/
2295	static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC)
2296	{
2297	int rc2 = RTCritSectEnter(&pStreamCC->State.CritSect);
2298	AssertRC(rc2);
2299	}
2300
2301	/**
2302	* Unlocks a formerly locked AC'97 stream.
2303	*
2304	* @returns IPRT status code.
2305	* @param pStreamCC The AC'97 stream to unlock (ring-3).
2306	*/
2307	static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC)
2308	{
2309	int rc2 = RTCritSectLeave(&pStreamCC->State.CritSect);
2310	AssertRC(rc2);
2311	}
2312
2313	/**
2314	* Retrieves the available size of (buffered) audio data (in bytes) of a given AC'97 stream.
2315	*
2316	* @returns Available data (in bytes).
2317	* @param pStreamCC The AC'97 stream to retrieve size for (ring-3).
2318	*/
2319	static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC)
2320	{
2321	if (!pStreamCC->State.pCircBuf)
2322	return 0;
2323
2324	return (uint32_t)RTCircBufUsed(pStreamCC->State.pCircBuf);
2325	}
2326
2327	/**
2328	* Retrieves the free size of audio data (in bytes) of a given AC'97 stream.
2329	*
2330	* @returns Free data (in bytes).
2331	* @param pStreamCC AC'97 stream to retrieve size for (ring-3).
2332	*/
2333	static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC)
2334	{
2335	if (!pStreamCC->State.pCircBuf)
2336	return 0;
2337
2338	return (uint32_t)RTCircBufFree(pStreamCC->State.pCircBuf);
2339	}
2340
2341	/**
2342	* Sets the volume of a specific AC'97 mixer control.
2343	*
2344	* This currently only supports attenuation -- gain support is currently not implemented.
2345	*
2346	* @returns IPRT status code.
2347	* @param pThis The shared AC'97 state.
2348	* @param pThisCC The ring-3 AC'97 state.
2349	* @param index AC'97 mixer index to set volume for.
2350	* @param enmMixerCtl Corresponding audio mixer sink.
2351	* @param uVal Volume value to set.
2352	*/
2353	static int ichac97R3MixerSetVolume(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2354	{
2355	/*
2356	* From AC'97 SoundMax Codec AD1981A/AD1981B:
2357	* "Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the
2358	* D5 or D13 bits are set to 1, their respective lower five volume bits are automatically
2359	* set to 1 by the Codec logic. On readback, all lower 5 bits will read ones whenever
2360	* these bits are set to 1."
2361	*
2362	* Linux ALSA depends on this behavior to detect that only 5 bits are used for volume
2363	* control and the optional 6th bit is not used. Note that this logic only applies to the
2364	* master volume controls.
2365	*/
2366	if (index == AC97_Master_Volume_Mute \|\| index == AC97_Headphone_Volume_Mute \|\| index == AC97_Master_Volume_Mono_Mute)
2367	{
2368	if (uVal & RT_BIT(5)) /* D5 bit set? */
2369	uVal \|= RT_BIT(4) \| RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1) \| RT_BIT(0);
2370	if (uVal & RT_BIT(13)) /* D13 bit set? */
2371	uVal \|= RT_BIT(12) \| RT_BIT(11) \| RT_BIT(10) \| RT_BIT(9) \| RT_BIT(8);
2372	}
2373
2374	const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2375	uint8_t uCtlAttLeft = (uVal >> 8) & AC97_BARS_VOL_MASK;
2376	uint8_t uCtlAttRight = uVal & AC97_BARS_VOL_MASK;
2377
2378	/* For the master and headphone volume, 0 corresponds to 0dB attenuation. For the other
2379	* volume controls, 0 means 12dB gain and 8 means unity gain.
2380	*/
2381	if (index != AC97_Master_Volume_Mute && index != AC97_Headphone_Volume_Mute)
2382	{
2383	# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2384	/* NB: Currently there is no gain support, only attenuation. */
2385	uCtlAttLeft = uCtlAttLeft < 8 ? 0 : uCtlAttLeft - 8;
2386	uCtlAttRight = uCtlAttRight < 8 ? 0 : uCtlAttRight - 8;
2387	# endif
2388	}
2389	Assert(uCtlAttLeft <= 255 / AC97_DB_FACTOR);
2390	Assert(uCtlAttRight <= 255 / AC97_DB_FACTOR);
2391
2392	LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2393	LogFunc(("uCtlAttLeft=%RU8, uCtlAttRight=%RU8 ", uCtlAttLeft, uCtlAttRight));
2394
2395	/*
2396	* For AC'97 volume controls, each additional step means -1.5dB attenuation with
2397	* zero being maximum. In contrast, we're internally using 255 (PDMAUDIO_VOLUME_MAX)
2398	* steps, each -0.375dB, where 0 corresponds to -96dB and 255 corresponds to 0dB.
2399	*/
2400	uint8_t lVol = PDMAUDIO_VOLUME_MAX - uCtlAttLeft * AC97_DB_FACTOR;
2401	uint8_t rVol = PDMAUDIO_VOLUME_MAX - uCtlAttRight * AC97_DB_FACTOR;
2402
2403	Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2404
2405	int rc = VINF_SUCCESS;
2406
2407	if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2408	{
2409	PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2410	PAUDMIXSINK pSink = NULL;
2411
2412	switch (enmMixerCtl)
2413	{
2414	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2415	rc = AudioMixerSetMasterVolume(pThisCC->pMixer, &Vol);
2416	break;
2417
2418	case PDMAUDIOMIXERCTL_FRONT:
2419	pSink = pThisCC->pSinkOut;
2420	break;
2421
2422	case PDMAUDIOMIXERCTL_MIC_IN:
2423	case PDMAUDIOMIXERCTL_LINE_IN:
2424	/* These are recognized but do nothing. */
2425	break;
2426
2427	default:
2428	AssertFailed();
2429	rc = VERR_NOT_SUPPORTED;
2430	break;
2431	}
2432
2433	if (pSink)
2434	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2435	}
2436
2437	ichac97MixerSet(pThis, index, uVal);
2438
2439	if (RT_FAILURE(rc))
2440	LogFlowFunc(("Failed with %Rrc\n", rc));
2441
2442	return rc;
2443	}
2444
2445	/**
2446	* Sets the gain of a specific AC'97 recording control.
2447	*
2448	* NB: gain support is currently not implemented in PDM audio.
2449	*
2450	* @returns IPRT status code.
2451	* @param pThis The shared AC'97 state.
2452	* @param pThisCC The ring-3 AC'97 state.
2453	* @param index AC'97 mixer index to set volume for.
2454	* @param enmMixerCtl Corresponding audio mixer sink.
2455	* @param uVal Volume value to set.
2456	*/
2457	static int ichac97R3MixerSetGain(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2458	{
2459	/*
2460	* For AC'97 recording controls, each additional step means +1.5dB gain with
2461	* zero being 0dB gain and 15 being +22.5dB gain.
2462	*/
2463	const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2464	uint8_t uCtlGainLeft = (uVal >> 8) & AC97_BARS_GAIN_MASK;
2465	uint8_t uCtlGainRight = uVal & AC97_BARS_GAIN_MASK;
2466
2467	Assert(uCtlGainLeft <= 255 / AC97_DB_FACTOR);
2468	Assert(uCtlGainRight <= 255 / AC97_DB_FACTOR);
2469
2470	LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2471	LogFunc(("uCtlGainLeft=%RU8, uCtlGainRight=%RU8 ", uCtlGainLeft, uCtlGainRight));
2472
2473	uint8_t lVol = PDMAUDIO_VOLUME_MAX + uCtlGainLeft * AC97_DB_FACTOR;
2474	uint8_t rVol = PDMAUDIO_VOLUME_MAX + uCtlGainRight * AC97_DB_FACTOR;
2475
2476	/* We do not currently support gain. Since AC'97 does not support attenuation
2477	* for the recording input, the best we can do is set the maximum volume.
2478	*/
2479	# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2480	/* NB: Currently there is no gain support, only attenuation. Since AC'97 does not
2481	* support attenuation for the recording inputs, the best we can do is set the
2482	* maximum volume.
2483	*/
2484	lVol = rVol = PDMAUDIO_VOLUME_MAX;
2485	# endif
2486
2487	Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2488
2489	int rc = VINF_SUCCESS;
2490
2491	if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2492	{
2493	PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2494	PAUDMIXSINK pSink = NULL;
2495
2496	switch (enmMixerCtl)
2497	{
2498	case PDMAUDIOMIXERCTL_MIC_IN:
2499	pSink = pThisCC->pSinkMicIn;
2500	break;
2501
2502	case PDMAUDIOMIXERCTL_LINE_IN:
2503	pSink = pThisCC->pSinkLineIn;
2504	break;
2505
2506	default:
2507	AssertFailed();
2508	rc = VERR_NOT_SUPPORTED;
2509	break;
2510	}
2511
2512	if (pSink) {
2513	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2514	/* There is only one AC'97 recording gain control. If line in
2515	* is changed, also update the microphone. If the optional dedicated
2516	* microphone is changed, only change that.
2517	* NB: The codecs we support do not have the dedicated microphone control.
2518	*/
2519	if ((pSink == pThisCC->pSinkLineIn) && pThisCC->pSinkMicIn)
2520	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2521	}
2522	}
2523
2524	ichac97MixerSet(pThis, index, uVal);
2525
2526	if (RT_FAILURE(rc))
2527	LogFlowFunc(("Failed with %Rrc\n", rc));
2528
2529	return rc;
2530	}
2531
2532	/**
2533	* Converts an AC'97 recording source index to a PDM audio recording source.
2534	*
2535	* @returns PDM audio recording source.
2536	* @param uIdx AC'97 index to convert.
2537	*/
2538	static PDMAUDIORECSRC ichac97R3IdxToRecSource(uint8_t uIdx)
2539	{
2540	switch (uIdx)
2541	{
2542	case AC97_REC_MIC: return PDMAUDIORECSRC_MIC;
2543	case AC97_REC_CD: return PDMAUDIORECSRC_CD;
2544	case AC97_REC_VIDEO: return PDMAUDIORECSRC_VIDEO;
2545	case AC97_REC_AUX: return PDMAUDIORECSRC_AUX;
2546	case AC97_REC_LINE_IN: return PDMAUDIORECSRC_LINE;
2547	case AC97_REC_PHONE: return PDMAUDIORECSRC_PHONE;
2548	default:
2549	break;
2550	}
2551
2552	LogFlowFunc(("Unknown record source %d, using MIC\n", uIdx));
2553	return PDMAUDIORECSRC_MIC;
2554	}
2555
2556	/**
2557	* Converts a PDM audio recording source to an AC'97 recording source index.
2558	*
2559	* @returns AC'97 recording source index.
2560	* @param enmRecSrc PDM audio recording source to convert.
2561	*/
2562	static uint8_t ichac97R3RecSourceToIdx(PDMAUDIORECSRC enmRecSrc)
2563	{
2564	switch (enmRecSrc)
2565	{
2566	case PDMAUDIORECSRC_MIC: return AC97_REC_MIC;
2567	case PDMAUDIORECSRC_CD: return AC97_REC_CD;
2568	case PDMAUDIORECSRC_VIDEO: return AC97_REC_VIDEO;
2569	case PDMAUDIORECSRC_AUX: return AC97_REC_AUX;
2570	case PDMAUDIORECSRC_LINE: return AC97_REC_LINE_IN;
2571	case PDMAUDIORECSRC_PHONE: return AC97_REC_PHONE;
2572	default:
2573	break;
2574	}
2575
2576	LogFlowFunc(("Unknown audio recording source %d using MIC\n", enmRecSrc));
2577	return AC97_REC_MIC;
2578	}
2579
2580	/**
2581	* Returns the audio direction of a specified stream descriptor.
2582	*
2583	* @return Audio direction.
2584	*/
2585	DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD)
2586	{
2587	switch (uSD)
2588	{
2589	case AC97SOUNDSOURCE_PI_INDEX: return PDMAUDIODIR_IN;
2590	case AC97SOUNDSOURCE_PO_INDEX: return PDMAUDIODIR_OUT;
2591	case AC97SOUNDSOURCE_MC_INDEX: return PDMAUDIODIR_IN;
2592	}
2593
2594	AssertFailed();
2595	return PDMAUDIODIR_UNKNOWN;
2596	}
2597
2598	#endif /* IN_RING3 */
2599
2600	#ifdef IN_RING3
2601
2602	/**
2603	* Performs an AC'97 mixer record select to switch to a different recording
2604	* source.
2605	*
2606	* @param pThis The shared AC'97 state.
2607	* @param val AC'97 recording source index to set.
2608	*/
2609	static void ichac97R3MixerRecordSelect(PAC97STATE pThis, uint32_t val)
2610	{
2611	uint8_t rs = val & AC97_REC_MASK;
2612	uint8_t ls = (val >> 8) & AC97_REC_MASK;
2613
2614	const PDMAUDIORECSRC ars = ichac97R3IdxToRecSource(rs);
2615	const PDMAUDIORECSRC als = ichac97R3IdxToRecSource(ls);
2616
2617	rs = ichac97R3RecSourceToIdx(ars);
2618	ls = ichac97R3RecSourceToIdx(als);
2619
2620	LogRel(("AC97: Record select to left=%s, right=%s\n", DrvAudioHlpRecSrcToStr(ars), DrvAudioHlpRecSrcToStr(als)));
2621
2622	ichac97MixerSet(pThis, AC97_Record_Select, rs \| (ls << 8));
2623	}
2624
2625	/**
2626	* Resets the AC'97 mixer.
2627	*
2628	* @returns IPRT status code.
2629	* @param pThis The shared AC'97 state.
2630	* @param pThisCC The ring-3 AC'97 state.
2631	*/
2632	static int ichac97R3MixerReset(PAC97STATE pThis, PAC97STATER3 pThisCC)
2633	{
2634	LogFlowFuncEnter();
2635
2636	RT_ZERO(pThis->mixer_data);
2637
2638	/* Note: Make sure to reset all registers first before bailing out on error. */
2639
2640	ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
2641	ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
2642	ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
2643
2644	ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
2645	ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
2646	ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
2647	ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
2648	ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
2649	ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
2650	ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
2651	ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
2652
2653	/* Configure Extended Audio ID (EAID) + Control & Status (EACS) registers. */
2654	const uint16_t fEAID = AC97_EAID_REV1 \| AC97_EACS_VRA \| AC97_EACS_VRM; /* Our hardware is AC'97 rev2.3 compliant. */
2655	const uint16_t fEACS = AC97_EACS_VRA \| AC97_EACS_VRM; /* Variable Rate PCM Audio (VRA) + Mic-In (VRM) capable. */
2656
2657	LogRel(("AC97: Mixer reset (EAID=0x%x, EACS=0x%x)\n", fEAID, fEACS));
2658
2659	ichac97MixerSet(pThis, AC97_Extended_Audio_ID, fEAID);
2660	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, fEACS);
2661	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2662	ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2663	ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2664	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2665	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2666
2667	if (pThis->enmCodecModel == AC97CODEC_AD1980)
2668	{
2669	/* Analog Devices 1980 (AD1980) */
2670	ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
2671	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2672	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
2673	ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
2674	}
2675	else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
2676	{
2677	/* Analog Devices 1981B (AD1981B) */
2678	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2679	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
2680	}
2681	else
2682	{
2683	/* Sigmatel 9700 (STAC9700) */
2684	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
2685	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
2686	}
2687	ichac97R3MixerRecordSelect(pThis, 0);
2688
2689	/* The default value is 8000h, which corresponds to 0 dB attenuation with mute on. */
2690	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER, 0x8000);
2691
2692	/* The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on.*/
2693	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT, 0x8808);
2694	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
2695	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8008);
2696
2697	/* The default for record controls is 0 dB gain with mute on. */
2698	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8000);
2699	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8000);
2700
2701	return VINF_SUCCESS;
2702	}
2703
2704	# if 0 /* Unused */
2705	static void ichac97R3WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
2706	{
2707	LogFlowFunc(("cbElapsed=%RU32\n", cbElapsed));
2708
2709	if (!(pThis->bup_flag & BUP_SET))
2710	{
2711	if (pThis->bup_flag & BUP_LAST)
2712	{
2713	unsigned int i;
2714	uint32_t p = (uint32_t)pThis->silence;
2715	for (i = 0; i < sizeof(pThis->silence) / 4; i++) /** @todo r=andy Assumes 16-bit samples, stereo. */
2716	*p++ = pThis->last_samp;
2717	}
2718	else
2719	RT_ZERO(pThis->silence);
2720
2721	pThis->bup_flag \|= BUP_SET;
2722	}
2723
2724	while (cbElapsed)
2725	{
2726	uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
2727	uint32_t cbWrittenToStream;
2728
2729	int rc2 = AudioMixerSinkWrite(pThisCC->pSinkOut, AUDMIXOP_COPY,
2730	pThis->silence, cbToWrite, &cbWrittenToStream);
2731	if (RT_SUCCESS(rc2))
2732	{
2733	if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2734	LogFlowFunc(("Warning: Only written %RU32 / %RU32 bytes, expect lags\n", cbWrittenToStream, cbToWrite));
2735	}
2736
2737	/* Always report all data as being written;
2738	* backends who were not able to catch up have to deal with it themselves. */
2739	Assert(cbElapsed >= cbToWrite);
2740	cbElapsed -= cbToWrite;
2741	}
2742	}
2743	# endif /* Unused */
2744
2745	/**
2746	* @callback_method_impl{FNTMTIMERDEV,
2747	* Timer callback which handles the audio data transfers on a periodic basis.}
2748	*/
2749	static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
2750	{
2751	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2752	STAM_PROFILE_START(&pThis->StatTimer, a);
2753	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
2754	PAC97STREAM pStream = (PAC97STREAM)pvUser;
2755	PAC97STREAMR3 pStreamCC = &RT_SAFE_SUBSCRIPT8(pThisCC->aStreams, pStream->u8SD);
2756	Assert(hTimer == pStream->hTimer); RT_NOREF(hTimer);
2757
2758	Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2759	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2760	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStream->hTimer));
2761
2762	ichac97R3StreamUpdate(pDevIns, pThis, pThisCC, pStream, pStreamCC, true /* fInTimer */);
2763
2764	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
2765	if (pSink && AudioMixerSinkIsActive(pSink))
2766	{
2767	ichac97R3StreamTransferUpdate(pDevIns, pStream, pStreamCC, pStream->Regs.picb << 1); /** @todo r=andy Assumes 16-bit samples. */
2768	ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
2769	}
2770
2771	STAM_PROFILE_STOP(&pThis->StatTimer, a);
2772	}
2773
2774
2775	/**
2776	* Sets the virtual device timer to a new expiration time.
2777	*
2778	* @param pDevIns The device instance.
2779	* @param pStream AC'97 stream to set timer for.
2780	* @param cTicksToDeadline The number of ticks to the new deadline.
2781	*
2782	* @remarks This used to be more complicated a long time ago...
2783	*/
2784	DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline)
2785	{
2786	int rc = PDMDevHlpTimerSetRelative(pDevIns, pStream->hTimer, cTicksToDeadline, NULL /pu64Now/);
2787	AssertRC(rc);
2788	}
2789
2790
2791	/**
2792	* Transfers data of an AC'97 stream according to its usage (input / output).
2793	*
2794	* For an SDO (output) stream this means reading DMA data from the device to
2795	* the AC'97 stream's internal FIFO buffer.
2796	*
2797	* For an SDI (input) stream this is reading audio data from the AC'97 stream's
2798	* internal FIFO buffer and writing it as DMA data to the device.
2799	*
2800	* @returns IPRT status code.
2801	* @param pDevIns The device instance.
2802	* @param pThis The shared AC'97 state.
2803	* @param pStream The AC'97 stream to update (shared).
2804	* @param pStreamCC The AC'97 stream to update (ring-3).
2805	* @param cbToProcessMax Maximum of data (in bytes) to process.
2806	*/
2807	static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
2808	PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax)
2809	{
2810	if (!cbToProcessMax)
2811	return VINF_SUCCESS;
2812
2813	#ifdef VBOX_STRICT
2814	const unsigned cbFrame = PDMAudioPropsBytesPerFrame(&pStreamCC->State.Cfg.Props);
2815	#endif
2816
2817	/* Make sure to only process an integer number of audio frames. */
2818	Assert(cbToProcessMax % cbFrame == 0);
2819
2820	ichac97R3StreamLock(pStreamCC);
2821
2822	PAC97BMREGS pRegs = &pStream->Regs;
2823
2824	if (pRegs->sr & AC97_SR_DCH) /* Controller halted? */
2825	{
2826	if (pRegs->cr & AC97_CR_RPBM) /* Bus master operation starts. */
2827	{
2828	switch (pStream->u8SD)
2829	{
2830	case AC97SOUNDSOURCE_PO_INDEX:
2831	/ichac97R3WriteBUP(pThis, cbToProcess);/
2832	break;
2833
2834	default:
2835	break;
2836	}
2837	}
2838
2839	ichac97R3StreamUnlock(pStreamCC);
2840	return VINF_SUCCESS;
2841	}
2842
2843	/* BCIS flag still set? Skip iteration. */
2844	if (pRegs->sr & AC97_SR_BCIS)
2845	{
2846	Log3Func(("[SD%RU8] BCIS set\n", pStream->u8SD));
2847
2848	ichac97R3StreamUnlock(pStreamCC);
2849	return VINF_SUCCESS;
2850	}
2851
2852	uint32_t cbLeft = RT_MIN((uint32_t)(pRegs->picb << 1), cbToProcessMax); /** @todo r=andy Assumes 16bit samples. */
2853	uint32_t cbProcessedTotal = 0;
2854
2855	PRTCIRCBUF pCircBuf = pStreamCC->State.pCircBuf;
2856	AssertPtr(pCircBuf);
2857
2858	int rc = VINF_SUCCESS;
2859
2860	Log3Func(("[SD%RU8] cbToProcessMax=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcessMax, cbLeft));
2861
2862	while (cbLeft)
2863	{
2864	if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
2865	{
2866	Log3Func(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
2867	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
2868	if (pRegs->civ == pRegs->lvi)
2869	{
2870	pRegs->sr \|= AC97_SR_DCH; /** @todo r=andy Also set CELV? */
2871	pThis->bup_flag = 0;
2872
2873	rc = VINF_EOF;
2874	break;
2875	}
2876
2877	pRegs->sr &= ~AC97_SR_CELV;
2878	pRegs->civ = pRegs->piv;
2879	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2880
2881	ichac97R3StreamFetchBDLE(pDevIns, pStream);
2882	continue;
2883	}
2884
2885	uint32_t cbChunk = cbLeft;
2886
2887	switch (pStream->u8SD)
2888	{
2889	case AC97SOUNDSOURCE_PO_INDEX: /* Output */
2890	{
2891	void *pvDst;
2892	size_t cbDst;
2893
2894	RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvDst, &cbDst);
2895
2896	if (cbDst)
2897	{
2898	int rc2 = PDMDevHlpPCIPhysRead(pDevIns, pRegs->bd.addr, (uint8_t *)pvDst, cbDst);
2899	AssertRC(rc2);
2900
2901	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2902	{ /* likely */ }
2903	else
2904	DrvAudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvDst, cbDst, 0 /* fFlags */);
2905	}
2906
2907	RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
2908
2909	cbChunk = (uint32_t)cbDst; /* Update the current chunk size to what really has been written. */
2910	break;
2911	}
2912
2913	case AC97SOUNDSOURCE_PI_INDEX: /* Input */
2914	case AC97SOUNDSOURCE_MC_INDEX: /* Input */
2915	{
2916	void *pvSrc;
2917	size_t cbSrc;
2918
2919	RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvSrc, &cbSrc);
2920
2921	if (cbSrc)
2922	{
2923	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, pRegs->bd.addr, (uint8_t *)pvSrc, cbSrc);
2924	AssertRC(rc2);
2925
2926	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2927	{ /* likely */ }
2928	else
2929	DrvAudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvSrc, cbSrc, 0 /* fFlags */);
2930	}
2931
2932	RTCircBufReleaseReadBlock(pCircBuf, cbSrc);
2933
2934	cbChunk = (uint32_t)cbSrc; /* Update the current chunk size to what really has been read. */
2935	break;
2936	}
2937
2938	default:
2939	AssertMsgFailed(("Stream #%RU8 not supported\n", pStream->u8SD));
2940	rc = VERR_NOT_SUPPORTED;
2941	break;
2942	}
2943
2944	if (RT_FAILURE(rc))
2945	break;
2946
2947	if (cbChunk)
2948	{
2949	cbProcessedTotal += cbChunk;
2950	Assert(cbProcessedTotal <= cbToProcessMax);
2951	Assert(cbLeft >= cbChunk);
2952	cbLeft -= cbChunk;
2953	Assert((cbChunk & 1) == 0); /* Else the following shift won't work */
2954
2955	pRegs->picb -= (cbChunk >> 1); /** @todo r=andy Assumes 16bit samples. */
2956	pRegs->bd.addr += cbChunk;
2957	}
2958
2959	LogFlowFunc(("[SD%RU8] cbChunk=%RU32, cbLeft=%RU32, cbTotal=%RU32, rc=%Rrc\n",
2960	pStream->u8SD, cbChunk, cbLeft, cbProcessedTotal, rc));
2961
2962	if (!pRegs->picb)
2963	{
2964	uint32_t new_sr = pRegs->sr & ~AC97_SR_CELV;
2965
2966	if (pRegs->bd.ctl_len & AC97_BD_IOC)
2967	{
2968	new_sr \|= AC97_SR_BCIS;
2969	}
2970
2971	if (pRegs->civ == pRegs->lvi)
2972	{
2973	/* Did we run out of data? */
2974	LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pRegs->civ, pRegs->lvi));
2975
2976	new_sr \|= AC97_SR_LVBCI \| AC97_SR_DCH \| AC97_SR_CELV;
2977	pThis->bup_flag = (pRegs->bd.ctl_len & AC97_BD_BUP) ? BUP_LAST : 0;
2978
2979	rc = VINF_EOF;
2980	}
2981	else
2982	{
2983	pRegs->civ = pRegs->piv;
2984	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2985	ichac97R3StreamFetchBDLE(pDevIns, pStream);
2986	}
2987
2988	ichac97StreamUpdateSR(pDevIns, pThis, pStream, new_sr);
2989	}
2990
2991	if (/* All data processed? */
2992	rc == VINF_EOF
2993	/* ... or an error occurred? */
2994	\|\| RT_FAILURE(rc))
2995	{
2996	break;
2997	}
2998	}
2999
3000	ichac97R3StreamUnlock(pStreamCC);
3001
3002	LogFlowFuncLeaveRC(rc);
3003	return rc;
3004	}
3005
3006	#endif /* IN_RING3 */
3007
3008
3009	/**
3010	* @callback_method_impl{FNIOMIOPORTNEWIN}
3011	*/
3012	static DECLCALLBACK(VBOXSTRICTRC)
3013	ichac97IoPortNabmRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3014	{
3015	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3016	RT_NOREF(pvUser);
3017
3018	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3019
3020	/* Get the index of the NABMBAR port. */
3021	if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
3022	&& offPort != AC97_GLOB_CNT)
3023	{
3024	PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
3025	PAC97BMREGS pRegs = &pStream->Regs;
3026
3027	switch (cb)
3028	{
3029	case 1:
3030	switch (offPort & AC97_NABM_OFF_MASK)
3031	{
3032	case AC97_NABM_OFF_CIV:
3033	/* Current Index Value Register */
3034	*pu32 = pRegs->civ;
3035	Log3Func(("CIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3036	break;
3037	case AC97_NABM_OFF_LVI:
3038	/* Last Valid Index Register */
3039	*pu32 = pRegs->lvi;
3040	Log3Func(("LVI[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3041	break;
3042	case AC97_NABM_OFF_PIV:
3043	/* Prefetched Index Value Register */
3044	*pu32 = pRegs->piv;
3045	Log3Func(("PIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3046	break;
3047	case AC97_NABM_OFF_CR:
3048	/* Control Register */
3049	*pu32 = pRegs->cr;
3050	Log3Func(("CR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3051	break;
3052	case AC97_NABM_OFF_SR:
3053	/* Status Register (lower part) */
3054	*pu32 = RT_LO_U8(pRegs->sr);
3055	Log3Func(("SRb[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3056	break;
3057	default:
3058	*pu32 = UINT32_MAX;
3059	LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
3060	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3061	break;
3062	}
3063	break;
3064
3065	case 2:
3066	switch (offPort & AC97_NABM_OFF_MASK)
3067	{
3068	case AC97_NABM_OFF_SR:
3069	/* Status Register */
3070	*pu32 = pRegs->sr;
3071	Log3Func(("SR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3072	break;
3073	case AC97_NABM_OFF_PICB:
3074	/* Position in Current Buffer */
3075	*pu32 = pRegs->picb;
3076	Log3Func(("PICB[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3077	break;
3078	default:
3079	*pu32 = UINT32_MAX;
3080	LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
3081	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3082	break;
3083	}
3084	break;
3085
3086	case 4:
3087	switch (offPort & AC97_NABM_OFF_MASK)
3088	{
3089	case AC97_NABM_OFF_BDBAR:
3090	/* Buffer Descriptor Base Address Register */
3091	*pu32 = pRegs->bdbar;
3092	Log3Func(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3093	break;
3094	case AC97_NABM_OFF_CIV:
3095	/* 32-bit access: Current Index Value Register +
3096	* Last Valid Index Register +
3097	* Status Register */
3098	pu32 = pRegs->civ \| (pRegs->lvi << 8) \| (pRegs->sr << 16); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
3099	Log3Func(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
3100	AC97_PORT2IDX(offPort), pRegs->civ, pRegs->lvi, pRegs->sr));
3101	break;
3102	case AC97_NABM_OFF_PICB:
3103	/* 32-bit access: Position in Current Buffer Register +
3104	* Prefetched Index Value Register +
3105	* Control Register */
3106	pu32 = pRegs->picb \| (pRegs->piv << 16) \| (pRegs->cr << 24); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
3107	Log3Func(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
3108	AC97_PORT2IDX(offPort), *pu32, pRegs->picb, pRegs->piv, pRegs->cr));
3109	break;
3110
3111	default:
3112	*pu32 = UINT32_MAX;
3113	LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
3114	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3115	break;
3116	}
3117	break;
3118
3119	default:
3120	DEVAC97_UNLOCK(pDevIns, pThis);
3121	AssertFailed();
3122	return VERR_IOM_IOPORT_UNUSED;
3123	}
3124	}
3125	else
3126	{
3127	switch (cb)
3128	{
3129	case 1:
3130	switch (offPort)
3131	{
3132	case AC97_CAS:
3133	/* Codec Access Semaphore Register */
3134	Log3Func(("CAS %d\n", pThis->cas));
3135	*pu32 = pThis->cas;
3136	pThis->cas = 1;
3137	break;
3138	default:
3139	*pu32 = UINT32_MAX;
3140	LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
3141	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3142	break;
3143	}
3144	break;
3145
3146	case 2:
3147	*pu32 = UINT32_MAX;
3148	LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
3149	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3150	break;
3151
3152	case 4:
3153	switch (offPort)
3154	{
3155	case AC97_GLOB_CNT:
3156	/* Global Control */
3157	*pu32 = pThis->glob_cnt;
3158	Log3Func(("glob_cnt -> %#x\n", *pu32));
3159	break;
3160	case AC97_GLOB_STA:
3161	/* Global Status */
3162	*pu32 = pThis->glob_sta \| AC97_GS_S0CR;
3163	Log3Func(("glob_sta -> %#x\n", *pu32));
3164	break;
3165	default:
3166	*pu32 = UINT32_MAX;
3167	LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
3168	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3169	break;
3170	}
3171	break;
3172
3173	default:
3174	DEVAC97_UNLOCK(pDevIns, pThis);
3175	AssertFailed();
3176	return VERR_IOM_IOPORT_UNUSED;
3177	}
3178	}
3179
3180	DEVAC97_UNLOCK(pDevIns, pThis);
3181	return VINF_SUCCESS;
3182	}
3183
3184	/**
3185	* @callback_method_impl{FNIOMIOPORTNEWOUT}
3186	*/
3187	static DECLCALLBACK(VBOXSTRICTRC)
3188	ichac97IoPortNabmWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3189	{
3190	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3191	#ifdef IN_RING3
3192	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3193	#endif
3194	RT_NOREF(pvUser);
3195
3196	VBOXSTRICTRC rc = VINF_SUCCESS;
3197	if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
3198	&& offPort != AC97_GLOB_CNT)
3199	{
3200	#ifdef IN_RING3
3201	PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[AC97_PORT2IDX(offPort)];
3202	#endif
3203	PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
3204	PAC97BMREGS pRegs = &pStream->Regs;
3205
3206	DEVAC97_LOCK_BOTH_RETURN(pDevIns, pThis, pStream, VINF_IOM_R3_IOPORT_WRITE);
3207	switch (cb)
3208	{
3209	case 1:
3210	switch (offPort & AC97_NABM_OFF_MASK)
3211	{
3212	/*
3213	* Last Valid Index.
3214	*/
3215	case AC97_NABM_OFF_LVI:
3216	if ( (pRegs->cr & AC97_CR_RPBM)
3217	&& (pRegs->sr & AC97_SR_DCH))
3218	{
3219	#ifdef IN_RING3
3220	pRegs->sr &= ~(AC97_SR_DCH \| AC97_SR_CELV);
3221	pRegs->civ = pRegs->piv;
3222	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3223	#else
3224	rc = VINF_IOM_R3_IOPORT_WRITE;
3225	#endif
3226	}
3227	pRegs->lvi = u32 % AC97_MAX_BDLE;
3228	Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32));
3229	break;
3230
3231	/*
3232	* Control Registers.
3233	*/
3234	case AC97_NABM_OFF_CR:
3235	#ifdef IN_RING3
3236	Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32, pRegs->cr));
3237	if (u32 & AC97_CR_RR) /* Busmaster reset. */
3238	{
3239	Log3Func(("[SD%RU8] Reset\n", pStream->u8SD));
3240
3241	/* Make sure that Run/Pause Bus Master bit (RPBM) is cleared (0). */
3242	Assert((pRegs->cr & AC97_CR_RPBM) == 0);
3243
3244	ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3245	ichac97R3StreamReset(pThis, pStream, pStreamCC);
3246
3247	ichac97StreamUpdateSR(pDevIns, pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */
3248	}
3249	else
3250	{
3251	pRegs->cr = u32 & AC97_CR_VALID_MASK;
3252
3253	if (!(pRegs->cr & AC97_CR_RPBM))
3254	{
3255	Log3Func(("[SD%RU8] Disable\n", pStream->u8SD));
3256
3257	ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3258
3259	pRegs->sr \|= AC97_SR_DCH;
3260	}
3261	else
3262	{
3263	Log3Func(("[SD%RU8] Enable\n", pStream->u8SD));
3264
3265	pRegs->civ = pRegs->piv;
3266	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3267
3268	pRegs->sr &= ~AC97_SR_DCH;
3269
3270	/* Fetch the initial BDLE descriptor. */
3271	ichac97R3StreamFetchBDLE(pDevIns, pStream);
3272	# ifdef LOG_ENABLED
3273	ichac97R3BDLEDumpAll(pDevIns, pStream->Regs.bdbar, pStream->Regs.lvi + 1);
3274	# endif
3275	ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, true /* fEnable */);
3276
3277	/* Arm the timer for this stream. */
3278	/** @todo r=bird: This function returns bool, not VBox status! */
3279	ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3280	}
3281	}
3282	#else /* !IN_RING3 */
3283	rc = VINF_IOM_R3_IOPORT_WRITE;
3284	#endif
3285	break;
3286
3287	/*
3288	* Status Registers.
3289	*/
3290	case AC97_NABM_OFF_SR:
3291	ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3292	break;
3293
3294	default:
3295	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3296	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3297	break;
3298	}
3299	break;
3300
3301	case 2:
3302	switch (offPort & AC97_NABM_OFF_MASK)
3303	{
3304	case AC97_NABM_OFF_SR:
3305	ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3306	break;
3307	default:
3308	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3309	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3310	break;
3311	}
3312	break;
3313
3314	case 4:
3315	switch (offPort & AC97_NABM_OFF_MASK)
3316	{
3317	case AC97_NABM_OFF_BDBAR:
3318	/* Buffer Descriptor list Base Address Register */
3319	pRegs->bdbar = u32 & ~3;
3320	Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(offPort), u32, pRegs->bdbar));
3321	break;
3322	default:
3323	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3324	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3325	break;
3326	}
3327	break;
3328
3329	default:
3330	AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3331	break;
3332	}
3333	DEVAC97_UNLOCK_BOTH(pDevIns, pThis, pStream);
3334	}
3335	else
3336	{
3337	switch (cb)
3338	{
3339	case 1:
3340	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3341	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3342	break;
3343
3344	case 2:
3345	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3346	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3347	break;
3348
3349	case 4:
3350	switch (offPort)
3351	{
3352	case AC97_GLOB_CNT:
3353	/* Global Control */
3354	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3355	if (u32 & AC97_GC_WR)
3356	ichac97WarmReset(pThis);
3357	if (u32 & AC97_GC_CR)
3358	ichac97ColdReset(pThis);
3359	if (!(u32 & (AC97_GC_WR \| AC97_GC_CR)))
3360	pThis->glob_cnt = u32 & AC97_GC_VALID_MASK;
3361	Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt));
3362	DEVAC97_UNLOCK(pDevIns, pThis);
3363	break;
3364	case AC97_GLOB_STA:
3365	/* Global Status */
3366	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3367	pThis->glob_sta &= ~(u32 & AC97_GS_WCLEAR_MASK);
3368	pThis->glob_sta \|= (u32 & ~(AC97_GS_WCLEAR_MASK \| AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK;
3369	Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta));
3370	DEVAC97_UNLOCK(pDevIns, pThis);
3371	break;
3372	default:
3373	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3374	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3375	break;
3376	}
3377	break;
3378
3379	default:
3380	AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3381	break;
3382	}
3383	}
3384
3385	return rc;
3386	}
3387
3388	/**
3389	* @callback_method_impl{FNIOMIOPORTNEWIN}
3390	*/
3391	static DECLCALLBACK(VBOXSTRICTRC)
3392	ichac97IoPortNamRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3393	{
3394	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3395	RT_NOREF(pvUser);
3396	Assert(offPort < 256);
3397
3398	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3399
3400	VBOXSTRICTRC rc = VINF_SUCCESS;
3401	switch (cb)
3402	{
3403	case 1:
3404	{
3405	LogRel2(("AC97: Warning: Unimplemented read (1 byte) offPort=%#x\n", offPort));
3406	pThis->cas = 0;
3407	*pu32 = UINT32_MAX;
3408	break;
3409	}
3410
3411	case 2:
3412	{
3413	pThis->cas = 0;
3414	*pu32 = ichac97MixerGet(pThis, offPort);
3415	break;
3416	}
3417
3418	case 4:
3419	{
3420	LogRel2(("AC97: Warning: Unimplemented read (4 bytes) offPort=%#x\n", offPort));
3421	pThis->cas = 0;
3422	*pu32 = UINT32_MAX;
3423	break;
3424	}
3425
3426	default:
3427	{
3428	AssertFailed();
3429	rc = VERR_IOM_IOPORT_UNUSED;
3430	}
3431	}
3432
3433	DEVAC97_UNLOCK(pDevIns, pThis);
3434	return rc;
3435	}
3436
3437	/**
3438	* @callback_method_impl{FNIOMIOPORTNEWOUT}
3439	*/
3440	static DECLCALLBACK(VBOXSTRICTRC)
3441	ichac97IoPortNamWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3442	{
3443	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3444	#ifdef IN_RING3
3445	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3446	#endif
3447	RT_NOREF(pvUser);
3448
3449	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3450
3451	VBOXSTRICTRC rc = VINF_SUCCESS;
3452	switch (cb)
3453	{
3454	case 1:
3455	{
3456	LogRel2(("AC97: Warning: Unimplemented NAMWrite (1 byte) offPort=%#x <- %#x\n", offPort, u32));
3457	pThis->cas = 0;
3458	break;
3459	}
3460
3461	case 2:
3462	{
3463	pThis->cas = 0;
3464	switch (offPort)
3465	{
3466	case AC97_Reset:
3467	#ifdef IN_RING3
3468	ichac97R3Reset(pDevIns);
3469	#else
3470	rc = VINF_IOM_R3_IOPORT_WRITE;
3471	#endif
3472	break;
3473	case AC97_Powerdown_Ctrl_Stat:
3474	u32 &= ~0xf;
3475	u32 \|= ichac97MixerGet(pThis, offPort) & 0xf;
3476	ichac97MixerSet(pThis, offPort, u32);
3477	break;
3478	case AC97_Master_Volume_Mute:
3479	if (pThis->enmCodecModel == AC97CODEC_AD1980)
3480	{
3481	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_LOSEL)
3482	break; /* Register controls surround (rear), do nothing. */
3483	}
3484	#ifdef IN_RING3
3485	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3486	#else
3487	rc = VINF_IOM_R3_IOPORT_WRITE;
3488	#endif
3489	break;
3490	case AC97_Headphone_Volume_Mute:
3491	if (pThis->enmCodecModel == AC97CODEC_AD1980)
3492	{
3493	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3494	{
3495	/* Register controls PCM (front) outputs. */
3496	#ifdef IN_RING3
3497	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3498	#else
3499	rc = VINF_IOM_R3_IOPORT_WRITE;
3500	#endif
3501	}
3502	}
3503	break;
3504	case AC97_PCM_Out_Volume_Mute:
3505	#ifdef IN_RING3
3506	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_FRONT, u32);
3507	#else
3508	rc = VINF_IOM_R3_IOPORT_WRITE;
3509	#endif
3510	break;
3511	case AC97_Line_In_Volume_Mute:
3512	#ifdef IN_RING3
3513	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3514	#else
3515	rc = VINF_IOM_R3_IOPORT_WRITE;
3516	#endif
3517	break;
3518	case AC97_Record_Select:
3519	#ifdef IN_RING3
3520	ichac97R3MixerRecordSelect(pThis, u32);
3521	#else
3522	rc = VINF_IOM_R3_IOPORT_WRITE;
3523	#endif
3524	break;
3525	case AC97_Record_Gain_Mute:
3526	#ifdef IN_RING3
3527	/* Newer Ubuntu guests rely on that when controlling gain and muting
3528	* the recording (capturing) levels. */
3529	ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3530	#else
3531	rc = VINF_IOM_R3_IOPORT_WRITE;
3532	#endif
3533	break;
3534	case AC97_Record_Gain_Mic_Mute:
3535	#ifdef IN_RING3
3536	/* Ditto; see note above. */
3537	ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_MIC_IN, u32);
3538	#else
3539	rc = VINF_IOM_R3_IOPORT_WRITE;
3540	#endif
3541	break;
3542	case AC97_Vendor_ID1:
3543	case AC97_Vendor_ID2:
3544	LogFunc(("Attempt to write vendor ID to %#x\n", u32));
3545	break;
3546	case AC97_Extended_Audio_ID:
3547	LogFunc(("Attempt to write extended audio ID to %#x\n", u32));
3548	break;
3549	case AC97_Extended_Audio_Ctrl_Stat:
3550	#ifdef IN_RING3
3551	/*
3552	* Handle VRA bits.
3553	*/
3554	if (!(u32 & AC97_EACS_VRA)) /* Check if VRA bit is not set. */
3555	{
3556	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 0xbb80); /* Set default (48000 Hz). */
3557	ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3558	&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3559
3560	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3561	ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3562	&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3563	}
3564	else
3565	LogRel2(("AC97: Variable rate audio (VRA) is not supported\n"));
3566
3567	/*
3568	* Handle VRM bits.
3569	*/
3570	if (!(u32 & AC97_EACS_VRM)) /* Check if VRM bit is not set. */
3571	{
3572	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3573	ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3574	&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3575	}
3576	else
3577	LogRel2(("AC97: Variable rate microphone audio (VRM) is not supported\n"));
3578
3579	LogRel2(("AC97: Setting extended audio control to %#x\n", u32));
3580	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32);
3581	#else /* !IN_RING3 */
3582	rc = VINF_IOM_R3_IOPORT_WRITE;
3583	#endif
3584	break;
3585	case AC97_PCM_Front_DAC_Rate: /* Output slots 3, 4, 6. */
3586	#ifdef IN_RING3
3587	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3588	{
3589	LogRel2(("AC97: Setting front DAC rate to 0x%x\n", u32));
3590	ichac97MixerSet(pThis, offPort, u32);
3591	ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3592	&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3593	}
3594	else
3595	LogRel2(("AC97: Setting front DAC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3596	#else
3597	rc = VINF_IOM_R3_IOPORT_WRITE;
3598	#endif
3599	break;
3600	case AC97_MIC_ADC_Rate: /* Input slot 6. */
3601	#ifdef IN_RING3
3602	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRM)
3603	{
3604	LogRel2(("AC97: Setting microphone ADC rate to 0x%x\n", u32));
3605	ichac97MixerSet(pThis, offPort, u32);
3606	ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3607	&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3608	}
3609	else
3610	LogRel2(("AC97: Setting microphone ADC rate (0x%x) when VRM is not set is forbidden, ignoring\n", u32));
3611	#else
3612	rc = VINF_IOM_R3_IOPORT_WRITE;
3613	#endif
3614	break;
3615	case AC97_PCM_LR_ADC_Rate: /* Input slots 3, 4. */
3616	#ifdef IN_RING3
3617	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3618	{
3619	LogRel2(("AC97: Setting line-in ADC rate to 0x%x\n", u32));
3620	ichac97MixerSet(pThis, offPort, u32);
3621	ichac97R3StreamReOpen(pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3622	&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3623	}
3624	else
3625	LogRel2(("AC97: Setting line-in ADC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3626	#else
3627	rc = VINF_IOM_R3_IOPORT_WRITE;
3628	#endif
3629	break;
3630	default:
3631	LogRel2(("AC97: Warning: Unimplemented NAMWrite (2 bytes) offPort=%#x <- %#x\n", offPort, u32));
3632	ichac97MixerSet(pThis, offPort, u32);
3633	break;
3634	}
3635	break;
3636	}
3637
3638	case 4:
3639	{
3640	LogRel2(("AC97: Warning: Unimplemented 4 byte NAMWrite: offPort=%#x <- %#x\n", offPort, u32));
3641	pThis->cas = 0;
3642	break;
3643	}
3644
3645	default:
3646	AssertMsgFailed(("Unhandled NAMWrite offPort=%#x, cb=%u u32=%#x\n", offPort, cb, u32));
3647	break;
3648	}
3649
3650	DEVAC97_UNLOCK(pDevIns, pThis);
3651	return rc;
3652	}
3653
3654	#ifdef IN_RING3
3655
3656	/**
3657	* Saves (serializes) an AC'97 stream using SSM.
3658	*
3659	* @param pDevIns Device instance.
3660	* @param pSSM Saved state manager (SSM) handle to use.
3661	* @param pStream AC'97 stream to save.
3662	*/
3663	static void ichac97R3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3664	{
3665	PAC97BMREGS pRegs = &pStream->Regs;
3666	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3667
3668	pHlp->pfnSSMPutU32(pSSM, pRegs->bdbar);
3669	pHlp->pfnSSMPutU8( pSSM, pRegs->civ);
3670	pHlp->pfnSSMPutU8( pSSM, pRegs->lvi);
3671	pHlp->pfnSSMPutU16(pSSM, pRegs->sr);
3672	pHlp->pfnSSMPutU16(pSSM, pRegs->picb);
3673	pHlp->pfnSSMPutU8( pSSM, pRegs->piv);
3674	pHlp->pfnSSMPutU8( pSSM, pRegs->cr);
3675	pHlp->pfnSSMPutS32(pSSM, pRegs->bd_valid);
3676	pHlp->pfnSSMPutU32(pSSM, pRegs->bd.addr);
3677	pHlp->pfnSSMPutU32(pSSM, pRegs->bd.ctl_len);
3678	}
3679
3680	/**
3681	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3682	*/
3683	static DECLCALLBACK(int) ichac97R3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3684	{
3685	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3686	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3687	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3688	LogFlowFuncEnter();
3689
3690	pHlp->pfnSSMPutU32(pSSM, pThis->glob_cnt);
3691	pHlp->pfnSSMPutU32(pSSM, pThis->glob_sta);
3692	pHlp->pfnSSMPutU32(pSSM, pThis->cas);
3693
3694	/*
3695	* The order that the streams are saved here is fixed, so don't change.
3696	*/
3697	/** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
3698	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3699	ichac97R3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3700
3701	pHlp->pfnSSMPutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3702
3703	/* The stream order is against fixed and set in stone. */
3704	uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3705	afActiveStrms[AC97SOUNDSOURCE_PI_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX]);
3706	afActiveStrms[AC97SOUNDSOURCE_PO_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX]);
3707	afActiveStrms[AC97SOUNDSOURCE_MC_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX]);
3708	AssertCompile(RT_ELEMENTS(afActiveStrms) == 3);
3709	pHlp->pfnSSMPutMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3710
3711	LogFlowFuncLeaveRC(VINF_SUCCESS);
3712	return VINF_SUCCESS;
3713	}
3714
3715	/**
3716	* Loads an AC'97 stream from SSM.
3717	*
3718	* @returns IPRT status code.
3719	* @param pDevIns The device instance.
3720	* @param pSSM Saved state manager (SSM) handle to use.
3721	* @param pStream AC'97 stream to load.
3722	*/
3723	static int ichac97R3LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3724	{
3725	PAC97BMREGS pRegs = &pStream->Regs;
3726	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3727
3728	pHlp->pfnSSMGetU32(pSSM, &pRegs->bdbar);
3729	pHlp->pfnSSMGetU8( pSSM, &pRegs->civ);
3730	pHlp->pfnSSMGetU8( pSSM, &pRegs->lvi);
3731	pHlp->pfnSSMGetU16(pSSM, &pRegs->sr);
3732	pHlp->pfnSSMGetU16(pSSM, &pRegs->picb);
3733	pHlp->pfnSSMGetU8( pSSM, &pRegs->piv);
3734	pHlp->pfnSSMGetU8( pSSM, &pRegs->cr);
3735	pHlp->pfnSSMGetS32(pSSM, &pRegs->bd_valid);
3736	pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.addr);
3737	return pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.ctl_len);
3738	}
3739
3740	/**
3741	* @callback_method_impl{FNSSMDEVLOADEXEC}
3742	*/
3743	static DECLCALLBACK(int) ichac97R3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3744	{
3745	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3746	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3747	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3748
3749	LogRel2(("ichac97LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3750
3751	AssertMsgReturn (uVersion == AC97_SAVED_STATE_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3752	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3753
3754	pHlp->pfnSSMGetU32(pSSM, &pThis->glob_cnt);
3755	pHlp->pfnSSMGetU32(pSSM, &pThis->glob_sta);
3756	pHlp->pfnSSMGetU32(pSSM, &pThis->cas);
3757
3758	/*
3759	* The order the streams are loaded here is critical (defined by
3760	* AC97SOUNDSOURCE_XX_INDEX), so don't touch!
3761	*/
3762	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3763	{
3764	int rc2 = ichac97R3LoadStream(pDevIns, pSSM, &pThis->aStreams[i]);
3765	AssertRCReturn(rc2, rc2);
3766	}
3767
3768	pHlp->pfnSSMGetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3769
3770	ichac97R3MixerRecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
3771	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3772	ichac97MixerGet(pThis, AC97_Master_Volume_Mute));
3773	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT,
3774	ichac97MixerGet(pThis, AC97_PCM_Out_Volume_Mute));
3775	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3776	ichac97MixerGet(pThis, AC97_Line_In_Volume_Mute));
3777	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3778	ichac97MixerGet(pThis, AC97_Mic_Volume_Mute));
3779	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3780	ichac97MixerGet(pThis, AC97_Record_Gain_Mic_Mute));
3781	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3782	ichac97MixerGet(pThis, AC97_Record_Gain_Mute));
3783	if (pThis->enmCodecModel == AC97CODEC_AD1980)
3784	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3785	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3786	ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
3787
3788	/*
3789	* Again the stream order is set is stone.
3790	*/
3791	uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3792	int rc2 = pHlp->pfnSSMGetMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3793	AssertRCReturn(rc2, rc2);
3794
3795	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3796	{
3797	const bool fEnable = RT_BOOL(afActiveStrms[i]);
3798	const PAC97STREAM pStream = &pThis->aStreams[i];
3799	const PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[i];
3800
3801	rc2 = ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, fEnable);
3802	AssertRC(rc2);
3803	if ( fEnable
3804	&& RT_SUCCESS(rc2))
3805	{
3806	/* Re-arm the timer for this stream. */
3807	/** @todo r=aeichner This causes a VM hang upon saved state resume when NetBSD is used as a guest
3808	* Stopping the timer if cTransferTicks is 0 is a workaround but needs further investigation,
3809	* see @bugref{9759} for more information. */
3810	if (pStreamCC->State.cTransferTicks)
3811	ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3812	else
3813	PDMDevHlpTimerStop(pDevIns, pStream->hTimer);
3814	}
3815
3816	/* Keep going. */
3817	}
3818
3819	pThis->bup_flag = 0;
3820	pThis->last_samp = 0;
3821
3822	return VINF_SUCCESS;
3823	}
3824
3825
3826	/**
3827	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3828	*/
3829	static DECLCALLBACK(void ) ichac97R3QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
3830	{
3831	PAC97STATER3 pThisCC = RT_FROM_MEMBER(pInterface, AC97STATER3, IBase);
3832	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
3833	return NULL;
3834	}
3835
3836
3837	/**
3838	* Powers off the device.
3839	*
3840	* @param pDevIns Device instance to power off.
3841	*/
3842	static DECLCALLBACK(void) ichac97R3PowerOff(PPDMDEVINS pDevIns)
3843	{
3844	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3845	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3846
3847	LogRel2(("AC97: Powering off ...\n"));
3848
3849	/* Note: Involves mixer stream / sink destruction, so also do this here
3850	* instead of in ichac97R3Destruct(). */
3851	ichac97R3StreamsDestroy(pThis, pThisCC);
3852
3853	/*
3854	* Note: Destroy the mixer while powering off and not in ichac97R3Destruct,
3855	* giving the mixer the chance to release any references held to
3856	* PDM audio streams it maintains.
3857	*/
3858	if (pThisCC->pMixer)
3859	{
3860	AudioMixerDestroy(pThisCC->pMixer);
3861	pThisCC->pMixer = NULL;
3862	}
3863	}
3864
3865
3866	/**
3867	* @interface_method_impl{PDMDEVREG,pfnReset}
3868	*
3869	* @remarks The original sources didn't install a reset handler, but it seems to
3870	* make sense to me so we'll do it.
3871	*/
3872	static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns)
3873	{
3874	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3875	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3876
3877	LogRel(("AC97: Reset\n"));
3878
3879	/*
3880	* Reset the mixer too. The Windows XP driver seems to rely on
3881	* this. At least it wants to read the vendor id before it resets
3882	* the codec manually.
3883	*/
3884	ichac97R3MixerReset(pThis, pThisCC);
3885
3886	/*
3887	* Reset all streams.
3888	*/
3889	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3890	{
3891	ichac97R3StreamEnable(pThis, pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], false /* fEnable */);
3892	ichac97R3StreamReset(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
3893	}
3894
3895	/*
3896	* Reset mixer sinks.
3897	*
3898	* Do the reset here instead of in ichac97R3StreamReset();
3899	* the mixer sink(s) might still have data to be processed when an audio stream gets reset.
3900	*/
3901	AudioMixerSinkReset(pThisCC->pSinkLineIn);
3902	AudioMixerSinkReset(pThisCC->pSinkMicIn);
3903	AudioMixerSinkReset(pThisCC->pSinkOut);
3904	}
3905
3906
3907	/**
3908	* Attach command, internal version.
3909	*
3910	* This is called to let the device attach to a driver for a specified LUN
3911	* during runtime. This is not called during VM construction, the device
3912	* constructor has to attach to all the available drivers.
3913	*
3914	* @returns VBox status code.
3915	* @param pDevIns The device instance.
3916	* @param pThisCC The ring-3 AC'97 device state.
3917	* @param iLun The logical unit which is being attached.
3918	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3919	* @param ppDrv Attached driver instance on success. Optional.
3920	*/
3921	static int ichac97R3AttachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned iLun, uint32_t fFlags, PAC97DRIVER *ppDrv)
3922	{
3923	RT_NOREF(fFlags);
3924
3925	/*
3926	* Attach driver.
3927	*/
3928	char *pszDesc;
3929	if (RTStrAPrintf(&pszDesc, "Audio driver port (AC'97) for LUN #%u", iLun) <= 0)
3930	AssertLogRelFailedReturn(VERR_NO_MEMORY);
3931
3932	PPDMIBASE pDrvBase;
3933	int rc = PDMDevHlpDriverAttach(pDevIns, iLun, &pThisCC->IBase, &pDrvBase, pszDesc);
3934	if (RT_SUCCESS(rc))
3935	{
3936	PAC97DRIVER pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
3937	if (pDrv)
3938	{
3939	pDrv->pDrvBase = pDrvBase;
3940	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
3941	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN #%u has no host audio interface, rc=%Rrc\n", iLun, rc));
3942	pDrv->uLUN = iLun;
3943	pDrv->pszDesc = pszDesc;
3944
3945	/*
3946	* For now we always set the driver at LUN 0 as our primary
3947	* host backend. This might change in the future.
3948	*/
3949	if (iLun == 0)
3950	pDrv->fFlags \|= PDMAUDIODRVFLAGS_PRIMARY;
3951
3952	LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", iLun, pDrv->pConnector, pDrv->fFlags));
3953
3954	/* Attach to driver list if not attached yet. */
3955	if (!pDrv->fAttached)
3956	{
3957	RTListAppend(&pThisCC->lstDrv, &pDrv->Node);
3958	pDrv->fAttached = true;
3959	}
3960
3961	if (ppDrv)
3962	*ppDrv = pDrv;
3963	}
3964	else
3965	rc = VERR_NO_MEMORY;
3966	}
3967	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3968	LogFunc(("No attached driver for LUN #%u\n", iLun));
3969
3970	if (RT_FAILURE(rc))
3971	{
3972	/* Only free this string on failure;
3973	* must remain valid for the live of the driver instance. */
3974	RTStrFree(pszDesc);
3975	}
3976
3977	LogFunc(("iLun=%u, fFlags=0x%x, rc=%Rrc\n", iLun, fFlags, rc));
3978	return rc;
3979	}
3980
3981	/**
3982	* Detach command, internal version.
3983	*
3984	* This is called to let the device detach from a driver for a specified LUN
3985	* during runtime.
3986	*
3987	* @returns VBox status code.
3988	* @param pThisCC The ring-3 AC'97 device state.
3989	* @param pDrv Driver to detach from device.
3990	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3991	*/
3992	static int ichac97R3DetachInternal(PAC97STATER3 pThisCC, PAC97DRIVER pDrv, uint32_t fFlags)
3993	{
3994	RT_NOREF(fFlags);
3995
3996	/* First, remove the driver from our list and destory it's associated streams.
3997	* This also will un-set the driver as a recording source (if associated). */
3998	ichac97R3MixerRemoveDrv(pThisCC, pDrv);
3999
4000	/* Next, search backwards for a capable (attached) driver which now will be the
4001	* new recording source. */
4002	PDMAUDIODSTSRCUNION dstSrc;
4003	PAC97DRIVER pDrvCur;
4004	RTListForEachReverse(&pThisCC->lstDrv, pDrvCur, AC97DRIVER, Node)
4005	{
4006	if (!pDrvCur->pConnector)
4007	continue;
4008
4009	PDMAUDIOBACKENDCFG Cfg;
4010	int rc2 = pDrvCur->pConnector->pfnGetConfig(pDrvCur->pConnector, &Cfg);
4011	if (RT_FAILURE(rc2))
4012	continue;
4013
4014	dstSrc.enmSrc = PDMAUDIORECSRC_MIC;
4015	PAC97DRIVERSTREAM pDrvStrm = ichac97R3MixerGetDrvStream(pDrvCur, PDMAUDIODIR_IN, dstSrc);
4016	if ( pDrvStrm
4017	&& pDrvStrm->pMixStrm)
4018	{
4019	rc2 = AudioMixerSinkSetRecordingSource(pThisCC->pSinkMicIn, pDrvStrm->pMixStrm);
4020	if (RT_SUCCESS(rc2))
4021	LogRel2(("AC97: Set new recording source for 'Mic In' to '%s'\n", Cfg.szName));
4022	}
4023
4024	dstSrc.enmSrc = PDMAUDIORECSRC_LINE;
4025	pDrvStrm = ichac97R3MixerGetDrvStream(pDrvCur, PDMAUDIODIR_IN, dstSrc);
4026	if ( pDrvStrm
4027	&& pDrvStrm->pMixStrm)
4028	{
4029	rc2 = AudioMixerSinkSetRecordingSource(pThisCC->pSinkLineIn, pDrvStrm->pMixStrm);
4030	if (RT_SUCCESS(rc2))
4031	LogRel2(("AC97: Set new recording source for 'Line In' to '%s'\n", Cfg.szName));
4032	}
4033	}
4034
4035	LogFunc(("uLUN=%u, fFlags=0x%x\n", pDrv->uLUN, fFlags));
4036	return VINF_SUCCESS;
4037	}
4038
4039	/**
4040	* @interface_method_impl{PDMDEVREGR3,pfnAttach}
4041	*/
4042	static DECLCALLBACK(int) ichac97R3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4043	{
4044	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4045	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4046
4047	LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
4048
4049	DEVAC97_LOCK(pDevIns, pThis);
4050
4051	PAC97DRIVER pDrv;
4052	int rc2 = ichac97R3AttachInternal(pDevIns, pThisCC, iLUN, fFlags, &pDrv);
4053	if (RT_SUCCESS(rc2))
4054	rc2 = ichac97R3MixerAddDrv(pThisCC, pDrv);
4055
4056	if (RT_FAILURE(rc2))
4057	LogFunc(("Failed with %Rrc\n", rc2));
4058
4059	DEVAC97_UNLOCK(pDevIns, pThis);
4060
4061	return VINF_SUCCESS;
4062	}
4063
4064	/**
4065	* @interface_method_impl{PDMDEVREG,pfnDetach}
4066	*/
4067	static DECLCALLBACK(void) ichac97R3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4068	{
4069	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4070	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4071
4072	LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
4073
4074	DEVAC97_LOCK(pDevIns, pThis);
4075
4076	PAC97DRIVER pDrv, pDrvNext;
4077	RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
4078	{
4079	if (pDrv->uLUN == iLUN)
4080	{
4081	int rc2 = ichac97R3DetachInternal(pThisCC, pDrv, fFlags);
4082	if (RT_SUCCESS(rc2))
4083	{
4084	RTStrFree(pDrv->pszDesc);
4085	RTMemFree(pDrv);
4086	pDrv = NULL;
4087	}
4088
4089	break;
4090	}
4091	}
4092
4093	DEVAC97_UNLOCK(pDevIns, pThis);
4094	}
4095
4096	/**
4097	* Replaces a driver with a the NullAudio drivers.
4098	*
4099	* @returns VBox status code.
4100	* @param pDevIns The device instance.
4101	* @param pThisCC The ring-3 AC'97 device state.
4102	* @param iLun The logical unit which is being replaced.
4103	*/
4104	static int ichac97R3ReconfigLunWithNullAudio(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned iLun)
4105	{
4106	int rc = PDMDevHlpDriverReconfigure2(pDevIns, iLun, "AUDIO", "NullAudio");
4107	if (RT_SUCCESS(rc))
4108	rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, 0 /* fFlags /, NULL / ppDrv */);
4109	LogFunc(("pThisCC=%p, iLun=%u, rc=%Rrc\n", pThisCC, iLun, rc));
4110	return rc;
4111	}
4112
4113	/**
4114	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4115	*/
4116	static DECLCALLBACK(int) ichac97R3Destruct(PPDMDEVINS pDevIns)
4117	{
4118	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4119	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4120
4121	LogFlowFuncEnter();
4122
4123	PAC97DRIVER pDrv, pDrvNext;
4124	RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
4125	{
4126	RTListNodeRemove(&pDrv->Node);
4127	RTMemFree(pDrv->pszDesc);
4128	RTMemFree(pDrv);
4129	}
4130
4131	/* Sanity. */
4132	Assert(RTListIsEmpty(&pThisCC->lstDrv));
4133
4134	return VINF_SUCCESS;
4135	}
4136
4137	/**
4138	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4139	*/
4140	static DECLCALLBACK(int) ichac97R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4141	{
4142	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4143	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4144	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4145	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4146	Assert(iInstance == 0); RT_NOREF(iInstance);
4147
4148	/*
4149	* Initialize data so we can run the destructor without scewing up.
4150	*/
4151	pThisCC->pDevIns = pDevIns;
4152	pThisCC->IBase.pfnQueryInterface = ichac97R3QueryInterface;
4153	RTListInit(&pThisCC->lstDrv);
4154
4155	/*
4156	* Validate and read configuration.
4157	*/
4158	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Codec\|TimerHz\|DebugEnabled\|DebugPathOut", "");
4159
4160	char szCodec[20];
4161	int rc = pHlp->pfnCFGMQueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
4162	if (RT_FAILURE(rc))
4163	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4164	N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
4165
4166	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, AC97_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4167	if (RT_FAILURE(rc))
4168	return PDMDEV_SET_ERROR(pDevIns, rc,
4169	N_("AC'97 configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4170
4171	if (pThis->uTimerHz != AC97_TIMER_HZ_DEFAULT)
4172	LogRel(("AC97: Using custom device timer rate (%RU16Hz)\n", pThis->uTimerHz));
4173
4174	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "DebugEnabled", &pThisCC->Dbg.fEnabled, false);
4175	if (RT_FAILURE(rc))
4176	return PDMDEV_SET_ERROR(pDevIns, rc,
4177	N_("AC97 configuration error: failed to read debugging enabled flag as boolean"));
4178
4179	rc = pHlp->pfnCFGMQueryStringAllocDef(pCfg, "DebugPathOut", &pThisCC->Dbg.pszOutPath, NULL);
4180	if (RT_FAILURE(rc))
4181	return PDMDEV_SET_ERROR(pDevIns, rc,
4182	N_("AC97 configuration error: failed to read debugging output path flag as string"));
4183
4184	if (pThisCC->Dbg.fEnabled)
4185	LogRel2(("AC97: Debug output will be saved to '%s'\n", pThisCC->Dbg.pszOutPath));
4186
4187	/*
4188	* The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
4189	* in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
4190	* 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
4191	*/
4192	if (!strcmp(szCodec, "STAC9700"))
4193	pThis->enmCodecModel = AC97CODEC_STAC9700;
4194	else if (!strcmp(szCodec, "AD1980"))
4195	pThis->enmCodecModel = AC97CODEC_AD1980;
4196	else if (!strcmp(szCodec, "AD1981B"))
4197	pThis->enmCodecModel = AC97CODEC_AD1981B;
4198	else
4199	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
4200	N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"), szCodec);
4201
4202	LogRel(("AC97: Using codec '%s'\n", szCodec));
4203
4204	/*
4205	* Use an own critical section for the device instead of the default
4206	* one provided by PDM. This allows fine-grained locking in combination
4207	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4208	*/
4209	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "AC'97");
4210	AssertRCReturn(rc, rc);
4211
4212	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4213	AssertRCReturn(rc, rc);
4214
4215	/*
4216	* Initialize data (most of it anyway).
4217	*/
4218	/* PCI Device */
4219	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4220	PCIDevSetVendorId(pPciDev, 0x8086); /* 00 ro - intel. */ Assert(pPciDev->abConfig[0x00] == 0x86); Assert(pPciDev->abConfig[0x01] == 0x80);
4221	PCIDevSetDeviceId(pPciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pPciDev->abConfig[0x02] == 0x15); Assert(pPciDev->abConfig[0x03] == 0x24);
4222	PCIDevSetCommand(pPciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pPciDev->abConfig[0x04] == 0x00); Assert(pPciDev->abConfig[0x05] == 0x00);
4223	PCIDevSetStatus(pPciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM \| VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pPciDev->abConfig[0x06] == 0x80); Assert(pPciDev->abConfig[0x07] == 0x02);
4224	PCIDevSetRevisionId(pPciDev, 0x01); /* 08 ro - rid. */ Assert(pPciDev->abConfig[0x08] == 0x01);
4225	PCIDevSetClassProg(pPciDev, 0x00); /* 09 ro - pi. */ Assert(pPciDev->abConfig[0x09] == 0x00);
4226	PCIDevSetClassSub(pPciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pPciDev->abConfig[0x0a] == 0x01);
4227	PCIDevSetClassBase(pPciDev, 0x04); /* 0b ro - bcc; 04 == multimedia.*/Assert(pPciDev->abConfig[0x0b] == 0x04);
4228	PCIDevSetHeaderType(pPciDev, 0x00); /* 0e ro - headtyp. */ Assert(pPciDev->abConfig[0x0e] == 0x00);
4229	PCIDevSetBaseAddress(pPciDev, 0, /* 10 rw - nambar - native audio mixer base. */
4230	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x10] == 0x01); Assert(pPciDev->abConfig[0x11] == 0x00); Assert(pPciDev->abConfig[0x12] == 0x00); Assert(pPciDev->abConfig[0x13] == 0x00);
4231	PCIDevSetBaseAddress(pPciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
4232	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x14] == 0x01); Assert(pPciDev->abConfig[0x15] == 0x00); Assert(pPciDev->abConfig[0x16] == 0x00); Assert(pPciDev->abConfig[0x17] == 0x00);
4233	PCIDevSetInterruptLine(pPciDev, 0x00); /* 3c rw. */ Assert(pPciDev->abConfig[0x3c] == 0x00);
4234	PCIDevSetInterruptPin(pPciDev, 0x01); /* 3d ro - INTA#. */ Assert(pPciDev->abConfig[0x3d] == 0x01);
4235
4236	if (pThis->enmCodecModel == AC97CODEC_AD1980)
4237	{
4238	PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4239	PCIDevSetSubSystemId(pPciDev, 0x0177); /* 2e ro. */
4240	}
4241	else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
4242	{
4243	PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4244	PCIDevSetSubSystemId(pPciDev, 0x01ad); /* 2e ro. */
4245	}
4246	else
4247	{
4248	PCIDevSetSubSystemVendorId(pPciDev, 0x8086); /* 2c ro - Intel.) */
4249	PCIDevSetSubSystemId(pPciDev, 0x0000); /* 2e ro. */
4250	}
4251
4252	/*
4253	* Register the PCI device and associated I/O regions.
4254	*/
4255	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4256	if (RT_FAILURE(rc))
4257	return rc;
4258
4259	rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 0 /iPciRegion/, 256 /cPorts/,
4260	ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /pvUser/,
4261	"ICHAC97 NAM", NULL /paExtDescs/, &pThis->hIoPortsNam);
4262	AssertRCReturn(rc, rc);
4263
4264	rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 1 /iPciRegion/, 64 /cPorts/,
4265	ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /pvUser/,
4266	"ICHAC97 NABM", g_aNabmPorts, &pThis->hIoPortsNabm);
4267	AssertRCReturn(rc, rc);
4268
4269	/*
4270	* Saved state.
4271	*/
4272	rc = PDMDevHlpSSMRegister(pDevIns, AC97_SAVED_STATE_VERSION, sizeof(*pThis), ichac97R3SaveExec, ichac97R3LoadExec);
4273	if (RT_FAILURE(rc))
4274	return rc;
4275
4276	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
4277	LogRel(("AC97: Asynchronous I/O enabled\n"));
4278	# endif
4279
4280	/*
4281	* Attach drivers. We ASSUME they are configured consecutively without any
4282	* gaps, so we stop when we hit the first LUN w/o a driver configured.
4283	*/
4284	for (unsigned iLun = 0; ; iLun++)
4285	{
4286	AssertBreak(iLun < UINT8_MAX);
4287	LogFunc(("Trying to attach driver for LUN#%u ...\n", iLun));
4288	rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, 0 /* fFlags /, NULL / ppDrv */);
4289	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4290	{
4291	LogFunc(("cLUNs=%u\n", iLun));
4292	break;
4293	}
4294	if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
4295	{
4296	ichac97R3ReconfigLunWithNullAudio(pDevIns, pThisCC, iLun); /* Pretend attaching to the NULL audio backend will never fail. */
4297	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4298	N_("Host audio backend initialization has failed. "
4299	"Selecting the NULL audio backend with the consequence that no sound is audible"));
4300	}
4301	else
4302	AssertLogRelMsgReturn(RT_SUCCESS(rc), ("LUN#%u: rc=%Rrc\n", iLun, rc), rc);
4303	}
4304
4305	uint32_t fMixer = AUDMIXER_FLAGS_NONE;
4306	if (pThisCC->Dbg.fEnabled)
4307	fMixer \|= AUDMIXER_FLAGS_DEBUG;
4308
4309	rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThisCC->pMixer);
4310	AssertRCReturn(rc, rc);
4311
4312	rc = AudioMixerCreateSink(pThisCC->pMixer, "[Recording] Line In", AUDMIXSINKDIR_INPUT, &pThisCC->pSinkLineIn);
4313	AssertRCReturn(rc, rc);
4314	rc = AudioMixerCreateSink(pThisCC->pMixer, "[Recording] Microphone In", AUDMIXSINKDIR_INPUT, &pThisCC->pSinkMicIn);
4315	AssertRCReturn(rc, rc);
4316	rc = AudioMixerCreateSink(pThisCC->pMixer, "[Playback] PCM Output", AUDMIXSINKDIR_OUTPUT, &pThisCC->pSinkOut);
4317	AssertRCReturn(rc, rc);
4318
4319	/*
4320	* Create all hardware streams.
4321	*/
4322	AssertCompile(RT_ELEMENTS(pThis->aStreams) == AC97_MAX_STREAMS);
4323	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4324	{
4325	rc = ichac97R3StreamCreate(pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], i /* SD# */);
4326	AssertRCReturn(rc, rc);
4327	}
4328
4329	/*
4330	* Create the emulation timers (one per stream).
4331	*
4332	* We must the critical section for the timers as the device has a
4333	* noop section associated with it.
4334	*
4335	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's AC'97 driver
4336	* relies on exact (virtual) DMA timing and uses DMA Position Buffers
4337	* instead of the LPIB registers.
4338	*/
4339	/** @todo r=bird: The need to use virtual sync is perhaps because TM
4340	* doesn't schedule regular TMCLOCK_VIRTUAL timers as accurately as it
4341	* should (VT-x preemption timer, etc). Hope to address that before
4342	* long. @bugref{9943}. */
4343	static const char * const s_apszNames[] = { "AC97 PI", "AC97 PO", "AC97 MC" };
4344	AssertCompile(RT_ELEMENTS(s_apszNames) == AC97_MAX_STREAMS);
4345	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4346	{
4347	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, ichac97R3Timer, &pThis->aStreams[i],
4348	TMTIMER_FLAGS_NO_CRIT_SECT \| TMTIMER_FLAGS_RING0, s_apszNames[i], &pThis->aStreams[i].hTimer);
4349	AssertRCReturn(rc, rc);
4350
4351	rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->aStreams[i].hTimer, &pThis->CritSect);
4352	AssertRCReturn(rc, rc);
4353	}
4354
4355
4356	# ifdef VBOX_WITH_AUDIO_AC97_ONETIME_INIT
4357	PAC97DRIVER pDrv;
4358	RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
4359	{
4360	/*
4361	* Only primary drivers are critical for the VM to run. Everything else
4362	* might not worth showing an own error message box in the GUI.
4363	*/
4364	if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
4365	continue;
4366
4367	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
4368	AssertPtr(pCon);
4369
4370	bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
4371	bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
4372	bool fValidOut = AudioMixerStreamIsValid(pDrv->Out.pMixStrm);
4373
4374	if ( !fValidLineIn
4375	&& !fValidMicIn
4376	&& !fValidOut)
4377	{
4378	LogRel(("AC97: Falling back to NULL backend (no sound audible)\n"));
4379	ichac97R3Reset(pDevIns);
4380	ichac97R3ReconfigLunWithNullAudio(pdEvIns, pThsiCC, iLun);
4381	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4382	N_("No audio devices could be opened. "
4383	"Selecting the NULL audio backend with the consequence that no sound is audible"));
4384	}
4385	else
4386	{
4387	bool fWarn = false;
4388
4389	PDMAUDIOBACKENDCFG backendCfg;
4390	int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
4391	if (RT_SUCCESS(rc2))
4392	{
4393	if (backendCfg.cMaxStreamsIn)
4394	{
4395	/* If the audio backend supports two or more input streams at once,
4396	* warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
4397	if (backendCfg.cMaxStreamsIn >= 2)
4398	fWarn = !fValidLineIn \|\| !fValidMicIn;
4399	/* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
4400	* not ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
4401	* One of the two simply is not in use then. */
4402	else if (backendCfg.cMaxStreamsIn == 1)
4403	fWarn = !fValidLineIn && !fValidMicIn;
4404	/* Don't warn if our backend is not able of supporting any input streams at all. */
4405	}
4406
4407	if ( !fWarn
4408	&& backendCfg.cMaxStreamsOut)
4409	{
4410	fWarn = !fValidOut;
4411	}
4412	}
4413	else
4414	{
4415	LogRel(("AC97: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
4416	fWarn = true;
4417	}
4418
4419	if (fWarn)
4420	{
4421	char szMissingStreams[255] = "";
4422	size_t len = 0;
4423	if (!fValidLineIn)
4424	{
4425	LogRel(("AC97: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
4426	len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
4427	}
4428	if (!fValidMicIn)
4429	{
4430	LogRel(("AC97: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
4431	len += RTStrPrintf(szMissingStreams + len,
4432	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
4433	}
4434	if (!fValidOut)
4435	{
4436	LogRel(("AC97: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
4437	len += RTStrPrintf(szMissingStreams + len,
4438	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
4439	}
4440
4441	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4442	N_("Some AC'97 audio streams (%s) could not be opened. Guest applications generating audio "
4443	"output or depending on audio input may hang. Make sure your host audio device "
4444	"is working properly. Check the logfile for error messages of the audio "
4445	"subsystem"), szMissingStreams);
4446	}
4447	}
4448	}
4449	# endif /* VBOX_WITH_AUDIO_AC97_ONETIME_INIT */
4450
4451	ichac97R3Reset(pDevIns);
4452
4453	/*
4454	* Register statistics.
4455	*/
4456	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmReads, STAMTYPE_COUNTER, "UnimplementedNabmReads", STAMUNIT_OCCURENCES, "Unimplemented NABM register reads.");
4457	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmWrites, STAMTYPE_COUNTER, "UnimplementedNabmWrites", STAMUNIT_OCCURENCES, "Unimplemented NABM register writes.");
4458	# ifdef VBOX_WITH_STATISTICS
4459	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
4460	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
4461	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
4462	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
4463	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
4464	# endif
4465
4466	LogFlowFuncLeaveRC(VINF_SUCCESS);
4467	return VINF_SUCCESS;
4468	}
4469
4470	#else /* !IN_RING3 */
4471
4472	/**
4473	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4474	*/
4475	static DECLCALLBACK(int) ichac97RZConstruct(PPDMDEVINS pDevIns)
4476	{
4477	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4478	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4479
4480	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4481	AssertRCReturn(rc, rc);
4482
4483	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNam, ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /pvUser/);
4484	AssertRCReturn(rc, rc);
4485	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNabm, ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /pvUser/);
4486	AssertRCReturn(rc, rc);
4487
4488	return VINF_SUCCESS;
4489	}
4490
4491	#endif /* !IN_RING3 */
4492
4493	/**
4494	* The device registration structure.
4495	*/
4496	const PDMDEVREG g_DeviceICHAC97 =
4497	{
4498	/* .u32Version = */ PDM_DEVREG_VERSION,
4499	/* .uReserved0 = */ 0,
4500	/* .szName = */ "ichac97",
4501	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
4502	/* .fClass = */ PDM_DEVREG_CLASS_AUDIO,
4503	/* .cMaxInstances = */ 1,
4504	/* .uSharedVersion = */ 42,
4505	/* .cbInstanceShared = */ sizeof(AC97STATE),
4506	/* .cbInstanceCC = */ CTX_EXPR(sizeof(AC97STATER3), 0, 0),
4507	/* .cbInstanceRC = */ 0,
4508	/* .cMaxPciDevices = */ 1,
4509	/* .cMaxMsixVectors = */ 0,
4510	/* .pszDescription = */ "ICH AC'97 Audio Controller",
4511	#if defined(IN_RING3)
4512	/* .pszRCMod = */ "VBoxDDRC.rc",
4513	/* .pszR0Mod = */ "VBoxDDR0.r0",
4514	/* .pfnConstruct = */ ichac97R3Construct,
4515	/* .pfnDestruct = */ ichac97R3Destruct,
4516	/* .pfnRelocate = */ NULL,
4517	/* .pfnMemSetup = */ NULL,
4518	/* .pfnPowerOn = */ NULL,
4519	/* .pfnReset = */ ichac97R3Reset,
4520	/* .pfnSuspend = */ NULL,
4521	/* .pfnResume = */ NULL,
4522	/* .pfnAttach = */ ichac97R3Attach,
4523	/* .pfnDetach = */ ichac97R3Detach,
4524	/* .pfnQueryInterface = */ NULL,
4525	/* .pfnInitComplete = */ NULL,
4526	/* .pfnPowerOff = */ ichac97R3PowerOff,
4527	/* .pfnSoftReset = */ NULL,
4528	/* .pfnReserved0 = */ NULL,
4529	/* .pfnReserved1 = */ NULL,
4530	/* .pfnReserved2 = */ NULL,
4531	/* .pfnReserved3 = */ NULL,
4532	/* .pfnReserved4 = */ NULL,
4533	/* .pfnReserved5 = */ NULL,
4534	/* .pfnReserved6 = */ NULL,
4535	/* .pfnReserved7 = */ NULL,
4536	#elif defined(IN_RING0)
4537	/* .pfnEarlyConstruct = */ NULL,
4538	/* .pfnConstruct = */ ichac97RZConstruct,
4539	/* .pfnDestruct = */ NULL,
4540	/* .pfnFinalDestruct = */ NULL,
4541	/* .pfnRequest = */ NULL,
4542	/* .pfnReserved0 = */ NULL,
4543	/* .pfnReserved1 = */ NULL,
4544	/* .pfnReserved2 = */ NULL,
4545	/* .pfnReserved3 = */ NULL,
4546	/* .pfnReserved4 = */ NULL,
4547	/* .pfnReserved5 = */ NULL,
4548	/* .pfnReserved6 = */ NULL,
4549	/* .pfnReserved7 = */ NULL,
4550	#elif defined(IN_RC)
4551	/* .pfnConstruct = */ ichac97RZConstruct,
4552	/* .pfnReserved0 = */ NULL,
4553	/* .pfnReserved1 = */ NULL,
4554	/* .pfnReserved2 = */ NULL,
4555	/* .pfnReserved3 = */ NULL,
4556	/* .pfnReserved4 = */ NULL,
4557	/* .pfnReserved5 = */ NULL,
4558	/* .pfnReserved6 = */ NULL,
4559	/* .pfnReserved7 = */ NULL,
4560	#else
4561	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4562	#endif
4563	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
4564	};
4565
4566	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4567

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source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 88023

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