DevIchAc97.cpp@ 88908

Last change on this file since 88908 was 88908, checked in by vboxsync, 4 years ago
Audio/Dev*: Stream adding cleanup fixes. bugref:9890
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1	/* $Id: DevIchAc97.cpp 88908 2021-05-06 16:35:40Z vboxsync $ */
2	/** @file
3	* DevIchAc97 - VBox ICH AC97 Audio Controller.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_AC97
23	#include <VBox/log.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/vmm/pdmaudioifs.h>
26	#include <VBox/vmm/pdmaudioinline.h>
27
28	#include <iprt/assert.h>
29	#ifdef IN_RING3
30	# ifdef DEBUG
31	# include <iprt/file.h>
32	# endif
33	# include <iprt/mem.h>
34	# include <iprt/semaphore.h>
35	# include <iprt/string.h>
36	# include <iprt/uuid.h>
37	#endif
38
39	#include "VBoxDD.h"
40
41	#include "AudioMixBuffer.h"
42	#include "AudioMixer.h"
43	#include "AudioHlp.h"
44
45
46	/*********************************************************************************************************************************
47	* Defined Constants And Macros *
48	*********************************************************************************************************************************/
49
50	/** Current saved state version. */
51	#define AC97_SAVED_STATE_VERSION 1
52
53	/** Default timer frequency (in Hz). */
54	#define AC97_TIMER_HZ_DEFAULT 100
55
56	/** Maximum number of streams we support. */
57	#define AC97_MAX_STREAMS 3
58
59	/** Maximum FIFO size (in bytes). */
60	#define AC97_FIFO_MAX 256
61
62	#define AC97_SR_FIFOE RT_BIT(4) /*< rwc, FIFO error. /
63	#define AC97_SR_BCIS RT_BIT(3) /*< rwc, Buffer completion interrupt status. /
64	#define AC97_SR_LVBCI RT_BIT(2) /*< rwc, Last valid buffer completion interrupt. /
65	#define AC97_SR_CELV RT_BIT(1) /*< ro, Current equals last valid. /
66	#define AC97_SR_DCH RT_BIT(0) /*< ro, Controller halted. /
67	#define AC97_SR_VALID_MASK (RT_BIT(5) - 1)
68	#define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE \| AC97_SR_BCIS \| AC97_SR_LVBCI)
69	#define AC97_SR_RO_MASK (AC97_SR_DCH \| AC97_SR_CELV)
70	#define AC97_SR_INT_MASK (AC97_SR_FIFOE \| AC97_SR_BCIS \| AC97_SR_LVBCI)
71
72	#define AC97_CR_IOCE RT_BIT(4) /*< rw, Interrupt On Completion Enable. /
73	#define AC97_CR_FEIE RT_BIT(3) /*< rw FIFO Error Interrupt Enable. /
74	#define AC97_CR_LVBIE RT_BIT(2) /*< rw Last Valid Buffer Interrupt Enable. /
75	#define AC97_CR_RR RT_BIT(1) /*< rw Reset Registers. /
76	#define AC97_CR_RPBM RT_BIT(0) /*< rw Run/Pause Bus Master. /
77	#define AC97_CR_VALID_MASK (RT_BIT(5) - 1)
78	#define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE \| AC97_CR_FEIE \| AC97_CR_LVBIE)
79
80	#define AC97_GC_WR 4 /*< rw Warm reset. /
81	#define AC97_GC_CR 2 /*< rw Cold reset. /
82	#define AC97_GC_VALID_MASK (RT_BIT(6) - 1)
83
84	#define AC97_GS_MD3 RT_BIT(17) /*< rw /
85	#define AC97_GS_AD3 RT_BIT(16) /*< rw /
86	#define AC97_GS_RCS RT_BIT(15) /*< rwc /
87	#define AC97_GS_B3S12 RT_BIT(14) /*< ro /
88	#define AC97_GS_B2S12 RT_BIT(13) /*< ro /
89	#define AC97_GS_B1S12 RT_BIT(12) /*< ro /
90	#define AC97_GS_S1R1 RT_BIT(11) /*< rwc /
91	#define AC97_GS_S0R1 RT_BIT(10) /*< rwc /
92	#define AC97_GS_S1CR RT_BIT(9) /*< ro /
93	#define AC97_GS_S0CR RT_BIT(8) /*< ro /
94	#define AC97_GS_MINT RT_BIT(7) /*< ro /
95	#define AC97_GS_POINT RT_BIT(6) /*< ro /
96	#define AC97_GS_PIINT RT_BIT(5) /*< ro /
97	#define AC97_GS_RSRVD (RT_BIT(4) \| RT_BIT(3))
98	#define AC97_GS_MOINT RT_BIT(2) /*< ro /
99	#define AC97_GS_MIINT RT_BIT(1) /*< ro /
100	#define AC97_GS_GSCI RT_BIT(0) /*< rwc /
101	#define AC97_GS_RO_MASK ( AC97_GS_B3S12 \
102	\| AC97_GS_B2S12 \
103	\| AC97_GS_B1S12 \
104	\| AC97_GS_S1CR \
105	\| AC97_GS_S0CR \
106	\| AC97_GS_MINT \
107	\| AC97_GS_POINT \
108	\| AC97_GS_PIINT \
109	\| AC97_GS_RSRVD \
110	\| AC97_GS_MOINT \
111	\| AC97_GS_MIINT)
112	#define AC97_GS_VALID_MASK (RT_BIT(18) - 1)
113	#define AC97_GS_WCLEAR_MASK (AC97_GS_RCS \| AC97_GS_S1R1 \| AC97_GS_S0R1 \| AC97_GS_GSCI)
114
115	/** @name Buffer Descriptor (BD).
116	* @{ */
117	#define AC97_BD_IOC RT_BIT(31) /*< Interrupt on Completion. /
118	#define AC97_BD_BUP RT_BIT(30) /*< Buffer Underrun Policy. /
119
120	#define AC97_BD_LEN_MASK 0xFFFF /*< Mask for the BDL buffer length. /
121
122	#define AC97_MAX_BDLE 32 /*< Maximum number of BDLEs. /
123	/** @} */
124
125	/** @name Extended Audio ID Register (EAID).
126	* @{ */
127	#define AC97_EAID_VRA RT_BIT(0) /*< Variable Rate Audio. /
128	#define AC97_EAID_VRM RT_BIT(3) /*< Variable Rate Mic Audio. /
129	#define AC97_EAID_REV0 RT_BIT(10) /*< AC'97 revision compliance. /
130	#define AC97_EAID_REV1 RT_BIT(11) /*< AC'97 revision compliance. /
131	/** @} */
132
133	/** @name Extended Audio Control and Status Register (EACS).
134	* @{ */
135	#define AC97_EACS_VRA RT_BIT(0) /*< Variable Rate Audio (4.2.1.1). /
136	#define AC97_EACS_VRM RT_BIT(3) /*< Variable Rate Mic Audio (4.2.1.1). /
137	/** @} */
138
139	/** @name Baseline Audio Register Set (BARS).
140	* @{ */
141	#define AC97_BARS_VOL_MASK 0x1f /*< Volume mask for the Baseline Audio Register Set (5.7.2). /
142	#define AC97_BARS_GAIN_MASK 0x0f /*< Gain mask for the Baseline Audio Register Set. /
143	#define AC97_BARS_VOL_MUTE_SHIFT 15 /*< Mute bit shift for the Baseline Audio Register Set (5.7.2). /
144	/** @} */
145
146	/** AC'97 uses 1.5dB steps, we use 0.375dB steps: 1 AC'97 step equals 4 PDM steps. */
147	#define AC97_DB_FACTOR 4
148
149	/** @name Recording inputs?
150	* @{ */
151	#define AC97_REC_MIC UINT8_C(0)
152	#define AC97_REC_CD UINT8_C(1)
153	#define AC97_REC_VIDEO UINT8_C(2)
154	#define AC97_REC_AUX UINT8_C(3)
155	#define AC97_REC_LINE_IN UINT8_C(4)
156	#define AC97_REC_STEREO_MIX UINT8_C(5)
157	#define AC97_REC_MONO_MIX UINT8_C(6)
158	#define AC97_REC_PHONE UINT8_C(7)
159	#define AC97_REC_MASK UINT8_C(7)
160	/** @} */
161
162	/** @name Mixer registers / NAM BAR registers?
163	* @{ */
164	#define AC97_Reset 0x00
165	#define AC97_Master_Volume_Mute 0x02
166	#define AC97_Headphone_Volume_Mute 0x04 /*< Also known as AUX, see table 16, section 5.7. /
167	#define AC97_Master_Volume_Mono_Mute 0x06
168	#define AC97_Master_Tone_RL 0x08
169	#define AC97_PC_BEEP_Volume_Mute 0x0a
170	#define AC97_Phone_Volume_Mute 0x0c
171	#define AC97_Mic_Volume_Mute 0x0e
172	#define AC97_Line_In_Volume_Mute 0x10
173	#define AC97_CD_Volume_Mute 0x12
174	#define AC97_Video_Volume_Mute 0x14
175	#define AC97_Aux_Volume_Mute 0x16
176	#define AC97_PCM_Out_Volume_Mute 0x18
177	#define AC97_Record_Select 0x1a
178	#define AC97_Record_Gain_Mute 0x1c
179	#define AC97_Record_Gain_Mic_Mute 0x1e
180	#define AC97_General_Purpose 0x20
181	#define AC97_3D_Control 0x22
182	#define AC97_AC_97_RESERVED 0x24
183	#define AC97_Powerdown_Ctrl_Stat 0x26
184	#define AC97_Extended_Audio_ID 0x28
185	#define AC97_Extended_Audio_Ctrl_Stat 0x2a
186	#define AC97_PCM_Front_DAC_Rate 0x2c
187	#define AC97_PCM_Surround_DAC_Rate 0x2e
188	#define AC97_PCM_LFE_DAC_Rate 0x30
189	#define AC97_PCM_LR_ADC_Rate 0x32
190	#define AC97_MIC_ADC_Rate 0x34
191	#define AC97_6Ch_Vol_C_LFE_Mute 0x36
192	#define AC97_6Ch_Vol_L_R_Surround_Mute 0x38
193	#define AC97_Vendor_Reserved 0x58
194	#define AC97_AD_Misc 0x76
195	#define AC97_Vendor_ID1 0x7c
196	#define AC97_Vendor_ID2 0x7e
197	/** @} */
198
199	/** @name Analog Devices miscellaneous regiter bits used in AD1980.
200	* @{ */
201	#define AC97_AD_MISC_LOSEL RT_BIT(5) /*< Surround (rear) goes to line out outputs. /
202	#define AC97_AD_MISC_HPSEL RT_BIT(10) /*< PCM (front) goes to headphone outputs. /
203	/** @} */
204
205
206	/** @name BUP flag values.
207	* @{ */
208	#define BUP_SET RT_BIT_32(0)
209	#define BUP_LAST RT_BIT_32(1)
210	/** @} */
211
212	/** @name AC'97 source indices.
213	* @note The order of these indices is fixed (also applies for saved states) for
214	* the moment. So make sure you know what you're done when altering this!
215	* @{
216	*/
217	#define AC97SOUNDSOURCE_PI_INDEX 0 /*< PCM in /
218	#define AC97SOUNDSOURCE_PO_INDEX 1 /*< PCM out /
219	#define AC97SOUNDSOURCE_MC_INDEX 2 /*< Mic in /
220	#define AC97SOUNDSOURCE_MAX 3 /*< Max sound sources. /
221	/** @} */
222
223	/** Port number (offset into NABM BAR) to stream index. */
224	#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
225	/** Port number (offset into NABM BAR) to stream index, but no masking. */
226	#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
227
228	/** @name Stream offsets
229	* @{ */
230	#define AC97_NABM_OFF_BDBAR 0x0 /*< Buffer Descriptor Base Address /
231	#define AC97_NABM_OFF_CIV 0x4 /*< Current Index Value /
232	#define AC97_NABM_OFF_LVI 0x5 /*< Last Valid Index /
233	#define AC97_NABM_OFF_SR 0x6 /*< Status Register /
234	#define AC97_NABM_OFF_PICB 0x8 /*< Position in Current Buffer /
235	#define AC97_NABM_OFF_PIV 0xa /*< Prefetched Index Value /
236	#define AC97_NABM_OFF_CR 0xb /*< Control Register /
237	#define AC97_NABM_OFF_MASK 0xf /*< Mask for getting the the per-stream register. /
238	/** @} */
239
240
241	/** @name PCM in NABM BAR registers (0x00..0x0f).
242	* @{ */
243	#define PI_BDBAR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x0) /*< PCM in: Buffer Descriptor Base Address /
244	#define PI_CIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x4) /*< PCM in: Current Index Value /
245	#define PI_LVI (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x5) /*< PCM in: Last Valid Index /
246	#define PI_SR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x6) /*< PCM in: Status Register /
247	#define PI_PICB (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x8) /*< PCM in: Position in Current Buffer /
248	#define PI_PIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xa) /*< PCM in: Prefetched Index Value /
249	#define PI_CR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xb) /*< PCM in: Control Register /
250	/** @} */
251
252	/** @name PCM out NABM BAR registers (0x10..0x1f).
253	* @{ */
254	#define PO_BDBAR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x0) /*< PCM out: Buffer Descriptor Base Address /
255	#define PO_CIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x4) /*< PCM out: Current Index Value /
256	#define PO_LVI (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x5) /*< PCM out: Last Valid Index /
257	#define PO_SR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x6) /*< PCM out: Status Register /
258	#define PO_PICB (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x8) /*< PCM out: Position in Current Buffer /
259	#define PO_PIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xa) /*< PCM out: Prefetched Index Value /
260	#define PO_CR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xb) /*< PCM out: Control Register /
261	/** @} */
262
263	/** @name Mic in NABM BAR registers (0x20..0x2f).
264	* @{ */
265	#define MC_BDBAR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x0) /*< PCM in: Buffer Descriptor Base Address /
266	#define MC_CIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x4) /*< PCM in: Current Index Value /
267	#define MC_LVI (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x5) /*< PCM in: Last Valid Index /
268	#define MC_SR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x6) /*< PCM in: Status Register /
269	#define MC_PICB (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x8) /*< PCM in: Position in Current Buffer /
270	#define MC_PIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xa) /*< PCM in: Prefetched Index Value /
271	#define MC_CR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xb) /*< PCM in: Control Register /
272	/** @} */
273
274	/** @name Misc NABM BAR registers.
275	* @{ */
276	/** NABMBAR: Global Control Register.
277	* @note This is kind of in the MIC IN area. */
278	#define AC97_GLOB_CNT 0x2c
279	/** NABMBAR: Global Status. */
280	#define AC97_GLOB_STA 0x30
281	/** Codec Access Semaphore Register. */
282	#define AC97_CAS 0x34
283	/** @} */
284
285
286	/*********************************************************************************************************************************
287	* Structures and Typedefs *
288	*********************************************************************************************************************************/
289	/** The ICH AC'97 (Intel) controller (shared). */
290	typedef struct AC97STATE *PAC97STATE;
291	/** The ICH AC'97 (Intel) controller (ring-3). */
292	typedef struct AC97STATER3 *PAC97STATER3;
293
294	/**
295	* Buffer Descriptor List Entry (BDLE).
296	*/
297	typedef struct AC97BDLE
298	{
299	/** Location of data buffer (bits 31:1). */
300	uint32_t addr;
301	/** Flags (bits 31 + 30) and length (bits 15:0) of data buffer (in audio samples). */
302	uint32_t ctl_len;
303	} AC97BDLE;
304	AssertCompileSize(AC97BDLE, 8);
305	/** Pointer to BDLE. */
306	typedef AC97BDLE *PAC97BDLE;
307
308	/**
309	* Bus master register set for an audio stream.
310	*/
311	typedef struct AC97BMREGS
312	{
313	uint32_t bdbar; /*< rw 0, Buffer Descriptor List: BAR (Base Address Register). /
314	uint8_t civ; /*< ro 0, Current index value. /
315	uint8_t lvi; /*< rw 0, Last valid index. /
316	uint16_t sr; /*< rw 1, Status register. /
317	uint16_t picb; /*< ro 0, Position in current buffer (in samples). /
318	uint8_t piv; /*< ro 0, Prefetched index value. /
319	uint8_t cr; /*< rw 0, Control register. /
320	int32_t bd_valid; /*< Whether current BDLE is initialized or not. /
321	AC97BDLE bd; /*< Current Buffer Descriptor List Entry (BDLE). /
322	} AC97BMREGS;
323	AssertCompileSizeAlignment(AC97BMREGS, 8);
324	/** Pointer to the BM registers of an audio stream. */
325	typedef AC97BMREGS *PAC97BMREGS;
326
327	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
328	/**
329	* Asynchronous I/O state for an AC'97 stream.
330	*/
331	typedef struct AC97STREAMSTATEAIO
332	{
333	/** Thread handle for the actual I/O thread. */
334	RTTHREAD Thread;
335	/** Event for letting the thread know there is some data to process. */
336	RTSEMEVENT Event;
337	/** Critical section for synchronizing access. */
338	RTCRITSECT CritSect;
339	/** Started indicator. */
340	volatile bool fStarted;
341	/** Shutdown indicator. */
342	volatile bool fShutdown;
343	/** Whether the thread should do any data processing or not. */
344	volatile bool fEnabled;
345	bool afPadding[5];
346	} AC97STREAMSTATEAIO;
347	/** Pointer to the async I/O state for an AC'97 stream. */
348	typedef AC97STREAMSTATEAIO *PAC97STREAMSTATEAIO;
349	#endif
350
351
352	/**
353	* The internal state of an AC'97 stream.
354	*/
355	typedef struct AC97STREAMSTATE
356	{
357	/** Criticial section for this stream. */
358	RTCRITSECT CritSect;
359	/** Circular buffer (FIFO) for holding DMA'ed data. */
360	R3PTRTYPE(PRTCIRCBUF) pCircBuf;
361	#if HC_ARCH_BITS == 32
362	uint32_t Padding;
363	#endif
364	/** The stream's current configuration. */
365	PDMAUDIOSTREAMCFG Cfg; //+108
366	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
367	/** Asynchronous I/O state members. */
368	AC97STREAMSTATEAIO AIO;
369	#endif
370	/** Timestamp of the last DMA data transfer. */
371	uint64_t tsTransferLast;
372	/** Timestamp of the next DMA data transfer.
373	* Next for determining the next scheduling window.
374	* Can be 0 if no next transfer is scheduled. */
375	uint64_t tsTransferNext;
376	/** Transfer chunk size (in bytes) of a transfer period. */
377	uint32_t cbTransferChunk;
378	/** The stream's timer Hz rate.
379	* This value can can be different from the device's default Hz rate,
380	* depending on the rate the stream expects (e.g. for 5.1 speaker setups).
381	* Set in R3StreamInit(). */
382	uint16_t uTimerHz;
383	uint8_t Padding3[2];
384	/** (Virtual) clock ticks per transfer. */
385	uint64_t cTransferTicks;
386	/** Timestamp (in ns) of last stream update. */
387	uint64_t tsLastUpdateNs;
388	} AC97STREAMSTATE;
389	AssertCompileSizeAlignment(AC97STREAMSTATE, 8);
390	/** Pointer to internal state of an AC'97 stream. */
391	typedef AC97STREAMSTATE *PAC97STREAMSTATE;
392
393	/**
394	* Runtime configurable debug stuff for an AC'97 stream.
395	*/
396	typedef struct AC97STREAMDEBUGRT
397	{
398	/** Whether debugging is enabled or not. */
399	bool fEnabled;
400	uint8_t Padding[7];
401	/** File for dumping stream reads / writes.
402	* For input streams, this dumps data being written to the device FIFO,
403	* whereas for output streams this dumps data being read from the device FIFO. */
404	R3PTRTYPE(PAUDIOHLPFILE) pFileStream;
405	/** File for dumping DMA reads / writes.
406	* For input streams, this dumps data being written to the device DMA,
407	* whereas for output streams this dumps data being read from the device DMA. */
408	R3PTRTYPE(PAUDIOHLPFILE) pFileDMA;
409	} AC97STREAMDEBUGRT;
410
411	/**
412	* Debug stuff for an AC'97 stream.
413	*/
414	typedef struct AC97STREAMDEBUG
415	{
416	/** Runtime debug stuff. */
417	AC97STREAMDEBUGRT Runtime;
418	} AC97STREAMDEBUG;
419
420	/**
421	* The shared AC'97 stream state.
422	*/
423	typedef struct AC97STREAM
424	{
425	/** Stream number (SDn). */
426	uint8_t u8SD;
427	uint8_t abPadding0[7];
428	/** Bus master registers of this stream. */
429	AC97BMREGS Regs;
430	/** The timer for pumping data thru the attached LUN drivers. */
431	TMTIMERHANDLE hTimer;
432	} AC97STREAM;
433	AssertCompileSizeAlignment(AC97STREAM, 8);
434	/** Pointer to a shared AC'97 stream state. */
435	typedef AC97STREAM *PAC97STREAM;
436
437
438	/**
439	* The ring-3 AC'97 stream state.
440	*/
441	typedef struct AC97STREAMR3
442	{
443	/** Stream number (SDn). */
444	uint8_t u8SD;
445	uint8_t abPadding0[7];
446	/** Internal state of this stream. */
447	AC97STREAMSTATE State;
448	/** Debug stuff. */
449	AC97STREAMDEBUG Dbg;
450	} AC97STREAMR3;
451	AssertCompileSizeAlignment(AC97STREAMR3, 8);
452	/** Pointer to an AC'97 stream state for ring-3. */
453	typedef AC97STREAMR3 *PAC97STREAMR3;
454
455
456	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
457	/**
458	* Asynchronous I/O thread context (arguments).
459	*/
460	typedef struct AC97STREAMTHREADCTX
461	{
462	/** The AC'97 device state (shared). */
463	PAC97STATE pThis;
464	/** The AC'97 device state (ring-3). */
465	PAC97STATER3 pThisCC;
466	/** The AC'97 stream state (shared). */
467	PAC97STREAM pStream;
468	/** The AC'97 stream state (ring-3). */
469	PAC97STREAMR3 pStreamCC;
470	} AC97STREAMTHREADCTX;
471	/** Pointer to the context for an async I/O thread. */
472	typedef AC97STREAMTHREADCTX *PAC97STREAMTHREADCTX;
473	#endif
474
475	/**
476	* A driver stream (host backend).
477	*
478	* Each driver has its own instances of audio mixer streams, which then
479	* can go into the same (or even different) audio mixer sinks.
480	*/
481	typedef struct AC97DRIVERSTREAM
482	{
483	/** Associated mixer stream handle. */
484	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
485	} AC97DRIVERSTREAM;
486	/** Pointer to a driver stream. */
487	typedef AC97DRIVERSTREAM *PAC97DRIVERSTREAM;
488
489	/**
490	* A host backend driver (LUN).
491	*/
492	typedef struct AC97DRIVER
493	{
494	/** Node for storing this driver in our device driver list of AC97STATE. */
495	RTLISTNODER3 Node;
496	/** Driver flags. */
497	PDMAUDIODRVFLAGS fFlags;
498	/** LUN # to which this driver has been assigned. */
499	uint8_t uLUN;
500	/** Whether this driver is in an attached state or not. */
501	bool fAttached;
502	uint8_t abPadding[2];
503	/** Pointer to the description string passed to PDMDevHlpDriverAttach(). */
504	R3PTRTYPE(char *) pszDesc;
505	/** Pointer to attached driver base interface. */
506	R3PTRTYPE(PPDMIBASE) pDrvBase;
507	/** Audio connector interface to the underlying host backend. */
508	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
509	/** Driver stream for line input. */
510	AC97DRIVERSTREAM LineIn;
511	/** Driver stream for mic input. */
512	AC97DRIVERSTREAM MicIn;
513	/** Driver stream for output. */
514	AC97DRIVERSTREAM Out;
515	} AC97DRIVER;
516	/** Pointer to a host backend driver (LUN). */
517	typedef AC97DRIVER *PAC97DRIVER;
518
519	/**
520	* Debug settings.
521	*/
522	typedef struct AC97STATEDEBUG
523	{
524	/** Whether debugging is enabled or not. */
525	bool fEnabled;
526	bool afAlignment[7];
527	/** Path where to dump the debug output to.
528	* Can be NULL, in which the system's temporary directory will be used then. */
529	R3PTRTYPE(char *) pszOutPath;
530	} AC97STATEDEBUG;
531
532
533	/* Codec models. */
534	typedef enum AC97CODEC
535	{
536	AC97CODEC_INVALID = 0, /*< Customary illegal zero value. /
537	AC97CODEC_STAC9700, /*< SigmaTel STAC9700 /
538	AC97CODEC_AD1980, /*< Analog Devices AD1980 /
539	AC97CODEC_AD1981B, /*< Analog Devices AD1981B /
540	AC97CODEC_32BIT_HACK = 0x7fffffff
541	} AC97CODEC;
542
543
544	/**
545	* The shared AC'97 device state.
546	*/
547	typedef struct AC97STATE
548	{
549	/** Critical section protecting the AC'97 state. */
550	PDMCRITSECT CritSect;
551	/** Global Control (Bus Master Control Register). */
552	uint32_t glob_cnt;
553	/** Global Status (Bus Master Control Register). */
554	uint32_t glob_sta;
555	/** Codec Access Semaphore Register (Bus Master Control Register). */
556	uint32_t cas;
557	uint32_t last_samp;
558	uint8_t mixer_data[256];
559	/** Array of AC'97 streams (parallel to AC97STATER3::aStreams). */
560	AC97STREAM aStreams[AC97_MAX_STREAMS];
561	/** The device timer Hz rate. Defaults to AC97_TIMER_HZ_DEFAULT_DEFAULT. */
562	uint16_t uTimerHz;
563	uint16_t au16Padding1[3];
564	uint8_t silence[128];
565	uint32_t bup_flag;
566	/** Codec model. */
567	AC97CODEC enmCodecModel;
568
569	/** PCI region \#0: NAM I/O ports. */
570	IOMIOPORTHANDLE hIoPortsNam;
571	/** PCI region \#0: NANM I/O ports. */
572	IOMIOPORTHANDLE hIoPortsNabm;
573
574	STAMCOUNTER StatUnimplementedNabmReads;
575	STAMCOUNTER StatUnimplementedNabmWrites;
576	#ifdef VBOX_WITH_STATISTICS
577	STAMPROFILE StatTimer;
578	STAMPROFILE StatIn;
579	STAMPROFILE StatOut;
580	STAMCOUNTER StatBytesRead;
581	STAMCOUNTER StatBytesWritten;
582	#endif
583	} AC97STATE;
584	AssertCompileMemberAlignment(AC97STATE, aStreams, 8);
585	AssertCompileMemberAlignment(AC97STATE, StatUnimplementedNabmReads, 8);
586	#ifdef VBOX_WITH_STATISTICS
587	AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
588	AssertCompileMemberAlignment(AC97STATE, StatBytesRead, 8);
589	AssertCompileMemberAlignment(AC97STATE, StatBytesWritten, 8);
590	#endif
591
592
593	/**
594	* The ring-3 AC'97 device state.
595	*/
596	typedef struct AC97STATER3
597	{
598	/** Array of AC'97 streams (parallel to AC97STATE:aStreams). */
599	AC97STREAMR3 aStreams[AC97_MAX_STREAMS];
600	/** R3 pointer to the device instance. */
601	PPDMDEVINSR3 pDevIns;
602	/** List of associated LUN drivers (AC97DRIVER). */
603	RTLISTANCHORR3 lstDrv;
604	/** The device's software mixer. */
605	R3PTRTYPE(PAUDIOMIXER) pMixer;
606	/** Audio sink for PCM output. */
607	R3PTRTYPE(PAUDMIXSINK) pSinkOut;
608	/** Audio sink for line input. */
609	R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
610	/** Audio sink for microphone input. */
611	R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
612	/** The base interface for LUN\#0. */
613	PDMIBASE IBase;
614	/** Debug settings. */
615	AC97STATEDEBUG Dbg;
616	} AC97STATER3;
617	AssertCompileMemberAlignment(AC97STATER3, aStreams, 8);
618	/** Pointer to the ring-3 AC'97 device state. */
619	typedef AC97STATER3 *PAC97STATER3;
620
621
622	/**
623	* Acquires the AC'97 lock.
624	*/
625	#define DEVAC97_LOCK(a_pDevIns, a_pThis) \
626	do { \
627	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
628	AssertRC(rcLock); \
629	} while (0)
630
631	/**
632	* Acquires the AC'97 lock or returns.
633	*/
634	# define DEVAC97_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
635	do { \
636	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, a_rcBusy); \
637	if (rcLock == VINF_SUCCESS) \
638	break; \
639	AssertRC(rcLock); \
640	return rcLock; \
641	} while (0)
642
643	/** Retrieves an attribute from a specific audio stream in RC. */
644	#define DEVAC97_CTX_SUFF_SD(a_Var, a_SD) CTX_SUFF(a_Var)[a_SD]
645
646	/**
647	* Releases the AC'97 lock.
648	*/
649	#define DEVAC97_UNLOCK(a_pDevIns, a_pThis) \
650	do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
651
652	/**
653	* Acquires the TM lock and AC'97 lock, returns on failure.
654	*
655	* @todo r=bird: Isn't this overkill for ring-0, only ring-3 access the timer
656	* from what I can tell (ichac97R3StreamTransferCalcNext,
657	* ichac97R3TimerSet, timer callback and state load).
658	*/
659	#define DEVAC97_LOCK_BOTH_RETURN(a_pDevIns, a_pThis, a_pStream, a_rcBusy) \
660	do { \
661	VBOXSTRICTRC rcLock = PDMDevHlpTimerLockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect, (a_rcBusy)); \
662	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
663	{ /* likely */ } \
664	else \
665	{ \
666	AssertRC(VBOXSTRICTRC_VAL(rcLock)); \
667	return rcLock; \
668	} \
669	} while (0)
670
671	/**
672	* Releases the AC'97 lock and TM lock.
673	*/
674	#define DEVAC97_UNLOCK_BOTH(a_pDevIns, a_pThis, a_pStream) \
675	PDMDevHlpTimerUnlockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect)
676
677	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
678
679
680	/*********************************************************************************************************************************
681	* Internal Functions *
682	*********************************************************************************************************************************/
683	#ifdef IN_RING3
684	static int ichac97R3StreamOpen(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
685	PAC97STREAMR3 pStreamCC, bool fForce);
686	static int ichac97R3StreamClose(PAC97STREAM pStream);
687	static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC);
688	static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC);
689	static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC);
690	static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC);
691	static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
692	PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax);
693	static void ichac97R3StreamUpdate(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
694	PAC97STREAMR3 pStreamCC, bool fInTimer);
695
696	static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns);
697
698	static void ichac97R3MixerRemoveDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
699	PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc);
700
701	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
702	static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC);
703	static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAMR3 pStreamCC);
704	static void ichac97R3StreamAsyncIOLock(PAC97STREAMR3 pStreamCC);
705	static void ichac97R3StreamAsyncIOUnlock(PAC97STREAMR3 pStreamCC);
706	/static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable); Unused /
707	# endif
708
709	DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD);
710	DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline);
711	#endif /* IN_RING3 */
712
713
714	/*********************************************************************************************************************************
715	* Global Variables *
716	*********************************************************************************************************************************/
717	#ifdef IN_RING3
718	/** NABM I/O port descriptions. */
719	static const IOMIOPORTDESC g_aNabmPorts[] =
720	{
721	{ "PCM IN - BDBAR", "PCM IN - BDBAR", NULL, NULL },
722	{ "", NULL, NULL, NULL },
723	{ "", NULL, NULL, NULL },
724	{ "", NULL, NULL, NULL },
725	{ "PCM IN - CIV", "PCM IN - CIV", NULL, NULL },
726	{ "PCM IN - LVI", "PCM IN - LIV", NULL, NULL },
727	{ "PCM IN - SR", "PCM IN - SR", NULL, NULL },
728	{ "", NULL, NULL, NULL },
729	{ "PCM IN - PICB", "PCM IN - PICB", NULL, NULL },
730	{ "", NULL, NULL, NULL },
731	{ "PCM IN - PIV", "PCM IN - PIV", NULL, NULL },
732	{ "PCM IN - CR", "PCM IN - CR", NULL, NULL },
733	{ "", NULL, NULL, NULL },
734	{ "", NULL, NULL, NULL },
735	{ "", NULL, NULL, NULL },
736	{ "", NULL, NULL, NULL },
737
738	{ "PCM OUT - BDBAR", "PCM OUT - BDBAR", NULL, NULL },
739	{ "", NULL, NULL, NULL },
740	{ "", NULL, NULL, NULL },
741	{ "", NULL, NULL, NULL },
742	{ "PCM OUT - CIV", "PCM OUT - CIV", NULL, NULL },
743	{ "PCM OUT - LVI", "PCM OUT - LIV", NULL, NULL },
744	{ "PCM OUT - SR", "PCM OUT - SR", NULL, NULL },
745	{ "", NULL, NULL, NULL },
746	{ "PCM OUT - PICB", "PCM OUT - PICB", NULL, NULL },
747	{ "", NULL, NULL, NULL },
748	{ "PCM OUT - PIV", "PCM OUT - PIV", NULL, NULL },
749	{ "PCM OUT - CR", "PCM IN - CR", NULL, NULL },
750	{ "", NULL, NULL, NULL },
751	{ "", NULL, NULL, NULL },
752	{ "", NULL, NULL, NULL },
753	{ "", NULL, NULL, NULL },
754
755	{ "MIC IN - BDBAR", "MIC IN - BDBAR", NULL, NULL },
756	{ "", NULL, NULL, NULL },
757	{ "", NULL, NULL, NULL },
758	{ "", NULL, NULL, NULL },
759	{ "MIC IN - CIV", "MIC IN - CIV", NULL, NULL },
760	{ "MIC IN - LVI", "MIC IN - LIV", NULL, NULL },
761	{ "MIC IN - SR", "MIC IN - SR", NULL, NULL },
762	{ "", NULL, NULL, NULL },
763	{ "MIC IN - PICB", "MIC IN - PICB", NULL, NULL },
764	{ "", NULL, NULL, NULL },
765	{ "MIC IN - PIV", "MIC IN - PIV", NULL, NULL },
766	{ "MIC IN - CR", "MIC IN - CR", NULL, NULL },
767	{ "GLOB CNT", "GLOB CNT", NULL, NULL },
768	{ "", NULL, NULL, NULL },
769	{ "", NULL, NULL, NULL },
770	{ "", NULL, NULL, NULL },
771
772	{ "GLOB STA", "GLOB STA", NULL, NULL },
773	{ "", NULL, NULL, NULL },
774	{ "", NULL, NULL, NULL },
775	{ "", NULL, NULL, NULL },
776	{ "CAS", "CAS", NULL, NULL },
777	{ NULL, NULL, NULL, NULL },
778	};
779
780	/** @name Source indices
781	* @{ */
782	#define AC97SOUNDSOURCE_PI_INDEX 0 /*< PCM in /
783	#define AC97SOUNDSOURCE_PO_INDEX 1 /*< PCM out /
784	#define AC97SOUNDSOURCE_MC_INDEX 2 /*< Mic in /
785	#define AC97SOUNDSOURCE_MAX 3 /*< Max sound sources. /
786	/** @} */
787
788	/** Port number (offset into NABM BAR) to stream index. */
789	#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
790	/** Port number (offset into NABM BAR) to stream index, but no masking. */
791	#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
792
793	/** @name Stream offsets
794	* @{ */
795	#define AC97_NABM_OFF_BDBAR 0x0 /*< Buffer Descriptor Base Address /
796	#define AC97_NABM_OFF_CIV 0x4 /*< Current Index Value /
797	#define AC97_NABM_OFF_LVI 0x5 /*< Last Valid Index /
798	#define AC97_NABM_OFF_SR 0x6 /*< Status Register /
799	#define AC97_NABM_OFF_PICB 0x8 /*< Position in Current Buffer /
800	#define AC97_NABM_OFF_PIV 0xa /*< Prefetched Index Value /
801	#define AC97_NABM_OFF_CR 0xb /*< Control Register /
802	#define AC97_NABM_OFF_MASK 0xf /*< Mask for getting the the per-stream register. /
803	/** @} */
804
805	#endif
806
807
808
809	static void ichac97WarmReset(PAC97STATE pThis)
810	{
811	NOREF(pThis);
812	}
813
814	static void ichac97ColdReset(PAC97STATE pThis)
815	{
816	NOREF(pThis);
817	}
818
819
820	#ifdef IN_RING3
821
822	/**
823	* Retrieves the audio mixer sink of a corresponding AC'97 stream index.
824	*
825	* @returns Pointer to audio mixer sink if found, or NULL if not found / invalid.
826	* @param pThisCC The ring-3 AC'97 state.
827	* @param uIndex Stream index to get audio mixer sink for.
828	*/
829	DECLINLINE(PAUDMIXSINK) ichac97R3IndexToSink(PAC97STATER3 pThisCC, uint8_t uIndex)
830	{
831	switch (uIndex)
832	{
833	case AC97SOUNDSOURCE_PI_INDEX: return pThisCC->pSinkLineIn;
834	case AC97SOUNDSOURCE_PO_INDEX: return pThisCC->pSinkOut;
835	case AC97SOUNDSOURCE_MC_INDEX: return pThisCC->pSinkMicIn;
836	default:
837	AssertMsgFailedReturn(("Wrong index %RU8\n", uIndex), NULL);
838	}
839	}
840
841	/**
842	* Fetches the current BDLE (Buffer Descriptor List Entry) of an AC'97 audio stream.
843	*
844	* @returns VBox status code.
845	* @param pDevIns The device instance.
846	* @param pStream AC'97 stream to fetch BDLE for.
847	*
848	* @remark Uses CIV as BDLE index.
849	*/
850	static void ichac97R3StreamFetchBDLE(PPDMDEVINS pDevIns, PAC97STREAM pStream)
851	{
852	PAC97BMREGS pRegs = &pStream->Regs;
853
854	AC97BDLE BDLE;
855	PDMDevHlpPCIPhysRead(pDevIns, pRegs->bdbar + pRegs->civ * sizeof(AC97BDLE), &BDLE, sizeof(AC97BDLE));
856	pRegs->bd_valid = 1;
857	# ifndef RT_LITTLE_ENDIAN
858	# error "Please adapt the code (audio buffers are little endian)!"
859	# else
860	pRegs->bd.addr = RT_H2LE_U32(BDLE.addr & ~3);
861	pRegs->bd.ctl_len = RT_H2LE_U32(BDLE.ctl_len);
862	# endif
863	pRegs->picb = pRegs->bd.ctl_len & AC97_BD_LEN_MASK;
864	LogFlowFunc(("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes), bup=%RTbool, ioc=%RTbool\n",
865	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len >> 16,
866	pRegs->bd.ctl_len & AC97_BD_LEN_MASK,
867	(pRegs->bd.ctl_len & AC97_BD_LEN_MASK) << 1, /** @todo r=andy Assumes 16bit samples. */
868	RT_BOOL(pRegs->bd.ctl_len & AC97_BD_BUP),
869	RT_BOOL(pRegs->bd.ctl_len & AC97_BD_IOC)));
870	}
871
872	#endif /* IN_RING3 */
873
874	/**
875	* Updates the status register (SR) of an AC'97 audio stream.
876	*
877	* @param pDevIns The device instance.
878	* @param pThis The shared AC'97 state.
879	* @param pStream AC'97 stream to update SR for.
880	* @param new_sr New value for status register (SR).
881	*/
882	static void ichac97StreamUpdateSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr)
883	{
884	PAC97BMREGS pRegs = &pStream->Regs;
885
886	bool fSignal = false;
887	int iIRQL = 0;
888
889	uint32_t new_mask = new_sr & AC97_SR_INT_MASK;
890	uint32_t old_mask = pRegs->sr & AC97_SR_INT_MASK;
891
892	if (new_mask ^ old_mask)
893	{
894	/** @todo Is IRQ deasserted when only one of status bits is cleared? */
895	if (!new_mask)
896	{
897	fSignal = true;
898	iIRQL = 0;
899	}
900	else if ((new_mask & AC97_SR_LVBCI) && (pRegs->cr & AC97_CR_LVBIE))
901	{
902	fSignal = true;
903	iIRQL = 1;
904	}
905	else if ((new_mask & AC97_SR_BCIS) && (pRegs->cr & AC97_CR_IOCE))
906	{
907	fSignal = true;
908	iIRQL = 1;
909	}
910	}
911
912	pRegs->sr = new_sr;
913
914	LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n",
915	pRegs->sr & AC97_SR_BCIS, pRegs->sr & AC97_SR_LVBCI, pRegs->sr, fSignal, iIRQL));
916
917	if (fSignal)
918	{
919	static uint32_t const s_aMasks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT };
920	Assert(pStream->u8SD < AC97_MAX_STREAMS);
921	if (iIRQL)
922	pThis->glob_sta \|= s_aMasks[pStream->u8SD];
923	else
924	pThis->glob_sta &= ~s_aMasks[pStream->u8SD];
925
926	LogFlowFunc(("Setting IRQ level=%d\n", iIRQL));
927	PDMDevHlpPCISetIrq(pDevIns, 0, iIRQL);
928	}
929	}
930
931	/**
932	* Writes a new value to a stream's status register (SR).
933	*
934	* @param pDevIns The device instance.
935	* @param pThis The shared AC'97 device state.
936	* @param pStream Stream to update SR for.
937	* @param u32Val New value to set the stream's SR to.
938	*/
939	static void ichac97StreamWriteSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t u32Val)
940	{
941	PAC97BMREGS pRegs = &pStream->Regs;
942
943	Log3Func(("[SD%RU8] SR <- %#x (sr %#x)\n", pStream->u8SD, u32Val, pRegs->sr));
944
945	pRegs->sr \|= u32Val & ~(AC97_SR_RO_MASK \| AC97_SR_WCLEAR_MASK);
946	ichac97StreamUpdateSR(pDevIns, pThis, pStream, pRegs->sr & ~(u32Val & AC97_SR_WCLEAR_MASK));
947	}
948
949	#ifdef IN_RING3
950
951	/**
952	* Returns whether an AC'97 stream is enabled or not.
953	*
954	* @returns VBox status code.
955	* @param pThisCC The ring-3 AC'97 device state.
956	* @param pStream Stream to return status for.
957	*/
958	static bool ichac97R3StreamIsEnabled(PAC97STATER3 pThisCC, PAC97STREAM pStream)
959	{
960	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
961	bool fIsEnabled = RT_BOOL(AudioMixerSinkGetStatus(pSink) & AUDMIXSINK_STS_RUNNING);
962
963	LogFunc(("[SD%RU8] fIsEnabled=%RTbool\n", pStream->u8SD, fIsEnabled));
964	return fIsEnabled;
965	}
966
967	/**
968	* Enables or disables an AC'97 audio stream.
969	*
970	* @returns VBox status code.
971	* @param pDevIns The device instance.
972	* @param pThis The shared AC'97 state.
973	* @param pThisCC The ring-3 AC'97 state.
974	* @param pStream The AC'97 stream to enable or disable (shared
975	* state).
976	* @param pStreamCC The ring-3 stream state (matching to @a pStream).
977	* @param fEnable Whether to enable or disable the stream.
978	*
979	*/
980	static int ichac97R3StreamEnable(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
981	PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fEnable)
982	{
983	ichac97R3StreamLock(pStreamCC);
984
985	int rc = VINF_SUCCESS;
986
987	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
988	if (fEnable)
989	rc = ichac97R3StreamAsyncIOCreate(pThis, pThisCC, pStream, pStreamCC);
990	if (RT_SUCCESS(rc))
991	ichac97R3StreamAsyncIOLock(pStreamCC);
992	# endif
993
994	if (fEnable)
995	{
996	if (pStreamCC->State.pCircBuf)
997	RTCircBufReset(pStreamCC->State.pCircBuf);
998
999	rc = ichac97R3StreamOpen(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fForce */);
1000
1001	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1002	{ /* likely */ }
1003	else
1004	{
1005	if (!AudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileStream))
1006	{
1007	int rc2 = AudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1008	&pStreamCC->State.Cfg.Props);
1009	AssertRC(rc2);
1010	}
1011
1012	if (!AudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileDMA))
1013	{
1014	int rc2 = AudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileDMA, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1015	&pStreamCC->State.Cfg.Props);
1016	AssertRC(rc2);
1017	}
1018	}
1019	}
1020	else
1021	rc = ichac97R3StreamClose(pStream);
1022
1023	if (RT_SUCCESS(rc))
1024	{
1025	/* First, enable or disable the stream and the stream's sink, if any. */
1026	rc = AudioMixerSinkCtl(ichac97R3IndexToSink(pThisCC, pStream->u8SD),
1027	fEnable ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE);
1028	}
1029
1030	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1031	ichac97R3StreamAsyncIOUnlock(pStreamCC);
1032	# endif
1033
1034	/* Make sure to leave the lock before (eventually) starting the timer. */
1035	ichac97R3StreamUnlock(pStreamCC);
1036
1037	LogFunc(("[SD%RU8] fEnable=%RTbool, rc=%Rrc\n", pStream->u8SD, fEnable, rc));
1038	return rc;
1039	}
1040
1041	/**
1042	* Resets an AC'97 stream.
1043	*
1044	* @param pThis The shared AC'97 state.
1045	* @param pStream The AC'97 stream to reset (shared).
1046	* @param pStreamCC The AC'97 stream to reset (ring-3).
1047	*/
1048	static void ichac97R3StreamReset(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1049	{
1050	ichac97R3StreamLock(pStreamCC);
1051
1052	LogFunc(("[SD%RU8]\n", pStream->u8SD));
1053
1054	if (pStreamCC->State.pCircBuf)
1055	RTCircBufReset(pStreamCC->State.pCircBuf);
1056
1057	PAC97BMREGS pRegs = &pStream->Regs;
1058
1059	pRegs->bdbar = 0;
1060	pRegs->civ = 0;
1061	pRegs->lvi = 0;
1062
1063	pRegs->picb = 0;
1064	pRegs->piv = 0;
1065	pRegs->cr = pRegs->cr & AC97_CR_DONT_CLEAR_MASK;
1066	pRegs->bd_valid = 0;
1067
1068	RT_ZERO(pThis->silence);
1069
1070	ichac97R3StreamUnlock(pStreamCC);
1071	}
1072
1073	/**
1074	* Creates an AC'97 audio stream.
1075	*
1076	* @returns VBox status code.
1077	* @param pThisCC The ring-3 AC'97 state.
1078	* @param pStream The AC'97 stream to create (shared).
1079	* @param pStreamCC The AC'97 stream to create (ring-3).
1080	* @param u8SD Stream descriptor number to assign.
1081	*/
1082	static int ichac97R3StreamCreate(PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint8_t u8SD)
1083	{
1084	LogFunc(("[SD%RU8] pStream=%p\n", u8SD, pStream));
1085
1086	AssertReturn(u8SD < AC97_MAX_STREAMS, VERR_INVALID_PARAMETER);
1087	pStream->u8SD = u8SD;
1088	pStreamCC->u8SD = u8SD;
1089
1090	int rc = RTCritSectInit(&pStreamCC->State.CritSect);
1091	AssertRCReturn(rc, rc);
1092
1093	pStreamCC->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
1094
1095	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1096	{ /* likely */ }
1097	else
1098	{
1099	char szFile[64];
1100
1101	if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1102	RTStrPrintf(szFile, sizeof(szFile), "ac97StreamWriteSD%RU8", pStream->u8SD);
1103	else
1104	RTStrPrintf(szFile, sizeof(szFile), "ac97StreamReadSD%RU8", pStream->u8SD);
1105
1106	char szPath[RTPATH_MAX];
1107	int rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1108	0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
1109	AssertRC(rc2);
1110	rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileStream);
1111	AssertRC(rc2);
1112
1113	if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1114	RTStrPrintf(szFile, sizeof(szFile), "ac97DMAWriteSD%RU8", pStream->u8SD);
1115	else
1116	RTStrPrintf(szFile, sizeof(szFile), "ac97DMAReadSD%RU8", pStream->u8SD);
1117
1118	rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1119	0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
1120	AssertRC(rc2);
1121
1122	rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileDMA);
1123	AssertRC(rc2);
1124
1125	/* Delete stale debugging files from a former run. */
1126	AudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileStream);
1127	AudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileDMA);
1128	}
1129
1130	return rc;
1131	}
1132
1133	/**
1134	* Destroys an AC'97 audio stream.
1135	*
1136	* @returns VBox status code.
1137	* @param pThis The shared AC'97 state.
1138	* @param pStream The AC'97 stream to destroy (shared).
1139	* @param pStreamCC The AC'97 stream to destroy (ring-3).
1140	*/
1141	static void ichac97R3StreamDestroy(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1142	{
1143	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
1144
1145	ichac97R3StreamClose(pStream);
1146
1147	int rc2 = RTCritSectDelete(&pStreamCC->State.CritSect);
1148	AssertRC(rc2);
1149
1150	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1151	rc2 = ichac97R3StreamAsyncIODestroy(pThis, pStreamCC);
1152	AssertRC(rc2);
1153	# else
1154	RT_NOREF(pThis);
1155	# endif
1156
1157	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1158	{ /* likely */ }
1159	else
1160	{
1161	AudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileStream);
1162	pStreamCC->Dbg.Runtime.pFileStream = NULL;
1163
1164	AudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileDMA);
1165	pStreamCC->Dbg.Runtime.pFileDMA = NULL;
1166	}
1167
1168	if (pStreamCC->State.pCircBuf)
1169	{
1170	RTCircBufDestroy(pStreamCC->State.pCircBuf);
1171	pStreamCC->State.pCircBuf = NULL;
1172	}
1173
1174	LogFlowFuncLeave();
1175	}
1176
1177	/**
1178	* Destroys all AC'97 audio streams of the device.
1179	*
1180	* @param pDevIns The device AC'97 instance.
1181	* @param pThis The shared AC'97 state.
1182	* @param pThisCC The ring-3 AC'97 state.
1183	*/
1184	static void ichac97R3StreamsDestroy(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC)
1185	{
1186	LogFlowFuncEnter();
1187
1188	/*
1189	* Destroy all AC'97 streams.
1190	*/
1191	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
1192	ichac97R3StreamDestroy(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
1193
1194	/*
1195	* Destroy all sinks.
1196	*/
1197
1198	PDMAUDIODSTSRCUNION dstSrc;
1199	if (pThisCC->pSinkLineIn)
1200	{
1201	dstSrc.enmSrc = PDMAUDIORECSRC_LINE;
1202	ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkLineIn, PDMAUDIODIR_IN, dstSrc);
1203
1204	AudioMixerSinkDestroy(pThisCC->pSinkLineIn, pDevIns);
1205	pThisCC->pSinkLineIn = NULL;
1206	}
1207
1208	if (pThisCC->pSinkMicIn)
1209	{
1210	dstSrc.enmSrc = PDMAUDIORECSRC_MIC;
1211	ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkMicIn, PDMAUDIODIR_IN, dstSrc);
1212
1213	AudioMixerSinkDestroy(pThisCC->pSinkMicIn, pDevIns);
1214	pThisCC->pSinkMicIn = NULL;
1215	}
1216
1217	if (pThisCC->pSinkOut)
1218	{
1219	dstSrc.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
1220	ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkOut, PDMAUDIODIR_OUT, dstSrc);
1221
1222	AudioMixerSinkDestroy(pThisCC->pSinkOut, pDevIns);
1223	pThisCC->pSinkOut = NULL;
1224	}
1225	}
1226
1227	/**
1228	* Writes audio data from a mixer sink into an AC'97 stream's DMA buffer.
1229	*
1230	* @returns VBox status code.
1231	* @param pDstStreamCC The AC'97 stream to write to (ring-3).
1232	* @param pSrcMixSink Mixer sink to get audio data to write from.
1233	* @param cbToWrite Number of bytes to write.
1234	* @param pcbWritten Number of bytes written. Optional.
1235	*/
1236	static int ichac97R3StreamWrite(PAC97STREAMR3 pDstStreamCC, PAUDMIXSINK pSrcMixSink, uint32_t cbToWrite, uint32_t *pcbWritten)
1237	{
1238	AssertPtrReturn(pSrcMixSink, VERR_INVALID_POINTER);
1239	AssertReturn(cbToWrite > 0, VERR_INVALID_PARAMETER);
1240	/* pcbWritten is optional. */
1241
1242	PRTCIRCBUF pCircBuf = pDstStreamCC->State.pCircBuf;
1243	AssertPtr(pCircBuf);
1244
1245	uint32_t cbRead = 0;
1246
1247	void *pvDst;
1248	size_t cbDst;
1249	RTCircBufAcquireWriteBlock(pCircBuf, cbToWrite, &pvDst, &cbDst);
1250
1251	if (cbDst)
1252	{
1253	int rc2 = AudioMixerSinkRead(pSrcMixSink, AUDMIXOP_COPY, pvDst, (uint32_t)cbDst, &cbRead);
1254	AssertRC(rc2);
1255
1256	if (RT_LIKELY(!pDstStreamCC->Dbg.Runtime.fEnabled))
1257	{ /* likely */ }
1258	else
1259	AudioHlpFileWrite(pDstStreamCC->Dbg.Runtime.pFileStream, pvDst, cbRead, 0 /* fFlags */);
1260	}
1261
1262	RTCircBufReleaseWriteBlock(pCircBuf, cbRead);
1263
1264	if (pcbWritten)
1265	*pcbWritten = cbRead;
1266
1267	return VINF_SUCCESS;
1268	}
1269
1270	/**
1271	* Reads audio data from an AC'97 stream's DMA buffer and writes into a specified mixer sink.
1272	*
1273	* @returns VBox status code.
1274	* @param pSrcStreamCC AC'97 stream to read audio data from (ring-3).
1275	* @param pDstMixSink Mixer sink to write audio data to.
1276	* @param cbToRead Number of bytes to read.
1277	* @param pcbRead Number of bytes read. Optional.
1278	*/
1279	static int ichac97R3StreamRead(PAC97STREAMR3 pSrcStreamCC, PAUDMIXSINK pDstMixSink, uint32_t cbToRead, uint32_t *pcbRead)
1280	{
1281	AssertPtrReturn(pDstMixSink, VERR_INVALID_POINTER);
1282	AssertReturn(cbToRead > 0, VERR_INVALID_PARAMETER);
1283	/* pcbRead is optional. */
1284
1285	PRTCIRCBUF pCircBuf = pSrcStreamCC->State.pCircBuf;
1286	AssertPtr(pCircBuf);
1287
1288	void *pvSrc;
1289	size_t cbSrc;
1290
1291	int rc = VINF_SUCCESS;
1292
1293	uint32_t cbReadTotal = 0;
1294	uint32_t cbLeft = RT_MIN(cbToRead, (uint32_t)RTCircBufUsed(pCircBuf));
1295
1296	while (cbLeft)
1297	{
1298	uint32_t cbWritten = 0;
1299
1300	RTCircBufAcquireReadBlock(pCircBuf, cbLeft, &pvSrc, &cbSrc);
1301
1302	if (cbSrc)
1303	{
1304	if (RT_LIKELY(!pSrcStreamCC->Dbg.Runtime.fEnabled))
1305	{ /* likely */ }
1306	else
1307	AudioHlpFileWrite(pSrcStreamCC->Dbg.Runtime.pFileStream, pvSrc, cbSrc, 0 /* fFlags */);
1308
1309	rc = AudioMixerSinkWrite(pDstMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbWritten);
1310	AssertRC(rc);
1311
1312	Assert(cbSrc >= cbWritten);
1313	Log3Func(("[SD%RU8] %RU32/%zu bytes read\n", pSrcStreamCC->u8SD, cbWritten, cbSrc));
1314	}
1315
1316	RTCircBufReleaseReadBlock(pCircBuf, cbWritten);
1317
1318	if ( !cbWritten /* Nothing written? */
1319	\|\| RT_FAILURE(rc))
1320	break;
1321
1322	Assert(cbLeft >= cbWritten);
1323	cbLeft -= cbWritten;
1324
1325	cbReadTotal += cbWritten;
1326	}
1327
1328	if (pcbRead)
1329	*pcbRead = cbReadTotal;
1330
1331	return rc;
1332	}
1333
1334	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1335
1336	/**
1337	* Asynchronous I/O thread for an AC'97 stream.
1338	* This will do the heavy lifting work for us as soon as it's getting notified by another thread.
1339	*
1340	* @returns VBox status code.
1341	* @param hThreadSelf Thread handle.
1342	* @param pvUser User argument. Must be of type PAC97STREAMTHREADCTX.
1343	*/
1344	static DECLCALLBACK(int) ichac97R3StreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
1345	{
1346	PAC97STREAMTHREADCTX pCtx = (PAC97STREAMTHREADCTX)pvUser;
1347	AssertPtr(pCtx);
1348
1349	PAC97STATE pThis = pCtx->pThis;
1350	AssertPtr(pThis);
1351
1352	PAC97STATER3 pThisCC = pCtx->pThisCC;
1353	AssertPtr(pThisCC);
1354
1355	PAC97STREAM pStream = pCtx->pStream;
1356	AssertPtr(pStream);
1357
1358	PAC97STREAMR3 pStreamCC = pCtx->pStreamCC;
1359	AssertPtr(pStreamCC);
1360
1361	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1362
1363	ASMAtomicXchgBool(&pAIO->fStarted, true);
1364
1365	RTThreadUserSignal(hThreadSelf);
1366
1367	LogFunc(("[SD%RU8] Started\n", pStream->u8SD));
1368
1369	for (;;)
1370	{
1371	Log2Func(("[SD%RU8] Waiting ...\n", pStream->u8SD));
1372
1373	int rc2 = RTSemEventWait(pAIO->Event, RT_INDEFINITE_WAIT);
1374	if (RT_FAILURE(rc2))
1375	break;
1376
1377	if (ASMAtomicReadBool(&pAIO->fShutdown))
1378	break;
1379
1380	rc2 = RTCritSectEnter(&pAIO->CritSect);
1381	if (RT_SUCCESS(rc2))
1382	{
1383	if (!pAIO->fEnabled)
1384	{
1385	RTCritSectLeave(&pAIO->CritSect);
1386	continue;
1387	}
1388
1389	ichac97R3StreamUpdate(pThisCC->pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fInTimer */);
1390
1391	int rc3 = RTCritSectLeave(&pAIO->CritSect);
1392	AssertRC(rc3);
1393	}
1394
1395	AssertRC(rc2);
1396	}
1397
1398	LogFunc(("[SD%RU8] Ended\n", pStream->u8SD));
1399
1400	ASMAtomicXchgBool(&pAIO->fStarted, false);
1401
1402	RTMemFree(pCtx);
1403	pCtx = NULL;
1404
1405	return VINF_SUCCESS;
1406	}
1407
1408	/**
1409	* Creates the async I/O thread for a specific AC'97 audio stream.
1410	*
1411	* @returns VBox status code.
1412	* @param pThis The shared AC'97 state (shared).
1413	* @param pThisCC The shared AC'97 state (ring-3).
1414	* @param pStream AC'97 audio stream to create the async I/O thread for (shared).
1415	* @param pStreamCC AC'97 audio stream to create the async I/O thread for (ring-3).
1416	*/
1417	static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1418	{
1419	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1420
1421	int rc;
1422
1423	if (!ASMAtomicReadBool(&pAIO->fStarted))
1424	{
1425	pAIO->fShutdown = false;
1426	pAIO->fEnabled = true; /* Enabled by default. */
1427
1428	rc = RTSemEventCreate(&pAIO->Event);
1429	if (RT_SUCCESS(rc))
1430	{
1431	rc = RTCritSectInit(&pAIO->CritSect);
1432	if (RT_SUCCESS(rc))
1433	{
1434	/** @todo r=bird:
1435	* Why aren't this code using the PDM threads (PDMDevHlpThreadCreate)?
1436	* They would help you with managing stuff like VM suspending, resuming
1437	* and powering off.
1438	*
1439	* Finally, just create the threads at construction time. */
1440	PAC97STREAMTHREADCTX pCtx = (PAC97STREAMTHREADCTX)RTMemAllocZ(sizeof(AC97STREAMTHREADCTX));
1441	if (pCtx)
1442	{
1443	pCtx->pStream = pStream;
1444	pCtx->pStreamCC = pStreamCC;
1445	pCtx->pThis = pThis;
1446	pCtx->pThisCC = pThisCC;
1447
1448	rc = RTThreadCreateF(&pAIO->Thread, ichac97R3StreamAsyncIOThread, pCtx, 0 /cbStack/, RTTHREADTYPE_IO,
1449	RTTHREADFLAGS_WAITABLE \| RTTHREADFLAGS_COM_MTA, "ac97AIO%RU8", pStreamCC->u8SD);
1450	if (RT_SUCCESS(rc))
1451	rc = RTThreadUserWait(pAIO->Thread, 30 * 1000 /* 30s timeout */);
1452	}
1453	else
1454	rc = VERR_NO_MEMORY;
1455	}
1456	}
1457	}
1458	else
1459	rc = VINF_SUCCESS;
1460
1461	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamCC->u8SD, rc));
1462	return rc;
1463	}
1464
1465	/**
1466	* Lets the stream's async I/O thread know that there is some data to process.
1467	*
1468	* @returns VBox status code.
1469	* @param pStreamCC The AC'97 stream to notify async I/O thread
1470	* for (ring-3).
1471	*/
1472	static int ichac97R3StreamAsyncIONotify(PAC97STREAMR3 pStreamCC)
1473	{
1474	LogFunc(("[SD%RU8]\n", pStreamCC->u8SD));
1475	return RTSemEventSignal(pStreamCC->State.AIO.Event);
1476	}
1477
1478	/**
1479	* Destroys the async I/O thread of a specific AC'97 audio stream.
1480	*
1481	* @returns VBox status code.
1482	* @param pThis The shared AC'97 state.
1483	* @param pStreamCC AC'97 audio stream to destroy the async I/O thread for.
1484	*/
1485	static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAMR3 pStreamR3)
1486	{
1487	RT_NOREF(pThis);
1488
1489	PAC97STREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
1490
1491	if (!ASMAtomicReadBool(&pAIO->fStarted))
1492	return VINF_SUCCESS;
1493
1494	ASMAtomicWriteBool(&pAIO->fShutdown, true);
1495
1496	int rc = ichac97R3StreamAsyncIONotify(pStreamR3);
1497	AssertRC(rc);
1498
1499	int rcThread;
1500	rc = RTThreadWait(pAIO->Thread, 30 * 1000 /* 30s timeout */, &rcThread);
1501	LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
1502
1503	if (RT_SUCCESS(rc))
1504	{
1505	rc = RTCritSectDelete(&pAIO->CritSect);
1506	AssertRC(rc);
1507
1508	rc = RTSemEventDestroy(pAIO->Event);
1509	AssertRC(rc);
1510
1511	pAIO->fStarted = false;
1512	pAIO->fShutdown = false;
1513	pAIO->fEnabled = false;
1514	}
1515
1516	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamR3->u8SD, rc));
1517	return rc;
1518	}
1519
1520	/**
1521	* Locks the async I/O thread of a specific AC'97 audio stream.
1522	*
1523	* @param pStreamCC AC'97 stream to lock async I/O thread for.
1524	*/
1525	static void ichac97R3StreamAsyncIOLock(PAC97STREAMR3 pStreamCC)
1526	{
1527	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1528
1529	if (!ASMAtomicReadBool(&pAIO->fStarted))
1530	return;
1531
1532	int rc2 = RTCritSectEnter(&pAIO->CritSect);
1533	AssertRC(rc2);
1534	}
1535
1536	/**
1537	* Unlocks the async I/O thread of a specific AC'97 audio stream.
1538	*
1539	* @param pStreamCC AC'97 stream to unlock async I/O thread for.
1540	*/
1541	static void ichac97R3StreamAsyncIOUnlock(PAC97STREAMR3 pStreamCC)
1542	{
1543	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1544
1545	if (!ASMAtomicReadBool(&pAIO->fStarted))
1546	return;
1547
1548	int rc2 = RTCritSectLeave(&pAIO->CritSect);
1549	AssertRC(rc2);
1550	}
1551
1552	#if 0 /* Unused */
1553	/**
1554	* Enables (resumes) or disables (pauses) the async I/O thread.
1555	*
1556	* @param pStream AC'97 stream to enable/disable async I/O thread for.
1557	* @param fEnable Whether to enable or disable the I/O thread.
1558	*
1559	* @remarks Does not do locking.
1560	*/
1561	static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable)
1562	{
1563	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1564	ASMAtomicXchgBool(&pAIO->fEnabled, fEnable);
1565	}
1566	#endif
1567	# endif /* VBOX_WITH_AUDIO_AC97_ASYNC_IO */
1568
1569	# ifdef LOG_ENABLED
1570	static void ichac97R3BDLEDumpAll(PPDMDEVINS pDevIns, uint64_t u64BDLBase, uint16_t cBDLE)
1571	{
1572	LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
1573	if (!u64BDLBase)
1574	return;
1575
1576	uint32_t cbBDLE = 0;
1577	for (uint16_t i = 0; i < cBDLE; i++)
1578	{
1579	AC97BDLE BDLE;
1580	PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase + i * sizeof(AC97BDLE), &BDLE, sizeof(AC97BDLE));
1581
1582	# ifndef RT_LITTLE_ENDIAN
1583	# error "Please adapt the code (audio buffers are little endian)!"
1584	# else
1585	BDLE.addr = RT_H2LE_U32(BDLE.addr & ~3);
1586	BDLE.ctl_len = RT_H2LE_U32(BDLE.ctl_len);
1587	#endif
1588	LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32 [%RU32 bytes], bup:%RTbool, ioc:%RTbool)\n",
1589	i, BDLE.addr,
1590	BDLE.ctl_len & AC97_BD_LEN_MASK,
1591	(BDLE.ctl_len & AC97_BD_LEN_MASK) << 1, /** @todo r=andy Assumes 16bit samples. */
1592	RT_BOOL(BDLE.ctl_len & AC97_BD_BUP),
1593	RT_BOOL(BDLE.ctl_len & AC97_BD_IOC)));
1594
1595	cbBDLE += (BDLE.ctl_len & AC97_BD_LEN_MASK) << 1; /** @todo r=andy Ditto. */
1596	}
1597
1598	LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
1599	}
1600	# endif /* LOG_ENABLED */
1601
1602	/**
1603	* Updates an AC'97 stream by doing its required data transfers.
1604	* The host sink(s) set the overall pace.
1605	*
1606	* This routine is called by both, the synchronous and the asynchronous
1607	* (VBOX_WITH_AUDIO_AC97_ASYNC_IO), implementations.
1608	*
1609	* When running synchronously, the device DMA transfers and the mixer sink
1610	* processing is within the device timer.
1611	*
1612	* When running asynchronously, only the device DMA transfers are done in the
1613	* device timer, whereas the mixer sink processing then is done in the stream's
1614	* own async I/O thread. This thread also will call this function
1615	* (with fInTimer set to @c false).
1616	*
1617	* @param pDevIns The device instance.
1618	* @param pThis The shared AC'97 state.
1619	* @param pThisCC The ring-3 AC'97 state.
1620	* @param pStream The AC'97 stream to update (shared).
1621	* @param pStreamCC The AC'97 stream to update (ring-3).
1622	* @param fInTimer Whether to this function was called from the timer
1623	* context or an asynchronous I/O stream thread (if supported).
1624	*/
1625	static void ichac97R3StreamUpdate(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
1626	PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fInTimer)
1627	{
1628	RT_NOREF(fInTimer);
1629
1630	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
1631	AssertPtr(pSink);
1632
1633	if (!AudioMixerSinkIsActive(pSink)) /* No sink available? Bail out. */
1634	return;
1635
1636	int rc2;
1637
1638	if (pStreamCC->State.Cfg.enmDir == PDMAUDIODIR_OUT) /* Output (SDO). */
1639	{
1640	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1641	if (fInTimer)
1642	# endif
1643	{
1644	const uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1645	if (cbStreamFree)
1646	{
1647	Log3Func(("[SD%RU8] PICB=%zu (%RU64ms), cbFree=%zu (%RU64ms), cbTransferChunk=%zu (%RU64ms)\n",
1648	pStream->u8SD,
1649	(pStream->Regs.picb << 1), PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, pStream->Regs.picb << 1),
1650	cbStreamFree, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, cbStreamFree),
1651	pStreamCC->State.cbTransferChunk, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, pStreamCC->State.cbTransferChunk)));
1652
1653	/* Do the DMA transfer. */
1654	rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC,
1655	RT_MIN(pStreamCC->State.cbTransferChunk, cbStreamFree));
1656	AssertRC(rc2);
1657
1658	pStreamCC->State.tsLastUpdateNs = RTTimeNanoTS();
1659	}
1660	}
1661
1662	Log3Func(("[SD%RU8] fInTimer=%RTbool\n", pStream->u8SD, fInTimer));
1663
1664	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1665	rc2 = ichac97R3StreamAsyncIONotify(pStreamCC);
1666	AssertRC(rc2);
1667	# endif
1668
1669	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1670	if (!fInTimer) /* In async I/O thread */
1671	{
1672	# endif
1673	const uint32_t cbSinkWritable = AudioMixerSinkGetWritable(pSink);
1674	const uint32_t cbStreamReadable = ichac97R3StreamGetUsed(pStreamCC);
1675	const uint32_t cbToReadFromStream = RT_MIN(cbStreamReadable, cbSinkWritable);
1676
1677	Log3Func(("[SD%RU8] cbSinkWritable=%RU32, cbStreamReadable=%RU32\n", pStream->u8SD, cbSinkWritable, cbStreamReadable));
1678
1679	if (cbToReadFromStream)
1680	{
1681	/* Read (guest output) data and write it to the stream's sink. */
1682	rc2 = ichac97R3StreamRead(pStreamCC, pSink, cbToReadFromStream, NULL /* pcbRead */);
1683	AssertRC(rc2);
1684	}
1685	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1686	}
1687	#endif
1688	/* When running synchronously, update the associated sink here.
1689	* Otherwise this will be done in the async I/O thread. */
1690	rc2 = AudioMixerSinkUpdate(pSink);
1691	AssertRC(rc2);
1692	}
1693	else /* Input (SDI). */
1694	{
1695	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1696	if (!fInTimer)
1697	{
1698	# endif
1699	rc2 = AudioMixerSinkUpdate(pSink);
1700	AssertRC(rc2);
1701
1702	/* Is the sink ready to be read (host input data) from? If so, by how much? */
1703	uint32_t cbSinkReadable = AudioMixerSinkGetReadable(pSink);
1704
1705	/* How much (guest input) data is available for writing at the moment for the AC'97 stream? */
1706	uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1707
1708	Log3Func(("[SD%RU8] cbSinkReadable=%RU32, cbStreamFree=%RU32\n", pStream->u8SD, cbSinkReadable, cbStreamFree));
1709
1710	/* Do not read more than the sink can provide at the moment.
1711	* The host sets the overall pace. */
1712	if (cbSinkReadable > cbStreamFree)
1713	cbSinkReadable = cbStreamFree;
1714
1715	if (cbSinkReadable)
1716	{
1717	/* Write (guest input) data to the stream which was read from stream's sink before. */
1718	rc2 = ichac97R3StreamWrite(pStreamCC, pSink, cbSinkReadable, NULL /* pcbWritten */);
1719	AssertRC(rc2);
1720	}
1721	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1722	}
1723	else /* fInTimer */
1724	{
1725	# endif
1726
1727	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1728	const uint64_t tsNowNs = RTTimeNanoTS();
1729	if (tsNowNs - pStreamCC->State.tsLastUpdateNs >= pStreamCC->State.Cfg.Device.cMsSchedulingHint * RT_NS_1MS)
1730	{
1731	rc2 = ichac97R3StreamAsyncIONotify(pStreamCC);
1732	AssertRC(rc2);
1733
1734	pStreamCC->State.tsLastUpdateNs = tsNowNs;
1735	}
1736	# endif
1737
1738	const uint32_t cbStreamUsed = ichac97R3StreamGetUsed(pStreamCC);
1739	if (cbStreamUsed)
1740	{
1741	/* When running synchronously, do the DMA data transfers here.
1742	* Otherwise this will be done in the stream's async I/O thread. */
1743	rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC, cbStreamUsed);
1744	AssertRC(rc2);
1745	}
1746	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1747	}
1748	# endif
1749	}
1750	}
1751
1752	#endif /* IN_RING3 */
1753
1754	/**
1755	* Sets a AC'97 mixer control to a specific value.
1756	*
1757	* @returns VBox status code.
1758	* @param pThis The shared AC'97 state.
1759	* @param uMixerIdx Mixer control to set value for.
1760	* @param uVal Value to set.
1761	*/
1762	static void ichac97MixerSet(PAC97STATE pThis, uint8_t uMixerIdx, uint16_t uVal)
1763	{
1764	AssertMsgReturnVoid(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1765	("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)));
1766
1767	LogRel2(("AC97: Setting mixer index #%RU8 to %RU16 (%RU8 %RU8)\n",
1768	uMixerIdx, uVal, RT_HI_U8(uVal), RT_LO_U8(uVal)));
1769
1770	pThis->mixer_data[uMixerIdx + 0] = RT_LO_U8(uVal);
1771	pThis->mixer_data[uMixerIdx + 1] = RT_HI_U8(uVal);
1772	}
1773
1774	/**
1775	* Gets a value from a specific AC'97 mixer control.
1776	*
1777	* @returns Retrieved mixer control value.
1778	* @param pThis The shared AC'97 state.
1779	* @param uMixerIdx Mixer control to get value for.
1780	*/
1781	static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t uMixerIdx)
1782	{
1783	AssertMsgReturn(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1784	("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)),
1785	UINT16_MAX);
1786	return RT_MAKE_U16(pThis->mixer_data[uMixerIdx + 0], pThis->mixer_data[uMixerIdx + 1]);
1787	}
1788
1789	#ifdef IN_RING3
1790
1791	/**
1792	* Retrieves a specific driver stream of a AC'97 driver.
1793	*
1794	* @returns Pointer to driver stream if found, or NULL if not found.
1795	* @param pDrv Driver to retrieve driver stream for.
1796	* @param enmDir Stream direction to retrieve.
1797	* @param dstSrc Stream destination / source to retrieve.
1798	*/
1799	static PAC97DRIVERSTREAM ichac97R3MixerGetDrvStream(PAC97DRIVER pDrv, PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc)
1800	{
1801	PAC97DRIVERSTREAM pDrvStream = NULL;
1802
1803	if (enmDir == PDMAUDIODIR_IN)
1804	{
1805	LogFunc(("enmRecSource=%d\n", dstSrc.enmSrc));
1806
1807	switch (dstSrc.enmSrc)
1808	{
1809	case PDMAUDIORECSRC_LINE:
1810	pDrvStream = &pDrv->LineIn;
1811	break;
1812	case PDMAUDIORECSRC_MIC:
1813	pDrvStream = &pDrv->MicIn;
1814	break;
1815	default:
1816	AssertFailed();
1817	break;
1818	}
1819	}
1820	else if (enmDir == PDMAUDIODIR_OUT)
1821	{
1822	LogFunc(("enmPlaybackDest=%d\n", dstSrc.enmDst));
1823
1824	switch (dstSrc.enmDst)
1825	{
1826	case PDMAUDIOPLAYBACKDST_FRONT:
1827	pDrvStream = &pDrv->Out;
1828	break;
1829	default:
1830	AssertFailed();
1831	break;
1832	}
1833	}
1834	else
1835	AssertFailed();
1836
1837	return pDrvStream;
1838	}
1839
1840	/**
1841	* Adds a driver stream to a specific mixer sink.
1842	*
1843	* @returns VBox status code.
1844	* @param pDevIns The device instance.
1845	* @param pMixSink Mixer sink to add driver stream to.
1846	* @param pCfg Stream configuration to use.
1847	* @param pDrv Driver stream to add.
1848	*/
1849	static int ichac97R3MixerAddDrvStream(PPDMDEVINS pDevIns, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PAC97DRIVER pDrv)
1850	{
1851	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1852
1853	PPDMAUDIOSTREAMCFG pStreamCfg = PDMAudioStrmCfgDup(pCfg);
1854	if (!pStreamCfg)
1855	return VERR_NO_MEMORY;
1856
1857	AssertCompile(sizeof(pStreamCfg->szName) == sizeof(pCfg->szName));
1858	RTStrCopy(pStreamCfg->szName, sizeof(pStreamCfg->szName), pCfg->szName);
1859
1860	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
1861
1862	int rc;
1863
1864	PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, pStreamCfg->enmDir, pStreamCfg->u);
1865	if (pDrvStream)
1866	{
1867	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
1868
1869	PAUDMIXSTREAM pMixStrm;
1870	rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, pDevIns, &pMixStrm);
1871	LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1872	if (RT_SUCCESS(rc))
1873	{
1874	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
1875	LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1876	if (RT_SUCCESS(rc))
1877	{
1878	/* If this is an input stream, always set the latest (added) stream
1879	* as the recording source. */
1880	/** @todo Make the recording source dynamic (CFGM?). */
1881	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
1882	{
1883	PDMAUDIOBACKENDCFG Cfg;
1884	rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
1885	if (RT_SUCCESS(rc))
1886	{
1887	if (Cfg.cMaxStreamsIn) /* At least one input source available? */
1888	{
1889	rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
1890	LogFlowFunc(("LUN#%RU8: Recording source for '%s' -> '%s', rc=%Rrc\n",
1891	pDrv->uLUN, pStreamCfg->szName, Cfg.szName, rc));
1892
1893	if (RT_SUCCESS(rc))
1894	LogRel2(("AC97: Set recording source for '%s' to '%s'\n", pStreamCfg->szName, Cfg.szName));
1895	}
1896	else
1897	LogRel(("AC97: Backend '%s' currently is not offering any recording source for '%s'\n",
1898	Cfg.szName, pStreamCfg->szName));
1899	}
1900	else if (RT_FAILURE(rc))
1901	LogFunc(("LUN#%RU8: Unable to retrieve backend configuratio for '%s', rc=%Rrc\n",
1902	pDrv->uLUN, pStreamCfg->szName, rc));
1903	}
1904	if (RT_FAILURE(rc))
1905	AudioMixerSinkRemoveStream(pMixSink, pMixStrm);
1906	}
1907	if (RT_FAILURE(rc))
1908	AudioMixerStreamDestroy(pMixStrm, pDevIns);
1909	}
1910
1911	if (RT_SUCCESS(rc))
1912	pDrvStream->pMixStrm = pMixStrm;
1913	}
1914	else
1915	rc = VERR_INVALID_PARAMETER;
1916
1917	PDMAudioStrmCfgFree(pStreamCfg);
1918
1919	LogFlowFuncLeaveRC(rc);
1920	return rc;
1921	}
1922
1923	/**
1924	* Adds all current driver streams to a specific mixer sink.
1925	*
1926	* @returns VBox status code.
1927	* @param pDevIns The device instance.
1928	* @param pThisCC The ring-3 AC'97 state.
1929	* @param pMixSink Mixer sink to add stream to.
1930	* @param pCfg Stream configuration to use.
1931	*/
1932	static int ichac97R3MixerAddDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
1933	{
1934	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1935
1936	if (!AudioHlpStreamCfgIsValid(pCfg))
1937	return VERR_INVALID_PARAMETER;
1938
1939	int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
1940	if (RT_FAILURE(rc))
1941	return rc;
1942
1943	PAC97DRIVER pDrv;
1944	RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
1945	{
1946	int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pMixSink, pCfg, pDrv);
1947	if (RT_FAILURE(rc2))
1948	LogFunc(("Attaching stream failed with %Rrc\n", rc2));
1949
1950	/* Do not pass failure to rc here, as there might be drivers which aren't
1951	* configured / ready yet. */
1952	}
1953
1954	LogFlowFuncLeaveRC(rc);
1955	return rc;
1956	}
1957
1958	/**
1959	* Adds a specific AC'97 driver to the driver chain.
1960	*
1961	* @returns VBox status code.
1962	* @param pDevIns The device instance.
1963	* @param pThisCC The ring-3 AC'97 device state.
1964	* @param pDrv The AC'97 driver to add.
1965	*/
1966	static int ichac97R3MixerAddDrv(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
1967	{
1968	int rc = VINF_SUCCESS;
1969
1970	if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg))
1971	rc = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkLineIn,
1972	&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg, pDrv);
1973
1974	if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg))
1975	{
1976	int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkOut,
1977	&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg, pDrv);
1978	if (RT_SUCCESS(rc))
1979	rc = rc2;
1980	}
1981
1982	if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg))
1983	{
1984	int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkMicIn,
1985	&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg, pDrv);
1986	if (RT_SUCCESS(rc))
1987	rc = rc2;
1988	}
1989
1990	return rc;
1991	}
1992
1993	/**
1994	* Removes a specific AC'97 driver from the driver chain and destroys its
1995	* associated streams.
1996	*
1997	* @param pDevIns The device instance.
1998	* @param pThisCC The ring-3 AC'97 device state.
1999	* @param pDrv AC'97 driver to remove.
2000	*/
2001	static void ichac97R3MixerRemoveDrv(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
2002	{
2003	if (pDrv->MicIn.pMixStrm)
2004	{
2005	if (AudioMixerSinkGetRecordingSource(pThisCC->pSinkMicIn) == pDrv->MicIn.pMixStrm)
2006	AudioMixerSinkSetRecordingSource(pThisCC->pSinkMicIn, NULL);
2007
2008	AudioMixerSinkRemoveStream(pThisCC->pSinkMicIn, pDrv->MicIn.pMixStrm);
2009	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm, pDevIns);
2010	pDrv->MicIn.pMixStrm = NULL;
2011	}
2012
2013	if (pDrv->LineIn.pMixStrm)
2014	{
2015	if (AudioMixerSinkGetRecordingSource(pThisCC->pSinkLineIn) == pDrv->LineIn.pMixStrm)
2016	AudioMixerSinkSetRecordingSource(pThisCC->pSinkLineIn, NULL);
2017
2018	AudioMixerSinkRemoveStream(pThisCC->pSinkLineIn, pDrv->LineIn.pMixStrm);
2019	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm, pDevIns);
2020	pDrv->LineIn.pMixStrm = NULL;
2021	}
2022
2023	if (pDrv->Out.pMixStrm)
2024	{
2025	AudioMixerSinkRemoveStream(pThisCC->pSinkOut, pDrv->Out.pMixStrm);
2026	AudioMixerStreamDestroy(pDrv->Out.pMixStrm, pDevIns);
2027	pDrv->Out.pMixStrm = NULL;
2028	}
2029
2030	RTListNodeRemove(&pDrv->Node);
2031	}
2032
2033	/**
2034	* Removes a driver stream from a specific mixer sink.
2035	*
2036	* @param pDevIns The device instance.
2037	* @param pMixSink Mixer sink to remove audio streams from.
2038	* @param enmDir Stream direction to remove.
2039	* @param dstSrc Stream destination / source to remove.
2040	* @param pDrv Driver stream to remove.
2041	*/
2042	static void ichac97R3MixerRemoveDrvStream(PPDMDEVINS pDevIns, PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir,
2043	PDMAUDIODSTSRCUNION dstSrc, PAC97DRIVER pDrv)
2044	{
2045	PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, enmDir, dstSrc);
2046	if (pDrvStream)
2047	{
2048	if (pDrvStream->pMixStrm)
2049	{
2050	AudioMixerSinkRemoveStream(pMixSink, pDrvStream->pMixStrm);
2051
2052	AudioMixerStreamDestroy(pDrvStream->pMixStrm, pDevIns);
2053	pDrvStream->pMixStrm = NULL;
2054	}
2055	}
2056	}
2057
2058	/**
2059	* Removes all driver streams from a specific mixer sink.
2060	*
2061	* @param pDevIns The device instance.
2062	* @param pThisCC The ring-3 AC'97 state.
2063	* @param pMixSink Mixer sink to remove audio streams from.
2064	* @param enmDir Stream direction to remove.
2065	* @param dstSrc Stream destination / source to remove.
2066	*/
2067	static void ichac97R3MixerRemoveDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
2068	PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc)
2069	{
2070	AssertPtrReturnVoid(pMixSink);
2071
2072	PAC97DRIVER pDrv;
2073	RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
2074	{
2075	ichac97R3MixerRemoveDrvStream(pDevIns, pMixSink, enmDir, dstSrc, pDrv);
2076	}
2077	}
2078
2079	/**
2080	* Calculates and returns the ticks for a specified amount of bytes.
2081	*
2082	* @returns Calculated ticks
2083	* @param pDevIns The device instance.
2084	* @param pStream AC'97 stream to calculate ticks for (shared).
2085	* @param pStreamCC AC'97 stream to calculate ticks for (ring-3).
2086	* @param cbBytes Bytes to calculate ticks for.
2087	*/
2088	static uint64_t ichac97R3StreamTransferCalcNext(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint32_t cbBytes)
2089	{
2090	if (!cbBytes)
2091	return 0;
2092
2093	const uint64_t usBytes = PDMAudioPropsBytesToMicro(&pStreamCC->State.Cfg.Props, cbBytes);
2094	const uint64_t cTransferTicks = PDMDevHlpTimerFromMicro(pDevIns, pStream->hTimer, usBytes);
2095
2096	Log3Func(("[SD%RU8] Timer %uHz, cbBytes=%RU32 -> usBytes=%RU64, cTransferTicks=%RU64\n",
2097	pStream->u8SD, pStreamCC->State.uTimerHz, cbBytes, usBytes, cTransferTicks));
2098
2099	return cTransferTicks;
2100	}
2101
2102	/**
2103	* Updates the next transfer based on a specific amount of bytes.
2104	*
2105	* @param pDevIns The device instance.
2106	* @param pStream The AC'97 stream to update (shared).
2107	* @param pStreamCC The AC'97 stream to update (ring-3).
2108	* @param cbBytes Bytes to update next transfer for.
2109	*/
2110	static void ichac97R3StreamTransferUpdate(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint32_t cbBytes)
2111	{
2112	if (!cbBytes)
2113	return;
2114
2115	/* Calculate the bytes we need to transfer to / from the stream's DMA per iteration.
2116	* This is bound to the device's Hz rate and thus to the (virtual) timing the device expects. */
2117	pStreamCC->State.cbTransferChunk = cbBytes;
2118
2119	/* Update the transfer ticks. */
2120	pStreamCC->State.cTransferTicks = ichac97R3StreamTransferCalcNext(pDevIns, pStream, pStreamCC,
2121	pStreamCC->State.cbTransferChunk);
2122	Assert(pStreamCC->State.cTransferTicks); /* Paranoia. */
2123	}
2124
2125	/**
2126	* Opens an AC'97 stream with its current mixer settings.
2127	*
2128	* This will open an AC'97 stream with 2 (stereo) channels, 16-bit samples and
2129	* the last set sample rate in the AC'97 mixer for this stream.
2130	*
2131	* @returns VBox status code.
2132	* @param pDevIns The device instance.
2133	* @param pThis The shared AC'97 device state (shared).
2134	* @param pThisCC The shared AC'97 device state (ring-3).
2135	* @param pStream The AC'97 stream to open (shared).
2136	* @param pStreamCC The AC'97 stream to open (ring-3).
2137	* @param fForce Whether to force re-opening the stream or not.
2138	* Otherwise re-opening only will happen if the PCM properties have changed.
2139	*/
2140	static int ichac97R3StreamOpen(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
2141	PAC97STREAMR3 pStreamCC, bool fForce)
2142	{
2143	int rc = VINF_SUCCESS;
2144	PAUDMIXSINK pMixSink;
2145	PDMAUDIOSTREAMCFG Cfg;
2146	RT_ZERO(Cfg);
2147	switch (pStream->u8SD)
2148	{
2149	case AC97SOUNDSOURCE_PI_INDEX:
2150	{
2151	PDMAudioPropsInit(&Cfg.Props, 2 /16-bit/, true /signed/, 2 /stereo/,
2152	ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate));
2153	Cfg.enmDir = PDMAUDIODIR_IN;
2154	Cfg.u.enmSrc = PDMAUDIORECSRC_LINE;
2155	Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2156	RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Line-In");
2157
2158	pMixSink = pThisCC->pSinkLineIn;
2159	break;
2160	}
2161
2162	case AC97SOUNDSOURCE_MC_INDEX:
2163	{
2164	PDMAudioPropsInit(&Cfg.Props, 2 /16-bit/, true /signed/, 2 /stereo/,
2165	ichac97MixerGet(pThis, AC97_MIC_ADC_Rate));
2166	Cfg.enmDir = PDMAUDIODIR_IN;
2167	Cfg.u.enmSrc = PDMAUDIORECSRC_MIC;
2168	Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2169	RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Mic-In");
2170
2171	pMixSink = pThisCC->pSinkMicIn;
2172	break;
2173	}
2174
2175	case AC97SOUNDSOURCE_PO_INDEX:
2176	{
2177	PDMAudioPropsInit(&Cfg.Props, 2 /16-bit/, true /signed/, 2 /stereo/,
2178	ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate));
2179	Cfg.enmDir = PDMAUDIODIR_OUT;
2180	Cfg.u.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
2181	Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2182	RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Output");
2183
2184	pMixSink = pThisCC->pSinkOut;
2185	break;
2186	}
2187
2188	default:
2189	rc = VERR_NOT_SUPPORTED;
2190	pMixSink = NULL;
2191	break;
2192	}
2193
2194	if (RT_SUCCESS(rc))
2195	{
2196	/* Only (re-)create the stream (and driver chain) if we really have to.
2197	* Otherwise avoid this and just reuse it, as this costs performance. */
2198	if ( !PDMAudioStrmCfgMatchesProps(&Cfg, &pStreamCC->State.Cfg.Props)
2199	\|\| fForce)
2200	{
2201	LogRel2(("AC97: (Re-)Opening stream '%s' (%RU32Hz, %RU8 channels, %s%RU8)\n", Cfg.szName, Cfg.Props.uHz,
2202	PDMAudioPropsChannels(&Cfg.Props), Cfg.Props.fSigned ? "S" : "U", PDMAudioPropsSampleBits(&Cfg.Props)));
2203
2204	LogFlowFunc(("[SD%RU8] uHz=%RU32\n", pStream->u8SD, Cfg.Props.uHz));
2205
2206	if (Cfg.Props.uHz)
2207	{
2208	Assert(Cfg.enmDir != PDMAUDIODIR_UNKNOWN);
2209
2210	/*
2211	* Set the stream's timer Hz rate, based on the PCM properties Hz rate.
2212	*/
2213	if (pThis->uTimerHz == AC97_TIMER_HZ_DEFAULT) /* Make sure that we don't have any custom Hz rate set we want to enforce */
2214	{
2215	if (Cfg.Props.uHz > 44100) /* E.g. 48000 Hz. */
2216	pStreamCC->State.uTimerHz = 200;
2217	else /* Just take the global Hz rate otherwise. */
2218	pStreamCC->State.uTimerHz = pThis->uTimerHz;
2219	}
2220	else
2221	pStreamCC->State.uTimerHz = pThis->uTimerHz;
2222
2223	/* Set scheduling hint (if available). */
2224	if (pStreamCC->State.uTimerHz)
2225	Cfg.Device.cMsSchedulingHint = 1000 /* ms */ / pStreamCC->State.uTimerHz;
2226
2227	if (pStreamCC->State.pCircBuf)
2228	{
2229	RTCircBufDestroy(pStreamCC->State.pCircBuf);
2230	pStreamCC->State.pCircBuf = NULL;
2231	}
2232
2233	rc = RTCircBufCreate(&pStreamCC->State.pCircBuf, PDMAudioPropsMilliToBytes(&Cfg.Props, 100 /ms/)); /** @todo Make this configurable. */
2234	if (RT_SUCCESS(rc))
2235	{
2236	ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pMixSink, Cfg.enmDir, Cfg.u);
2237
2238	rc = ichac97R3MixerAddDrvStreams(pDevIns, pThisCC, pMixSink, &Cfg);
2239	if (RT_SUCCESS(rc))
2240	rc = PDMAudioStrmCfgCopy(&pStreamCC->State.Cfg, &Cfg);
2241	}
2242	}
2243	}
2244	else
2245	LogFlowFunc(("[SD%RU8] Skipping (re-)creation\n", pStream->u8SD));
2246	}
2247
2248	LogFlowFunc(("[SD%RU8] rc=%Rrc\n", pStream->u8SD, rc));
2249	return rc;
2250	}
2251
2252	/**
2253	* Closes an AC'97 stream.
2254	*
2255	* @returns VBox status code.
2256	* @param pStream The AC'97 stream to close (shared).
2257	*/
2258	static int ichac97R3StreamClose(PAC97STREAM pStream)
2259	{
2260	RT_NOREF(pStream);
2261	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2262	return VINF_SUCCESS;
2263	}
2264
2265	/**
2266	* Re-opens (that is, closes and opens again) an AC'97 stream on the backend
2267	* side with the current AC'97 mixer settings for this stream.
2268	*
2269	* @returns VBox status code.
2270	* @param pDevIns The device instance.
2271	* @param pThis The shared AC'97 device state.
2272	* @param pThisCC The ring-3 AC'97 device state.
2273	* @param pStream The AC'97 stream to re-open (shared).
2274	* @param pStreamCC The AC'97 stream to re-open (ring-3).
2275	* @param fForce Whether to force re-opening the stream or not.
2276	* Otherwise re-opening only will happen if the PCM properties have changed.
2277	*/
2278	static int ichac97R3StreamReOpen(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
2279	PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2280	{
2281	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2282	Assert(pStream->u8SD == pStreamCC->u8SD);
2283	Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2284	Assert(pStreamCC - &pThisCC->aStreams[0] == pStream->u8SD);
2285
2286	int rc = ichac97R3StreamClose(pStream);
2287	if (RT_SUCCESS(rc))
2288	rc = ichac97R3StreamOpen(pDevIns, pThis, pThisCC, pStream, pStreamCC, fForce);
2289
2290	return rc;
2291	}
2292
2293	/**
2294	* Locks an AC'97 stream for serialized access.
2295	*
2296	* @returns VBox status code.
2297	* @param pStreamCC The AC'97 stream to lock (ring-3).
2298	*/
2299	static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC)
2300	{
2301	int rc2 = RTCritSectEnter(&pStreamCC->State.CritSect);
2302	AssertRC(rc2);
2303	}
2304
2305	/**
2306	* Unlocks a formerly locked AC'97 stream.
2307	*
2308	* @returns VBox status code.
2309	* @param pStreamCC The AC'97 stream to unlock (ring-3).
2310	*/
2311	static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC)
2312	{
2313	int rc2 = RTCritSectLeave(&pStreamCC->State.CritSect);
2314	AssertRC(rc2);
2315	}
2316
2317	/**
2318	* Retrieves the available size of (buffered) audio data (in bytes) of a given AC'97 stream.
2319	*
2320	* @returns Available data (in bytes).
2321	* @param pStreamCC The AC'97 stream to retrieve size for (ring-3).
2322	*/
2323	static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC)
2324	{
2325	if (!pStreamCC->State.pCircBuf)
2326	return 0;
2327
2328	return (uint32_t)RTCircBufUsed(pStreamCC->State.pCircBuf);
2329	}
2330
2331	/**
2332	* Retrieves the free size of audio data (in bytes) of a given AC'97 stream.
2333	*
2334	* @returns Free data (in bytes).
2335	* @param pStreamCC AC'97 stream to retrieve size for (ring-3).
2336	*/
2337	static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC)
2338	{
2339	if (!pStreamCC->State.pCircBuf)
2340	return 0;
2341
2342	return (uint32_t)RTCircBufFree(pStreamCC->State.pCircBuf);
2343	}
2344
2345	/**
2346	* Sets the volume of a specific AC'97 mixer control.
2347	*
2348	* This currently only supports attenuation -- gain support is currently not implemented.
2349	*
2350	* @returns VBox status code.
2351	* @param pThis The shared AC'97 state.
2352	* @param pThisCC The ring-3 AC'97 state.
2353	* @param index AC'97 mixer index to set volume for.
2354	* @param enmMixerCtl Corresponding audio mixer sink.
2355	* @param uVal Volume value to set.
2356	*/
2357	static int ichac97R3MixerSetVolume(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2358	{
2359	/*
2360	* From AC'97 SoundMax Codec AD1981A/AD1981B:
2361	* "Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the
2362	* D5 or D13 bits are set to 1, their respective lower five volume bits are automatically
2363	* set to 1 by the Codec logic. On readback, all lower 5 bits will read ones whenever
2364	* these bits are set to 1."
2365	*
2366	* Linux ALSA depends on this behavior to detect that only 5 bits are used for volume
2367	* control and the optional 6th bit is not used. Note that this logic only applies to the
2368	* master volume controls.
2369	*/
2370	if (index == AC97_Master_Volume_Mute \|\| index == AC97_Headphone_Volume_Mute \|\| index == AC97_Master_Volume_Mono_Mute)
2371	{
2372	if (uVal & RT_BIT(5)) /* D5 bit set? */
2373	uVal \|= RT_BIT(4) \| RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1) \| RT_BIT(0);
2374	if (uVal & RT_BIT(13)) /* D13 bit set? */
2375	uVal \|= RT_BIT(12) \| RT_BIT(11) \| RT_BIT(10) \| RT_BIT(9) \| RT_BIT(8);
2376	}
2377
2378	const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2379	uint8_t uCtlAttLeft = (uVal >> 8) & AC97_BARS_VOL_MASK;
2380	uint8_t uCtlAttRight = uVal & AC97_BARS_VOL_MASK;
2381
2382	/* For the master and headphone volume, 0 corresponds to 0dB attenuation. For the other
2383	* volume controls, 0 means 12dB gain and 8 means unity gain.
2384	*/
2385	if (index != AC97_Master_Volume_Mute && index != AC97_Headphone_Volume_Mute)
2386	{
2387	# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2388	/* NB: Currently there is no gain support, only attenuation. */
2389	uCtlAttLeft = uCtlAttLeft < 8 ? 0 : uCtlAttLeft - 8;
2390	uCtlAttRight = uCtlAttRight < 8 ? 0 : uCtlAttRight - 8;
2391	# endif
2392	}
2393	Assert(uCtlAttLeft <= 255 / AC97_DB_FACTOR);
2394	Assert(uCtlAttRight <= 255 / AC97_DB_FACTOR);
2395
2396	LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2397	LogFunc(("uCtlAttLeft=%RU8, uCtlAttRight=%RU8 ", uCtlAttLeft, uCtlAttRight));
2398
2399	/*
2400	* For AC'97 volume controls, each additional step means -1.5dB attenuation with
2401	* zero being maximum. In contrast, we're internally using 255 (PDMAUDIO_VOLUME_MAX)
2402	* steps, each -0.375dB, where 0 corresponds to -96dB and 255 corresponds to 0dB.
2403	*/
2404	uint8_t lVol = PDMAUDIO_VOLUME_MAX - uCtlAttLeft * AC97_DB_FACTOR;
2405	uint8_t rVol = PDMAUDIO_VOLUME_MAX - uCtlAttRight * AC97_DB_FACTOR;
2406
2407	Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2408
2409	int rc = VINF_SUCCESS;
2410
2411	if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2412	{
2413	PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2414	PAUDMIXSINK pSink = NULL;
2415
2416	switch (enmMixerCtl)
2417	{
2418	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2419	rc = AudioMixerSetMasterVolume(pThisCC->pMixer, &Vol);
2420	break;
2421
2422	case PDMAUDIOMIXERCTL_FRONT:
2423	pSink = pThisCC->pSinkOut;
2424	break;
2425
2426	case PDMAUDIOMIXERCTL_MIC_IN:
2427	case PDMAUDIOMIXERCTL_LINE_IN:
2428	/* These are recognized but do nothing. */
2429	break;
2430
2431	default:
2432	AssertFailed();
2433	rc = VERR_NOT_SUPPORTED;
2434	break;
2435	}
2436
2437	if (pSink)
2438	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2439	}
2440
2441	ichac97MixerSet(pThis, index, uVal);
2442
2443	if (RT_FAILURE(rc))
2444	LogFlowFunc(("Failed with %Rrc\n", rc));
2445
2446	return rc;
2447	}
2448
2449	/**
2450	* Sets the gain of a specific AC'97 recording control.
2451	*
2452	* NB: gain support is currently not implemented in PDM audio.
2453	*
2454	* @returns VBox status code.
2455	* @param pThis The shared AC'97 state.
2456	* @param pThisCC The ring-3 AC'97 state.
2457	* @param index AC'97 mixer index to set volume for.
2458	* @param enmMixerCtl Corresponding audio mixer sink.
2459	* @param uVal Volume value to set.
2460	*/
2461	static int ichac97R3MixerSetGain(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2462	{
2463	/*
2464	* For AC'97 recording controls, each additional step means +1.5dB gain with
2465	* zero being 0dB gain and 15 being +22.5dB gain.
2466	*/
2467	const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2468	uint8_t uCtlGainLeft = (uVal >> 8) & AC97_BARS_GAIN_MASK;
2469	uint8_t uCtlGainRight = uVal & AC97_BARS_GAIN_MASK;
2470
2471	Assert(uCtlGainLeft <= 255 / AC97_DB_FACTOR);
2472	Assert(uCtlGainRight <= 255 / AC97_DB_FACTOR);
2473
2474	LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2475	LogFunc(("uCtlGainLeft=%RU8, uCtlGainRight=%RU8 ", uCtlGainLeft, uCtlGainRight));
2476
2477	uint8_t lVol = PDMAUDIO_VOLUME_MAX + uCtlGainLeft * AC97_DB_FACTOR;
2478	uint8_t rVol = PDMAUDIO_VOLUME_MAX + uCtlGainRight * AC97_DB_FACTOR;
2479
2480	/* We do not currently support gain. Since AC'97 does not support attenuation
2481	* for the recording input, the best we can do is set the maximum volume.
2482	*/
2483	# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2484	/* NB: Currently there is no gain support, only attenuation. Since AC'97 does not
2485	* support attenuation for the recording inputs, the best we can do is set the
2486	* maximum volume.
2487	*/
2488	lVol = rVol = PDMAUDIO_VOLUME_MAX;
2489	# endif
2490
2491	Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2492
2493	int rc = VINF_SUCCESS;
2494
2495	if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2496	{
2497	PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2498	PAUDMIXSINK pSink = NULL;
2499
2500	switch (enmMixerCtl)
2501	{
2502	case PDMAUDIOMIXERCTL_MIC_IN:
2503	pSink = pThisCC->pSinkMicIn;
2504	break;
2505
2506	case PDMAUDIOMIXERCTL_LINE_IN:
2507	pSink = pThisCC->pSinkLineIn;
2508	break;
2509
2510	default:
2511	AssertFailed();
2512	rc = VERR_NOT_SUPPORTED;
2513	break;
2514	}
2515
2516	if (pSink) {
2517	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2518	/* There is only one AC'97 recording gain control. If line in
2519	* is changed, also update the microphone. If the optional dedicated
2520	* microphone is changed, only change that.
2521	* NB: The codecs we support do not have the dedicated microphone control.
2522	*/
2523	if ((pSink == pThisCC->pSinkLineIn) && pThisCC->pSinkMicIn)
2524	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2525	}
2526	}
2527
2528	ichac97MixerSet(pThis, index, uVal);
2529
2530	if (RT_FAILURE(rc))
2531	LogFlowFunc(("Failed with %Rrc\n", rc));
2532
2533	return rc;
2534	}
2535
2536	/**
2537	* Converts an AC'97 recording source index to a PDM audio recording source.
2538	*
2539	* @returns PDM audio recording source.
2540	* @param uIdx AC'97 index to convert.
2541	*/
2542	static PDMAUDIORECSRC ichac97R3IdxToRecSource(uint8_t uIdx)
2543	{
2544	switch (uIdx)
2545	{
2546	case AC97_REC_MIC: return PDMAUDIORECSRC_MIC;
2547	case AC97_REC_CD: return PDMAUDIORECSRC_CD;
2548	case AC97_REC_VIDEO: return PDMAUDIORECSRC_VIDEO;
2549	case AC97_REC_AUX: return PDMAUDIORECSRC_AUX;
2550	case AC97_REC_LINE_IN: return PDMAUDIORECSRC_LINE;
2551	case AC97_REC_PHONE: return PDMAUDIORECSRC_PHONE;
2552	default:
2553	break;
2554	}
2555
2556	LogFlowFunc(("Unknown record source %d, using MIC\n", uIdx));
2557	return PDMAUDIORECSRC_MIC;
2558	}
2559
2560	/**
2561	* Converts a PDM audio recording source to an AC'97 recording source index.
2562	*
2563	* @returns AC'97 recording source index.
2564	* @param enmRecSrc PDM audio recording source to convert.
2565	*/
2566	static uint8_t ichac97R3RecSourceToIdx(PDMAUDIORECSRC enmRecSrc)
2567	{
2568	switch (enmRecSrc)
2569	{
2570	case PDMAUDIORECSRC_MIC: return AC97_REC_MIC;
2571	case PDMAUDIORECSRC_CD: return AC97_REC_CD;
2572	case PDMAUDIORECSRC_VIDEO: return AC97_REC_VIDEO;
2573	case PDMAUDIORECSRC_AUX: return AC97_REC_AUX;
2574	case PDMAUDIORECSRC_LINE: return AC97_REC_LINE_IN;
2575	case PDMAUDIORECSRC_PHONE: return AC97_REC_PHONE;
2576	/* no default */
2577	case PDMAUDIORECSRC_UNKNOWN:
2578	case PDMAUDIORECSRC_END:
2579	case PDMAUDIORECSRC_32BIT_HACK:
2580	break;
2581	}
2582
2583	LogFlowFunc(("Unknown audio recording source %d using MIC\n", enmRecSrc));
2584	return AC97_REC_MIC;
2585	}
2586
2587	/**
2588	* Returns the audio direction of a specified stream descriptor.
2589	*
2590	* @return Audio direction.
2591	*/
2592	DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD)
2593	{
2594	switch (uSD)
2595	{
2596	case AC97SOUNDSOURCE_PI_INDEX: return PDMAUDIODIR_IN;
2597	case AC97SOUNDSOURCE_PO_INDEX: return PDMAUDIODIR_OUT;
2598	case AC97SOUNDSOURCE_MC_INDEX: return PDMAUDIODIR_IN;
2599	}
2600
2601	AssertFailed();
2602	return PDMAUDIODIR_UNKNOWN;
2603	}
2604
2605	#endif /* IN_RING3 */
2606
2607	#ifdef IN_RING3
2608
2609	/**
2610	* Performs an AC'97 mixer record select to switch to a different recording
2611	* source.
2612	*
2613	* @param pThis The shared AC'97 state.
2614	* @param val AC'97 recording source index to set.
2615	*/
2616	static void ichac97R3MixerRecordSelect(PAC97STATE pThis, uint32_t val)
2617	{
2618	uint8_t rs = val & AC97_REC_MASK;
2619	uint8_t ls = (val >> 8) & AC97_REC_MASK;
2620
2621	const PDMAUDIORECSRC ars = ichac97R3IdxToRecSource(rs);
2622	const PDMAUDIORECSRC als = ichac97R3IdxToRecSource(ls);
2623
2624	rs = ichac97R3RecSourceToIdx(ars);
2625	ls = ichac97R3RecSourceToIdx(als);
2626
2627	LogRel(("AC97: Record select to left=%s, right=%s\n", PDMAudioRecSrcGetName(ars), PDMAudioRecSrcGetName(als)));
2628
2629	ichac97MixerSet(pThis, AC97_Record_Select, rs \| (ls << 8));
2630	}
2631
2632	/**
2633	* Resets the AC'97 mixer.
2634	*
2635	* @returns VBox status code.
2636	* @param pThis The shared AC'97 state.
2637	* @param pThisCC The ring-3 AC'97 state.
2638	*/
2639	static int ichac97R3MixerReset(PAC97STATE pThis, PAC97STATER3 pThisCC)
2640	{
2641	LogFlowFuncEnter();
2642
2643	RT_ZERO(pThis->mixer_data);
2644
2645	/* Note: Make sure to reset all registers first before bailing out on error. */
2646
2647	ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
2648	ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
2649	ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
2650
2651	ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
2652	ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
2653	ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
2654	ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
2655	ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
2656	ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
2657	ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
2658	ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
2659
2660	/* Configure Extended Audio ID (EAID) + Control & Status (EACS) registers. */
2661	const uint16_t fEAID = AC97_EAID_REV1 \| AC97_EACS_VRA \| AC97_EACS_VRM; /* Our hardware is AC'97 rev2.3 compliant. */
2662	const uint16_t fEACS = AC97_EACS_VRA \| AC97_EACS_VRM; /* Variable Rate PCM Audio (VRA) + Mic-In (VRM) capable. */
2663
2664	LogRel(("AC97: Mixer reset (EAID=0x%x, EACS=0x%x)\n", fEAID, fEACS));
2665
2666	ichac97MixerSet(pThis, AC97_Extended_Audio_ID, fEAID);
2667	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, fEACS);
2668	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2669	ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2670	ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2671	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2672	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2673
2674	if (pThis->enmCodecModel == AC97CODEC_AD1980)
2675	{
2676	/* Analog Devices 1980 (AD1980) */
2677	ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
2678	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2679	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
2680	ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
2681	}
2682	else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
2683	{
2684	/* Analog Devices 1981B (AD1981B) */
2685	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2686	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
2687	}
2688	else
2689	{
2690	/* Sigmatel 9700 (STAC9700) */
2691	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
2692	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
2693	}
2694	ichac97R3MixerRecordSelect(pThis, 0);
2695
2696	/* The default value is 8000h, which corresponds to 0 dB attenuation with mute on. */
2697	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER, 0x8000);
2698
2699	/* The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on.*/
2700	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT, 0x8808);
2701	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
2702	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8008);
2703
2704	/* The default for record controls is 0 dB gain with mute on. */
2705	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8000);
2706	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8000);
2707
2708	return VINF_SUCCESS;
2709	}
2710
2711	# if 0 /* Unused */
2712	static void ichac97R3WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
2713	{
2714	LogFlowFunc(("cbElapsed=%RU32\n", cbElapsed));
2715
2716	if (!(pThis->bup_flag & BUP_SET))
2717	{
2718	if (pThis->bup_flag & BUP_LAST)
2719	{
2720	unsigned int i;
2721	uint32_t p = (uint32_t)pThis->silence;
2722	for (i = 0; i < sizeof(pThis->silence) / 4; i++) /** @todo r=andy Assumes 16-bit samples, stereo. */
2723	*p++ = pThis->last_samp;
2724	}
2725	else
2726	RT_ZERO(pThis->silence);
2727
2728	pThis->bup_flag \|= BUP_SET;
2729	}
2730
2731	while (cbElapsed)
2732	{
2733	uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
2734	uint32_t cbWrittenToStream;
2735
2736	int rc2 = AudioMixerSinkWrite(pThisCC->pSinkOut, AUDMIXOP_COPY,
2737	pThis->silence, cbToWrite, &cbWrittenToStream);
2738	if (RT_SUCCESS(rc2))
2739	{
2740	if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2741	LogFlowFunc(("Warning: Only written %RU32 / %RU32 bytes, expect lags\n", cbWrittenToStream, cbToWrite));
2742	}
2743
2744	/* Always report all data as being written;
2745	* backends who were not able to catch up have to deal with it themselves. */
2746	Assert(cbElapsed >= cbToWrite);
2747	cbElapsed -= cbToWrite;
2748	}
2749	}
2750	# endif /* Unused */
2751
2752	/**
2753	* @callback_method_impl{FNTMTIMERDEV,
2754	* Timer callback which handles the audio data transfers on a periodic basis.}
2755	*/
2756	static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
2757	{
2758	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2759	STAM_PROFILE_START(&pThis->StatTimer, a);
2760	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
2761	PAC97STREAM pStream = (PAC97STREAM)pvUser;
2762	PAC97STREAMR3 pStreamCC = &RT_SAFE_SUBSCRIPT8(pThisCC->aStreams, pStream->u8SD);
2763	Assert(hTimer == pStream->hTimer); RT_NOREF(hTimer);
2764
2765	Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2766	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2767	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStream->hTimer));
2768
2769	ichac97R3StreamUpdate(pDevIns, pThis, pThisCC, pStream, pStreamCC, true /* fInTimer */);
2770
2771	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
2772	if (pSink && AudioMixerSinkIsActive(pSink))
2773	{
2774	ichac97R3StreamTransferUpdate(pDevIns, pStream, pStreamCC, pStream->Regs.picb << 1); /** @todo r=andy Assumes 16-bit samples. */
2775	ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
2776	}
2777
2778	STAM_PROFILE_STOP(&pThis->StatTimer, a);
2779	}
2780
2781
2782	/**
2783	* Sets the virtual device timer to a new expiration time.
2784	*
2785	* @param pDevIns The device instance.
2786	* @param pStream AC'97 stream to set timer for.
2787	* @param cTicksToDeadline The number of ticks to the new deadline.
2788	*
2789	* @remarks This used to be more complicated a long time ago...
2790	*/
2791	DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline)
2792	{
2793	int rc = PDMDevHlpTimerSetRelative(pDevIns, pStream->hTimer, cTicksToDeadline, NULL /pu64Now/);
2794	AssertRC(rc);
2795	}
2796
2797
2798	/**
2799	* Transfers data of an AC'97 stream according to its usage (input / output).
2800	*
2801	* For an SDO (output) stream this means reading DMA data from the device to
2802	* the AC'97 stream's internal FIFO buffer.
2803	*
2804	* For an SDI (input) stream this is reading audio data from the AC'97 stream's
2805	* internal FIFO buffer and writing it as DMA data to the device.
2806	*
2807	* @returns VBox status code.
2808	* @param pDevIns The device instance.
2809	* @param pThis The shared AC'97 state.
2810	* @param pStream The AC'97 stream to update (shared).
2811	* @param pStreamCC The AC'97 stream to update (ring-3).
2812	* @param cbToProcessMax Maximum of data (in bytes) to process.
2813	*/
2814	static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
2815	PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax)
2816	{
2817	if (!cbToProcessMax)
2818	return VINF_SUCCESS;
2819
2820	#ifdef VBOX_STRICT
2821	const unsigned cbFrame = PDMAudioPropsBytesPerFrame(&pStreamCC->State.Cfg.Props);
2822	#endif
2823
2824	/* Make sure to only process an integer number of audio frames. */
2825	Assert(cbToProcessMax % cbFrame == 0);
2826
2827	ichac97R3StreamLock(pStreamCC);
2828
2829	PAC97BMREGS pRegs = &pStream->Regs;
2830
2831	if (pRegs->sr & AC97_SR_DCH) /* Controller halted? */
2832	{
2833	if (pRegs->cr & AC97_CR_RPBM) /* Bus master operation starts. */
2834	{
2835	switch (pStream->u8SD)
2836	{
2837	case AC97SOUNDSOURCE_PO_INDEX:
2838	/ichac97R3WriteBUP(pThis, cbToProcess);/
2839	break;
2840
2841	default:
2842	break;
2843	}
2844	}
2845
2846	ichac97R3StreamUnlock(pStreamCC);
2847	return VINF_SUCCESS;
2848	}
2849
2850	/* BCIS flag still set? Skip iteration. */
2851	if (pRegs->sr & AC97_SR_BCIS)
2852	{
2853	Log3Func(("[SD%RU8] BCIS set\n", pStream->u8SD));
2854
2855	ichac97R3StreamUnlock(pStreamCC);
2856	return VINF_SUCCESS;
2857	}
2858
2859	uint32_t cbLeft = RT_MIN((uint32_t)(pRegs->picb << 1), cbToProcessMax); /** @todo r=andy Assumes 16bit samples. */
2860	uint32_t cbProcessedTotal = 0;
2861
2862	PRTCIRCBUF pCircBuf = pStreamCC->State.pCircBuf;
2863	AssertPtr(pCircBuf);
2864
2865	int rc = VINF_SUCCESS;
2866
2867	Log3Func(("[SD%RU8] cbToProcessMax=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcessMax, cbLeft));
2868
2869	while (cbLeft)
2870	{
2871	if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
2872	{
2873	Log3Func(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
2874	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
2875	if (pRegs->civ == pRegs->lvi)
2876	{
2877	pRegs->sr \|= AC97_SR_DCH; /** @todo r=andy Also set CELV? */
2878	pThis->bup_flag = 0;
2879
2880	rc = VINF_EOF;
2881	break;
2882	}
2883
2884	pRegs->sr &= ~AC97_SR_CELV;
2885	pRegs->civ = pRegs->piv;
2886	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2887
2888	ichac97R3StreamFetchBDLE(pDevIns, pStream);
2889	continue;
2890	}
2891
2892	uint32_t cbChunk = cbLeft;
2893
2894	switch (pStream->u8SD)
2895	{
2896	case AC97SOUNDSOURCE_PO_INDEX: /* Output */
2897	{
2898	void *pvDst;
2899	size_t cbDst;
2900
2901	RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvDst, &cbDst);
2902
2903	if (cbDst)
2904	{
2905	int rc2 = PDMDevHlpPCIPhysRead(pDevIns, pRegs->bd.addr, (uint8_t *)pvDst, cbDst);
2906	AssertRC(rc2);
2907
2908	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2909	{ /* likely */ }
2910	else
2911	AudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvDst, cbDst, 0 /* fFlags */);
2912	}
2913
2914	RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
2915
2916	cbChunk = (uint32_t)cbDst; /* Update the current chunk size to what really has been written. */
2917	break;
2918	}
2919
2920	case AC97SOUNDSOURCE_PI_INDEX: /* Input */
2921	case AC97SOUNDSOURCE_MC_INDEX: /* Input */
2922	{
2923	void *pvSrc;
2924	size_t cbSrc;
2925
2926	RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvSrc, &cbSrc);
2927
2928	if (cbSrc)
2929	{
2930	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, pRegs->bd.addr, (uint8_t *)pvSrc, cbSrc);
2931	AssertRC(rc2);
2932
2933	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2934	{ /* likely */ }
2935	else
2936	AudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvSrc, cbSrc, 0 /* fFlags */);
2937	}
2938
2939	RTCircBufReleaseReadBlock(pCircBuf, cbSrc);
2940
2941	cbChunk = (uint32_t)cbSrc; /* Update the current chunk size to what really has been read. */
2942	break;
2943	}
2944
2945	default:
2946	AssertMsgFailed(("Stream #%RU8 not supported\n", pStream->u8SD));
2947	rc = VERR_NOT_SUPPORTED;
2948	break;
2949	}
2950
2951	if (RT_FAILURE(rc))
2952	break;
2953
2954	if (cbChunk)
2955	{
2956	cbProcessedTotal += cbChunk;
2957	Assert(cbProcessedTotal <= cbToProcessMax);
2958	Assert(cbLeft >= cbChunk);
2959	cbLeft -= cbChunk;
2960	Assert((cbChunk & 1) == 0); /* Else the following shift won't work */
2961
2962	pRegs->picb -= (cbChunk >> 1); /** @todo r=andy Assumes 16bit samples. */
2963	pRegs->bd.addr += cbChunk;
2964	}
2965
2966	LogFlowFunc(("[SD%RU8] cbChunk=%RU32, cbLeft=%RU32, cbTotal=%RU32, rc=%Rrc\n",
2967	pStream->u8SD, cbChunk, cbLeft, cbProcessedTotal, rc));
2968
2969	if (!pRegs->picb)
2970	{
2971	uint32_t new_sr = pRegs->sr & ~AC97_SR_CELV;
2972
2973	if (pRegs->bd.ctl_len & AC97_BD_IOC)
2974	{
2975	new_sr \|= AC97_SR_BCIS;
2976	}
2977
2978	if (pRegs->civ == pRegs->lvi)
2979	{
2980	/* Did we run out of data? */
2981	LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pRegs->civ, pRegs->lvi));
2982
2983	new_sr \|= AC97_SR_LVBCI \| AC97_SR_DCH \| AC97_SR_CELV;
2984	pThis->bup_flag = (pRegs->bd.ctl_len & AC97_BD_BUP) ? BUP_LAST : 0;
2985
2986	rc = VINF_EOF;
2987	}
2988	else
2989	{
2990	pRegs->civ = pRegs->piv;
2991	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2992	ichac97R3StreamFetchBDLE(pDevIns, pStream);
2993	}
2994
2995	ichac97StreamUpdateSR(pDevIns, pThis, pStream, new_sr);
2996	}
2997
2998	if (/* All data processed? */
2999	rc == VINF_EOF
3000	/* ... or an error occurred? */
3001	\|\| RT_FAILURE(rc))
3002	{
3003	break;
3004	}
3005	}
3006
3007	ichac97R3StreamUnlock(pStreamCC);
3008
3009	LogFlowFuncLeaveRC(rc);
3010	return rc;
3011	}
3012
3013	#endif /* IN_RING3 */
3014
3015
3016	/**
3017	* @callback_method_impl{FNIOMIOPORTNEWIN}
3018	*/
3019	static DECLCALLBACK(VBOXSTRICTRC)
3020	ichac97IoPortNabmRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3021	{
3022	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3023	RT_NOREF(pvUser);
3024
3025	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3026
3027	/* Get the index of the NABMBAR port. */
3028	if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
3029	&& offPort != AC97_GLOB_CNT)
3030	{
3031	PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
3032	PAC97BMREGS pRegs = &pStream->Regs;
3033
3034	switch (cb)
3035	{
3036	case 1:
3037	switch (offPort & AC97_NABM_OFF_MASK)
3038	{
3039	case AC97_NABM_OFF_CIV:
3040	/* Current Index Value Register */
3041	*pu32 = pRegs->civ;
3042	Log3Func(("CIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3043	break;
3044	case AC97_NABM_OFF_LVI:
3045	/* Last Valid Index Register */
3046	*pu32 = pRegs->lvi;
3047	Log3Func(("LVI[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3048	break;
3049	case AC97_NABM_OFF_PIV:
3050	/* Prefetched Index Value Register */
3051	*pu32 = pRegs->piv;
3052	Log3Func(("PIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3053	break;
3054	case AC97_NABM_OFF_CR:
3055	/* Control Register */
3056	*pu32 = pRegs->cr;
3057	Log3Func(("CR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3058	break;
3059	case AC97_NABM_OFF_SR:
3060	/* Status Register (lower part) */
3061	*pu32 = RT_LO_U8(pRegs->sr);
3062	Log3Func(("SRb[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3063	break;
3064	default:
3065	*pu32 = UINT32_MAX;
3066	LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
3067	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3068	break;
3069	}
3070	break;
3071
3072	case 2:
3073	switch (offPort & AC97_NABM_OFF_MASK)
3074	{
3075	case AC97_NABM_OFF_SR:
3076	/* Status Register */
3077	*pu32 = pRegs->sr;
3078	Log3Func(("SR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3079	break;
3080	case AC97_NABM_OFF_PICB:
3081	/* Position in Current Buffer */
3082	*pu32 = pRegs->picb;
3083	Log3Func(("PICB[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3084	break;
3085	default:
3086	*pu32 = UINT32_MAX;
3087	LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
3088	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3089	break;
3090	}
3091	break;
3092
3093	case 4:
3094	switch (offPort & AC97_NABM_OFF_MASK)
3095	{
3096	case AC97_NABM_OFF_BDBAR:
3097	/* Buffer Descriptor Base Address Register */
3098	*pu32 = pRegs->bdbar;
3099	Log3Func(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3100	break;
3101	case AC97_NABM_OFF_CIV:
3102	/* 32-bit access: Current Index Value Register +
3103	* Last Valid Index Register +
3104	* Status Register */
3105	pu32 = pRegs->civ \| (pRegs->lvi << 8) \| (pRegs->sr << 16); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
3106	Log3Func(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
3107	AC97_PORT2IDX(offPort), pRegs->civ, pRegs->lvi, pRegs->sr));
3108	break;
3109	case AC97_NABM_OFF_PICB:
3110	/* 32-bit access: Position in Current Buffer Register +
3111	* Prefetched Index Value Register +
3112	* Control Register */
3113	pu32 = pRegs->picb \| (pRegs->piv << 16) \| (pRegs->cr << 24); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
3114	Log3Func(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
3115	AC97_PORT2IDX(offPort), *pu32, pRegs->picb, pRegs->piv, pRegs->cr));
3116	break;
3117
3118	default:
3119	*pu32 = UINT32_MAX;
3120	LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
3121	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3122	break;
3123	}
3124	break;
3125
3126	default:
3127	DEVAC97_UNLOCK(pDevIns, pThis);
3128	AssertFailed();
3129	return VERR_IOM_IOPORT_UNUSED;
3130	}
3131	}
3132	else
3133	{
3134	switch (cb)
3135	{
3136	case 1:
3137	switch (offPort)
3138	{
3139	case AC97_CAS:
3140	/* Codec Access Semaphore Register */
3141	Log3Func(("CAS %d\n", pThis->cas));
3142	*pu32 = pThis->cas;
3143	pThis->cas = 1;
3144	break;
3145	default:
3146	*pu32 = UINT32_MAX;
3147	LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
3148	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3149	break;
3150	}
3151	break;
3152
3153	case 2:
3154	*pu32 = UINT32_MAX;
3155	LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
3156	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3157	break;
3158
3159	case 4:
3160	switch (offPort)
3161	{
3162	case AC97_GLOB_CNT:
3163	/* Global Control */
3164	*pu32 = pThis->glob_cnt;
3165	Log3Func(("glob_cnt -> %#x\n", *pu32));
3166	break;
3167	case AC97_GLOB_STA:
3168	/* Global Status */
3169	*pu32 = pThis->glob_sta \| AC97_GS_S0CR;
3170	Log3Func(("glob_sta -> %#x\n", *pu32));
3171	break;
3172	default:
3173	*pu32 = UINT32_MAX;
3174	LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
3175	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3176	break;
3177	}
3178	break;
3179
3180	default:
3181	DEVAC97_UNLOCK(pDevIns, pThis);
3182	AssertFailed();
3183	return VERR_IOM_IOPORT_UNUSED;
3184	}
3185	}
3186
3187	DEVAC97_UNLOCK(pDevIns, pThis);
3188	return VINF_SUCCESS;
3189	}
3190
3191	/**
3192	* @callback_method_impl{FNIOMIOPORTNEWOUT}
3193	*/
3194	static DECLCALLBACK(VBOXSTRICTRC)
3195	ichac97IoPortNabmWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3196	{
3197	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3198	#ifdef IN_RING3
3199	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3200	#endif
3201	RT_NOREF(pvUser);
3202
3203	VBOXSTRICTRC rc = VINF_SUCCESS;
3204	if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
3205	&& offPort != AC97_GLOB_CNT)
3206	{
3207	#ifdef IN_RING3
3208	PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[AC97_PORT2IDX(offPort)];
3209	#endif
3210	PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
3211	PAC97BMREGS pRegs = &pStream->Regs;
3212
3213	DEVAC97_LOCK_BOTH_RETURN(pDevIns, pThis, pStream, VINF_IOM_R3_IOPORT_WRITE);
3214	switch (cb)
3215	{
3216	case 1:
3217	switch (offPort & AC97_NABM_OFF_MASK)
3218	{
3219	/*
3220	* Last Valid Index.
3221	*/
3222	case AC97_NABM_OFF_LVI:
3223	if ( (pRegs->cr & AC97_CR_RPBM)
3224	&& (pRegs->sr & AC97_SR_DCH))
3225	{
3226	#ifdef IN_RING3
3227	pRegs->sr &= ~(AC97_SR_DCH \| AC97_SR_CELV);
3228	pRegs->civ = pRegs->piv;
3229	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3230	#else
3231	rc = VINF_IOM_R3_IOPORT_WRITE;
3232	#endif
3233	}
3234	pRegs->lvi = u32 % AC97_MAX_BDLE;
3235	Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32));
3236	break;
3237
3238	/*
3239	* Control Registers.
3240	*/
3241	case AC97_NABM_OFF_CR:
3242	#ifdef IN_RING3
3243	Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32, pRegs->cr));
3244	if (u32 & AC97_CR_RR) /* Busmaster reset. */
3245	{
3246	Log3Func(("[SD%RU8] Reset\n", pStream->u8SD));
3247
3248	/* Make sure that Run/Pause Bus Master bit (RPBM) is cleared (0). */
3249	Assert((pRegs->cr & AC97_CR_RPBM) == 0);
3250
3251	ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3252	ichac97R3StreamReset(pThis, pStream, pStreamCC);
3253
3254	ichac97StreamUpdateSR(pDevIns, pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */
3255	}
3256	else
3257	{
3258	pRegs->cr = u32 & AC97_CR_VALID_MASK;
3259
3260	if (!(pRegs->cr & AC97_CR_RPBM))
3261	{
3262	Log3Func(("[SD%RU8] Disable\n", pStream->u8SD));
3263
3264	ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3265
3266	pRegs->sr \|= AC97_SR_DCH;
3267	}
3268	else
3269	{
3270	Log3Func(("[SD%RU8] Enable\n", pStream->u8SD));
3271
3272	pRegs->civ = pRegs->piv;
3273	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3274
3275	pRegs->sr &= ~AC97_SR_DCH;
3276
3277	/* Fetch the initial BDLE descriptor. */
3278	ichac97R3StreamFetchBDLE(pDevIns, pStream);
3279	# ifdef LOG_ENABLED
3280	ichac97R3BDLEDumpAll(pDevIns, pStream->Regs.bdbar, pStream->Regs.lvi + 1);
3281	# endif
3282	ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, true /* fEnable */);
3283
3284	/* Arm the timer for this stream. */
3285	/** @todo r=bird: This function returns bool, not VBox status! */
3286	ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3287	}
3288	}
3289	#else /* !IN_RING3 */
3290	rc = VINF_IOM_R3_IOPORT_WRITE;
3291	#endif
3292	break;
3293
3294	/*
3295	* Status Registers.
3296	*/
3297	case AC97_NABM_OFF_SR:
3298	ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3299	break;
3300
3301	default:
3302	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3303	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3304	break;
3305	}
3306	break;
3307
3308	case 2:
3309	switch (offPort & AC97_NABM_OFF_MASK)
3310	{
3311	case AC97_NABM_OFF_SR:
3312	ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3313	break;
3314	default:
3315	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3316	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3317	break;
3318	}
3319	break;
3320
3321	case 4:
3322	switch (offPort & AC97_NABM_OFF_MASK)
3323	{
3324	case AC97_NABM_OFF_BDBAR:
3325	/* Buffer Descriptor list Base Address Register */
3326	pRegs->bdbar = u32 & ~3;
3327	Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(offPort), u32, pRegs->bdbar));
3328	break;
3329	default:
3330	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3331	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3332	break;
3333	}
3334	break;
3335
3336	default:
3337	AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3338	break;
3339	}
3340	DEVAC97_UNLOCK_BOTH(pDevIns, pThis, pStream);
3341	}
3342	else
3343	{
3344	switch (cb)
3345	{
3346	case 1:
3347	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3348	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3349	break;
3350
3351	case 2:
3352	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3353	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3354	break;
3355
3356	case 4:
3357	switch (offPort)
3358	{
3359	case AC97_GLOB_CNT:
3360	/* Global Control */
3361	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3362	if (u32 & AC97_GC_WR)
3363	ichac97WarmReset(pThis);
3364	if (u32 & AC97_GC_CR)
3365	ichac97ColdReset(pThis);
3366	if (!(u32 & (AC97_GC_WR \| AC97_GC_CR)))
3367	pThis->glob_cnt = u32 & AC97_GC_VALID_MASK;
3368	Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt));
3369	DEVAC97_UNLOCK(pDevIns, pThis);
3370	break;
3371	case AC97_GLOB_STA:
3372	/* Global Status */
3373	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3374	pThis->glob_sta &= ~(u32 & AC97_GS_WCLEAR_MASK);
3375	pThis->glob_sta \|= (u32 & ~(AC97_GS_WCLEAR_MASK \| AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK;
3376	Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta));
3377	DEVAC97_UNLOCK(pDevIns, pThis);
3378	break;
3379	default:
3380	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3381	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3382	break;
3383	}
3384	break;
3385
3386	default:
3387	AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3388	break;
3389	}
3390	}
3391
3392	return rc;
3393	}
3394
3395	/**
3396	* @callback_method_impl{FNIOMIOPORTNEWIN}
3397	*/
3398	static DECLCALLBACK(VBOXSTRICTRC)
3399	ichac97IoPortNamRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3400	{
3401	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3402	RT_NOREF(pvUser);
3403	Assert(offPort < 256);
3404
3405	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3406
3407	VBOXSTRICTRC rc = VINF_SUCCESS;
3408	switch (cb)
3409	{
3410	case 1:
3411	{
3412	LogRel2(("AC97: Warning: Unimplemented read (1 byte) offPort=%#x\n", offPort));
3413	pThis->cas = 0;
3414	*pu32 = UINT32_MAX;
3415	break;
3416	}
3417
3418	case 2:
3419	{
3420	pThis->cas = 0;
3421	*pu32 = ichac97MixerGet(pThis, offPort);
3422	break;
3423	}
3424
3425	case 4:
3426	{
3427	LogRel2(("AC97: Warning: Unimplemented read (4 bytes) offPort=%#x\n", offPort));
3428	pThis->cas = 0;
3429	*pu32 = UINT32_MAX;
3430	break;
3431	}
3432
3433	default:
3434	{
3435	AssertFailed();
3436	rc = VERR_IOM_IOPORT_UNUSED;
3437	}
3438	}
3439
3440	DEVAC97_UNLOCK(pDevIns, pThis);
3441	return rc;
3442	}
3443
3444	/**
3445	* @callback_method_impl{FNIOMIOPORTNEWOUT}
3446	*/
3447	static DECLCALLBACK(VBOXSTRICTRC)
3448	ichac97IoPortNamWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3449	{
3450	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3451	#ifdef IN_RING3
3452	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3453	#endif
3454	RT_NOREF(pvUser);
3455
3456	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3457
3458	VBOXSTRICTRC rc = VINF_SUCCESS;
3459	switch (cb)
3460	{
3461	case 1:
3462	{
3463	LogRel2(("AC97: Warning: Unimplemented NAMWrite (1 byte) offPort=%#x <- %#x\n", offPort, u32));
3464	pThis->cas = 0;
3465	break;
3466	}
3467
3468	case 2:
3469	{
3470	pThis->cas = 0;
3471	switch (offPort)
3472	{
3473	case AC97_Reset:
3474	#ifdef IN_RING3
3475	ichac97R3Reset(pDevIns);
3476	#else
3477	rc = VINF_IOM_R3_IOPORT_WRITE;
3478	#endif
3479	break;
3480	case AC97_Powerdown_Ctrl_Stat:
3481	u32 &= ~0xf;
3482	u32 \|= ichac97MixerGet(pThis, offPort) & 0xf;
3483	ichac97MixerSet(pThis, offPort, u32);
3484	break;
3485	case AC97_Master_Volume_Mute:
3486	if (pThis->enmCodecModel == AC97CODEC_AD1980)
3487	{
3488	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_LOSEL)
3489	break; /* Register controls surround (rear), do nothing. */
3490	}
3491	#ifdef IN_RING3
3492	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3493	#else
3494	rc = VINF_IOM_R3_IOPORT_WRITE;
3495	#endif
3496	break;
3497	case AC97_Headphone_Volume_Mute:
3498	if (pThis->enmCodecModel == AC97CODEC_AD1980)
3499	{
3500	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3501	{
3502	/* Register controls PCM (front) outputs. */
3503	#ifdef IN_RING3
3504	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3505	#else
3506	rc = VINF_IOM_R3_IOPORT_WRITE;
3507	#endif
3508	}
3509	}
3510	break;
3511	case AC97_PCM_Out_Volume_Mute:
3512	#ifdef IN_RING3
3513	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_FRONT, u32);
3514	#else
3515	rc = VINF_IOM_R3_IOPORT_WRITE;
3516	#endif
3517	break;
3518	case AC97_Line_In_Volume_Mute:
3519	#ifdef IN_RING3
3520	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3521	#else
3522	rc = VINF_IOM_R3_IOPORT_WRITE;
3523	#endif
3524	break;
3525	case AC97_Record_Select:
3526	#ifdef IN_RING3
3527	ichac97R3MixerRecordSelect(pThis, u32);
3528	#else
3529	rc = VINF_IOM_R3_IOPORT_WRITE;
3530	#endif
3531	break;
3532	case AC97_Record_Gain_Mute:
3533	#ifdef IN_RING3
3534	/* Newer Ubuntu guests rely on that when controlling gain and muting
3535	* the recording (capturing) levels. */
3536	ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3537	#else
3538	rc = VINF_IOM_R3_IOPORT_WRITE;
3539	#endif
3540	break;
3541	case AC97_Record_Gain_Mic_Mute:
3542	#ifdef IN_RING3
3543	/* Ditto; see note above. */
3544	ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_MIC_IN, u32);
3545	#else
3546	rc = VINF_IOM_R3_IOPORT_WRITE;
3547	#endif
3548	break;
3549	case AC97_Vendor_ID1:
3550	case AC97_Vendor_ID2:
3551	LogFunc(("Attempt to write vendor ID to %#x\n", u32));
3552	break;
3553	case AC97_Extended_Audio_ID:
3554	LogFunc(("Attempt to write extended audio ID to %#x\n", u32));
3555	break;
3556	case AC97_Extended_Audio_Ctrl_Stat:
3557	#ifdef IN_RING3
3558	/*
3559	* Handle VRA bits.
3560	*/
3561	if (!(u32 & AC97_EACS_VRA)) /* Check if VRA bit is not set. */
3562	{
3563	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 0xbb80); /* Set default (48000 Hz). */
3564	ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3565	&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3566
3567	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3568	ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3569	&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3570	}
3571	else
3572	LogRel2(("AC97: Variable rate audio (VRA) is not supported\n"));
3573
3574	/*
3575	* Handle VRM bits.
3576	*/
3577	if (!(u32 & AC97_EACS_VRM)) /* Check if VRM bit is not set. */
3578	{
3579	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3580	ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3581	&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3582	}
3583	else
3584	LogRel2(("AC97: Variable rate microphone audio (VRM) is not supported\n"));
3585
3586	LogRel2(("AC97: Setting extended audio control to %#x\n", u32));
3587	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32);
3588	#else /* !IN_RING3 */
3589	rc = VINF_IOM_R3_IOPORT_WRITE;
3590	#endif
3591	break;
3592	case AC97_PCM_Front_DAC_Rate: /* Output slots 3, 4, 6. */
3593	#ifdef IN_RING3
3594	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3595	{
3596	LogRel2(("AC97: Setting front DAC rate to 0x%x\n", u32));
3597	ichac97MixerSet(pThis, offPort, u32);
3598	ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3599	&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3600	}
3601	else
3602	LogRel2(("AC97: Setting front DAC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3603	#else
3604	rc = VINF_IOM_R3_IOPORT_WRITE;
3605	#endif
3606	break;
3607	case AC97_MIC_ADC_Rate: /* Input slot 6. */
3608	#ifdef IN_RING3
3609	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRM)
3610	{
3611	LogRel2(("AC97: Setting microphone ADC rate to 0x%x\n", u32));
3612	ichac97MixerSet(pThis, offPort, u32);
3613	ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3614	&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3615	}
3616	else
3617	LogRel2(("AC97: Setting microphone ADC rate (0x%x) when VRM is not set is forbidden, ignoring\n", u32));
3618	#else
3619	rc = VINF_IOM_R3_IOPORT_WRITE;
3620	#endif
3621	break;
3622	case AC97_PCM_LR_ADC_Rate: /* Input slots 3, 4. */
3623	#ifdef IN_RING3
3624	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3625	{
3626	LogRel2(("AC97: Setting line-in ADC rate to 0x%x\n", u32));
3627	ichac97MixerSet(pThis, offPort, u32);
3628	ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3629	&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3630	}
3631	else
3632	LogRel2(("AC97: Setting line-in ADC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3633	#else
3634	rc = VINF_IOM_R3_IOPORT_WRITE;
3635	#endif
3636	break;
3637	default:
3638	LogRel2(("AC97: Warning: Unimplemented NAMWrite (2 bytes) offPort=%#x <- %#x\n", offPort, u32));
3639	ichac97MixerSet(pThis, offPort, u32);
3640	break;
3641	}
3642	break;
3643	}
3644
3645	case 4:
3646	{
3647	LogRel2(("AC97: Warning: Unimplemented 4 byte NAMWrite: offPort=%#x <- %#x\n", offPort, u32));
3648	pThis->cas = 0;
3649	break;
3650	}
3651
3652	default:
3653	AssertMsgFailed(("Unhandled NAMWrite offPort=%#x, cb=%u u32=%#x\n", offPort, cb, u32));
3654	break;
3655	}
3656
3657	DEVAC97_UNLOCK(pDevIns, pThis);
3658	return rc;
3659	}
3660
3661	#ifdef IN_RING3
3662
3663	/**
3664	* Saves (serializes) an AC'97 stream using SSM.
3665	*
3666	* @param pDevIns Device instance.
3667	* @param pSSM Saved state manager (SSM) handle to use.
3668	* @param pStream AC'97 stream to save.
3669	*/
3670	static void ichac97R3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3671	{
3672	PAC97BMREGS pRegs = &pStream->Regs;
3673	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3674
3675	pHlp->pfnSSMPutU32(pSSM, pRegs->bdbar);
3676	pHlp->pfnSSMPutU8( pSSM, pRegs->civ);
3677	pHlp->pfnSSMPutU8( pSSM, pRegs->lvi);
3678	pHlp->pfnSSMPutU16(pSSM, pRegs->sr);
3679	pHlp->pfnSSMPutU16(pSSM, pRegs->picb);
3680	pHlp->pfnSSMPutU8( pSSM, pRegs->piv);
3681	pHlp->pfnSSMPutU8( pSSM, pRegs->cr);
3682	pHlp->pfnSSMPutS32(pSSM, pRegs->bd_valid);
3683	pHlp->pfnSSMPutU32(pSSM, pRegs->bd.addr);
3684	pHlp->pfnSSMPutU32(pSSM, pRegs->bd.ctl_len);
3685	}
3686
3687	/**
3688	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3689	*/
3690	static DECLCALLBACK(int) ichac97R3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3691	{
3692	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3693	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3694	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3695	LogFlowFuncEnter();
3696
3697	pHlp->pfnSSMPutU32(pSSM, pThis->glob_cnt);
3698	pHlp->pfnSSMPutU32(pSSM, pThis->glob_sta);
3699	pHlp->pfnSSMPutU32(pSSM, pThis->cas);
3700
3701	/*
3702	* The order that the streams are saved here is fixed, so don't change.
3703	*/
3704	/** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
3705	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3706	ichac97R3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3707
3708	pHlp->pfnSSMPutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3709
3710	/* The stream order is against fixed and set in stone. */
3711	uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3712	afActiveStrms[AC97SOUNDSOURCE_PI_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX]);
3713	afActiveStrms[AC97SOUNDSOURCE_PO_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX]);
3714	afActiveStrms[AC97SOUNDSOURCE_MC_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX]);
3715	AssertCompile(RT_ELEMENTS(afActiveStrms) == 3);
3716	pHlp->pfnSSMPutMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3717
3718	LogFlowFuncLeaveRC(VINF_SUCCESS);
3719	return VINF_SUCCESS;
3720	}
3721
3722	/**
3723	* Loads an AC'97 stream from SSM.
3724	*
3725	* @returns VBox status code.
3726	* @param pDevIns The device instance.
3727	* @param pSSM Saved state manager (SSM) handle to use.
3728	* @param pStream AC'97 stream to load.
3729	*/
3730	static int ichac97R3LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3731	{
3732	PAC97BMREGS pRegs = &pStream->Regs;
3733	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3734
3735	pHlp->pfnSSMGetU32(pSSM, &pRegs->bdbar);
3736	pHlp->pfnSSMGetU8( pSSM, &pRegs->civ);
3737	pHlp->pfnSSMGetU8( pSSM, &pRegs->lvi);
3738	pHlp->pfnSSMGetU16(pSSM, &pRegs->sr);
3739	pHlp->pfnSSMGetU16(pSSM, &pRegs->picb);
3740	pHlp->pfnSSMGetU8( pSSM, &pRegs->piv);
3741	pHlp->pfnSSMGetU8( pSSM, &pRegs->cr);
3742	pHlp->pfnSSMGetS32(pSSM, &pRegs->bd_valid);
3743	pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.addr);
3744	return pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.ctl_len);
3745	}
3746
3747	/**
3748	* @callback_method_impl{FNSSMDEVLOADEXEC}
3749	*/
3750	static DECLCALLBACK(int) ichac97R3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3751	{
3752	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3753	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3754	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3755
3756	LogRel2(("ichac97LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3757
3758	AssertMsgReturn (uVersion == AC97_SAVED_STATE_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3759	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3760
3761	pHlp->pfnSSMGetU32(pSSM, &pThis->glob_cnt);
3762	pHlp->pfnSSMGetU32(pSSM, &pThis->glob_sta);
3763	pHlp->pfnSSMGetU32(pSSM, &pThis->cas);
3764
3765	/*
3766	* The order the streams are loaded here is critical (defined by
3767	* AC97SOUNDSOURCE_XX_INDEX), so don't touch!
3768	*/
3769	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3770	{
3771	int rc2 = ichac97R3LoadStream(pDevIns, pSSM, &pThis->aStreams[i]);
3772	AssertRCReturn(rc2, rc2);
3773	}
3774
3775	pHlp->pfnSSMGetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3776
3777	ichac97R3MixerRecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
3778	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3779	ichac97MixerGet(pThis, AC97_Master_Volume_Mute));
3780	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT,
3781	ichac97MixerGet(pThis, AC97_PCM_Out_Volume_Mute));
3782	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3783	ichac97MixerGet(pThis, AC97_Line_In_Volume_Mute));
3784	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3785	ichac97MixerGet(pThis, AC97_Mic_Volume_Mute));
3786	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3787	ichac97MixerGet(pThis, AC97_Record_Gain_Mic_Mute));
3788	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3789	ichac97MixerGet(pThis, AC97_Record_Gain_Mute));
3790	if (pThis->enmCodecModel == AC97CODEC_AD1980)
3791	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3792	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3793	ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
3794
3795	/*
3796	* Again the stream order is set is stone.
3797	*/
3798	uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3799	int rc2 = pHlp->pfnSSMGetMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3800	AssertRCReturn(rc2, rc2);
3801
3802	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3803	{
3804	const bool fEnable = RT_BOOL(afActiveStrms[i]);
3805	const PAC97STREAM pStream = &pThis->aStreams[i];
3806	const PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[i];
3807
3808	rc2 = ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, fEnable);
3809	AssertRC(rc2);
3810	if ( fEnable
3811	&& RT_SUCCESS(rc2))
3812	{
3813	/* Re-arm the timer for this stream. */
3814	/** @todo r=aeichner This causes a VM hang upon saved state resume when NetBSD is used as a guest
3815	* Stopping the timer if cTransferTicks is 0 is a workaround but needs further investigation,
3816	* see @bugref{9759} for more information. */
3817	if (pStreamCC->State.cTransferTicks)
3818	ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3819	else
3820	PDMDevHlpTimerStop(pDevIns, pStream->hTimer);
3821	}
3822
3823	/* Keep going. */
3824	}
3825
3826	pThis->bup_flag = 0;
3827	pThis->last_samp = 0;
3828
3829	return VINF_SUCCESS;
3830	}
3831
3832
3833	/**
3834	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3835	*/
3836	static DECLCALLBACK(void ) ichac97R3QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
3837	{
3838	PAC97STATER3 pThisCC = RT_FROM_MEMBER(pInterface, AC97STATER3, IBase);
3839	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
3840	return NULL;
3841	}
3842
3843
3844	/**
3845	* Powers off the device.
3846	*
3847	* @param pDevIns Device instance to power off.
3848	*/
3849	static DECLCALLBACK(void) ichac97R3PowerOff(PPDMDEVINS pDevIns)
3850	{
3851	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3852	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3853
3854	LogRel2(("AC97: Powering off ...\n"));
3855
3856	/* Note: Involves mixer stream / sink destruction, so also do this here
3857	* instead of in ichac97R3Destruct(). */
3858	ichac97R3StreamsDestroy(pDevIns, pThis, pThisCC);
3859
3860	/*
3861	* Note: Destroy the mixer while powering off and not in ichac97R3Destruct,
3862	* giving the mixer the chance to release any references held to
3863	* PDM audio streams it maintains.
3864	*/
3865	if (pThisCC->pMixer)
3866	{
3867	AudioMixerDestroy(pThisCC->pMixer, pDevIns);
3868	pThisCC->pMixer = NULL;
3869	}
3870	}
3871
3872
3873	/**
3874	* @interface_method_impl{PDMDEVREG,pfnReset}
3875	*
3876	* @remarks The original sources didn't install a reset handler, but it seems to
3877	* make sense to me so we'll do it.
3878	*/
3879	static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns)
3880	{
3881	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3882	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3883
3884	LogRel(("AC97: Reset\n"));
3885
3886	/*
3887	* Reset the mixer too. The Windows XP driver seems to rely on
3888	* this. At least it wants to read the vendor id before it resets
3889	* the codec manually.
3890	*/
3891	ichac97R3MixerReset(pThis, pThisCC);
3892
3893	/*
3894	* Reset all streams.
3895	*/
3896	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3897	{
3898	ichac97R3StreamEnable(pDevIns, pThis, pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], false /* fEnable */);
3899	ichac97R3StreamReset(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
3900	}
3901
3902	/*
3903	* Reset mixer sinks.
3904	*
3905	* Do the reset here instead of in ichac97R3StreamReset();
3906	* the mixer sink(s) might still have data to be processed when an audio stream gets reset.
3907	*/
3908	AudioMixerSinkReset(pThisCC->pSinkLineIn);
3909	AudioMixerSinkReset(pThisCC->pSinkMicIn);
3910	AudioMixerSinkReset(pThisCC->pSinkOut);
3911	}
3912
3913
3914	/**
3915	* Worker for ichac97R3Construct() and ichac97R3Attach().
3916	*
3917	* @returns VBox status code.
3918	* @param pDevIns The device instance.
3919	* @param pThisCC The ring-3 AC'97 device state.
3920	* @param iLun The logical unit which is being attached.
3921	* @param ppDrv Attached driver instance on success. Optional.
3922	*/
3923	static int ichac97R3AttachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned iLun, PAC97DRIVER *ppDrv)
3924	{
3925	/*
3926	* Attach driver.
3927	*/
3928	char *pszDesc = RTStrAPrintf2("Audio driver port (AC'97) for LUN #%u", iLun);
3929	AssertLogRelReturn(pszDesc, VERR_NO_STR_MEMORY);
3930
3931	PPDMIBASE pDrvBase;
3932	int rc = PDMDevHlpDriverAttach(pDevIns, iLun, &pThisCC->IBase, &pDrvBase, pszDesc);
3933	if (RT_SUCCESS(rc))
3934	{
3935	PAC97DRIVER pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
3936	if (pDrv)
3937	{
3938	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
3939	AssertPtr(pDrv->pConnector);
3940	if (pDrv->pConnector)
3941	{
3942	pDrv->pDrvBase = pDrvBase;
3943	pDrv->uLUN = iLun;
3944	pDrv->pszDesc = pszDesc;
3945
3946	/*
3947	* For now we always set the driver at LUN 0 as our primary
3948	* host backend. This might change in the future.
3949	*/
3950	if (iLun == 0)
3951	pDrv->fFlags \|= PDMAUDIODRVFLAGS_PRIMARY;
3952
3953	LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", iLun, pDrv->pConnector, pDrv->fFlags));
3954
3955	/* Attach to driver list if not attached yet. */
3956	if (!pDrv->fAttached)
3957	{
3958	RTListAppend(&pThisCC->lstDrv, &pDrv->Node);
3959	pDrv->fAttached = true;
3960	}
3961
3962	if (ppDrv)
3963	*ppDrv = pDrv;
3964	LogFunc(("LUN#%u: VINF_SUCCESS\n", iLun));
3965	return VINF_SUCCESS;
3966	}
3967	RTMemFree(pDrv);
3968	rc = VERR_PDM_MISSING_INTERFACE_BELOW;
3969	}
3970	else
3971	rc = VERR_NO_MEMORY;
3972	}
3973	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3974	LogFunc(("No attached driver for LUN #%u\n", iLun));
3975	else
3976	LogFunc(("Attached driver for LUN #%u failed: %Rrc\n", iLun, rc));
3977
3978	RTStrFree(pszDesc);
3979	LogFunc(("LUN#%u: rc=%Rrc\n", iLun, rc));
3980	return rc;
3981	}
3982
3983	/**
3984	* @interface_method_impl{PDMDEVREGR3,pfnAttach}
3985	*/
3986	static DECLCALLBACK(int) ichac97R3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3987	{
3988	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3989	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3990	RT_NOREF(fFlags);
3991	LogFunc(("iLUN=%u, fFlags=%#x\n", iLUN, fFlags));
3992
3993	DEVAC97_LOCK(pDevIns, pThis);
3994
3995	PAC97DRIVER pDrv;
3996	int rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLUN, &pDrv);
3997	if (RT_SUCCESS(rc))
3998	{
3999	int rc2 = ichac97R3MixerAddDrv(pDevIns, pThisCC, pDrv);
4000	if (RT_FAILURE(rc2))
4001	LogFunc(("ichac97R3MixerAddDrv failed with %Rrc (ignored)\n", rc2));
4002	}
4003
4004	DEVAC97_UNLOCK(pDevIns, pThis);
4005
4006	return rc;
4007	}
4008
4009	/**
4010	* Worker for ichac97R3Detach that does all but freeing the pDrv structure.
4011	*
4012	* This is called to let the device detach from a driver for a specified LUN
4013	* at runtime.
4014	*
4015	* @param pDevIns The device instance.
4016	* @param pThisCC The ring-3 AC'97 device state.
4017	* @param pDrv Driver to detach from device.
4018	*/
4019	static void ichac97R3DetachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
4020	{
4021	/* First, remove the driver from our list and destory it's associated streams.
4022	* This also will un-set the driver as a recording source (if associated). */
4023	ichac97R3MixerRemoveDrv(pDevIns, pThisCC, pDrv);
4024
4025	/* Next, search backwards for a capable (attached) driver which now will be the
4026	* new recording source. */
4027	PDMAUDIODSTSRCUNION dstSrc;
4028	PAC97DRIVER pDrvCur;
4029	RTListForEachReverse(&pThisCC->lstDrv, pDrvCur, AC97DRIVER, Node)
4030	{
4031	if (!pDrvCur->pConnector)
4032	continue;
4033
4034	PDMAUDIOBACKENDCFG Cfg;
4035	int rc2 = pDrvCur->pConnector->pfnGetConfig(pDrvCur->pConnector, &Cfg);
4036	if (RT_FAILURE(rc2))
4037	continue;
4038
4039	dstSrc.enmSrc = PDMAUDIORECSRC_MIC;
4040	PAC97DRIVERSTREAM pDrvStrm = ichac97R3MixerGetDrvStream(pDrvCur, PDMAUDIODIR_IN, dstSrc);
4041	if ( pDrvStrm
4042	&& pDrvStrm->pMixStrm)
4043	{
4044	rc2 = AudioMixerSinkSetRecordingSource(pThisCC->pSinkMicIn, pDrvStrm->pMixStrm);
4045	if (RT_SUCCESS(rc2))
4046	LogRel2(("AC97: Set new recording source for 'Mic In' to '%s'\n", Cfg.szName));
4047	}
4048
4049	dstSrc.enmSrc = PDMAUDIORECSRC_LINE;
4050	pDrvStrm = ichac97R3MixerGetDrvStream(pDrvCur, PDMAUDIODIR_IN, dstSrc);
4051	if ( pDrvStrm
4052	&& pDrvStrm->pMixStrm)
4053	{
4054	rc2 = AudioMixerSinkSetRecordingSource(pThisCC->pSinkLineIn, pDrvStrm->pMixStrm);
4055	if (RT_SUCCESS(rc2))
4056	LogRel2(("AC97: Set new recording source for 'Line In' to '%s'\n", Cfg.szName));
4057	}
4058	}
4059
4060	LogFunc(("Detached LUN#%u\n", pDrv->uLUN));
4061	}
4062
4063	/**
4064	* @interface_method_impl{PDMDEVREG,pfnDetach}
4065	*/
4066	static DECLCALLBACK(void) ichac97R3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4067	{
4068	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4069	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4070	RT_NOREF(fFlags);
4071
4072	LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
4073
4074	DEVAC97_LOCK(pDevIns, pThis);
4075
4076	PAC97DRIVER pDrv;
4077	RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
4078	{
4079	if (pDrv->uLUN == iLUN)
4080	{
4081	ichac97R3DetachInternal(pDevIns, pThisCC, pDrv);
4082	RTStrFree(pDrv->pszDesc);
4083	RTMemFree(pDrv);
4084	DEVAC97_UNLOCK(pDevIns, pThis);
4085	return;
4086	}
4087	}
4088
4089	DEVAC97_UNLOCK(pDevIns, pThis);
4090	LogFunc(("LUN#%u was not found\n", iLUN));
4091	}
4092
4093
4094	/**
4095	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4096	*/
4097	static DECLCALLBACK(int) ichac97R3Destruct(PPDMDEVINS pDevIns)
4098	{
4099	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4100	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4101
4102	LogFlowFuncEnter();
4103
4104	PAC97DRIVER pDrv, pDrvNext;
4105	RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
4106	{
4107	RTListNodeRemove(&pDrv->Node);
4108	RTMemFree(pDrv->pszDesc);
4109	RTMemFree(pDrv);
4110	}
4111
4112	/* Sanity. */
4113	Assert(RTListIsEmpty(&pThisCC->lstDrv));
4114
4115	return VINF_SUCCESS;
4116	}
4117
4118	/**
4119	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4120	*/
4121	static DECLCALLBACK(int) ichac97R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4122	{
4123	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4124	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4125	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4126	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4127	Assert(iInstance == 0); RT_NOREF(iInstance);
4128
4129	/*
4130	* Initialize data so we can run the destructor without scewing up.
4131	*/
4132	pThisCC->pDevIns = pDevIns;
4133	pThisCC->IBase.pfnQueryInterface = ichac97R3QueryInterface;
4134	RTListInit(&pThisCC->lstDrv);
4135
4136	/*
4137	* Validate and read configuration.
4138	*/
4139	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Codec\|TimerHz\|DebugEnabled\|DebugPathOut", "");
4140
4141	char szCodec[20];
4142	int rc = pHlp->pfnCFGMQueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
4143	if (RT_FAILURE(rc))
4144	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4145	N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
4146
4147	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, AC97_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4148	if (RT_FAILURE(rc))
4149	return PDMDEV_SET_ERROR(pDevIns, rc,
4150	N_("AC'97 configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4151
4152	if (pThis->uTimerHz != AC97_TIMER_HZ_DEFAULT)
4153	LogRel(("AC97: Using custom device timer rate (%RU16Hz)\n", pThis->uTimerHz));
4154
4155	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "DebugEnabled", &pThisCC->Dbg.fEnabled, false);
4156	if (RT_FAILURE(rc))
4157	return PDMDEV_SET_ERROR(pDevIns, rc,
4158	N_("AC97 configuration error: failed to read debugging enabled flag as boolean"));
4159
4160	rc = pHlp->pfnCFGMQueryStringAllocDef(pCfg, "DebugPathOut", &pThisCC->Dbg.pszOutPath, NULL);
4161	if (RT_FAILURE(rc))
4162	return PDMDEV_SET_ERROR(pDevIns, rc,
4163	N_("AC97 configuration error: failed to read debugging output path flag as string"));
4164
4165	if (pThisCC->Dbg.fEnabled)
4166	LogRel2(("AC97: Debug output will be saved to '%s'\n", pThisCC->Dbg.pszOutPath));
4167
4168	/*
4169	* The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
4170	* in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
4171	* 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
4172	*/
4173	if (!strcmp(szCodec, "STAC9700"))
4174	pThis->enmCodecModel = AC97CODEC_STAC9700;
4175	else if (!strcmp(szCodec, "AD1980"))
4176	pThis->enmCodecModel = AC97CODEC_AD1980;
4177	else if (!strcmp(szCodec, "AD1981B"))
4178	pThis->enmCodecModel = AC97CODEC_AD1981B;
4179	else
4180	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
4181	N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"), szCodec);
4182
4183	LogRel(("AC97: Using codec '%s'\n", szCodec));
4184
4185	/*
4186	* Use an own critical section for the device instead of the default
4187	* one provided by PDM. This allows fine-grained locking in combination
4188	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4189	*/
4190	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "AC'97");
4191	AssertRCReturn(rc, rc);
4192
4193	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4194	AssertRCReturn(rc, rc);
4195
4196	/*
4197	* Initialize data (most of it anyway).
4198	*/
4199	/* PCI Device */
4200	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4201	PCIDevSetVendorId(pPciDev, 0x8086); /* 00 ro - intel. */ Assert(pPciDev->abConfig[0x00] == 0x86); Assert(pPciDev->abConfig[0x01] == 0x80);
4202	PCIDevSetDeviceId(pPciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pPciDev->abConfig[0x02] == 0x15); Assert(pPciDev->abConfig[0x03] == 0x24);
4203	PCIDevSetCommand(pPciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pPciDev->abConfig[0x04] == 0x00); Assert(pPciDev->abConfig[0x05] == 0x00);
4204	PCIDevSetStatus(pPciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM \| VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pPciDev->abConfig[0x06] == 0x80); Assert(pPciDev->abConfig[0x07] == 0x02);
4205	PCIDevSetRevisionId(pPciDev, 0x01); /* 08 ro - rid. */ Assert(pPciDev->abConfig[0x08] == 0x01);
4206	PCIDevSetClassProg(pPciDev, 0x00); /* 09 ro - pi. */ Assert(pPciDev->abConfig[0x09] == 0x00);
4207	PCIDevSetClassSub(pPciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pPciDev->abConfig[0x0a] == 0x01);
4208	PCIDevSetClassBase(pPciDev, 0x04); /* 0b ro - bcc; 04 == multimedia.*/Assert(pPciDev->abConfig[0x0b] == 0x04);
4209	PCIDevSetHeaderType(pPciDev, 0x00); /* 0e ro - headtyp. */ Assert(pPciDev->abConfig[0x0e] == 0x00);
4210	PCIDevSetBaseAddress(pPciDev, 0, /* 10 rw - nambar - native audio mixer base. */
4211	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x10] == 0x01); Assert(pPciDev->abConfig[0x11] == 0x00); Assert(pPciDev->abConfig[0x12] == 0x00); Assert(pPciDev->abConfig[0x13] == 0x00);
4212	PCIDevSetBaseAddress(pPciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
4213	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x14] == 0x01); Assert(pPciDev->abConfig[0x15] == 0x00); Assert(pPciDev->abConfig[0x16] == 0x00); Assert(pPciDev->abConfig[0x17] == 0x00);
4214	PCIDevSetInterruptLine(pPciDev, 0x00); /* 3c rw. */ Assert(pPciDev->abConfig[0x3c] == 0x00);
4215	PCIDevSetInterruptPin(pPciDev, 0x01); /* 3d ro - INTA#. */ Assert(pPciDev->abConfig[0x3d] == 0x01);
4216
4217	if (pThis->enmCodecModel == AC97CODEC_AD1980)
4218	{
4219	PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4220	PCIDevSetSubSystemId(pPciDev, 0x0177); /* 2e ro. */
4221	}
4222	else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
4223	{
4224	PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4225	PCIDevSetSubSystemId(pPciDev, 0x01ad); /* 2e ro. */
4226	}
4227	else
4228	{
4229	PCIDevSetSubSystemVendorId(pPciDev, 0x8086); /* 2c ro - Intel.) */
4230	PCIDevSetSubSystemId(pPciDev, 0x0000); /* 2e ro. */
4231	}
4232
4233	/*
4234	* Register the PCI device and associated I/O regions.
4235	*/
4236	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4237	if (RT_FAILURE(rc))
4238	return rc;
4239
4240	rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 0 /iPciRegion/, 256 /cPorts/,
4241	ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /pvUser/,
4242	"ICHAC97 NAM", NULL /paExtDescs/, &pThis->hIoPortsNam);
4243	AssertRCReturn(rc, rc);
4244
4245	rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 1 /iPciRegion/, 64 /cPorts/,
4246	ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /pvUser/,
4247	"ICHAC97 NABM", g_aNabmPorts, &pThis->hIoPortsNabm);
4248	AssertRCReturn(rc, rc);
4249
4250	/*
4251	* Saved state.
4252	*/
4253	rc = PDMDevHlpSSMRegister(pDevIns, AC97_SAVED_STATE_VERSION, sizeof(*pThis), ichac97R3SaveExec, ichac97R3LoadExec);
4254	if (RT_FAILURE(rc))
4255	return rc;
4256
4257	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
4258	LogRel(("AC97: Asynchronous I/O enabled\n"));
4259	# endif
4260
4261	/*
4262	* Attach drivers. We ASSUME they are configured consecutively without any
4263	* gaps, so we stop when we hit the first LUN w/o a driver configured.
4264	*/
4265	for (unsigned iLun = 0; ; iLun++)
4266	{
4267	AssertBreak(iLun < UINT8_MAX);
4268	LogFunc(("Trying to attach driver for LUN#%u ...\n", iLun));
4269	rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, NULL /* ppDrv */);
4270	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4271	{
4272	LogFunc(("cLUNs=%u\n", iLun));
4273	break;
4274	}
4275	AssertLogRelMsgReturn(RT_SUCCESS(rc), ("LUN#%u: rc=%Rrc\n", iLun, rc), rc);
4276	}
4277
4278	uint32_t fMixer = AUDMIXER_FLAGS_NONE;
4279	if (pThisCC->Dbg.fEnabled)
4280	fMixer \|= AUDMIXER_FLAGS_DEBUG;
4281
4282	rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThisCC->pMixer);
4283	AssertRCReturn(rc, rc);
4284
4285	rc = AudioMixerCreateSink(pThisCC->pMixer, "Line In",
4286	AUDMIXSINKDIR_INPUT, pDevIns, &pThisCC->pSinkLineIn);
4287	AssertRCReturn(rc, rc);
4288	rc = AudioMixerCreateSink(pThisCC->pMixer, "Microphone In",
4289	AUDMIXSINKDIR_INPUT, pDevIns, &pThisCC->pSinkMicIn);
4290	AssertRCReturn(rc, rc);
4291	rc = AudioMixerCreateSink(pThisCC->pMixer, "PCM Output",
4292	AUDMIXSINKDIR_OUTPUT, pDevIns, &pThisCC->pSinkOut);
4293	AssertRCReturn(rc, rc);
4294
4295	/*
4296	* Create all hardware streams.
4297	*/
4298	AssertCompile(RT_ELEMENTS(pThis->aStreams) == AC97_MAX_STREAMS);
4299	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4300	{
4301	rc = ichac97R3StreamCreate(pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], i /* SD# */);
4302	AssertRCReturn(rc, rc);
4303	}
4304
4305	/*
4306	* Create the emulation timers (one per stream).
4307	*
4308	* We must the critical section for the timers as the device has a
4309	* noop section associated with it.
4310	*
4311	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's AC'97 driver
4312	* relies on exact (virtual) DMA timing and uses DMA Position Buffers
4313	* instead of the LPIB registers.
4314	*/
4315	/** @todo r=bird: The need to use virtual sync is perhaps because TM
4316	* doesn't schedule regular TMCLOCK_VIRTUAL timers as accurately as it
4317	* should (VT-x preemption timer, etc). Hope to address that before
4318	* long. @bugref{9943}. */
4319	static const char * const s_apszNames[] = { "AC97 PI", "AC97 PO", "AC97 MC" };
4320	AssertCompile(RT_ELEMENTS(s_apszNames) == AC97_MAX_STREAMS);
4321	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4322	{
4323	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, ichac97R3Timer, &pThis->aStreams[i],
4324	TMTIMER_FLAGS_NO_CRIT_SECT \| TMTIMER_FLAGS_RING0, s_apszNames[i], &pThis->aStreams[i].hTimer);
4325	AssertRCReturn(rc, rc);
4326
4327	rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->aStreams[i].hTimer, &pThis->CritSect);
4328	AssertRCReturn(rc, rc);
4329	}
4330
4331	ichac97R3Reset(pDevIns);
4332
4333	/*
4334	* Register statistics.
4335	*/
4336	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmReads, STAMTYPE_COUNTER, "UnimplementedNabmReads", STAMUNIT_OCCURENCES, "Unimplemented NABM register reads.");
4337	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmWrites, STAMTYPE_COUNTER, "UnimplementedNabmWrites", STAMUNIT_OCCURENCES, "Unimplemented NABM register writes.");
4338	# ifdef VBOX_WITH_STATISTICS
4339	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
4340	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
4341	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
4342	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
4343	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
4344	# endif
4345
4346	LogFlowFuncLeaveRC(VINF_SUCCESS);
4347	return VINF_SUCCESS;
4348	}
4349
4350	#else /* !IN_RING3 */
4351
4352	/**
4353	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4354	*/
4355	static DECLCALLBACK(int) ichac97RZConstruct(PPDMDEVINS pDevIns)
4356	{
4357	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4358	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4359
4360	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4361	AssertRCReturn(rc, rc);
4362
4363	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNam, ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /pvUser/);
4364	AssertRCReturn(rc, rc);
4365	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNabm, ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /pvUser/);
4366	AssertRCReturn(rc, rc);
4367
4368	return VINF_SUCCESS;
4369	}
4370
4371	#endif /* !IN_RING3 */
4372
4373	/**
4374	* The device registration structure.
4375	*/
4376	const PDMDEVREG g_DeviceICHAC97 =
4377	{
4378	/* .u32Version = */ PDM_DEVREG_VERSION,
4379	/* .uReserved0 = */ 0,
4380	/* .szName = */ "ichac97",
4381	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
4382	\| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION /* stream clearnup with working drivers */,
4383	/* .fClass = */ PDM_DEVREG_CLASS_AUDIO,
4384	/* .cMaxInstances = */ 1,
4385	/* .uSharedVersion = */ 42,
4386	/* .cbInstanceShared = */ sizeof(AC97STATE),
4387	/* .cbInstanceCC = */ CTX_EXPR(sizeof(AC97STATER3), 0, 0),
4388	/* .cbInstanceRC = */ 0,
4389	/* .cMaxPciDevices = */ 1,
4390	/* .cMaxMsixVectors = */ 0,
4391	/* .pszDescription = */ "ICH AC'97 Audio Controller",
4392	#if defined(IN_RING3)
4393	/* .pszRCMod = */ "VBoxDDRC.rc",
4394	/* .pszR0Mod = */ "VBoxDDR0.r0",
4395	/* .pfnConstruct = */ ichac97R3Construct,
4396	/* .pfnDestruct = */ ichac97R3Destruct,
4397	/* .pfnRelocate = */ NULL,
4398	/* .pfnMemSetup = */ NULL,
4399	/* .pfnPowerOn = */ NULL,
4400	/* .pfnReset = */ ichac97R3Reset,
4401	/* .pfnSuspend = */ NULL,
4402	/* .pfnResume = */ NULL,
4403	/* .pfnAttach = */ ichac97R3Attach,
4404	/* .pfnDetach = */ ichac97R3Detach,
4405	/* .pfnQueryInterface = */ NULL,
4406	/* .pfnInitComplete = */ NULL,
4407	/* .pfnPowerOff = */ ichac97R3PowerOff,
4408	/* .pfnSoftReset = */ NULL,
4409	/* .pfnReserved0 = */ NULL,
4410	/* .pfnReserved1 = */ NULL,
4411	/* .pfnReserved2 = */ NULL,
4412	/* .pfnReserved3 = */ NULL,
4413	/* .pfnReserved4 = */ NULL,
4414	/* .pfnReserved5 = */ NULL,
4415	/* .pfnReserved6 = */ NULL,
4416	/* .pfnReserved7 = */ NULL,
4417	#elif defined(IN_RING0)
4418	/* .pfnEarlyConstruct = */ NULL,
4419	/* .pfnConstruct = */ ichac97RZConstruct,
4420	/* .pfnDestruct = */ NULL,
4421	/* .pfnFinalDestruct = */ NULL,
4422	/* .pfnRequest = */ NULL,
4423	/* .pfnReserved0 = */ NULL,
4424	/* .pfnReserved1 = */ NULL,
4425	/* .pfnReserved2 = */ NULL,
4426	/* .pfnReserved3 = */ NULL,
4427	/* .pfnReserved4 = */ NULL,
4428	/* .pfnReserved5 = */ NULL,
4429	/* .pfnReserved6 = */ NULL,
4430	/* .pfnReserved7 = */ NULL,
4431	#elif defined(IN_RC)
4432	/* .pfnConstruct = */ ichac97RZConstruct,
4433	/* .pfnReserved0 = */ NULL,
4434	/* .pfnReserved1 = */ NULL,
4435	/* .pfnReserved2 = */ NULL,
4436	/* .pfnReserved3 = */ NULL,
4437	/* .pfnReserved4 = */ NULL,
4438	/* .pfnReserved5 = */ NULL,
4439	/* .pfnReserved6 = */ NULL,
4440	/* .pfnReserved7 = */ NULL,
4441	#else
4442	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4443	#endif
4444	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
4445	};
4446
4447	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4448

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source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 88908

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