DevIchAc97.cpp@ 88919

Last change on this file since 88919 was 88919, checked in by vboxsync, 4 years ago
DevHda,DevIchAc97: This detach code looks completely random. bugref:9890
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1	/* $Id: DevIchAc97.cpp 88919 2021-05-06 23:05:19Z vboxsync $ */
2	/** @file
3	* DevIchAc97 - VBox ICH AC97 Audio Controller.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_AC97
23	#include <VBox/log.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/vmm/pdmaudioifs.h>
26	#include <VBox/vmm/pdmaudioinline.h>
27
28	#include <iprt/assert.h>
29	#ifdef IN_RING3
30	# ifdef DEBUG
31	# include <iprt/file.h>
32	# endif
33	# include <iprt/mem.h>
34	# include <iprt/semaphore.h>
35	# include <iprt/string.h>
36	# include <iprt/uuid.h>
37	#endif
38
39	#include "VBoxDD.h"
40
41	#include "AudioMixBuffer.h"
42	#include "AudioMixer.h"
43	#include "AudioHlp.h"
44
45
46	/*********************************************************************************************************************************
47	* Defined Constants And Macros *
48	*********************************************************************************************************************************/
49
50	/** Current saved state version. */
51	#define AC97_SAVED_STATE_VERSION 1
52
53	/** Default timer frequency (in Hz). */
54	#define AC97_TIMER_HZ_DEFAULT 100
55
56	/** Maximum number of streams we support. */
57	#define AC97_MAX_STREAMS 3
58
59	/** Maximum FIFO size (in bytes). */
60	#define AC97_FIFO_MAX 256
61
62	#define AC97_SR_FIFOE RT_BIT(4) /*< rwc, FIFO error. /
63	#define AC97_SR_BCIS RT_BIT(3) /*< rwc, Buffer completion interrupt status. /
64	#define AC97_SR_LVBCI RT_BIT(2) /*< rwc, Last valid buffer completion interrupt. /
65	#define AC97_SR_CELV RT_BIT(1) /*< ro, Current equals last valid. /
66	#define AC97_SR_DCH RT_BIT(0) /*< ro, Controller halted. /
67	#define AC97_SR_VALID_MASK (RT_BIT(5) - 1)
68	#define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE \| AC97_SR_BCIS \| AC97_SR_LVBCI)
69	#define AC97_SR_RO_MASK (AC97_SR_DCH \| AC97_SR_CELV)
70	#define AC97_SR_INT_MASK (AC97_SR_FIFOE \| AC97_SR_BCIS \| AC97_SR_LVBCI)
71
72	#define AC97_CR_IOCE RT_BIT(4) /*< rw, Interrupt On Completion Enable. /
73	#define AC97_CR_FEIE RT_BIT(3) /*< rw FIFO Error Interrupt Enable. /
74	#define AC97_CR_LVBIE RT_BIT(2) /*< rw Last Valid Buffer Interrupt Enable. /
75	#define AC97_CR_RR RT_BIT(1) /*< rw Reset Registers. /
76	#define AC97_CR_RPBM RT_BIT(0) /*< rw Run/Pause Bus Master. /
77	#define AC97_CR_VALID_MASK (RT_BIT(5) - 1)
78	#define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE \| AC97_CR_FEIE \| AC97_CR_LVBIE)
79
80	#define AC97_GC_WR 4 /*< rw Warm reset. /
81	#define AC97_GC_CR 2 /*< rw Cold reset. /
82	#define AC97_GC_VALID_MASK (RT_BIT(6) - 1)
83
84	#define AC97_GS_MD3 RT_BIT(17) /*< rw /
85	#define AC97_GS_AD3 RT_BIT(16) /*< rw /
86	#define AC97_GS_RCS RT_BIT(15) /*< rwc /
87	#define AC97_GS_B3S12 RT_BIT(14) /*< ro /
88	#define AC97_GS_B2S12 RT_BIT(13) /*< ro /
89	#define AC97_GS_B1S12 RT_BIT(12) /*< ro /
90	#define AC97_GS_S1R1 RT_BIT(11) /*< rwc /
91	#define AC97_GS_S0R1 RT_BIT(10) /*< rwc /
92	#define AC97_GS_S1CR RT_BIT(9) /*< ro /
93	#define AC97_GS_S0CR RT_BIT(8) /*< ro /
94	#define AC97_GS_MINT RT_BIT(7) /*< ro /
95	#define AC97_GS_POINT RT_BIT(6) /*< ro /
96	#define AC97_GS_PIINT RT_BIT(5) /*< ro /
97	#define AC97_GS_RSRVD (RT_BIT(4) \| RT_BIT(3))
98	#define AC97_GS_MOINT RT_BIT(2) /*< ro /
99	#define AC97_GS_MIINT RT_BIT(1) /*< ro /
100	#define AC97_GS_GSCI RT_BIT(0) /*< rwc /
101	#define AC97_GS_RO_MASK ( AC97_GS_B3S12 \
102	\| AC97_GS_B2S12 \
103	\| AC97_GS_B1S12 \
104	\| AC97_GS_S1CR \
105	\| AC97_GS_S0CR \
106	\| AC97_GS_MINT \
107	\| AC97_GS_POINT \
108	\| AC97_GS_PIINT \
109	\| AC97_GS_RSRVD \
110	\| AC97_GS_MOINT \
111	\| AC97_GS_MIINT)
112	#define AC97_GS_VALID_MASK (RT_BIT(18) - 1)
113	#define AC97_GS_WCLEAR_MASK (AC97_GS_RCS \| AC97_GS_S1R1 \| AC97_GS_S0R1 \| AC97_GS_GSCI)
114
115	/** @name Buffer Descriptor (BD).
116	* @{ */
117	#define AC97_BD_IOC RT_BIT(31) /*< Interrupt on Completion. /
118	#define AC97_BD_BUP RT_BIT(30) /*< Buffer Underrun Policy. /
119
120	#define AC97_BD_LEN_MASK 0xFFFF /*< Mask for the BDL buffer length. /
121
122	#define AC97_MAX_BDLE 32 /*< Maximum number of BDLEs. /
123	/** @} */
124
125	/** @name Extended Audio ID Register (EAID).
126	* @{ */
127	#define AC97_EAID_VRA RT_BIT(0) /*< Variable Rate Audio. /
128	#define AC97_EAID_VRM RT_BIT(3) /*< Variable Rate Mic Audio. /
129	#define AC97_EAID_REV0 RT_BIT(10) /*< AC'97 revision compliance. /
130	#define AC97_EAID_REV1 RT_BIT(11) /*< AC'97 revision compliance. /
131	/** @} */
132
133	/** @name Extended Audio Control and Status Register (EACS).
134	* @{ */
135	#define AC97_EACS_VRA RT_BIT(0) /*< Variable Rate Audio (4.2.1.1). /
136	#define AC97_EACS_VRM RT_BIT(3) /*< Variable Rate Mic Audio (4.2.1.1). /
137	/** @} */
138
139	/** @name Baseline Audio Register Set (BARS).
140	* @{ */
141	#define AC97_BARS_VOL_MASK 0x1f /*< Volume mask for the Baseline Audio Register Set (5.7.2). /
142	#define AC97_BARS_GAIN_MASK 0x0f /*< Gain mask for the Baseline Audio Register Set. /
143	#define AC97_BARS_VOL_MUTE_SHIFT 15 /*< Mute bit shift for the Baseline Audio Register Set (5.7.2). /
144	/** @} */
145
146	/** AC'97 uses 1.5dB steps, we use 0.375dB steps: 1 AC'97 step equals 4 PDM steps. */
147	#define AC97_DB_FACTOR 4
148
149	/** @name Recording inputs?
150	* @{ */
151	#define AC97_REC_MIC UINT8_C(0)
152	#define AC97_REC_CD UINT8_C(1)
153	#define AC97_REC_VIDEO UINT8_C(2)
154	#define AC97_REC_AUX UINT8_C(3)
155	#define AC97_REC_LINE_IN UINT8_C(4)
156	#define AC97_REC_STEREO_MIX UINT8_C(5)
157	#define AC97_REC_MONO_MIX UINT8_C(6)
158	#define AC97_REC_PHONE UINT8_C(7)
159	#define AC97_REC_MASK UINT8_C(7)
160	/** @} */
161
162	/** @name Mixer registers / NAM BAR registers?
163	* @{ */
164	#define AC97_Reset 0x00
165	#define AC97_Master_Volume_Mute 0x02
166	#define AC97_Headphone_Volume_Mute 0x04 /*< Also known as AUX, see table 16, section 5.7. /
167	#define AC97_Master_Volume_Mono_Mute 0x06
168	#define AC97_Master_Tone_RL 0x08
169	#define AC97_PC_BEEP_Volume_Mute 0x0a
170	#define AC97_Phone_Volume_Mute 0x0c
171	#define AC97_Mic_Volume_Mute 0x0e
172	#define AC97_Line_In_Volume_Mute 0x10
173	#define AC97_CD_Volume_Mute 0x12
174	#define AC97_Video_Volume_Mute 0x14
175	#define AC97_Aux_Volume_Mute 0x16
176	#define AC97_PCM_Out_Volume_Mute 0x18
177	#define AC97_Record_Select 0x1a
178	#define AC97_Record_Gain_Mute 0x1c
179	#define AC97_Record_Gain_Mic_Mute 0x1e
180	#define AC97_General_Purpose 0x20
181	#define AC97_3D_Control 0x22
182	#define AC97_AC_97_RESERVED 0x24
183	#define AC97_Powerdown_Ctrl_Stat 0x26
184	#define AC97_Extended_Audio_ID 0x28
185	#define AC97_Extended_Audio_Ctrl_Stat 0x2a
186	#define AC97_PCM_Front_DAC_Rate 0x2c
187	#define AC97_PCM_Surround_DAC_Rate 0x2e
188	#define AC97_PCM_LFE_DAC_Rate 0x30
189	#define AC97_PCM_LR_ADC_Rate 0x32
190	#define AC97_MIC_ADC_Rate 0x34
191	#define AC97_6Ch_Vol_C_LFE_Mute 0x36
192	#define AC97_6Ch_Vol_L_R_Surround_Mute 0x38
193	#define AC97_Vendor_Reserved 0x58
194	#define AC97_AD_Misc 0x76
195	#define AC97_Vendor_ID1 0x7c
196	#define AC97_Vendor_ID2 0x7e
197	/** @} */
198
199	/** @name Analog Devices miscellaneous regiter bits used in AD1980.
200	* @{ */
201	#define AC97_AD_MISC_LOSEL RT_BIT(5) /*< Surround (rear) goes to line out outputs. /
202	#define AC97_AD_MISC_HPSEL RT_BIT(10) /*< PCM (front) goes to headphone outputs. /
203	/** @} */
204
205
206	/** @name BUP flag values.
207	* @{ */
208	#define BUP_SET RT_BIT_32(0)
209	#define BUP_LAST RT_BIT_32(1)
210	/** @} */
211
212	/** @name AC'97 source indices.
213	* @note The order of these indices is fixed (also applies for saved states) for
214	* the moment. So make sure you know what you're done when altering this!
215	* @{
216	*/
217	#define AC97SOUNDSOURCE_PI_INDEX 0 /*< PCM in /
218	#define AC97SOUNDSOURCE_PO_INDEX 1 /*< PCM out /
219	#define AC97SOUNDSOURCE_MC_INDEX 2 /*< Mic in /
220	#define AC97SOUNDSOURCE_MAX 3 /*< Max sound sources. /
221	/** @} */
222
223	/** Port number (offset into NABM BAR) to stream index. */
224	#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
225	/** Port number (offset into NABM BAR) to stream index, but no masking. */
226	#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
227
228	/** @name Stream offsets
229	* @{ */
230	#define AC97_NABM_OFF_BDBAR 0x0 /*< Buffer Descriptor Base Address /
231	#define AC97_NABM_OFF_CIV 0x4 /*< Current Index Value /
232	#define AC97_NABM_OFF_LVI 0x5 /*< Last Valid Index /
233	#define AC97_NABM_OFF_SR 0x6 /*< Status Register /
234	#define AC97_NABM_OFF_PICB 0x8 /*< Position in Current Buffer /
235	#define AC97_NABM_OFF_PIV 0xa /*< Prefetched Index Value /
236	#define AC97_NABM_OFF_CR 0xb /*< Control Register /
237	#define AC97_NABM_OFF_MASK 0xf /*< Mask for getting the the per-stream register. /
238	/** @} */
239
240
241	/** @name PCM in NABM BAR registers (0x00..0x0f).
242	* @{ */
243	#define PI_BDBAR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x0) /*< PCM in: Buffer Descriptor Base Address /
244	#define PI_CIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x4) /*< PCM in: Current Index Value /
245	#define PI_LVI (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x5) /*< PCM in: Last Valid Index /
246	#define PI_SR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x6) /*< PCM in: Status Register /
247	#define PI_PICB (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x8) /*< PCM in: Position in Current Buffer /
248	#define PI_PIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xa) /*< PCM in: Prefetched Index Value /
249	#define PI_CR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xb) /*< PCM in: Control Register /
250	/** @} */
251
252	/** @name PCM out NABM BAR registers (0x10..0x1f).
253	* @{ */
254	#define PO_BDBAR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x0) /*< PCM out: Buffer Descriptor Base Address /
255	#define PO_CIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x4) /*< PCM out: Current Index Value /
256	#define PO_LVI (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x5) /*< PCM out: Last Valid Index /
257	#define PO_SR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x6) /*< PCM out: Status Register /
258	#define PO_PICB (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x8) /*< PCM out: Position in Current Buffer /
259	#define PO_PIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xa) /*< PCM out: Prefetched Index Value /
260	#define PO_CR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xb) /*< PCM out: Control Register /
261	/** @} */
262
263	/** @name Mic in NABM BAR registers (0x20..0x2f).
264	* @{ */
265	#define MC_BDBAR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x0) /*< PCM in: Buffer Descriptor Base Address /
266	#define MC_CIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x4) /*< PCM in: Current Index Value /
267	#define MC_LVI (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x5) /*< PCM in: Last Valid Index /
268	#define MC_SR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x6) /*< PCM in: Status Register /
269	#define MC_PICB (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x8) /*< PCM in: Position in Current Buffer /
270	#define MC_PIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xa) /*< PCM in: Prefetched Index Value /
271	#define MC_CR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xb) /*< PCM in: Control Register /
272	/** @} */
273
274	/** @name Misc NABM BAR registers.
275	* @{ */
276	/** NABMBAR: Global Control Register.
277	* @note This is kind of in the MIC IN area. */
278	#define AC97_GLOB_CNT 0x2c
279	/** NABMBAR: Global Status. */
280	#define AC97_GLOB_STA 0x30
281	/** Codec Access Semaphore Register. */
282	#define AC97_CAS 0x34
283	/** @} */
284
285
286	/*********************************************************************************************************************************
287	* Structures and Typedefs *
288	*********************************************************************************************************************************/
289	/** The ICH AC'97 (Intel) controller (shared). */
290	typedef struct AC97STATE *PAC97STATE;
291	/** The ICH AC'97 (Intel) controller (ring-3). */
292	typedef struct AC97STATER3 *PAC97STATER3;
293
294	/**
295	* Buffer Descriptor List Entry (BDLE).
296	*/
297	typedef struct AC97BDLE
298	{
299	/** Location of data buffer (bits 31:1). */
300	uint32_t addr;
301	/** Flags (bits 31 + 30) and length (bits 15:0) of data buffer (in audio samples). */
302	uint32_t ctl_len;
303	} AC97BDLE;
304	AssertCompileSize(AC97BDLE, 8);
305	/** Pointer to BDLE. */
306	typedef AC97BDLE *PAC97BDLE;
307
308	/**
309	* Bus master register set for an audio stream.
310	*/
311	typedef struct AC97BMREGS
312	{
313	uint32_t bdbar; /*< rw 0, Buffer Descriptor List: BAR (Base Address Register). /
314	uint8_t civ; /*< ro 0, Current index value. /
315	uint8_t lvi; /*< rw 0, Last valid index. /
316	uint16_t sr; /*< rw 1, Status register. /
317	uint16_t picb; /*< ro 0, Position in current buffer (in samples). /
318	uint8_t piv; /*< ro 0, Prefetched index value. /
319	uint8_t cr; /*< rw 0, Control register. /
320	int32_t bd_valid; /*< Whether current BDLE is initialized or not. /
321	AC97BDLE bd; /*< Current Buffer Descriptor List Entry (BDLE). /
322	} AC97BMREGS;
323	AssertCompileSizeAlignment(AC97BMREGS, 8);
324	/** Pointer to the BM registers of an audio stream. */
325	typedef AC97BMREGS *PAC97BMREGS;
326
327	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
328	/**
329	* Asynchronous I/O state for an AC'97 stream.
330	*/
331	typedef struct AC97STREAMSTATEAIO
332	{
333	/** Thread handle for the actual I/O thread. */
334	RTTHREAD Thread;
335	/** Event for letting the thread know there is some data to process. */
336	RTSEMEVENT Event;
337	/** Critical section for synchronizing access. */
338	RTCRITSECT CritSect;
339	/** Started indicator. */
340	volatile bool fStarted;
341	/** Shutdown indicator. */
342	volatile bool fShutdown;
343	/** Whether the thread should do any data processing or not. */
344	volatile bool fEnabled;
345	bool afPadding[5];
346	} AC97STREAMSTATEAIO;
347	/** Pointer to the async I/O state for an AC'97 stream. */
348	typedef AC97STREAMSTATEAIO *PAC97STREAMSTATEAIO;
349	#endif
350
351
352	/**
353	* The internal state of an AC'97 stream.
354	*/
355	typedef struct AC97STREAMSTATE
356	{
357	/** Criticial section for this stream. */
358	RTCRITSECT CritSect;
359	/** Circular buffer (FIFO) for holding DMA'ed data. */
360	R3PTRTYPE(PRTCIRCBUF) pCircBuf;
361	#if HC_ARCH_BITS == 32
362	uint32_t Padding;
363	#endif
364	/** The stream's current configuration. */
365	PDMAUDIOSTREAMCFG Cfg; //+108
366	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
367	/** Asynchronous I/O state members. */
368	AC97STREAMSTATEAIO AIO;
369	#endif
370	/** Timestamp of the last DMA data transfer. */
371	uint64_t tsTransferLast;
372	/** Timestamp of the next DMA data transfer.
373	* Next for determining the next scheduling window.
374	* Can be 0 if no next transfer is scheduled. */
375	uint64_t tsTransferNext;
376	/** Transfer chunk size (in bytes) of a transfer period. */
377	uint32_t cbTransferChunk;
378	/** The stream's timer Hz rate.
379	* This value can can be different from the device's default Hz rate,
380	* depending on the rate the stream expects (e.g. for 5.1 speaker setups).
381	* Set in R3StreamInit(). */
382	uint16_t uTimerHz;
383	uint8_t Padding3[2];
384	/** (Virtual) clock ticks per transfer. */
385	uint64_t cTransferTicks;
386	/** Timestamp (in ns) of last stream update. */
387	uint64_t tsLastUpdateNs;
388	} AC97STREAMSTATE;
389	AssertCompileSizeAlignment(AC97STREAMSTATE, 8);
390	/** Pointer to internal state of an AC'97 stream. */
391	typedef AC97STREAMSTATE *PAC97STREAMSTATE;
392
393	/**
394	* Runtime configurable debug stuff for an AC'97 stream.
395	*/
396	typedef struct AC97STREAMDEBUGRT
397	{
398	/** Whether debugging is enabled or not. */
399	bool fEnabled;
400	uint8_t Padding[7];
401	/** File for dumping stream reads / writes.
402	* For input streams, this dumps data being written to the device FIFO,
403	* whereas for output streams this dumps data being read from the device FIFO. */
404	R3PTRTYPE(PAUDIOHLPFILE) pFileStream;
405	/** File for dumping DMA reads / writes.
406	* For input streams, this dumps data being written to the device DMA,
407	* whereas for output streams this dumps data being read from the device DMA. */
408	R3PTRTYPE(PAUDIOHLPFILE) pFileDMA;
409	} AC97STREAMDEBUGRT;
410
411	/**
412	* Debug stuff for an AC'97 stream.
413	*/
414	typedef struct AC97STREAMDEBUG
415	{
416	/** Runtime debug stuff. */
417	AC97STREAMDEBUGRT Runtime;
418	} AC97STREAMDEBUG;
419
420	/**
421	* The shared AC'97 stream state.
422	*/
423	typedef struct AC97STREAM
424	{
425	/** Stream number (SDn). */
426	uint8_t u8SD;
427	uint8_t abPadding0[7];
428	/** Bus master registers of this stream. */
429	AC97BMREGS Regs;
430	/** The timer for pumping data thru the attached LUN drivers. */
431	TMTIMERHANDLE hTimer;
432	} AC97STREAM;
433	AssertCompileSizeAlignment(AC97STREAM, 8);
434	/** Pointer to a shared AC'97 stream state. */
435	typedef AC97STREAM *PAC97STREAM;
436
437
438	/**
439	* The ring-3 AC'97 stream state.
440	*/
441	typedef struct AC97STREAMR3
442	{
443	/** Stream number (SDn). */
444	uint8_t u8SD;
445	uint8_t abPadding0[7];
446	/** Internal state of this stream. */
447	AC97STREAMSTATE State;
448	/** Debug stuff. */
449	AC97STREAMDEBUG Dbg;
450	} AC97STREAMR3;
451	AssertCompileSizeAlignment(AC97STREAMR3, 8);
452	/** Pointer to an AC'97 stream state for ring-3. */
453	typedef AC97STREAMR3 *PAC97STREAMR3;
454
455
456	#ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
457	/**
458	* Asynchronous I/O thread context (arguments).
459	*/
460	typedef struct AC97STREAMTHREADCTX
461	{
462	/** The AC'97 device state (shared). */
463	PAC97STATE pThis;
464	/** The AC'97 device state (ring-3). */
465	PAC97STATER3 pThisCC;
466	/** The AC'97 stream state (shared). */
467	PAC97STREAM pStream;
468	/** The AC'97 stream state (ring-3). */
469	PAC97STREAMR3 pStreamCC;
470	} AC97STREAMTHREADCTX;
471	/** Pointer to the context for an async I/O thread. */
472	typedef AC97STREAMTHREADCTX *PAC97STREAMTHREADCTX;
473	#endif
474
475	/**
476	* A driver stream (host backend).
477	*
478	* Each driver has its own instances of audio mixer streams, which then
479	* can go into the same (or even different) audio mixer sinks.
480	*/
481	typedef struct AC97DRIVERSTREAM
482	{
483	/** Associated mixer stream handle. */
484	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
485	} AC97DRIVERSTREAM;
486	/** Pointer to a driver stream. */
487	typedef AC97DRIVERSTREAM *PAC97DRIVERSTREAM;
488
489	/**
490	* A host backend driver (LUN).
491	*/
492	typedef struct AC97DRIVER
493	{
494	/** Node for storing this driver in our device driver list of AC97STATE. */
495	RTLISTNODER3 Node;
496	/** Driver flags. */
497	PDMAUDIODRVFLAGS fFlags;
498	/** LUN # to which this driver has been assigned. */
499	uint8_t uLUN;
500	/** Whether this driver is in an attached state or not. */
501	bool fAttached;
502	uint8_t abPadding[2];
503	/** Pointer to the description string passed to PDMDevHlpDriverAttach(). */
504	R3PTRTYPE(char *) pszDesc;
505	/** Pointer to attached driver base interface. */
506	R3PTRTYPE(PPDMIBASE) pDrvBase;
507	/** Audio connector interface to the underlying host backend. */
508	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
509	/** Driver stream for line input. */
510	AC97DRIVERSTREAM LineIn;
511	/** Driver stream for mic input. */
512	AC97DRIVERSTREAM MicIn;
513	/** Driver stream for output. */
514	AC97DRIVERSTREAM Out;
515	} AC97DRIVER;
516	/** Pointer to a host backend driver (LUN). */
517	typedef AC97DRIVER *PAC97DRIVER;
518
519	/**
520	* Debug settings.
521	*/
522	typedef struct AC97STATEDEBUG
523	{
524	/** Whether debugging is enabled or not. */
525	bool fEnabled;
526	bool afAlignment[7];
527	/** Path where to dump the debug output to.
528	* Can be NULL, in which the system's temporary directory will be used then. */
529	R3PTRTYPE(char *) pszOutPath;
530	} AC97STATEDEBUG;
531
532
533	/* Codec models. */
534	typedef enum AC97CODEC
535	{
536	AC97CODEC_INVALID = 0, /*< Customary illegal zero value. /
537	AC97CODEC_STAC9700, /*< SigmaTel STAC9700 /
538	AC97CODEC_AD1980, /*< Analog Devices AD1980 /
539	AC97CODEC_AD1981B, /*< Analog Devices AD1981B /
540	AC97CODEC_32BIT_HACK = 0x7fffffff
541	} AC97CODEC;
542
543
544	/**
545	* The shared AC'97 device state.
546	*/
547	typedef struct AC97STATE
548	{
549	/** Critical section protecting the AC'97 state. */
550	PDMCRITSECT CritSect;
551	/** Global Control (Bus Master Control Register). */
552	uint32_t glob_cnt;
553	/** Global Status (Bus Master Control Register). */
554	uint32_t glob_sta;
555	/** Codec Access Semaphore Register (Bus Master Control Register). */
556	uint32_t cas;
557	uint32_t last_samp;
558	uint8_t mixer_data[256];
559	/** Array of AC'97 streams (parallel to AC97STATER3::aStreams). */
560	AC97STREAM aStreams[AC97_MAX_STREAMS];
561	/** The device timer Hz rate. Defaults to AC97_TIMER_HZ_DEFAULT_DEFAULT. */
562	uint16_t uTimerHz;
563	uint16_t au16Padding1[3];
564	uint8_t silence[128];
565	uint32_t bup_flag;
566	/** Codec model. */
567	AC97CODEC enmCodecModel;
568
569	/** PCI region \#0: NAM I/O ports. */
570	IOMIOPORTHANDLE hIoPortsNam;
571	/** PCI region \#0: NANM I/O ports. */
572	IOMIOPORTHANDLE hIoPortsNabm;
573
574	STAMCOUNTER StatUnimplementedNabmReads;
575	STAMCOUNTER StatUnimplementedNabmWrites;
576	#ifdef VBOX_WITH_STATISTICS
577	STAMPROFILE StatTimer;
578	STAMPROFILE StatIn;
579	STAMPROFILE StatOut;
580	STAMCOUNTER StatBytesRead;
581	STAMCOUNTER StatBytesWritten;
582	#endif
583	} AC97STATE;
584	AssertCompileMemberAlignment(AC97STATE, aStreams, 8);
585	AssertCompileMemberAlignment(AC97STATE, StatUnimplementedNabmReads, 8);
586	#ifdef VBOX_WITH_STATISTICS
587	AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
588	AssertCompileMemberAlignment(AC97STATE, StatBytesRead, 8);
589	AssertCompileMemberAlignment(AC97STATE, StatBytesWritten, 8);
590	#endif
591
592
593	/**
594	* The ring-3 AC'97 device state.
595	*/
596	typedef struct AC97STATER3
597	{
598	/** Array of AC'97 streams (parallel to AC97STATE:aStreams). */
599	AC97STREAMR3 aStreams[AC97_MAX_STREAMS];
600	/** R3 pointer to the device instance. */
601	PPDMDEVINSR3 pDevIns;
602	/** List of associated LUN drivers (AC97DRIVER). */
603	RTLISTANCHORR3 lstDrv;
604	/** The device's software mixer. */
605	R3PTRTYPE(PAUDIOMIXER) pMixer;
606	/** Audio sink for PCM output. */
607	R3PTRTYPE(PAUDMIXSINK) pSinkOut;
608	/** Audio sink for line input. */
609	R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
610	/** Audio sink for microphone input. */
611	R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
612	/** The base interface for LUN\#0. */
613	PDMIBASE IBase;
614	/** Debug settings. */
615	AC97STATEDEBUG Dbg;
616	} AC97STATER3;
617	AssertCompileMemberAlignment(AC97STATER3, aStreams, 8);
618	/** Pointer to the ring-3 AC'97 device state. */
619	typedef AC97STATER3 *PAC97STATER3;
620
621
622	/**
623	* Acquires the AC'97 lock.
624	*/
625	#define DEVAC97_LOCK(a_pDevIns, a_pThis) \
626	do { \
627	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
628	AssertRC(rcLock); \
629	} while (0)
630
631	/**
632	* Acquires the AC'97 lock or returns.
633	*/
634	# define DEVAC97_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
635	do { \
636	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, a_rcBusy); \
637	if (rcLock == VINF_SUCCESS) \
638	break; \
639	AssertRC(rcLock); \
640	return rcLock; \
641	} while (0)
642
643	/** Retrieves an attribute from a specific audio stream in RC. */
644	#define DEVAC97_CTX_SUFF_SD(a_Var, a_SD) CTX_SUFF(a_Var)[a_SD]
645
646	/**
647	* Releases the AC'97 lock.
648	*/
649	#define DEVAC97_UNLOCK(a_pDevIns, a_pThis) \
650	do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
651
652	/**
653	* Acquires the TM lock and AC'97 lock, returns on failure.
654	*
655	* @todo r=bird: Isn't this overkill for ring-0, only ring-3 access the timer
656	* from what I can tell (ichac97R3StreamTransferCalcNext,
657	* ichac97R3TimerSet, timer callback and state load).
658	*/
659	#define DEVAC97_LOCK_BOTH_RETURN(a_pDevIns, a_pThis, a_pStream, a_rcBusy) \
660	do { \
661	VBOXSTRICTRC rcLock = PDMDevHlpTimerLockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect, (a_rcBusy)); \
662	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
663	{ /* likely */ } \
664	else \
665	{ \
666	AssertRC(VBOXSTRICTRC_VAL(rcLock)); \
667	return rcLock; \
668	} \
669	} while (0)
670
671	/**
672	* Releases the AC'97 lock and TM lock.
673	*/
674	#define DEVAC97_UNLOCK_BOTH(a_pDevIns, a_pThis, a_pStream) \
675	PDMDevHlpTimerUnlockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect)
676
677	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
678
679
680	/*********************************************************************************************************************************
681	* Internal Functions *
682	*********************************************************************************************************************************/
683	#ifdef IN_RING3
684	static int ichac97R3StreamOpen(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
685	PAC97STREAMR3 pStreamCC, bool fForce);
686	static int ichac97R3StreamClose(PAC97STREAM pStream);
687	static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC);
688	static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC);
689	static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC);
690	static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC);
691	static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
692	PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax);
693	static void ichac97R3StreamUpdate(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
694	PAC97STREAMR3 pStreamCC, bool fInTimer);
695
696	static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns);
697
698	static void ichac97R3MixerRemoveDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
699	PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc);
700
701	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
702	static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC);
703	static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAMR3 pStreamCC);
704	static void ichac97R3StreamAsyncIOLock(PAC97STREAMR3 pStreamCC);
705	static void ichac97R3StreamAsyncIOUnlock(PAC97STREAMR3 pStreamCC);
706	/static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable); Unused /
707	# endif
708
709	DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD);
710	DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline);
711	#endif /* IN_RING3 */
712
713
714	/*********************************************************************************************************************************
715	* Global Variables *
716	*********************************************************************************************************************************/
717	#ifdef IN_RING3
718	/** NABM I/O port descriptions. */
719	static const IOMIOPORTDESC g_aNabmPorts[] =
720	{
721	{ "PCM IN - BDBAR", "PCM IN - BDBAR", NULL, NULL },
722	{ "", NULL, NULL, NULL },
723	{ "", NULL, NULL, NULL },
724	{ "", NULL, NULL, NULL },
725	{ "PCM IN - CIV", "PCM IN - CIV", NULL, NULL },
726	{ "PCM IN - LVI", "PCM IN - LIV", NULL, NULL },
727	{ "PCM IN - SR", "PCM IN - SR", NULL, NULL },
728	{ "", NULL, NULL, NULL },
729	{ "PCM IN - PICB", "PCM IN - PICB", NULL, NULL },
730	{ "", NULL, NULL, NULL },
731	{ "PCM IN - PIV", "PCM IN - PIV", NULL, NULL },
732	{ "PCM IN - CR", "PCM IN - CR", NULL, NULL },
733	{ "", NULL, NULL, NULL },
734	{ "", NULL, NULL, NULL },
735	{ "", NULL, NULL, NULL },
736	{ "", NULL, NULL, NULL },
737
738	{ "PCM OUT - BDBAR", "PCM OUT - BDBAR", NULL, NULL },
739	{ "", NULL, NULL, NULL },
740	{ "", NULL, NULL, NULL },
741	{ "", NULL, NULL, NULL },
742	{ "PCM OUT - CIV", "PCM OUT - CIV", NULL, NULL },
743	{ "PCM OUT - LVI", "PCM OUT - LIV", NULL, NULL },
744	{ "PCM OUT - SR", "PCM OUT - SR", NULL, NULL },
745	{ "", NULL, NULL, NULL },
746	{ "PCM OUT - PICB", "PCM OUT - PICB", NULL, NULL },
747	{ "", NULL, NULL, NULL },
748	{ "PCM OUT - PIV", "PCM OUT - PIV", NULL, NULL },
749	{ "PCM OUT - CR", "PCM IN - CR", NULL, NULL },
750	{ "", NULL, NULL, NULL },
751	{ "", NULL, NULL, NULL },
752	{ "", NULL, NULL, NULL },
753	{ "", NULL, NULL, NULL },
754
755	{ "MIC IN - BDBAR", "MIC IN - BDBAR", NULL, NULL },
756	{ "", NULL, NULL, NULL },
757	{ "", NULL, NULL, NULL },
758	{ "", NULL, NULL, NULL },
759	{ "MIC IN - CIV", "MIC IN - CIV", NULL, NULL },
760	{ "MIC IN - LVI", "MIC IN - LIV", NULL, NULL },
761	{ "MIC IN - SR", "MIC IN - SR", NULL, NULL },
762	{ "", NULL, NULL, NULL },
763	{ "MIC IN - PICB", "MIC IN - PICB", NULL, NULL },
764	{ "", NULL, NULL, NULL },
765	{ "MIC IN - PIV", "MIC IN - PIV", NULL, NULL },
766	{ "MIC IN - CR", "MIC IN - CR", NULL, NULL },
767	{ "GLOB CNT", "GLOB CNT", NULL, NULL },
768	{ "", NULL, NULL, NULL },
769	{ "", NULL, NULL, NULL },
770	{ "", NULL, NULL, NULL },
771
772	{ "GLOB STA", "GLOB STA", NULL, NULL },
773	{ "", NULL, NULL, NULL },
774	{ "", NULL, NULL, NULL },
775	{ "", NULL, NULL, NULL },
776	{ "CAS", "CAS", NULL, NULL },
777	{ NULL, NULL, NULL, NULL },
778	};
779
780	/** @name Source indices
781	* @{ */
782	#define AC97SOUNDSOURCE_PI_INDEX 0 /*< PCM in /
783	#define AC97SOUNDSOURCE_PO_INDEX 1 /*< PCM out /
784	#define AC97SOUNDSOURCE_MC_INDEX 2 /*< Mic in /
785	#define AC97SOUNDSOURCE_MAX 3 /*< Max sound sources. /
786	/** @} */
787
788	/** Port number (offset into NABM BAR) to stream index. */
789	#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
790	/** Port number (offset into NABM BAR) to stream index, but no masking. */
791	#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
792
793	/** @name Stream offsets
794	* @{ */
795	#define AC97_NABM_OFF_BDBAR 0x0 /*< Buffer Descriptor Base Address /
796	#define AC97_NABM_OFF_CIV 0x4 /*< Current Index Value /
797	#define AC97_NABM_OFF_LVI 0x5 /*< Last Valid Index /
798	#define AC97_NABM_OFF_SR 0x6 /*< Status Register /
799	#define AC97_NABM_OFF_PICB 0x8 /*< Position in Current Buffer /
800	#define AC97_NABM_OFF_PIV 0xa /*< Prefetched Index Value /
801	#define AC97_NABM_OFF_CR 0xb /*< Control Register /
802	#define AC97_NABM_OFF_MASK 0xf /*< Mask for getting the the per-stream register. /
803	/** @} */
804
805	#endif
806
807
808
809	static void ichac97WarmReset(PAC97STATE pThis)
810	{
811	NOREF(pThis);
812	}
813
814	static void ichac97ColdReset(PAC97STATE pThis)
815	{
816	NOREF(pThis);
817	}
818
819
820	#ifdef IN_RING3
821
822	/**
823	* Retrieves the audio mixer sink of a corresponding AC'97 stream index.
824	*
825	* @returns Pointer to audio mixer sink if found, or NULL if not found / invalid.
826	* @param pThisCC The ring-3 AC'97 state.
827	* @param uIndex Stream index to get audio mixer sink for.
828	*/
829	DECLINLINE(PAUDMIXSINK) ichac97R3IndexToSink(PAC97STATER3 pThisCC, uint8_t uIndex)
830	{
831	switch (uIndex)
832	{
833	case AC97SOUNDSOURCE_PI_INDEX: return pThisCC->pSinkLineIn;
834	case AC97SOUNDSOURCE_PO_INDEX: return pThisCC->pSinkOut;
835	case AC97SOUNDSOURCE_MC_INDEX: return pThisCC->pSinkMicIn;
836	default:
837	AssertMsgFailedReturn(("Wrong index %RU8\n", uIndex), NULL);
838	}
839	}
840
841	/**
842	* Fetches the current BDLE (Buffer Descriptor List Entry) of an AC'97 audio stream.
843	*
844	* @returns VBox status code.
845	* @param pDevIns The device instance.
846	* @param pStream AC'97 stream to fetch BDLE for.
847	*
848	* @remark Uses CIV as BDLE index.
849	*/
850	static void ichac97R3StreamFetchBDLE(PPDMDEVINS pDevIns, PAC97STREAM pStream)
851	{
852	PAC97BMREGS pRegs = &pStream->Regs;
853
854	AC97BDLE BDLE;
855	PDMDevHlpPCIPhysRead(pDevIns, pRegs->bdbar + pRegs->civ * sizeof(AC97BDLE), &BDLE, sizeof(AC97BDLE));
856	pRegs->bd_valid = 1;
857	# ifndef RT_LITTLE_ENDIAN
858	# error "Please adapt the code (audio buffers are little endian)!"
859	# else
860	pRegs->bd.addr = RT_H2LE_U32(BDLE.addr & ~3);
861	pRegs->bd.ctl_len = RT_H2LE_U32(BDLE.ctl_len);
862	# endif
863	pRegs->picb = pRegs->bd.ctl_len & AC97_BD_LEN_MASK;
864	LogFlowFunc(("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes), bup=%RTbool, ioc=%RTbool\n",
865	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len >> 16,
866	pRegs->bd.ctl_len & AC97_BD_LEN_MASK,
867	(pRegs->bd.ctl_len & AC97_BD_LEN_MASK) << 1, /** @todo r=andy Assumes 16bit samples. */
868	RT_BOOL(pRegs->bd.ctl_len & AC97_BD_BUP),
869	RT_BOOL(pRegs->bd.ctl_len & AC97_BD_IOC)));
870	}
871
872	#endif /* IN_RING3 */
873
874	/**
875	* Updates the status register (SR) of an AC'97 audio stream.
876	*
877	* @param pDevIns The device instance.
878	* @param pThis The shared AC'97 state.
879	* @param pStream AC'97 stream to update SR for.
880	* @param new_sr New value for status register (SR).
881	*/
882	static void ichac97StreamUpdateSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr)
883	{
884	PAC97BMREGS pRegs = &pStream->Regs;
885
886	bool fSignal = false;
887	int iIRQL = 0;
888
889	uint32_t new_mask = new_sr & AC97_SR_INT_MASK;
890	uint32_t old_mask = pRegs->sr & AC97_SR_INT_MASK;
891
892	if (new_mask ^ old_mask)
893	{
894	/** @todo Is IRQ deasserted when only one of status bits is cleared? */
895	if (!new_mask)
896	{
897	fSignal = true;
898	iIRQL = 0;
899	}
900	else if ((new_mask & AC97_SR_LVBCI) && (pRegs->cr & AC97_CR_LVBIE))
901	{
902	fSignal = true;
903	iIRQL = 1;
904	}
905	else if ((new_mask & AC97_SR_BCIS) && (pRegs->cr & AC97_CR_IOCE))
906	{
907	fSignal = true;
908	iIRQL = 1;
909	}
910	}
911
912	pRegs->sr = new_sr;
913
914	LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n",
915	pRegs->sr & AC97_SR_BCIS, pRegs->sr & AC97_SR_LVBCI, pRegs->sr, fSignal, iIRQL));
916
917	if (fSignal)
918	{
919	static uint32_t const s_aMasks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT };
920	Assert(pStream->u8SD < AC97_MAX_STREAMS);
921	if (iIRQL)
922	pThis->glob_sta \|= s_aMasks[pStream->u8SD];
923	else
924	pThis->glob_sta &= ~s_aMasks[pStream->u8SD];
925
926	LogFlowFunc(("Setting IRQ level=%d\n", iIRQL));
927	PDMDevHlpPCISetIrq(pDevIns, 0, iIRQL);
928	}
929	}
930
931	/**
932	* Writes a new value to a stream's status register (SR).
933	*
934	* @param pDevIns The device instance.
935	* @param pThis The shared AC'97 device state.
936	* @param pStream Stream to update SR for.
937	* @param u32Val New value to set the stream's SR to.
938	*/
939	static void ichac97StreamWriteSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t u32Val)
940	{
941	PAC97BMREGS pRegs = &pStream->Regs;
942
943	Log3Func(("[SD%RU8] SR <- %#x (sr %#x)\n", pStream->u8SD, u32Val, pRegs->sr));
944
945	pRegs->sr \|= u32Val & ~(AC97_SR_RO_MASK \| AC97_SR_WCLEAR_MASK);
946	ichac97StreamUpdateSR(pDevIns, pThis, pStream, pRegs->sr & ~(u32Val & AC97_SR_WCLEAR_MASK));
947	}
948
949	#ifdef IN_RING3
950
951	/**
952	* Returns whether an AC'97 stream is enabled or not.
953	*
954	* @returns VBox status code.
955	* @param pThisCC The ring-3 AC'97 device state.
956	* @param pStream Stream to return status for.
957	*/
958	static bool ichac97R3StreamIsEnabled(PAC97STATER3 pThisCC, PAC97STREAM pStream)
959	{
960	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
961	bool fIsEnabled = RT_BOOL(AudioMixerSinkGetStatus(pSink) & AUDMIXSINK_STS_RUNNING);
962
963	LogFunc(("[SD%RU8] fIsEnabled=%RTbool\n", pStream->u8SD, fIsEnabled));
964	return fIsEnabled;
965	}
966
967	/**
968	* Enables or disables an AC'97 audio stream.
969	*
970	* @returns VBox status code.
971	* @param pDevIns The device instance.
972	* @param pThis The shared AC'97 state.
973	* @param pThisCC The ring-3 AC'97 state.
974	* @param pStream The AC'97 stream to enable or disable (shared
975	* state).
976	* @param pStreamCC The ring-3 stream state (matching to @a pStream).
977	* @param fEnable Whether to enable or disable the stream.
978	*
979	*/
980	static int ichac97R3StreamEnable(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
981	PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fEnable)
982	{
983	ichac97R3StreamLock(pStreamCC);
984
985	int rc = VINF_SUCCESS;
986
987	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
988	if (fEnable)
989	rc = ichac97R3StreamAsyncIOCreate(pThis, pThisCC, pStream, pStreamCC);
990	if (RT_SUCCESS(rc))
991	ichac97R3StreamAsyncIOLock(pStreamCC);
992	# endif
993
994	if (fEnable)
995	{
996	if (pStreamCC->State.pCircBuf)
997	RTCircBufReset(pStreamCC->State.pCircBuf);
998
999	rc = ichac97R3StreamOpen(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fForce */);
1000
1001	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1002	{ /* likely */ }
1003	else
1004	{
1005	if (!AudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileStream))
1006	{
1007	int rc2 = AudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1008	&pStreamCC->State.Cfg.Props);
1009	AssertRC(rc2);
1010	}
1011
1012	if (!AudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileDMA))
1013	{
1014	int rc2 = AudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileDMA, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1015	&pStreamCC->State.Cfg.Props);
1016	AssertRC(rc2);
1017	}
1018	}
1019	}
1020	else
1021	rc = ichac97R3StreamClose(pStream);
1022
1023	if (RT_SUCCESS(rc))
1024	{
1025	/* First, enable or disable the stream and the stream's sink, if any. */
1026	rc = AudioMixerSinkEnable(ichac97R3IndexToSink(pThisCC, pStream->u8SD), fEnable);
1027	}
1028
1029	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1030	ichac97R3StreamAsyncIOUnlock(pStreamCC);
1031	# endif
1032
1033	/* Make sure to leave the lock before (eventually) starting the timer. */
1034	ichac97R3StreamUnlock(pStreamCC);
1035
1036	LogFunc(("[SD%RU8] fEnable=%RTbool, rc=%Rrc\n", pStream->u8SD, fEnable, rc));
1037	return rc;
1038	}
1039
1040	/**
1041	* Resets an AC'97 stream.
1042	*
1043	* @param pThis The shared AC'97 state.
1044	* @param pStream The AC'97 stream to reset (shared).
1045	* @param pStreamCC The AC'97 stream to reset (ring-3).
1046	*/
1047	static void ichac97R3StreamReset(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1048	{
1049	ichac97R3StreamLock(pStreamCC);
1050
1051	LogFunc(("[SD%RU8]\n", pStream->u8SD));
1052
1053	if (pStreamCC->State.pCircBuf)
1054	RTCircBufReset(pStreamCC->State.pCircBuf);
1055
1056	PAC97BMREGS pRegs = &pStream->Regs;
1057
1058	pRegs->bdbar = 0;
1059	pRegs->civ = 0;
1060	pRegs->lvi = 0;
1061
1062	pRegs->picb = 0;
1063	pRegs->piv = 0;
1064	pRegs->cr = pRegs->cr & AC97_CR_DONT_CLEAR_MASK;
1065	pRegs->bd_valid = 0;
1066
1067	RT_ZERO(pThis->silence);
1068
1069	ichac97R3StreamUnlock(pStreamCC);
1070	}
1071
1072	/**
1073	* Creates an AC'97 audio stream.
1074	*
1075	* @returns VBox status code.
1076	* @param pThisCC The ring-3 AC'97 state.
1077	* @param pStream The AC'97 stream to create (shared).
1078	* @param pStreamCC The AC'97 stream to create (ring-3).
1079	* @param u8SD Stream descriptor number to assign.
1080	*/
1081	static int ichac97R3StreamCreate(PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint8_t u8SD)
1082	{
1083	LogFunc(("[SD%RU8] pStream=%p\n", u8SD, pStream));
1084
1085	AssertReturn(u8SD < AC97_MAX_STREAMS, VERR_INVALID_PARAMETER);
1086	pStream->u8SD = u8SD;
1087	pStreamCC->u8SD = u8SD;
1088
1089	int rc = RTCritSectInit(&pStreamCC->State.CritSect);
1090	AssertRCReturn(rc, rc);
1091
1092	pStreamCC->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
1093
1094	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1095	{ /* likely */ }
1096	else
1097	{
1098	char szFile[64];
1099
1100	if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1101	RTStrPrintf(szFile, sizeof(szFile), "ac97StreamWriteSD%RU8", pStream->u8SD);
1102	else
1103	RTStrPrintf(szFile, sizeof(szFile), "ac97StreamReadSD%RU8", pStream->u8SD);
1104
1105	char szPath[RTPATH_MAX];
1106	int rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1107	0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
1108	AssertRC(rc2);
1109	rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileStream);
1110	AssertRC(rc2);
1111
1112	if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1113	RTStrPrintf(szFile, sizeof(szFile), "ac97DMAWriteSD%RU8", pStream->u8SD);
1114	else
1115	RTStrPrintf(szFile, sizeof(szFile), "ac97DMAReadSD%RU8", pStream->u8SD);
1116
1117	rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1118	0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
1119	AssertRC(rc2);
1120
1121	rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileDMA);
1122	AssertRC(rc2);
1123
1124	/* Delete stale debugging files from a former run. */
1125	AudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileStream);
1126	AudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileDMA);
1127	}
1128
1129	return rc;
1130	}
1131
1132	/**
1133	* Destroys an AC'97 audio stream.
1134	*
1135	* @returns VBox status code.
1136	* @param pThis The shared AC'97 state.
1137	* @param pStream The AC'97 stream to destroy (shared).
1138	* @param pStreamCC The AC'97 stream to destroy (ring-3).
1139	*/
1140	static void ichac97R3StreamDestroy(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1141	{
1142	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
1143
1144	ichac97R3StreamClose(pStream);
1145
1146	int rc2 = RTCritSectDelete(&pStreamCC->State.CritSect);
1147	AssertRC(rc2);
1148
1149	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1150	rc2 = ichac97R3StreamAsyncIODestroy(pThis, pStreamCC);
1151	AssertRC(rc2);
1152	# else
1153	RT_NOREF(pThis);
1154	# endif
1155
1156	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1157	{ /* likely */ }
1158	else
1159	{
1160	AudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileStream);
1161	pStreamCC->Dbg.Runtime.pFileStream = NULL;
1162
1163	AudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileDMA);
1164	pStreamCC->Dbg.Runtime.pFileDMA = NULL;
1165	}
1166
1167	if (pStreamCC->State.pCircBuf)
1168	{
1169	RTCircBufDestroy(pStreamCC->State.pCircBuf);
1170	pStreamCC->State.pCircBuf = NULL;
1171	}
1172
1173	LogFlowFuncLeave();
1174	}
1175
1176	/**
1177	* Destroys all AC'97 audio streams of the device.
1178	*
1179	* @param pDevIns The device AC'97 instance.
1180	* @param pThis The shared AC'97 state.
1181	* @param pThisCC The ring-3 AC'97 state.
1182	*/
1183	static void ichac97R3StreamsDestroy(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC)
1184	{
1185	LogFlowFuncEnter();
1186
1187	/*
1188	* Destroy all AC'97 streams.
1189	*/
1190	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
1191	ichac97R3StreamDestroy(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
1192
1193	/*
1194	* Destroy all sinks.
1195	*/
1196
1197	PDMAUDIODSTSRCUNION dstSrc;
1198	if (pThisCC->pSinkLineIn)
1199	{
1200	dstSrc.enmSrc = PDMAUDIORECSRC_LINE;
1201	ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkLineIn, PDMAUDIODIR_IN, dstSrc);
1202
1203	AudioMixerSinkDestroy(pThisCC->pSinkLineIn, pDevIns);
1204	pThisCC->pSinkLineIn = NULL;
1205	}
1206
1207	if (pThisCC->pSinkMicIn)
1208	{
1209	dstSrc.enmSrc = PDMAUDIORECSRC_MIC;
1210	ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkMicIn, PDMAUDIODIR_IN, dstSrc);
1211
1212	AudioMixerSinkDestroy(pThisCC->pSinkMicIn, pDevIns);
1213	pThisCC->pSinkMicIn = NULL;
1214	}
1215
1216	if (pThisCC->pSinkOut)
1217	{
1218	dstSrc.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
1219	ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkOut, PDMAUDIODIR_OUT, dstSrc);
1220
1221	AudioMixerSinkDestroy(pThisCC->pSinkOut, pDevIns);
1222	pThisCC->pSinkOut = NULL;
1223	}
1224	}
1225
1226	/**
1227	* Writes audio data from a mixer sink into an AC'97 stream's DMA buffer.
1228	*
1229	* @returns VBox status code.
1230	* @param pDstStreamCC The AC'97 stream to write to (ring-3).
1231	* @param pSrcMixSink Mixer sink to get audio data to write from.
1232	* @param cbToWrite Number of bytes to write.
1233	* @param pcbWritten Number of bytes written. Optional.
1234	*/
1235	static int ichac97R3StreamWrite(PAC97STREAMR3 pDstStreamCC, PAUDMIXSINK pSrcMixSink, uint32_t cbToWrite, uint32_t *pcbWritten)
1236	{
1237	AssertPtrReturn(pSrcMixSink, VERR_INVALID_POINTER);
1238	AssertReturn(cbToWrite > 0, VERR_INVALID_PARAMETER);
1239	/* pcbWritten is optional. */
1240
1241	PRTCIRCBUF pCircBuf = pDstStreamCC->State.pCircBuf;
1242	AssertPtr(pCircBuf);
1243
1244	uint32_t cbRead = 0;
1245
1246	void *pvDst;
1247	size_t cbDst;
1248	RTCircBufAcquireWriteBlock(pCircBuf, cbToWrite, &pvDst, &cbDst);
1249
1250	if (cbDst)
1251	{
1252	int rc2 = AudioMixerSinkRead(pSrcMixSink, AUDMIXOP_COPY, pvDst, (uint32_t)cbDst, &cbRead);
1253	AssertRC(rc2);
1254
1255	if (RT_LIKELY(!pDstStreamCC->Dbg.Runtime.fEnabled))
1256	{ /* likely */ }
1257	else
1258	AudioHlpFileWrite(pDstStreamCC->Dbg.Runtime.pFileStream, pvDst, cbRead, 0 /* fFlags */);
1259	}
1260
1261	RTCircBufReleaseWriteBlock(pCircBuf, cbRead);
1262
1263	if (pcbWritten)
1264	*pcbWritten = cbRead;
1265
1266	return VINF_SUCCESS;
1267	}
1268
1269	/**
1270	* Reads audio data from an AC'97 stream's DMA buffer and writes into a specified mixer sink.
1271	*
1272	* @returns VBox status code.
1273	* @param pSrcStreamCC AC'97 stream to read audio data from (ring-3).
1274	* @param pDstMixSink Mixer sink to write audio data to.
1275	* @param cbToRead Number of bytes to read.
1276	* @param pcbRead Number of bytes read. Optional.
1277	*/
1278	static int ichac97R3StreamRead(PAC97STREAMR3 pSrcStreamCC, PAUDMIXSINK pDstMixSink, uint32_t cbToRead, uint32_t *pcbRead)
1279	{
1280	AssertPtrReturn(pDstMixSink, VERR_INVALID_POINTER);
1281	AssertReturn(cbToRead > 0, VERR_INVALID_PARAMETER);
1282	/* pcbRead is optional. */
1283
1284	PRTCIRCBUF pCircBuf = pSrcStreamCC->State.pCircBuf;
1285	AssertPtr(pCircBuf);
1286
1287	void *pvSrc;
1288	size_t cbSrc;
1289
1290	int rc = VINF_SUCCESS;
1291
1292	uint32_t cbReadTotal = 0;
1293	uint32_t cbLeft = RT_MIN(cbToRead, (uint32_t)RTCircBufUsed(pCircBuf));
1294
1295	while (cbLeft)
1296	{
1297	uint32_t cbWritten = 0;
1298
1299	RTCircBufAcquireReadBlock(pCircBuf, cbLeft, &pvSrc, &cbSrc);
1300
1301	if (cbSrc)
1302	{
1303	if (RT_LIKELY(!pSrcStreamCC->Dbg.Runtime.fEnabled))
1304	{ /* likely */ }
1305	else
1306	AudioHlpFileWrite(pSrcStreamCC->Dbg.Runtime.pFileStream, pvSrc, cbSrc, 0 /* fFlags */);
1307
1308	rc = AudioMixerSinkWrite(pDstMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbWritten);
1309	AssertRC(rc);
1310
1311	Assert(cbSrc >= cbWritten);
1312	Log3Func(("[SD%RU8] %RU32/%zu bytes read\n", pSrcStreamCC->u8SD, cbWritten, cbSrc));
1313	}
1314
1315	RTCircBufReleaseReadBlock(pCircBuf, cbWritten);
1316
1317	if ( !cbWritten /* Nothing written? */
1318	\|\| RT_FAILURE(rc))
1319	break;
1320
1321	Assert(cbLeft >= cbWritten);
1322	cbLeft -= cbWritten;
1323
1324	cbReadTotal += cbWritten;
1325	}
1326
1327	if (pcbRead)
1328	*pcbRead = cbReadTotal;
1329
1330	return rc;
1331	}
1332
1333	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1334
1335	/**
1336	* Asynchronous I/O thread for an AC'97 stream.
1337	* This will do the heavy lifting work for us as soon as it's getting notified by another thread.
1338	*
1339	* @returns VBox status code.
1340	* @param hThreadSelf Thread handle.
1341	* @param pvUser User argument. Must be of type PAC97STREAMTHREADCTX.
1342	*/
1343	static DECLCALLBACK(int) ichac97R3StreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
1344	{
1345	PAC97STREAMTHREADCTX pCtx = (PAC97STREAMTHREADCTX)pvUser;
1346	AssertPtr(pCtx);
1347
1348	PAC97STATE pThis = pCtx->pThis;
1349	AssertPtr(pThis);
1350
1351	PAC97STATER3 pThisCC = pCtx->pThisCC;
1352	AssertPtr(pThisCC);
1353
1354	PAC97STREAM pStream = pCtx->pStream;
1355	AssertPtr(pStream);
1356
1357	PAC97STREAMR3 pStreamCC = pCtx->pStreamCC;
1358	AssertPtr(pStreamCC);
1359
1360	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1361
1362	ASMAtomicXchgBool(&pAIO->fStarted, true);
1363
1364	RTThreadUserSignal(hThreadSelf);
1365
1366	LogFunc(("[SD%RU8] Started\n", pStream->u8SD));
1367
1368	for (;;)
1369	{
1370	Log2Func(("[SD%RU8] Waiting ...\n", pStream->u8SD));
1371
1372	int rc2 = RTSemEventWait(pAIO->Event, RT_INDEFINITE_WAIT);
1373	if (RT_FAILURE(rc2))
1374	break;
1375
1376	if (ASMAtomicReadBool(&pAIO->fShutdown))
1377	break;
1378
1379	rc2 = RTCritSectEnter(&pAIO->CritSect);
1380	if (RT_SUCCESS(rc2))
1381	{
1382	if (!pAIO->fEnabled)
1383	{
1384	RTCritSectLeave(&pAIO->CritSect);
1385	continue;
1386	}
1387
1388	ichac97R3StreamUpdate(pThisCC->pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fInTimer */);
1389
1390	int rc3 = RTCritSectLeave(&pAIO->CritSect);
1391	AssertRC(rc3);
1392	}
1393
1394	AssertRC(rc2);
1395	}
1396
1397	LogFunc(("[SD%RU8] Ended\n", pStream->u8SD));
1398
1399	ASMAtomicXchgBool(&pAIO->fStarted, false);
1400
1401	RTMemFree(pCtx);
1402	pCtx = NULL;
1403
1404	return VINF_SUCCESS;
1405	}
1406
1407	/**
1408	* Creates the async I/O thread for a specific AC'97 audio stream.
1409	*
1410	* @returns VBox status code.
1411	* @param pThis The shared AC'97 state (shared).
1412	* @param pThisCC The shared AC'97 state (ring-3).
1413	* @param pStream AC'97 audio stream to create the async I/O thread for (shared).
1414	* @param pStreamCC AC'97 audio stream to create the async I/O thread for (ring-3).
1415	*/
1416	static int ichac97R3StreamAsyncIOCreate(PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1417	{
1418	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1419
1420	int rc;
1421
1422	if (!ASMAtomicReadBool(&pAIO->fStarted))
1423	{
1424	pAIO->fShutdown = false;
1425	pAIO->fEnabled = true; /* Enabled by default. */
1426
1427	rc = RTSemEventCreate(&pAIO->Event);
1428	if (RT_SUCCESS(rc))
1429	{
1430	rc = RTCritSectInit(&pAIO->CritSect);
1431	if (RT_SUCCESS(rc))
1432	{
1433	/** @todo r=bird:
1434	* Why aren't this code using the PDM threads (PDMDevHlpThreadCreate)?
1435	* They would help you with managing stuff like VM suspending, resuming
1436	* and powering off.
1437	*
1438	* Finally, just create the threads at construction time. */
1439	PAC97STREAMTHREADCTX pCtx = (PAC97STREAMTHREADCTX)RTMemAllocZ(sizeof(AC97STREAMTHREADCTX));
1440	if (pCtx)
1441	{
1442	pCtx->pStream = pStream;
1443	pCtx->pStreamCC = pStreamCC;
1444	pCtx->pThis = pThis;
1445	pCtx->pThisCC = pThisCC;
1446
1447	rc = RTThreadCreateF(&pAIO->Thread, ichac97R3StreamAsyncIOThread, pCtx, 0 /cbStack/, RTTHREADTYPE_IO,
1448	RTTHREADFLAGS_WAITABLE \| RTTHREADFLAGS_COM_MTA, "ac97AIO%RU8", pStreamCC->u8SD);
1449	if (RT_SUCCESS(rc))
1450	rc = RTThreadUserWait(pAIO->Thread, 30 * 1000 /* 30s timeout */);
1451	}
1452	else
1453	rc = VERR_NO_MEMORY;
1454	}
1455	}
1456	}
1457	else
1458	rc = VINF_SUCCESS;
1459
1460	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamCC->u8SD, rc));
1461	return rc;
1462	}
1463
1464	/**
1465	* Lets the stream's async I/O thread know that there is some data to process.
1466	*
1467	* @returns VBox status code.
1468	* @param pStreamCC The AC'97 stream to notify async I/O thread
1469	* for (ring-3).
1470	*/
1471	static int ichac97R3StreamAsyncIONotify(PAC97STREAMR3 pStreamCC)
1472	{
1473	LogFunc(("[SD%RU8]\n", pStreamCC->u8SD));
1474	return RTSemEventSignal(pStreamCC->State.AIO.Event);
1475	}
1476
1477	/**
1478	* Destroys the async I/O thread of a specific AC'97 audio stream.
1479	*
1480	* @returns VBox status code.
1481	* @param pThis The shared AC'97 state.
1482	* @param pStreamCC AC'97 audio stream to destroy the async I/O thread for.
1483	*/
1484	static int ichac97R3StreamAsyncIODestroy(PAC97STATE pThis, PAC97STREAMR3 pStreamR3)
1485	{
1486	RT_NOREF(pThis);
1487
1488	PAC97STREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
1489
1490	if (!ASMAtomicReadBool(&pAIO->fStarted))
1491	return VINF_SUCCESS;
1492
1493	ASMAtomicWriteBool(&pAIO->fShutdown, true);
1494
1495	int rc = ichac97R3StreamAsyncIONotify(pStreamR3);
1496	AssertRC(rc);
1497
1498	int rcThread;
1499	rc = RTThreadWait(pAIO->Thread, 30 * 1000 /* 30s timeout */, &rcThread);
1500	LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
1501
1502	if (RT_SUCCESS(rc))
1503	{
1504	rc = RTCritSectDelete(&pAIO->CritSect);
1505	AssertRC(rc);
1506
1507	rc = RTSemEventDestroy(pAIO->Event);
1508	AssertRC(rc);
1509
1510	pAIO->fStarted = false;
1511	pAIO->fShutdown = false;
1512	pAIO->fEnabled = false;
1513	}
1514
1515	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamR3->u8SD, rc));
1516	return rc;
1517	}
1518
1519	/**
1520	* Locks the async I/O thread of a specific AC'97 audio stream.
1521	*
1522	* @param pStreamCC AC'97 stream to lock async I/O thread for.
1523	*/
1524	static void ichac97R3StreamAsyncIOLock(PAC97STREAMR3 pStreamCC)
1525	{
1526	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1527
1528	if (!ASMAtomicReadBool(&pAIO->fStarted))
1529	return;
1530
1531	int rc2 = RTCritSectEnter(&pAIO->CritSect);
1532	AssertRC(rc2);
1533	}
1534
1535	/**
1536	* Unlocks the async I/O thread of a specific AC'97 audio stream.
1537	*
1538	* @param pStreamCC AC'97 stream to unlock async I/O thread for.
1539	*/
1540	static void ichac97R3StreamAsyncIOUnlock(PAC97STREAMR3 pStreamCC)
1541	{
1542	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1543
1544	if (!ASMAtomicReadBool(&pAIO->fStarted))
1545	return;
1546
1547	int rc2 = RTCritSectLeave(&pAIO->CritSect);
1548	AssertRC(rc2);
1549	}
1550
1551	#if 0 /* Unused */
1552	/**
1553	* Enables (resumes) or disables (pauses) the async I/O thread.
1554	*
1555	* @param pStream AC'97 stream to enable/disable async I/O thread for.
1556	* @param fEnable Whether to enable or disable the I/O thread.
1557	*
1558	* @remarks Does not do locking.
1559	*/
1560	static void ichac97R3StreamAsyncIOEnable(PAC97STREAM pStream, bool fEnable)
1561	{
1562	PAC97STREAMSTATEAIO pAIO = &pStreamCC->State.AIO;
1563	ASMAtomicXchgBool(&pAIO->fEnabled, fEnable);
1564	}
1565	#endif
1566	# endif /* VBOX_WITH_AUDIO_AC97_ASYNC_IO */
1567
1568	# ifdef LOG_ENABLED
1569	static void ichac97R3BDLEDumpAll(PPDMDEVINS pDevIns, uint64_t u64BDLBase, uint16_t cBDLE)
1570	{
1571	LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
1572	if (!u64BDLBase)
1573	return;
1574
1575	uint32_t cbBDLE = 0;
1576	for (uint16_t i = 0; i < cBDLE; i++)
1577	{
1578	AC97BDLE BDLE;
1579	PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase + i * sizeof(AC97BDLE), &BDLE, sizeof(AC97BDLE));
1580
1581	# ifndef RT_LITTLE_ENDIAN
1582	# error "Please adapt the code (audio buffers are little endian)!"
1583	# else
1584	BDLE.addr = RT_H2LE_U32(BDLE.addr & ~3);
1585	BDLE.ctl_len = RT_H2LE_U32(BDLE.ctl_len);
1586	#endif
1587	LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32 [%RU32 bytes], bup:%RTbool, ioc:%RTbool)\n",
1588	i, BDLE.addr,
1589	BDLE.ctl_len & AC97_BD_LEN_MASK,
1590	(BDLE.ctl_len & AC97_BD_LEN_MASK) << 1, /** @todo r=andy Assumes 16bit samples. */
1591	RT_BOOL(BDLE.ctl_len & AC97_BD_BUP),
1592	RT_BOOL(BDLE.ctl_len & AC97_BD_IOC)));
1593
1594	cbBDLE += (BDLE.ctl_len & AC97_BD_LEN_MASK) << 1; /** @todo r=andy Ditto. */
1595	}
1596
1597	LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
1598	}
1599	# endif /* LOG_ENABLED */
1600
1601	/**
1602	* Updates an AC'97 stream by doing its required data transfers.
1603	* The host sink(s) set the overall pace.
1604	*
1605	* This routine is called by both, the synchronous and the asynchronous
1606	* (VBOX_WITH_AUDIO_AC97_ASYNC_IO), implementations.
1607	*
1608	* When running synchronously, the device DMA transfers and the mixer sink
1609	* processing is within the device timer.
1610	*
1611	* When running asynchronously, only the device DMA transfers are done in the
1612	* device timer, whereas the mixer sink processing then is done in the stream's
1613	* own async I/O thread. This thread also will call this function
1614	* (with fInTimer set to @c false).
1615	*
1616	* @param pDevIns The device instance.
1617	* @param pThis The shared AC'97 state.
1618	* @param pThisCC The ring-3 AC'97 state.
1619	* @param pStream The AC'97 stream to update (shared).
1620	* @param pStreamCC The AC'97 stream to update (ring-3).
1621	* @param fInTimer Whether to this function was called from the timer
1622	* context or an asynchronous I/O stream thread (if supported).
1623	*/
1624	static void ichac97R3StreamUpdate(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
1625	PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fInTimer)
1626	{
1627	RT_NOREF(fInTimer);
1628
1629	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
1630	AssertPtr(pSink);
1631
1632	if (!AudioMixerSinkIsActive(pSink)) /* No sink available? Bail out. */
1633	return;
1634
1635	int rc2;
1636
1637	if (pStreamCC->State.Cfg.enmDir == PDMAUDIODIR_OUT) /* Output (SDO). */
1638	{
1639	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1640	if (fInTimer)
1641	# endif
1642	{
1643	const uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1644	if (cbStreamFree)
1645	{
1646	Log3Func(("[SD%RU8] PICB=%zu (%RU64ms), cbFree=%zu (%RU64ms), cbTransferChunk=%zu (%RU64ms)\n",
1647	pStream->u8SD,
1648	(pStream->Regs.picb << 1), PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, pStream->Regs.picb << 1),
1649	cbStreamFree, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, cbStreamFree),
1650	pStreamCC->State.cbTransferChunk, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, pStreamCC->State.cbTransferChunk)));
1651
1652	/* Do the DMA transfer. */
1653	rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC,
1654	RT_MIN(pStreamCC->State.cbTransferChunk, cbStreamFree));
1655	AssertRC(rc2);
1656
1657	pStreamCC->State.tsLastUpdateNs = RTTimeNanoTS();
1658	}
1659	}
1660
1661	Log3Func(("[SD%RU8] fInTimer=%RTbool\n", pStream->u8SD, fInTimer));
1662
1663	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1664	rc2 = ichac97R3StreamAsyncIONotify(pStreamCC);
1665	AssertRC(rc2);
1666	# endif
1667
1668	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1669	if (!fInTimer) /* In async I/O thread */
1670	{
1671	# endif
1672	const uint32_t cbSinkWritable = AudioMixerSinkGetWritable(pSink);
1673	const uint32_t cbStreamReadable = ichac97R3StreamGetUsed(pStreamCC);
1674	const uint32_t cbToReadFromStream = RT_MIN(cbStreamReadable, cbSinkWritable);
1675
1676	Log3Func(("[SD%RU8] cbSinkWritable=%RU32, cbStreamReadable=%RU32\n", pStream->u8SD, cbSinkWritable, cbStreamReadable));
1677
1678	if (cbToReadFromStream)
1679	{
1680	/* Read (guest output) data and write it to the stream's sink. */
1681	rc2 = ichac97R3StreamRead(pStreamCC, pSink, cbToReadFromStream, NULL /* pcbRead */);
1682	AssertRC(rc2);
1683	}
1684	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1685	}
1686	#endif
1687	/* When running synchronously, update the associated sink here.
1688	* Otherwise this will be done in the async I/O thread. */
1689	rc2 = AudioMixerSinkUpdate(pSink);
1690	AssertRC(rc2);
1691	}
1692	else /* Input (SDI). */
1693	{
1694	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1695	if (!fInTimer)
1696	{
1697	# endif
1698	rc2 = AudioMixerSinkUpdate(pSink);
1699	AssertRC(rc2);
1700
1701	/* Is the sink ready to be read (host input data) from? If so, by how much? */
1702	uint32_t cbSinkReadable = AudioMixerSinkGetReadable(pSink);
1703
1704	/* How much (guest input) data is available for writing at the moment for the AC'97 stream? */
1705	uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1706
1707	Log3Func(("[SD%RU8] cbSinkReadable=%RU32, cbStreamFree=%RU32\n", pStream->u8SD, cbSinkReadable, cbStreamFree));
1708
1709	/* Do not read more than the sink can provide at the moment.
1710	* The host sets the overall pace. */
1711	if (cbSinkReadable > cbStreamFree)
1712	cbSinkReadable = cbStreamFree;
1713
1714	if (cbSinkReadable)
1715	{
1716	/* Write (guest input) data to the stream which was read from stream's sink before. */
1717	rc2 = ichac97R3StreamWrite(pStreamCC, pSink, cbSinkReadable, NULL /* pcbWritten */);
1718	AssertRC(rc2);
1719	}
1720	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1721	}
1722	else /* fInTimer */
1723	{
1724	# endif
1725
1726	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1727	const uint64_t tsNowNs = RTTimeNanoTS();
1728	if (tsNowNs - pStreamCC->State.tsLastUpdateNs >= pStreamCC->State.Cfg.Device.cMsSchedulingHint * RT_NS_1MS)
1729	{
1730	rc2 = ichac97R3StreamAsyncIONotify(pStreamCC);
1731	AssertRC(rc2);
1732
1733	pStreamCC->State.tsLastUpdateNs = tsNowNs;
1734	}
1735	# endif
1736
1737	const uint32_t cbStreamUsed = ichac97R3StreamGetUsed(pStreamCC);
1738	if (cbStreamUsed)
1739	{
1740	/* When running synchronously, do the DMA data transfers here.
1741	* Otherwise this will be done in the stream's async I/O thread. */
1742	rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC, cbStreamUsed);
1743	AssertRC(rc2);
1744	}
1745	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
1746	}
1747	# endif
1748	}
1749	}
1750
1751	#endif /* IN_RING3 */
1752
1753	/**
1754	* Sets a AC'97 mixer control to a specific value.
1755	*
1756	* @returns VBox status code.
1757	* @param pThis The shared AC'97 state.
1758	* @param uMixerIdx Mixer control to set value for.
1759	* @param uVal Value to set.
1760	*/
1761	static void ichac97MixerSet(PAC97STATE pThis, uint8_t uMixerIdx, uint16_t uVal)
1762	{
1763	AssertMsgReturnVoid(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1764	("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)));
1765
1766	LogRel2(("AC97: Setting mixer index #%RU8 to %RU16 (%RU8 %RU8)\n",
1767	uMixerIdx, uVal, RT_HI_U8(uVal), RT_LO_U8(uVal)));
1768
1769	pThis->mixer_data[uMixerIdx + 0] = RT_LO_U8(uVal);
1770	pThis->mixer_data[uMixerIdx + 1] = RT_HI_U8(uVal);
1771	}
1772
1773	/**
1774	* Gets a value from a specific AC'97 mixer control.
1775	*
1776	* @returns Retrieved mixer control value.
1777	* @param pThis The shared AC'97 state.
1778	* @param uMixerIdx Mixer control to get value for.
1779	*/
1780	static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t uMixerIdx)
1781	{
1782	AssertMsgReturn(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1783	("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)),
1784	UINT16_MAX);
1785	return RT_MAKE_U16(pThis->mixer_data[uMixerIdx + 0], pThis->mixer_data[uMixerIdx + 1]);
1786	}
1787
1788	#ifdef IN_RING3
1789
1790	/**
1791	* Retrieves a specific driver stream of a AC'97 driver.
1792	*
1793	* @returns Pointer to driver stream if found, or NULL if not found.
1794	* @param pDrv Driver to retrieve driver stream for.
1795	* @param enmDir Stream direction to retrieve.
1796	* @param dstSrc Stream destination / source to retrieve.
1797	*/
1798	static PAC97DRIVERSTREAM ichac97R3MixerGetDrvStream(PAC97DRIVER pDrv, PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc)
1799	{
1800	PAC97DRIVERSTREAM pDrvStream = NULL;
1801
1802	if (enmDir == PDMAUDIODIR_IN)
1803	{
1804	LogFunc(("enmRecSource=%d\n", dstSrc.enmSrc));
1805
1806	switch (dstSrc.enmSrc)
1807	{
1808	case PDMAUDIORECSRC_LINE:
1809	pDrvStream = &pDrv->LineIn;
1810	break;
1811	case PDMAUDIORECSRC_MIC:
1812	pDrvStream = &pDrv->MicIn;
1813	break;
1814	default:
1815	AssertFailed();
1816	break;
1817	}
1818	}
1819	else if (enmDir == PDMAUDIODIR_OUT)
1820	{
1821	LogFunc(("enmPlaybackDest=%d\n", dstSrc.enmDst));
1822
1823	switch (dstSrc.enmDst)
1824	{
1825	case PDMAUDIOPLAYBACKDST_FRONT:
1826	pDrvStream = &pDrv->Out;
1827	break;
1828	default:
1829	AssertFailed();
1830	break;
1831	}
1832	}
1833	else
1834	AssertFailed();
1835
1836	return pDrvStream;
1837	}
1838
1839	/**
1840	* Adds a driver stream to a specific mixer sink.
1841	*
1842	* @returns VBox status code.
1843	* @param pDevIns The device instance.
1844	* @param pMixSink Mixer sink to add driver stream to.
1845	* @param pCfg Stream configuration to use.
1846	* @param pDrv Driver stream to add.
1847	*/
1848	static int ichac97R3MixerAddDrvStream(PPDMDEVINS pDevIns, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PAC97DRIVER pDrv)
1849	{
1850	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1851
1852	PPDMAUDIOSTREAMCFG pStreamCfg = PDMAudioStrmCfgDup(pCfg);
1853	if (!pStreamCfg)
1854	return VERR_NO_MEMORY;
1855
1856	AssertCompile(sizeof(pStreamCfg->szName) == sizeof(pCfg->szName));
1857	RTStrCopy(pStreamCfg->szName, sizeof(pStreamCfg->szName), pCfg->szName);
1858
1859	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
1860
1861	int rc;
1862
1863	PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, pStreamCfg->enmDir, pStreamCfg->u);
1864	if (pDrvStream)
1865	{
1866	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
1867
1868	PAUDMIXSTREAM pMixStrm;
1869	rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, pDevIns, &pMixStrm);
1870	LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1871	if (RT_SUCCESS(rc))
1872	{
1873	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
1874	LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1875	if (RT_SUCCESS(rc))
1876	{
1877	/* If this is an input stream, always set the latest (added) stream
1878	* as the recording source. */
1879	/** @todo Make the recording source dynamic (CFGM?). */
1880	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
1881	{
1882	PDMAUDIOBACKENDCFG Cfg;
1883	rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
1884	if (RT_SUCCESS(rc))
1885	{
1886	if (Cfg.cMaxStreamsIn) /* At least one input source available? */
1887	{
1888	rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
1889	LogFlowFunc(("LUN#%RU8: Recording source for '%s' -> '%s', rc=%Rrc\n",
1890	pDrv->uLUN, pStreamCfg->szName, Cfg.szName, rc));
1891
1892	if (RT_SUCCESS(rc))
1893	LogRel2(("AC97: Set recording source for '%s' to '%s'\n", pStreamCfg->szName, Cfg.szName));
1894	}
1895	else
1896	LogRel(("AC97: Backend '%s' currently is not offering any recording source for '%s'\n",
1897	Cfg.szName, pStreamCfg->szName));
1898	}
1899	else if (RT_FAILURE(rc))
1900	LogFunc(("LUN#%RU8: Unable to retrieve backend configuratio for '%s', rc=%Rrc\n",
1901	pDrv->uLUN, pStreamCfg->szName, rc));
1902	}
1903	if (RT_FAILURE(rc))
1904	AudioMixerSinkRemoveStream(pMixSink, pMixStrm);
1905	}
1906	if (RT_FAILURE(rc))
1907	AudioMixerStreamDestroy(pMixStrm, pDevIns);
1908	}
1909
1910	if (RT_SUCCESS(rc))
1911	pDrvStream->pMixStrm = pMixStrm;
1912	}
1913	else
1914	rc = VERR_INVALID_PARAMETER;
1915
1916	PDMAudioStrmCfgFree(pStreamCfg);
1917
1918	LogFlowFuncLeaveRC(rc);
1919	return rc;
1920	}
1921
1922	/**
1923	* Adds all current driver streams to a specific mixer sink.
1924	*
1925	* @returns VBox status code.
1926	* @param pDevIns The device instance.
1927	* @param pThisCC The ring-3 AC'97 state.
1928	* @param pMixSink Mixer sink to add stream to.
1929	* @param pCfg Stream configuration to use.
1930	*/
1931	static int ichac97R3MixerAddDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
1932	{
1933	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1934
1935	if (!AudioHlpStreamCfgIsValid(pCfg))
1936	return VERR_INVALID_PARAMETER;
1937
1938	int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
1939	if (RT_FAILURE(rc))
1940	return rc;
1941
1942	PAC97DRIVER pDrv;
1943	RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
1944	{
1945	int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pMixSink, pCfg, pDrv);
1946	if (RT_FAILURE(rc2))
1947	LogFunc(("Attaching stream failed with %Rrc\n", rc2));
1948
1949	/* Do not pass failure to rc here, as there might be drivers which aren't
1950	* configured / ready yet. */
1951	}
1952
1953	LogFlowFuncLeaveRC(rc);
1954	return rc;
1955	}
1956
1957	/**
1958	* Adds a specific AC'97 driver to the driver chain.
1959	*
1960	* @returns VBox status code.
1961	* @param pDevIns The device instance.
1962	* @param pThisCC The ring-3 AC'97 device state.
1963	* @param pDrv The AC'97 driver to add.
1964	*/
1965	static int ichac97R3MixerAddDrv(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
1966	{
1967	int rc = VINF_SUCCESS;
1968
1969	if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg))
1970	rc = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkLineIn,
1971	&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg, pDrv);
1972
1973	if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg))
1974	{
1975	int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkOut,
1976	&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg, pDrv);
1977	if (RT_SUCCESS(rc))
1978	rc = rc2;
1979	}
1980
1981	if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg))
1982	{
1983	int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkMicIn,
1984	&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg, pDrv);
1985	if (RT_SUCCESS(rc))
1986	rc = rc2;
1987	}
1988
1989	return rc;
1990	}
1991
1992	/**
1993	* Removes a specific AC'97 driver from the driver chain and destroys its
1994	* associated streams.
1995	*
1996	* @param pDevIns The device instance.
1997	* @param pThisCC The ring-3 AC'97 device state.
1998	* @param pDrv AC'97 driver to remove.
1999	*/
2000	static void ichac97R3MixerRemoveDrv(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
2001	{
2002	if (pDrv->MicIn.pMixStrm)
2003	{
2004	if (AudioMixerSinkGetRecordingSource(pThisCC->pSinkMicIn) == pDrv->MicIn.pMixStrm)
2005	AudioMixerSinkSetRecordingSource(pThisCC->pSinkMicIn, NULL);
2006
2007	AudioMixerSinkRemoveStream(pThisCC->pSinkMicIn, pDrv->MicIn.pMixStrm);
2008	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm, pDevIns);
2009	pDrv->MicIn.pMixStrm = NULL;
2010	}
2011
2012	if (pDrv->LineIn.pMixStrm)
2013	{
2014	if (AudioMixerSinkGetRecordingSource(pThisCC->pSinkLineIn) == pDrv->LineIn.pMixStrm)
2015	AudioMixerSinkSetRecordingSource(pThisCC->pSinkLineIn, NULL);
2016
2017	AudioMixerSinkRemoveStream(pThisCC->pSinkLineIn, pDrv->LineIn.pMixStrm);
2018	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm, pDevIns);
2019	pDrv->LineIn.pMixStrm = NULL;
2020	}
2021
2022	if (pDrv->Out.pMixStrm)
2023	{
2024	AudioMixerSinkRemoveStream(pThisCC->pSinkOut, pDrv->Out.pMixStrm);
2025	AudioMixerStreamDestroy(pDrv->Out.pMixStrm, pDevIns);
2026	pDrv->Out.pMixStrm = NULL;
2027	}
2028
2029	RTListNodeRemove(&pDrv->Node);
2030	}
2031
2032	/**
2033	* Removes a driver stream from a specific mixer sink.
2034	*
2035	* @param pDevIns The device instance.
2036	* @param pMixSink Mixer sink to remove audio streams from.
2037	* @param enmDir Stream direction to remove.
2038	* @param dstSrc Stream destination / source to remove.
2039	* @param pDrv Driver stream to remove.
2040	*/
2041	static void ichac97R3MixerRemoveDrvStream(PPDMDEVINS pDevIns, PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir,
2042	PDMAUDIODSTSRCUNION dstSrc, PAC97DRIVER pDrv)
2043	{
2044	PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, enmDir, dstSrc);
2045	if (pDrvStream)
2046	{
2047	if (pDrvStream->pMixStrm)
2048	{
2049	AudioMixerSinkRemoveStream(pMixSink, pDrvStream->pMixStrm);
2050
2051	AudioMixerStreamDestroy(pDrvStream->pMixStrm, pDevIns);
2052	pDrvStream->pMixStrm = NULL;
2053	}
2054	}
2055	}
2056
2057	/**
2058	* Removes all driver streams from a specific mixer sink.
2059	*
2060	* @param pDevIns The device instance.
2061	* @param pThisCC The ring-3 AC'97 state.
2062	* @param pMixSink Mixer sink to remove audio streams from.
2063	* @param enmDir Stream direction to remove.
2064	* @param dstSrc Stream destination / source to remove.
2065	*/
2066	static void ichac97R3MixerRemoveDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
2067	PDMAUDIODIR enmDir, PDMAUDIODSTSRCUNION dstSrc)
2068	{
2069	AssertPtrReturnVoid(pMixSink);
2070
2071	PAC97DRIVER pDrv;
2072	RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
2073	{
2074	ichac97R3MixerRemoveDrvStream(pDevIns, pMixSink, enmDir, dstSrc, pDrv);
2075	}
2076	}
2077
2078	/**
2079	* Calculates and returns the ticks for a specified amount of bytes.
2080	*
2081	* @returns Calculated ticks
2082	* @param pDevIns The device instance.
2083	* @param pStream AC'97 stream to calculate ticks for (shared).
2084	* @param pStreamCC AC'97 stream to calculate ticks for (ring-3).
2085	* @param cbBytes Bytes to calculate ticks for.
2086	*/
2087	static uint64_t ichac97R3StreamTransferCalcNext(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint32_t cbBytes)
2088	{
2089	if (!cbBytes)
2090	return 0;
2091
2092	const uint64_t usBytes = PDMAudioPropsBytesToMicro(&pStreamCC->State.Cfg.Props, cbBytes);
2093	const uint64_t cTransferTicks = PDMDevHlpTimerFromMicro(pDevIns, pStream->hTimer, usBytes);
2094
2095	Log3Func(("[SD%RU8] Timer %uHz, cbBytes=%RU32 -> usBytes=%RU64, cTransferTicks=%RU64\n",
2096	pStream->u8SD, pStreamCC->State.uTimerHz, cbBytes, usBytes, cTransferTicks));
2097
2098	return cTransferTicks;
2099	}
2100
2101	/**
2102	* Updates the next transfer based on a specific amount of bytes.
2103	*
2104	* @param pDevIns The device instance.
2105	* @param pStream The AC'97 stream to update (shared).
2106	* @param pStreamCC The AC'97 stream to update (ring-3).
2107	* @param cbBytes Bytes to update next transfer for.
2108	*/
2109	static void ichac97R3StreamTransferUpdate(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint32_t cbBytes)
2110	{
2111	if (!cbBytes)
2112	return;
2113
2114	/* Calculate the bytes we need to transfer to / from the stream's DMA per iteration.
2115	* This is bound to the device's Hz rate and thus to the (virtual) timing the device expects. */
2116	pStreamCC->State.cbTransferChunk = cbBytes;
2117
2118	/* Update the transfer ticks. */
2119	pStreamCC->State.cTransferTicks = ichac97R3StreamTransferCalcNext(pDevIns, pStream, pStreamCC,
2120	pStreamCC->State.cbTransferChunk);
2121	Assert(pStreamCC->State.cTransferTicks); /* Paranoia. */
2122	}
2123
2124	/**
2125	* Opens an AC'97 stream with its current mixer settings.
2126	*
2127	* This will open an AC'97 stream with 2 (stereo) channels, 16-bit samples and
2128	* the last set sample rate in the AC'97 mixer for this stream.
2129	*
2130	* @returns VBox status code.
2131	* @param pDevIns The device instance.
2132	* @param pThis The shared AC'97 device state (shared).
2133	* @param pThisCC The shared AC'97 device state (ring-3).
2134	* @param pStream The AC'97 stream to open (shared).
2135	* @param pStreamCC The AC'97 stream to open (ring-3).
2136	* @param fForce Whether to force re-opening the stream or not.
2137	* Otherwise re-opening only will happen if the PCM properties have changed.
2138	*/
2139	static int ichac97R3StreamOpen(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
2140	PAC97STREAMR3 pStreamCC, bool fForce)
2141	{
2142	int rc = VINF_SUCCESS;
2143	PAUDMIXSINK pMixSink;
2144	PDMAUDIOSTREAMCFG Cfg;
2145	RT_ZERO(Cfg);
2146	switch (pStream->u8SD)
2147	{
2148	case AC97SOUNDSOURCE_PI_INDEX:
2149	{
2150	PDMAudioPropsInit(&Cfg.Props, 2 /16-bit/, true /signed/, 2 /stereo/,
2151	ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate));
2152	Cfg.enmDir = PDMAUDIODIR_IN;
2153	Cfg.u.enmSrc = PDMAUDIORECSRC_LINE;
2154	Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2155	RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Line-In");
2156
2157	pMixSink = pThisCC->pSinkLineIn;
2158	break;
2159	}
2160
2161	case AC97SOUNDSOURCE_MC_INDEX:
2162	{
2163	PDMAudioPropsInit(&Cfg.Props, 2 /16-bit/, true /signed/, 2 /stereo/,
2164	ichac97MixerGet(pThis, AC97_MIC_ADC_Rate));
2165	Cfg.enmDir = PDMAUDIODIR_IN;
2166	Cfg.u.enmSrc = PDMAUDIORECSRC_MIC;
2167	Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2168	RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Mic-In");
2169
2170	pMixSink = pThisCC->pSinkMicIn;
2171	break;
2172	}
2173
2174	case AC97SOUNDSOURCE_PO_INDEX:
2175	{
2176	PDMAudioPropsInit(&Cfg.Props, 2 /16-bit/, true /signed/, 2 /stereo/,
2177	ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate));
2178	Cfg.enmDir = PDMAUDIODIR_OUT;
2179	Cfg.u.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
2180	Cfg.enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
2181	RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Output");
2182
2183	pMixSink = pThisCC->pSinkOut;
2184	break;
2185	}
2186
2187	default:
2188	rc = VERR_NOT_SUPPORTED;
2189	pMixSink = NULL;
2190	break;
2191	}
2192
2193	if (RT_SUCCESS(rc))
2194	{
2195	/* Only (re-)create the stream (and driver chain) if we really have to.
2196	* Otherwise avoid this and just reuse it, as this costs performance. */
2197	if ( !PDMAudioStrmCfgMatchesProps(&Cfg, &pStreamCC->State.Cfg.Props)
2198	\|\| fForce)
2199	{
2200	LogRel2(("AC97: (Re-)Opening stream '%s' (%RU32Hz, %RU8 channels, %s%RU8)\n", Cfg.szName, Cfg.Props.uHz,
2201	PDMAudioPropsChannels(&Cfg.Props), Cfg.Props.fSigned ? "S" : "U", PDMAudioPropsSampleBits(&Cfg.Props)));
2202
2203	LogFlowFunc(("[SD%RU8] uHz=%RU32\n", pStream->u8SD, Cfg.Props.uHz));
2204
2205	if (Cfg.Props.uHz)
2206	{
2207	Assert(Cfg.enmDir != PDMAUDIODIR_UNKNOWN);
2208
2209	/*
2210	* Set the stream's timer Hz rate, based on the PCM properties Hz rate.
2211	*/
2212	if (pThis->uTimerHz == AC97_TIMER_HZ_DEFAULT) /* Make sure that we don't have any custom Hz rate set we want to enforce */
2213	{
2214	if (Cfg.Props.uHz > 44100) /* E.g. 48000 Hz. */
2215	pStreamCC->State.uTimerHz = 200;
2216	else /* Just take the global Hz rate otherwise. */
2217	pStreamCC->State.uTimerHz = pThis->uTimerHz;
2218	}
2219	else
2220	pStreamCC->State.uTimerHz = pThis->uTimerHz;
2221
2222	/* Set scheduling hint (if available). */
2223	if (pStreamCC->State.uTimerHz)
2224	Cfg.Device.cMsSchedulingHint = 1000 /* ms */ / pStreamCC->State.uTimerHz;
2225
2226	if (pStreamCC->State.pCircBuf)
2227	{
2228	RTCircBufDestroy(pStreamCC->State.pCircBuf);
2229	pStreamCC->State.pCircBuf = NULL;
2230	}
2231
2232	rc = RTCircBufCreate(&pStreamCC->State.pCircBuf, PDMAudioPropsMilliToBytes(&Cfg.Props, 100 /ms/)); /** @todo Make this configurable. */
2233	if (RT_SUCCESS(rc))
2234	{
2235	ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pMixSink, Cfg.enmDir, Cfg.u);
2236
2237	rc = ichac97R3MixerAddDrvStreams(pDevIns, pThisCC, pMixSink, &Cfg);
2238	if (RT_SUCCESS(rc))
2239	rc = PDMAudioStrmCfgCopy(&pStreamCC->State.Cfg, &Cfg);
2240	}
2241	}
2242	}
2243	else
2244	LogFlowFunc(("[SD%RU8] Skipping (re-)creation\n", pStream->u8SD));
2245	}
2246
2247	LogFlowFunc(("[SD%RU8] rc=%Rrc\n", pStream->u8SD, rc));
2248	return rc;
2249	}
2250
2251	/**
2252	* Closes an AC'97 stream.
2253	*
2254	* @returns VBox status code.
2255	* @param pStream The AC'97 stream to close (shared).
2256	*/
2257	static int ichac97R3StreamClose(PAC97STREAM pStream)
2258	{
2259	RT_NOREF(pStream);
2260	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2261	return VINF_SUCCESS;
2262	}
2263
2264	/**
2265	* Re-opens (that is, closes and opens again) an AC'97 stream on the backend
2266	* side with the current AC'97 mixer settings for this stream.
2267	*
2268	* @returns VBox status code.
2269	* @param pDevIns The device instance.
2270	* @param pThis The shared AC'97 device state.
2271	* @param pThisCC The ring-3 AC'97 device state.
2272	* @param pStream The AC'97 stream to re-open (shared).
2273	* @param pStreamCC The AC'97 stream to re-open (ring-3).
2274	* @param fForce Whether to force re-opening the stream or not.
2275	* Otherwise re-opening only will happen if the PCM properties have changed.
2276	*/
2277	static int ichac97R3StreamReOpen(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
2278	PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2279	{
2280	LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2281	Assert(pStream->u8SD == pStreamCC->u8SD);
2282	Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2283	Assert(pStreamCC - &pThisCC->aStreams[0] == pStream->u8SD);
2284
2285	int rc = ichac97R3StreamClose(pStream);
2286	if (RT_SUCCESS(rc))
2287	rc = ichac97R3StreamOpen(pDevIns, pThis, pThisCC, pStream, pStreamCC, fForce);
2288
2289	return rc;
2290	}
2291
2292	/**
2293	* Locks an AC'97 stream for serialized access.
2294	*
2295	* @returns VBox status code.
2296	* @param pStreamCC The AC'97 stream to lock (ring-3).
2297	*/
2298	static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC)
2299	{
2300	int rc2 = RTCritSectEnter(&pStreamCC->State.CritSect);
2301	AssertRC(rc2);
2302	}
2303
2304	/**
2305	* Unlocks a formerly locked AC'97 stream.
2306	*
2307	* @returns VBox status code.
2308	* @param pStreamCC The AC'97 stream to unlock (ring-3).
2309	*/
2310	static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC)
2311	{
2312	int rc2 = RTCritSectLeave(&pStreamCC->State.CritSect);
2313	AssertRC(rc2);
2314	}
2315
2316	/**
2317	* Retrieves the available size of (buffered) audio data (in bytes) of a given AC'97 stream.
2318	*
2319	* @returns Available data (in bytes).
2320	* @param pStreamCC The AC'97 stream to retrieve size for (ring-3).
2321	*/
2322	static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC)
2323	{
2324	if (!pStreamCC->State.pCircBuf)
2325	return 0;
2326
2327	return (uint32_t)RTCircBufUsed(pStreamCC->State.pCircBuf);
2328	}
2329
2330	/**
2331	* Retrieves the free size of audio data (in bytes) of a given AC'97 stream.
2332	*
2333	* @returns Free data (in bytes).
2334	* @param pStreamCC AC'97 stream to retrieve size for (ring-3).
2335	*/
2336	static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC)
2337	{
2338	if (!pStreamCC->State.pCircBuf)
2339	return 0;
2340
2341	return (uint32_t)RTCircBufFree(pStreamCC->State.pCircBuf);
2342	}
2343
2344	/**
2345	* Sets the volume of a specific AC'97 mixer control.
2346	*
2347	* This currently only supports attenuation -- gain support is currently not implemented.
2348	*
2349	* @returns VBox status code.
2350	* @param pThis The shared AC'97 state.
2351	* @param pThisCC The ring-3 AC'97 state.
2352	* @param index AC'97 mixer index to set volume for.
2353	* @param enmMixerCtl Corresponding audio mixer sink.
2354	* @param uVal Volume value to set.
2355	*/
2356	static int ichac97R3MixerSetVolume(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2357	{
2358	/*
2359	* From AC'97 SoundMax Codec AD1981A/AD1981B:
2360	* "Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the
2361	* D5 or D13 bits are set to 1, their respective lower five volume bits are automatically
2362	* set to 1 by the Codec logic. On readback, all lower 5 bits will read ones whenever
2363	* these bits are set to 1."
2364	*
2365	* Linux ALSA depends on this behavior to detect that only 5 bits are used for volume
2366	* control and the optional 6th bit is not used. Note that this logic only applies to the
2367	* master volume controls.
2368	*/
2369	if (index == AC97_Master_Volume_Mute \|\| index == AC97_Headphone_Volume_Mute \|\| index == AC97_Master_Volume_Mono_Mute)
2370	{
2371	if (uVal & RT_BIT(5)) /* D5 bit set? */
2372	uVal \|= RT_BIT(4) \| RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1) \| RT_BIT(0);
2373	if (uVal & RT_BIT(13)) /* D13 bit set? */
2374	uVal \|= RT_BIT(12) \| RT_BIT(11) \| RT_BIT(10) \| RT_BIT(9) \| RT_BIT(8);
2375	}
2376
2377	const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2378	uint8_t uCtlAttLeft = (uVal >> 8) & AC97_BARS_VOL_MASK;
2379	uint8_t uCtlAttRight = uVal & AC97_BARS_VOL_MASK;
2380
2381	/* For the master and headphone volume, 0 corresponds to 0dB attenuation. For the other
2382	* volume controls, 0 means 12dB gain and 8 means unity gain.
2383	*/
2384	if (index != AC97_Master_Volume_Mute && index != AC97_Headphone_Volume_Mute)
2385	{
2386	# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2387	/* NB: Currently there is no gain support, only attenuation. */
2388	uCtlAttLeft = uCtlAttLeft < 8 ? 0 : uCtlAttLeft - 8;
2389	uCtlAttRight = uCtlAttRight < 8 ? 0 : uCtlAttRight - 8;
2390	# endif
2391	}
2392	Assert(uCtlAttLeft <= 255 / AC97_DB_FACTOR);
2393	Assert(uCtlAttRight <= 255 / AC97_DB_FACTOR);
2394
2395	LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2396	LogFunc(("uCtlAttLeft=%RU8, uCtlAttRight=%RU8 ", uCtlAttLeft, uCtlAttRight));
2397
2398	/*
2399	* For AC'97 volume controls, each additional step means -1.5dB attenuation with
2400	* zero being maximum. In contrast, we're internally using 255 (PDMAUDIO_VOLUME_MAX)
2401	* steps, each -0.375dB, where 0 corresponds to -96dB and 255 corresponds to 0dB.
2402	*/
2403	uint8_t lVol = PDMAUDIO_VOLUME_MAX - uCtlAttLeft * AC97_DB_FACTOR;
2404	uint8_t rVol = PDMAUDIO_VOLUME_MAX - uCtlAttRight * AC97_DB_FACTOR;
2405
2406	Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2407
2408	int rc = VINF_SUCCESS;
2409
2410	if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2411	{
2412	PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2413	PAUDMIXSINK pSink = NULL;
2414
2415	switch (enmMixerCtl)
2416	{
2417	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2418	rc = AudioMixerSetMasterVolume(pThisCC->pMixer, &Vol);
2419	break;
2420
2421	case PDMAUDIOMIXERCTL_FRONT:
2422	pSink = pThisCC->pSinkOut;
2423	break;
2424
2425	case PDMAUDIOMIXERCTL_MIC_IN:
2426	case PDMAUDIOMIXERCTL_LINE_IN:
2427	/* These are recognized but do nothing. */
2428	break;
2429
2430	default:
2431	AssertFailed();
2432	rc = VERR_NOT_SUPPORTED;
2433	break;
2434	}
2435
2436	if (pSink)
2437	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2438	}
2439
2440	ichac97MixerSet(pThis, index, uVal);
2441
2442	if (RT_FAILURE(rc))
2443	LogFlowFunc(("Failed with %Rrc\n", rc));
2444
2445	return rc;
2446	}
2447
2448	/**
2449	* Sets the gain of a specific AC'97 recording control.
2450	*
2451	* NB: gain support is currently not implemented in PDM audio.
2452	*
2453	* @returns VBox status code.
2454	* @param pThis The shared AC'97 state.
2455	* @param pThisCC The ring-3 AC'97 state.
2456	* @param index AC'97 mixer index to set volume for.
2457	* @param enmMixerCtl Corresponding audio mixer sink.
2458	* @param uVal Volume value to set.
2459	*/
2460	static int ichac97R3MixerSetGain(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2461	{
2462	/*
2463	* For AC'97 recording controls, each additional step means +1.5dB gain with
2464	* zero being 0dB gain and 15 being +22.5dB gain.
2465	*/
2466	const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2467	uint8_t uCtlGainLeft = (uVal >> 8) & AC97_BARS_GAIN_MASK;
2468	uint8_t uCtlGainRight = uVal & AC97_BARS_GAIN_MASK;
2469
2470	Assert(uCtlGainLeft <= 255 / AC97_DB_FACTOR);
2471	Assert(uCtlGainRight <= 255 / AC97_DB_FACTOR);
2472
2473	LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2474	LogFunc(("uCtlGainLeft=%RU8, uCtlGainRight=%RU8 ", uCtlGainLeft, uCtlGainRight));
2475
2476	uint8_t lVol = PDMAUDIO_VOLUME_MAX + uCtlGainLeft * AC97_DB_FACTOR;
2477	uint8_t rVol = PDMAUDIO_VOLUME_MAX + uCtlGainRight * AC97_DB_FACTOR;
2478
2479	/* We do not currently support gain. Since AC'97 does not support attenuation
2480	* for the recording input, the best we can do is set the maximum volume.
2481	*/
2482	# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2483	/* NB: Currently there is no gain support, only attenuation. Since AC'97 does not
2484	* support attenuation for the recording inputs, the best we can do is set the
2485	* maximum volume.
2486	*/
2487	lVol = rVol = PDMAUDIO_VOLUME_MAX;
2488	# endif
2489
2490	Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2491
2492	int rc = VINF_SUCCESS;
2493
2494	if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2495	{
2496	PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2497	PAUDMIXSINK pSink = NULL;
2498
2499	switch (enmMixerCtl)
2500	{
2501	case PDMAUDIOMIXERCTL_MIC_IN:
2502	pSink = pThisCC->pSinkMicIn;
2503	break;
2504
2505	case PDMAUDIOMIXERCTL_LINE_IN:
2506	pSink = pThisCC->pSinkLineIn;
2507	break;
2508
2509	default:
2510	AssertFailed();
2511	rc = VERR_NOT_SUPPORTED;
2512	break;
2513	}
2514
2515	if (pSink) {
2516	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2517	/* There is only one AC'97 recording gain control. If line in
2518	* is changed, also update the microphone. If the optional dedicated
2519	* microphone is changed, only change that.
2520	* NB: The codecs we support do not have the dedicated microphone control.
2521	*/
2522	if ((pSink == pThisCC->pSinkLineIn) && pThisCC->pSinkMicIn)
2523	rc = AudioMixerSinkSetVolume(pSink, &Vol);
2524	}
2525	}
2526
2527	ichac97MixerSet(pThis, index, uVal);
2528
2529	if (RT_FAILURE(rc))
2530	LogFlowFunc(("Failed with %Rrc\n", rc));
2531
2532	return rc;
2533	}
2534
2535	/**
2536	* Converts an AC'97 recording source index to a PDM audio recording source.
2537	*
2538	* @returns PDM audio recording source.
2539	* @param uIdx AC'97 index to convert.
2540	*/
2541	static PDMAUDIORECSRC ichac97R3IdxToRecSource(uint8_t uIdx)
2542	{
2543	switch (uIdx)
2544	{
2545	case AC97_REC_MIC: return PDMAUDIORECSRC_MIC;
2546	case AC97_REC_CD: return PDMAUDIORECSRC_CD;
2547	case AC97_REC_VIDEO: return PDMAUDIORECSRC_VIDEO;
2548	case AC97_REC_AUX: return PDMAUDIORECSRC_AUX;
2549	case AC97_REC_LINE_IN: return PDMAUDIORECSRC_LINE;
2550	case AC97_REC_PHONE: return PDMAUDIORECSRC_PHONE;
2551	default:
2552	break;
2553	}
2554
2555	LogFlowFunc(("Unknown record source %d, using MIC\n", uIdx));
2556	return PDMAUDIORECSRC_MIC;
2557	}
2558
2559	/**
2560	* Converts a PDM audio recording source to an AC'97 recording source index.
2561	*
2562	* @returns AC'97 recording source index.
2563	* @param enmRecSrc PDM audio recording source to convert.
2564	*/
2565	static uint8_t ichac97R3RecSourceToIdx(PDMAUDIORECSRC enmRecSrc)
2566	{
2567	switch (enmRecSrc)
2568	{
2569	case PDMAUDIORECSRC_MIC: return AC97_REC_MIC;
2570	case PDMAUDIORECSRC_CD: return AC97_REC_CD;
2571	case PDMAUDIORECSRC_VIDEO: return AC97_REC_VIDEO;
2572	case PDMAUDIORECSRC_AUX: return AC97_REC_AUX;
2573	case PDMAUDIORECSRC_LINE: return AC97_REC_LINE_IN;
2574	case PDMAUDIORECSRC_PHONE: return AC97_REC_PHONE;
2575	/* no default */
2576	case PDMAUDIORECSRC_UNKNOWN:
2577	case PDMAUDIORECSRC_END:
2578	case PDMAUDIORECSRC_32BIT_HACK:
2579	break;
2580	}
2581
2582	LogFlowFunc(("Unknown audio recording source %d using MIC\n", enmRecSrc));
2583	return AC97_REC_MIC;
2584	}
2585
2586	/**
2587	* Returns the audio direction of a specified stream descriptor.
2588	*
2589	* @return Audio direction.
2590	*/
2591	DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD)
2592	{
2593	switch (uSD)
2594	{
2595	case AC97SOUNDSOURCE_PI_INDEX: return PDMAUDIODIR_IN;
2596	case AC97SOUNDSOURCE_PO_INDEX: return PDMAUDIODIR_OUT;
2597	case AC97SOUNDSOURCE_MC_INDEX: return PDMAUDIODIR_IN;
2598	}
2599
2600	AssertFailed();
2601	return PDMAUDIODIR_UNKNOWN;
2602	}
2603
2604	#endif /* IN_RING3 */
2605
2606	#ifdef IN_RING3
2607
2608	/**
2609	* Performs an AC'97 mixer record select to switch to a different recording
2610	* source.
2611	*
2612	* @param pThis The shared AC'97 state.
2613	* @param val AC'97 recording source index to set.
2614	*/
2615	static void ichac97R3MixerRecordSelect(PAC97STATE pThis, uint32_t val)
2616	{
2617	uint8_t rs = val & AC97_REC_MASK;
2618	uint8_t ls = (val >> 8) & AC97_REC_MASK;
2619
2620	const PDMAUDIORECSRC ars = ichac97R3IdxToRecSource(rs);
2621	const PDMAUDIORECSRC als = ichac97R3IdxToRecSource(ls);
2622
2623	rs = ichac97R3RecSourceToIdx(ars);
2624	ls = ichac97R3RecSourceToIdx(als);
2625
2626	LogRel(("AC97: Record select to left=%s, right=%s\n", PDMAudioRecSrcGetName(ars), PDMAudioRecSrcGetName(als)));
2627
2628	ichac97MixerSet(pThis, AC97_Record_Select, rs \| (ls << 8));
2629	}
2630
2631	/**
2632	* Resets the AC'97 mixer.
2633	*
2634	* @returns VBox status code.
2635	* @param pThis The shared AC'97 state.
2636	* @param pThisCC The ring-3 AC'97 state.
2637	*/
2638	static int ichac97R3MixerReset(PAC97STATE pThis, PAC97STATER3 pThisCC)
2639	{
2640	LogFlowFuncEnter();
2641
2642	RT_ZERO(pThis->mixer_data);
2643
2644	/* Note: Make sure to reset all registers first before bailing out on error. */
2645
2646	ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
2647	ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
2648	ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
2649
2650	ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
2651	ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
2652	ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
2653	ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
2654	ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
2655	ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
2656	ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
2657	ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
2658
2659	/* Configure Extended Audio ID (EAID) + Control & Status (EACS) registers. */
2660	const uint16_t fEAID = AC97_EAID_REV1 \| AC97_EACS_VRA \| AC97_EACS_VRM; /* Our hardware is AC'97 rev2.3 compliant. */
2661	const uint16_t fEACS = AC97_EACS_VRA \| AC97_EACS_VRM; /* Variable Rate PCM Audio (VRA) + Mic-In (VRM) capable. */
2662
2663	LogRel(("AC97: Mixer reset (EAID=0x%x, EACS=0x%x)\n", fEAID, fEACS));
2664
2665	ichac97MixerSet(pThis, AC97_Extended_Audio_ID, fEAID);
2666	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, fEACS);
2667	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2668	ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2669	ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2670	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2671	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2672
2673	if (pThis->enmCodecModel == AC97CODEC_AD1980)
2674	{
2675	/* Analog Devices 1980 (AD1980) */
2676	ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
2677	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2678	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
2679	ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
2680	}
2681	else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
2682	{
2683	/* Analog Devices 1981B (AD1981B) */
2684	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2685	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
2686	}
2687	else
2688	{
2689	/* Sigmatel 9700 (STAC9700) */
2690	ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
2691	ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
2692	}
2693	ichac97R3MixerRecordSelect(pThis, 0);
2694
2695	/* The default value is 8000h, which corresponds to 0 dB attenuation with mute on. */
2696	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER, 0x8000);
2697
2698	/* The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on.*/
2699	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT, 0x8808);
2700	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
2701	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8008);
2702
2703	/* The default for record controls is 0 dB gain with mute on. */
2704	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8000);
2705	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8000);
2706
2707	return VINF_SUCCESS;
2708	}
2709
2710	# if 0 /* Unused */
2711	static void ichac97R3WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
2712	{
2713	LogFlowFunc(("cbElapsed=%RU32\n", cbElapsed));
2714
2715	if (!(pThis->bup_flag & BUP_SET))
2716	{
2717	if (pThis->bup_flag & BUP_LAST)
2718	{
2719	unsigned int i;
2720	uint32_t p = (uint32_t)pThis->silence;
2721	for (i = 0; i < sizeof(pThis->silence) / 4; i++) /** @todo r=andy Assumes 16-bit samples, stereo. */
2722	*p++ = pThis->last_samp;
2723	}
2724	else
2725	RT_ZERO(pThis->silence);
2726
2727	pThis->bup_flag \|= BUP_SET;
2728	}
2729
2730	while (cbElapsed)
2731	{
2732	uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
2733	uint32_t cbWrittenToStream;
2734
2735	int rc2 = AudioMixerSinkWrite(pThisCC->pSinkOut, AUDMIXOP_COPY,
2736	pThis->silence, cbToWrite, &cbWrittenToStream);
2737	if (RT_SUCCESS(rc2))
2738	{
2739	if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2740	LogFlowFunc(("Warning: Only written %RU32 / %RU32 bytes, expect lags\n", cbWrittenToStream, cbToWrite));
2741	}
2742
2743	/* Always report all data as being written;
2744	* backends who were not able to catch up have to deal with it themselves. */
2745	Assert(cbElapsed >= cbToWrite);
2746	cbElapsed -= cbToWrite;
2747	}
2748	}
2749	# endif /* Unused */
2750
2751	/**
2752	* @callback_method_impl{FNTMTIMERDEV,
2753	* Timer callback which handles the audio data transfers on a periodic basis.}
2754	*/
2755	static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
2756	{
2757	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2758	STAM_PROFILE_START(&pThis->StatTimer, a);
2759	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
2760	PAC97STREAM pStream = (PAC97STREAM)pvUser;
2761	PAC97STREAMR3 pStreamCC = &RT_SAFE_SUBSCRIPT8(pThisCC->aStreams, pStream->u8SD);
2762	Assert(hTimer == pStream->hTimer); RT_NOREF(hTimer);
2763
2764	Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2765	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2766	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStream->hTimer));
2767
2768	ichac97R3StreamUpdate(pDevIns, pThis, pThisCC, pStream, pStreamCC, true /* fInTimer */);
2769
2770	PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
2771	if (pSink && AudioMixerSinkIsActive(pSink))
2772	{
2773	ichac97R3StreamTransferUpdate(pDevIns, pStream, pStreamCC, pStream->Regs.picb << 1); /** @todo r=andy Assumes 16-bit samples. */
2774	ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
2775	}
2776
2777	STAM_PROFILE_STOP(&pThis->StatTimer, a);
2778	}
2779
2780
2781	/**
2782	* Sets the virtual device timer to a new expiration time.
2783	*
2784	* @param pDevIns The device instance.
2785	* @param pStream AC'97 stream to set timer for.
2786	* @param cTicksToDeadline The number of ticks to the new deadline.
2787	*
2788	* @remarks This used to be more complicated a long time ago...
2789	*/
2790	DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline)
2791	{
2792	int rc = PDMDevHlpTimerSetRelative(pDevIns, pStream->hTimer, cTicksToDeadline, NULL /pu64Now/);
2793	AssertRC(rc);
2794	}
2795
2796
2797	/**
2798	* Transfers data of an AC'97 stream according to its usage (input / output).
2799	*
2800	* For an SDO (output) stream this means reading DMA data from the device to
2801	* the AC'97 stream's internal FIFO buffer.
2802	*
2803	* For an SDI (input) stream this is reading audio data from the AC'97 stream's
2804	* internal FIFO buffer and writing it as DMA data to the device.
2805	*
2806	* @returns VBox status code.
2807	* @param pDevIns The device instance.
2808	* @param pThis The shared AC'97 state.
2809	* @param pStream The AC'97 stream to update (shared).
2810	* @param pStreamCC The AC'97 stream to update (ring-3).
2811	* @param cbToProcessMax Maximum of data (in bytes) to process.
2812	*/
2813	static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
2814	PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax)
2815	{
2816	if (!cbToProcessMax)
2817	return VINF_SUCCESS;
2818
2819	#ifdef VBOX_STRICT
2820	const unsigned cbFrame = PDMAudioPropsBytesPerFrame(&pStreamCC->State.Cfg.Props);
2821	#endif
2822
2823	/* Make sure to only process an integer number of audio frames. */
2824	Assert(cbToProcessMax % cbFrame == 0);
2825
2826	ichac97R3StreamLock(pStreamCC);
2827
2828	PAC97BMREGS pRegs = &pStream->Regs;
2829
2830	if (pRegs->sr & AC97_SR_DCH) /* Controller halted? */
2831	{
2832	if (pRegs->cr & AC97_CR_RPBM) /* Bus master operation starts. */
2833	{
2834	switch (pStream->u8SD)
2835	{
2836	case AC97SOUNDSOURCE_PO_INDEX:
2837	/ichac97R3WriteBUP(pThis, cbToProcess);/
2838	break;
2839
2840	default:
2841	break;
2842	}
2843	}
2844
2845	ichac97R3StreamUnlock(pStreamCC);
2846	return VINF_SUCCESS;
2847	}
2848
2849	/* BCIS flag still set? Skip iteration. */
2850	if (pRegs->sr & AC97_SR_BCIS)
2851	{
2852	Log3Func(("[SD%RU8] BCIS set\n", pStream->u8SD));
2853
2854	ichac97R3StreamUnlock(pStreamCC);
2855	return VINF_SUCCESS;
2856	}
2857
2858	uint32_t cbLeft = RT_MIN((uint32_t)(pRegs->picb << 1), cbToProcessMax); /** @todo r=andy Assumes 16bit samples. */
2859	uint32_t cbProcessedTotal = 0;
2860
2861	PRTCIRCBUF pCircBuf = pStreamCC->State.pCircBuf;
2862	AssertPtr(pCircBuf);
2863
2864	int rc = VINF_SUCCESS;
2865
2866	Log3Func(("[SD%RU8] cbToProcessMax=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcessMax, cbLeft));
2867
2868	while (cbLeft)
2869	{
2870	if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
2871	{
2872	Log3Func(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
2873	pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
2874	if (pRegs->civ == pRegs->lvi)
2875	{
2876	pRegs->sr \|= AC97_SR_DCH; /** @todo r=andy Also set CELV? */
2877	pThis->bup_flag = 0;
2878
2879	rc = VINF_EOF;
2880	break;
2881	}
2882
2883	pRegs->sr &= ~AC97_SR_CELV;
2884	pRegs->civ = pRegs->piv;
2885	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2886
2887	ichac97R3StreamFetchBDLE(pDevIns, pStream);
2888	continue;
2889	}
2890
2891	uint32_t cbChunk = cbLeft;
2892
2893	switch (pStream->u8SD)
2894	{
2895	case AC97SOUNDSOURCE_PO_INDEX: /* Output */
2896	{
2897	void *pvDst;
2898	size_t cbDst;
2899
2900	RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvDst, &cbDst);
2901
2902	if (cbDst)
2903	{
2904	int rc2 = PDMDevHlpPCIPhysRead(pDevIns, pRegs->bd.addr, (uint8_t *)pvDst, cbDst);
2905	AssertRC(rc2);
2906
2907	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2908	{ /* likely */ }
2909	else
2910	AudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvDst, cbDst, 0 /* fFlags */);
2911	}
2912
2913	RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
2914
2915	cbChunk = (uint32_t)cbDst; /* Update the current chunk size to what really has been written. */
2916	break;
2917	}
2918
2919	case AC97SOUNDSOURCE_PI_INDEX: /* Input */
2920	case AC97SOUNDSOURCE_MC_INDEX: /* Input */
2921	{
2922	void *pvSrc;
2923	size_t cbSrc;
2924
2925	RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvSrc, &cbSrc);
2926
2927	if (cbSrc)
2928	{
2929	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, pRegs->bd.addr, (uint8_t *)pvSrc, cbSrc);
2930	AssertRC(rc2);
2931
2932	if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2933	{ /* likely */ }
2934	else
2935	AudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvSrc, cbSrc, 0 /* fFlags */);
2936	}
2937
2938	RTCircBufReleaseReadBlock(pCircBuf, cbSrc);
2939
2940	cbChunk = (uint32_t)cbSrc; /* Update the current chunk size to what really has been read. */
2941	break;
2942	}
2943
2944	default:
2945	AssertMsgFailed(("Stream #%RU8 not supported\n", pStream->u8SD));
2946	rc = VERR_NOT_SUPPORTED;
2947	break;
2948	}
2949
2950	if (RT_FAILURE(rc))
2951	break;
2952
2953	if (cbChunk)
2954	{
2955	cbProcessedTotal += cbChunk;
2956	Assert(cbProcessedTotal <= cbToProcessMax);
2957	Assert(cbLeft >= cbChunk);
2958	cbLeft -= cbChunk;
2959	Assert((cbChunk & 1) == 0); /* Else the following shift won't work */
2960
2961	pRegs->picb -= (cbChunk >> 1); /** @todo r=andy Assumes 16bit samples. */
2962	pRegs->bd.addr += cbChunk;
2963	}
2964
2965	LogFlowFunc(("[SD%RU8] cbChunk=%RU32, cbLeft=%RU32, cbTotal=%RU32, rc=%Rrc\n",
2966	pStream->u8SD, cbChunk, cbLeft, cbProcessedTotal, rc));
2967
2968	if (!pRegs->picb)
2969	{
2970	uint32_t new_sr = pRegs->sr & ~AC97_SR_CELV;
2971
2972	if (pRegs->bd.ctl_len & AC97_BD_IOC)
2973	{
2974	new_sr \|= AC97_SR_BCIS;
2975	}
2976
2977	if (pRegs->civ == pRegs->lvi)
2978	{
2979	/* Did we run out of data? */
2980	LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pRegs->civ, pRegs->lvi));
2981
2982	new_sr \|= AC97_SR_LVBCI \| AC97_SR_DCH \| AC97_SR_CELV;
2983	pThis->bup_flag = (pRegs->bd.ctl_len & AC97_BD_BUP) ? BUP_LAST : 0;
2984
2985	rc = VINF_EOF;
2986	}
2987	else
2988	{
2989	pRegs->civ = pRegs->piv;
2990	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2991	ichac97R3StreamFetchBDLE(pDevIns, pStream);
2992	}
2993
2994	ichac97StreamUpdateSR(pDevIns, pThis, pStream, new_sr);
2995	}
2996
2997	if (/* All data processed? */
2998	rc == VINF_EOF
2999	/* ... or an error occurred? */
3000	\|\| RT_FAILURE(rc))
3001	{
3002	break;
3003	}
3004	}
3005
3006	ichac97R3StreamUnlock(pStreamCC);
3007
3008	LogFlowFuncLeaveRC(rc);
3009	return rc;
3010	}
3011
3012	#endif /* IN_RING3 */
3013
3014
3015	/**
3016	* @callback_method_impl{FNIOMIOPORTNEWIN}
3017	*/
3018	static DECLCALLBACK(VBOXSTRICTRC)
3019	ichac97IoPortNabmRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3020	{
3021	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3022	RT_NOREF(pvUser);
3023
3024	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3025
3026	/* Get the index of the NABMBAR port. */
3027	if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
3028	&& offPort != AC97_GLOB_CNT)
3029	{
3030	PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
3031	PAC97BMREGS pRegs = &pStream->Regs;
3032
3033	switch (cb)
3034	{
3035	case 1:
3036	switch (offPort & AC97_NABM_OFF_MASK)
3037	{
3038	case AC97_NABM_OFF_CIV:
3039	/* Current Index Value Register */
3040	*pu32 = pRegs->civ;
3041	Log3Func(("CIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3042	break;
3043	case AC97_NABM_OFF_LVI:
3044	/* Last Valid Index Register */
3045	*pu32 = pRegs->lvi;
3046	Log3Func(("LVI[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3047	break;
3048	case AC97_NABM_OFF_PIV:
3049	/* Prefetched Index Value Register */
3050	*pu32 = pRegs->piv;
3051	Log3Func(("PIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3052	break;
3053	case AC97_NABM_OFF_CR:
3054	/* Control Register */
3055	*pu32 = pRegs->cr;
3056	Log3Func(("CR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3057	break;
3058	case AC97_NABM_OFF_SR:
3059	/* Status Register (lower part) */
3060	*pu32 = RT_LO_U8(pRegs->sr);
3061	Log3Func(("SRb[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3062	break;
3063	default:
3064	*pu32 = UINT32_MAX;
3065	LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
3066	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3067	break;
3068	}
3069	break;
3070
3071	case 2:
3072	switch (offPort & AC97_NABM_OFF_MASK)
3073	{
3074	case AC97_NABM_OFF_SR:
3075	/* Status Register */
3076	*pu32 = pRegs->sr;
3077	Log3Func(("SR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3078	break;
3079	case AC97_NABM_OFF_PICB:
3080	/* Position in Current Buffer */
3081	*pu32 = pRegs->picb;
3082	Log3Func(("PICB[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3083	break;
3084	default:
3085	*pu32 = UINT32_MAX;
3086	LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
3087	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3088	break;
3089	}
3090	break;
3091
3092	case 4:
3093	switch (offPort & AC97_NABM_OFF_MASK)
3094	{
3095	case AC97_NABM_OFF_BDBAR:
3096	/* Buffer Descriptor Base Address Register */
3097	*pu32 = pRegs->bdbar;
3098	Log3Func(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
3099	break;
3100	case AC97_NABM_OFF_CIV:
3101	/* 32-bit access: Current Index Value Register +
3102	* Last Valid Index Register +
3103	* Status Register */
3104	pu32 = pRegs->civ \| (pRegs->lvi << 8) \| (pRegs->sr << 16); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
3105	Log3Func(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
3106	AC97_PORT2IDX(offPort), pRegs->civ, pRegs->lvi, pRegs->sr));
3107	break;
3108	case AC97_NABM_OFF_PICB:
3109	/* 32-bit access: Position in Current Buffer Register +
3110	* Prefetched Index Value Register +
3111	* Control Register */
3112	pu32 = pRegs->picb \| (pRegs->piv << 16) \| (pRegs->cr << 24); /* @todo r=andy Use RT_MAKE_U32_FROM_U8. */
3113	Log3Func(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
3114	AC97_PORT2IDX(offPort), *pu32, pRegs->picb, pRegs->piv, pRegs->cr));
3115	break;
3116
3117	default:
3118	*pu32 = UINT32_MAX;
3119	LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
3120	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3121	break;
3122	}
3123	break;
3124
3125	default:
3126	DEVAC97_UNLOCK(pDevIns, pThis);
3127	AssertFailed();
3128	return VERR_IOM_IOPORT_UNUSED;
3129	}
3130	}
3131	else
3132	{
3133	switch (cb)
3134	{
3135	case 1:
3136	switch (offPort)
3137	{
3138	case AC97_CAS:
3139	/* Codec Access Semaphore Register */
3140	Log3Func(("CAS %d\n", pThis->cas));
3141	*pu32 = pThis->cas;
3142	pThis->cas = 1;
3143	break;
3144	default:
3145	*pu32 = UINT32_MAX;
3146	LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
3147	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3148	break;
3149	}
3150	break;
3151
3152	case 2:
3153	*pu32 = UINT32_MAX;
3154	LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
3155	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3156	break;
3157
3158	case 4:
3159	switch (offPort)
3160	{
3161	case AC97_GLOB_CNT:
3162	/* Global Control */
3163	*pu32 = pThis->glob_cnt;
3164	Log3Func(("glob_cnt -> %#x\n", *pu32));
3165	break;
3166	case AC97_GLOB_STA:
3167	/* Global Status */
3168	*pu32 = pThis->glob_sta \| AC97_GS_S0CR;
3169	Log3Func(("glob_sta -> %#x\n", *pu32));
3170	break;
3171	default:
3172	*pu32 = UINT32_MAX;
3173	LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
3174	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
3175	break;
3176	}
3177	break;
3178
3179	default:
3180	DEVAC97_UNLOCK(pDevIns, pThis);
3181	AssertFailed();
3182	return VERR_IOM_IOPORT_UNUSED;
3183	}
3184	}
3185
3186	DEVAC97_UNLOCK(pDevIns, pThis);
3187	return VINF_SUCCESS;
3188	}
3189
3190	/**
3191	* @callback_method_impl{FNIOMIOPORTNEWOUT}
3192	*/
3193	static DECLCALLBACK(VBOXSTRICTRC)
3194	ichac97IoPortNabmWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3195	{
3196	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3197	#ifdef IN_RING3
3198	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3199	#endif
3200	RT_NOREF(pvUser);
3201
3202	VBOXSTRICTRC rc = VINF_SUCCESS;
3203	if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
3204	&& offPort != AC97_GLOB_CNT)
3205	{
3206	#ifdef IN_RING3
3207	PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[AC97_PORT2IDX(offPort)];
3208	#endif
3209	PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
3210	PAC97BMREGS pRegs = &pStream->Regs;
3211
3212	DEVAC97_LOCK_BOTH_RETURN(pDevIns, pThis, pStream, VINF_IOM_R3_IOPORT_WRITE);
3213	switch (cb)
3214	{
3215	case 1:
3216	switch (offPort & AC97_NABM_OFF_MASK)
3217	{
3218	/*
3219	* Last Valid Index.
3220	*/
3221	case AC97_NABM_OFF_LVI:
3222	if ( (pRegs->cr & AC97_CR_RPBM)
3223	&& (pRegs->sr & AC97_SR_DCH))
3224	{
3225	#ifdef IN_RING3
3226	pRegs->sr &= ~(AC97_SR_DCH \| AC97_SR_CELV);
3227	pRegs->civ = pRegs->piv;
3228	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3229	#else
3230	rc = VINF_IOM_R3_IOPORT_WRITE;
3231	#endif
3232	}
3233	pRegs->lvi = u32 % AC97_MAX_BDLE;
3234	Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32));
3235	break;
3236
3237	/*
3238	* Control Registers.
3239	*/
3240	case AC97_NABM_OFF_CR:
3241	#ifdef IN_RING3
3242	Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32, pRegs->cr));
3243	if (u32 & AC97_CR_RR) /* Busmaster reset. */
3244	{
3245	Log3Func(("[SD%RU8] Reset\n", pStream->u8SD));
3246
3247	/* Make sure that Run/Pause Bus Master bit (RPBM) is cleared (0). */
3248	Assert((pRegs->cr & AC97_CR_RPBM) == 0);
3249
3250	ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3251	ichac97R3StreamReset(pThis, pStream, pStreamCC);
3252
3253	ichac97StreamUpdateSR(pDevIns, pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */
3254	}
3255	else
3256	{
3257	pRegs->cr = u32 & AC97_CR_VALID_MASK;
3258
3259	if (!(pRegs->cr & AC97_CR_RPBM))
3260	{
3261	Log3Func(("[SD%RU8] Disable\n", pStream->u8SD));
3262
3263	ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3264
3265	pRegs->sr \|= AC97_SR_DCH;
3266	}
3267	else
3268	{
3269	Log3Func(("[SD%RU8] Enable\n", pStream->u8SD));
3270
3271	pRegs->civ = pRegs->piv;
3272	pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
3273
3274	pRegs->sr &= ~AC97_SR_DCH;
3275
3276	/* Fetch the initial BDLE descriptor. */
3277	ichac97R3StreamFetchBDLE(pDevIns, pStream);
3278	# ifdef LOG_ENABLED
3279	ichac97R3BDLEDumpAll(pDevIns, pStream->Regs.bdbar, pStream->Regs.lvi + 1);
3280	# endif
3281	ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, true /* fEnable */);
3282
3283	/* Arm the timer for this stream. */
3284	/** @todo r=bird: This function returns bool, not VBox status! */
3285	ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3286	}
3287	}
3288	#else /* !IN_RING3 */
3289	rc = VINF_IOM_R3_IOPORT_WRITE;
3290	#endif
3291	break;
3292
3293	/*
3294	* Status Registers.
3295	*/
3296	case AC97_NABM_OFF_SR:
3297	ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3298	break;
3299
3300	default:
3301	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3302	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3303	break;
3304	}
3305	break;
3306
3307	case 2:
3308	switch (offPort & AC97_NABM_OFF_MASK)
3309	{
3310	case AC97_NABM_OFF_SR:
3311	ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3312	break;
3313	default:
3314	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3315	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3316	break;
3317	}
3318	break;
3319
3320	case 4:
3321	switch (offPort & AC97_NABM_OFF_MASK)
3322	{
3323	case AC97_NABM_OFF_BDBAR:
3324	/* Buffer Descriptor list Base Address Register */
3325	pRegs->bdbar = u32 & ~3;
3326	Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(offPort), u32, pRegs->bdbar));
3327	break;
3328	default:
3329	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3330	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3331	break;
3332	}
3333	break;
3334
3335	default:
3336	AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3337	break;
3338	}
3339	DEVAC97_UNLOCK_BOTH(pDevIns, pThis, pStream);
3340	}
3341	else
3342	{
3343	switch (cb)
3344	{
3345	case 1:
3346	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3347	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3348	break;
3349
3350	case 2:
3351	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3352	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3353	break;
3354
3355	case 4:
3356	switch (offPort)
3357	{
3358	case AC97_GLOB_CNT:
3359	/* Global Control */
3360	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3361	if (u32 & AC97_GC_WR)
3362	ichac97WarmReset(pThis);
3363	if (u32 & AC97_GC_CR)
3364	ichac97ColdReset(pThis);
3365	if (!(u32 & (AC97_GC_WR \| AC97_GC_CR)))
3366	pThis->glob_cnt = u32 & AC97_GC_VALID_MASK;
3367	Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt));
3368	DEVAC97_UNLOCK(pDevIns, pThis);
3369	break;
3370	case AC97_GLOB_STA:
3371	/* Global Status */
3372	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3373	pThis->glob_sta &= ~(u32 & AC97_GS_WCLEAR_MASK);
3374	pThis->glob_sta \|= (u32 & ~(AC97_GS_WCLEAR_MASK \| AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK;
3375	Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta));
3376	DEVAC97_UNLOCK(pDevIns, pThis);
3377	break;
3378	default:
3379	LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3380	STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3381	break;
3382	}
3383	break;
3384
3385	default:
3386	AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3387	break;
3388	}
3389	}
3390
3391	return rc;
3392	}
3393
3394	/**
3395	* @callback_method_impl{FNIOMIOPORTNEWIN}
3396	*/
3397	static DECLCALLBACK(VBOXSTRICTRC)
3398	ichac97IoPortNamRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3399	{
3400	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3401	RT_NOREF(pvUser);
3402	Assert(offPort < 256);
3403
3404	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3405
3406	VBOXSTRICTRC rc = VINF_SUCCESS;
3407	switch (cb)
3408	{
3409	case 1:
3410	{
3411	LogRel2(("AC97: Warning: Unimplemented read (1 byte) offPort=%#x\n", offPort));
3412	pThis->cas = 0;
3413	*pu32 = UINT32_MAX;
3414	break;
3415	}
3416
3417	case 2:
3418	{
3419	pThis->cas = 0;
3420	*pu32 = ichac97MixerGet(pThis, offPort);
3421	break;
3422	}
3423
3424	case 4:
3425	{
3426	LogRel2(("AC97: Warning: Unimplemented read (4 bytes) offPort=%#x\n", offPort));
3427	pThis->cas = 0;
3428	*pu32 = UINT32_MAX;
3429	break;
3430	}
3431
3432	default:
3433	{
3434	AssertFailed();
3435	rc = VERR_IOM_IOPORT_UNUSED;
3436	}
3437	}
3438
3439	DEVAC97_UNLOCK(pDevIns, pThis);
3440	return rc;
3441	}
3442
3443	/**
3444	* @callback_method_impl{FNIOMIOPORTNEWOUT}
3445	*/
3446	static DECLCALLBACK(VBOXSTRICTRC)
3447	ichac97IoPortNamWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3448	{
3449	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3450	#ifdef IN_RING3
3451	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3452	#endif
3453	RT_NOREF(pvUser);
3454
3455	DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3456
3457	VBOXSTRICTRC rc = VINF_SUCCESS;
3458	switch (cb)
3459	{
3460	case 1:
3461	{
3462	LogRel2(("AC97: Warning: Unimplemented NAMWrite (1 byte) offPort=%#x <- %#x\n", offPort, u32));
3463	pThis->cas = 0;
3464	break;
3465	}
3466
3467	case 2:
3468	{
3469	pThis->cas = 0;
3470	switch (offPort)
3471	{
3472	case AC97_Reset:
3473	#ifdef IN_RING3
3474	ichac97R3Reset(pDevIns);
3475	#else
3476	rc = VINF_IOM_R3_IOPORT_WRITE;
3477	#endif
3478	break;
3479	case AC97_Powerdown_Ctrl_Stat:
3480	u32 &= ~0xf;
3481	u32 \|= ichac97MixerGet(pThis, offPort) & 0xf;
3482	ichac97MixerSet(pThis, offPort, u32);
3483	break;
3484	case AC97_Master_Volume_Mute:
3485	if (pThis->enmCodecModel == AC97CODEC_AD1980)
3486	{
3487	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_LOSEL)
3488	break; /* Register controls surround (rear), do nothing. */
3489	}
3490	#ifdef IN_RING3
3491	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3492	#else
3493	rc = VINF_IOM_R3_IOPORT_WRITE;
3494	#endif
3495	break;
3496	case AC97_Headphone_Volume_Mute:
3497	if (pThis->enmCodecModel == AC97CODEC_AD1980)
3498	{
3499	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3500	{
3501	/* Register controls PCM (front) outputs. */
3502	#ifdef IN_RING3
3503	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3504	#else
3505	rc = VINF_IOM_R3_IOPORT_WRITE;
3506	#endif
3507	}
3508	}
3509	break;
3510	case AC97_PCM_Out_Volume_Mute:
3511	#ifdef IN_RING3
3512	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_FRONT, u32);
3513	#else
3514	rc = VINF_IOM_R3_IOPORT_WRITE;
3515	#endif
3516	break;
3517	case AC97_Line_In_Volume_Mute:
3518	#ifdef IN_RING3
3519	ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3520	#else
3521	rc = VINF_IOM_R3_IOPORT_WRITE;
3522	#endif
3523	break;
3524	case AC97_Record_Select:
3525	#ifdef IN_RING3
3526	ichac97R3MixerRecordSelect(pThis, u32);
3527	#else
3528	rc = VINF_IOM_R3_IOPORT_WRITE;
3529	#endif
3530	break;
3531	case AC97_Record_Gain_Mute:
3532	#ifdef IN_RING3
3533	/* Newer Ubuntu guests rely on that when controlling gain and muting
3534	* the recording (capturing) levels. */
3535	ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3536	#else
3537	rc = VINF_IOM_R3_IOPORT_WRITE;
3538	#endif
3539	break;
3540	case AC97_Record_Gain_Mic_Mute:
3541	#ifdef IN_RING3
3542	/* Ditto; see note above. */
3543	ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_MIC_IN, u32);
3544	#else
3545	rc = VINF_IOM_R3_IOPORT_WRITE;
3546	#endif
3547	break;
3548	case AC97_Vendor_ID1:
3549	case AC97_Vendor_ID2:
3550	LogFunc(("Attempt to write vendor ID to %#x\n", u32));
3551	break;
3552	case AC97_Extended_Audio_ID:
3553	LogFunc(("Attempt to write extended audio ID to %#x\n", u32));
3554	break;
3555	case AC97_Extended_Audio_Ctrl_Stat:
3556	#ifdef IN_RING3
3557	/*
3558	* Handle VRA bits.
3559	*/
3560	if (!(u32 & AC97_EACS_VRA)) /* Check if VRA bit is not set. */
3561	{
3562	ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 0xbb80); /* Set default (48000 Hz). */
3563	ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3564	&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3565
3566	ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3567	ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3568	&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3569	}
3570	else
3571	LogRel2(("AC97: Variable rate audio (VRA) is not supported\n"));
3572
3573	/*
3574	* Handle VRM bits.
3575	*/
3576	if (!(u32 & AC97_EACS_VRM)) /* Check if VRM bit is not set. */
3577	{
3578	ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3579	ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3580	&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3581	}
3582	else
3583	LogRel2(("AC97: Variable rate microphone audio (VRM) is not supported\n"));
3584
3585	LogRel2(("AC97: Setting extended audio control to %#x\n", u32));
3586	ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32);
3587	#else /* !IN_RING3 */
3588	rc = VINF_IOM_R3_IOPORT_WRITE;
3589	#endif
3590	break;
3591	case AC97_PCM_Front_DAC_Rate: /* Output slots 3, 4, 6. */
3592	#ifdef IN_RING3
3593	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3594	{
3595	LogRel2(("AC97: Setting front DAC rate to 0x%x\n", u32));
3596	ichac97MixerSet(pThis, offPort, u32);
3597	ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3598	&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3599	}
3600	else
3601	LogRel2(("AC97: Setting front DAC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3602	#else
3603	rc = VINF_IOM_R3_IOPORT_WRITE;
3604	#endif
3605	break;
3606	case AC97_MIC_ADC_Rate: /* Input slot 6. */
3607	#ifdef IN_RING3
3608	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRM)
3609	{
3610	LogRel2(("AC97: Setting microphone ADC rate to 0x%x\n", u32));
3611	ichac97MixerSet(pThis, offPort, u32);
3612	ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3613	&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3614	}
3615	else
3616	LogRel2(("AC97: Setting microphone ADC rate (0x%x) when VRM is not set is forbidden, ignoring\n", u32));
3617	#else
3618	rc = VINF_IOM_R3_IOPORT_WRITE;
3619	#endif
3620	break;
3621	case AC97_PCM_LR_ADC_Rate: /* Input slots 3, 4. */
3622	#ifdef IN_RING3
3623	if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3624	{
3625	LogRel2(("AC97: Setting line-in ADC rate to 0x%x\n", u32));
3626	ichac97MixerSet(pThis, offPort, u32);
3627	ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3628	&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3629	}
3630	else
3631	LogRel2(("AC97: Setting line-in ADC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3632	#else
3633	rc = VINF_IOM_R3_IOPORT_WRITE;
3634	#endif
3635	break;
3636	default:
3637	LogRel2(("AC97: Warning: Unimplemented NAMWrite (2 bytes) offPort=%#x <- %#x\n", offPort, u32));
3638	ichac97MixerSet(pThis, offPort, u32);
3639	break;
3640	}
3641	break;
3642	}
3643
3644	case 4:
3645	{
3646	LogRel2(("AC97: Warning: Unimplemented 4 byte NAMWrite: offPort=%#x <- %#x\n", offPort, u32));
3647	pThis->cas = 0;
3648	break;
3649	}
3650
3651	default:
3652	AssertMsgFailed(("Unhandled NAMWrite offPort=%#x, cb=%u u32=%#x\n", offPort, cb, u32));
3653	break;
3654	}
3655
3656	DEVAC97_UNLOCK(pDevIns, pThis);
3657	return rc;
3658	}
3659
3660	#ifdef IN_RING3
3661
3662	/**
3663	* Saves (serializes) an AC'97 stream using SSM.
3664	*
3665	* @param pDevIns Device instance.
3666	* @param pSSM Saved state manager (SSM) handle to use.
3667	* @param pStream AC'97 stream to save.
3668	*/
3669	static void ichac97R3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3670	{
3671	PAC97BMREGS pRegs = &pStream->Regs;
3672	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3673
3674	pHlp->pfnSSMPutU32(pSSM, pRegs->bdbar);
3675	pHlp->pfnSSMPutU8( pSSM, pRegs->civ);
3676	pHlp->pfnSSMPutU8( pSSM, pRegs->lvi);
3677	pHlp->pfnSSMPutU16(pSSM, pRegs->sr);
3678	pHlp->pfnSSMPutU16(pSSM, pRegs->picb);
3679	pHlp->pfnSSMPutU8( pSSM, pRegs->piv);
3680	pHlp->pfnSSMPutU8( pSSM, pRegs->cr);
3681	pHlp->pfnSSMPutS32(pSSM, pRegs->bd_valid);
3682	pHlp->pfnSSMPutU32(pSSM, pRegs->bd.addr);
3683	pHlp->pfnSSMPutU32(pSSM, pRegs->bd.ctl_len);
3684	}
3685
3686	/**
3687	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3688	*/
3689	static DECLCALLBACK(int) ichac97R3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3690	{
3691	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3692	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3693	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3694	LogFlowFuncEnter();
3695
3696	pHlp->pfnSSMPutU32(pSSM, pThis->glob_cnt);
3697	pHlp->pfnSSMPutU32(pSSM, pThis->glob_sta);
3698	pHlp->pfnSSMPutU32(pSSM, pThis->cas);
3699
3700	/*
3701	* The order that the streams are saved here is fixed, so don't change.
3702	*/
3703	/** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
3704	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3705	ichac97R3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3706
3707	pHlp->pfnSSMPutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3708
3709	/* The stream order is against fixed and set in stone. */
3710	uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3711	afActiveStrms[AC97SOUNDSOURCE_PI_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX]);
3712	afActiveStrms[AC97SOUNDSOURCE_PO_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX]);
3713	afActiveStrms[AC97SOUNDSOURCE_MC_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX]);
3714	AssertCompile(RT_ELEMENTS(afActiveStrms) == 3);
3715	pHlp->pfnSSMPutMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3716
3717	LogFlowFuncLeaveRC(VINF_SUCCESS);
3718	return VINF_SUCCESS;
3719	}
3720
3721	/**
3722	* Loads an AC'97 stream from SSM.
3723	*
3724	* @returns VBox status code.
3725	* @param pDevIns The device instance.
3726	* @param pSSM Saved state manager (SSM) handle to use.
3727	* @param pStream AC'97 stream to load.
3728	*/
3729	static int ichac97R3LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3730	{
3731	PAC97BMREGS pRegs = &pStream->Regs;
3732	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3733
3734	pHlp->pfnSSMGetU32(pSSM, &pRegs->bdbar);
3735	pHlp->pfnSSMGetU8( pSSM, &pRegs->civ);
3736	pHlp->pfnSSMGetU8( pSSM, &pRegs->lvi);
3737	pHlp->pfnSSMGetU16(pSSM, &pRegs->sr);
3738	pHlp->pfnSSMGetU16(pSSM, &pRegs->picb);
3739	pHlp->pfnSSMGetU8( pSSM, &pRegs->piv);
3740	pHlp->pfnSSMGetU8( pSSM, &pRegs->cr);
3741	pHlp->pfnSSMGetS32(pSSM, &pRegs->bd_valid);
3742	pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.addr);
3743	return pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.ctl_len);
3744	}
3745
3746	/**
3747	* @callback_method_impl{FNSSMDEVLOADEXEC}
3748	*/
3749	static DECLCALLBACK(int) ichac97R3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3750	{
3751	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3752	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3753	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3754
3755	LogRel2(("ichac97LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3756
3757	AssertMsgReturn (uVersion == AC97_SAVED_STATE_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3758	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3759
3760	pHlp->pfnSSMGetU32(pSSM, &pThis->glob_cnt);
3761	pHlp->pfnSSMGetU32(pSSM, &pThis->glob_sta);
3762	pHlp->pfnSSMGetU32(pSSM, &pThis->cas);
3763
3764	/*
3765	* The order the streams are loaded here is critical (defined by
3766	* AC97SOUNDSOURCE_XX_INDEX), so don't touch!
3767	*/
3768	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3769	{
3770	int rc2 = ichac97R3LoadStream(pDevIns, pSSM, &pThis->aStreams[i]);
3771	AssertRCReturn(rc2, rc2);
3772	}
3773
3774	pHlp->pfnSSMGetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3775
3776	ichac97R3MixerRecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
3777	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3778	ichac97MixerGet(pThis, AC97_Master_Volume_Mute));
3779	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT,
3780	ichac97MixerGet(pThis, AC97_PCM_Out_Volume_Mute));
3781	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3782	ichac97MixerGet(pThis, AC97_Line_In_Volume_Mute));
3783	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3784	ichac97MixerGet(pThis, AC97_Mic_Volume_Mute));
3785	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3786	ichac97MixerGet(pThis, AC97_Record_Gain_Mic_Mute));
3787	ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3788	ichac97MixerGet(pThis, AC97_Record_Gain_Mute));
3789	if (pThis->enmCodecModel == AC97CODEC_AD1980)
3790	if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3791	ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3792	ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
3793
3794	/*
3795	* Again the stream order is set is stone.
3796	*/
3797	uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3798	int rc2 = pHlp->pfnSSMGetMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3799	AssertRCReturn(rc2, rc2);
3800
3801	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3802	{
3803	const bool fEnable = RT_BOOL(afActiveStrms[i]);
3804	const PAC97STREAM pStream = &pThis->aStreams[i];
3805	const PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[i];
3806
3807	rc2 = ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, fEnable);
3808	AssertRC(rc2);
3809	if ( fEnable
3810	&& RT_SUCCESS(rc2))
3811	{
3812	/* Re-arm the timer for this stream. */
3813	/** @todo r=aeichner This causes a VM hang upon saved state resume when NetBSD is used as a guest
3814	* Stopping the timer if cTransferTicks is 0 is a workaround but needs further investigation,
3815	* see @bugref{9759} for more information. */
3816	if (pStreamCC->State.cTransferTicks)
3817	ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3818	else
3819	PDMDevHlpTimerStop(pDevIns, pStream->hTimer);
3820	}
3821
3822	/* Keep going. */
3823	}
3824
3825	pThis->bup_flag = 0;
3826	pThis->last_samp = 0;
3827
3828	return VINF_SUCCESS;
3829	}
3830
3831
3832	/**
3833	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3834	*/
3835	static DECLCALLBACK(void ) ichac97R3QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
3836	{
3837	PAC97STATER3 pThisCC = RT_FROM_MEMBER(pInterface, AC97STATER3, IBase);
3838	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
3839	return NULL;
3840	}
3841
3842
3843	/**
3844	* Powers off the device.
3845	*
3846	* @param pDevIns Device instance to power off.
3847	*/
3848	static DECLCALLBACK(void) ichac97R3PowerOff(PPDMDEVINS pDevIns)
3849	{
3850	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3851	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3852
3853	LogRel2(("AC97: Powering off ...\n"));
3854
3855	/* Note: Involves mixer stream / sink destruction, so also do this here
3856	* instead of in ichac97R3Destruct(). */
3857	ichac97R3StreamsDestroy(pDevIns, pThis, pThisCC);
3858
3859	/*
3860	* Note: Destroy the mixer while powering off and not in ichac97R3Destruct,
3861	* giving the mixer the chance to release any references held to
3862	* PDM audio streams it maintains.
3863	*/
3864	if (pThisCC->pMixer)
3865	{
3866	AudioMixerDestroy(pThisCC->pMixer, pDevIns);
3867	pThisCC->pMixer = NULL;
3868	}
3869	}
3870
3871
3872	/**
3873	* @interface_method_impl{PDMDEVREG,pfnReset}
3874	*
3875	* @remarks The original sources didn't install a reset handler, but it seems to
3876	* make sense to me so we'll do it.
3877	*/
3878	static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns)
3879	{
3880	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3881	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3882
3883	LogRel(("AC97: Reset\n"));
3884
3885	/*
3886	* Reset the mixer too. The Windows XP driver seems to rely on
3887	* this. At least it wants to read the vendor id before it resets
3888	* the codec manually.
3889	*/
3890	ichac97R3MixerReset(pThis, pThisCC);
3891
3892	/*
3893	* Reset all streams.
3894	*/
3895	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3896	{
3897	ichac97R3StreamEnable(pDevIns, pThis, pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], false /* fEnable */);
3898	ichac97R3StreamReset(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
3899	}
3900
3901	/*
3902	* Reset mixer sinks.
3903	*
3904	* Do the reset here instead of in ichac97R3StreamReset();
3905	* the mixer sink(s) might still have data to be processed when an audio stream gets reset.
3906	*/
3907	AudioMixerSinkReset(pThisCC->pSinkLineIn);
3908	AudioMixerSinkReset(pThisCC->pSinkMicIn);
3909	AudioMixerSinkReset(pThisCC->pSinkOut);
3910	}
3911
3912
3913	/**
3914	* Worker for ichac97R3Construct() and ichac97R3Attach().
3915	*
3916	* @returns VBox status code.
3917	* @param pDevIns The device instance.
3918	* @param pThisCC The ring-3 AC'97 device state.
3919	* @param iLun The logical unit which is being attached.
3920	* @param ppDrv Attached driver instance on success. Optional.
3921	*/
3922	static int ichac97R3AttachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned iLun, PAC97DRIVER *ppDrv)
3923	{
3924	/*
3925	* Attach driver.
3926	*/
3927	char *pszDesc = RTStrAPrintf2("Audio driver port (AC'97) for LUN #%u", iLun);
3928	AssertLogRelReturn(pszDesc, VERR_NO_STR_MEMORY);
3929
3930	PPDMIBASE pDrvBase;
3931	int rc = PDMDevHlpDriverAttach(pDevIns, iLun, &pThisCC->IBase, &pDrvBase, pszDesc);
3932	if (RT_SUCCESS(rc))
3933	{
3934	PAC97DRIVER pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
3935	if (pDrv)
3936	{
3937	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
3938	AssertPtr(pDrv->pConnector);
3939	if (pDrv->pConnector)
3940	{
3941	pDrv->pDrvBase = pDrvBase;
3942	pDrv->uLUN = iLun;
3943	pDrv->pszDesc = pszDesc;
3944
3945	/*
3946	* For now we always set the driver at LUN 0 as our primary
3947	* host backend. This might change in the future.
3948	*/
3949	if (iLun == 0)
3950	pDrv->fFlags \|= PDMAUDIODRVFLAGS_PRIMARY;
3951
3952	LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", iLun, pDrv->pConnector, pDrv->fFlags));
3953
3954	/* Attach to driver list if not attached yet. */
3955	if (!pDrv->fAttached)
3956	{
3957	RTListAppend(&pThisCC->lstDrv, &pDrv->Node);
3958	pDrv->fAttached = true;
3959	}
3960
3961	if (ppDrv)
3962	*ppDrv = pDrv;
3963	LogFunc(("LUN#%u: VINF_SUCCESS\n", iLun));
3964	return VINF_SUCCESS;
3965	}
3966	RTMemFree(pDrv);
3967	rc = VERR_PDM_MISSING_INTERFACE_BELOW;
3968	}
3969	else
3970	rc = VERR_NO_MEMORY;
3971	}
3972	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3973	LogFunc(("No attached driver for LUN #%u\n", iLun));
3974	else
3975	LogFunc(("Attached driver for LUN #%u failed: %Rrc\n", iLun, rc));
3976
3977	RTStrFree(pszDesc);
3978	LogFunc(("LUN#%u: rc=%Rrc\n", iLun, rc));
3979	return rc;
3980	}
3981
3982	/**
3983	* @interface_method_impl{PDMDEVREGR3,pfnAttach}
3984	*/
3985	static DECLCALLBACK(int) ichac97R3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3986	{
3987	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3988	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3989	RT_NOREF(fFlags);
3990	LogFunc(("iLUN=%u, fFlags=%#x\n", iLUN, fFlags));
3991
3992	DEVAC97_LOCK(pDevIns, pThis);
3993
3994	PAC97DRIVER pDrv;
3995	int rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLUN, &pDrv);
3996	if (RT_SUCCESS(rc))
3997	{
3998	int rc2 = ichac97R3MixerAddDrv(pDevIns, pThisCC, pDrv);
3999	if (RT_FAILURE(rc2))
4000	LogFunc(("ichac97R3MixerAddDrv failed with %Rrc (ignored)\n", rc2));
4001	}
4002
4003	DEVAC97_UNLOCK(pDevIns, pThis);
4004
4005	return rc;
4006	}
4007
4008	/**
4009	* Worker for ichac97R3Detach that does all but freeing the pDrv structure.
4010	*
4011	* This is called to let the device detach from a driver for a specified LUN
4012	* at runtime.
4013	*
4014	* @param pDevIns The device instance.
4015	* @param pThisCC The ring-3 AC'97 device state.
4016	* @param pDrv Driver to detach from device.
4017	*/
4018	static void ichac97R3DetachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
4019	{
4020	/* First, remove the driver from our list and destory it's associated streams.
4021	* This also will un-set the driver as a recording source (if associated). */
4022	ichac97R3MixerRemoveDrv(pDevIns, pThisCC, pDrv);
4023
4024	/* Next, search backwards for a capable (attached) driver which now will be the
4025	* new recording source. */
4026	/** @todo r=bird: This looks completely wrong. What if the detatched devices wasn't the recording source
4027	* and we pick a different one here? I also don't get why we need to do this in revese order, given that
4028	* the primary device is first. I guess this code isn't really tested. */
4029	PDMAUDIODSTSRCUNION dstSrc;
4030	PAC97DRIVER pDrvCur;
4031	RTListForEachReverse(&pThisCC->lstDrv, pDrvCur, AC97DRIVER, Node)
4032	{
4033	if (!pDrvCur->pConnector)
4034	continue;
4035
4036	PDMAUDIOBACKENDCFG Cfg;
4037	int rc2 = pDrvCur->pConnector->pfnGetConfig(pDrvCur->pConnector, &Cfg);
4038	if (RT_FAILURE(rc2))
4039	continue;
4040
4041	dstSrc.enmSrc = PDMAUDIORECSRC_MIC;
4042	PAC97DRIVERSTREAM pDrvStrm = ichac97R3MixerGetDrvStream(pDrvCur, PDMAUDIODIR_IN, dstSrc);
4043	if ( pDrvStrm
4044	&& pDrvStrm->pMixStrm)
4045	{
4046	rc2 = AudioMixerSinkSetRecordingSource(pThisCC->pSinkMicIn, pDrvStrm->pMixStrm);
4047	if (RT_SUCCESS(rc2))
4048	LogRel2(("AC97: Set new recording source for 'Mic In' to '%s'\n", Cfg.szName));
4049	}
4050
4051	dstSrc.enmSrc = PDMAUDIORECSRC_LINE;
4052	pDrvStrm = ichac97R3MixerGetDrvStream(pDrvCur, PDMAUDIODIR_IN, dstSrc);
4053	if ( pDrvStrm
4054	&& pDrvStrm->pMixStrm)
4055	{
4056	rc2 = AudioMixerSinkSetRecordingSource(pThisCC->pSinkLineIn, pDrvStrm->pMixStrm);
4057	if (RT_SUCCESS(rc2))
4058	LogRel2(("AC97: Set new recording source for 'Line In' to '%s'\n", Cfg.szName));
4059	}
4060	}
4061
4062	LogFunc(("Detached LUN#%u\n", pDrv->uLUN));
4063	}
4064
4065	/**
4066	* @interface_method_impl{PDMDEVREG,pfnDetach}
4067	*/
4068	static DECLCALLBACK(void) ichac97R3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4069	{
4070	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4071	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4072	RT_NOREF(fFlags);
4073
4074	LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
4075
4076	DEVAC97_LOCK(pDevIns, pThis);
4077
4078	PAC97DRIVER pDrv;
4079	RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
4080	{
4081	if (pDrv->uLUN == iLUN)
4082	{
4083	ichac97R3DetachInternal(pDevIns, pThisCC, pDrv);
4084	RTStrFree(pDrv->pszDesc);
4085	RTMemFree(pDrv);
4086	DEVAC97_UNLOCK(pDevIns, pThis);
4087	return;
4088	}
4089	}
4090
4091	DEVAC97_UNLOCK(pDevIns, pThis);
4092	LogFunc(("LUN#%u was not found\n", iLUN));
4093	}
4094
4095
4096	/**
4097	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4098	*/
4099	static DECLCALLBACK(int) ichac97R3Destruct(PPDMDEVINS pDevIns)
4100	{
4101	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4102	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4103
4104	LogFlowFuncEnter();
4105
4106	PAC97DRIVER pDrv, pDrvNext;
4107	RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
4108	{
4109	RTListNodeRemove(&pDrv->Node);
4110	RTMemFree(pDrv->pszDesc);
4111	RTMemFree(pDrv);
4112	}
4113
4114	/* Sanity. */
4115	Assert(RTListIsEmpty(&pThisCC->lstDrv));
4116
4117	return VINF_SUCCESS;
4118	}
4119
4120	/**
4121	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4122	*/
4123	static DECLCALLBACK(int) ichac97R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4124	{
4125	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4126	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4127	PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4128	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4129	Assert(iInstance == 0); RT_NOREF(iInstance);
4130
4131	/*
4132	* Initialize data so we can run the destructor without scewing up.
4133	*/
4134	pThisCC->pDevIns = pDevIns;
4135	pThisCC->IBase.pfnQueryInterface = ichac97R3QueryInterface;
4136	RTListInit(&pThisCC->lstDrv);
4137
4138	/*
4139	* Validate and read configuration.
4140	*/
4141	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Codec\|TimerHz\|DebugEnabled\|DebugPathOut", "");
4142
4143	char szCodec[20];
4144	int rc = pHlp->pfnCFGMQueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
4145	if (RT_FAILURE(rc))
4146	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4147	N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
4148
4149	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, AC97_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4150	if (RT_FAILURE(rc))
4151	return PDMDEV_SET_ERROR(pDevIns, rc,
4152	N_("AC'97 configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4153
4154	if (pThis->uTimerHz != AC97_TIMER_HZ_DEFAULT)
4155	LogRel(("AC97: Using custom device timer rate (%RU16Hz)\n", pThis->uTimerHz));
4156
4157	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "DebugEnabled", &pThisCC->Dbg.fEnabled, false);
4158	if (RT_FAILURE(rc))
4159	return PDMDEV_SET_ERROR(pDevIns, rc,
4160	N_("AC97 configuration error: failed to read debugging enabled flag as boolean"));
4161
4162	rc = pHlp->pfnCFGMQueryStringAllocDef(pCfg, "DebugPathOut", &pThisCC->Dbg.pszOutPath, NULL);
4163	if (RT_FAILURE(rc))
4164	return PDMDEV_SET_ERROR(pDevIns, rc,
4165	N_("AC97 configuration error: failed to read debugging output path flag as string"));
4166
4167	if (pThisCC->Dbg.fEnabled)
4168	LogRel2(("AC97: Debug output will be saved to '%s'\n", pThisCC->Dbg.pszOutPath));
4169
4170	/*
4171	* The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
4172	* in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
4173	* 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
4174	*/
4175	if (!strcmp(szCodec, "STAC9700"))
4176	pThis->enmCodecModel = AC97CODEC_STAC9700;
4177	else if (!strcmp(szCodec, "AD1980"))
4178	pThis->enmCodecModel = AC97CODEC_AD1980;
4179	else if (!strcmp(szCodec, "AD1981B"))
4180	pThis->enmCodecModel = AC97CODEC_AD1981B;
4181	else
4182	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
4183	N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"), szCodec);
4184
4185	LogRel(("AC97: Using codec '%s'\n", szCodec));
4186
4187	/*
4188	* Use an own critical section for the device instead of the default
4189	* one provided by PDM. This allows fine-grained locking in combination
4190	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4191	*/
4192	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "AC'97");
4193	AssertRCReturn(rc, rc);
4194
4195	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4196	AssertRCReturn(rc, rc);
4197
4198	/*
4199	* Initialize data (most of it anyway).
4200	*/
4201	/* PCI Device */
4202	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4203	PCIDevSetVendorId(pPciDev, 0x8086); /* 00 ro - intel. */ Assert(pPciDev->abConfig[0x00] == 0x86); Assert(pPciDev->abConfig[0x01] == 0x80);
4204	PCIDevSetDeviceId(pPciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pPciDev->abConfig[0x02] == 0x15); Assert(pPciDev->abConfig[0x03] == 0x24);
4205	PCIDevSetCommand(pPciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pPciDev->abConfig[0x04] == 0x00); Assert(pPciDev->abConfig[0x05] == 0x00);
4206	PCIDevSetStatus(pPciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM \| VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pPciDev->abConfig[0x06] == 0x80); Assert(pPciDev->abConfig[0x07] == 0x02);
4207	PCIDevSetRevisionId(pPciDev, 0x01); /* 08 ro - rid. */ Assert(pPciDev->abConfig[0x08] == 0x01);
4208	PCIDevSetClassProg(pPciDev, 0x00); /* 09 ro - pi. */ Assert(pPciDev->abConfig[0x09] == 0x00);
4209	PCIDevSetClassSub(pPciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pPciDev->abConfig[0x0a] == 0x01);
4210	PCIDevSetClassBase(pPciDev, 0x04); /* 0b ro - bcc; 04 == multimedia.*/Assert(pPciDev->abConfig[0x0b] == 0x04);
4211	PCIDevSetHeaderType(pPciDev, 0x00); /* 0e ro - headtyp. */ Assert(pPciDev->abConfig[0x0e] == 0x00);
4212	PCIDevSetBaseAddress(pPciDev, 0, /* 10 rw - nambar - native audio mixer base. */
4213	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x10] == 0x01); Assert(pPciDev->abConfig[0x11] == 0x00); Assert(pPciDev->abConfig[0x12] == 0x00); Assert(pPciDev->abConfig[0x13] == 0x00);
4214	PCIDevSetBaseAddress(pPciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
4215	true /* fIoSpace /, false / fPrefetchable /, false / f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x14] == 0x01); Assert(pPciDev->abConfig[0x15] == 0x00); Assert(pPciDev->abConfig[0x16] == 0x00); Assert(pPciDev->abConfig[0x17] == 0x00);
4216	PCIDevSetInterruptLine(pPciDev, 0x00); /* 3c rw. */ Assert(pPciDev->abConfig[0x3c] == 0x00);
4217	PCIDevSetInterruptPin(pPciDev, 0x01); /* 3d ro - INTA#. */ Assert(pPciDev->abConfig[0x3d] == 0x01);
4218
4219	if (pThis->enmCodecModel == AC97CODEC_AD1980)
4220	{
4221	PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4222	PCIDevSetSubSystemId(pPciDev, 0x0177); /* 2e ro. */
4223	}
4224	else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
4225	{
4226	PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4227	PCIDevSetSubSystemId(pPciDev, 0x01ad); /* 2e ro. */
4228	}
4229	else
4230	{
4231	PCIDevSetSubSystemVendorId(pPciDev, 0x8086); /* 2c ro - Intel.) */
4232	PCIDevSetSubSystemId(pPciDev, 0x0000); /* 2e ro. */
4233	}
4234
4235	/*
4236	* Register the PCI device and associated I/O regions.
4237	*/
4238	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4239	if (RT_FAILURE(rc))
4240	return rc;
4241
4242	rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 0 /iPciRegion/, 256 /cPorts/,
4243	ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /pvUser/,
4244	"ICHAC97 NAM", NULL /paExtDescs/, &pThis->hIoPortsNam);
4245	AssertRCReturn(rc, rc);
4246
4247	rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 1 /iPciRegion/, 64 /cPorts/,
4248	ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /pvUser/,
4249	"ICHAC97 NABM", g_aNabmPorts, &pThis->hIoPortsNabm);
4250	AssertRCReturn(rc, rc);
4251
4252	/*
4253	* Saved state.
4254	*/
4255	rc = PDMDevHlpSSMRegister(pDevIns, AC97_SAVED_STATE_VERSION, sizeof(*pThis), ichac97R3SaveExec, ichac97R3LoadExec);
4256	if (RT_FAILURE(rc))
4257	return rc;
4258
4259	# ifdef VBOX_WITH_AUDIO_AC97_ASYNC_IO
4260	LogRel(("AC97: Asynchronous I/O enabled\n"));
4261	# endif
4262
4263	/*
4264	* Attach drivers. We ASSUME they are configured consecutively without any
4265	* gaps, so we stop when we hit the first LUN w/o a driver configured.
4266	*/
4267	for (unsigned iLun = 0; ; iLun++)
4268	{
4269	AssertBreak(iLun < UINT8_MAX);
4270	LogFunc(("Trying to attach driver for LUN#%u ...\n", iLun));
4271	rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, NULL /* ppDrv */);
4272	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4273	{
4274	LogFunc(("cLUNs=%u\n", iLun));
4275	break;
4276	}
4277	AssertLogRelMsgReturn(RT_SUCCESS(rc), ("LUN#%u: rc=%Rrc\n", iLun, rc), rc);
4278	}
4279
4280	uint32_t fMixer = AUDMIXER_FLAGS_NONE;
4281	if (pThisCC->Dbg.fEnabled)
4282	fMixer \|= AUDMIXER_FLAGS_DEBUG;
4283
4284	rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThisCC->pMixer);
4285	AssertRCReturn(rc, rc);
4286
4287	rc = AudioMixerCreateSink(pThisCC->pMixer, "Line In",
4288	PDMAUDIODIR_IN, pDevIns, &pThisCC->pSinkLineIn);
4289	AssertRCReturn(rc, rc);
4290	rc = AudioMixerCreateSink(pThisCC->pMixer, "Microphone In",
4291	PDMAUDIODIR_IN, pDevIns, &pThisCC->pSinkMicIn);
4292	AssertRCReturn(rc, rc);
4293	rc = AudioMixerCreateSink(pThisCC->pMixer, "PCM Output",
4294	PDMAUDIODIR_OUT, pDevIns, &pThisCC->pSinkOut);
4295	AssertRCReturn(rc, rc);
4296
4297	/*
4298	* Create all hardware streams.
4299	*/
4300	AssertCompile(RT_ELEMENTS(pThis->aStreams) == AC97_MAX_STREAMS);
4301	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4302	{
4303	rc = ichac97R3StreamCreate(pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], i /* SD# */);
4304	AssertRCReturn(rc, rc);
4305	}
4306
4307	/*
4308	* Create the emulation timers (one per stream).
4309	*
4310	* We must the critical section for the timers as the device has a
4311	* noop section associated with it.
4312	*
4313	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's AC'97 driver
4314	* relies on exact (virtual) DMA timing and uses DMA Position Buffers
4315	* instead of the LPIB registers.
4316	*/
4317	/** @todo r=bird: The need to use virtual sync is perhaps because TM
4318	* doesn't schedule regular TMCLOCK_VIRTUAL timers as accurately as it
4319	* should (VT-x preemption timer, etc). Hope to address that before
4320	* long. @bugref{9943}. */
4321	static const char * const s_apszNames[] = { "AC97 PI", "AC97 PO", "AC97 MC" };
4322	AssertCompile(RT_ELEMENTS(s_apszNames) == AC97_MAX_STREAMS);
4323	for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4324	{
4325	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, ichac97R3Timer, &pThis->aStreams[i],
4326	TMTIMER_FLAGS_NO_CRIT_SECT \| TMTIMER_FLAGS_RING0, s_apszNames[i], &pThis->aStreams[i].hTimer);
4327	AssertRCReturn(rc, rc);
4328
4329	rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->aStreams[i].hTimer, &pThis->CritSect);
4330	AssertRCReturn(rc, rc);
4331	}
4332
4333	ichac97R3Reset(pDevIns);
4334
4335	/*
4336	* Register statistics.
4337	*/
4338	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmReads, STAMTYPE_COUNTER, "UnimplementedNabmReads", STAMUNIT_OCCURENCES, "Unimplemented NABM register reads.");
4339	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmWrites, STAMTYPE_COUNTER, "UnimplementedNabmWrites", STAMUNIT_OCCURENCES, "Unimplemented NABM register writes.");
4340	# ifdef VBOX_WITH_STATISTICS
4341	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
4342	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
4343	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
4344	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
4345	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
4346	# endif
4347
4348	LogFlowFuncLeaveRC(VINF_SUCCESS);
4349	return VINF_SUCCESS;
4350	}
4351
4352	#else /* !IN_RING3 */
4353
4354	/**
4355	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4356	*/
4357	static DECLCALLBACK(int) ichac97RZConstruct(PPDMDEVINS pDevIns)
4358	{
4359	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4360	PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4361
4362	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4363	AssertRCReturn(rc, rc);
4364
4365	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNam, ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /pvUser/);
4366	AssertRCReturn(rc, rc);
4367	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNabm, ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /pvUser/);
4368	AssertRCReturn(rc, rc);
4369
4370	return VINF_SUCCESS;
4371	}
4372
4373	#endif /* !IN_RING3 */
4374
4375	/**
4376	* The device registration structure.
4377	*/
4378	const PDMDEVREG g_DeviceICHAC97 =
4379	{
4380	/* .u32Version = */ PDM_DEVREG_VERSION,
4381	/* .uReserved0 = */ 0,
4382	/* .szName = */ "ichac97",
4383	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
4384	\| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION /* stream clearnup with working drivers */,
4385	/* .fClass = */ PDM_DEVREG_CLASS_AUDIO,
4386	/* .cMaxInstances = */ 1,
4387	/* .uSharedVersion = */ 42,
4388	/* .cbInstanceShared = */ sizeof(AC97STATE),
4389	/* .cbInstanceCC = */ CTX_EXPR(sizeof(AC97STATER3), 0, 0),
4390	/* .cbInstanceRC = */ 0,
4391	/* .cMaxPciDevices = */ 1,
4392	/* .cMaxMsixVectors = */ 0,
4393	/* .pszDescription = */ "ICH AC'97 Audio Controller",
4394	#if defined(IN_RING3)
4395	/* .pszRCMod = */ "VBoxDDRC.rc",
4396	/* .pszR0Mod = */ "VBoxDDR0.r0",
4397	/* .pfnConstruct = */ ichac97R3Construct,
4398	/* .pfnDestruct = */ ichac97R3Destruct,
4399	/* .pfnRelocate = */ NULL,
4400	/* .pfnMemSetup = */ NULL,
4401	/* .pfnPowerOn = */ NULL,
4402	/* .pfnReset = */ ichac97R3Reset,
4403	/* .pfnSuspend = */ NULL,
4404	/* .pfnResume = */ NULL,
4405	/* .pfnAttach = */ ichac97R3Attach,
4406	/* .pfnDetach = */ ichac97R3Detach,
4407	/* .pfnQueryInterface = */ NULL,
4408	/* .pfnInitComplete = */ NULL,
4409	/* .pfnPowerOff = */ ichac97R3PowerOff,
4410	/* .pfnSoftReset = */ NULL,
4411	/* .pfnReserved0 = */ NULL,
4412	/* .pfnReserved1 = */ NULL,
4413	/* .pfnReserved2 = */ NULL,
4414	/* .pfnReserved3 = */ NULL,
4415	/* .pfnReserved4 = */ NULL,
4416	/* .pfnReserved5 = */ NULL,
4417	/* .pfnReserved6 = */ NULL,
4418	/* .pfnReserved7 = */ NULL,
4419	#elif defined(IN_RING0)
4420	/* .pfnEarlyConstruct = */ NULL,
4421	/* .pfnConstruct = */ ichac97RZConstruct,
4422	/* .pfnDestruct = */ NULL,
4423	/* .pfnFinalDestruct = */ NULL,
4424	/* .pfnRequest = */ NULL,
4425	/* .pfnReserved0 = */ NULL,
4426	/* .pfnReserved1 = */ NULL,
4427	/* .pfnReserved2 = */ NULL,
4428	/* .pfnReserved3 = */ NULL,
4429	/* .pfnReserved4 = */ NULL,
4430	/* .pfnReserved5 = */ NULL,
4431	/* .pfnReserved6 = */ NULL,
4432	/* .pfnReserved7 = */ NULL,
4433	#elif defined(IN_RC)
4434	/* .pfnConstruct = */ ichac97RZConstruct,
4435	/* .pfnReserved0 = */ NULL,
4436	/* .pfnReserved1 = */ NULL,
4437	/* .pfnReserved2 = */ NULL,
4438	/* .pfnReserved3 = */ NULL,
4439	/* .pfnReserved4 = */ NULL,
4440	/* .pfnReserved5 = */ NULL,
4441	/* .pfnReserved6 = */ NULL,
4442	/* .pfnReserved7 = */ NULL,
4443	#else
4444	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4445	#endif
4446	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
4447	};
4448
4449	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4450

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source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 88919

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