VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 89687

Last change on this file since 89687 was 89687, checked in by vboxsync, 3 years ago

DevIchAc97: ichac97R3DbgPrintBdl misunderstood LVI. Some todos and nits. bugref:9890
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1/* $Id: DevIchAc97.cpp 89687 2021-06-14 16:11:37Z vboxsync $ */
2/** @file
3 * DevIchAc97 - VBox ICH AC97 Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_AC97
23#include <VBox/log.h>
24#include <VBox/vmm/pdmdev.h>
25#include <VBox/vmm/pdmaudioifs.h>
26#include <VBox/vmm/pdmaudioinline.h>
27#include <VBox/AssertGuest.h>
28
29#include <iprt/assert.h>
30#ifdef IN_RING3
31# ifdef DEBUG
32# include <iprt/file.h>
33# endif
34# include <iprt/mem.h>
35# include <iprt/semaphore.h>
36# include <iprt/string.h>
37# include <iprt/uuid.h>
38#endif
39
40#include "VBoxDD.h"
41
42#include "AudioMixBuffer.h"
43#include "AudioMixer.h"
44#include "AudioHlp.h"
45
46
47/*********************************************************************************************************************************
48* Defined Constants And Macros *
49*********************************************************************************************************************************/
50/** Current saved state version. */
51#define AC97_SAVED_STATE_VERSION 1
52
53/** Default timer frequency (in Hz). */
54#define AC97_TIMER_HZ_DEFAULT 100
55
56/** Maximum number of streams we support. */
57#define AC97_MAX_STREAMS 3
58
59/** Maximum FIFO size (in bytes) - unused. */
60#define AC97_FIFO_MAX 256
61
62/** @name AC97_SR_XXX - Status Register Bits (AC97_NABM_OFF_SR, PI_SR, PO_SR, MC_SR).
63 * @{ */
64#define AC97_SR_FIFOE RT_BIT(4) /**< rwc, FIFO error. */
65#define AC97_SR_BCIS RT_BIT(3) /**< rwc, Buffer completion interrupt status. */
66#define AC97_SR_LVBCI RT_BIT(2) /**< rwc, Last valid buffer completion interrupt. */
67#define AC97_SR_CELV RT_BIT(1) /**< ro, Current equals last valid. */
68#define AC97_SR_DCH RT_BIT(0) /**< ro, Controller halted. */
69#define AC97_SR_VALID_MASK (RT_BIT(5) - 1)
70#define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)
71#define AC97_SR_RO_MASK (AC97_SR_DCH | AC97_SR_CELV)
72#define AC97_SR_INT_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)
73/** @} */
74
75/** @name AC97_CR_XXX - Control Register Bits (AC97_NABM_OFF_CR, PI_CR, PO_CR, MC_CR).
76 * @{ */
77#define AC97_CR_IOCE RT_BIT(4) /**< rw, Interrupt On Completion Enable. */
78#define AC97_CR_FEIE RT_BIT(3) /**< rw FIFO Error Interrupt Enable. */
79#define AC97_CR_LVBIE RT_BIT(2) /**< rw Last Valid Buffer Interrupt Enable. */
80#define AC97_CR_RR RT_BIT(1) /**< rw Reset Registers. */
81#define AC97_CR_RPBM RT_BIT(0) /**< rw Run/Pause Bus Master. */
82#define AC97_CR_VALID_MASK (RT_BIT(5) - 1)
83#define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE | AC97_CR_FEIE | AC97_CR_LVBIE)
84/** @} */
85
86/** @name AC97_GC_XXX - Global Control Bits (see AC97_GLOB_CNT). */
87#define AC97_GC_WR 4 /**< rw Warm reset. */
88#define AC97_GC_CR 2 /**< rw Cold reset. */
89#define AC97_GC_VALID_MASK (RT_BIT(6) - 1)
90/** @} */
91
92/** @name AC97_GS_XXX - Global Status Bits (AC97_GLOB_STA).
93 * @{ */
94#define AC97_GS_MD3 RT_BIT(17) /**< rw */
95#define AC97_GS_AD3 RT_BIT(16) /**< rw */
96#define AC97_GS_RCS RT_BIT(15) /**< rwc */
97#define AC97_GS_B3S12 RT_BIT(14) /**< ro */
98#define AC97_GS_B2S12 RT_BIT(13) /**< ro */
99#define AC97_GS_B1S12 RT_BIT(12) /**< ro */
100#define AC97_GS_S1R1 RT_BIT(11) /**< rwc */
101#define AC97_GS_S0R1 RT_BIT(10) /**< rwc */
102#define AC97_GS_S1CR RT_BIT(9) /**< ro */
103#define AC97_GS_S0CR RT_BIT(8) /**< ro */
104#define AC97_GS_MINT RT_BIT(7) /**< ro */
105#define AC97_GS_POINT RT_BIT(6) /**< ro */
106#define AC97_GS_PIINT RT_BIT(5) /**< ro */
107#define AC97_GS_RSRVD (RT_BIT(4) | RT_BIT(3))
108#define AC97_GS_MOINT RT_BIT(2) /**< ro */
109#define AC97_GS_MIINT RT_BIT(1) /**< ro */
110#define AC97_GS_GSCI RT_BIT(0) /**< rwc */
111#define AC97_GS_RO_MASK ( AC97_GS_B3S12 \
112 | AC97_GS_B2S12 \
113 | AC97_GS_B1S12 \
114 | AC97_GS_S1CR \
115 | AC97_GS_S0CR \
116 | AC97_GS_MINT \
117 | AC97_GS_POINT \
118 | AC97_GS_PIINT \
119 | AC97_GS_RSRVD \
120 | AC97_GS_MOINT \
121 | AC97_GS_MIINT)
122#define AC97_GS_VALID_MASK (RT_BIT(18) - 1)
123#define AC97_GS_WCLEAR_MASK (AC97_GS_RCS | AC97_GS_S1R1 | AC97_GS_S0R1 | AC97_GS_GSCI)
124/** @} */
125
126/** @name Buffer Descriptor (BDLE, BDL).
127 * @{ */
128#define AC97_BD_IOC RT_BIT(31) /**< Interrupt on Completion. */
129#define AC97_BD_BUP RT_BIT(30) /**< Buffer Underrun Policy. */
130
131#define AC97_BD_LEN_MASK 0xFFFF /**< Mask for the BDL buffer length. */
132
133#define AC97_BD_LEN_CTL_MBZ UINT32_C(0x3fff0000) /**< Must-be-zero mask for AC97BDLE.ctl_len. */
134
135#define AC97_MAX_BDLE 32 /**< Maximum number of BDLEs. */
136/** @} */
137
138/** @name Extended Audio ID Register (EAID).
139 * @{ */
140#define AC97_EAID_VRA RT_BIT(0) /**< Variable Rate Audio. */
141#define AC97_EAID_VRM RT_BIT(3) /**< Variable Rate Mic Audio. */
142#define AC97_EAID_REV0 RT_BIT(10) /**< AC'97 revision compliance. */
143#define AC97_EAID_REV1 RT_BIT(11) /**< AC'97 revision compliance. */
144/** @} */
145
146/** @name Extended Audio Control and Status Register (EACS).
147 * @{ */
148#define AC97_EACS_VRA RT_BIT(0) /**< Variable Rate Audio (4.2.1.1). */
149#define AC97_EACS_VRM RT_BIT(3) /**< Variable Rate Mic Audio (4.2.1.1). */
150/** @} */
151
152/** @name Baseline Audio Register Set (BARS).
153 * @{ */
154#define AC97_BARS_VOL_MASK 0x1f /**< Volume mask for the Baseline Audio Register Set (5.7.2). */
155#define AC97_BARS_GAIN_MASK 0x0f /**< Gain mask for the Baseline Audio Register Set. */
156#define AC97_BARS_VOL_MUTE_SHIFT 15 /**< Mute bit shift for the Baseline Audio Register Set (5.7.2). */
157/** @} */
158
159/** AC'97 uses 1.5dB steps, we use 0.375dB steps: 1 AC'97 step equals 4 PDM steps. */
160#define AC97_DB_FACTOR 4
161
162/** @name Recording inputs?
163 * @{ */
164#define AC97_REC_MIC UINT8_C(0)
165#define AC97_REC_CD UINT8_C(1)
166#define AC97_REC_VIDEO UINT8_C(2)
167#define AC97_REC_AUX UINT8_C(3)
168#define AC97_REC_LINE_IN UINT8_C(4)
169#define AC97_REC_STEREO_MIX UINT8_C(5)
170#define AC97_REC_MONO_MIX UINT8_C(6)
171#define AC97_REC_PHONE UINT8_C(7)
172#define AC97_REC_MASK UINT8_C(7)
173/** @} */
174
175/** @name Mixer registers / NAM BAR registers?
176 * @{ */
177#define AC97_Reset 0x00
178#define AC97_Master_Volume_Mute 0x02
179#define AC97_Headphone_Volume_Mute 0x04 /**< Also known as AUX, see table 16, section 5.7. */
180#define AC97_Master_Volume_Mono_Mute 0x06
181#define AC97_Master_Tone_RL 0x08
182#define AC97_PC_BEEP_Volume_Mute 0x0a
183#define AC97_Phone_Volume_Mute 0x0c
184#define AC97_Mic_Volume_Mute 0x0e
185#define AC97_Line_In_Volume_Mute 0x10
186#define AC97_CD_Volume_Mute 0x12
187#define AC97_Video_Volume_Mute 0x14
188#define AC97_Aux_Volume_Mute 0x16
189#define AC97_PCM_Out_Volume_Mute 0x18
190#define AC97_Record_Select 0x1a
191#define AC97_Record_Gain_Mute 0x1c
192#define AC97_Record_Gain_Mic_Mute 0x1e
193#define AC97_General_Purpose 0x20
194#define AC97_3D_Control 0x22
195#define AC97_AC_97_RESERVED 0x24
196#define AC97_Powerdown_Ctrl_Stat 0x26
197#define AC97_Extended_Audio_ID 0x28
198#define AC97_Extended_Audio_Ctrl_Stat 0x2a
199#define AC97_PCM_Front_DAC_Rate 0x2c
200#define AC97_PCM_Surround_DAC_Rate 0x2e
201#define AC97_PCM_LFE_DAC_Rate 0x30
202#define AC97_PCM_LR_ADC_Rate 0x32
203#define AC97_MIC_ADC_Rate 0x34
204#define AC97_6Ch_Vol_C_LFE_Mute 0x36
205#define AC97_6Ch_Vol_L_R_Surround_Mute 0x38
206#define AC97_Vendor_Reserved 0x58
207#define AC97_AD_Misc 0x76
208#define AC97_Vendor_ID1 0x7c
209#define AC97_Vendor_ID2 0x7e
210/** @} */
211
212/** @name Analog Devices miscellaneous regiter bits used in AD1980.
213 * @{ */
214#define AC97_AD_MISC_LOSEL RT_BIT(5) /**< Surround (rear) goes to line out outputs. */
215#define AC97_AD_MISC_HPSEL RT_BIT(10) /**< PCM (front) goes to headphone outputs. */
216/** @} */
217
218
219/** @name BUP flag values.
220 * @{ */
221#define BUP_SET RT_BIT_32(0)
222#define BUP_LAST RT_BIT_32(1)
223/** @} */
224
225/** @name AC'97 source indices.
226 * @note The order of these indices is fixed (also applies for saved states) for
227 * the moment. So make sure you know what you're done when altering this!
228 * @{
229 */
230#define AC97SOUNDSOURCE_PI_INDEX 0 /**< PCM in */
231#define AC97SOUNDSOURCE_PO_INDEX 1 /**< PCM out */
232#define AC97SOUNDSOURCE_MC_INDEX 2 /**< Mic in */
233#define AC97SOUNDSOURCE_MAX 3 /**< Max sound sources. */
234/** @} */
235
236/** Port number (offset into NABM BAR) to stream index. */
237#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
238/** Port number (offset into NABM BAR) to stream index, but no masking. */
239#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
240
241/** @name Stream offsets
242 * @{ */
243#define AC97_NABM_OFF_BDBAR 0x0 /**< Buffer Descriptor Base Address */
244#define AC97_NABM_OFF_CIV 0x4 /**< Current Index Value */
245#define AC97_NABM_OFF_LVI 0x5 /**< Last Valid Index */
246#define AC97_NABM_OFF_SR 0x6 /**< Status Register */
247#define AC97_NABM_OFF_PICB 0x8 /**< Position in Current Buffer */
248#define AC97_NABM_OFF_PIV 0xa /**< Prefetched Index Value */
249#define AC97_NABM_OFF_CR 0xb /**< Control Register */
250#define AC97_NABM_OFF_MASK 0xf /**< Mask for getting the the per-stream register. */
251/** @} */
252
253
254/** @name PCM in NABM BAR registers (0x00..0x0f).
255 * @{ */
256#define PI_BDBAR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x0) /**< PCM in: Buffer Descriptor Base Address */
257#define PI_CIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x4) /**< PCM in: Current Index Value */
258#define PI_LVI (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x5) /**< PCM in: Last Valid Index */
259#define PI_SR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x6) /**< PCM in: Status Register */
260#define PI_PICB (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x8) /**< PCM in: Position in Current Buffer */
261#define PI_PIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xa) /**< PCM in: Prefetched Index Value */
262#define PI_CR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xb) /**< PCM in: Control Register */
263/** @} */
264
265/** @name PCM out NABM BAR registers (0x10..0x1f).
266 * @{ */
267#define PO_BDBAR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x0) /**< PCM out: Buffer Descriptor Base Address */
268#define PO_CIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x4) /**< PCM out: Current Index Value */
269#define PO_LVI (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x5) /**< PCM out: Last Valid Index */
270#define PO_SR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x6) /**< PCM out: Status Register */
271#define PO_PICB (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x8) /**< PCM out: Position in Current Buffer */
272#define PO_PIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xa) /**< PCM out: Prefetched Index Value */
273#define PO_CR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xb) /**< PCM out: Control Register */
274/** @} */
275
276/** @name Mic in NABM BAR registers (0x20..0x2f).
277 * @{ */
278#define MC_BDBAR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x0) /**< PCM in: Buffer Descriptor Base Address */
279#define MC_CIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x4) /**< PCM in: Current Index Value */
280#define MC_LVI (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x5) /**< PCM in: Last Valid Index */
281#define MC_SR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x6) /**< PCM in: Status Register */
282#define MC_PICB (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x8) /**< PCM in: Position in Current Buffer */
283#define MC_PIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xa) /**< PCM in: Prefetched Index Value */
284#define MC_CR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xb) /**< PCM in: Control Register */
285/** @} */
286
287/** @name Misc NABM BAR registers.
288 * @{ */
289/** NABMBAR: Global Control Register.
290 * @note This is kind of in the MIC IN area. */
291#define AC97_GLOB_CNT 0x2c
292/** NABMBAR: Global Status. */
293#define AC97_GLOB_STA 0x30
294/** Codec Access Semaphore Register. */
295#define AC97_CAS 0x34
296/** @} */
297
298
299/*********************************************************************************************************************************
300* Structures and Typedefs *
301*********************************************************************************************************************************/
302/** The ICH AC'97 (Intel) controller (shared). */
303typedef struct AC97STATE *PAC97STATE;
304/** The ICH AC'97 (Intel) controller (ring-3). */
305typedef struct AC97STATER3 *PAC97STATER3;
306
307/**
308 * Buffer Descriptor List Entry (BDLE).
309 *
310 * (See section 3.2.1 in Intel document number 252751-001, or section 1.2.2.1 in
311 * Intel document number 302349-003.)
312 */
313typedef struct AC97BDLE
314{
315 /** Location of data buffer (bits 31:1). */
316 uint32_t addr;
317 /** Flags (bits 31 + 30) and length (bits 15:0) of data buffer (in audio samples).
318 * @todo split up into two 16-bit fields. */
319 uint32_t ctl_len;
320} AC97BDLE;
321AssertCompileSize(AC97BDLE, 8);
322/** Pointer to BDLE. */
323typedef AC97BDLE *PAC97BDLE;
324
325/**
326 * Bus master register set for an audio stream.
327 *
328 * (See section 16.2 in Intel document 301473-002, or section 2.2 in Intel
329 * document 302349-003.)
330 */
331typedef struct AC97BMREGS
332{
333 uint32_t bdbar; /**< rw 0, Buffer Descriptor List: BAR (Base Address Register). */
334 uint8_t civ; /**< ro 0, Current index value. */
335 uint8_t lvi; /**< rw 0, Last valid index. */
336 uint16_t sr; /**< rw 1, Status register. */
337 uint16_t picb; /**< ro 0, Position in current buffer (samples left to process). */
338 uint8_t piv; /**< ro 0, Prefetched index value. */
339 uint8_t cr; /**< rw 0, Control register. */
340 int32_t bd_valid; /**< Whether current BDLE is initialized or not. */
341 AC97BDLE bd; /**< Current Buffer Descriptor List Entry (BDLE). */
342} AC97BMREGS;
343AssertCompileSizeAlignment(AC97BMREGS, 8);
344/** Pointer to the BM registers of an audio stream. */
345typedef AC97BMREGS *PAC97BMREGS;
346
347/**
348 * The internal state of an AC'97 stream.
349 */
350typedef struct AC97STREAMSTATE
351{
352 /** Critical section for this stream. */
353 RTCRITSECT CritSect;
354 /** Circular buffer (FIFO) for holding DMA'ed data. */
355 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
356#if HC_ARCH_BITS == 32
357 uint32_t Padding;
358#endif
359 /** Current circular buffer read offset (for tracing & logging). */
360 uint64_t offRead;
361 /** Current circular buffer write offset (for tracing & logging). */
362 uint64_t offWrite;
363 /** The stream's current configuration. */
364 PDMAUDIOSTREAMCFG Cfg; //+108
365 /** Timestamp of the last DMA data transfer. */
366 uint64_t tsTransferLast;
367 /** Timestamp of the next DMA data transfer.
368 * Next for determining the next scheduling window.
369 * Can be 0 if no next transfer is scheduled. */
370 uint64_t tsTransferNext;
371 /** Transfer chunk size (in bytes) of a transfer period. */
372 uint32_t cbTransferChunk;
373 /** The stream's timer Hz rate.
374 * This value can can be different from the device's default Hz rate,
375 * depending on the rate the stream expects (e.g. for 5.1 speaker setups).
376 * Set in R3StreamInit(). */
377 uint16_t uTimerHz;
378 /** Set if we've registered the asynchronous update job. */
379 bool fRegisteredAsyncUpdateJob;
380 uint8_t Padding3;
381 /** (Virtual) clock ticks per transfer. */
382 uint64_t cTransferTicks;
383 /** Timestamp (in ns) of last stream update. */
384 uint64_t tsLastUpdateNs;
385
386 /** Size of the DMA buffer (pCircBuf) in bytes. */
387 uint32_t StatDmaBufSize;
388 /** Number of used bytes in the DMA buffer (pCircBuf). */
389 uint32_t StatDmaBufUsed;
390} AC97STREAMSTATE;
391AssertCompileSizeAlignment(AC97STREAMSTATE, 8);
392/** Pointer to internal state of an AC'97 stream. */
393typedef AC97STREAMSTATE *PAC97STREAMSTATE;
394
395/**
396 * Runtime configurable debug stuff for an AC'97 stream.
397 */
398typedef struct AC97STREAMDEBUGRT
399{
400 /** Whether debugging is enabled or not. */
401 bool fEnabled;
402 uint8_t Padding[7];
403 /** File for dumping stream reads / writes.
404 * For input streams, this dumps data being written to the device FIFO,
405 * whereas for output streams this dumps data being read from the device FIFO. */
406 R3PTRTYPE(PAUDIOHLPFILE) pFileStream;
407 /** File for dumping DMA reads / writes.
408 * For input streams, this dumps data being written to the device DMA,
409 * whereas for output streams this dumps data being read from the device DMA. */
410 R3PTRTYPE(PAUDIOHLPFILE) pFileDMA;
411} AC97STREAMDEBUGRT;
412
413/**
414 * Debug stuff for an AC'97 stream.
415 */
416typedef struct AC97STREAMDEBUG
417{
418 /** Runtime debug stuff. */
419 AC97STREAMDEBUGRT Runtime;
420} AC97STREAMDEBUG;
421
422/**
423 * The shared AC'97 stream state.
424 */
425typedef struct AC97STREAM
426{
427 /** Stream number (SDn). */
428 uint8_t u8SD;
429 uint8_t abPadding0[7];
430 /** Bus master registers of this stream. */
431 AC97BMREGS Regs;
432 /** The timer for pumping data thru the attached LUN drivers. */
433 TMTIMERHANDLE hTimer;
434} AC97STREAM;
435AssertCompileSizeAlignment(AC97STREAM, 8);
436/** Pointer to a shared AC'97 stream state. */
437typedef AC97STREAM *PAC97STREAM;
438
439
440/**
441 * The ring-3 AC'97 stream state.
442 */
443typedef struct AC97STREAMR3
444{
445 /** Stream number (SDn). */
446 uint8_t u8SD;
447 uint8_t abPadding0[7];
448 /** Internal state of this stream. */
449 AC97STREAMSTATE State;
450 /** Debug stuff. */
451 AC97STREAMDEBUG Dbg;
452} AC97STREAMR3;
453AssertCompileSizeAlignment(AC97STREAMR3, 8);
454/** Pointer to an AC'97 stream state for ring-3. */
455typedef AC97STREAMR3 *PAC97STREAMR3;
456
457
458/**
459 * A driver stream (host backend).
460 *
461 * Each driver has its own instances of audio mixer streams, which then
462 * can go into the same (or even different) audio mixer sinks.
463 */
464typedef struct AC97DRIVERSTREAM
465{
466 /** Associated mixer stream handle. */
467 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
468} AC97DRIVERSTREAM;
469/** Pointer to a driver stream. */
470typedef AC97DRIVERSTREAM *PAC97DRIVERSTREAM;
471
472/**
473 * A host backend driver (LUN).
474 */
475typedef struct AC97DRIVER
476{
477 /** Node for storing this driver in our device driver list of AC97STATE. */
478 RTLISTNODER3 Node;
479 /** LUN # to which this driver has been assigned. */
480 uint8_t uLUN;
481 /** Whether this driver is in an attached state or not. */
482 bool fAttached;
483 uint8_t abPadding[6];
484 /** Pointer to the description string passed to PDMDevHlpDriverAttach(). */
485 R3PTRTYPE(char *) pszDesc;
486 /** Pointer to attached driver base interface. */
487 R3PTRTYPE(PPDMIBASE) pDrvBase;
488 /** Audio connector interface to the underlying host backend. */
489 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
490 /** Driver stream for line input. */
491 AC97DRIVERSTREAM LineIn;
492 /** Driver stream for mic input. */
493 AC97DRIVERSTREAM MicIn;
494 /** Driver stream for output. */
495 AC97DRIVERSTREAM Out;
496} AC97DRIVER;
497/** Pointer to a host backend driver (LUN). */
498typedef AC97DRIVER *PAC97DRIVER;
499
500/**
501 * Debug settings.
502 */
503typedef struct AC97STATEDEBUG
504{
505 /** Whether debugging is enabled or not. */
506 bool fEnabled;
507 bool afAlignment[7];
508 /** Path where to dump the debug output to.
509 * Can be NULL, in which the system's temporary directory will be used then. */
510 R3PTRTYPE(char *) pszOutPath;
511} AC97STATEDEBUG;
512
513
514/* Codec models. */
515typedef enum AC97CODEC
516{
517 AC97CODEC_INVALID = 0, /**< Customary illegal zero value. */
518 AC97CODEC_STAC9700, /**< SigmaTel STAC9700 */
519 AC97CODEC_AD1980, /**< Analog Devices AD1980 */
520 AC97CODEC_AD1981B, /**< Analog Devices AD1981B */
521 AC97CODEC_32BIT_HACK = 0x7fffffff
522} AC97CODEC;
523
524
525/**
526 * The shared AC'97 device state.
527 */
528typedef struct AC97STATE
529{
530 /** Critical section protecting the AC'97 state. */
531 PDMCRITSECT CritSect;
532 /** Global Control (Bus Master Control Register). */
533 uint32_t glob_cnt;
534 /** Global Status (Bus Master Control Register). */
535 uint32_t glob_sta;
536 /** Codec Access Semaphore Register (Bus Master Control Register). */
537 uint32_t cas;
538 uint32_t last_samp;
539 uint8_t mixer_data[256];
540 /** Array of AC'97 streams (parallel to AC97STATER3::aStreams). */
541 AC97STREAM aStreams[AC97_MAX_STREAMS];
542 /** The device timer Hz rate. Defaults to AC97_TIMER_HZ_DEFAULT_DEFAULT. */
543 uint16_t uTimerHz;
544 /** Config: Internal input DMA buffer size override, specified in milliseconds.
545 * Zero means default size according to buffer and stream config.
546 * @sa BufSizeInMs config value. */
547 uint16_t cMsCircBufIn;
548 /** Config: Internal output DMA buffer size override, specified in milliseconds.
549 * Zero means default size according to buffer and stream config.
550 * @sa BufSizeOutMs config value. */
551 uint16_t cMsCircBufOut;
552 uint16_t au16Padding1[1];
553 uint8_t silence[128];
554 uint32_t bup_flag;
555 /** Codec model. */
556 AC97CODEC enmCodecModel;
557
558 /** PCI region \#0: NAM I/O ports. */
559 IOMIOPORTHANDLE hIoPortsNam;
560 /** PCI region \#0: NANM I/O ports. */
561 IOMIOPORTHANDLE hIoPortsNabm;
562
563 STAMCOUNTER StatUnimplementedNabmReads;
564 STAMCOUNTER StatUnimplementedNabmWrites;
565#ifdef VBOX_WITH_STATISTICS
566 STAMPROFILE StatTimer;
567 STAMPROFILE StatIn;
568 STAMPROFILE StatOut;
569 STAMCOUNTER StatBytesRead;
570 STAMCOUNTER StatBytesWritten;
571#endif
572} AC97STATE;
573AssertCompileMemberAlignment(AC97STATE, aStreams, 8);
574AssertCompileMemberAlignment(AC97STATE, StatUnimplementedNabmReads, 8);
575#ifdef VBOX_WITH_STATISTICS
576AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
577AssertCompileMemberAlignment(AC97STATE, StatBytesRead, 8);
578AssertCompileMemberAlignment(AC97STATE, StatBytesWritten, 8);
579#endif
580
581
582/**
583 * The ring-3 AC'97 device state.
584 */
585typedef struct AC97STATER3
586{
587 /** Array of AC'97 streams (parallel to AC97STATE:aStreams). */
588 AC97STREAMR3 aStreams[AC97_MAX_STREAMS];
589 /** R3 pointer to the device instance. */
590 PPDMDEVINSR3 pDevIns;
591 /** List of associated LUN drivers (AC97DRIVER). */
592 RTLISTANCHORR3 lstDrv;
593 /** The device's software mixer. */
594 R3PTRTYPE(PAUDIOMIXER) pMixer;
595 /** Audio sink for PCM output. */
596 R3PTRTYPE(PAUDMIXSINK) pSinkOut;
597 /** Audio sink for line input. */
598 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
599 /** Audio sink for microphone input. */
600 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
601 /** The base interface for LUN\#0. */
602 PDMIBASE IBase;
603 /** Debug settings. */
604 AC97STATEDEBUG Dbg;
605} AC97STATER3;
606AssertCompileMemberAlignment(AC97STATER3, aStreams, 8);
607/** Pointer to the ring-3 AC'97 device state. */
608typedef AC97STATER3 *PAC97STATER3;
609
610
611/**
612 * Acquires the AC'97 lock.
613 */
614#define DEVAC97_LOCK(a_pDevIns, a_pThis) \
615 do { \
616 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
617 AssertRC(rcLock); \
618 } while (0)
619
620/**
621 * Acquires the AC'97 lock or returns.
622 */
623# define DEVAC97_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
624 do { \
625 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, a_rcBusy); \
626 if (rcLock == VINF_SUCCESS) \
627 break; \
628 AssertRC(rcLock); \
629 return rcLock; \
630 } while (0)
631
632/** Retrieves an attribute from a specific audio stream in RC. */
633#define DEVAC97_CTX_SUFF_SD(a_Var, a_SD) CTX_SUFF(a_Var)[a_SD]
634
635/**
636 * Releases the AC'97 lock.
637 */
638#define DEVAC97_UNLOCK(a_pDevIns, a_pThis) \
639 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
640
641/**
642 * Acquires the TM lock and AC'97 lock, returns on failure.
643 *
644 * @todo r=bird: Isn't this overkill for ring-0, only ring-3 access the timer
645 * from what I can tell (ichac97R3StreamTransferCalcNext,
646 * ichac97R3TimerSet, timer callback and state load).
647 */
648#define DEVAC97_LOCK_BOTH_RETURN(a_pDevIns, a_pThis, a_pStream, a_rcBusy) \
649 do { \
650 VBOXSTRICTRC rcLock = PDMDevHlpTimerLockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect, (a_rcBusy)); \
651 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
652 { /* likely */ } \
653 else \
654 { \
655 AssertRC(VBOXSTRICTRC_VAL(rcLock)); \
656 return rcLock; \
657 } \
658 } while (0)
659
660/**
661 * Releases the AC'97 lock and TM lock.
662 */
663#define DEVAC97_UNLOCK_BOTH(a_pDevIns, a_pThis, a_pStream) \
664 PDMDevHlpTimerUnlockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect)
665
666#ifndef VBOX_DEVICE_STRUCT_TESTCASE
667
668
669/*********************************************************************************************************************************
670* Internal Functions *
671*********************************************************************************************************************************/
672#ifdef IN_RING3
673static int ichac97R3StreamOpen(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
674 PAC97STREAMR3 pStreamCC, bool fForce);
675static int ichac97R3StreamClose(PAC97STREAM pStream);
676static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC);
677static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC);
678static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC);
679static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC);
680static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
681 PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax);
682static DECLCALLBACK(void) ichac97R3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser);
683
684static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns);
685
686static void ichac97R3MixerRemoveDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
687 PDMAUDIODIR enmDir, PDMAUDIOPATH enmPath);
688
689DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD);
690DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline);
691
692static void ichac97R3DbgPrintBdl(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
693 PCDBGFINFOHLP pHlp, const char *pszPrefix);
694#endif /* IN_RING3 */
695
696
697/*********************************************************************************************************************************
698* Global Variables *
699*********************************************************************************************************************************/
700#ifdef IN_RING3
701/** NABM I/O port descriptions. */
702static const IOMIOPORTDESC g_aNabmPorts[] =
703{
704 { "PCM IN - BDBAR", "PCM IN - BDBAR", NULL, NULL },
705 { "", NULL, NULL, NULL },
706 { "", NULL, NULL, NULL },
707 { "", NULL, NULL, NULL },
708 { "PCM IN - CIV", "PCM IN - CIV", NULL, NULL },
709 { "PCM IN - LVI", "PCM IN - LIV", NULL, NULL },
710 { "PCM IN - SR", "PCM IN - SR", NULL, NULL },
711 { "", NULL, NULL, NULL },
712 { "PCM IN - PICB", "PCM IN - PICB", NULL, NULL },
713 { "", NULL, NULL, NULL },
714 { "PCM IN - PIV", "PCM IN - PIV", NULL, NULL },
715 { "PCM IN - CR", "PCM IN - CR", NULL, NULL },
716 { "", NULL, NULL, NULL },
717 { "", NULL, NULL, NULL },
718 { "", NULL, NULL, NULL },
719 { "", NULL, NULL, NULL },
720
721 { "PCM OUT - BDBAR", "PCM OUT - BDBAR", NULL, NULL },
722 { "", NULL, NULL, NULL },
723 { "", NULL, NULL, NULL },
724 { "", NULL, NULL, NULL },
725 { "PCM OUT - CIV", "PCM OUT - CIV", NULL, NULL },
726 { "PCM OUT - LVI", "PCM OUT - LIV", NULL, NULL },
727 { "PCM OUT - SR", "PCM OUT - SR", NULL, NULL },
728 { "", NULL, NULL, NULL },
729 { "PCM OUT - PICB", "PCM OUT - PICB", NULL, NULL },
730 { "", NULL, NULL, NULL },
731 { "PCM OUT - PIV", "PCM OUT - PIV", NULL, NULL },
732 { "PCM OUT - CR", "PCM IN - CR", NULL, NULL },
733 { "", NULL, NULL, NULL },
734 { "", NULL, NULL, NULL },
735 { "", NULL, NULL, NULL },
736 { "", NULL, NULL, NULL },
737
738 { "MIC IN - BDBAR", "MIC IN - BDBAR", NULL, NULL },
739 { "", NULL, NULL, NULL },
740 { "", NULL, NULL, NULL },
741 { "", NULL, NULL, NULL },
742 { "MIC IN - CIV", "MIC IN - CIV", NULL, NULL },
743 { "MIC IN - LVI", "MIC IN - LIV", NULL, NULL },
744 { "MIC IN - SR", "MIC IN - SR", NULL, NULL },
745 { "", NULL, NULL, NULL },
746 { "MIC IN - PICB", "MIC IN - PICB", NULL, NULL },
747 { "", NULL, NULL, NULL },
748 { "MIC IN - PIV", "MIC IN - PIV", NULL, NULL },
749 { "MIC IN - CR", "MIC IN - CR", NULL, NULL },
750 { "GLOB CNT", "GLOB CNT", NULL, NULL },
751 { "", NULL, NULL, NULL },
752 { "", NULL, NULL, NULL },
753 { "", NULL, NULL, NULL },
754
755 { "GLOB STA", "GLOB STA", NULL, NULL },
756 { "", NULL, NULL, NULL },
757 { "", NULL, NULL, NULL },
758 { "", NULL, NULL, NULL },
759 { "CAS", "CAS", NULL, NULL },
760 { NULL, NULL, NULL, NULL },
761};
762
763/** @name Source indices
764 * @{ */
765# define AC97SOUNDSOURCE_PI_INDEX 0 /**< PCM in */
766# define AC97SOUNDSOURCE_PO_INDEX 1 /**< PCM out */
767# define AC97SOUNDSOURCE_MC_INDEX 2 /**< Mic in */
768# define AC97SOUNDSOURCE_MAX 3 /**< Max sound sources. */
769/** @} */
770
771/** Port number (offset into NABM BAR) to stream index. */
772# define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
773/** Port number (offset into NABM BAR) to stream index, but no masking. */
774# define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
775
776/** @name Stream offsets
777 * @{ */
778# define AC97_NABM_OFF_BDBAR 0x0 /**< Buffer Descriptor Base Address */
779# define AC97_NABM_OFF_CIV 0x4 /**< Current Index Value */
780# define AC97_NABM_OFF_LVI 0x5 /**< Last Valid Index */
781# define AC97_NABM_OFF_SR 0x6 /**< Status Register */
782# define AC97_NABM_OFF_PICB 0x8 /**< Position in Current Buffer */
783# define AC97_NABM_OFF_PIV 0xa /**< Prefetched Index Value */
784# define AC97_NABM_OFF_CR 0xb /**< Control Register */
785# define AC97_NABM_OFF_MASK 0xf /**< Mask for getting the the per-stream register. */
786/** @} */
787
788#endif /* IN_RING3 */
789
790
791
792static void ichac97WarmReset(PAC97STATE pThis)
793{
794 NOREF(pThis);
795}
796
797static void ichac97ColdReset(PAC97STATE pThis)
798{
799 NOREF(pThis);
800}
801
802
803#ifdef IN_RING3
804
805/**
806 * Retrieves the audio mixer sink of a corresponding AC'97 stream index.
807 *
808 * @returns Pointer to audio mixer sink if found, or NULL if not found / invalid.
809 * @param pThisCC The ring-3 AC'97 state.
810 * @param uIndex Stream index to get audio mixer sink for.
811 */
812DECLINLINE(PAUDMIXSINK) ichac97R3IndexToSink(PAC97STATER3 pThisCC, uint8_t uIndex)
813{
814 switch (uIndex)
815 {
816 case AC97SOUNDSOURCE_PI_INDEX: return pThisCC->pSinkLineIn;
817 case AC97SOUNDSOURCE_PO_INDEX: return pThisCC->pSinkOut;
818 case AC97SOUNDSOURCE_MC_INDEX: return pThisCC->pSinkMicIn;
819 default:
820 AssertMsgFailedReturn(("Wrong index %RU8\n", uIndex), NULL);
821 }
822}
823
824/**
825 * Fetches the next buffer descriptor (BDLE) updating the stream registers.
826 *
827 * This will skip zero length descriptors.
828 *
829 * @returns Zero, or AC97_SR_BCIS if skipped zero length buffer with IOC set.
830 * @param pDevIns The device instance.
831 * @param pStream AC'97 stream to fetch BDLE for.
832 * @param pStreamCC The AC'97 stream, ring-3 state.
833 *
834 * @remark Updates CIV, PIV, BD and PICB.
835 */
836static uint32_t ichac97R3StreamFetchNextBdle(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
837{
838 RT_NOREF(pStreamCC);
839 uint32_t fSrBcis = 0;
840
841 /*
842 * Loop for skipping zero length entries.
843 */
844 for (;;)
845 {
846 /* Advance the buffer. */
847 pStream->Regs.civ = pStream->Regs.piv;
848 pStream->Regs.piv = (pStream->Regs.piv + 1) % AC97_MAX_BDLE;
849
850 /* Load it. */
851 AC97BDLE Bdle = { 0, 0 };
852 PDMDevHlpPCIPhysRead(pDevIns, pStream->Regs.bdbar + pStream->Regs.civ * sizeof(AC97BDLE), &Bdle, sizeof(AC97BDLE));
853 pStream->Regs.bd_valid = 1;
854 pStream->Regs.bd.addr = RT_H2LE_U32(Bdle.addr) & ~3;
855 pStream->Regs.bd.ctl_len = RT_H2LE_U32(Bdle.ctl_len);
856 pStream->Regs.picb = pStream->Regs.bd.ctl_len & AC97_BD_LEN_MASK;
857
858 LogFlowFunc(("BDLE%02u: %#RX32 L %#x / LB %#x, ctl=%#06x%s%s\n",
859 pStream->Regs.civ, pStream->Regs.bd.addr, pStream->Regs.bd.ctl_len & AC97_BD_LEN_MASK,
860 (pStream->Regs.bd.ctl_len & AC97_BD_LEN_MASK) * PDMAudioPropsSampleSize(&pStreamCC->State.Cfg.Props),
861 pStream->Regs.bd.ctl_len >> 16,
862 pStream->Regs.bd.ctl_len & AC97_BD_IOC ? " ioc" : "",
863 pStream->Regs.bd.ctl_len & AC97_BD_BUP ? " bup" : ""));
864
865 /* Complain about any reserved bits set in CTL and ADDR: */
866 ASSERT_GUEST_MSG(!(pStream->Regs.bd.ctl_len & AC97_BD_LEN_CTL_MBZ),
867 ("Reserved bits set: %#RX32\n", pStream->Regs.bd.ctl_len));
868 ASSERT_GUEST_MSG(!(RT_H2LE_U32(Bdle.addr) & 3),
869 ("Reserved addr bits set: %#RX32\n", RT_H2LE_U32(Bdle.addr) ));
870
871 /* If the length is non-zero or if we've reached LVI, we're done regardless
872 of what's been loaded. Otherwise, we skip zero length buffers. */
873 if (pStream->Regs.picb)
874 break;
875 if (pStream->Regs.civ == pStream->Regs.lvi)
876 {
877 LogFunc(("BDLE%02u is zero length! Can't skip (CIV=LVI). %#RX32 %#RX32\n", pStream->Regs.civ, Bdle.addr, Bdle.ctl_len));
878 break;
879 }
880 LogFunc(("BDLE%02u is zero length! Skipping. %#RX32 %#RX32\n", pStream->Regs.civ, Bdle.addr, Bdle.ctl_len));
881
882 /* If the buffer has IOC set, make sure it's triggered by the caller. */
883 if (pStream->Regs.bd.ctl_len & AC97_BD_IOC)
884 fSrBcis |= AC97_SR_BCIS;
885 }
886
887 /* 1.2.4.2 PCM Buffer Restrictions (in 302349-003) - #1 */
888 ASSERT_GUEST_MSG(!(pStream->Regs.picb & 1),
889 ("Odd lengths buffers are not allowed: %#x (%d) samples\n", pStream->Regs.picb, pStream->Regs.picb));
890
891 /* 1.2.4.2 PCM Buffer Restrictions (in 302349-003) - #2 */
892 ASSERT_GUEST_MSG(pStream->Regs.picb > 0, ("Zero length buffers not allowed to terminate list (LVI=%u CIV=%u)\n",
893 pStream->Regs.lvi, pStream->Regs.civ));
894
895 return fSrBcis;
896}
897
898#endif /* IN_RING3 */
899
900/**
901 * Updates the status register (SR) of an AC'97 audio stream.
902 *
903 * @param pDevIns The device instance.
904 * @param pThis The shared AC'97 state.
905 * @param pStream AC'97 stream to update SR for.
906 * @param new_sr New value for status register (SR).
907 */
908static void ichac97StreamUpdateSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr)
909{
910 PAC97BMREGS pRegs = &pStream->Regs;
911
912 bool fSignal = false;
913 int iIRQL = 0;
914
915 uint32_t new_mask = new_sr & AC97_SR_INT_MASK;
916 uint32_t old_mask = pRegs->sr & AC97_SR_INT_MASK;
917
918 if (new_mask ^ old_mask)
919 {
920 /** @todo Is IRQ deasserted when only one of status bits is cleared? */
921 if (!new_mask)
922 {
923 fSignal = true;
924 iIRQL = 0;
925 }
926 else if ((new_mask & AC97_SR_LVBCI) && (pRegs->cr & AC97_CR_LVBIE))
927 {
928 fSignal = true;
929 iIRQL = 1;
930 }
931 else if ((new_mask & AC97_SR_BCIS) && (pRegs->cr & AC97_CR_IOCE))
932 {
933 fSignal = true;
934 iIRQL = 1;
935 }
936 }
937
938 pRegs->sr = new_sr;
939
940 LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n",
941 pRegs->sr & AC97_SR_BCIS, pRegs->sr & AC97_SR_LVBCI, pRegs->sr, fSignal, iIRQL));
942
943 if (fSignal)
944 {
945 static uint32_t const s_aMasks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT };
946 Assert(pStream->u8SD < AC97_MAX_STREAMS);
947 if (iIRQL)
948 pThis->glob_sta |= s_aMasks[pStream->u8SD];
949 else
950 pThis->glob_sta &= ~s_aMasks[pStream->u8SD];
951
952 LogFlowFunc(("Setting IRQ level=%d\n", iIRQL));
953 PDMDevHlpPCISetIrq(pDevIns, 0, iIRQL);
954 }
955}
956
957/**
958 * Writes a new value to a stream's status register (SR).
959 *
960 * @param pDevIns The device instance.
961 * @param pThis The shared AC'97 device state.
962 * @param pStream Stream to update SR for.
963 * @param u32Val New value to set the stream's SR to.
964 */
965static void ichac97StreamWriteSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t u32Val)
966{
967 PAC97BMREGS pRegs = &pStream->Regs;
968
969 Log3Func(("[SD%RU8] SR <- %#x (sr %#x)\n", pStream->u8SD, u32Val, pRegs->sr));
970
971 pRegs->sr |= u32Val & ~(AC97_SR_RO_MASK | AC97_SR_WCLEAR_MASK);
972 ichac97StreamUpdateSR(pDevIns, pThis, pStream, pRegs->sr & ~(u32Val & AC97_SR_WCLEAR_MASK));
973}
974
975#ifdef IN_RING3
976
977/**
978 * Returns whether an AC'97 stream is enabled or not.
979 *
980 * @returns VBox status code.
981 * @param pThisCC The ring-3 AC'97 device state.
982 * @param pStream Stream to return status for.
983 */
984static bool ichac97R3StreamIsEnabled(PAC97STATER3 pThisCC, PAC97STREAM pStream)
985{
986 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
987 bool fIsEnabled = pSink && (AudioMixerSinkGetStatus(pSink) & AUDMIXSINK_STS_RUNNING);
988
989 LogFunc(("[SD%RU8] fIsEnabled=%RTbool\n", pStream->u8SD, fIsEnabled));
990 return fIsEnabled;
991}
992
993/**
994 * Enables or disables an AC'97 audio stream.
995 *
996 * @returns VBox status code.
997 * @param pDevIns The device instance.
998 * @param pThis The shared AC'97 state.
999 * @param pThisCC The ring-3 AC'97 state.
1000 * @param pStream The AC'97 stream to enable or disable (shared state).
1001 * @param pStreamCC The ring-3 stream state (matching to @a pStream).
1002 * @param fEnable Whether to enable or disable the stream.
1003 *
1004 */
1005static int ichac97R3StreamEnable(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
1006 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fEnable)
1007{
1008 ichac97R3StreamLock(pStreamCC);
1009 PAUDMIXSINK const pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
1010 AudioMixerSinkLock(pSink);
1011
1012 int rc = VINF_SUCCESS;
1013 if (fEnable)
1014 {
1015 if (pStreamCC->State.pCircBuf)
1016 RTCircBufReset(pStreamCC->State.pCircBuf);
1017
1018 rc = ichac97R3StreamOpen(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fForce */);
1019
1020 /* Re-register the update job with the AIO thread with correct sched hint.
1021 Note! We do not unregister it on disable because of draining. */
1022 if (pStreamCC->State.fRegisteredAsyncUpdateJob)
1023 AudioMixerSinkRemoveUpdateJob(pSink, ichac97R3StreamUpdateAsyncIoJob, pStreamCC);
1024 int rc2 = AudioMixerSinkAddUpdateJob(pSink, ichac97R3StreamUpdateAsyncIoJob, pStreamCC,
1025 pStreamCC->State.Cfg.Device.cMsSchedulingHint);
1026 AssertRC(rc2);
1027 pStreamCC->State.fRegisteredAsyncUpdateJob = RT_SUCCESS(rc2) || rc2 == VERR_ALREADY_EXISTS;
1028
1029 /* Open debug files: */
1030 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1031 { /* likely */ }
1032 else
1033 {
1034 if (!AudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileStream))
1035 {
1036 rc2 = AudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1037 &pStreamCC->State.Cfg.Props);
1038 AssertRC(rc2);
1039 }
1040
1041 if (!AudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileDMA))
1042 {
1043 rc2 = AudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileDMA, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1044 &pStreamCC->State.Cfg.Props);
1045 AssertRC(rc2);
1046 }
1047 }
1048
1049 if (RT_SUCCESS(rc))
1050 rc = AudioMixerSinkStart(pSink);
1051 }
1052 else
1053 {
1054 rc = ichac97R3StreamClose(pStream);
1055 if (RT_SUCCESS(rc))
1056 rc = AudioMixerSinkDrainAndStop(pSink,
1057 pStreamCC->State.pCircBuf ? (uint32_t)RTCircBufUsed(pStreamCC->State.pCircBuf) : 0);
1058 }
1059
1060 /* Make sure to leave the lock before (eventually) starting the timer. */
1061 AudioMixerSinkUnlock(pSink);
1062 ichac97R3StreamUnlock(pStreamCC);
1063 LogFunc(("[SD%RU8] fEnable=%RTbool, rc=%Rrc\n", pStream->u8SD, fEnable, rc));
1064 return rc;
1065}
1066
1067/**
1068 * Resets an AC'97 stream.
1069 *
1070 * @param pThis The shared AC'97 state.
1071 * @param pStream The AC'97 stream to reset (shared).
1072 * @param pStreamCC The AC'97 stream to reset (ring-3).
1073 */
1074static void ichac97R3StreamReset(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1075{
1076 ichac97R3StreamLock(pStreamCC);
1077
1078 LogFunc(("[SD%RU8]\n", pStream->u8SD));
1079
1080 if (pStreamCC->State.pCircBuf)
1081 RTCircBufReset(pStreamCC->State.pCircBuf);
1082
1083 PAC97BMREGS pRegs = &pStream->Regs;
1084
1085 pRegs->bdbar = 0;
1086 pRegs->civ = 0;
1087 pRegs->lvi = 0;
1088
1089 pRegs->picb = 0;
1090 pRegs->piv = 0;
1091 pRegs->cr = pRegs->cr & AC97_CR_DONT_CLEAR_MASK;
1092 pRegs->bd_valid = 0;
1093
1094 RT_ZERO(pThis->silence);
1095
1096 ichac97R3StreamUnlock(pStreamCC);
1097}
1098
1099/**
1100 * Creates an AC'97 audio stream.
1101 *
1102 * @returns VBox status code.
1103 * @param pThisCC The ring-3 AC'97 state.
1104 * @param pStream The AC'97 stream to create (shared).
1105 * @param pStreamCC The AC'97 stream to create (ring-3).
1106 * @param u8SD Stream descriptor number to assign.
1107 */
1108static int ichac97R3StreamCreate(PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint8_t u8SD)
1109{
1110 LogFunc(("[SD%RU8] pStream=%p\n", u8SD, pStream));
1111
1112 AssertReturn(u8SD < AC97_MAX_STREAMS, VERR_INVALID_PARAMETER);
1113 pStream->u8SD = u8SD;
1114 pStreamCC->u8SD = u8SD;
1115
1116 int rc = RTCritSectInit(&pStreamCC->State.CritSect);
1117 AssertRCReturn(rc, rc);
1118
1119 pStreamCC->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
1120
1121 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1122 { /* likely */ }
1123 else
1124 {
1125 char szFile[64];
1126
1127 if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1128 RTStrPrintf(szFile, sizeof(szFile), "ac97StreamWriteSD%RU8", pStream->u8SD);
1129 else
1130 RTStrPrintf(szFile, sizeof(szFile), "ac97StreamReadSD%RU8", pStream->u8SD);
1131
1132 char szPath[RTPATH_MAX];
1133 int rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1134 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
1135 AssertRC(rc2);
1136 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileStream);
1137 AssertRC(rc2);
1138
1139 if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1140 RTStrPrintf(szFile, sizeof(szFile), "ac97DMAWriteSD%RU8", pStream->u8SD);
1141 else
1142 RTStrPrintf(szFile, sizeof(szFile), "ac97DMAReadSD%RU8", pStream->u8SD);
1143
1144 rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1145 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
1146 AssertRC(rc2);
1147
1148 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileDMA);
1149 AssertRC(rc2);
1150
1151 /* Delete stale debugging files from a former run. */
1152 AudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileStream);
1153 AudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileDMA);
1154 }
1155
1156 return rc;
1157}
1158
1159/**
1160 * Destroys an AC'97 audio stream.
1161 *
1162 * @returns VBox status code.
1163 * @param pThisCC The ring-3 AC'97 state.
1164 * @param pStream The AC'97 stream to destroy (shared).
1165 * @param pStreamCC The AC'97 stream to destroy (ring-3).
1166 */
1167static void ichac97R3StreamDestroy(PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1168{
1169 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
1170
1171 ichac97R3StreamClose(pStream);
1172
1173 int rc2 = RTCritSectDelete(&pStreamCC->State.CritSect);
1174 AssertRC(rc2);
1175
1176 if (pStreamCC->State.fRegisteredAsyncUpdateJob)
1177 {
1178 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
1179 if (pSink)
1180 AudioMixerSinkRemoveUpdateJob(pSink, ichac97R3StreamUpdateAsyncIoJob, pStreamCC);
1181 pStreamCC->State.fRegisteredAsyncUpdateJob = false;
1182 }
1183
1184 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1185 { /* likely */ }
1186 else
1187 {
1188 AudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileStream);
1189 pStreamCC->Dbg.Runtime.pFileStream = NULL;
1190
1191 AudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileDMA);
1192 pStreamCC->Dbg.Runtime.pFileDMA = NULL;
1193 }
1194
1195 if (pStreamCC->State.pCircBuf)
1196 {
1197 RTCircBufDestroy(pStreamCC->State.pCircBuf);
1198 pStreamCC->State.pCircBuf = NULL;
1199 }
1200
1201 LogFlowFuncLeave();
1202}
1203
1204/**
1205 * Destroys all AC'97 audio streams of the device.
1206 *
1207 * @param pDevIns The device AC'97 instance.
1208 * @param pThis The shared AC'97 state.
1209 * @param pThisCC The ring-3 AC'97 state.
1210 */
1211static void ichac97R3StreamsDestroy(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC)
1212{
1213 LogFlowFuncEnter();
1214
1215 /*
1216 * Destroy all AC'97 streams.
1217 */
1218 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
1219 ichac97R3StreamDestroy(pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i]);
1220
1221 /*
1222 * Destroy all sinks.
1223 */
1224 if (pThisCC->pSinkLineIn)
1225 {
1226 ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkLineIn, PDMAUDIODIR_IN, PDMAUDIOPATH_IN_LINE);
1227
1228 AudioMixerSinkDestroy(pThisCC->pSinkLineIn, pDevIns);
1229 pThisCC->pSinkLineIn = NULL;
1230 }
1231
1232 if (pThisCC->pSinkMicIn)
1233 {
1234 ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkMicIn, PDMAUDIODIR_IN, PDMAUDIOPATH_IN_MIC);
1235
1236 AudioMixerSinkDestroy(pThisCC->pSinkMicIn, pDevIns);
1237 pThisCC->pSinkMicIn = NULL;
1238 }
1239
1240 if (pThisCC->pSinkOut)
1241 {
1242 ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkOut, PDMAUDIODIR_OUT, PDMAUDIOPATH_OUT_FRONT);
1243
1244 AudioMixerSinkDestroy(pThisCC->pSinkOut, pDevIns);
1245 pThisCC->pSinkOut = NULL;
1246 }
1247}
1248
1249
1250/**
1251 * Input streams: Pulls data from the mixer, putting it in the internal DMA
1252 * buffer.
1253 *
1254 * @param pStreamR3 The AC'97 stream (ring-3 bits).
1255 * @param pSink The mixer sink to pull from.
1256 */
1257static void ichac97R3StreamPullFromMixer(PAC97STREAMR3 pStreamR3, PAUDMIXSINK pSink)
1258{
1259#ifdef LOG_ENABLED
1260 uint64_t const offWriteOld = pStreamR3->State.offWrite;
1261#endif
1262 pStreamR3->State.offWrite = AudioMixerSinkTransferToCircBuf(pSink,
1263 pStreamR3->State.pCircBuf,
1264 pStreamR3->State.offWrite,
1265 pStreamR3->u8SD,
1266 pStreamR3->Dbg.Runtime.fEnabled
1267 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1268
1269 Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1270 pStreamR3->State.offWrite - offWriteOld, pStreamR3->State.offWrite));
1271
1272 /* Update buffer stats. */
1273 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1274}
1275
1276
1277/**
1278 * Output streams: Pushes data to the mixer.
1279 *
1280 * @param pStreamR3 The AC'97 stream (ring-3 bits).
1281 * @param pSink The mixer sink to push to.
1282 */
1283static void ichac97R3StreamPushToMixer(PAC97STREAMR3 pStreamR3, PAUDMIXSINK pSink)
1284{
1285#ifdef LOG_ENABLED
1286 uint64_t const offReadOld = pStreamR3->State.offRead;
1287#endif
1288 pStreamR3->State.offRead = AudioMixerSinkTransferFromCircBuf(pSink,
1289 pStreamR3->State.pCircBuf,
1290 pStreamR3->State.offRead,
1291 pStreamR3->u8SD,
1292 pStreamR3->Dbg.Runtime.fEnabled
1293 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1294
1295 Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1296 pStreamR3->State.offRead - offReadOld, pStreamR3->State.offRead));
1297
1298 /* Update buffer stats. */
1299 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1300}
1301
1302
1303/**
1304 * Updates an AC'97 stream by doing its DMA transfers.
1305 *
1306 * The host sink(s) set the overall pace (bird: no it doesn't, the DMA timer
1307 * does - we just hope like heck it matches the speed at which the *backend*
1308 * host audio driver processes samples).
1309 *
1310 * @param pDevIns The device instance.
1311 * @param pThis The shared AC'97 state.
1312 * @param pThisCC The ring-3 AC'97 state.
1313 * @param pStream The AC'97 stream to update (shared).
1314 * @param pStreamCC The AC'97 stream to update (ring-3).
1315 */
1316static void ichac97R3StreamUpdateDma(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
1317 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1318{
1319 /*
1320 * Make sure we're running and got an active mixer sink.
1321 */
1322 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD); /** @todo caller will need + check this too afterwards... */
1323 AssertPtr(pSink);
1324 if (RT_LIKELY(AudioMixerSinkIsActive(pSink)))
1325 { /* likely */ }
1326 else
1327 return;
1328
1329 int rc2;
1330
1331 /*
1332 * Output streams (SDO).
1333 */
1334 if (pStreamCC->State.Cfg.enmDir == PDMAUDIODIR_OUT)
1335 {
1336 uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1337 if (cbStreamFree)
1338 { /* likely */ }
1339 else
1340 {
1341 /** @todo Record this as a statistic. Try make some space available. */
1342 }
1343 if (cbStreamFree)
1344 {
1345 Log3Func(("[SD%RU8] PICB=%zu (%RU64ms), cbFree=%zu (%RU64ms), cbTransferChunk=%zu (%RU64ms)\n",
1346 pStream->u8SD,
1347 (pStream->Regs.picb << 1), PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, pStream->Regs.picb << 1),
1348 cbStreamFree, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, cbStreamFree),
1349 pStreamCC->State.cbTransferChunk, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, pStreamCC->State.cbTransferChunk)));
1350
1351 /* Do the DMA transfer. */
1352 rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC,
1353 RT_MIN(pStreamCC->State.cbTransferChunk, cbStreamFree));
1354 AssertRC(rc2);
1355
1356 pStreamCC->State.tsLastUpdateNs = RTTimeNanoTS();
1357 }
1358
1359 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
1360 AssertRC(rc2);
1361 }
1362 else /* Input (SDI). */
1363 {
1364#if 0 /* bird: I just love when crusial code like this with no explanation. This just causing AIO
1365 * skipping a DMA timer cycle if the timer callback is a bit quicker than the 'hint' (see HDA/9890). */
1366 const uint64_t tsNowNs = RTTimeNanoTS();
1367 if (tsNowNs - pStreamCC->State.tsLastUpdateNs >= pStreamCC->State.Cfg.Device.cMsSchedulingHint * RT_NS_1MS)
1368 {
1369 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
1370 AssertRC(rc2);
1371
1372 pStreamCC->State.tsLastUpdateNs = tsNowNs;
1373 }
1374#endif
1375
1376 uint32_t cbStreamUsed = ichac97R3StreamGetUsed(pStreamCC);
1377 if (cbStreamUsed)
1378 { /* likey */ }
1379 else
1380 {
1381 /** @todo Record this as a statistic. Try pull some data into the DMA buffer.*/
1382 }
1383
1384 if (cbStreamUsed)
1385 {
1386 /* When running synchronously, do the DMA data transfers here.
1387 * Otherwise this will be done in the stream's async I/O thread. */
1388 rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC, cbStreamUsed);
1389 AssertRC(rc2);
1390 }
1391
1392 /*
1393 * We should always kick the AIO thread.
1394 */
1395 /** @todo This isn't entirely ideal. If we get into an underrun situation,
1396 * we ideally want the AIO thread to run right before the DMA timer
1397 * rather than right after it ran. */
1398 Log5Func(("Notifying AIO thread\n"));
1399 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
1400 AssertRC(rc2);
1401 pStreamCC->State.tsLastUpdateNs = RTTimeNanoTS();
1402 }
1403}
1404
1405
1406/**
1407 * @callback_method_impl{FNAUDMIXSINKUPDATE}
1408 *
1409 * For output streams this moves data from the internal DMA buffer (in which
1410 * ichac97R3StreamUpdateDma put it), thru the mixer and to the various backend
1411 * audio devices.
1412 *
1413 * For input streams this pulls data from the backend audio device(s), thru the
1414 * mixer and puts it in the internal DMA buffer ready for
1415 * ichac97R3StreamUpdateDma to pump into guest memory.
1416 */
1417static DECLCALLBACK(void) ichac97R3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser)
1418{
1419 PAC97STATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
1420 PAC97STREAMR3 const pStreamCC = (PAC97STREAMR3)pvUser;
1421 Assert(pStreamCC->u8SD == (uintptr_t)(pStreamCC - &pThisCC->aStreams[0]));
1422 Assert(pSink == ichac97R3IndexToSink(pThisCC, pStreamCC->u8SD));
1423 RT_NOREF(pThisCC);
1424
1425 /*
1426 * Output (SDO).
1427 */
1428 if (pStreamCC->State.Cfg.enmDir == PDMAUDIODIR_OUT)
1429 ichac97R3StreamPushToMixer(pStreamCC, pSink);
1430 /*
1431 * Input (SDI).
1432 */
1433 else
1434 ichac97R3StreamPullFromMixer(pStreamCC, pSink);
1435}
1436
1437#endif /* IN_RING3 */
1438
1439/**
1440 * Sets a AC'97 mixer control to a specific value.
1441 *
1442 * @returns VBox status code.
1443 * @param pThis The shared AC'97 state.
1444 * @param uMixerIdx Mixer control to set value for.
1445 * @param uVal Value to set.
1446 */
1447static void ichac97MixerSet(PAC97STATE pThis, uint8_t uMixerIdx, uint16_t uVal)
1448{
1449 AssertMsgReturnVoid(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1450 ("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)));
1451
1452 LogRel2(("AC97: Setting mixer index #%RU8 to %RU16 (%RU8 %RU8)\n",
1453 uMixerIdx, uVal, RT_HI_U8(uVal), RT_LO_U8(uVal)));
1454
1455 pThis->mixer_data[uMixerIdx + 0] = RT_LO_U8(uVal);
1456 pThis->mixer_data[uMixerIdx + 1] = RT_HI_U8(uVal);
1457}
1458
1459/**
1460 * Gets a value from a specific AC'97 mixer control.
1461 *
1462 * @returns Retrieved mixer control value.
1463 * @param pThis The shared AC'97 state.
1464 * @param uMixerIdx Mixer control to get value for.
1465 */
1466static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t uMixerIdx)
1467{
1468 AssertMsgReturn(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1469 ("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)),
1470 UINT16_MAX);
1471 return RT_MAKE_U16(pThis->mixer_data[uMixerIdx + 0], pThis->mixer_data[uMixerIdx + 1]);
1472}
1473
1474#ifdef IN_RING3
1475
1476/**
1477 * Retrieves a specific driver stream of a AC'97 driver.
1478 *
1479 * @returns Pointer to driver stream if found, or NULL if not found.
1480 * @param pDrv Driver to retrieve driver stream for.
1481 * @param enmDir Stream direction to retrieve.
1482 * @param enmPath Stream destination / source to retrieve.
1483 */
1484static PAC97DRIVERSTREAM ichac97R3MixerGetDrvStream(PAC97DRIVER pDrv, PDMAUDIODIR enmDir, PDMAUDIOPATH enmPath)
1485{
1486 PAC97DRIVERSTREAM pDrvStream = NULL;
1487
1488 if (enmDir == PDMAUDIODIR_IN)
1489 {
1490 LogFunc(("enmRecSource=%d\n", enmPath));
1491
1492 switch (enmPath)
1493 {
1494 case PDMAUDIOPATH_IN_LINE:
1495 pDrvStream = &pDrv->LineIn;
1496 break;
1497 case PDMAUDIOPATH_IN_MIC:
1498 pDrvStream = &pDrv->MicIn;
1499 break;
1500 default:
1501 AssertFailed();
1502 break;
1503 }
1504 }
1505 else if (enmDir == PDMAUDIODIR_OUT)
1506 {
1507 LogFunc(("enmPlaybackDst=%d\n", enmPath));
1508
1509 switch (enmPath)
1510 {
1511 case PDMAUDIOPATH_OUT_FRONT:
1512 pDrvStream = &pDrv->Out;
1513 break;
1514 default:
1515 AssertFailed();
1516 break;
1517 }
1518 }
1519 else
1520 AssertFailed();
1521
1522 return pDrvStream;
1523}
1524
1525/**
1526 * Adds a driver stream to a specific mixer sink.
1527 *
1528 * @returns VBox status code.
1529 * @param pDevIns The device instance.
1530 * @param pMixSink Mixer sink to add driver stream to.
1531 * @param pCfg Stream configuration to use.
1532 * @param pDrv Driver stream to add.
1533 */
1534static int ichac97R3MixerAddDrvStream(PPDMDEVINS pDevIns, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PAC97DRIVER pDrv)
1535{
1536 AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1537
1538 PPDMAUDIOSTREAMCFG pStreamCfg = PDMAudioStrmCfgDup(pCfg);
1539 if (!pStreamCfg)
1540 return VERR_NO_MEMORY;
1541
1542 AssertCompile(sizeof(pStreamCfg->szName) == sizeof(pCfg->szName));
1543 RTStrCopy(pStreamCfg->szName, sizeof(pStreamCfg->szName), pCfg->szName);
1544
1545 LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
1546
1547 int rc;
1548
1549 PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, pStreamCfg->enmDir, pStreamCfg->enmPath);
1550 if (pDrvStream)
1551 {
1552 AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
1553
1554 PAUDMIXSTREAM pMixStrm;
1555 rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, pDevIns, &pMixStrm);
1556 LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1557 if (RT_SUCCESS(rc))
1558 {
1559 rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
1560 LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1561 if (RT_FAILURE(rc))
1562 AudioMixerStreamDestroy(pMixStrm, pDevIns, true /*fImmediate*/);
1563 }
1564
1565 if (RT_SUCCESS(rc))
1566 pDrvStream->pMixStrm = pMixStrm;
1567 }
1568 else
1569 rc = VERR_INVALID_PARAMETER;
1570
1571 PDMAudioStrmCfgFree(pStreamCfg);
1572
1573 LogFlowFuncLeaveRC(rc);
1574 return rc;
1575}
1576
1577/**
1578 * Adds all current driver streams to a specific mixer sink.
1579 *
1580 * @returns VBox status code.
1581 * @param pDevIns The device instance.
1582 * @param pThisCC The ring-3 AC'97 state.
1583 * @param pMixSink Mixer sink to add stream to.
1584 * @param pCfg Stream configuration to use.
1585 */
1586static int ichac97R3MixerAddDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
1587{
1588 AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1589
1590 if (!AudioHlpStreamCfgIsValid(pCfg))
1591 return VERR_INVALID_PARAMETER;
1592
1593 int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
1594 if (RT_FAILURE(rc))
1595 return rc;
1596
1597 PAC97DRIVER pDrv;
1598 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
1599 {
1600 int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pMixSink, pCfg, pDrv);
1601 if (RT_FAILURE(rc2))
1602 LogFunc(("Attaching stream failed with %Rrc\n", rc2));
1603
1604 /* Do not pass failure to rc here, as there might be drivers which aren't
1605 * configured / ready yet. */
1606 }
1607
1608 LogFlowFuncLeaveRC(rc);
1609 return rc;
1610}
1611
1612/**
1613 * Adds a specific AC'97 driver to the driver chain.
1614 *
1615 * @returns VBox status code.
1616 * @param pDevIns The device instance.
1617 * @param pThisCC The ring-3 AC'97 device state.
1618 * @param pDrv The AC'97 driver to add.
1619 */
1620static int ichac97R3MixerAddDrv(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
1621{
1622 int rc = VINF_SUCCESS;
1623
1624 if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg))
1625 rc = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkLineIn,
1626 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg, pDrv);
1627
1628 if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg))
1629 {
1630 int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkOut,
1631 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg, pDrv);
1632 if (RT_SUCCESS(rc))
1633 rc = rc2;
1634 }
1635
1636 if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg))
1637 {
1638 int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkMicIn,
1639 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg, pDrv);
1640 if (RT_SUCCESS(rc))
1641 rc = rc2;
1642 }
1643
1644 return rc;
1645}
1646
1647/**
1648 * Removes a specific AC'97 driver from the driver chain and destroys its
1649 * associated streams.
1650 *
1651 * @param pDevIns The device instance.
1652 * @param pThisCC The ring-3 AC'97 device state.
1653 * @param pDrv AC'97 driver to remove.
1654 */
1655static void ichac97R3MixerRemoveDrv(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
1656{
1657 if (pDrv->MicIn.pMixStrm)
1658 {
1659 AudioMixerSinkRemoveStream(pThisCC->pSinkMicIn, pDrv->MicIn.pMixStrm);
1660 AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm, pDevIns, true /*fImmediate*/);
1661 pDrv->MicIn.pMixStrm = NULL;
1662 }
1663
1664 if (pDrv->LineIn.pMixStrm)
1665 {
1666 AudioMixerSinkRemoveStream(pThisCC->pSinkLineIn, pDrv->LineIn.pMixStrm);
1667 AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm, pDevIns, true /*fImmediate*/);
1668 pDrv->LineIn.pMixStrm = NULL;
1669 }
1670
1671 if (pDrv->Out.pMixStrm)
1672 {
1673 AudioMixerSinkRemoveStream(pThisCC->pSinkOut, pDrv->Out.pMixStrm);
1674 AudioMixerStreamDestroy(pDrv->Out.pMixStrm, pDevIns, true /*fImmediate*/);
1675 pDrv->Out.pMixStrm = NULL;
1676 }
1677
1678 RTListNodeRemove(&pDrv->Node);
1679}
1680
1681/**
1682 * Removes a driver stream from a specific mixer sink.
1683 *
1684 * @param pDevIns The device instance.
1685 * @param pMixSink Mixer sink to remove audio streams from.
1686 * @param enmDir Stream direction to remove.
1687 * @param enmPath Stream destination / source to remove.
1688 * @param pDrv Driver stream to remove.
1689 */
1690static void ichac97R3MixerRemoveDrvStream(PPDMDEVINS pDevIns, PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir,
1691 PDMAUDIOPATH enmPath, PAC97DRIVER pDrv)
1692{
1693 PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, enmDir, enmPath);
1694 if (pDrvStream)
1695 {
1696 if (pDrvStream->pMixStrm)
1697 {
1698 AudioMixerSinkRemoveStream(pMixSink, pDrvStream->pMixStrm);
1699
1700 AudioMixerStreamDestroy(pDrvStream->pMixStrm, pDevIns, false /*fImmediate*/);
1701 pDrvStream->pMixStrm = NULL;
1702 }
1703 }
1704}
1705
1706/**
1707 * Removes all driver streams from a specific mixer sink.
1708 *
1709 * @param pDevIns The device instance.
1710 * @param pThisCC The ring-3 AC'97 state.
1711 * @param pMixSink Mixer sink to remove audio streams from.
1712 * @param enmDir Stream direction to remove.
1713 * @param enmPath Stream destination / source to remove.
1714 */
1715static void ichac97R3MixerRemoveDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
1716 PDMAUDIODIR enmDir, PDMAUDIOPATH enmPath)
1717{
1718 AssertPtrReturnVoid(pMixSink);
1719
1720 PAC97DRIVER pDrv;
1721 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
1722 {
1723 ichac97R3MixerRemoveDrvStream(pDevIns, pMixSink, enmDir, enmPath, pDrv);
1724 }
1725}
1726
1727
1728/**
1729 * Updates the next transfer based on a specific amount of bytes.
1730 *
1731 * @param pDevIns The device instance.
1732 * @param pStream The AC'97 stream to update (shared).
1733 * @param pStreamCC The AC'97 stream to update (ring-3).
1734 */
1735static void ichac97R3StreamTransferUpdate(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1736{
1737 /*
1738 * Get the number of bytes left in the current buffer.
1739 *
1740 * This isn't entirely optimal iff the current entry doesn't have IOC set, in
1741 * that case we should use the number of bytes to the next IOC. Unfortuantely,
1742 * it seems the spec doesn't allow us to prefetch more than one BDLE, so we
1743 * probably cannot look ahead without violating that restriction. This is
1744 * probably a purely theoretical problem at this point.
1745 */
1746 uint32_t const cbLeftInBdle = pStream->Regs.picb * PDMAudioPropsSampleSize(&pStreamCC->State.Cfg.Props);
1747 if (cbLeftInBdle > 0) /** @todo r=bird: see todo about this in ichac97R3StreamFetchBDLE. */
1748 {
1749 /*
1750 * Since the buffer can be up to 0xfffe samples long (frame aligning stereo
1751 * prevents 0xffff), which translates to 743ms at a 44.1kHz rate, we must
1752 * also take the nominal timer frequency into account here so we keep
1753 * moving data at a steady rate. (In theory, I think the guest can even
1754 * set up just one buffer and anticipate where we are in the buffer
1755 * processing when it writes/reads from it. Linux seems to be doing such
1756 * configs when not playing or something.)
1757 */
1758 uint32_t const cbMaxPerHz = PDMAudioPropsNanoToBytes(&pStreamCC->State.Cfg.Props, RT_NS_1SEC / pStreamCC->State.uTimerHz);
1759
1760 if (cbLeftInBdle <= cbMaxPerHz)
1761 pStreamCC->State.cbTransferChunk = cbLeftInBdle;
1762 /* Try avoid leaving a very short period at the end of a buffer. */
1763 else if (cbLeftInBdle >= cbMaxPerHz + cbMaxPerHz / 2)
1764 pStreamCC->State.cbTransferChunk = cbMaxPerHz;
1765 else
1766 pStreamCC->State.cbTransferChunk = PDMAudioPropsFloorBytesToFrame(&pStreamCC->State.Cfg.Props, cbLeftInBdle / 2);
1767
1768 /*
1769 * Translate the chunk size to timer ticks.
1770 */
1771 uint64_t const cNsXferChunk = PDMAudioPropsBytesToNano(&pStreamCC->State.Cfg.Props, pStreamCC->State.cbTransferChunk);
1772 pStreamCC->State.cTransferTicks = PDMDevHlpTimerFromNano(pDevIns, pStream->hTimer, cNsXferChunk);
1773 Assert(pStreamCC->State.cTransferTicks > 0);
1774
1775 Log3Func(("[SD%RU8] cbLeftInBdle=%#RX32 cbMaxPerHz=%#RX32 (%RU16Hz) -> cbTransferChunk=%#RX32 cTransferTicks=%RX64\n",
1776 pStream->u8SD, cbLeftInBdle, cbMaxPerHz, pStreamCC->State.uTimerHz,
1777 pStreamCC->State.cbTransferChunk, pStreamCC->State.cTransferTicks));
1778 }
1779}
1780
1781
1782/**
1783 * Gets the frequency of a given stream.
1784 *
1785 * @returns The frequency. Zero if invalid stream index.
1786 * @param pThis The shared AC'97 device state.
1787 * @param idxStream The stream.
1788 */
1789DECLINLINE(uint32_t) ichach97R3CalcStreamHz(PAC97STATE pThis, uint8_t idxStream)
1790{
1791 switch (idxStream)
1792 {
1793 case AC97SOUNDSOURCE_PI_INDEX:
1794 return ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate);
1795
1796 case AC97SOUNDSOURCE_MC_INDEX:
1797 return ichac97MixerGet(pThis, AC97_MIC_ADC_Rate);
1798
1799 case AC97SOUNDSOURCE_PO_INDEX:
1800 return ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate);
1801
1802 default:
1803 AssertMsgFailedReturn(("%d\n", idxStream), 0);
1804 }
1805}
1806
1807
1808/**
1809 * Gets the PCM properties for a given stream.
1810 *
1811 * @returns pProps.
1812 * @param pThis The shared AC'97 device state.
1813 * @param idxStream Which stream
1814 * @param pProps Where to return the stream properties.
1815 */
1816DECLINLINE(PPDMAUDIOPCMPROPS) ichach97R3CalcStreamProps(PAC97STATE pThis, uint8_t idxStream, PPDMAUDIOPCMPROPS pProps)
1817{
1818 PDMAudioPropsInit(pProps, 2 /*16-bit*/, true /*signed*/, 2 /*stereo*/, ichach97R3CalcStreamHz(pThis, idxStream));
1819 return pProps;
1820}
1821
1822
1823/**
1824 * Opens an AC'97 stream with its current mixer settings.
1825 *
1826 * This will open an AC'97 stream with 2 (stereo) channels, 16-bit samples and
1827 * the last set sample rate in the AC'97 mixer for this stream.
1828 *
1829 * @returns VBox status code.
1830 * @param pDevIns The device instance.
1831 * @param pThis The shared AC'97 device state (shared).
1832 * @param pThisCC The shared AC'97 device state (ring-3).
1833 * @param pStream The AC'97 stream to open (shared).
1834 * @param pStreamCC The AC'97 stream to open (ring-3).
1835 * @param fForce Whether to force re-opening the stream or not.
1836 * Otherwise re-opening only will happen if the PCM properties have changed.
1837 */
1838static int ichac97R3StreamOpen(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
1839 PAC97STREAMR3 pStreamCC, bool fForce)
1840{
1841 /*
1842 * Assemble the stream config and get the associate mixer sink.
1843 */
1844 PDMAUDIOPCMPROPS PropsTmp;
1845 PDMAUDIOSTREAMCFG Cfg;
1846 PDMAudioStrmCfgInitWithProps(&Cfg, ichach97R3CalcStreamProps(pThis, pStream->u8SD, &PropsTmp));
1847
1848 PAUDMIXSINK pMixSink;
1849 switch (pStream->u8SD)
1850 {
1851 case AC97SOUNDSOURCE_PI_INDEX:
1852 Cfg.enmDir = PDMAUDIODIR_IN;
1853 Cfg.enmPath = PDMAUDIOPATH_IN_LINE;
1854 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Line-In");
1855
1856 pMixSink = pThisCC->pSinkLineIn;
1857 break;
1858
1859 case AC97SOUNDSOURCE_MC_INDEX:
1860 Cfg.enmDir = PDMAUDIODIR_IN;
1861 Cfg.enmPath = PDMAUDIOPATH_IN_MIC;
1862 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Mic-In");
1863
1864 pMixSink = pThisCC->pSinkMicIn;
1865 break;
1866
1867 case AC97SOUNDSOURCE_PO_INDEX:
1868 Cfg.enmDir = PDMAUDIODIR_OUT;
1869 Cfg.enmPath = PDMAUDIOPATH_OUT_FRONT;
1870 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Output");
1871
1872 pMixSink = pThisCC->pSinkOut;
1873 break;
1874
1875 default:
1876 AssertMsgFailedReturn(("u8SD=%d\n", pStream->u8SD), VERR_INTERNAL_ERROR_3);
1877 }
1878
1879 /*
1880 * Read the buffer descriptors and check what the max distance between
1881 * interrupts are, so we can more correctly size the internal DMA buffer.
1882 *
1883 * Note! The buffer list are not fixed once the stream starts running as
1884 * with HDA, so this is just a general idea of what the guest is
1885 * up to and we cannot really make much of a plan out of it.
1886 */
1887 /** @todo This is wrong! The valid range is CVI thru LVI. However, CVI is
1888 * typically reset to zero, I guess... */
1889 AC97BDLE aBdl[AC97_MAX_BDLE];
1890 RT_ZERO(aBdl);
1891 unsigned const cBuffers = pStream->Regs.lvi + 1;
1892 PDMDevHlpPCIPhysRead(pDevIns, pStream->Regs.bdbar, aBdl, sizeof(aBdl[0]) * cBuffers);
1893
1894 uint32_t cSamplesMax = 0;
1895 uint32_t cSamplesMin = UINT32_MAX;
1896 uint32_t cSamplesCur = 0;
1897 uint32_t cSamplesTotal = 0;
1898 for (unsigned i = 0; i < cBuffers; i++)
1899 {
1900 cSamplesCur += aBdl[0].ctl_len & AC97_BD_LEN_MASK;
1901 cSamplesTotal += aBdl[0].ctl_len & AC97_BD_LEN_MASK;
1902 if (aBdl[0].ctl_len & AC97_BD_IOC)
1903 {
1904 if (cSamplesCur > cSamplesMax)
1905 cSamplesMax = cSamplesCur;
1906 if (cSamplesCur < cSamplesMin)
1907 cSamplesMin = cSamplesCur;
1908 cSamplesCur = 0;
1909 }
1910 }
1911
1912 if (cSamplesCur && cSamplesMax != 0)
1913 {
1914 LogFlowFunc(("Tail buffer w/o IOC, loops.\n"));
1915 for (unsigned i = 0; i < cBuffers; i++)
1916 {
1917 cSamplesCur += aBdl[0].ctl_len & AC97_BD_LEN_MASK;
1918 if (aBdl[0].ctl_len & AC97_BD_IOC)
1919 {
1920 if (cSamplesCur > cSamplesMax)
1921 cSamplesMax = cSamplesCur;
1922 if (cSamplesCur < cSamplesMin)
1923 cSamplesMin = cSamplesCur;
1924 cSamplesCur = 0;
1925 break;
1926 }
1927 }
1928 }
1929
1930 uint32_t const cbDmaMinBuf = cSamplesMax * PDMAudioPropsSampleSize(&Cfg.Props) * 3; /* see further down */
1931 uint32_t const cMsDmaMinBuf = PDMAudioPropsBytesToMilli(&Cfg.Props, cbDmaMinBuf);
1932 LogRel3(("AC97: [SD%RU8] buffer length stats: total=%#x in %u buffers, min=%#x, max=%#x => min DMA buffer %u ms / %#x bytes\n",
1933 pStream->u8SD, cSamplesTotal, cBuffers, cSamplesMin, cSamplesMax, cMsDmaMinBuf, cbDmaMinBuf));
1934
1935 /*
1936 * Only (re-)create the stream (and driver chain) if we really have to.
1937 * Otherwise avoid this and just reuse it, as this costs performance.
1938 */
1939 int rc = VINF_SUCCESS;
1940 if ( fForce
1941 || !PDMAudioStrmCfgMatchesProps(&Cfg, &pStreamCC->State.Cfg.Props)
1942 || !pStreamCC->State.pCircBuf
1943 || cbDmaMinBuf > RTCircBufSize(pStreamCC->State.pCircBuf))
1944 {
1945 LogRel2(("AC97: (Re-)Opening stream '%s' (%RU32Hz, %RU8 channels, %s%RU8)\n", Cfg.szName, Cfg.Props.uHz,
1946 PDMAudioPropsChannels(&Cfg.Props), Cfg.Props.fSigned ? "S" : "U", PDMAudioPropsSampleBits(&Cfg.Props)));
1947
1948 LogFlowFunc(("[SD%RU8] uHz=%RU32\n", pStream->u8SD, Cfg.Props.uHz));
1949
1950 if (Cfg.Props.uHz)
1951 {
1952 Assert(Cfg.enmDir != PDMAUDIODIR_UNKNOWN);
1953
1954 /*
1955 * Set the stream's timer Hz rate, based on the PCM properties Hz rate.
1956 */
1957 if (pThis->uTimerHz == AC97_TIMER_HZ_DEFAULT) /* Make sure that we don't have any custom Hz rate set we want to enforce */
1958 {
1959 if (Cfg.Props.uHz > 44100) /* E.g. 48000 Hz. */
1960 pStreamCC->State.uTimerHz = 200;
1961 else /* Just take the global Hz rate otherwise. */
1962 pStreamCC->State.uTimerHz = pThis->uTimerHz;
1963 }
1964 else
1965 pStreamCC->State.uTimerHz = pThis->uTimerHz;
1966
1967 if ( pStreamCC->State.uTimerHz >= 10
1968 && pStreamCC->State.uTimerHz <= 500)
1969 { /* likely */ }
1970 else
1971 {
1972 LogFunc(("[SD%RU8] Adjusting uTimerHz=%u to %u\n", pStream->u8SD, pStreamCC->State.uTimerHz,
1973 Cfg.Props.uHz > 44100 ? 200 : AC97_TIMER_HZ_DEFAULT));
1974 pStreamCC->State.uTimerHz = Cfg.Props.uHz > 44100 ? 200 : AC97_TIMER_HZ_DEFAULT;
1975 }
1976
1977 /* Set scheduling hint. */
1978 Cfg.Device.cMsSchedulingHint = RT_MS_1SEC / pStreamCC->State.uTimerHz;
1979
1980 /*
1981 * Re-create the circular buffer if necessary.
1982 *
1983 * As mentioned in the HDA code, this should be at least able to hold the
1984 * data transferred in three DMA periods and in three AIO period (whichever
1985 * is higher). However, if we assume that the DMA code will engage the DMA
1986 * timer thread (currently EMT) if the AIO thread isn't getting schduled to
1987 * transfer data thru the stack, we don't need to go overboard and double
1988 * the minimums here. The less buffer the less possible delay can build when
1989 * TM is doing catch up.
1990 */
1991 uint32_t cMsCircBuf = Cfg.enmDir == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut;
1992 cMsCircBuf = RT_MAX(cMsCircBuf, cMsDmaMinBuf);
1993 cMsCircBuf = RT_MAX(cMsCircBuf, Cfg.Device.cMsSchedulingHint * 3);
1994 cMsCircBuf = RT_MIN(cMsCircBuf, RT_MS_1SEC * 2); /** @todo make sure the DMA timer doesn't go over 500ms (use uTimerHz as max, really). */
1995 uint32_t const cbCircBuf = PDMAudioPropsMilliToBytes(&Cfg.Props, cMsCircBuf);
1996
1997 if (pStreamCC->State.pCircBuf && RTCircBufSize(pStreamCC->State.pCircBuf) == cbCircBuf)
1998 RTCircBufReset(pStreamCC->State.pCircBuf);
1999 else
2000 {
2001 LogFlowFunc(("Re-creating circular buffer with size %u ms / %#x bytes (was %#x); cMsSchedulingHint=%u cMsDmaMinBuf=%u cMsCircBufXxx=%u\n",
2002 cMsCircBuf, cbCircBuf, pStreamCC->State.StatDmaBufSize, Cfg.Device.cMsSchedulingHint, cMsDmaMinBuf,
2003 Cfg.enmDir == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut));
2004 if (pStreamCC->State.pCircBuf)
2005 RTCircBufDestroy(pStreamCC->State.pCircBuf);
2006
2007 rc = RTCircBufCreate(&pStreamCC->State.pCircBuf, cbCircBuf);
2008 AssertRCReturnStmt(rc, pStreamCC->State.pCircBuf = NULL, rc);
2009
2010 pStreamCC->State.StatDmaBufSize = (uint32_t)RTCircBufSize(pStreamCC->State.pCircBuf);
2011 }
2012 Assert(pStreamCC->State.StatDmaBufSize == cbCircBuf);
2013
2014 /*
2015 * <there should be a comment here>
2016 */
2017 ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pMixSink, Cfg.enmDir, Cfg.enmPath);
2018 rc = ichac97R3MixerAddDrvStreams(pDevIns, pThisCC, pMixSink, &Cfg);
2019 if (RT_SUCCESS(rc))
2020 rc = PDMAudioStrmCfgCopy(&pStreamCC->State.Cfg, &Cfg);
2021 }
2022 LogFlowFunc(("[SD%RU8] rc=%Rrc\n", pStream->u8SD, rc));
2023 }
2024 else
2025 LogFlowFunc(("[SD%RU8] Skipping (re-)creation\n", pStream->u8SD));
2026 return rc;
2027}
2028
2029/**
2030 * Closes an AC'97 stream.
2031 *
2032 * @returns VBox status code.
2033 * @param pStream The AC'97 stream to close (shared).
2034 */
2035static int ichac97R3StreamClose(PAC97STREAM pStream)
2036{
2037 RT_NOREF(pStream);
2038 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2039 return VINF_SUCCESS;
2040}
2041
2042/**
2043 * Re-opens (that is, closes and opens again) an AC'97 stream on the backend
2044 * side with the current AC'97 mixer settings for this stream.
2045 *
2046 * @returns VBox status code.
2047 * @param pDevIns The device instance.
2048 * @param pThis The shared AC'97 device state.
2049 * @param pThisCC The ring-3 AC'97 device state.
2050 * @param pStream The AC'97 stream to re-open (shared).
2051 * @param pStreamCC The AC'97 stream to re-open (ring-3).
2052 * @param fForce Whether to force re-opening the stream or not.
2053 * Otherwise re-opening only will happen if the PCM properties have changed.
2054 */
2055static int ichac97R3StreamReOpen(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
2056 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2057{
2058 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2059 Assert(pStream->u8SD == pStreamCC->u8SD);
2060 Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2061 Assert(pStreamCC - &pThisCC->aStreams[0] == pStream->u8SD);
2062
2063 int rc = ichac97R3StreamClose(pStream);
2064 if (RT_SUCCESS(rc))
2065 rc = ichac97R3StreamOpen(pDevIns, pThis, pThisCC, pStream, pStreamCC, fForce);
2066
2067 return rc;
2068}
2069
2070/**
2071 * Locks an AC'97 stream for serialized access.
2072 *
2073 * @returns VBox status code.
2074 * @param pStreamCC The AC'97 stream to lock (ring-3).
2075 */
2076static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC)
2077{
2078 int rc2 = RTCritSectEnter(&pStreamCC->State.CritSect);
2079 AssertRC(rc2);
2080}
2081
2082/**
2083 * Unlocks a formerly locked AC'97 stream.
2084 *
2085 * @returns VBox status code.
2086 * @param pStreamCC The AC'97 stream to unlock (ring-3).
2087 */
2088static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC)
2089{
2090 int rc2 = RTCritSectLeave(&pStreamCC->State.CritSect);
2091 AssertRC(rc2);
2092}
2093
2094/**
2095 * Retrieves the available size of (buffered) audio data (in bytes) of a given AC'97 stream.
2096 *
2097 * @returns Available data (in bytes).
2098 * @param pStreamCC The AC'97 stream to retrieve size for (ring-3).
2099 */
2100static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC)
2101{
2102 if (!pStreamCC->State.pCircBuf)
2103 return 0;
2104
2105 return (uint32_t)RTCircBufUsed(pStreamCC->State.pCircBuf);
2106}
2107
2108/**
2109 * Retrieves the free size of audio data (in bytes) of a given AC'97 stream.
2110 *
2111 * @returns Free data (in bytes).
2112 * @param pStreamCC AC'97 stream to retrieve size for (ring-3).
2113 */
2114static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC)
2115{
2116 if (!pStreamCC->State.pCircBuf)
2117 return 0;
2118
2119 return (uint32_t)RTCircBufFree(pStreamCC->State.pCircBuf);
2120}
2121
2122/**
2123 * Sets the volume of a specific AC'97 mixer control.
2124 *
2125 * This currently only supports attenuation -- gain support is currently not implemented.
2126 *
2127 * @returns VBox status code.
2128 * @param pThis The shared AC'97 state.
2129 * @param pThisCC The ring-3 AC'97 state.
2130 * @param index AC'97 mixer index to set volume for.
2131 * @param enmMixerCtl Corresponding audio mixer sink.
2132 * @param uVal Volume value to set.
2133 */
2134static int ichac97R3MixerSetVolume(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2135{
2136 /*
2137 * From AC'97 SoundMax Codec AD1981A/AD1981B:
2138 * "Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the
2139 * D5 or D13 bits are set to 1, their respective lower five volume bits are automatically
2140 * set to 1 by the Codec logic. On readback, all lower 5 bits will read ones whenever
2141 * these bits are set to 1."
2142 *
2143 * Linux ALSA depends on this behavior to detect that only 5 bits are used for volume
2144 * control and the optional 6th bit is not used. Note that this logic only applies to the
2145 * master volume controls.
2146 */
2147 if (index == AC97_Master_Volume_Mute || index == AC97_Headphone_Volume_Mute || index == AC97_Master_Volume_Mono_Mute)
2148 {
2149 if (uVal & RT_BIT(5)) /* D5 bit set? */
2150 uVal |= RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0);
2151 if (uVal & RT_BIT(13)) /* D13 bit set? */
2152 uVal |= RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8);
2153 }
2154
2155 const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2156 uint8_t uCtlAttLeft = (uVal >> 8) & AC97_BARS_VOL_MASK;
2157 uint8_t uCtlAttRight = uVal & AC97_BARS_VOL_MASK;
2158
2159 /* For the master and headphone volume, 0 corresponds to 0dB attenuation. For the other
2160 * volume controls, 0 means 12dB gain and 8 means unity gain.
2161 */
2162 if (index != AC97_Master_Volume_Mute && index != AC97_Headphone_Volume_Mute)
2163 {
2164# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2165 /* NB: Currently there is no gain support, only attenuation. */
2166 uCtlAttLeft = uCtlAttLeft < 8 ? 0 : uCtlAttLeft - 8;
2167 uCtlAttRight = uCtlAttRight < 8 ? 0 : uCtlAttRight - 8;
2168# endif
2169 }
2170 Assert(uCtlAttLeft <= 255 / AC97_DB_FACTOR);
2171 Assert(uCtlAttRight <= 255 / AC97_DB_FACTOR);
2172
2173 LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2174 LogFunc(("uCtlAttLeft=%RU8, uCtlAttRight=%RU8 ", uCtlAttLeft, uCtlAttRight));
2175
2176 /*
2177 * For AC'97 volume controls, each additional step means -1.5dB attenuation with
2178 * zero being maximum. In contrast, we're internally using 255 (PDMAUDIO_VOLUME_MAX)
2179 * steps, each -0.375dB, where 0 corresponds to -96dB and 255 corresponds to 0dB.
2180 */
2181 uint8_t lVol = PDMAUDIO_VOLUME_MAX - uCtlAttLeft * AC97_DB_FACTOR;
2182 uint8_t rVol = PDMAUDIO_VOLUME_MAX - uCtlAttRight * AC97_DB_FACTOR;
2183
2184 Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2185
2186 int rc = VINF_SUCCESS;
2187
2188 if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2189 {
2190 PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2191 PAUDMIXSINK pSink = NULL;
2192
2193 switch (enmMixerCtl)
2194 {
2195 case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2196 rc = AudioMixerSetMasterVolume(pThisCC->pMixer, &Vol);
2197 break;
2198
2199 case PDMAUDIOMIXERCTL_FRONT:
2200 pSink = pThisCC->pSinkOut;
2201 break;
2202
2203 case PDMAUDIOMIXERCTL_MIC_IN:
2204 case PDMAUDIOMIXERCTL_LINE_IN:
2205 /* These are recognized but do nothing. */
2206 break;
2207
2208 default:
2209 AssertFailed();
2210 rc = VERR_NOT_SUPPORTED;
2211 break;
2212 }
2213
2214 if (pSink)
2215 rc = AudioMixerSinkSetVolume(pSink, &Vol);
2216 }
2217
2218 ichac97MixerSet(pThis, index, uVal);
2219
2220 if (RT_FAILURE(rc))
2221 LogFlowFunc(("Failed with %Rrc\n", rc));
2222
2223 return rc;
2224}
2225
2226/**
2227 * Sets the gain of a specific AC'97 recording control.
2228 *
2229 * NB: gain support is currently not implemented in PDM audio.
2230 *
2231 * @returns VBox status code.
2232 * @param pThis The shared AC'97 state.
2233 * @param pThisCC The ring-3 AC'97 state.
2234 * @param index AC'97 mixer index to set volume for.
2235 * @param enmMixerCtl Corresponding audio mixer sink.
2236 * @param uVal Volume value to set.
2237 */
2238static int ichac97R3MixerSetGain(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2239{
2240 /*
2241 * For AC'97 recording controls, each additional step means +1.5dB gain with
2242 * zero being 0dB gain and 15 being +22.5dB gain.
2243 */
2244 const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2245 uint8_t uCtlGainLeft = (uVal >> 8) & AC97_BARS_GAIN_MASK;
2246 uint8_t uCtlGainRight = uVal & AC97_BARS_GAIN_MASK;
2247
2248 Assert(uCtlGainLeft <= 255 / AC97_DB_FACTOR);
2249 Assert(uCtlGainRight <= 255 / AC97_DB_FACTOR);
2250
2251 LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2252 LogFunc(("uCtlGainLeft=%RU8, uCtlGainRight=%RU8 ", uCtlGainLeft, uCtlGainRight));
2253
2254 uint8_t lVol = PDMAUDIO_VOLUME_MAX + uCtlGainLeft * AC97_DB_FACTOR;
2255 uint8_t rVol = PDMAUDIO_VOLUME_MAX + uCtlGainRight * AC97_DB_FACTOR;
2256
2257 /* We do not currently support gain. Since AC'97 does not support attenuation
2258 * for the recording input, the best we can do is set the maximum volume.
2259 */
2260# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2261 /* NB: Currently there is no gain support, only attenuation. Since AC'97 does not
2262 * support attenuation for the recording inputs, the best we can do is set the
2263 * maximum volume.
2264 */
2265 lVol = rVol = PDMAUDIO_VOLUME_MAX;
2266# endif
2267
2268 Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2269
2270 int rc = VINF_SUCCESS;
2271
2272 if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2273 {
2274 PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2275 PAUDMIXSINK pSink = NULL;
2276
2277 switch (enmMixerCtl)
2278 {
2279 case PDMAUDIOMIXERCTL_MIC_IN:
2280 pSink = pThisCC->pSinkMicIn;
2281 break;
2282
2283 case PDMAUDIOMIXERCTL_LINE_IN:
2284 pSink = pThisCC->pSinkLineIn;
2285 break;
2286
2287 default:
2288 AssertFailed();
2289 rc = VERR_NOT_SUPPORTED;
2290 break;
2291 }
2292
2293 if (pSink) {
2294 rc = AudioMixerSinkSetVolume(pSink, &Vol);
2295 /* There is only one AC'97 recording gain control. If line in
2296 * is changed, also update the microphone. If the optional dedicated
2297 * microphone is changed, only change that.
2298 * NB: The codecs we support do not have the dedicated microphone control.
2299 */
2300 if ((pSink == pThisCC->pSinkLineIn) && pThisCC->pSinkMicIn)
2301 rc = AudioMixerSinkSetVolume(pSink, &Vol);
2302 }
2303 }
2304
2305 ichac97MixerSet(pThis, index, uVal);
2306
2307 if (RT_FAILURE(rc))
2308 LogFlowFunc(("Failed with %Rrc\n", rc));
2309
2310 return rc;
2311}
2312
2313/**
2314 * Converts an AC'97 recording source index to a PDM audio recording source.
2315 *
2316 * @returns PDM audio recording source.
2317 * @param uIdx AC'97 index to convert.
2318 */
2319static PDMAUDIOPATH ichac97R3IdxToRecSource(uint8_t uIdx)
2320{
2321 switch (uIdx)
2322 {
2323 case AC97_REC_MIC: return PDMAUDIOPATH_IN_MIC;
2324 case AC97_REC_CD: return PDMAUDIOPATH_IN_CD;
2325 case AC97_REC_VIDEO: return PDMAUDIOPATH_IN_VIDEO;
2326 case AC97_REC_AUX: return PDMAUDIOPATH_IN_AUX;
2327 case AC97_REC_LINE_IN: return PDMAUDIOPATH_IN_LINE;
2328 case AC97_REC_PHONE: return PDMAUDIOPATH_IN_PHONE;
2329 default:
2330 break;
2331 }
2332
2333 LogFlowFunc(("Unknown record source %d, using MIC\n", uIdx));
2334 return PDMAUDIOPATH_IN_MIC;
2335}
2336
2337/**
2338 * Converts a PDM audio recording source to an AC'97 recording source index.
2339 *
2340 * @returns AC'97 recording source index.
2341 * @param enmRecSrc PDM audio recording source to convert.
2342 */
2343static uint8_t ichac97R3RecSourceToIdx(PDMAUDIOPATH enmRecSrc)
2344{
2345 switch (enmRecSrc)
2346 {
2347 case PDMAUDIOPATH_IN_MIC: return AC97_REC_MIC;
2348 case PDMAUDIOPATH_IN_CD: return AC97_REC_CD;
2349 case PDMAUDIOPATH_IN_VIDEO: return AC97_REC_VIDEO;
2350 case PDMAUDIOPATH_IN_AUX: return AC97_REC_AUX;
2351 case PDMAUDIOPATH_IN_LINE: return AC97_REC_LINE_IN;
2352 case PDMAUDIOPATH_IN_PHONE: return AC97_REC_PHONE;
2353 default:
2354 AssertMsgFailedBreak(("%d\n", enmRecSrc));
2355 }
2356
2357 LogFlowFunc(("Unknown audio recording source %d using MIC\n", enmRecSrc));
2358 return AC97_REC_MIC;
2359}
2360
2361/**
2362 * Returns the audio direction of a specified stream descriptor.
2363 *
2364 * @return Audio direction.
2365 */
2366DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD)
2367{
2368 switch (uSD)
2369 {
2370 case AC97SOUNDSOURCE_PI_INDEX: return PDMAUDIODIR_IN;
2371 case AC97SOUNDSOURCE_PO_INDEX: return PDMAUDIODIR_OUT;
2372 case AC97SOUNDSOURCE_MC_INDEX: return PDMAUDIODIR_IN;
2373 }
2374
2375 AssertFailed();
2376 return PDMAUDIODIR_UNKNOWN;
2377}
2378
2379#endif /* IN_RING3 */
2380
2381#ifdef IN_RING3
2382
2383/**
2384 * Performs an AC'97 mixer record select to switch to a different recording
2385 * source.
2386 *
2387 * @param pThis The shared AC'97 state.
2388 * @param val AC'97 recording source index to set.
2389 */
2390static void ichac97R3MixerRecordSelect(PAC97STATE pThis, uint32_t val)
2391{
2392 uint8_t rs = val & AC97_REC_MASK;
2393 uint8_t ls = (val >> 8) & AC97_REC_MASK;
2394
2395 PDMAUDIOPATH const ars = ichac97R3IdxToRecSource(rs);
2396 PDMAUDIOPATH const als = ichac97R3IdxToRecSource(ls);
2397
2398 rs = ichac97R3RecSourceToIdx(ars);
2399 ls = ichac97R3RecSourceToIdx(als);
2400
2401 LogRel(("AC97: Record select to left=%s, right=%s\n", PDMAudioPathGetName(ars), PDMAudioPathGetName(als)));
2402
2403 ichac97MixerSet(pThis, AC97_Record_Select, rs | (ls << 8));
2404}
2405
2406/**
2407 * Resets the AC'97 mixer.
2408 *
2409 * @returns VBox status code.
2410 * @param pThis The shared AC'97 state.
2411 * @param pThisCC The ring-3 AC'97 state.
2412 */
2413static int ichac97R3MixerReset(PAC97STATE pThis, PAC97STATER3 pThisCC)
2414{
2415 LogFlowFuncEnter();
2416
2417 RT_ZERO(pThis->mixer_data);
2418
2419 /* Note: Make sure to reset all registers first before bailing out on error. */
2420
2421 ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
2422 ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
2423 ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
2424
2425 ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
2426 ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
2427 ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
2428 ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
2429 ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
2430 ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
2431 ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
2432 ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
2433
2434 /* Configure Extended Audio ID (EAID) + Control & Status (EACS) registers. */
2435 const uint16_t fEAID = AC97_EAID_REV1 | AC97_EACS_VRA | AC97_EACS_VRM; /* Our hardware is AC'97 rev2.3 compliant. */
2436 const uint16_t fEACS = AC97_EACS_VRA | AC97_EACS_VRM; /* Variable Rate PCM Audio (VRA) + Mic-In (VRM) capable. */
2437
2438 LogRel(("AC97: Mixer reset (EAID=0x%x, EACS=0x%x)\n", fEAID, fEACS));
2439
2440 ichac97MixerSet(pThis, AC97_Extended_Audio_ID, fEAID);
2441 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, fEACS);
2442 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2443 ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2444 ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2445 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2446 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2447
2448 if (pThis->enmCodecModel == AC97CODEC_AD1980)
2449 {
2450 /* Analog Devices 1980 (AD1980) */
2451 ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
2452 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2453 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
2454 ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
2455 }
2456 else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
2457 {
2458 /* Analog Devices 1981B (AD1981B) */
2459 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2460 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
2461 }
2462 else
2463 {
2464 /* Sigmatel 9700 (STAC9700) */
2465 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
2466 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
2467 }
2468 ichac97R3MixerRecordSelect(pThis, 0);
2469
2470 /* The default value is 8000h, which corresponds to 0 dB attenuation with mute on. */
2471 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER, 0x8000);
2472
2473 /* The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on.*/
2474 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT, 0x8808);
2475 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
2476 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8008);
2477
2478 /* The default for record controls is 0 dB gain with mute on. */
2479 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8000);
2480 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8000);
2481
2482 return VINF_SUCCESS;
2483}
2484
2485# if 0 /* Unused */
2486static void ichac97R3WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
2487{
2488 LogFlowFunc(("cbElapsed=%RU32\n", cbElapsed));
2489
2490 if (!(pThis->bup_flag & BUP_SET))
2491 {
2492 if (pThis->bup_flag & BUP_LAST)
2493 {
2494 unsigned int i;
2495 uint32_t *p = (uint32_t*)pThis->silence;
2496 for (i = 0; i < sizeof(pThis->silence) / 4; i++) /** @todo r=andy Assumes 16-bit samples, stereo. */
2497 *p++ = pThis->last_samp;
2498 }
2499 else
2500 RT_ZERO(pThis->silence);
2501
2502 pThis->bup_flag |= BUP_SET;
2503 }
2504
2505 while (cbElapsed)
2506 {
2507 uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
2508 uint32_t cbWrittenToStream;
2509
2510 int rc2 = AudioMixerSinkWrite(pThisCC->pSinkOut, AUDMIXOP_COPY,
2511 pThis->silence, cbToWrite, &cbWrittenToStream);
2512 if (RT_SUCCESS(rc2))
2513 {
2514 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2515 LogFlowFunc(("Warning: Only written %RU32 / %RU32 bytes, expect lags\n", cbWrittenToStream, cbToWrite));
2516 }
2517
2518 /* Always report all data as being written;
2519 * backends who were not able to catch up have to deal with it themselves. */
2520 Assert(cbElapsed >= cbToWrite);
2521 cbElapsed -= cbToWrite;
2522 }
2523}
2524# endif /* Unused */
2525
2526/**
2527 * @callback_method_impl{FNTMTIMERDEV,
2528 * Timer callback which handles the audio data transfers on a periodic basis.}
2529 */
2530static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
2531{
2532 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2533 STAM_PROFILE_START(&pThis->StatTimer, a);
2534 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
2535 PAC97STREAM pStream = (PAC97STREAM)pvUser;
2536 PAC97STREAMR3 pStreamCC = &RT_SAFE_SUBSCRIPT8(pThisCC->aStreams, pStream->u8SD);
2537 Assert(hTimer == pStream->hTimer); RT_NOREF(hTimer);
2538
2539 Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2540 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2541 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStream->hTimer));
2542
2543 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
2544 if (pSink && AudioMixerSinkIsActive(pSink))
2545 {
2546 ichac97R3StreamUpdateDma(pDevIns, pThis, pThisCC, pStream, pStreamCC);
2547
2548 ichac97R3StreamTransferUpdate(pDevIns, pStream, pStreamCC);
2549 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
2550 }
2551
2552 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2553}
2554
2555
2556/**
2557 * Sets the virtual device timer to a new expiration time.
2558 *
2559 * @param pDevIns The device instance.
2560 * @param pStream AC'97 stream to set timer for.
2561 * @param cTicksToDeadline The number of ticks to the new deadline.
2562 *
2563 * @remarks This used to be more complicated a long time ago...
2564 */
2565DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline)
2566{
2567 int rc = PDMDevHlpTimerSetRelative(pDevIns, pStream->hTimer, cTicksToDeadline, NULL /*pu64Now*/);
2568 AssertRC(rc);
2569}
2570
2571
2572/**
2573 * Transfers data of an AC'97 stream according to its usage (input / output).
2574 *
2575 * For an SDO (output) stream this means reading DMA data from the device to
2576 * the AC'97 stream's internal FIFO buffer.
2577 *
2578 * For an SDI (input) stream this is reading audio data from the AC'97 stream's
2579 * internal FIFO buffer and writing it as DMA data to the device.
2580 *
2581 * @returns VBox status code.
2582 * @param pDevIns The device instance.
2583 * @param pThis The shared AC'97 state.
2584 * @param pStream The AC'97 stream to update (shared).
2585 * @param pStreamCC The AC'97 stream to update (ring-3).
2586 * @param cbToProcessMax Maximum of data (in bytes) to process.
2587 */
2588static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
2589 PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax)
2590{
2591 if (!cbToProcessMax)
2592 return VINF_SUCCESS;
2593
2594#ifdef VBOX_STRICT
2595 const unsigned cbFrame = PDMAudioPropsBytesPerFrame(&pStreamCC->State.Cfg.Props);
2596#endif
2597
2598 /* Make sure to only process an integer number of audio frames. */
2599 Assert(cbToProcessMax % cbFrame == 0);
2600
2601 ichac97R3StreamLock(pStreamCC);
2602
2603 PAC97BMREGS pRegs = &pStream->Regs;
2604
2605 if (pRegs->sr & AC97_SR_DCH) /* Controller halted? */
2606 {
2607 if (pRegs->cr & AC97_CR_RPBM) /* Bus master operation starts. */
2608 {
2609 switch (pStream->u8SD)
2610 {
2611 case AC97SOUNDSOURCE_PO_INDEX:
2612 /*ichac97R3WriteBUP(pThis, cbToProcess);*/
2613 break;
2614
2615 default:
2616 break;
2617 }
2618 }
2619
2620 ichac97R3StreamUnlock(pStreamCC);
2621 return VINF_SUCCESS;
2622 }
2623
2624 /* BCIS flag still set? Skip iteration. */
2625 if (pRegs->sr & AC97_SR_BCIS)
2626 {
2627 Log3Func(("[SD%RU8] BCIS set\n", pStream->u8SD));
2628
2629 ichac97R3StreamUnlock(pStreamCC);
2630 return VINF_SUCCESS;
2631 }
2632
2633 uint32_t cbLeft = RT_MIN((uint32_t)(pRegs->picb << 1), cbToProcessMax); /** @todo r=andy Assumes 16bit samples. */
2634 uint32_t cbProcessedTotal = 0;
2635
2636 PRTCIRCBUF pCircBuf = pStreamCC->State.pCircBuf;
2637 AssertPtr(pCircBuf);
2638
2639 int rc = VINF_SUCCESS;
2640
2641 Log3Func(("[SD%RU8] cbToProcessMax=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcessMax, cbLeft));
2642
2643 while (cbLeft)
2644 {
2645 if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
2646 {
2647 Log3Func(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
2648 pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
2649 if (pRegs->civ == pRegs->lvi)
2650 {
2651 pRegs->sr |= AC97_SR_DCH; /** @todo r=andy Also set CELV? */
2652 pThis->bup_flag = 0;
2653
2654 rc = VINF_EOF;
2655 break;
2656 }
2657
2658 pRegs->sr &= ~AC97_SR_CELV;
2659 if (ichac97R3StreamFetchNextBdle(pDevIns, pStream, pStreamCC))
2660 ichac97StreamUpdateSR(pDevIns, pThis, pStream, pRegs->sr | AC97_SR_BCIS);
2661 continue;
2662 }
2663
2664 uint32_t cbChunk = cbLeft;
2665
2666 switch (pStream->u8SD)
2667 {
2668 case AC97SOUNDSOURCE_PO_INDEX: /* Output */
2669 {
2670 void *pvDst;
2671 size_t cbDst;
2672
2673 RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvDst, &cbDst);
2674
2675 if (cbDst)
2676 {
2677 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, pRegs->bd.addr, (uint8_t *)pvDst, cbDst);
2678 AssertRC(rc2);
2679
2680 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2681 { /* likely */ }
2682 else
2683 AudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvDst, cbDst, 0 /* fFlags */);
2684 }
2685
2686 RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
2687
2688 cbChunk = (uint32_t)cbDst; /* Update the current chunk size to what really has been written. */
2689 break;
2690 }
2691
2692 case AC97SOUNDSOURCE_PI_INDEX: /* Input */
2693 case AC97SOUNDSOURCE_MC_INDEX: /* Input */
2694 {
2695 void *pvSrc;
2696 size_t cbSrc;
2697
2698 RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvSrc, &cbSrc);
2699
2700 if (cbSrc)
2701 {
2702 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, pRegs->bd.addr, (uint8_t *)pvSrc, cbSrc);
2703 AssertRC(rc2);
2704
2705 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2706 { /* likely */ }
2707 else
2708 AudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvSrc, cbSrc, 0 /* fFlags */);
2709 }
2710
2711 RTCircBufReleaseReadBlock(pCircBuf, cbSrc);
2712
2713 cbChunk = (uint32_t)cbSrc; /* Update the current chunk size to what really has been read. */
2714 break;
2715 }
2716
2717 default:
2718 AssertMsgFailed(("Stream #%RU8 not supported\n", pStream->u8SD));
2719 rc = VERR_NOT_SUPPORTED;
2720 break;
2721 }
2722
2723 if (RT_FAILURE(rc))
2724 break;
2725
2726 if (cbChunk)
2727 {
2728 cbProcessedTotal += cbChunk;
2729 Assert(cbProcessedTotal <= cbToProcessMax);
2730 Assert(cbLeft >= cbChunk);
2731 cbLeft -= cbChunk;
2732 Assert((cbChunk & 1) == 0); /* Else the following shift won't work */
2733
2734 pRegs->picb -= (cbChunk >> 1); /** @todo r=andy Assumes 16bit samples. */
2735 pRegs->bd.addr += cbChunk;
2736 }
2737
2738 LogFlowFunc(("[SD%RU8] cbChunk=%RU32, cbLeft=%RU32, cbTotal=%RU32, rc=%Rrc\n",
2739 pStream->u8SD, cbChunk, cbLeft, cbProcessedTotal, rc));
2740
2741 if (!pRegs->picb)
2742 {
2743 uint32_t new_sr = pRegs->sr & ~AC97_SR_CELV;
2744
2745 if (pRegs->bd.ctl_len & AC97_BD_IOC)
2746 {
2747 new_sr |= AC97_SR_BCIS;
2748 }
2749
2750 if (pRegs->civ == pRegs->lvi)
2751 {
2752 /* Did we run out of data? */
2753 LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pRegs->civ, pRegs->lvi));
2754
2755 new_sr |= AC97_SR_LVBCI | AC97_SR_DCH | AC97_SR_CELV;
2756 pThis->bup_flag = (pRegs->bd.ctl_len & AC97_BD_BUP) ? BUP_LAST : 0;
2757
2758 rc = VINF_EOF;
2759 }
2760 else
2761 new_sr |= ichac97R3StreamFetchNextBdle(pDevIns, pStream, pStreamCC);
2762
2763 ichac97StreamUpdateSR(pDevIns, pThis, pStream, new_sr);
2764 }
2765
2766 if (/* All data processed? */
2767 rc == VINF_EOF
2768 /* ... or an error occurred? */
2769 || RT_FAILURE(rc))
2770 {
2771 break;
2772 }
2773 }
2774
2775 ichac97R3StreamUnlock(pStreamCC);
2776
2777 LogFlowFuncLeaveRC(rc);
2778 return rc;
2779}
2780
2781#endif /* IN_RING3 */
2782
2783
2784/**
2785 * @callback_method_impl{FNIOMIOPORTNEWIN}
2786 */
2787static DECLCALLBACK(VBOXSTRICTRC)
2788ichac97IoPortNabmRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2789{
2790 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2791 RT_NOREF(pvUser);
2792
2793 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
2794
2795 /* Get the index of the NABMBAR port. */
2796 if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
2797 && offPort != AC97_GLOB_CNT)
2798 {
2799 PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
2800 PAC97BMREGS pRegs = &pStream->Regs;
2801
2802 switch (cb)
2803 {
2804 case 1:
2805 switch (offPort & AC97_NABM_OFF_MASK)
2806 {
2807 case AC97_NABM_OFF_CIV:
2808 /* Current Index Value Register */
2809 *pu32 = pRegs->civ;
2810 Log3Func(("CIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2811 break;
2812 case AC97_NABM_OFF_LVI:
2813 /* Last Valid Index Register */
2814 *pu32 = pRegs->lvi;
2815 Log3Func(("LVI[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2816 break;
2817 case AC97_NABM_OFF_PIV:
2818 /* Prefetched Index Value Register */
2819 *pu32 = pRegs->piv;
2820 Log3Func(("PIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2821 break;
2822 case AC97_NABM_OFF_CR:
2823 /* Control Register */
2824 *pu32 = pRegs->cr;
2825 Log3Func(("CR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2826 break;
2827 case AC97_NABM_OFF_SR:
2828 /* Status Register (lower part) */
2829 *pu32 = RT_LO_U8(pRegs->sr);
2830 Log3Func(("SRb[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2831 break;
2832 default:
2833 *pu32 = UINT32_MAX;
2834 LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
2835 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2836 break;
2837 }
2838 break;
2839
2840 case 2:
2841 switch (offPort & AC97_NABM_OFF_MASK)
2842 {
2843 case AC97_NABM_OFF_SR:
2844 /* Status Register */
2845 *pu32 = pRegs->sr;
2846 Log3Func(("SR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2847 break;
2848 case AC97_NABM_OFF_PICB:
2849 /* Position in Current Buffer */
2850 *pu32 = pRegs->picb;
2851 Log3Func(("PICB[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2852 break;
2853 default:
2854 *pu32 = UINT32_MAX;
2855 LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
2856 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2857 break;
2858 }
2859 break;
2860
2861 case 4:
2862 switch (offPort & AC97_NABM_OFF_MASK)
2863 {
2864 case AC97_NABM_OFF_BDBAR:
2865 /* Buffer Descriptor Base Address Register */
2866 *pu32 = pRegs->bdbar;
2867 Log3Func(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2868 break;
2869 case AC97_NABM_OFF_CIV:
2870 /* 32-bit access: Current Index Value Register +
2871 * Last Valid Index Register +
2872 * Status Register */
2873 *pu32 = pRegs->civ | ((uint32_t)pRegs->lvi << 8) | ((uint32_t)pRegs->sr << 16);
2874 Log3Func(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
2875 AC97_PORT2IDX(offPort), pRegs->civ, pRegs->lvi, pRegs->sr));
2876 break;
2877 case AC97_NABM_OFF_PICB:
2878 /* 32-bit access: Position in Current Buffer Register +
2879 * Prefetched Index Value Register +
2880 * Control Register */
2881 *pu32 = pRegs->picb | ((uint32_t)pRegs->piv << 16) | ((uint32_t)pRegs->cr << 24);
2882 Log3Func(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
2883 AC97_PORT2IDX(offPort), *pu32, pRegs->picb, pRegs->piv, pRegs->cr));
2884 break;
2885
2886 default:
2887 *pu32 = UINT32_MAX;
2888 LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
2889 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2890 break;
2891 }
2892 break;
2893
2894 default:
2895 DEVAC97_UNLOCK(pDevIns, pThis);
2896 AssertFailed();
2897 return VERR_IOM_IOPORT_UNUSED;
2898 }
2899 }
2900 else
2901 {
2902 switch (cb)
2903 {
2904 case 1:
2905 switch (offPort)
2906 {
2907 case AC97_CAS:
2908 /* Codec Access Semaphore Register */
2909 Log3Func(("CAS %d\n", pThis->cas));
2910 *pu32 = pThis->cas;
2911 pThis->cas = 1;
2912 break;
2913 default:
2914 *pu32 = UINT32_MAX;
2915 LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
2916 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2917 break;
2918 }
2919 break;
2920
2921 case 2:
2922 *pu32 = UINT32_MAX;
2923 LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
2924 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2925 break;
2926
2927 case 4:
2928 switch (offPort)
2929 {
2930 case AC97_GLOB_CNT:
2931 /* Global Control */
2932 *pu32 = pThis->glob_cnt;
2933 Log3Func(("glob_cnt -> %#x\n", *pu32));
2934 break;
2935 case AC97_GLOB_STA:
2936 /* Global Status */
2937 *pu32 = pThis->glob_sta | AC97_GS_S0CR;
2938 Log3Func(("glob_sta -> %#x\n", *pu32));
2939 break;
2940 default:
2941 *pu32 = UINT32_MAX;
2942 LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
2943 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2944 break;
2945 }
2946 break;
2947
2948 default:
2949 DEVAC97_UNLOCK(pDevIns, pThis);
2950 AssertFailed();
2951 return VERR_IOM_IOPORT_UNUSED;
2952 }
2953 }
2954
2955 DEVAC97_UNLOCK(pDevIns, pThis);
2956 return VINF_SUCCESS;
2957}
2958
2959/**
2960 * @callback_method_impl{FNIOMIOPORTNEWOUT}
2961 */
2962static DECLCALLBACK(VBOXSTRICTRC)
2963ichac97IoPortNabmWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2964{
2965 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2966#ifdef IN_RING3
2967 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
2968#endif
2969 RT_NOREF(pvUser);
2970
2971 VBOXSTRICTRC rc = VINF_SUCCESS;
2972 if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
2973 && offPort != AC97_GLOB_CNT)
2974 {
2975#ifdef IN_RING3
2976 PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[AC97_PORT2IDX(offPort)];
2977#endif
2978 PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
2979 PAC97BMREGS pRegs = &pStream->Regs;
2980
2981 DEVAC97_LOCK_BOTH_RETURN(pDevIns, pThis, pStream, VINF_IOM_R3_IOPORT_WRITE);
2982 switch (cb)
2983 {
2984 case 1:
2985 switch (offPort & AC97_NABM_OFF_MASK)
2986 {
2987 /*
2988 * Last Valid Index.
2989 */
2990 case AC97_NABM_OFF_LVI:
2991 if ( (pRegs->cr & AC97_CR_RPBM)
2992 && (pRegs->sr & AC97_SR_DCH))
2993 {
2994#ifdef IN_RING3 /** @todo r=bird: What kind of unexplained non-sense is this ifdef?!? */
2995 pRegs->sr &= ~(AC97_SR_DCH | AC97_SR_CELV);
2996 pRegs->civ = pRegs->piv;
2997 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2998#else
2999 rc = VINF_IOM_R3_IOPORT_WRITE;
3000#endif
3001 }
3002 pRegs->lvi = u32 % AC97_MAX_BDLE;
3003 Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32));
3004 break;
3005
3006 /*
3007 * Control Registers.
3008 */
3009 case AC97_NABM_OFF_CR:
3010#ifdef IN_RING3
3011 Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32, pRegs->cr));
3012 if (u32 & AC97_CR_RR) /* Busmaster reset. */
3013 {
3014 Log3Func(("[SD%RU8] Reset\n", pStream->u8SD));
3015
3016 /* Make sure that Run/Pause Bus Master bit (RPBM) is cleared (0). */
3017 Assert((pRegs->cr & AC97_CR_RPBM) == 0);
3018 if (pRegs->cr & AC97_CR_RPBM)
3019 ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3020
3021 ichac97R3StreamReset(pThis, pStream, pStreamCC);
3022
3023 ichac97StreamUpdateSR(pDevIns, pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */
3024 }
3025 else
3026 {
3027 pRegs->cr = u32 & AC97_CR_VALID_MASK;
3028
3029 if (!(pRegs->cr & AC97_CR_RPBM))
3030 {
3031 Log3Func(("[SD%RU8] Disable\n", pStream->u8SD));
3032
3033 ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3034
3035 pRegs->sr |= AC97_SR_DCH;
3036 }
3037 else
3038 {
3039 Log3Func(("[SD%RU8] Enable\n", pStream->u8SD));
3040
3041 pRegs->sr &= ~AC97_SR_DCH;
3042
3043 if (ichac97R3StreamFetchNextBdle(pDevIns, pStream, pStreamCC))
3044 ichac97StreamUpdateSR(pDevIns, pThis, pStream, pRegs->sr | AC97_SR_BCIS);
3045# ifdef LOG_ENABLED
3046 if (LogIsFlowEnabled())
3047 ichac97R3DbgPrintBdl(pDevIns, pThis, pStream, DBGFR3InfoLogHlp(), "ichac97IoPortNabmWrite: ");
3048# endif
3049 ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, true /* fEnable */);
3050
3051 /* Arm the timer for this stream. */
3052 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3053 }
3054 }
3055#else /* !IN_RING3 */
3056 rc = VINF_IOM_R3_IOPORT_WRITE;
3057#endif
3058 break;
3059
3060 /*
3061 * Status Registers.
3062 */
3063 case AC97_NABM_OFF_SR:
3064 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3065 break;
3066
3067 default:
3068 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3069 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3070 break;
3071 }
3072 break;
3073
3074 case 2:
3075 switch (offPort & AC97_NABM_OFF_MASK)
3076 {
3077 case AC97_NABM_OFF_SR:
3078 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3079 break;
3080 default:
3081 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3082 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3083 break;
3084 }
3085 break;
3086
3087 case 4:
3088 switch (offPort & AC97_NABM_OFF_MASK)
3089 {
3090 case AC97_NABM_OFF_BDBAR:
3091 /* Buffer Descriptor list Base Address Register */
3092 pRegs->bdbar = u32 & ~(uint32_t)3;
3093 Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(offPort), u32, pRegs->bdbar));
3094 break;
3095 default:
3096 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3097 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3098 break;
3099 }
3100 break;
3101
3102 default:
3103 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3104 break;
3105 }
3106 DEVAC97_UNLOCK_BOTH(pDevIns, pThis, pStream);
3107 }
3108 else
3109 {
3110 switch (cb)
3111 {
3112 case 1:
3113 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3114 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3115 break;
3116
3117 case 2:
3118 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3119 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3120 break;
3121
3122 case 4:
3123 switch (offPort)
3124 {
3125 case AC97_GLOB_CNT:
3126 /* Global Control */
3127 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3128 if (u32 & AC97_GC_WR)
3129 ichac97WarmReset(pThis);
3130 if (u32 & AC97_GC_CR)
3131 ichac97ColdReset(pThis);
3132 if (!(u32 & (AC97_GC_WR | AC97_GC_CR)))
3133 pThis->glob_cnt = u32 & AC97_GC_VALID_MASK;
3134 Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt));
3135 DEVAC97_UNLOCK(pDevIns, pThis);
3136 break;
3137 case AC97_GLOB_STA:
3138 /* Global Status */
3139 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3140 pThis->glob_sta &= ~(u32 & AC97_GS_WCLEAR_MASK);
3141 pThis->glob_sta |= (u32 & ~(AC97_GS_WCLEAR_MASK | AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK;
3142 Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta));
3143 DEVAC97_UNLOCK(pDevIns, pThis);
3144 break;
3145 default:
3146 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3147 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3148 break;
3149 }
3150 break;
3151
3152 default:
3153 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3154 break;
3155 }
3156 }
3157
3158 return rc;
3159}
3160
3161/**
3162 * @callback_method_impl{FNIOMIOPORTNEWIN}
3163 */
3164static DECLCALLBACK(VBOXSTRICTRC)
3165ichac97IoPortNamRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
3166{
3167 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3168 RT_NOREF(pvUser);
3169 Assert(offPort < 256);
3170
3171 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3172
3173 VBOXSTRICTRC rc = VINF_SUCCESS;
3174 switch (cb)
3175 {
3176 case 1:
3177 {
3178 LogRel2(("AC97: Warning: Unimplemented read (1 byte) offPort=%#x\n", offPort));
3179 pThis->cas = 0;
3180 *pu32 = UINT32_MAX;
3181 break;
3182 }
3183
3184 case 2:
3185 {
3186 pThis->cas = 0;
3187 *pu32 = ichac97MixerGet(pThis, offPort);
3188 break;
3189 }
3190
3191 case 4:
3192 {
3193 LogRel2(("AC97: Warning: Unimplemented read (4 bytes) offPort=%#x\n", offPort));
3194 pThis->cas = 0;
3195 *pu32 = UINT32_MAX;
3196 break;
3197 }
3198
3199 default:
3200 {
3201 AssertFailed();
3202 rc = VERR_IOM_IOPORT_UNUSED;
3203 }
3204 }
3205
3206 DEVAC97_UNLOCK(pDevIns, pThis);
3207 return rc;
3208}
3209
3210/**
3211 * @callback_method_impl{FNIOMIOPORTNEWOUT}
3212 */
3213static DECLCALLBACK(VBOXSTRICTRC)
3214ichac97IoPortNamWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3215{
3216 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3217#ifdef IN_RING3
3218 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3219#endif
3220 RT_NOREF(pvUser);
3221
3222 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3223
3224 VBOXSTRICTRC rc = VINF_SUCCESS;
3225 switch (cb)
3226 {
3227 case 1:
3228 {
3229 LogRel2(("AC97: Warning: Unimplemented NAMWrite (1 byte) offPort=%#x <- %#x\n", offPort, u32));
3230 pThis->cas = 0;
3231 break;
3232 }
3233
3234 case 2:
3235 {
3236 pThis->cas = 0;
3237 switch (offPort)
3238 {
3239 case AC97_Reset:
3240#ifdef IN_RING3
3241 ichac97R3Reset(pDevIns);
3242#else
3243 rc = VINF_IOM_R3_IOPORT_WRITE;
3244#endif
3245 break;
3246 case AC97_Powerdown_Ctrl_Stat:
3247 u32 &= ~0xf;
3248 u32 |= ichac97MixerGet(pThis, offPort) & 0xf;
3249 ichac97MixerSet(pThis, offPort, u32);
3250 break;
3251 case AC97_Master_Volume_Mute:
3252 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3253 {
3254 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_LOSEL)
3255 break; /* Register controls surround (rear), do nothing. */
3256 }
3257#ifdef IN_RING3
3258 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3259#else
3260 rc = VINF_IOM_R3_IOPORT_WRITE;
3261#endif
3262 break;
3263 case AC97_Headphone_Volume_Mute:
3264 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3265 {
3266 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3267 {
3268 /* Register controls PCM (front) outputs. */
3269#ifdef IN_RING3
3270 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3271#else
3272 rc = VINF_IOM_R3_IOPORT_WRITE;
3273#endif
3274 }
3275 }
3276 break;
3277 case AC97_PCM_Out_Volume_Mute:
3278#ifdef IN_RING3
3279 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_FRONT, u32);
3280#else
3281 rc = VINF_IOM_R3_IOPORT_WRITE;
3282#endif
3283 break;
3284 case AC97_Line_In_Volume_Mute:
3285#ifdef IN_RING3
3286 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3287#else
3288 rc = VINF_IOM_R3_IOPORT_WRITE;
3289#endif
3290 break;
3291 case AC97_Record_Select:
3292#ifdef IN_RING3
3293 ichac97R3MixerRecordSelect(pThis, u32);
3294#else
3295 rc = VINF_IOM_R3_IOPORT_WRITE;
3296#endif
3297 break;
3298 case AC97_Record_Gain_Mute:
3299#ifdef IN_RING3
3300 /* Newer Ubuntu guests rely on that when controlling gain and muting
3301 * the recording (capturing) levels. */
3302 ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3303#else
3304 rc = VINF_IOM_R3_IOPORT_WRITE;
3305#endif
3306 break;
3307 case AC97_Record_Gain_Mic_Mute:
3308#ifdef IN_RING3
3309 /* Ditto; see note above. */
3310 ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_MIC_IN, u32);
3311#else
3312 rc = VINF_IOM_R3_IOPORT_WRITE;
3313#endif
3314 break;
3315 case AC97_Vendor_ID1:
3316 case AC97_Vendor_ID2:
3317 LogFunc(("Attempt to write vendor ID to %#x\n", u32));
3318 break;
3319 case AC97_Extended_Audio_ID:
3320 LogFunc(("Attempt to write extended audio ID to %#x\n", u32));
3321 break;
3322 case AC97_Extended_Audio_Ctrl_Stat:
3323#ifdef IN_RING3
3324 /*
3325 * Handle VRA bits.
3326 */
3327 if (!(u32 & AC97_EACS_VRA)) /* Check if VRA bit is not set. */
3328 {
3329 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 0xbb80); /* Set default (48000 Hz). */
3330 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3331 * actually used? */
3332 ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3333 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3334
3335 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3336 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3337 * actually used? */
3338 ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3339 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3340 }
3341 else
3342 LogRel2(("AC97: Variable rate audio (VRA) is not supported\n"));
3343
3344 /*
3345 * Handle VRM bits.
3346 */
3347 if (!(u32 & AC97_EACS_VRM)) /* Check if VRM bit is not set. */
3348 {
3349 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3350 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3351 * actually used? */
3352 ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3353 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3354 }
3355 else
3356 LogRel2(("AC97: Variable rate microphone audio (VRM) is not supported\n"));
3357
3358 LogRel2(("AC97: Setting extended audio control to %#x\n", u32));
3359 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32);
3360#else /* !IN_RING3 */
3361 rc = VINF_IOM_R3_IOPORT_WRITE;
3362#endif
3363 break;
3364 case AC97_PCM_Front_DAC_Rate: /* Output slots 3, 4, 6. */
3365#ifdef IN_RING3
3366 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3367 {
3368 LogRel2(("AC97: Setting front DAC rate to 0x%x\n", u32));
3369 ichac97MixerSet(pThis, offPort, u32);
3370 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3371 * actually used? */
3372 ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3373 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3374 }
3375 else
3376 LogRel2(("AC97: Setting front DAC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3377#else
3378 rc = VINF_IOM_R3_IOPORT_WRITE;
3379#endif
3380 break;
3381 case AC97_MIC_ADC_Rate: /* Input slot 6. */
3382#ifdef IN_RING3
3383 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRM)
3384 {
3385 LogRel2(("AC97: Setting microphone ADC rate to 0x%x\n", u32));
3386 ichac97MixerSet(pThis, offPort, u32);
3387 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3388 * actually used? */
3389 ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3390 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3391 }
3392 else
3393 LogRel2(("AC97: Setting microphone ADC rate (0x%x) when VRM is not set is forbidden, ignoring\n", u32));
3394#else
3395 rc = VINF_IOM_R3_IOPORT_WRITE;
3396#endif
3397 break;
3398 case AC97_PCM_LR_ADC_Rate: /* Input slots 3, 4. */
3399#ifdef IN_RING3
3400 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3401 {
3402 LogRel2(("AC97: Setting line-in ADC rate to 0x%x\n", u32));
3403 ichac97MixerSet(pThis, offPort, u32);
3404 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3405 * actually used? */
3406 ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3407 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3408 }
3409 else
3410 LogRel2(("AC97: Setting line-in ADC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3411#else
3412 rc = VINF_IOM_R3_IOPORT_WRITE;
3413#endif
3414 break;
3415 default:
3416 LogRel2(("AC97: Warning: Unimplemented NAMWrite (2 bytes) offPort=%#x <- %#x\n", offPort, u32));
3417 ichac97MixerSet(pThis, offPort, u32);
3418 break;
3419 }
3420 break;
3421 }
3422
3423 case 4:
3424 {
3425 LogRel2(("AC97: Warning: Unimplemented 4 byte NAMWrite: offPort=%#x <- %#x\n", offPort, u32));
3426 pThis->cas = 0;
3427 break;
3428 }
3429
3430 default:
3431 AssertMsgFailed(("Unhandled NAMWrite offPort=%#x, cb=%u u32=%#x\n", offPort, cb, u32));
3432 break;
3433 }
3434
3435 DEVAC97_UNLOCK(pDevIns, pThis);
3436 return rc;
3437}
3438
3439#ifdef IN_RING3
3440
3441
3442/*********************************************************************************************************************************
3443* State Saving & Loading *
3444*********************************************************************************************************************************/
3445
3446/**
3447 * Saves (serializes) an AC'97 stream using SSM.
3448 *
3449 * @param pDevIns Device instance.
3450 * @param pSSM Saved state manager (SSM) handle to use.
3451 * @param pStream AC'97 stream to save.
3452 */
3453static void ichac97R3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3454{
3455 PAC97BMREGS pRegs = &pStream->Regs;
3456 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3457
3458 pHlp->pfnSSMPutU32(pSSM, pRegs->bdbar);
3459 pHlp->pfnSSMPutU8( pSSM, pRegs->civ);
3460 pHlp->pfnSSMPutU8( pSSM, pRegs->lvi);
3461 pHlp->pfnSSMPutU16(pSSM, pRegs->sr);
3462 pHlp->pfnSSMPutU16(pSSM, pRegs->picb);
3463 pHlp->pfnSSMPutU8( pSSM, pRegs->piv);
3464 pHlp->pfnSSMPutU8( pSSM, pRegs->cr);
3465 pHlp->pfnSSMPutS32(pSSM, pRegs->bd_valid);
3466 pHlp->pfnSSMPutU32(pSSM, pRegs->bd.addr);
3467 pHlp->pfnSSMPutU32(pSSM, pRegs->bd.ctl_len);
3468}
3469
3470/**
3471 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3472 */
3473static DECLCALLBACK(int) ichac97R3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3474{
3475 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3476 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3477 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3478 LogFlowFuncEnter();
3479
3480 pHlp->pfnSSMPutU32(pSSM, pThis->glob_cnt);
3481 pHlp->pfnSSMPutU32(pSSM, pThis->glob_sta);
3482 pHlp->pfnSSMPutU32(pSSM, pThis->cas);
3483
3484 /*
3485 * The order that the streams are saved here is fixed, so don't change.
3486 */
3487 /** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
3488 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3489 ichac97R3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3490
3491 pHlp->pfnSSMPutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3492
3493 /* The stream order is against fixed and set in stone. */
3494 uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3495 afActiveStrms[AC97SOUNDSOURCE_PI_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX]);
3496 afActiveStrms[AC97SOUNDSOURCE_PO_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX]);
3497 afActiveStrms[AC97SOUNDSOURCE_MC_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX]);
3498 AssertCompile(RT_ELEMENTS(afActiveStrms) == 3);
3499 pHlp->pfnSSMPutMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3500
3501 LogFlowFuncLeaveRC(VINF_SUCCESS);
3502 return VINF_SUCCESS;
3503}
3504
3505/**
3506 * Loads an AC'97 stream from SSM.
3507 *
3508 * @returns VBox status code.
3509 * @param pDevIns The device instance.
3510 * @param pSSM Saved state manager (SSM) handle to use.
3511 * @param pStream AC'97 stream to load.
3512 */
3513static int ichac97R3LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3514{
3515 PAC97BMREGS pRegs = &pStream->Regs;
3516 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3517
3518 pHlp->pfnSSMGetU32(pSSM, &pRegs->bdbar);
3519 pHlp->pfnSSMGetU8( pSSM, &pRegs->civ);
3520 pHlp->pfnSSMGetU8( pSSM, &pRegs->lvi);
3521 pHlp->pfnSSMGetU16(pSSM, &pRegs->sr);
3522 pHlp->pfnSSMGetU16(pSSM, &pRegs->picb);
3523 pHlp->pfnSSMGetU8( pSSM, &pRegs->piv);
3524 pHlp->pfnSSMGetU8( pSSM, &pRegs->cr);
3525 pHlp->pfnSSMGetS32(pSSM, &pRegs->bd_valid);
3526 pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.addr);
3527 return pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.ctl_len);
3528}
3529
3530/**
3531 * @callback_method_impl{FNSSMDEVLOADEXEC}
3532 */
3533static DECLCALLBACK(int) ichac97R3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3534{
3535 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3536 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3537 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3538
3539 LogRel2(("ichac97LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3540
3541 AssertMsgReturn (uVersion == AC97_SAVED_STATE_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3542 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3543
3544 pHlp->pfnSSMGetU32(pSSM, &pThis->glob_cnt);
3545 pHlp->pfnSSMGetU32(pSSM, &pThis->glob_sta);
3546 pHlp->pfnSSMGetU32(pSSM, &pThis->cas);
3547
3548 /*
3549 * The order the streams are loaded here is critical (defined by
3550 * AC97SOUNDSOURCE_XX_INDEX), so don't touch!
3551 */
3552 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3553 {
3554 int rc2 = ichac97R3LoadStream(pDevIns, pSSM, &pThis->aStreams[i]);
3555 AssertRCReturn(rc2, rc2);
3556 }
3557
3558 pHlp->pfnSSMGetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3559
3560 ichac97R3MixerRecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
3561 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3562 ichac97MixerGet(pThis, AC97_Master_Volume_Mute));
3563 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT,
3564 ichac97MixerGet(pThis, AC97_PCM_Out_Volume_Mute));
3565 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3566 ichac97MixerGet(pThis, AC97_Line_In_Volume_Mute));
3567 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3568 ichac97MixerGet(pThis, AC97_Mic_Volume_Mute));
3569 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3570 ichac97MixerGet(pThis, AC97_Record_Gain_Mic_Mute));
3571 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3572 ichac97MixerGet(pThis, AC97_Record_Gain_Mute));
3573 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3574 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3575 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3576 ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
3577
3578 /*
3579 * Again the stream order is set is stone.
3580 */
3581 uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3582 int rc2 = pHlp->pfnSSMGetMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3583 AssertRCReturn(rc2, rc2);
3584
3585 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3586 {
3587 const bool fEnable = RT_BOOL(afActiveStrms[i]);
3588 const PAC97STREAM pStream = &pThis->aStreams[i];
3589 const PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[i];
3590
3591 rc2 = ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, fEnable);
3592 AssertRC(rc2);
3593 if ( fEnable
3594 && RT_SUCCESS(rc2))
3595 {
3596 /* Re-arm the timer for this stream. */
3597 /** @todo r=aeichner This causes a VM hang upon saved state resume when NetBSD is used as a guest
3598 * Stopping the timer if cTransferTicks is 0 is a workaround but needs further investigation,
3599 * see @bugref{9759} for more information. */
3600 if (pStreamCC->State.cTransferTicks)
3601 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3602 else
3603 PDMDevHlpTimerStop(pDevIns, pStream->hTimer);
3604 }
3605
3606 /* Keep going. */
3607 }
3608
3609 pThis->bup_flag = 0;
3610 pThis->last_samp = 0;
3611
3612 return VINF_SUCCESS;
3613}
3614
3615
3616/*********************************************************************************************************************************
3617* Debug Info Items *
3618*********************************************************************************************************************************/
3619
3620/** Used by ichac97R3DbgInfoStream and ichac97R3DbgInfoBDL. */
3621static int ichac97R3DbgLookupStrmIdx(PCDBGFINFOHLP pHlp, const char *pszArgs)
3622{
3623 if (pszArgs && *pszArgs)
3624 {
3625 int32_t idxStream;
3626 int rc = RTStrToInt32Full(pszArgs, 0, &idxStream);
3627 if (RT_SUCCESS(rc) && idxStream >= -1 && idxStream < AC97_MAX_STREAMS)
3628 return idxStream;
3629 pHlp->pfnPrintf(pHlp, "Argument '%s' is not a valid stream number!\n", pszArgs);
3630 }
3631 return -1;
3632}
3633
3634
3635/**
3636 * Generic buffer descriptor list dumper.
3637 */
3638static void ichac97R3DbgPrintBdl(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
3639 PCDBGFINFOHLP pHlp, const char *pszPrefix)
3640{
3641 uint8_t const bLvi = pStream->Regs.lvi;
3642 uint8_t const bCiv = pStream->Regs.civ;
3643 pHlp->pfnPrintf(pHlp, "%sBDL for stream #%u: @ %#RX32 LB 0x100; CIV=%#04x LVI=%#04x:\n",
3644 pszPrefix, pStream->u8SD, pStream->Regs.bdbar, bCiv, bLvi);
3645 if (pStream->Regs.bdbar != 0)
3646 {
3647 /* Read all in one go. */
3648 AC97BDLE aBdl[AC97_MAX_BDLE];
3649 RT_ZERO(aBdl);
3650 PDMDevHlpPCIPhysRead(pDevIns, pStream->Regs.bdbar, aBdl, sizeof(aBdl));
3651
3652 /* Get the audio props for the stream so we can translate the sizes correctly. */
3653 PDMAUDIOPCMPROPS Props;
3654 ichach97R3CalcStreamProps(pThis, pStream->u8SD, &Props);
3655
3656 /* Dump them. */
3657 uint64_t cbTotal = 0;
3658 uint64_t cbValid = 0;
3659 for (unsigned i = 0; i < RT_ELEMENTS(aBdl); i++)
3660 {
3661 aBdl[i].addr = RT_LE2H_U32(aBdl[i].addr);
3662 aBdl[i].ctl_len = RT_LE2H_U32(aBdl[i].ctl_len);
3663
3664 bool const fValid = bCiv <= bLvi
3665 ? i >= bCiv && i <= bLvi
3666 : (i >= bCiv && i < RT_ELEMENTS(aBdl)) || i <= bLvi;
3667
3668 uint32_t const cb = (aBdl[i].ctl_len & AC97_BD_LEN_MASK) * PDMAudioPropsSampleSize(&Props); /** @todo or frame size? OSDev says frame... */
3669 cbTotal += cb;
3670 if (fValid)
3671 cbValid += cb;
3672
3673 char szFlags[64];
3674 szFlags[0] = '\0';
3675 if (aBdl[i].ctl_len & ~(AC97_BD_LEN_MASK | AC97_BD_IOC | AC97_BD_BUP))
3676 RTStrPrintf(szFlags, sizeof(szFlags), " !!fFlags=%#x!!\n", aBdl[i].ctl_len & ~AC97_BD_LEN_MASK);
3677
3678 pHlp->pfnPrintf(pHlp, "%s %cBDLE%02u: %#010RX32 L %#06x / LB %#RX32 / %RU64ms%s%s%s%s\n",
3679 pszPrefix, fValid ? ' ' : '?', i, aBdl[i].addr,
3680 aBdl[i].ctl_len & AC97_BD_LEN_MASK, cb, PDMAudioPropsBytesToMilli(&Props, cb),
3681 aBdl[i].ctl_len & AC97_BD_IOC ? " ioc" : "",
3682 aBdl[i].ctl_len & AC97_BD_BUP ? " bup" : "",
3683 szFlags, !(aBdl[i].addr & 3) ? "" : " !!Addr!!");
3684 }
3685
3686 pHlp->pfnPrintf(pHlp, "%sTotal: %#RX64 bytes (%RU64), %RU64 ms; Valid: %#RX64 bytes (%RU64), %RU64 ms\n", pszPrefix,
3687 cbTotal, cbTotal, PDMAudioPropsBytesToMilli(&Props, cbTotal),
3688 cbValid, cbValid, PDMAudioPropsBytesToMilli(&Props, cbValid) );
3689 }
3690}
3691
3692
3693/**
3694 * @callback_method_impl{FNDBGFHANDLERDEV, ac97bdl}
3695 */
3696static DECLCALLBACK(void) ichac97R3DbgInfoBDL(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3697{
3698 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3699 int idxStream = ichac97R3DbgLookupStrmIdx(pHlp, pszArgs);
3700 if (idxStream != -1)
3701 ichac97R3DbgPrintBdl(pDevIns, pThis, &pThis->aStreams[idxStream], pHlp, "");
3702 else
3703 for (idxStream = 0; idxStream < AC97_MAX_STREAMS; ++idxStream)
3704 ichac97R3DbgPrintBdl(pDevIns, pThis, &pThis->aStreams[idxStream], pHlp, "");
3705}
3706
3707
3708/** Worker for ichac97R3DbgInfoStream. */
3709static void ichac97R3DbgPrintStream(PCDBGFINFOHLP pHlp, PAC97STREAM pStream, PAC97STREAMR3 pStreamR3)
3710{
3711 char szTmp[PDMAUDIOSTRMCFGTOSTRING_MAX];
3712 pHlp->pfnPrintf(pHlp, "Stream #%d: %s\n", pStream->u8SD,
3713 PDMAudioStrmCfgToString(&pStreamR3->State.Cfg, szTmp, sizeof(szTmp)));
3714 pHlp->pfnPrintf(pHlp, " BDBAR %#010RX32\n", pStream->Regs.bdbar);
3715 pHlp->pfnPrintf(pHlp, " CIV %#04RX8\n", pStream->Regs.civ);
3716 pHlp->pfnPrintf(pHlp, " LVI %#04RX8\n", pStream->Regs.lvi);
3717 pHlp->pfnPrintf(pHlp, " SR %#06RX16\n", pStream->Regs.sr);
3718 pHlp->pfnPrintf(pHlp, " PICB %#06RX16\n", pStream->Regs.picb);
3719 pHlp->pfnPrintf(pHlp, " PIV %#04RX8\n", pStream->Regs.piv);
3720 pHlp->pfnPrintf(pHlp, " CR %#04RX8\n", pStream->Regs.cr);
3721 if (pStream->Regs.bd_valid)
3722 {
3723 pHlp->pfnPrintf(pHlp, " BD.ADDR %#010RX32\n", pStream->Regs.bd.addr);
3724 pHlp->pfnPrintf(pHlp, " BD.LEN %#04RX16\n", (uint16_t)pStream->Regs.bd.ctl_len);
3725 pHlp->pfnPrintf(pHlp, " BD.CTL %#04RX16\n", (uint16_t)(pStream->Regs.bd.ctl_len >> 16));
3726 }
3727
3728 pHlp->pfnPrintf(pHlp, " offRead %#RX64\n", pStreamR3->State.offRead);
3729 pHlp->pfnPrintf(pHlp, " offWrite %#RX64\n", pStreamR3->State.offWrite);
3730 pHlp->pfnPrintf(pHlp, " uTimerHz %RU16\n", pStreamR3->State.uTimerHz);
3731 pHlp->pfnPrintf(pHlp, " cTransferTicks %RU64\n", pStreamR3->State.cTransferTicks);
3732 pHlp->pfnPrintf(pHlp, " cbTransferChunk %#RX32\n", pStreamR3->State.cbTransferChunk);
3733}
3734
3735
3736/**
3737 * @callback_method_impl{FNDBGFHANDLERDEV, ac97stream}
3738 */
3739static DECLCALLBACK(void) ichac97R3DbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3740{
3741 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3742 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3743 int idxStream = ichac97R3DbgLookupStrmIdx(pHlp, pszArgs);
3744 if (idxStream != -1)
3745 ichac97R3DbgPrintStream(pHlp, &pThis->aStreams[idxStream], &pThisCC->aStreams[idxStream]);
3746 else
3747 for (idxStream = 0; idxStream < AC97_MAX_STREAMS; ++idxStream)
3748 ichac97R3DbgPrintStream(pHlp, &pThis->aStreams[idxStream], &pThisCC->aStreams[idxStream]);
3749}
3750
3751
3752/*********************************************************************************************************************************
3753* PDMIBASE *
3754*********************************************************************************************************************************/
3755
3756/**
3757 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3758 */
3759static DECLCALLBACK(void *) ichac97R3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3760{
3761 PAC97STATER3 pThisCC = RT_FROM_MEMBER(pInterface, AC97STATER3, IBase);
3762 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
3763 return NULL;
3764}
3765
3766
3767/*********************************************************************************************************************************
3768* PDMDEVREG *
3769*********************************************************************************************************************************/
3770
3771/**
3772 * Powers off the device.
3773 *
3774 * @param pDevIns Device instance to power off.
3775 */
3776static DECLCALLBACK(void) ichac97R3PowerOff(PPDMDEVINS pDevIns)
3777{
3778 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3779 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3780
3781 LogRel2(("AC97: Powering off ...\n"));
3782
3783 /* Note: Involves mixer stream / sink destruction, so also do this here
3784 * instead of in ichac97R3Destruct(). */
3785 ichac97R3StreamsDestroy(pDevIns, pThis, pThisCC);
3786
3787 /*
3788 * Note: Destroy the mixer while powering off and *not* in ichac97R3Destruct,
3789 * giving the mixer the chance to release any references held to
3790 * PDM audio streams it maintains.
3791 */
3792 if (pThisCC->pMixer)
3793 {
3794 AudioMixerDestroy(pThisCC->pMixer, pDevIns);
3795 pThisCC->pMixer = NULL;
3796 }
3797}
3798
3799
3800/**
3801 * @interface_method_impl{PDMDEVREG,pfnReset}
3802 *
3803 * @remarks The original sources didn't install a reset handler, but it seems to
3804 * make sense to me so we'll do it.
3805 */
3806static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns)
3807{
3808 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3809 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3810
3811 LogRel(("AC97: Reset\n"));
3812
3813 /*
3814 * Reset the mixer too. The Windows XP driver seems to rely on
3815 * this. At least it wants to read the vendor id before it resets
3816 * the codec manually.
3817 */
3818 ichac97R3MixerReset(pThis, pThisCC);
3819
3820 /*
3821 * Reset all streams.
3822 */
3823 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3824 {
3825 ichac97R3StreamEnable(pDevIns, pThis, pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], false /* fEnable */);
3826 ichac97R3StreamReset(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
3827 }
3828
3829 /*
3830 * Reset mixer sinks.
3831 *
3832 * Do the reset here instead of in ichac97R3StreamReset();
3833 * the mixer sink(s) might still have data to be processed when an audio stream gets reset.
3834 */
3835 AudioMixerSinkReset(pThisCC->pSinkLineIn);
3836 AudioMixerSinkReset(pThisCC->pSinkMicIn);
3837 AudioMixerSinkReset(pThisCC->pSinkOut);
3838}
3839
3840
3841/**
3842 * Worker for ichac97R3Construct() and ichac97R3Attach().
3843 *
3844 * @returns VBox status code.
3845 * @param pDevIns The device instance.
3846 * @param pThisCC The ring-3 AC'97 device state.
3847 * @param iLun The logical unit which is being attached.
3848 * @param ppDrv Attached driver instance on success. Optional.
3849 */
3850static int ichac97R3AttachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned iLun, PAC97DRIVER *ppDrv)
3851{
3852 /*
3853 * Attach driver.
3854 */
3855 char *pszDesc = RTStrAPrintf2("Audio driver port (AC'97) for LUN #%u", iLun);
3856 AssertLogRelReturn(pszDesc, VERR_NO_STR_MEMORY);
3857
3858 PPDMIBASE pDrvBase;
3859 int rc = PDMDevHlpDriverAttach(pDevIns, iLun, &pThisCC->IBase, &pDrvBase, pszDesc);
3860 if (RT_SUCCESS(rc))
3861 {
3862 PAC97DRIVER pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
3863 if (pDrv)
3864 {
3865 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
3866 AssertPtr(pDrv->pConnector);
3867 if (RT_VALID_PTR(pDrv->pConnector))
3868 {
3869 pDrv->pDrvBase = pDrvBase;
3870 pDrv->uLUN = iLun;
3871 pDrv->pszDesc = pszDesc;
3872
3873 /* Attach to driver list if not attached yet. */
3874 if (!pDrv->fAttached)
3875 {
3876 RTListAppend(&pThisCC->lstDrv, &pDrv->Node);
3877 pDrv->fAttached = true;
3878 }
3879
3880 if (ppDrv)
3881 *ppDrv = pDrv;
3882 LogFunc(("LUN#%u: returns VINF_SUCCESS (pCon=%p)\n", iLun, pDrv->pConnector));
3883 return VINF_SUCCESS;
3884 }
3885 RTMemFree(pDrv);
3886 rc = VERR_PDM_MISSING_INTERFACE_BELOW;
3887 }
3888 else
3889 rc = VERR_NO_MEMORY;
3890 }
3891 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3892 LogFunc(("No attached driver for LUN #%u\n", iLun));
3893 else
3894 LogFunc(("Attached driver for LUN #%u failed: %Rrc\n", iLun, rc));
3895
3896 RTStrFree(pszDesc);
3897 LogFunc(("LUN#%u: rc=%Rrc\n", iLun, rc));
3898 return rc;
3899}
3900
3901/**
3902 * @interface_method_impl{PDMDEVREGR3,pfnAttach}
3903 */
3904static DECLCALLBACK(int) ichac97R3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3905{
3906 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3907 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3908 RT_NOREF(fFlags);
3909 LogFunc(("iLUN=%u, fFlags=%#x\n", iLUN, fFlags));
3910
3911 DEVAC97_LOCK(pDevIns, pThis);
3912
3913 PAC97DRIVER pDrv;
3914 int rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLUN, &pDrv);
3915 if (RT_SUCCESS(rc))
3916 {
3917 int rc2 = ichac97R3MixerAddDrv(pDevIns, pThisCC, pDrv);
3918 if (RT_FAILURE(rc2))
3919 LogFunc(("ichac97R3MixerAddDrv failed with %Rrc (ignored)\n", rc2));
3920 }
3921
3922 DEVAC97_UNLOCK(pDevIns, pThis);
3923
3924 return rc;
3925}
3926
3927/**
3928 * Worker for ichac97R3Detach that does all but freeing the pDrv structure.
3929 *
3930 * This is called to let the device detach from a driver for a specified LUN
3931 * at runtime.
3932 *
3933 * @param pDevIns The device instance.
3934 * @param pThisCC The ring-3 AC'97 device state.
3935 * @param pDrv Driver to detach from device.
3936 */
3937static void ichac97R3DetachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
3938{
3939 /* Remove the driver from our list and destory it's associated streams.
3940 This also will un-set the driver as a recording source (if associated). */
3941 ichac97R3MixerRemoveDrv(pDevIns, pThisCC, pDrv);
3942 LogFunc(("Detached LUN#%u\n", pDrv->uLUN));
3943}
3944
3945/**
3946 * @interface_method_impl{PDMDEVREG,pfnDetach}
3947 */
3948static DECLCALLBACK(void) ichac97R3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3949{
3950 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3951 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3952 RT_NOREF(fFlags);
3953
3954 LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
3955
3956 DEVAC97_LOCK(pDevIns, pThis);
3957
3958 PAC97DRIVER pDrv;
3959 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
3960 {
3961 if (pDrv->uLUN == iLUN)
3962 {
3963 ichac97R3DetachInternal(pDevIns, pThisCC, pDrv);
3964 RTStrFree(pDrv->pszDesc);
3965 RTMemFree(pDrv);
3966 DEVAC97_UNLOCK(pDevIns, pThis);
3967 return;
3968 }
3969 }
3970
3971 DEVAC97_UNLOCK(pDevIns, pThis);
3972 LogFunc(("LUN#%u was not found\n", iLUN));
3973}
3974
3975
3976/**
3977 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3978 */
3979static DECLCALLBACK(int) ichac97R3Destruct(PPDMDEVINS pDevIns)
3980{
3981 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
3982 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3983
3984 LogFlowFuncEnter();
3985
3986 PAC97DRIVER pDrv, pDrvNext;
3987 RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
3988 {
3989 RTListNodeRemove(&pDrv->Node);
3990 RTMemFree(pDrv->pszDesc);
3991 RTMemFree(pDrv);
3992 }
3993
3994 /* Sanity. */
3995 Assert(RTListIsEmpty(&pThisCC->lstDrv));
3996
3997 /* We don't always go via PowerOff, so make sure the mixer is destroyed. */
3998 if (pThisCC->pMixer)
3999 {
4000 AudioMixerDestroy(pThisCC->pMixer, pDevIns);
4001 pThisCC->pMixer = NULL;
4002 }
4003
4004 return VINF_SUCCESS;
4005}
4006
4007/**
4008 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4009 */
4010static DECLCALLBACK(int) ichac97R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4011{
4012 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4013 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4014 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4015 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4016 Assert(iInstance == 0); RT_NOREF(iInstance);
4017
4018 /*
4019 * Initialize data so we can run the destructor without scewing up.
4020 */
4021 pThisCC->pDevIns = pDevIns;
4022 pThisCC->IBase.pfnQueryInterface = ichac97R3QueryInterface;
4023 RTListInit(&pThisCC->lstDrv);
4024
4025 /*
4026 * Validate and read configuration.
4027 */
4028 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "BufSizeInMs|BufSizeOutMs|Codec|TimerHz|DebugEnabled|DebugPathOut", "");
4029
4030 /** @devcfgm{ac97,BufSizeInMs,uint16_t,0,2000,0,ms}
4031 * The size of the DMA buffer for input streams expressed in milliseconds. */
4032 int rc = pHlp->pfnCFGMQueryU16Def(pCfg, "BufSizeInMs", &pThis->cMsCircBufIn, 0);
4033 if (RT_FAILURE(rc))
4034 return PDMDEV_SET_ERROR(pDevIns, rc,
4035 N_("AC97 configuration error: failed to read 'BufSizeInMs' as 16-bit unsigned integer"));
4036 if (pThis->cMsCircBufIn > 2000)
4037 return PDMDEV_SET_ERROR(pDevIns, VERR_OUT_OF_RANGE,
4038 N_("AC97 configuration error: 'BufSizeInMs' is out of bound, max 2000 ms"));
4039
4040 /** @devcfgm{ac97,BufSizeOutMs,uint16_t,0,2000,0,ms}
4041 * The size of the DMA buffer for output streams expressed in milliseconds. */
4042 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "BufSizeOutMs", &pThis->cMsCircBufOut, 0);
4043 if (RT_FAILURE(rc))
4044 return PDMDEV_SET_ERROR(pDevIns, rc,
4045 N_("AC97 configuration error: failed to read 'BufSizeOutMs' as 16-bit unsigned integer"));
4046 if (pThis->cMsCircBufOut > 2000)
4047 return PDMDEV_SET_ERROR(pDevIns, VERR_OUT_OF_RANGE,
4048 N_("AC97 configuration error: 'BufSizeOutMs' is out of bound, max 2000 ms"));
4049
4050 /** @devcfgm{ac97,TimerHz,uint16_t,10,1000,100,ms}
4051 * Currently the approximate rate at which the asynchronous I/O threads move
4052 * data from/to the DMA buffer, thru the mixer and drivers stack, and
4053 * to/from the host device/whatever. (It does NOT govern any DMA timer rate any
4054 * more as might be hinted at by the name.) */
4055 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, AC97_TIMER_HZ_DEFAULT);
4056 if (RT_FAILURE(rc))
4057 return PDMDEV_SET_ERROR(pDevIns, rc,
4058 N_("AC'97 configuration error: failed to read 'TimerHz' as a 16-bit unsigned integer"));
4059 if (pThis->uTimerHz < 10 || pThis->uTimerHz > 1000)
4060 return PDMDEV_SET_ERROR(pDevIns, VERR_OUT_OF_RANGE,
4061 N_("AC'97 configuration error: 'TimerHz' is out of range (10-1000 Hz)"));
4062
4063 if (pThis->uTimerHz != AC97_TIMER_HZ_DEFAULT)
4064 LogRel(("AC97: Using custom device timer rate: %RU16 Hz\n", pThis->uTimerHz));
4065
4066 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "DebugEnabled", &pThisCC->Dbg.fEnabled, false);
4067 if (RT_FAILURE(rc))
4068 return PDMDEV_SET_ERROR(pDevIns, rc,
4069 N_("AC97 configuration error: failed to read debugging enabled flag as boolean"));
4070
4071 rc = pHlp->pfnCFGMQueryStringAllocDef(pCfg, "DebugPathOut", &pThisCC->Dbg.pszOutPath, NULL);
4072 if (RT_FAILURE(rc))
4073 return PDMDEV_SET_ERROR(pDevIns, rc,
4074 N_("AC97 configuration error: failed to read debugging output path flag as string"));
4075
4076 if (pThisCC->Dbg.fEnabled)
4077 LogRel2(("AC97: Debug output will be saved to '%s'\n", pThisCC->Dbg.pszOutPath));
4078
4079 /*
4080 * The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
4081 * in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
4082 * 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
4083 */
4084 char szCodec[20];
4085 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
4086 if (RT_FAILURE(rc))
4087 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4088 N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
4089 if (!strcmp(szCodec, "STAC9700"))
4090 pThis->enmCodecModel = AC97CODEC_STAC9700;
4091 else if (!strcmp(szCodec, "AD1980"))
4092 pThis->enmCodecModel = AC97CODEC_AD1980;
4093 else if (!strcmp(szCodec, "AD1981B"))
4094 pThis->enmCodecModel = AC97CODEC_AD1981B;
4095 else
4096 return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
4097 N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"), szCodec);
4098
4099 LogRel(("AC97: Using codec '%s'\n", szCodec));
4100
4101 /*
4102 * Use an own critical section for the device instead of the default
4103 * one provided by PDM. This allows fine-grained locking in combination
4104 * with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4105 */
4106 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "AC'97");
4107 AssertRCReturn(rc, rc);
4108
4109 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4110 AssertRCReturn(rc, rc);
4111
4112 /*
4113 * Initialize data (most of it anyway).
4114 */
4115 /* PCI Device */
4116 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4117 PCIDevSetVendorId(pPciDev, 0x8086); /* 00 ro - intel. */ Assert(pPciDev->abConfig[0x00] == 0x86); Assert(pPciDev->abConfig[0x01] == 0x80);
4118 PCIDevSetDeviceId(pPciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pPciDev->abConfig[0x02] == 0x15); Assert(pPciDev->abConfig[0x03] == 0x24);
4119 PCIDevSetCommand(pPciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pPciDev->abConfig[0x04] == 0x00); Assert(pPciDev->abConfig[0x05] == 0x00);
4120 PCIDevSetStatus(pPciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pPciDev->abConfig[0x06] == 0x80); Assert(pPciDev->abConfig[0x07] == 0x02);
4121 PCIDevSetRevisionId(pPciDev, 0x01); /* 08 ro - rid. */ Assert(pPciDev->abConfig[0x08] == 0x01);
4122 PCIDevSetClassProg(pPciDev, 0x00); /* 09 ro - pi. */ Assert(pPciDev->abConfig[0x09] == 0x00);
4123 PCIDevSetClassSub(pPciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pPciDev->abConfig[0x0a] == 0x01);
4124 PCIDevSetClassBase(pPciDev, 0x04); /* 0b ro - bcc; 04 == multimedia.*/Assert(pPciDev->abConfig[0x0b] == 0x04);
4125 PCIDevSetHeaderType(pPciDev, 0x00); /* 0e ro - headtyp. */ Assert(pPciDev->abConfig[0x0e] == 0x00);
4126 PCIDevSetBaseAddress(pPciDev, 0, /* 10 rw - nambar - native audio mixer base. */
4127 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x10] == 0x01); Assert(pPciDev->abConfig[0x11] == 0x00); Assert(pPciDev->abConfig[0x12] == 0x00); Assert(pPciDev->abConfig[0x13] == 0x00);
4128 PCIDevSetBaseAddress(pPciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
4129 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x14] == 0x01); Assert(pPciDev->abConfig[0x15] == 0x00); Assert(pPciDev->abConfig[0x16] == 0x00); Assert(pPciDev->abConfig[0x17] == 0x00);
4130 PCIDevSetInterruptLine(pPciDev, 0x00); /* 3c rw. */ Assert(pPciDev->abConfig[0x3c] == 0x00);
4131 PCIDevSetInterruptPin(pPciDev, 0x01); /* 3d ro - INTA#. */ Assert(pPciDev->abConfig[0x3d] == 0x01);
4132
4133 if (pThis->enmCodecModel == AC97CODEC_AD1980)
4134 {
4135 PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4136 PCIDevSetSubSystemId(pPciDev, 0x0177); /* 2e ro. */
4137 }
4138 else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
4139 {
4140 PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4141 PCIDevSetSubSystemId(pPciDev, 0x01ad); /* 2e ro. */
4142 }
4143 else
4144 {
4145 PCIDevSetSubSystemVendorId(pPciDev, 0x8086); /* 2c ro - Intel.) */
4146 PCIDevSetSubSystemId(pPciDev, 0x0000); /* 2e ro. */
4147 }
4148
4149 /*
4150 * Register the PCI device and associated I/O regions.
4151 */
4152 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4153 if (RT_FAILURE(rc))
4154 return rc;
4155
4156 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 0 /*iPciRegion*/, 256 /*cPorts*/,
4157 ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /*pvUser*/,
4158 "ICHAC97 NAM", NULL /*paExtDescs*/, &pThis->hIoPortsNam);
4159 AssertRCReturn(rc, rc);
4160
4161 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 1 /*iPciRegion*/, 64 /*cPorts*/,
4162 ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /*pvUser*/,
4163 "ICHAC97 NABM", g_aNabmPorts, &pThis->hIoPortsNabm);
4164 AssertRCReturn(rc, rc);
4165
4166 /*
4167 * Saved state.
4168 */
4169 rc = PDMDevHlpSSMRegister(pDevIns, AC97_SAVED_STATE_VERSION, sizeof(*pThis), ichac97R3SaveExec, ichac97R3LoadExec);
4170 if (RT_FAILURE(rc))
4171 return rc;
4172
4173 /*
4174 * Attach drivers. We ASSUME they are configured consecutively without any
4175 * gaps, so we stop when we hit the first LUN w/o a driver configured.
4176 */
4177 for (unsigned iLun = 0; ; iLun++)
4178 {
4179 AssertBreak(iLun < UINT8_MAX);
4180 LogFunc(("Trying to attach driver for LUN#%u ...\n", iLun));
4181 rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, NULL /* ppDrv */);
4182 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4183 {
4184 LogFunc(("cLUNs=%u\n", iLun));
4185 break;
4186 }
4187 AssertLogRelMsgReturn(RT_SUCCESS(rc), ("LUN#%u: rc=%Rrc\n", iLun, rc), rc);
4188 }
4189
4190 uint32_t fMixer = AUDMIXER_FLAGS_NONE;
4191 if (pThisCC->Dbg.fEnabled)
4192 fMixer |= AUDMIXER_FLAGS_DEBUG;
4193
4194 rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThisCC->pMixer);
4195 AssertRCReturn(rc, rc);
4196
4197 rc = AudioMixerCreateSink(pThisCC->pMixer, "Line In",
4198 PDMAUDIODIR_IN, pDevIns, &pThisCC->pSinkLineIn);
4199 AssertRCReturn(rc, rc);
4200 rc = AudioMixerCreateSink(pThisCC->pMixer, "Microphone In",
4201 PDMAUDIODIR_IN, pDevIns, &pThisCC->pSinkMicIn);
4202 AssertRCReturn(rc, rc);
4203 rc = AudioMixerCreateSink(pThisCC->pMixer, "PCM Output",
4204 PDMAUDIODIR_OUT, pDevIns, &pThisCC->pSinkOut);
4205 AssertRCReturn(rc, rc);
4206
4207 /*
4208 * Create all hardware streams.
4209 */
4210 AssertCompile(RT_ELEMENTS(pThis->aStreams) == AC97_MAX_STREAMS);
4211 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4212 {
4213 rc = ichac97R3StreamCreate(pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], i /* SD# */);
4214 AssertRCReturn(rc, rc);
4215 }
4216
4217 /*
4218 * Create the emulation timers (one per stream).
4219 *
4220 * We must the critical section for the timers as the device has a
4221 * noop section associated with it.
4222 *
4223 * Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's AC'97 driver
4224 * relies on exact (virtual) DMA timing and uses DMA Position Buffers
4225 * instead of the LPIB registers.
4226 */
4227 /** @todo r=bird: The need to use virtual sync is perhaps because TM
4228 * doesn't schedule regular TMCLOCK_VIRTUAL timers as accurately as it
4229 * should (VT-x preemption timer, etc). Hope to address that before
4230 * long. @bugref{9943}. */
4231 static const char * const s_apszNames[] = { "AC97 PI", "AC97 PO", "AC97 MC" };
4232 AssertCompile(RT_ELEMENTS(s_apszNames) == AC97_MAX_STREAMS);
4233 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4234 {
4235 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, ichac97R3Timer, &pThis->aStreams[i],
4236 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, s_apszNames[i], &pThis->aStreams[i].hTimer);
4237 AssertRCReturn(rc, rc);
4238
4239 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->aStreams[i].hTimer, &pThis->CritSect);
4240 AssertRCReturn(rc, rc);
4241 }
4242
4243 ichac97R3Reset(pDevIns);
4244
4245 /*
4246 * Info items.
4247 */
4248 //PDMDevHlpDBGFInfoRegister(pDevIns, "ac97", "AC'97 registers. (ac97 [register case-insensitive])", ichac97R3DbgInfo);
4249 PDMDevHlpDBGFInfoRegister(pDevIns, "ac97bdl", "AC'97 buffer descriptor list (BDL). (ac97bdl [stream number])",
4250 ichac97R3DbgInfoBDL);
4251 PDMDevHlpDBGFInfoRegister(pDevIns, "ac97stream", "AC'97 stream info. (ac97stream [stream number])", ichac97R3DbgInfoStream);
4252 //PDMDevHlpDBGFInfoRegister(pDevIns, "ac97mixer", "AC'97 mixer state.", ichac97R3DbgInfoMixer);
4253
4254 /*
4255 * Register statistics.
4256 */
4257 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmReads, STAMTYPE_COUNTER, "UnimplementedNabmReads", STAMUNIT_OCCURENCES, "Unimplemented NABM register reads.");
4258 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmWrites, STAMTYPE_COUNTER, "UnimplementedNabmWrites", STAMUNIT_OCCURENCES, "Unimplemented NABM register writes.");
4259# ifdef VBOX_WITH_STATISTICS
4260 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
4261 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
4262 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
4263 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
4264 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
4265# endif
4266 for (unsigned idxStream = 0; idxStream < RT_ELEMENTS(pThis->aStreams); idxStream++)
4267 {
4268 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.offRead, STAMTYPE_U64, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4269 "Virtual internal buffer read position.", "Stream%u/offRead", idxStream);
4270 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.offWrite, STAMTYPE_U64, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4271 "Virtual internal buffer write position.", "Stream%u/offWrite", idxStream);
4272 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaBufSize, STAMTYPE_U32, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4273 "Size of the internal DMA buffer.", "Stream%u/DMABufSize", idxStream);
4274 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaBufUsed, STAMTYPE_U32, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4275 "Number of bytes used in the internal DMA buffer.", "Stream%u/DMABufUsed", idxStream);
4276 }
4277
4278 LogFlowFuncLeaveRC(VINF_SUCCESS);
4279 return VINF_SUCCESS;
4280}
4281
4282#else /* !IN_RING3 */
4283
4284/**
4285 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4286 */
4287static DECLCALLBACK(int) ichac97RZConstruct(PPDMDEVINS pDevIns)
4288{
4289 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4290 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4291
4292 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4293 AssertRCReturn(rc, rc);
4294
4295 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNam, ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /*pvUser*/);
4296 AssertRCReturn(rc, rc);
4297 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNabm, ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /*pvUser*/);
4298 AssertRCReturn(rc, rc);
4299
4300 return VINF_SUCCESS;
4301}
4302
4303#endif /* !IN_RING3 */
4304
4305/**
4306 * The device registration structure.
4307 */
4308const PDMDEVREG g_DeviceICHAC97 =
4309{
4310 /* .u32Version = */ PDM_DEVREG_VERSION,
4311 /* .uReserved0 = */ 0,
4312 /* .szName = */ "ichac97",
4313 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE
4314 | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION /* stream clearnup with working drivers */,
4315 /* .fClass = */ PDM_DEVREG_CLASS_AUDIO,
4316 /* .cMaxInstances = */ 1,
4317 /* .uSharedVersion = */ 42,
4318 /* .cbInstanceShared = */ sizeof(AC97STATE),
4319 /* .cbInstanceCC = */ CTX_EXPR(sizeof(AC97STATER3), 0, 0),
4320 /* .cbInstanceRC = */ 0,
4321 /* .cMaxPciDevices = */ 1,
4322 /* .cMaxMsixVectors = */ 0,
4323 /* .pszDescription = */ "ICH AC'97 Audio Controller",
4324#if defined(IN_RING3)
4325 /* .pszRCMod = */ "VBoxDDRC.rc",
4326 /* .pszR0Mod = */ "VBoxDDR0.r0",
4327 /* .pfnConstruct = */ ichac97R3Construct,
4328 /* .pfnDestruct = */ ichac97R3Destruct,
4329 /* .pfnRelocate = */ NULL,
4330 /* .pfnMemSetup = */ NULL,
4331 /* .pfnPowerOn = */ NULL,
4332 /* .pfnReset = */ ichac97R3Reset,
4333 /* .pfnSuspend = */ NULL,
4334 /* .pfnResume = */ NULL,
4335 /* .pfnAttach = */ ichac97R3Attach,
4336 /* .pfnDetach = */ ichac97R3Detach,
4337 /* .pfnQueryInterface = */ NULL,
4338 /* .pfnInitComplete = */ NULL,
4339 /* .pfnPowerOff = */ ichac97R3PowerOff,
4340 /* .pfnSoftReset = */ NULL,
4341 /* .pfnReserved0 = */ NULL,
4342 /* .pfnReserved1 = */ NULL,
4343 /* .pfnReserved2 = */ NULL,
4344 /* .pfnReserved3 = */ NULL,
4345 /* .pfnReserved4 = */ NULL,
4346 /* .pfnReserved5 = */ NULL,
4347 /* .pfnReserved6 = */ NULL,
4348 /* .pfnReserved7 = */ NULL,
4349#elif defined(IN_RING0)
4350 /* .pfnEarlyConstruct = */ NULL,
4351 /* .pfnConstruct = */ ichac97RZConstruct,
4352 /* .pfnDestruct = */ NULL,
4353 /* .pfnFinalDestruct = */ NULL,
4354 /* .pfnRequest = */ NULL,
4355 /* .pfnReserved0 = */ NULL,
4356 /* .pfnReserved1 = */ NULL,
4357 /* .pfnReserved2 = */ NULL,
4358 /* .pfnReserved3 = */ NULL,
4359 /* .pfnReserved4 = */ NULL,
4360 /* .pfnReserved5 = */ NULL,
4361 /* .pfnReserved6 = */ NULL,
4362 /* .pfnReserved7 = */ NULL,
4363#elif defined(IN_RC)
4364 /* .pfnConstruct = */ ichac97RZConstruct,
4365 /* .pfnReserved0 = */ NULL,
4366 /* .pfnReserved1 = */ NULL,
4367 /* .pfnReserved2 = */ NULL,
4368 /* .pfnReserved3 = */ NULL,
4369 /* .pfnReserved4 = */ NULL,
4370 /* .pfnReserved5 = */ NULL,
4371 /* .pfnReserved6 = */ NULL,
4372 /* .pfnReserved7 = */ NULL,
4373#else
4374# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4375#endif
4376 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4377};
4378
4379#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4380
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