VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 89692

Last change on this file since 89692 was 89692, checked in by vboxsync, 3 years ago

DevIchAc97: Don't recheck sink active status in ichac97R3StreamUpdateDma, caller already does that. bugref:9890
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1/* $Id: DevIchAc97.cpp 89692 2021-06-14 20:54:07Z vboxsync $ */
2/** @file
3 * DevIchAc97 - VBox ICH AC97 Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_AC97
23#include <VBox/log.h>
24#include <VBox/vmm/pdmdev.h>
25#include <VBox/vmm/pdmaudioifs.h>
26#include <VBox/vmm/pdmaudioinline.h>
27#include <VBox/AssertGuest.h>
28
29#include <iprt/assert.h>
30#ifdef IN_RING3
31# ifdef DEBUG
32# include <iprt/file.h>
33# endif
34# include <iprt/mem.h>
35# include <iprt/semaphore.h>
36# include <iprt/string.h>
37# include <iprt/uuid.h>
38#endif
39
40#include "VBoxDD.h"
41
42#include "AudioMixBuffer.h"
43#include "AudioMixer.h"
44#include "AudioHlp.h"
45
46
47/*********************************************************************************************************************************
48* Defined Constants And Macros *
49*********************************************************************************************************************************/
50/** Current saved state version. */
51#define AC97_SAVED_STATE_VERSION 1
52
53/** Default timer frequency (in Hz). */
54#define AC97_TIMER_HZ_DEFAULT 100
55
56/** Maximum number of streams we support. */
57#define AC97_MAX_STREAMS 3
58
59/** Maximum FIFO size (in bytes) - unused. */
60#define AC97_FIFO_MAX 256
61
62/** @name AC97_SR_XXX - Status Register Bits (AC97_NABM_OFF_SR, PI_SR, PO_SR, MC_SR).
63 * @{ */
64#define AC97_SR_FIFOE RT_BIT(4) /**< rwc, FIFO error. */
65#define AC97_SR_BCIS RT_BIT(3) /**< rwc, Buffer completion interrupt status. */
66#define AC97_SR_LVBCI RT_BIT(2) /**< rwc, Last valid buffer completion interrupt. */
67#define AC97_SR_CELV RT_BIT(1) /**< ro, Current equals last valid. */
68#define AC97_SR_DCH RT_BIT(0) /**< ro, Controller halted. */
69#define AC97_SR_VALID_MASK (RT_BIT(5) - 1)
70#define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)
71#define AC97_SR_RO_MASK (AC97_SR_DCH | AC97_SR_CELV)
72#define AC97_SR_INT_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)
73/** @} */
74
75/** @name AC97_CR_XXX - Control Register Bits (AC97_NABM_OFF_CR, PI_CR, PO_CR, MC_CR).
76 * @{ */
77#define AC97_CR_IOCE RT_BIT(4) /**< rw, Interrupt On Completion Enable. */
78#define AC97_CR_FEIE RT_BIT(3) /**< rw FIFO Error Interrupt Enable. */
79#define AC97_CR_LVBIE RT_BIT(2) /**< rw Last Valid Buffer Interrupt Enable. */
80#define AC97_CR_RR RT_BIT(1) /**< rw Reset Registers. */
81#define AC97_CR_RPBM RT_BIT(0) /**< rw Run/Pause Bus Master. */
82#define AC97_CR_VALID_MASK (RT_BIT(5) - 1)
83#define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE | AC97_CR_FEIE | AC97_CR_LVBIE)
84/** @} */
85
86/** @name AC97_GC_XXX - Global Control Bits (see AC97_GLOB_CNT). */
87#define AC97_GC_WR 4 /**< rw Warm reset. */
88#define AC97_GC_CR 2 /**< rw Cold reset. */
89#define AC97_GC_VALID_MASK (RT_BIT(6) - 1)
90/** @} */
91
92/** @name AC97_GS_XXX - Global Status Bits (AC97_GLOB_STA).
93 * @{ */
94#define AC97_GS_MD3 RT_BIT(17) /**< rw */
95#define AC97_GS_AD3 RT_BIT(16) /**< rw */
96#define AC97_GS_RCS RT_BIT(15) /**< rwc */
97#define AC97_GS_B3S12 RT_BIT(14) /**< ro */
98#define AC97_GS_B2S12 RT_BIT(13) /**< ro */
99#define AC97_GS_B1S12 RT_BIT(12) /**< ro */
100#define AC97_GS_S1R1 RT_BIT(11) /**< rwc */
101#define AC97_GS_S0R1 RT_BIT(10) /**< rwc */
102#define AC97_GS_S1CR RT_BIT(9) /**< ro */
103#define AC97_GS_S0CR RT_BIT(8) /**< ro */
104#define AC97_GS_MINT RT_BIT(7) /**< ro */
105#define AC97_GS_POINT RT_BIT(6) /**< ro */
106#define AC97_GS_PIINT RT_BIT(5) /**< ro */
107#define AC97_GS_RSRVD (RT_BIT(4) | RT_BIT(3))
108#define AC97_GS_MOINT RT_BIT(2) /**< ro */
109#define AC97_GS_MIINT RT_BIT(1) /**< ro */
110#define AC97_GS_GSCI RT_BIT(0) /**< rwc */
111#define AC97_GS_RO_MASK ( AC97_GS_B3S12 \
112 | AC97_GS_B2S12 \
113 | AC97_GS_B1S12 \
114 | AC97_GS_S1CR \
115 | AC97_GS_S0CR \
116 | AC97_GS_MINT \
117 | AC97_GS_POINT \
118 | AC97_GS_PIINT \
119 | AC97_GS_RSRVD \
120 | AC97_GS_MOINT \
121 | AC97_GS_MIINT)
122#define AC97_GS_VALID_MASK (RT_BIT(18) - 1)
123#define AC97_GS_WCLEAR_MASK (AC97_GS_RCS | AC97_GS_S1R1 | AC97_GS_S0R1 | AC97_GS_GSCI)
124/** @} */
125
126/** @name Buffer Descriptor (BDLE, BDL).
127 * @{ */
128#define AC97_BD_IOC RT_BIT(31) /**< Interrupt on Completion. */
129#define AC97_BD_BUP RT_BIT(30) /**< Buffer Underrun Policy. */
130
131#define AC97_BD_LEN_MASK 0xFFFF /**< Mask for the BDL buffer length. */
132
133#define AC97_BD_LEN_CTL_MBZ UINT32_C(0x3fff0000) /**< Must-be-zero mask for AC97BDLE.ctl_len. */
134
135#define AC97_MAX_BDLE 32 /**< Maximum number of BDLEs. */
136/** @} */
137
138/** @name Extended Audio ID Register (EAID).
139 * @{ */
140#define AC97_EAID_VRA RT_BIT(0) /**< Variable Rate Audio. */
141#define AC97_EAID_VRM RT_BIT(3) /**< Variable Rate Mic Audio. */
142#define AC97_EAID_REV0 RT_BIT(10) /**< AC'97 revision compliance. */
143#define AC97_EAID_REV1 RT_BIT(11) /**< AC'97 revision compliance. */
144/** @} */
145
146/** @name Extended Audio Control and Status Register (EACS).
147 * @{ */
148#define AC97_EACS_VRA RT_BIT(0) /**< Variable Rate Audio (4.2.1.1). */
149#define AC97_EACS_VRM RT_BIT(3) /**< Variable Rate Mic Audio (4.2.1.1). */
150/** @} */
151
152/** @name Baseline Audio Register Set (BARS).
153 * @{ */
154#define AC97_BARS_VOL_MASK 0x1f /**< Volume mask for the Baseline Audio Register Set (5.7.2). */
155#define AC97_BARS_GAIN_MASK 0x0f /**< Gain mask for the Baseline Audio Register Set. */
156#define AC97_BARS_VOL_MUTE_SHIFT 15 /**< Mute bit shift for the Baseline Audio Register Set (5.7.2). */
157/** @} */
158
159/** AC'97 uses 1.5dB steps, we use 0.375dB steps: 1 AC'97 step equals 4 PDM steps. */
160#define AC97_DB_FACTOR 4
161
162/** @name Recording inputs?
163 * @{ */
164#define AC97_REC_MIC UINT8_C(0)
165#define AC97_REC_CD UINT8_C(1)
166#define AC97_REC_VIDEO UINT8_C(2)
167#define AC97_REC_AUX UINT8_C(3)
168#define AC97_REC_LINE_IN UINT8_C(4)
169#define AC97_REC_STEREO_MIX UINT8_C(5)
170#define AC97_REC_MONO_MIX UINT8_C(6)
171#define AC97_REC_PHONE UINT8_C(7)
172#define AC97_REC_MASK UINT8_C(7)
173/** @} */
174
175/** @name Mixer registers / NAM BAR registers?
176 * @{ */
177#define AC97_Reset 0x00
178#define AC97_Master_Volume_Mute 0x02
179#define AC97_Headphone_Volume_Mute 0x04 /**< Also known as AUX, see table 16, section 5.7. */
180#define AC97_Master_Volume_Mono_Mute 0x06
181#define AC97_Master_Tone_RL 0x08
182#define AC97_PC_BEEP_Volume_Mute 0x0a
183#define AC97_Phone_Volume_Mute 0x0c
184#define AC97_Mic_Volume_Mute 0x0e
185#define AC97_Line_In_Volume_Mute 0x10
186#define AC97_CD_Volume_Mute 0x12
187#define AC97_Video_Volume_Mute 0x14
188#define AC97_Aux_Volume_Mute 0x16
189#define AC97_PCM_Out_Volume_Mute 0x18
190#define AC97_Record_Select 0x1a
191#define AC97_Record_Gain_Mute 0x1c
192#define AC97_Record_Gain_Mic_Mute 0x1e
193#define AC97_General_Purpose 0x20
194#define AC97_3D_Control 0x22
195#define AC97_AC_97_RESERVED 0x24
196#define AC97_Powerdown_Ctrl_Stat 0x26
197#define AC97_Extended_Audio_ID 0x28
198#define AC97_Extended_Audio_Ctrl_Stat 0x2a
199#define AC97_PCM_Front_DAC_Rate 0x2c
200#define AC97_PCM_Surround_DAC_Rate 0x2e
201#define AC97_PCM_LFE_DAC_Rate 0x30
202#define AC97_PCM_LR_ADC_Rate 0x32
203#define AC97_MIC_ADC_Rate 0x34
204#define AC97_6Ch_Vol_C_LFE_Mute 0x36
205#define AC97_6Ch_Vol_L_R_Surround_Mute 0x38
206#define AC97_Vendor_Reserved 0x58
207#define AC97_AD_Misc 0x76
208#define AC97_Vendor_ID1 0x7c
209#define AC97_Vendor_ID2 0x7e
210/** @} */
211
212/** @name Analog Devices miscellaneous regiter bits used in AD1980.
213 * @{ */
214#define AC97_AD_MISC_LOSEL RT_BIT(5) /**< Surround (rear) goes to line out outputs. */
215#define AC97_AD_MISC_HPSEL RT_BIT(10) /**< PCM (front) goes to headphone outputs. */
216/** @} */
217
218
219/** @name BUP flag values.
220 * @{ */
221#define BUP_SET RT_BIT_32(0)
222#define BUP_LAST RT_BIT_32(1)
223/** @} */
224
225/** @name AC'97 source indices.
226 * @note The order of these indices is fixed (also applies for saved states) for
227 * the moment. So make sure you know what you're done when altering this!
228 * @{
229 */
230#define AC97SOUNDSOURCE_PI_INDEX 0 /**< PCM in */
231#define AC97SOUNDSOURCE_PO_INDEX 1 /**< PCM out */
232#define AC97SOUNDSOURCE_MC_INDEX 2 /**< Mic in */
233#define AC97SOUNDSOURCE_MAX 3 /**< Max sound sources. */
234/** @} */
235
236/** Port number (offset into NABM BAR) to stream index. */
237#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
238/** Port number (offset into NABM BAR) to stream index, but no masking. */
239#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
240
241/** @name Stream offsets
242 * @{ */
243#define AC97_NABM_OFF_BDBAR 0x0 /**< Buffer Descriptor Base Address */
244#define AC97_NABM_OFF_CIV 0x4 /**< Current Index Value */
245#define AC97_NABM_OFF_LVI 0x5 /**< Last Valid Index */
246#define AC97_NABM_OFF_SR 0x6 /**< Status Register */
247#define AC97_NABM_OFF_PICB 0x8 /**< Position in Current Buffer */
248#define AC97_NABM_OFF_PIV 0xa /**< Prefetched Index Value */
249#define AC97_NABM_OFF_CR 0xb /**< Control Register */
250#define AC97_NABM_OFF_MASK 0xf /**< Mask for getting the the per-stream register. */
251/** @} */
252
253
254/** @name PCM in NABM BAR registers (0x00..0x0f).
255 * @{ */
256#define PI_BDBAR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x0) /**< PCM in: Buffer Descriptor Base Address */
257#define PI_CIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x4) /**< PCM in: Current Index Value */
258#define PI_LVI (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x5) /**< PCM in: Last Valid Index */
259#define PI_SR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x6) /**< PCM in: Status Register */
260#define PI_PICB (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x8) /**< PCM in: Position in Current Buffer */
261#define PI_PIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xa) /**< PCM in: Prefetched Index Value */
262#define PI_CR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xb) /**< PCM in: Control Register */
263/** @} */
264
265/** @name PCM out NABM BAR registers (0x10..0x1f).
266 * @{ */
267#define PO_BDBAR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x0) /**< PCM out: Buffer Descriptor Base Address */
268#define PO_CIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x4) /**< PCM out: Current Index Value */
269#define PO_LVI (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x5) /**< PCM out: Last Valid Index */
270#define PO_SR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x6) /**< PCM out: Status Register */
271#define PO_PICB (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x8) /**< PCM out: Position in Current Buffer */
272#define PO_PIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xa) /**< PCM out: Prefetched Index Value */
273#define PO_CR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xb) /**< PCM out: Control Register */
274/** @} */
275
276/** @name Mic in NABM BAR registers (0x20..0x2f).
277 * @{ */
278#define MC_BDBAR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x0) /**< PCM in: Buffer Descriptor Base Address */
279#define MC_CIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x4) /**< PCM in: Current Index Value */
280#define MC_LVI (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x5) /**< PCM in: Last Valid Index */
281#define MC_SR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x6) /**< PCM in: Status Register */
282#define MC_PICB (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x8) /**< PCM in: Position in Current Buffer */
283#define MC_PIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xa) /**< PCM in: Prefetched Index Value */
284#define MC_CR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xb) /**< PCM in: Control Register */
285/** @} */
286
287/** @name Misc NABM BAR registers.
288 * @{ */
289/** NABMBAR: Global Control Register.
290 * @note This is kind of in the MIC IN area. */
291#define AC97_GLOB_CNT 0x2c
292/** NABMBAR: Global Status. */
293#define AC97_GLOB_STA 0x30
294/** Codec Access Semaphore Register. */
295#define AC97_CAS 0x34
296/** @} */
297
298
299/*********************************************************************************************************************************
300* Structures and Typedefs *
301*********************************************************************************************************************************/
302/** The ICH AC'97 (Intel) controller (shared). */
303typedef struct AC97STATE *PAC97STATE;
304/** The ICH AC'97 (Intel) controller (ring-3). */
305typedef struct AC97STATER3 *PAC97STATER3;
306
307/**
308 * Buffer Descriptor List Entry (BDLE).
309 *
310 * (See section 3.2.1 in Intel document number 252751-001, or section 1.2.2.1 in
311 * Intel document number 302349-003.)
312 */
313typedef struct AC97BDLE
314{
315 /** Location of data buffer (bits 31:1). */
316 uint32_t addr;
317 /** Flags (bits 31 + 30) and length (bits 15:0) of data buffer (in audio samples).
318 * @todo split up into two 16-bit fields. */
319 uint32_t ctl_len;
320} AC97BDLE;
321AssertCompileSize(AC97BDLE, 8);
322/** Pointer to BDLE. */
323typedef AC97BDLE *PAC97BDLE;
324
325/**
326 * Bus master register set for an audio stream.
327 *
328 * (See section 16.2 in Intel document 301473-002, or section 2.2 in Intel
329 * document 302349-003.)
330 */
331typedef struct AC97BMREGS
332{
333 uint32_t bdbar; /**< rw 0, Buffer Descriptor List: BAR (Base Address Register). */
334 uint8_t civ; /**< ro 0, Current index value. */
335 uint8_t lvi; /**< rw 0, Last valid index. */
336 uint16_t sr; /**< rw 1, Status register. */
337 uint16_t picb; /**< ro 0, Position in current buffer (samples left to process). */
338 uint8_t piv; /**< ro 0, Prefetched index value. */
339 uint8_t cr; /**< rw 0, Control register. */
340 int32_t bd_valid; /**< Whether current BDLE is initialized or not. */
341 AC97BDLE bd; /**< Current Buffer Descriptor List Entry (BDLE). */
342} AC97BMREGS;
343AssertCompileSizeAlignment(AC97BMREGS, 8);
344/** Pointer to the BM registers of an audio stream. */
345typedef AC97BMREGS *PAC97BMREGS;
346
347/**
348 * The internal state of an AC'97 stream.
349 */
350typedef struct AC97STREAMSTATE
351{
352 /** Critical section for this stream. */
353 RTCRITSECT CritSect;
354 /** Circular buffer (FIFO) for holding DMA'ed data. */
355 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
356#if HC_ARCH_BITS == 32
357 uint32_t Padding;
358#endif
359 /** Current circular buffer read offset (for tracing & logging). */
360 uint64_t offRead;
361 /** Current circular buffer write offset (for tracing & logging). */
362 uint64_t offWrite;
363 /** The stream's current configuration. */
364 PDMAUDIOSTREAMCFG Cfg; //+108
365 /** Timestamp of the last DMA data transfer. */
366 uint64_t tsTransferLast;
367 /** Timestamp of the next DMA data transfer.
368 * Next for determining the next scheduling window.
369 * Can be 0 if no next transfer is scheduled. */
370 uint64_t tsTransferNext;
371 /** Transfer chunk size (in bytes) of a transfer period. */
372 uint32_t cbTransferChunk;
373 /** The stream's timer Hz rate.
374 * This value can can be different from the device's default Hz rate,
375 * depending on the rate the stream expects (e.g. for 5.1 speaker setups).
376 * Set in R3StreamInit(). */
377 uint16_t uTimerHz;
378 /** Set if we've registered the asynchronous update job. */
379 bool fRegisteredAsyncUpdateJob;
380 uint8_t Padding3;
381 /** (Virtual) clock ticks per transfer. */
382 uint64_t cTransferTicks;
383 /** Timestamp (in ns) of last stream update. */
384 uint64_t tsLastUpdateNs;
385
386 /** Size of the DMA buffer (pCircBuf) in bytes. */
387 uint32_t StatDmaBufSize;
388 /** Number of used bytes in the DMA buffer (pCircBuf). */
389 uint32_t StatDmaBufUsed;
390} AC97STREAMSTATE;
391AssertCompileSizeAlignment(AC97STREAMSTATE, 8);
392/** Pointer to internal state of an AC'97 stream. */
393typedef AC97STREAMSTATE *PAC97STREAMSTATE;
394
395/**
396 * Runtime configurable debug stuff for an AC'97 stream.
397 */
398typedef struct AC97STREAMDEBUGRT
399{
400 /** Whether debugging is enabled or not. */
401 bool fEnabled;
402 uint8_t Padding[7];
403 /** File for dumping stream reads / writes.
404 * For input streams, this dumps data being written to the device FIFO,
405 * whereas for output streams this dumps data being read from the device FIFO. */
406 R3PTRTYPE(PAUDIOHLPFILE) pFileStream;
407 /** File for dumping DMA reads / writes.
408 * For input streams, this dumps data being written to the device DMA,
409 * whereas for output streams this dumps data being read from the device DMA. */
410 R3PTRTYPE(PAUDIOHLPFILE) pFileDMA;
411} AC97STREAMDEBUGRT;
412
413/**
414 * Debug stuff for an AC'97 stream.
415 */
416typedef struct AC97STREAMDEBUG
417{
418 /** Runtime debug stuff. */
419 AC97STREAMDEBUGRT Runtime;
420} AC97STREAMDEBUG;
421
422/**
423 * The shared AC'97 stream state.
424 */
425typedef struct AC97STREAM
426{
427 /** Stream number (SDn). */
428 uint8_t u8SD;
429 uint8_t abPadding0[7];
430 /** Bus master registers of this stream. */
431 AC97BMREGS Regs;
432 /** The timer for pumping data thru the attached LUN drivers. */
433 TMTIMERHANDLE hTimer;
434} AC97STREAM;
435AssertCompileSizeAlignment(AC97STREAM, 8);
436/** Pointer to a shared AC'97 stream state. */
437typedef AC97STREAM *PAC97STREAM;
438
439
440/**
441 * The ring-3 AC'97 stream state.
442 */
443typedef struct AC97STREAMR3
444{
445 /** Stream number (SDn). */
446 uint8_t u8SD;
447 uint8_t abPadding0[7];
448 /** Internal state of this stream. */
449 AC97STREAMSTATE State;
450 /** Debug stuff. */
451 AC97STREAMDEBUG Dbg;
452} AC97STREAMR3;
453AssertCompileSizeAlignment(AC97STREAMR3, 8);
454/** Pointer to an AC'97 stream state for ring-3. */
455typedef AC97STREAMR3 *PAC97STREAMR3;
456
457
458/**
459 * A driver stream (host backend).
460 *
461 * Each driver has its own instances of audio mixer streams, which then
462 * can go into the same (or even different) audio mixer sinks.
463 */
464typedef struct AC97DRIVERSTREAM
465{
466 /** Associated mixer stream handle. */
467 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
468} AC97DRIVERSTREAM;
469/** Pointer to a driver stream. */
470typedef AC97DRIVERSTREAM *PAC97DRIVERSTREAM;
471
472/**
473 * A host backend driver (LUN).
474 */
475typedef struct AC97DRIVER
476{
477 /** Node for storing this driver in our device driver list of AC97STATE. */
478 RTLISTNODER3 Node;
479 /** LUN # to which this driver has been assigned. */
480 uint8_t uLUN;
481 /** Whether this driver is in an attached state or not. */
482 bool fAttached;
483 uint8_t abPadding[6];
484 /** Pointer to the description string passed to PDMDevHlpDriverAttach(). */
485 R3PTRTYPE(char *) pszDesc;
486 /** Pointer to attached driver base interface. */
487 R3PTRTYPE(PPDMIBASE) pDrvBase;
488 /** Audio connector interface to the underlying host backend. */
489 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
490 /** Driver stream for line input. */
491 AC97DRIVERSTREAM LineIn;
492 /** Driver stream for mic input. */
493 AC97DRIVERSTREAM MicIn;
494 /** Driver stream for output. */
495 AC97DRIVERSTREAM Out;
496} AC97DRIVER;
497/** Pointer to a host backend driver (LUN). */
498typedef AC97DRIVER *PAC97DRIVER;
499
500/**
501 * Debug settings.
502 */
503typedef struct AC97STATEDEBUG
504{
505 /** Whether debugging is enabled or not. */
506 bool fEnabled;
507 bool afAlignment[7];
508 /** Path where to dump the debug output to.
509 * Can be NULL, in which the system's temporary directory will be used then. */
510 R3PTRTYPE(char *) pszOutPath;
511} AC97STATEDEBUG;
512
513
514/* Codec models. */
515typedef enum AC97CODEC
516{
517 AC97CODEC_INVALID = 0, /**< Customary illegal zero value. */
518 AC97CODEC_STAC9700, /**< SigmaTel STAC9700 */
519 AC97CODEC_AD1980, /**< Analog Devices AD1980 */
520 AC97CODEC_AD1981B, /**< Analog Devices AD1981B */
521 AC97CODEC_32BIT_HACK = 0x7fffffff
522} AC97CODEC;
523
524
525/**
526 * The shared AC'97 device state.
527 */
528typedef struct AC97STATE
529{
530 /** Critical section protecting the AC'97 state. */
531 PDMCRITSECT CritSect;
532 /** Global Control (Bus Master Control Register). */
533 uint32_t glob_cnt;
534 /** Global Status (Bus Master Control Register). */
535 uint32_t glob_sta;
536 /** Codec Access Semaphore Register (Bus Master Control Register). */
537 uint32_t cas;
538 uint32_t last_samp;
539 uint8_t mixer_data[256];
540 /** Array of AC'97 streams (parallel to AC97STATER3::aStreams). */
541 AC97STREAM aStreams[AC97_MAX_STREAMS];
542 /** The device timer Hz rate. Defaults to AC97_TIMER_HZ_DEFAULT_DEFAULT. */
543 uint16_t uTimerHz;
544 /** Config: Internal input DMA buffer size override, specified in milliseconds.
545 * Zero means default size according to buffer and stream config.
546 * @sa BufSizeInMs config value. */
547 uint16_t cMsCircBufIn;
548 /** Config: Internal output DMA buffer size override, specified in milliseconds.
549 * Zero means default size according to buffer and stream config.
550 * @sa BufSizeOutMs config value. */
551 uint16_t cMsCircBufOut;
552 uint16_t au16Padding1[1];
553 uint8_t silence[128];
554 uint32_t bup_flag;
555 /** Codec model. */
556 AC97CODEC enmCodecModel;
557
558 /** PCI region \#0: NAM I/O ports. */
559 IOMIOPORTHANDLE hIoPortsNam;
560 /** PCI region \#0: NANM I/O ports. */
561 IOMIOPORTHANDLE hIoPortsNabm;
562
563 STAMCOUNTER StatUnimplementedNabmReads;
564 STAMCOUNTER StatUnimplementedNabmWrites;
565#ifdef VBOX_WITH_STATISTICS
566 STAMPROFILE StatTimer;
567 STAMPROFILE StatIn;
568 STAMPROFILE StatOut;
569 STAMCOUNTER StatBytesRead;
570 STAMCOUNTER StatBytesWritten;
571#endif
572} AC97STATE;
573AssertCompileMemberAlignment(AC97STATE, aStreams, 8);
574AssertCompileMemberAlignment(AC97STATE, StatUnimplementedNabmReads, 8);
575#ifdef VBOX_WITH_STATISTICS
576AssertCompileMemberAlignment(AC97STATE, StatTimer, 8);
577AssertCompileMemberAlignment(AC97STATE, StatBytesRead, 8);
578AssertCompileMemberAlignment(AC97STATE, StatBytesWritten, 8);
579#endif
580
581
582/**
583 * The ring-3 AC'97 device state.
584 */
585typedef struct AC97STATER3
586{
587 /** Array of AC'97 streams (parallel to AC97STATE:aStreams). */
588 AC97STREAMR3 aStreams[AC97_MAX_STREAMS];
589 /** R3 pointer to the device instance. */
590 PPDMDEVINSR3 pDevIns;
591 /** List of associated LUN drivers (AC97DRIVER). */
592 RTLISTANCHORR3 lstDrv;
593 /** The device's software mixer. */
594 R3PTRTYPE(PAUDIOMIXER) pMixer;
595 /** Audio sink for PCM output. */
596 R3PTRTYPE(PAUDMIXSINK) pSinkOut;
597 /** Audio sink for line input. */
598 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
599 /** Audio sink for microphone input. */
600 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
601 /** The base interface for LUN\#0. */
602 PDMIBASE IBase;
603 /** Debug settings. */
604 AC97STATEDEBUG Dbg;
605} AC97STATER3;
606AssertCompileMemberAlignment(AC97STATER3, aStreams, 8);
607/** Pointer to the ring-3 AC'97 device state. */
608typedef AC97STATER3 *PAC97STATER3;
609
610
611/**
612 * Acquires the AC'97 lock.
613 */
614#define DEVAC97_LOCK(a_pDevIns, a_pThis) \
615 do { \
616 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
617 AssertRC(rcLock); \
618 } while (0)
619
620/**
621 * Acquires the AC'97 lock or returns.
622 */
623# define DEVAC97_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
624 do { \
625 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, a_rcBusy); \
626 if (rcLock == VINF_SUCCESS) \
627 break; \
628 AssertRC(rcLock); \
629 return rcLock; \
630 } while (0)
631
632/** Retrieves an attribute from a specific audio stream in RC. */
633#define DEVAC97_CTX_SUFF_SD(a_Var, a_SD) CTX_SUFF(a_Var)[a_SD]
634
635/**
636 * Releases the AC'97 lock.
637 */
638#define DEVAC97_UNLOCK(a_pDevIns, a_pThis) \
639 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
640
641/**
642 * Acquires the TM lock and AC'97 lock, returns on failure.
643 *
644 * @todo r=bird: Isn't this overkill for ring-0, only ring-3 access the timer
645 * from what I can tell (ichac97R3StreamTransferCalcNext,
646 * ichac97R3TimerSet, timer callback and state load).
647 */
648#define DEVAC97_LOCK_BOTH_RETURN(a_pDevIns, a_pThis, a_pStream, a_rcBusy) \
649 do { \
650 VBOXSTRICTRC rcLock = PDMDevHlpTimerLockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect, (a_rcBusy)); \
651 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
652 { /* likely */ } \
653 else \
654 { \
655 AssertRC(VBOXSTRICTRC_VAL(rcLock)); \
656 return rcLock; \
657 } \
658 } while (0)
659
660/**
661 * Releases the AC'97 lock and TM lock.
662 */
663#define DEVAC97_UNLOCK_BOTH(a_pDevIns, a_pThis, a_pStream) \
664 PDMDevHlpTimerUnlockClock2((a_pDevIns), (a_pStream)->hTimer, &(a_pThis)->CritSect)
665
666#ifndef VBOX_DEVICE_STRUCT_TESTCASE
667
668
669/*********************************************************************************************************************************
670* Internal Functions *
671*********************************************************************************************************************************/
672#ifdef IN_RING3
673static int ichac97R3StreamOpen(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
674 PAC97STREAMR3 pStreamCC, bool fForce);
675static int ichac97R3StreamClose(PAC97STREAM pStream);
676static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC);
677static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC);
678static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC);
679static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC);
680static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
681 PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax);
682static DECLCALLBACK(void) ichac97R3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser);
683
684static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns);
685
686static void ichac97R3MixerRemoveDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
687 PDMAUDIODIR enmDir, PDMAUDIOPATH enmPath);
688
689DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD);
690DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline);
691
692static void ichac97R3DbgPrintBdl(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
693 PCDBGFINFOHLP pHlp, const char *pszPrefix);
694#endif /* IN_RING3 */
695
696
697/*********************************************************************************************************************************
698* Global Variables *
699*********************************************************************************************************************************/
700#ifdef IN_RING3
701/** NABM I/O port descriptions. */
702static const IOMIOPORTDESC g_aNabmPorts[] =
703{
704 { "PCM IN - BDBAR", "PCM IN - BDBAR", NULL, NULL },
705 { "", NULL, NULL, NULL },
706 { "", NULL, NULL, NULL },
707 { "", NULL, NULL, NULL },
708 { "PCM IN - CIV", "PCM IN - CIV", NULL, NULL },
709 { "PCM IN - LVI", "PCM IN - LIV", NULL, NULL },
710 { "PCM IN - SR", "PCM IN - SR", NULL, NULL },
711 { "", NULL, NULL, NULL },
712 { "PCM IN - PICB", "PCM IN - PICB", NULL, NULL },
713 { "", NULL, NULL, NULL },
714 { "PCM IN - PIV", "PCM IN - PIV", NULL, NULL },
715 { "PCM IN - CR", "PCM IN - CR", NULL, NULL },
716 { "", NULL, NULL, NULL },
717 { "", NULL, NULL, NULL },
718 { "", NULL, NULL, NULL },
719 { "", NULL, NULL, NULL },
720
721 { "PCM OUT - BDBAR", "PCM OUT - BDBAR", NULL, NULL },
722 { "", NULL, NULL, NULL },
723 { "", NULL, NULL, NULL },
724 { "", NULL, NULL, NULL },
725 { "PCM OUT - CIV", "PCM OUT - CIV", NULL, NULL },
726 { "PCM OUT - LVI", "PCM OUT - LIV", NULL, NULL },
727 { "PCM OUT - SR", "PCM OUT - SR", NULL, NULL },
728 { "", NULL, NULL, NULL },
729 { "PCM OUT - PICB", "PCM OUT - PICB", NULL, NULL },
730 { "", NULL, NULL, NULL },
731 { "PCM OUT - PIV", "PCM OUT - PIV", NULL, NULL },
732 { "PCM OUT - CR", "PCM IN - CR", NULL, NULL },
733 { "", NULL, NULL, NULL },
734 { "", NULL, NULL, NULL },
735 { "", NULL, NULL, NULL },
736 { "", NULL, NULL, NULL },
737
738 { "MIC IN - BDBAR", "MIC IN - BDBAR", NULL, NULL },
739 { "", NULL, NULL, NULL },
740 { "", NULL, NULL, NULL },
741 { "", NULL, NULL, NULL },
742 { "MIC IN - CIV", "MIC IN - CIV", NULL, NULL },
743 { "MIC IN - LVI", "MIC IN - LIV", NULL, NULL },
744 { "MIC IN - SR", "MIC IN - SR", NULL, NULL },
745 { "", NULL, NULL, NULL },
746 { "MIC IN - PICB", "MIC IN - PICB", NULL, NULL },
747 { "", NULL, NULL, NULL },
748 { "MIC IN - PIV", "MIC IN - PIV", NULL, NULL },
749 { "MIC IN - CR", "MIC IN - CR", NULL, NULL },
750 { "GLOB CNT", "GLOB CNT", NULL, NULL },
751 { "", NULL, NULL, NULL },
752 { "", NULL, NULL, NULL },
753 { "", NULL, NULL, NULL },
754
755 { "GLOB STA", "GLOB STA", NULL, NULL },
756 { "", NULL, NULL, NULL },
757 { "", NULL, NULL, NULL },
758 { "", NULL, NULL, NULL },
759 { "CAS", "CAS", NULL, NULL },
760 { NULL, NULL, NULL, NULL },
761};
762
763/** @name Source indices
764 * @{ */
765# define AC97SOUNDSOURCE_PI_INDEX 0 /**< PCM in */
766# define AC97SOUNDSOURCE_PO_INDEX 1 /**< PCM out */
767# define AC97SOUNDSOURCE_MC_INDEX 2 /**< Mic in */
768# define AC97SOUNDSOURCE_MAX 3 /**< Max sound sources. */
769/** @} */
770
771/** Port number (offset into NABM BAR) to stream index. */
772# define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
773/** Port number (offset into NABM BAR) to stream index, but no masking. */
774# define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
775
776/** @name Stream offsets
777 * @{ */
778# define AC97_NABM_OFF_BDBAR 0x0 /**< Buffer Descriptor Base Address */
779# define AC97_NABM_OFF_CIV 0x4 /**< Current Index Value */
780# define AC97_NABM_OFF_LVI 0x5 /**< Last Valid Index */
781# define AC97_NABM_OFF_SR 0x6 /**< Status Register */
782# define AC97_NABM_OFF_PICB 0x8 /**< Position in Current Buffer */
783# define AC97_NABM_OFF_PIV 0xa /**< Prefetched Index Value */
784# define AC97_NABM_OFF_CR 0xb /**< Control Register */
785# define AC97_NABM_OFF_MASK 0xf /**< Mask for getting the the per-stream register. */
786/** @} */
787
788#endif /* IN_RING3 */
789
790
791
792static void ichac97WarmReset(PAC97STATE pThis)
793{
794 NOREF(pThis);
795}
796
797static void ichac97ColdReset(PAC97STATE pThis)
798{
799 NOREF(pThis);
800}
801
802
803#ifdef IN_RING3
804
805/**
806 * Retrieves the audio mixer sink of a corresponding AC'97 stream index.
807 *
808 * @returns Pointer to audio mixer sink if found, or NULL if not found / invalid.
809 * @param pThisCC The ring-3 AC'97 state.
810 * @param uIndex Stream index to get audio mixer sink for.
811 */
812DECLINLINE(PAUDMIXSINK) ichac97R3IndexToSink(PAC97STATER3 pThisCC, uint8_t uIndex)
813{
814 switch (uIndex)
815 {
816 case AC97SOUNDSOURCE_PI_INDEX: return pThisCC->pSinkLineIn;
817 case AC97SOUNDSOURCE_PO_INDEX: return pThisCC->pSinkOut;
818 case AC97SOUNDSOURCE_MC_INDEX: return pThisCC->pSinkMicIn;
819 default:
820 AssertMsgFailedReturn(("Wrong index %RU8\n", uIndex), NULL);
821 }
822}
823
824/**
825 * Fetches the next buffer descriptor (BDLE) updating the stream registers.
826 *
827 * This will skip zero length descriptors.
828 *
829 * @returns Zero, or AC97_SR_BCIS if skipped zero length buffer with IOC set.
830 * @param pDevIns The device instance.
831 * @param pStream AC'97 stream to fetch BDLE for.
832 * @param pStreamCC The AC'97 stream, ring-3 state.
833 *
834 * @remarks Updates CIV, PIV, BD and PICB.
835 *
836 * @note Both PIV and CIV will be zero after a stream reset, so the first
837 * time we advance the buffer position afterwards, CIV will remain zero
838 * and PIV becomes 1. Thus we will start processing from BDLE00 and
839 * not BDLE01 as CIV=0 may lead you to think.
840 */
841static uint32_t ichac97R3StreamFetchNextBdle(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
842{
843 RT_NOREF(pStreamCC);
844 uint32_t fSrBcis = 0;
845
846 /*
847 * Loop for skipping zero length entries.
848 */
849 for (;;)
850 {
851 /* Advance the buffer. */
852 pStream->Regs.civ = pStream->Regs.piv % AC97_MAX_BDLE /* (paranoia) */;
853 pStream->Regs.piv = (pStream->Regs.piv + 1) % AC97_MAX_BDLE;
854
855 /* Load it. */
856 AC97BDLE Bdle = { 0, 0 };
857 PDMDevHlpPCIPhysRead(pDevIns, pStream->Regs.bdbar + pStream->Regs.civ * sizeof(AC97BDLE), &Bdle, sizeof(AC97BDLE));
858 pStream->Regs.bd_valid = 1;
859 pStream->Regs.bd.addr = RT_H2LE_U32(Bdle.addr) & ~3;
860 pStream->Regs.bd.ctl_len = RT_H2LE_U32(Bdle.ctl_len);
861 pStream->Regs.picb = pStream->Regs.bd.ctl_len & AC97_BD_LEN_MASK;
862
863 LogFlowFunc(("BDLE%02u: %#RX32 L %#x / LB %#x, ctl=%#06x%s%s\n",
864 pStream->Regs.civ, pStream->Regs.bd.addr, pStream->Regs.bd.ctl_len & AC97_BD_LEN_MASK,
865 (pStream->Regs.bd.ctl_len & AC97_BD_LEN_MASK) * PDMAudioPropsSampleSize(&pStreamCC->State.Cfg.Props),
866 pStream->Regs.bd.ctl_len >> 16,
867 pStream->Regs.bd.ctl_len & AC97_BD_IOC ? " ioc" : "",
868 pStream->Regs.bd.ctl_len & AC97_BD_BUP ? " bup" : ""));
869
870 /* Complain about any reserved bits set in CTL and ADDR: */
871 ASSERT_GUEST_MSG(!(pStream->Regs.bd.ctl_len & AC97_BD_LEN_CTL_MBZ),
872 ("Reserved bits set: %#RX32\n", pStream->Regs.bd.ctl_len));
873 ASSERT_GUEST_MSG(!(RT_H2LE_U32(Bdle.addr) & 3),
874 ("Reserved addr bits set: %#RX32\n", RT_H2LE_U32(Bdle.addr) ));
875
876 /* If the length is non-zero or if we've reached LVI, we're done regardless
877 of what's been loaded. Otherwise, we skip zero length buffers. */
878 if (pStream->Regs.picb)
879 break;
880 if (pStream->Regs.civ == (pStream->Regs.lvi % AC97_MAX_BDLE /* (paranoia) */))
881 {
882 LogFunc(("BDLE%02u is zero length! Can't skip (CIV=LVI). %#RX32 %#RX32\n", pStream->Regs.civ, Bdle.addr, Bdle.ctl_len));
883 break;
884 }
885 LogFunc(("BDLE%02u is zero length! Skipping. %#RX32 %#RX32\n", pStream->Regs.civ, Bdle.addr, Bdle.ctl_len));
886
887 /* If the buffer has IOC set, make sure it's triggered by the caller. */
888 if (pStream->Regs.bd.ctl_len & AC97_BD_IOC)
889 fSrBcis |= AC97_SR_BCIS;
890 }
891
892 /* 1.2.4.2 PCM Buffer Restrictions (in 302349-003) - #1 */
893 ASSERT_GUEST_MSG(!(pStream->Regs.picb & 1),
894 ("Odd lengths buffers are not allowed: %#x (%d) samples\n", pStream->Regs.picb, pStream->Regs.picb));
895
896 /* 1.2.4.2 PCM Buffer Restrictions (in 302349-003) - #2 */
897 ASSERT_GUEST_MSG(pStream->Regs.picb > 0, ("Zero length buffers not allowed to terminate list (LVI=%u CIV=%u)\n",
898 pStream->Regs.lvi, pStream->Regs.civ));
899
900 return fSrBcis;
901}
902
903#endif /* IN_RING3 */
904
905/**
906 * Updates the status register (SR) of an AC'97 audio stream.
907 *
908 * @param pDevIns The device instance.
909 * @param pThis The shared AC'97 state.
910 * @param pStream AC'97 stream to update SR for.
911 * @param new_sr New value for status register (SR).
912 */
913static void ichac97StreamUpdateSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr)
914{
915 PAC97BMREGS pRegs = &pStream->Regs;
916
917 bool fSignal = false;
918 int iIRQL = 0;
919
920 uint32_t new_mask = new_sr & AC97_SR_INT_MASK;
921 uint32_t old_mask = pRegs->sr & AC97_SR_INT_MASK;
922
923 if (new_mask ^ old_mask)
924 {
925 /** @todo Is IRQ deasserted when only one of status bits is cleared? */
926 if (!new_mask)
927 {
928 fSignal = true;
929 iIRQL = 0;
930 }
931 else if ((new_mask & AC97_SR_LVBCI) && (pRegs->cr & AC97_CR_LVBIE))
932 {
933 fSignal = true;
934 iIRQL = 1;
935 }
936 else if ((new_mask & AC97_SR_BCIS) && (pRegs->cr & AC97_CR_IOCE))
937 {
938 fSignal = true;
939 iIRQL = 1;
940 }
941 }
942
943 pRegs->sr = new_sr;
944
945 LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n",
946 pRegs->sr & AC97_SR_BCIS, pRegs->sr & AC97_SR_LVBCI, pRegs->sr, fSignal, iIRQL));
947
948 if (fSignal)
949 {
950 static uint32_t const s_aMasks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT };
951 Assert(pStream->u8SD < AC97_MAX_STREAMS);
952 if (iIRQL)
953 pThis->glob_sta |= s_aMasks[pStream->u8SD];
954 else
955 pThis->glob_sta &= ~s_aMasks[pStream->u8SD];
956
957 LogFlowFunc(("Setting IRQ level=%d\n", iIRQL));
958 PDMDevHlpPCISetIrq(pDevIns, 0, iIRQL);
959 }
960}
961
962/**
963 * Writes a new value to a stream's status register (SR).
964 *
965 * @param pDevIns The device instance.
966 * @param pThis The shared AC'97 device state.
967 * @param pStream Stream to update SR for.
968 * @param u32Val New value to set the stream's SR to.
969 */
970static void ichac97StreamWriteSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t u32Val)
971{
972 PAC97BMREGS pRegs = &pStream->Regs;
973
974 Log3Func(("[SD%RU8] SR <- %#x (sr %#x)\n", pStream->u8SD, u32Val, pRegs->sr));
975
976 pRegs->sr |= u32Val & ~(AC97_SR_RO_MASK | AC97_SR_WCLEAR_MASK);
977 ichac97StreamUpdateSR(pDevIns, pThis, pStream, pRegs->sr & ~(u32Val & AC97_SR_WCLEAR_MASK));
978}
979
980#ifdef IN_RING3
981
982/**
983 * Returns whether an AC'97 stream is enabled or not.
984 *
985 * @returns VBox status code.
986 * @param pThisCC The ring-3 AC'97 device state.
987 * @param pStream Stream to return status for.
988 */
989static bool ichac97R3StreamIsEnabled(PAC97STATER3 pThisCC, PAC97STREAM pStream)
990{
991 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
992 bool fIsEnabled = pSink && (AudioMixerSinkGetStatus(pSink) & AUDMIXSINK_STS_RUNNING);
993
994 LogFunc(("[SD%RU8] fIsEnabled=%RTbool\n", pStream->u8SD, fIsEnabled));
995 return fIsEnabled;
996}
997
998/**
999 * Enables or disables an AC'97 audio stream.
1000 *
1001 * @returns VBox status code.
1002 * @param pDevIns The device instance.
1003 * @param pThis The shared AC'97 state.
1004 * @param pThisCC The ring-3 AC'97 state.
1005 * @param pStream The AC'97 stream to enable or disable (shared state).
1006 * @param pStreamCC The ring-3 stream state (matching to @a pStream).
1007 * @param fEnable Whether to enable or disable the stream.
1008 *
1009 */
1010static int ichac97R3StreamEnable(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
1011 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fEnable)
1012{
1013 ichac97R3StreamLock(pStreamCC);
1014 PAUDMIXSINK const pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
1015 AudioMixerSinkLock(pSink);
1016
1017 int rc = VINF_SUCCESS;
1018 if (fEnable)
1019 {
1020 if (pStreamCC->State.pCircBuf)
1021 RTCircBufReset(pStreamCC->State.pCircBuf);
1022
1023 rc = ichac97R3StreamOpen(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fForce */);
1024
1025 /* Re-register the update job with the AIO thread with correct sched hint.
1026 Note! We do not unregister it on disable because of draining. */
1027 if (pStreamCC->State.fRegisteredAsyncUpdateJob)
1028 AudioMixerSinkRemoveUpdateJob(pSink, ichac97R3StreamUpdateAsyncIoJob, pStreamCC);
1029 int rc2 = AudioMixerSinkAddUpdateJob(pSink, ichac97R3StreamUpdateAsyncIoJob, pStreamCC,
1030 pStreamCC->State.Cfg.Device.cMsSchedulingHint);
1031 AssertRC(rc2);
1032 pStreamCC->State.fRegisteredAsyncUpdateJob = RT_SUCCESS(rc2) || rc2 == VERR_ALREADY_EXISTS;
1033
1034 /* Open debug files: */
1035 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1036 { /* likely */ }
1037 else
1038 {
1039 if (!AudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileStream))
1040 {
1041 rc2 = AudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1042 &pStreamCC->State.Cfg.Props);
1043 AssertRC(rc2);
1044 }
1045
1046 if (!AudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileDMA))
1047 {
1048 rc2 = AudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileDMA, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1049 &pStreamCC->State.Cfg.Props);
1050 AssertRC(rc2);
1051 }
1052 }
1053
1054 if (RT_SUCCESS(rc))
1055 rc = AudioMixerSinkStart(pSink);
1056 }
1057 else
1058 {
1059 rc = ichac97R3StreamClose(pStream);
1060 if (RT_SUCCESS(rc))
1061 rc = AudioMixerSinkDrainAndStop(pSink,
1062 pStreamCC->State.pCircBuf ? (uint32_t)RTCircBufUsed(pStreamCC->State.pCircBuf) : 0);
1063 }
1064
1065 /* Make sure to leave the lock before (eventually) starting the timer. */
1066 AudioMixerSinkUnlock(pSink);
1067 ichac97R3StreamUnlock(pStreamCC);
1068 LogFunc(("[SD%RU8] fEnable=%RTbool, rc=%Rrc\n", pStream->u8SD, fEnable, rc));
1069 return rc;
1070}
1071
1072/**
1073 * Resets an AC'97 stream.
1074 *
1075 * @param pThis The shared AC'97 state.
1076 * @param pStream The AC'97 stream to reset (shared).
1077 * @param pStreamCC The AC'97 stream to reset (ring-3).
1078 */
1079static void ichac97R3StreamReset(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1080{
1081 ichac97R3StreamLock(pStreamCC);
1082
1083 LogFunc(("[SD%RU8]\n", pStream->u8SD));
1084
1085 if (pStreamCC->State.pCircBuf)
1086 RTCircBufReset(pStreamCC->State.pCircBuf);
1087
1088 PAC97BMREGS pRegs = &pStream->Regs;
1089
1090 pRegs->bdbar = 0;
1091 pRegs->civ = 0;
1092 pRegs->lvi = 0;
1093
1094 pRegs->picb = 0;
1095 pRegs->piv = 0; /* Note! Because this is also zero, we will actually start transferring with BDLE00. */
1096 pRegs->cr = pRegs->cr & AC97_CR_DONT_CLEAR_MASK;
1097 pRegs->bd_valid = 0;
1098
1099 RT_ZERO(pThis->silence);
1100
1101 ichac97R3StreamUnlock(pStreamCC);
1102}
1103
1104/**
1105 * Creates an AC'97 audio stream.
1106 *
1107 * @returns VBox status code.
1108 * @param pThisCC The ring-3 AC'97 state.
1109 * @param pStream The AC'97 stream to create (shared).
1110 * @param pStreamCC The AC'97 stream to create (ring-3).
1111 * @param u8SD Stream descriptor number to assign.
1112 */
1113static int ichac97R3StreamCreate(PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint8_t u8SD)
1114{
1115 LogFunc(("[SD%RU8] pStream=%p\n", u8SD, pStream));
1116
1117 AssertReturn(u8SD < AC97_MAX_STREAMS, VERR_INVALID_PARAMETER);
1118 pStream->u8SD = u8SD;
1119 pStreamCC->u8SD = u8SD;
1120
1121 int rc = RTCritSectInit(&pStreamCC->State.CritSect);
1122 AssertRCReturn(rc, rc);
1123
1124 pStreamCC->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
1125
1126 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1127 { /* likely */ }
1128 else
1129 {
1130 char szFile[64];
1131
1132 if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1133 RTStrPrintf(szFile, sizeof(szFile), "ac97StreamWriteSD%RU8", pStream->u8SD);
1134 else
1135 RTStrPrintf(szFile, sizeof(szFile), "ac97StreamReadSD%RU8", pStream->u8SD);
1136
1137 char szPath[RTPATH_MAX];
1138 int rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1139 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
1140 AssertRC(rc2);
1141 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileStream);
1142 AssertRC(rc2);
1143
1144 if (ichac97GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
1145 RTStrPrintf(szFile, sizeof(szFile), "ac97DMAWriteSD%RU8", pStream->u8SD);
1146 else
1147 RTStrPrintf(szFile, sizeof(szFile), "ac97DMAReadSD%RU8", pStream->u8SD);
1148
1149 rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
1150 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
1151 AssertRC(rc2);
1152
1153 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamCC->Dbg.Runtime.pFileDMA);
1154 AssertRC(rc2);
1155
1156 /* Delete stale debugging files from a former run. */
1157 AudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileStream);
1158 AudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileDMA);
1159 }
1160
1161 return rc;
1162}
1163
1164/**
1165 * Destroys an AC'97 audio stream.
1166 *
1167 * @returns VBox status code.
1168 * @param pThisCC The ring-3 AC'97 state.
1169 * @param pStream The AC'97 stream to destroy (shared).
1170 * @param pStreamCC The AC'97 stream to destroy (ring-3).
1171 */
1172static void ichac97R3StreamDestroy(PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1173{
1174 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
1175
1176 ichac97R3StreamClose(pStream);
1177
1178 int rc2 = RTCritSectDelete(&pStreamCC->State.CritSect);
1179 AssertRC(rc2);
1180
1181 if (pStreamCC->State.fRegisteredAsyncUpdateJob)
1182 {
1183 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
1184 if (pSink)
1185 AudioMixerSinkRemoveUpdateJob(pSink, ichac97R3StreamUpdateAsyncIoJob, pStreamCC);
1186 pStreamCC->State.fRegisteredAsyncUpdateJob = false;
1187 }
1188
1189 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
1190 { /* likely */ }
1191 else
1192 {
1193 AudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileStream);
1194 pStreamCC->Dbg.Runtime.pFileStream = NULL;
1195
1196 AudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileDMA);
1197 pStreamCC->Dbg.Runtime.pFileDMA = NULL;
1198 }
1199
1200 if (pStreamCC->State.pCircBuf)
1201 {
1202 RTCircBufDestroy(pStreamCC->State.pCircBuf);
1203 pStreamCC->State.pCircBuf = NULL;
1204 }
1205
1206 LogFlowFuncLeave();
1207}
1208
1209/**
1210 * Destroys all AC'97 audio streams of the device.
1211 *
1212 * @param pDevIns The device AC'97 instance.
1213 * @param pThis The shared AC'97 state.
1214 * @param pThisCC The ring-3 AC'97 state.
1215 */
1216static void ichac97R3StreamsDestroy(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC)
1217{
1218 LogFlowFuncEnter();
1219
1220 /*
1221 * Destroy all AC'97 streams.
1222 */
1223 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
1224 ichac97R3StreamDestroy(pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i]);
1225
1226 /*
1227 * Destroy all sinks.
1228 */
1229 if (pThisCC->pSinkLineIn)
1230 {
1231 ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkLineIn, PDMAUDIODIR_IN, PDMAUDIOPATH_IN_LINE);
1232
1233 AudioMixerSinkDestroy(pThisCC->pSinkLineIn, pDevIns);
1234 pThisCC->pSinkLineIn = NULL;
1235 }
1236
1237 if (pThisCC->pSinkMicIn)
1238 {
1239 ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkMicIn, PDMAUDIODIR_IN, PDMAUDIOPATH_IN_MIC);
1240
1241 AudioMixerSinkDestroy(pThisCC->pSinkMicIn, pDevIns);
1242 pThisCC->pSinkMicIn = NULL;
1243 }
1244
1245 if (pThisCC->pSinkOut)
1246 {
1247 ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkOut, PDMAUDIODIR_OUT, PDMAUDIOPATH_OUT_FRONT);
1248
1249 AudioMixerSinkDestroy(pThisCC->pSinkOut, pDevIns);
1250 pThisCC->pSinkOut = NULL;
1251 }
1252}
1253
1254
1255/**
1256 * Input streams: Pulls data from the mixer, putting it in the internal DMA
1257 * buffer.
1258 *
1259 * @param pStreamR3 The AC'97 stream (ring-3 bits).
1260 * @param pSink The mixer sink to pull from.
1261 */
1262static void ichac97R3StreamPullFromMixer(PAC97STREAMR3 pStreamR3, PAUDMIXSINK pSink)
1263{
1264#ifdef LOG_ENABLED
1265 uint64_t const offWriteOld = pStreamR3->State.offWrite;
1266#endif
1267 pStreamR3->State.offWrite = AudioMixerSinkTransferToCircBuf(pSink,
1268 pStreamR3->State.pCircBuf,
1269 pStreamR3->State.offWrite,
1270 pStreamR3->u8SD,
1271 pStreamR3->Dbg.Runtime.fEnabled
1272 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1273
1274 Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1275 pStreamR3->State.offWrite - offWriteOld, pStreamR3->State.offWrite));
1276
1277 /* Update buffer stats. */
1278 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1279}
1280
1281
1282/**
1283 * Output streams: Pushes data to the mixer.
1284 *
1285 * @param pStreamR3 The AC'97 stream (ring-3 bits).
1286 * @param pSink The mixer sink to push to.
1287 */
1288static void ichac97R3StreamPushToMixer(PAC97STREAMR3 pStreamR3, PAUDMIXSINK pSink)
1289{
1290#ifdef LOG_ENABLED
1291 uint64_t const offReadOld = pStreamR3->State.offRead;
1292#endif
1293 pStreamR3->State.offRead = AudioMixerSinkTransferFromCircBuf(pSink,
1294 pStreamR3->State.pCircBuf,
1295 pStreamR3->State.offRead,
1296 pStreamR3->u8SD,
1297 pStreamR3->Dbg.Runtime.fEnabled
1298 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1299
1300 Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1301 pStreamR3->State.offRead - offReadOld, pStreamR3->State.offRead));
1302
1303 /* Update buffer stats. */
1304 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1305}
1306
1307
1308/**
1309 * Updates an AC'97 stream by doing its DMA transfers.
1310 *
1311 * The host sink(s) set the overall pace (bird: no it doesn't, the DMA timer
1312 * does - we just hope like heck it matches the speed at which the *backend*
1313 * host audio driver processes samples).
1314 *
1315 * @param pDevIns The device instance.
1316 * @param pThis The shared AC'97 state.
1317 * @param pThisCC The ring-3 AC'97 state.
1318 * @param pStream The AC'97 stream to update (shared).
1319 * @param pStreamCC The AC'97 stream to update (ring-3).
1320 */
1321static void ichac97R3StreamUpdateDma(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
1322 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, PAUDMIXSINK pSink)
1323{
1324 RT_NOREF(pThisCC);
1325 int rc2;
1326
1327 /*
1328 * Output streams (SDO).
1329 */
1330 if (pStreamCC->State.Cfg.enmDir == PDMAUDIODIR_OUT)
1331 {
1332 uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1333 if (cbStreamFree)
1334 { /* likely */ }
1335 else
1336 {
1337 /** @todo Record this as a statistic. Try make some space available. */
1338 }
1339 if (cbStreamFree)
1340 {
1341 Log3Func(("[SD%RU8] PICB=%zu (%RU64ms), cbFree=%zu (%RU64ms), cbTransferChunk=%zu (%RU64ms)\n",
1342 pStream->u8SD,
1343 (pStream->Regs.picb << 1), PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, pStream->Regs.picb << 1),
1344 cbStreamFree, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, cbStreamFree),
1345 pStreamCC->State.cbTransferChunk, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, pStreamCC->State.cbTransferChunk)));
1346
1347 /* Do the DMA transfer. */
1348 rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC,
1349 RT_MIN(pStreamCC->State.cbTransferChunk, cbStreamFree));
1350 AssertRC(rc2);
1351
1352 pStreamCC->State.tsLastUpdateNs = RTTimeNanoTS();
1353 }
1354
1355 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
1356 AssertRC(rc2);
1357 }
1358 else /* Input (SDI). */
1359 {
1360#if 0 /* bird: I just love when crusial code like this with no explanation. This just causing AIO
1361 * skipping a DMA timer cycle if the timer callback is a bit quicker than the 'hint' (see HDA/9890). */
1362 const uint64_t tsNowNs = RTTimeNanoTS();
1363 if (tsNowNs - pStreamCC->State.tsLastUpdateNs >= pStreamCC->State.Cfg.Device.cMsSchedulingHint * RT_NS_1MS)
1364 {
1365 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
1366 AssertRC(rc2);
1367
1368 pStreamCC->State.tsLastUpdateNs = tsNowNs;
1369 }
1370#endif
1371
1372 uint32_t cbStreamUsed = ichac97R3StreamGetUsed(pStreamCC);
1373 if (cbStreamUsed)
1374 { /* likey */ }
1375 else
1376 {
1377 /** @todo Record this as a statistic. Try pull some data into the DMA buffer.*/
1378 }
1379
1380 if (cbStreamUsed)
1381 {
1382 /* When running synchronously, do the DMA data transfers here.
1383 * Otherwise this will be done in the stream's async I/O thread. */
1384 rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC, cbStreamUsed);
1385 AssertRC(rc2);
1386 }
1387
1388 /*
1389 * We should always kick the AIO thread.
1390 */
1391 /** @todo This isn't entirely ideal. If we get into an underrun situation,
1392 * we ideally want the AIO thread to run right before the DMA timer
1393 * rather than right after it ran. */
1394 Log5Func(("Notifying AIO thread\n"));
1395 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
1396 AssertRC(rc2);
1397 pStreamCC->State.tsLastUpdateNs = RTTimeNanoTS();
1398 }
1399}
1400
1401
1402/**
1403 * @callback_method_impl{FNAUDMIXSINKUPDATE}
1404 *
1405 * For output streams this moves data from the internal DMA buffer (in which
1406 * ichac97R3StreamUpdateDma put it), thru the mixer and to the various backend
1407 * audio devices.
1408 *
1409 * For input streams this pulls data from the backend audio device(s), thru the
1410 * mixer and puts it in the internal DMA buffer ready for
1411 * ichac97R3StreamUpdateDma to pump into guest memory.
1412 */
1413static DECLCALLBACK(void) ichac97R3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser)
1414{
1415 PAC97STATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
1416 PAC97STREAMR3 const pStreamCC = (PAC97STREAMR3)pvUser;
1417 Assert(pStreamCC->u8SD == (uintptr_t)(pStreamCC - &pThisCC->aStreams[0]));
1418 Assert(pSink == ichac97R3IndexToSink(pThisCC, pStreamCC->u8SD));
1419 RT_NOREF(pThisCC);
1420
1421 /*
1422 * Output (SDO).
1423 */
1424 if (pStreamCC->State.Cfg.enmDir == PDMAUDIODIR_OUT)
1425 ichac97R3StreamPushToMixer(pStreamCC, pSink);
1426 /*
1427 * Input (SDI).
1428 */
1429 else
1430 ichac97R3StreamPullFromMixer(pStreamCC, pSink);
1431}
1432
1433#endif /* IN_RING3 */
1434
1435/**
1436 * Sets a AC'97 mixer control to a specific value.
1437 *
1438 * @returns VBox status code.
1439 * @param pThis The shared AC'97 state.
1440 * @param uMixerIdx Mixer control to set value for.
1441 * @param uVal Value to set.
1442 */
1443static void ichac97MixerSet(PAC97STATE pThis, uint8_t uMixerIdx, uint16_t uVal)
1444{
1445 AssertMsgReturnVoid(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1446 ("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)));
1447
1448 LogRel2(("AC97: Setting mixer index #%RU8 to %RU16 (%RU8 %RU8)\n",
1449 uMixerIdx, uVal, RT_HI_U8(uVal), RT_LO_U8(uVal)));
1450
1451 pThis->mixer_data[uMixerIdx + 0] = RT_LO_U8(uVal);
1452 pThis->mixer_data[uMixerIdx + 1] = RT_HI_U8(uVal);
1453}
1454
1455/**
1456 * Gets a value from a specific AC'97 mixer control.
1457 *
1458 * @returns Retrieved mixer control value.
1459 * @param pThis The shared AC'97 state.
1460 * @param uMixerIdx Mixer control to get value for.
1461 */
1462static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t uMixerIdx)
1463{
1464 AssertMsgReturn(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
1465 ("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)),
1466 UINT16_MAX);
1467 return RT_MAKE_U16(pThis->mixer_data[uMixerIdx + 0], pThis->mixer_data[uMixerIdx + 1]);
1468}
1469
1470#ifdef IN_RING3
1471
1472/**
1473 * Retrieves a specific driver stream of a AC'97 driver.
1474 *
1475 * @returns Pointer to driver stream if found, or NULL if not found.
1476 * @param pDrv Driver to retrieve driver stream for.
1477 * @param enmDir Stream direction to retrieve.
1478 * @param enmPath Stream destination / source to retrieve.
1479 */
1480static PAC97DRIVERSTREAM ichac97R3MixerGetDrvStream(PAC97DRIVER pDrv, PDMAUDIODIR enmDir, PDMAUDIOPATH enmPath)
1481{
1482 PAC97DRIVERSTREAM pDrvStream = NULL;
1483
1484 if (enmDir == PDMAUDIODIR_IN)
1485 {
1486 LogFunc(("enmRecSource=%d\n", enmPath));
1487
1488 switch (enmPath)
1489 {
1490 case PDMAUDIOPATH_IN_LINE:
1491 pDrvStream = &pDrv->LineIn;
1492 break;
1493 case PDMAUDIOPATH_IN_MIC:
1494 pDrvStream = &pDrv->MicIn;
1495 break;
1496 default:
1497 AssertFailed();
1498 break;
1499 }
1500 }
1501 else if (enmDir == PDMAUDIODIR_OUT)
1502 {
1503 LogFunc(("enmPlaybackDst=%d\n", enmPath));
1504
1505 switch (enmPath)
1506 {
1507 case PDMAUDIOPATH_OUT_FRONT:
1508 pDrvStream = &pDrv->Out;
1509 break;
1510 default:
1511 AssertFailed();
1512 break;
1513 }
1514 }
1515 else
1516 AssertFailed();
1517
1518 return pDrvStream;
1519}
1520
1521/**
1522 * Adds a driver stream to a specific mixer sink.
1523 *
1524 * @returns VBox status code.
1525 * @param pDevIns The device instance.
1526 * @param pMixSink Mixer sink to add driver stream to.
1527 * @param pCfg Stream configuration to use.
1528 * @param pDrv Driver stream to add.
1529 */
1530static int ichac97R3MixerAddDrvStream(PPDMDEVINS pDevIns, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PAC97DRIVER pDrv)
1531{
1532 AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1533
1534 PPDMAUDIOSTREAMCFG pStreamCfg = PDMAudioStrmCfgDup(pCfg);
1535 if (!pStreamCfg)
1536 return VERR_NO_MEMORY;
1537
1538 AssertCompile(sizeof(pStreamCfg->szName) == sizeof(pCfg->szName));
1539 RTStrCopy(pStreamCfg->szName, sizeof(pStreamCfg->szName), pCfg->szName);
1540
1541 LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
1542
1543 int rc;
1544
1545 PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, pStreamCfg->enmDir, pStreamCfg->enmPath);
1546 if (pDrvStream)
1547 {
1548 AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
1549
1550 PAUDMIXSTREAM pMixStrm;
1551 rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, pDevIns, &pMixStrm);
1552 LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1553 if (RT_SUCCESS(rc))
1554 {
1555 rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
1556 LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
1557 if (RT_FAILURE(rc))
1558 AudioMixerStreamDestroy(pMixStrm, pDevIns, true /*fImmediate*/);
1559 }
1560
1561 if (RT_SUCCESS(rc))
1562 pDrvStream->pMixStrm = pMixStrm;
1563 }
1564 else
1565 rc = VERR_INVALID_PARAMETER;
1566
1567 PDMAudioStrmCfgFree(pStreamCfg);
1568
1569 LogFlowFuncLeaveRC(rc);
1570 return rc;
1571}
1572
1573/**
1574 * Adds all current driver streams to a specific mixer sink.
1575 *
1576 * @returns VBox status code.
1577 * @param pDevIns The device instance.
1578 * @param pThisCC The ring-3 AC'97 state.
1579 * @param pMixSink Mixer sink to add stream to.
1580 * @param pCfg Stream configuration to use.
1581 */
1582static int ichac97R3MixerAddDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
1583{
1584 AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1585
1586 if (!AudioHlpStreamCfgIsValid(pCfg))
1587 return VERR_INVALID_PARAMETER;
1588
1589 int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
1590 if (RT_FAILURE(rc))
1591 return rc;
1592
1593 PAC97DRIVER pDrv;
1594 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
1595 {
1596 int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pMixSink, pCfg, pDrv);
1597 if (RT_FAILURE(rc2))
1598 LogFunc(("Attaching stream failed with %Rrc\n", rc2));
1599
1600 /* Do not pass failure to rc here, as there might be drivers which aren't
1601 * configured / ready yet. */
1602 }
1603
1604 LogFlowFuncLeaveRC(rc);
1605 return rc;
1606}
1607
1608/**
1609 * Adds a specific AC'97 driver to the driver chain.
1610 *
1611 * @returns VBox status code.
1612 * @param pDevIns The device instance.
1613 * @param pThisCC The ring-3 AC'97 device state.
1614 * @param pDrv The AC'97 driver to add.
1615 */
1616static int ichac97R3MixerAddDrv(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
1617{
1618 int rc = VINF_SUCCESS;
1619
1620 if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg))
1621 rc = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkLineIn,
1622 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg, pDrv);
1623
1624 if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg))
1625 {
1626 int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkOut,
1627 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg, pDrv);
1628 if (RT_SUCCESS(rc))
1629 rc = rc2;
1630 }
1631
1632 if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg))
1633 {
1634 int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkMicIn,
1635 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg, pDrv);
1636 if (RT_SUCCESS(rc))
1637 rc = rc2;
1638 }
1639
1640 return rc;
1641}
1642
1643/**
1644 * Removes a specific AC'97 driver from the driver chain and destroys its
1645 * associated streams.
1646 *
1647 * @param pDevIns The device instance.
1648 * @param pThisCC The ring-3 AC'97 device state.
1649 * @param pDrv AC'97 driver to remove.
1650 */
1651static void ichac97R3MixerRemoveDrv(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
1652{
1653 if (pDrv->MicIn.pMixStrm)
1654 {
1655 AudioMixerSinkRemoveStream(pThisCC->pSinkMicIn, pDrv->MicIn.pMixStrm);
1656 AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm, pDevIns, true /*fImmediate*/);
1657 pDrv->MicIn.pMixStrm = NULL;
1658 }
1659
1660 if (pDrv->LineIn.pMixStrm)
1661 {
1662 AudioMixerSinkRemoveStream(pThisCC->pSinkLineIn, pDrv->LineIn.pMixStrm);
1663 AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm, pDevIns, true /*fImmediate*/);
1664 pDrv->LineIn.pMixStrm = NULL;
1665 }
1666
1667 if (pDrv->Out.pMixStrm)
1668 {
1669 AudioMixerSinkRemoveStream(pThisCC->pSinkOut, pDrv->Out.pMixStrm);
1670 AudioMixerStreamDestroy(pDrv->Out.pMixStrm, pDevIns, true /*fImmediate*/);
1671 pDrv->Out.pMixStrm = NULL;
1672 }
1673
1674 RTListNodeRemove(&pDrv->Node);
1675}
1676
1677/**
1678 * Removes a driver stream from a specific mixer sink.
1679 *
1680 * @param pDevIns The device instance.
1681 * @param pMixSink Mixer sink to remove audio streams from.
1682 * @param enmDir Stream direction to remove.
1683 * @param enmPath Stream destination / source to remove.
1684 * @param pDrv Driver stream to remove.
1685 */
1686static void ichac97R3MixerRemoveDrvStream(PPDMDEVINS pDevIns, PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir,
1687 PDMAUDIOPATH enmPath, PAC97DRIVER pDrv)
1688{
1689 PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, enmDir, enmPath);
1690 if (pDrvStream)
1691 {
1692 if (pDrvStream->pMixStrm)
1693 {
1694 AudioMixerSinkRemoveStream(pMixSink, pDrvStream->pMixStrm);
1695
1696 AudioMixerStreamDestroy(pDrvStream->pMixStrm, pDevIns, false /*fImmediate*/);
1697 pDrvStream->pMixStrm = NULL;
1698 }
1699 }
1700}
1701
1702/**
1703 * Removes all driver streams from a specific mixer sink.
1704 *
1705 * @param pDevIns The device instance.
1706 * @param pThisCC The ring-3 AC'97 state.
1707 * @param pMixSink Mixer sink to remove audio streams from.
1708 * @param enmDir Stream direction to remove.
1709 * @param enmPath Stream destination / source to remove.
1710 */
1711static void ichac97R3MixerRemoveDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
1712 PDMAUDIODIR enmDir, PDMAUDIOPATH enmPath)
1713{
1714 AssertPtrReturnVoid(pMixSink);
1715
1716 PAC97DRIVER pDrv;
1717 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
1718 {
1719 ichac97R3MixerRemoveDrvStream(pDevIns, pMixSink, enmDir, enmPath, pDrv);
1720 }
1721}
1722
1723
1724/**
1725 * Updates the next transfer based on a specific amount of bytes.
1726 *
1727 * @param pDevIns The device instance.
1728 * @param pStream The AC'97 stream to update (shared).
1729 * @param pStreamCC The AC'97 stream to update (ring-3).
1730 */
1731static void ichac97R3StreamTransferUpdate(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1732{
1733 /*
1734 * Get the number of bytes left in the current buffer.
1735 *
1736 * This isn't entirely optimal iff the current entry doesn't have IOC set, in
1737 * that case we should use the number of bytes to the next IOC. Unfortuantely,
1738 * it seems the spec doesn't allow us to prefetch more than one BDLE, so we
1739 * probably cannot look ahead without violating that restriction. This is
1740 * probably a purely theoretical problem at this point.
1741 */
1742 uint32_t const cbLeftInBdle = pStream->Regs.picb * PDMAudioPropsSampleSize(&pStreamCC->State.Cfg.Props);
1743 if (cbLeftInBdle > 0) /** @todo r=bird: see todo about this in ichac97R3StreamFetchBDLE. */
1744 {
1745 /*
1746 * Since the buffer can be up to 0xfffe samples long (frame aligning stereo
1747 * prevents 0xffff), which translates to 743ms at a 44.1kHz rate, we must
1748 * also take the nominal timer frequency into account here so we keep
1749 * moving data at a steady rate. (In theory, I think the guest can even
1750 * set up just one buffer and anticipate where we are in the buffer
1751 * processing when it writes/reads from it. Linux seems to be doing such
1752 * configs when not playing or something.)
1753 */
1754 uint32_t const cbMaxPerHz = PDMAudioPropsNanoToBytes(&pStreamCC->State.Cfg.Props, RT_NS_1SEC / pStreamCC->State.uTimerHz);
1755
1756 if (cbLeftInBdle <= cbMaxPerHz)
1757 pStreamCC->State.cbTransferChunk = cbLeftInBdle;
1758 /* Try avoid leaving a very short period at the end of a buffer. */
1759 else if (cbLeftInBdle >= cbMaxPerHz + cbMaxPerHz / 2)
1760 pStreamCC->State.cbTransferChunk = cbMaxPerHz;
1761 else
1762 pStreamCC->State.cbTransferChunk = PDMAudioPropsFloorBytesToFrame(&pStreamCC->State.Cfg.Props, cbLeftInBdle / 2);
1763
1764 /*
1765 * Translate the chunk size to timer ticks.
1766 */
1767 uint64_t const cNsXferChunk = PDMAudioPropsBytesToNano(&pStreamCC->State.Cfg.Props, pStreamCC->State.cbTransferChunk);
1768 pStreamCC->State.cTransferTicks = PDMDevHlpTimerFromNano(pDevIns, pStream->hTimer, cNsXferChunk);
1769 Assert(pStreamCC->State.cTransferTicks > 0);
1770
1771 Log3Func(("[SD%RU8] cbLeftInBdle=%#RX32 cbMaxPerHz=%#RX32 (%RU16Hz) -> cbTransferChunk=%#RX32 cTransferTicks=%RX64\n",
1772 pStream->u8SD, cbLeftInBdle, cbMaxPerHz, pStreamCC->State.uTimerHz,
1773 pStreamCC->State.cbTransferChunk, pStreamCC->State.cTransferTicks));
1774 }
1775}
1776
1777
1778/**
1779 * Gets the frequency of a given stream.
1780 *
1781 * @returns The frequency. Zero if invalid stream index.
1782 * @param pThis The shared AC'97 device state.
1783 * @param idxStream The stream.
1784 */
1785DECLINLINE(uint32_t) ichach97R3CalcStreamHz(PAC97STATE pThis, uint8_t idxStream)
1786{
1787 switch (idxStream)
1788 {
1789 case AC97SOUNDSOURCE_PI_INDEX:
1790 return ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate);
1791
1792 case AC97SOUNDSOURCE_MC_INDEX:
1793 return ichac97MixerGet(pThis, AC97_MIC_ADC_Rate);
1794
1795 case AC97SOUNDSOURCE_PO_INDEX:
1796 return ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate);
1797
1798 default:
1799 AssertMsgFailedReturn(("%d\n", idxStream), 0);
1800 }
1801}
1802
1803
1804/**
1805 * Gets the PCM properties for a given stream.
1806 *
1807 * @returns pProps.
1808 * @param pThis The shared AC'97 device state.
1809 * @param idxStream Which stream
1810 * @param pProps Where to return the stream properties.
1811 */
1812DECLINLINE(PPDMAUDIOPCMPROPS) ichach97R3CalcStreamProps(PAC97STATE pThis, uint8_t idxStream, PPDMAUDIOPCMPROPS pProps)
1813{
1814 PDMAudioPropsInit(pProps, 2 /*16-bit*/, true /*signed*/, 2 /*stereo*/, ichach97R3CalcStreamHz(pThis, idxStream));
1815 return pProps;
1816}
1817
1818
1819/**
1820 * Opens an AC'97 stream with its current mixer settings.
1821 *
1822 * This will open an AC'97 stream with 2 (stereo) channels, 16-bit samples and
1823 * the last set sample rate in the AC'97 mixer for this stream.
1824 *
1825 * @returns VBox status code.
1826 * @param pDevIns The device instance.
1827 * @param pThis The shared AC'97 device state (shared).
1828 * @param pThisCC The shared AC'97 device state (ring-3).
1829 * @param pStream The AC'97 stream to open (shared).
1830 * @param pStreamCC The AC'97 stream to open (ring-3).
1831 * @param fForce Whether to force re-opening the stream or not.
1832 * Otherwise re-opening only will happen if the PCM properties have changed.
1833 */
1834static int ichac97R3StreamOpen(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
1835 PAC97STREAMR3 pStreamCC, bool fForce)
1836{
1837 /*
1838 * Assemble the stream config and get the associate mixer sink.
1839 */
1840 PDMAUDIOPCMPROPS PropsTmp;
1841 PDMAUDIOSTREAMCFG Cfg;
1842 PDMAudioStrmCfgInitWithProps(&Cfg, ichach97R3CalcStreamProps(pThis, pStream->u8SD, &PropsTmp));
1843
1844 PAUDMIXSINK pMixSink;
1845 switch (pStream->u8SD)
1846 {
1847 case AC97SOUNDSOURCE_PI_INDEX:
1848 Cfg.enmDir = PDMAUDIODIR_IN;
1849 Cfg.enmPath = PDMAUDIOPATH_IN_LINE;
1850 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Line-In");
1851
1852 pMixSink = pThisCC->pSinkLineIn;
1853 break;
1854
1855 case AC97SOUNDSOURCE_MC_INDEX:
1856 Cfg.enmDir = PDMAUDIODIR_IN;
1857 Cfg.enmPath = PDMAUDIOPATH_IN_MIC;
1858 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Mic-In");
1859
1860 pMixSink = pThisCC->pSinkMicIn;
1861 break;
1862
1863 case AC97SOUNDSOURCE_PO_INDEX:
1864 Cfg.enmDir = PDMAUDIODIR_OUT;
1865 Cfg.enmPath = PDMAUDIOPATH_OUT_FRONT;
1866 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Output");
1867
1868 pMixSink = pThisCC->pSinkOut;
1869 break;
1870
1871 default:
1872 AssertMsgFailedReturn(("u8SD=%d\n", pStream->u8SD), VERR_INTERNAL_ERROR_3);
1873 }
1874
1875 /*
1876 * Read the buffer descriptors and check what the max distance between
1877 * interrupts are, so we can more correctly size the internal DMA buffer.
1878 *
1879 * Note! The buffer list are not fixed once the stream starts running as
1880 * with HDA, so this is just a general idea of what the guest is
1881 * up to and we cannot really make much of a plan out of it.
1882 */
1883 AC97BDLE aBdl[AC97_MAX_BDLE];
1884 RT_ZERO(aBdl);
1885 PDMDevHlpPCIPhysRead(pDevIns, pStream->Regs.bdbar, aBdl, sizeof(aBdl));
1886
1887 uint8_t const bLvi = pStream->Regs.lvi % AC97_MAX_BDLE /* paranoia */;
1888 uint8_t const bCiv = pStream->Regs.civ % AC97_MAX_BDLE /* paranoia */;
1889 uint32_t cSamplesMax = 0;
1890 uint32_t cSamplesMin = UINT32_MAX;
1891 uint32_t cSamplesCur = 0;
1892 uint32_t cSamplesTotal = 0;
1893 uint32_t cBuffers = 1;
1894 for (uintptr_t i = bCiv; ; cBuffers++)
1895 {
1896 cSamplesTotal += aBdl[i].ctl_len & AC97_BD_LEN_MASK;
1897 cSamplesCur += aBdl[i].ctl_len & AC97_BD_LEN_MASK;
1898 if (aBdl[i].ctl_len & AC97_BD_IOC)
1899 {
1900 if (cSamplesCur > cSamplesMax)
1901 cSamplesMax = cSamplesCur;
1902 if (cSamplesCur < cSamplesMin)
1903 cSamplesMin = cSamplesCur;
1904 cSamplesCur = 0;
1905 }
1906
1907 /* Advance. */
1908 if (i != bLvi)
1909 i = (i + 1) % RT_ELEMENTS(aBdl);
1910 else
1911 break;
1912 }
1913 if (!cSamplesCur)
1914 { /* likely */ }
1915 else if (!cSamplesMax)
1916 {
1917 LogFlowFunc(("%u buffers without IOC set, assuming %#x samples as the IOC period.\n", cBuffers, cSamplesMax));
1918 cSamplesMin = cSamplesMax = cSamplesCur;
1919 }
1920 else if (cSamplesCur > cSamplesMax)
1921 {
1922 LogFlowFunc(("final buffer is without IOC, using open period as max (%#x vs current max %#x).\n", cSamplesCur, cSamplesMax));
1923 cSamplesMax = cSamplesCur;
1924 }
1925 else
1926 LogFlowFunc(("final buffer is without IOC, ignoring (%#x vs current max %#x).\n", cSamplesCur, cSamplesMax));
1927
1928 uint32_t const cbDmaMinBuf = cSamplesMax * PDMAudioPropsSampleSize(&Cfg.Props) * 3; /* see further down */
1929 uint32_t const cMsDmaMinBuf = PDMAudioPropsBytesToMilli(&Cfg.Props, cbDmaMinBuf);
1930 LogRel3(("AC97: [SD%RU8] buffer length stats: total=%#x in %u buffers, min=%#x, max=%#x => min DMA buffer %u ms / %#x bytes\n",
1931 pStream->u8SD, cSamplesTotal, cBuffers, cSamplesMin, cSamplesMax, cMsDmaMinBuf, cbDmaMinBuf));
1932
1933 /*
1934 * Only (re-)create the stream (and driver chain) if we really have to.
1935 * Otherwise avoid this and just reuse it, as this costs performance.
1936 */
1937 int rc = VINF_SUCCESS;
1938 if ( fForce
1939 || !PDMAudioStrmCfgMatchesProps(&Cfg, &pStreamCC->State.Cfg.Props)
1940 || !pStreamCC->State.pCircBuf
1941 || cbDmaMinBuf > RTCircBufSize(pStreamCC->State.pCircBuf))
1942 {
1943 LogRel2(("AC97: (Re-)Opening stream '%s' (%RU32Hz, %RU8 channels, %s%RU8)\n", Cfg.szName, Cfg.Props.uHz,
1944 PDMAudioPropsChannels(&Cfg.Props), Cfg.Props.fSigned ? "S" : "U", PDMAudioPropsSampleBits(&Cfg.Props)));
1945
1946 LogFlowFunc(("[SD%RU8] uHz=%RU32\n", pStream->u8SD, Cfg.Props.uHz));
1947
1948 if (Cfg.Props.uHz)
1949 {
1950 Assert(Cfg.enmDir != PDMAUDIODIR_UNKNOWN);
1951
1952 /*
1953 * Set the stream's timer Hz rate, based on the PCM properties Hz rate.
1954 */
1955 if (pThis->uTimerHz == AC97_TIMER_HZ_DEFAULT) /* Make sure that we don't have any custom Hz rate set we want to enforce */
1956 {
1957 if (Cfg.Props.uHz > 44100) /* E.g. 48000 Hz. */
1958 pStreamCC->State.uTimerHz = 200;
1959 else /* Just take the global Hz rate otherwise. */
1960 pStreamCC->State.uTimerHz = pThis->uTimerHz;
1961 }
1962 else
1963 pStreamCC->State.uTimerHz = pThis->uTimerHz;
1964
1965 if ( pStreamCC->State.uTimerHz >= 10
1966 && pStreamCC->State.uTimerHz <= 500)
1967 { /* likely */ }
1968 else
1969 {
1970 LogFunc(("[SD%RU8] Adjusting uTimerHz=%u to %u\n", pStream->u8SD, pStreamCC->State.uTimerHz,
1971 Cfg.Props.uHz > 44100 ? 200 : AC97_TIMER_HZ_DEFAULT));
1972 pStreamCC->State.uTimerHz = Cfg.Props.uHz > 44100 ? 200 : AC97_TIMER_HZ_DEFAULT;
1973 }
1974
1975 /* Set scheduling hint. */
1976 Cfg.Device.cMsSchedulingHint = RT_MS_1SEC / pStreamCC->State.uTimerHz;
1977
1978 /*
1979 * Re-create the circular buffer if necessary.
1980 *
1981 * As mentioned in the HDA code, this should be at least able to hold the
1982 * data transferred in three DMA periods and in three AIO period (whichever
1983 * is higher). However, if we assume that the DMA code will engage the DMA
1984 * timer thread (currently EMT) if the AIO thread isn't getting schduled to
1985 * transfer data thru the stack, we don't need to go overboard and double
1986 * the minimums here. The less buffer the less possible delay can build when
1987 * TM is doing catch up.
1988 */
1989 uint32_t cMsCircBuf = Cfg.enmDir == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut;
1990 cMsCircBuf = RT_MAX(cMsCircBuf, cMsDmaMinBuf);
1991 cMsCircBuf = RT_MAX(cMsCircBuf, Cfg.Device.cMsSchedulingHint * 3);
1992 cMsCircBuf = RT_MIN(cMsCircBuf, RT_MS_1SEC * 2); /** @todo make sure the DMA timer doesn't go over 500ms (use uTimerHz as max, really). */
1993 uint32_t const cbCircBuf = PDMAudioPropsMilliToBytes(&Cfg.Props, cMsCircBuf);
1994
1995 if (pStreamCC->State.pCircBuf && RTCircBufSize(pStreamCC->State.pCircBuf) == cbCircBuf)
1996 RTCircBufReset(pStreamCC->State.pCircBuf);
1997 else
1998 {
1999 LogFlowFunc(("Re-creating circular buffer with size %u ms / %#x bytes (was %#x); cMsSchedulingHint=%u cMsDmaMinBuf=%u cMsCircBufXxx=%u\n",
2000 cMsCircBuf, cbCircBuf, pStreamCC->State.StatDmaBufSize, Cfg.Device.cMsSchedulingHint, cMsDmaMinBuf,
2001 Cfg.enmDir == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut));
2002 if (pStreamCC->State.pCircBuf)
2003 RTCircBufDestroy(pStreamCC->State.pCircBuf);
2004
2005 rc = RTCircBufCreate(&pStreamCC->State.pCircBuf, cbCircBuf);
2006 AssertRCReturnStmt(rc, pStreamCC->State.pCircBuf = NULL, rc);
2007
2008 pStreamCC->State.StatDmaBufSize = (uint32_t)RTCircBufSize(pStreamCC->State.pCircBuf);
2009 }
2010 Assert(pStreamCC->State.StatDmaBufSize == cbCircBuf);
2011
2012 /*
2013 * <there should be a comment here>
2014 */
2015 ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pMixSink, Cfg.enmDir, Cfg.enmPath);
2016 rc = ichac97R3MixerAddDrvStreams(pDevIns, pThisCC, pMixSink, &Cfg);
2017 if (RT_SUCCESS(rc))
2018 rc = PDMAudioStrmCfgCopy(&pStreamCC->State.Cfg, &Cfg);
2019 }
2020 LogFlowFunc(("[SD%RU8] rc=%Rrc\n", pStream->u8SD, rc));
2021 }
2022 else
2023 LogFlowFunc(("[SD%RU8] Skipping (re-)creation\n", pStream->u8SD));
2024 return rc;
2025}
2026
2027/**
2028 * Closes an AC'97 stream.
2029 *
2030 * @returns VBox status code.
2031 * @param pStream The AC'97 stream to close (shared).
2032 */
2033static int ichac97R3StreamClose(PAC97STREAM pStream)
2034{
2035 RT_NOREF(pStream);
2036 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2037 return VINF_SUCCESS;
2038}
2039
2040/**
2041 * Re-opens (that is, closes and opens again) an AC'97 stream on the backend
2042 * side with the current AC'97 mixer settings for this stream.
2043 *
2044 * @returns VBox status code.
2045 * @param pDevIns The device instance.
2046 * @param pThis The shared AC'97 device state.
2047 * @param pThisCC The ring-3 AC'97 device state.
2048 * @param pStream The AC'97 stream to re-open (shared).
2049 * @param pStreamCC The AC'97 stream to re-open (ring-3).
2050 * @param fForce Whether to force re-opening the stream or not.
2051 * Otherwise re-opening only will happen if the PCM properties have changed.
2052 */
2053static int ichac97R3StreamReOpen(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
2054 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2055{
2056 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2057 Assert(pStream->u8SD == pStreamCC->u8SD);
2058 Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2059 Assert(pStreamCC - &pThisCC->aStreams[0] == pStream->u8SD);
2060
2061 int rc = ichac97R3StreamClose(pStream);
2062 if (RT_SUCCESS(rc))
2063 rc = ichac97R3StreamOpen(pDevIns, pThis, pThisCC, pStream, pStreamCC, fForce);
2064
2065 return rc;
2066}
2067
2068/**
2069 * Locks an AC'97 stream for serialized access.
2070 *
2071 * @returns VBox status code.
2072 * @param pStreamCC The AC'97 stream to lock (ring-3).
2073 */
2074static void ichac97R3StreamLock(PAC97STREAMR3 pStreamCC)
2075{
2076 int rc2 = RTCritSectEnter(&pStreamCC->State.CritSect);
2077 AssertRC(rc2);
2078}
2079
2080/**
2081 * Unlocks a formerly locked AC'97 stream.
2082 *
2083 * @returns VBox status code.
2084 * @param pStreamCC The AC'97 stream to unlock (ring-3).
2085 */
2086static void ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC)
2087{
2088 int rc2 = RTCritSectLeave(&pStreamCC->State.CritSect);
2089 AssertRC(rc2);
2090}
2091
2092/**
2093 * Retrieves the available size of (buffered) audio data (in bytes) of a given AC'97 stream.
2094 *
2095 * @returns Available data (in bytes).
2096 * @param pStreamCC The AC'97 stream to retrieve size for (ring-3).
2097 */
2098static uint32_t ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC)
2099{
2100 if (!pStreamCC->State.pCircBuf)
2101 return 0;
2102
2103 return (uint32_t)RTCircBufUsed(pStreamCC->State.pCircBuf);
2104}
2105
2106/**
2107 * Retrieves the free size of audio data (in bytes) of a given AC'97 stream.
2108 *
2109 * @returns Free data (in bytes).
2110 * @param pStreamCC AC'97 stream to retrieve size for (ring-3).
2111 */
2112static uint32_t ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC)
2113{
2114 if (!pStreamCC->State.pCircBuf)
2115 return 0;
2116
2117 return (uint32_t)RTCircBufFree(pStreamCC->State.pCircBuf);
2118}
2119
2120/**
2121 * Sets the volume of a specific AC'97 mixer control.
2122 *
2123 * This currently only supports attenuation -- gain support is currently not implemented.
2124 *
2125 * @returns VBox status code.
2126 * @param pThis The shared AC'97 state.
2127 * @param pThisCC The ring-3 AC'97 state.
2128 * @param index AC'97 mixer index to set volume for.
2129 * @param enmMixerCtl Corresponding audio mixer sink.
2130 * @param uVal Volume value to set.
2131 */
2132static int ichac97R3MixerSetVolume(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2133{
2134 /*
2135 * From AC'97 SoundMax Codec AD1981A/AD1981B:
2136 * "Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the
2137 * D5 or D13 bits are set to 1, their respective lower five volume bits are automatically
2138 * set to 1 by the Codec logic. On readback, all lower 5 bits will read ones whenever
2139 * these bits are set to 1."
2140 *
2141 * Linux ALSA depends on this behavior to detect that only 5 bits are used for volume
2142 * control and the optional 6th bit is not used. Note that this logic only applies to the
2143 * master volume controls.
2144 */
2145 if (index == AC97_Master_Volume_Mute || index == AC97_Headphone_Volume_Mute || index == AC97_Master_Volume_Mono_Mute)
2146 {
2147 if (uVal & RT_BIT(5)) /* D5 bit set? */
2148 uVal |= RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0);
2149 if (uVal & RT_BIT(13)) /* D13 bit set? */
2150 uVal |= RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8);
2151 }
2152
2153 const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2154 uint8_t uCtlAttLeft = (uVal >> 8) & AC97_BARS_VOL_MASK;
2155 uint8_t uCtlAttRight = uVal & AC97_BARS_VOL_MASK;
2156
2157 /* For the master and headphone volume, 0 corresponds to 0dB attenuation. For the other
2158 * volume controls, 0 means 12dB gain and 8 means unity gain.
2159 */
2160 if (index != AC97_Master_Volume_Mute && index != AC97_Headphone_Volume_Mute)
2161 {
2162# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2163 /* NB: Currently there is no gain support, only attenuation. */
2164 uCtlAttLeft = uCtlAttLeft < 8 ? 0 : uCtlAttLeft - 8;
2165 uCtlAttRight = uCtlAttRight < 8 ? 0 : uCtlAttRight - 8;
2166# endif
2167 }
2168 Assert(uCtlAttLeft <= 255 / AC97_DB_FACTOR);
2169 Assert(uCtlAttRight <= 255 / AC97_DB_FACTOR);
2170
2171 LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2172 LogFunc(("uCtlAttLeft=%RU8, uCtlAttRight=%RU8 ", uCtlAttLeft, uCtlAttRight));
2173
2174 /*
2175 * For AC'97 volume controls, each additional step means -1.5dB attenuation with
2176 * zero being maximum. In contrast, we're internally using 255 (PDMAUDIO_VOLUME_MAX)
2177 * steps, each -0.375dB, where 0 corresponds to -96dB and 255 corresponds to 0dB.
2178 */
2179 uint8_t lVol = PDMAUDIO_VOLUME_MAX - uCtlAttLeft * AC97_DB_FACTOR;
2180 uint8_t rVol = PDMAUDIO_VOLUME_MAX - uCtlAttRight * AC97_DB_FACTOR;
2181
2182 Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2183
2184 int rc = VINF_SUCCESS;
2185
2186 if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2187 {
2188 PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2189 PAUDMIXSINK pSink = NULL;
2190
2191 switch (enmMixerCtl)
2192 {
2193 case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2194 rc = AudioMixerSetMasterVolume(pThisCC->pMixer, &Vol);
2195 break;
2196
2197 case PDMAUDIOMIXERCTL_FRONT:
2198 pSink = pThisCC->pSinkOut;
2199 break;
2200
2201 case PDMAUDIOMIXERCTL_MIC_IN:
2202 case PDMAUDIOMIXERCTL_LINE_IN:
2203 /* These are recognized but do nothing. */
2204 break;
2205
2206 default:
2207 AssertFailed();
2208 rc = VERR_NOT_SUPPORTED;
2209 break;
2210 }
2211
2212 if (pSink)
2213 rc = AudioMixerSinkSetVolume(pSink, &Vol);
2214 }
2215
2216 ichac97MixerSet(pThis, index, uVal);
2217
2218 if (RT_FAILURE(rc))
2219 LogFlowFunc(("Failed with %Rrc\n", rc));
2220
2221 return rc;
2222}
2223
2224/**
2225 * Sets the gain of a specific AC'97 recording control.
2226 *
2227 * NB: gain support is currently not implemented in PDM audio.
2228 *
2229 * @returns VBox status code.
2230 * @param pThis The shared AC'97 state.
2231 * @param pThisCC The ring-3 AC'97 state.
2232 * @param index AC'97 mixer index to set volume for.
2233 * @param enmMixerCtl Corresponding audio mixer sink.
2234 * @param uVal Volume value to set.
2235 */
2236static int ichac97R3MixerSetGain(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
2237{
2238 /*
2239 * For AC'97 recording controls, each additional step means +1.5dB gain with
2240 * zero being 0dB gain and 15 being +22.5dB gain.
2241 */
2242 const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
2243 uint8_t uCtlGainLeft = (uVal >> 8) & AC97_BARS_GAIN_MASK;
2244 uint8_t uCtlGainRight = uVal & AC97_BARS_GAIN_MASK;
2245
2246 Assert(uCtlGainLeft <= 255 / AC97_DB_FACTOR);
2247 Assert(uCtlGainRight <= 255 / AC97_DB_FACTOR);
2248
2249 LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
2250 LogFunc(("uCtlGainLeft=%RU8, uCtlGainRight=%RU8 ", uCtlGainLeft, uCtlGainRight));
2251
2252 uint8_t lVol = PDMAUDIO_VOLUME_MAX + uCtlGainLeft * AC97_DB_FACTOR;
2253 uint8_t rVol = PDMAUDIO_VOLUME_MAX + uCtlGainRight * AC97_DB_FACTOR;
2254
2255 /* We do not currently support gain. Since AC'97 does not support attenuation
2256 * for the recording input, the best we can do is set the maximum volume.
2257 */
2258# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
2259 /* NB: Currently there is no gain support, only attenuation. Since AC'97 does not
2260 * support attenuation for the recording inputs, the best we can do is set the
2261 * maximum volume.
2262 */
2263 lVol = rVol = PDMAUDIO_VOLUME_MAX;
2264# endif
2265
2266 Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
2267
2268 int rc = VINF_SUCCESS;
2269
2270 if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
2271 {
2272 PDMAUDIOVOLUME Vol = { fCtlMuted, lVol, rVol };
2273 PAUDMIXSINK pSink = NULL;
2274
2275 switch (enmMixerCtl)
2276 {
2277 case PDMAUDIOMIXERCTL_MIC_IN:
2278 pSink = pThisCC->pSinkMicIn;
2279 break;
2280
2281 case PDMAUDIOMIXERCTL_LINE_IN:
2282 pSink = pThisCC->pSinkLineIn;
2283 break;
2284
2285 default:
2286 AssertFailed();
2287 rc = VERR_NOT_SUPPORTED;
2288 break;
2289 }
2290
2291 if (pSink) {
2292 rc = AudioMixerSinkSetVolume(pSink, &Vol);
2293 /* There is only one AC'97 recording gain control. If line in
2294 * is changed, also update the microphone. If the optional dedicated
2295 * microphone is changed, only change that.
2296 * NB: The codecs we support do not have the dedicated microphone control.
2297 */
2298 if ((pSink == pThisCC->pSinkLineIn) && pThisCC->pSinkMicIn)
2299 rc = AudioMixerSinkSetVolume(pSink, &Vol);
2300 }
2301 }
2302
2303 ichac97MixerSet(pThis, index, uVal);
2304
2305 if (RT_FAILURE(rc))
2306 LogFlowFunc(("Failed with %Rrc\n", rc));
2307
2308 return rc;
2309}
2310
2311/**
2312 * Converts an AC'97 recording source index to a PDM audio recording source.
2313 *
2314 * @returns PDM audio recording source.
2315 * @param uIdx AC'97 index to convert.
2316 */
2317static PDMAUDIOPATH ichac97R3IdxToRecSource(uint8_t uIdx)
2318{
2319 switch (uIdx)
2320 {
2321 case AC97_REC_MIC: return PDMAUDIOPATH_IN_MIC;
2322 case AC97_REC_CD: return PDMAUDIOPATH_IN_CD;
2323 case AC97_REC_VIDEO: return PDMAUDIOPATH_IN_VIDEO;
2324 case AC97_REC_AUX: return PDMAUDIOPATH_IN_AUX;
2325 case AC97_REC_LINE_IN: return PDMAUDIOPATH_IN_LINE;
2326 case AC97_REC_PHONE: return PDMAUDIOPATH_IN_PHONE;
2327 default:
2328 break;
2329 }
2330
2331 LogFlowFunc(("Unknown record source %d, using MIC\n", uIdx));
2332 return PDMAUDIOPATH_IN_MIC;
2333}
2334
2335/**
2336 * Converts a PDM audio recording source to an AC'97 recording source index.
2337 *
2338 * @returns AC'97 recording source index.
2339 * @param enmRecSrc PDM audio recording source to convert.
2340 */
2341static uint8_t ichac97R3RecSourceToIdx(PDMAUDIOPATH enmRecSrc)
2342{
2343 switch (enmRecSrc)
2344 {
2345 case PDMAUDIOPATH_IN_MIC: return AC97_REC_MIC;
2346 case PDMAUDIOPATH_IN_CD: return AC97_REC_CD;
2347 case PDMAUDIOPATH_IN_VIDEO: return AC97_REC_VIDEO;
2348 case PDMAUDIOPATH_IN_AUX: return AC97_REC_AUX;
2349 case PDMAUDIOPATH_IN_LINE: return AC97_REC_LINE_IN;
2350 case PDMAUDIOPATH_IN_PHONE: return AC97_REC_PHONE;
2351 default:
2352 AssertMsgFailedBreak(("%d\n", enmRecSrc));
2353 }
2354
2355 LogFlowFunc(("Unknown audio recording source %d using MIC\n", enmRecSrc));
2356 return AC97_REC_MIC;
2357}
2358
2359/**
2360 * Returns the audio direction of a specified stream descriptor.
2361 *
2362 * @return Audio direction.
2363 */
2364DECLINLINE(PDMAUDIODIR) ichac97GetDirFromSD(uint8_t uSD)
2365{
2366 switch (uSD)
2367 {
2368 case AC97SOUNDSOURCE_PI_INDEX: return PDMAUDIODIR_IN;
2369 case AC97SOUNDSOURCE_PO_INDEX: return PDMAUDIODIR_OUT;
2370 case AC97SOUNDSOURCE_MC_INDEX: return PDMAUDIODIR_IN;
2371 }
2372
2373 AssertFailed();
2374 return PDMAUDIODIR_UNKNOWN;
2375}
2376
2377#endif /* IN_RING3 */
2378
2379#ifdef IN_RING3
2380
2381/**
2382 * Performs an AC'97 mixer record select to switch to a different recording
2383 * source.
2384 *
2385 * @param pThis The shared AC'97 state.
2386 * @param val AC'97 recording source index to set.
2387 */
2388static void ichac97R3MixerRecordSelect(PAC97STATE pThis, uint32_t val)
2389{
2390 uint8_t rs = val & AC97_REC_MASK;
2391 uint8_t ls = (val >> 8) & AC97_REC_MASK;
2392
2393 PDMAUDIOPATH const ars = ichac97R3IdxToRecSource(rs);
2394 PDMAUDIOPATH const als = ichac97R3IdxToRecSource(ls);
2395
2396 rs = ichac97R3RecSourceToIdx(ars);
2397 ls = ichac97R3RecSourceToIdx(als);
2398
2399 LogRel(("AC97: Record select to left=%s, right=%s\n", PDMAudioPathGetName(ars), PDMAudioPathGetName(als)));
2400
2401 ichac97MixerSet(pThis, AC97_Record_Select, rs | (ls << 8));
2402}
2403
2404/**
2405 * Resets the AC'97 mixer.
2406 *
2407 * @returns VBox status code.
2408 * @param pThis The shared AC'97 state.
2409 * @param pThisCC The ring-3 AC'97 state.
2410 */
2411static int ichac97R3MixerReset(PAC97STATE pThis, PAC97STATER3 pThisCC)
2412{
2413 LogFlowFuncEnter();
2414
2415 RT_ZERO(pThis->mixer_data);
2416
2417 /* Note: Make sure to reset all registers first before bailing out on error. */
2418
2419 ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
2420 ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
2421 ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
2422
2423 ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
2424 ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
2425 ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
2426 ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
2427 ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
2428 ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
2429 ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
2430 ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
2431
2432 /* Configure Extended Audio ID (EAID) + Control & Status (EACS) registers. */
2433 const uint16_t fEAID = AC97_EAID_REV1 | AC97_EACS_VRA | AC97_EACS_VRM; /* Our hardware is AC'97 rev2.3 compliant. */
2434 const uint16_t fEACS = AC97_EACS_VRA | AC97_EACS_VRM; /* Variable Rate PCM Audio (VRA) + Mic-In (VRM) capable. */
2435
2436 LogRel(("AC97: Mixer reset (EAID=0x%x, EACS=0x%x)\n", fEAID, fEACS));
2437
2438 ichac97MixerSet(pThis, AC97_Extended_Audio_ID, fEAID);
2439 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, fEACS);
2440 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2441 ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2442 ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
2443 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2444 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
2445
2446 if (pThis->enmCodecModel == AC97CODEC_AD1980)
2447 {
2448 /* Analog Devices 1980 (AD1980) */
2449 ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
2450 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2451 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
2452 ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
2453 }
2454 else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
2455 {
2456 /* Analog Devices 1981B (AD1981B) */
2457 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
2458 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
2459 }
2460 else
2461 {
2462 /* Sigmatel 9700 (STAC9700) */
2463 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
2464 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
2465 }
2466 ichac97R3MixerRecordSelect(pThis, 0);
2467
2468 /* The default value is 8000h, which corresponds to 0 dB attenuation with mute on. */
2469 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER, 0x8000);
2470
2471 /* The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on.*/
2472 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT, 0x8808);
2473 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
2474 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8008);
2475
2476 /* The default for record controls is 0 dB gain with mute on. */
2477 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8000);
2478 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8000);
2479
2480 return VINF_SUCCESS;
2481}
2482
2483# if 0 /* Unused */
2484static void ichac97R3WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
2485{
2486 LogFlowFunc(("cbElapsed=%RU32\n", cbElapsed));
2487
2488 if (!(pThis->bup_flag & BUP_SET))
2489 {
2490 if (pThis->bup_flag & BUP_LAST)
2491 {
2492 unsigned int i;
2493 uint32_t *p = (uint32_t*)pThis->silence;
2494 for (i = 0; i < sizeof(pThis->silence) / 4; i++) /** @todo r=andy Assumes 16-bit samples, stereo. */
2495 *p++ = pThis->last_samp;
2496 }
2497 else
2498 RT_ZERO(pThis->silence);
2499
2500 pThis->bup_flag |= BUP_SET;
2501 }
2502
2503 while (cbElapsed)
2504 {
2505 uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
2506 uint32_t cbWrittenToStream;
2507
2508 int rc2 = AudioMixerSinkWrite(pThisCC->pSinkOut, AUDMIXOP_COPY,
2509 pThis->silence, cbToWrite, &cbWrittenToStream);
2510 if (RT_SUCCESS(rc2))
2511 {
2512 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2513 LogFlowFunc(("Warning: Only written %RU32 / %RU32 bytes, expect lags\n", cbWrittenToStream, cbToWrite));
2514 }
2515
2516 /* Always report all data as being written;
2517 * backends who were not able to catch up have to deal with it themselves. */
2518 Assert(cbElapsed >= cbToWrite);
2519 cbElapsed -= cbToWrite;
2520 }
2521}
2522# endif /* Unused */
2523
2524/**
2525 * @callback_method_impl{FNTMTIMERDEV,
2526 * Timer callback which handles the audio data transfers on a periodic basis.}
2527 */
2528static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
2529{
2530 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2531 STAM_PROFILE_START(&pThis->StatTimer, a);
2532 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
2533 PAC97STREAM pStream = (PAC97STREAM)pvUser;
2534 PAC97STREAMR3 pStreamCC = &RT_SAFE_SUBSCRIPT8(pThisCC->aStreams, pStream->u8SD);
2535 Assert(hTimer == pStream->hTimer); RT_NOREF(hTimer);
2536
2537 Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2538 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2539 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStream->hTimer));
2540
2541 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
2542 if (pSink && AudioMixerSinkIsActive(pSink))
2543 {
2544 ichac97R3StreamUpdateDma(pDevIns, pThis, pThisCC, pStream, pStreamCC, pSink);
2545
2546 ichac97R3StreamTransferUpdate(pDevIns, pStream, pStreamCC);
2547 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
2548 }
2549
2550 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2551}
2552
2553
2554/**
2555 * Sets the virtual device timer to a new expiration time.
2556 *
2557 * @param pDevIns The device instance.
2558 * @param pStream AC'97 stream to set timer for.
2559 * @param cTicksToDeadline The number of ticks to the new deadline.
2560 *
2561 * @remarks This used to be more complicated a long time ago...
2562 */
2563DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline)
2564{
2565 int rc = PDMDevHlpTimerSetRelative(pDevIns, pStream->hTimer, cTicksToDeadline, NULL /*pu64Now*/);
2566 AssertRC(rc);
2567}
2568
2569
2570/**
2571 * Transfers data of an AC'97 stream according to its usage (input / output).
2572 *
2573 * For an SDO (output) stream this means reading DMA data from the device to
2574 * the AC'97 stream's internal FIFO buffer.
2575 *
2576 * For an SDI (input) stream this is reading audio data from the AC'97 stream's
2577 * internal FIFO buffer and writing it as DMA data to the device.
2578 *
2579 * @returns VBox status code.
2580 * @param pDevIns The device instance.
2581 * @param pThis The shared AC'97 state.
2582 * @param pStream The AC'97 stream to update (shared).
2583 * @param pStreamCC The AC'97 stream to update (ring-3).
2584 * @param cbToProcessMax Maximum of data (in bytes) to process.
2585 */
2586static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
2587 PAC97STREAMR3 pStreamCC, uint32_t cbToProcessMax)
2588{
2589 if (!cbToProcessMax)
2590 return VINF_SUCCESS;
2591
2592#ifdef VBOX_STRICT
2593 const unsigned cbFrame = PDMAudioPropsBytesPerFrame(&pStreamCC->State.Cfg.Props);
2594#endif
2595
2596 /* Make sure to only process an integer number of audio frames. */
2597 Assert(cbToProcessMax % cbFrame == 0);
2598
2599 ichac97R3StreamLock(pStreamCC);
2600
2601 PAC97BMREGS pRegs = &pStream->Regs;
2602
2603 if (pRegs->sr & AC97_SR_DCH) /* Controller halted? */
2604 {
2605 if (pRegs->cr & AC97_CR_RPBM) /* Bus master operation starts. */
2606 {
2607 switch (pStream->u8SD)
2608 {
2609 case AC97SOUNDSOURCE_PO_INDEX:
2610 /*ichac97R3WriteBUP(pThis, cbToProcess);*/
2611 break;
2612
2613 default:
2614 break;
2615 }
2616 }
2617
2618 ichac97R3StreamUnlock(pStreamCC);
2619 return VINF_SUCCESS;
2620 }
2621
2622 /* BCIS flag still set? Skip iteration. */
2623 if (pRegs->sr & AC97_SR_BCIS)
2624 {
2625 Log3Func(("[SD%RU8] BCIS set\n", pStream->u8SD));
2626
2627 ichac97R3StreamUnlock(pStreamCC);
2628 return VINF_SUCCESS;
2629 }
2630
2631 uint32_t cbLeft = RT_MIN((uint32_t)(pRegs->picb << 1), cbToProcessMax); /** @todo r=andy Assumes 16bit samples. */
2632 uint32_t cbProcessedTotal = 0;
2633
2634 PRTCIRCBUF pCircBuf = pStreamCC->State.pCircBuf;
2635 AssertPtr(pCircBuf);
2636
2637 int rc = VINF_SUCCESS;
2638
2639 Log3Func(("[SD%RU8] cbToProcessMax=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcessMax, cbLeft));
2640
2641 while (cbLeft)
2642 {
2643 if (!pRegs->picb) /* Got a new buffer descriptor, that is, the position is 0? */
2644 {
2645 Log3Func(("Fresh buffer descriptor %RU8 is empty, addr=%#x, len=%#x, skipping\n",
2646 pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len));
2647 if (pRegs->civ == pRegs->lvi)
2648 {
2649 pRegs->sr |= AC97_SR_DCH; /** @todo r=andy Also set CELV? */
2650 pThis->bup_flag = 0;
2651
2652 rc = VINF_EOF;
2653 break;
2654 }
2655
2656 pRegs->sr &= ~AC97_SR_CELV;
2657 if (ichac97R3StreamFetchNextBdle(pDevIns, pStream, pStreamCC))
2658 ichac97StreamUpdateSR(pDevIns, pThis, pStream, pRegs->sr | AC97_SR_BCIS);
2659 continue;
2660 }
2661
2662 uint32_t cbChunk = cbLeft;
2663
2664 switch (pStream->u8SD)
2665 {
2666 case AC97SOUNDSOURCE_PO_INDEX: /* Output */
2667 {
2668 void *pvDst;
2669 size_t cbDst;
2670
2671 RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvDst, &cbDst);
2672
2673 if (cbDst)
2674 {
2675 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, pRegs->bd.addr, (uint8_t *)pvDst, cbDst);
2676 AssertRC(rc2);
2677
2678 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2679 { /* likely */ }
2680 else
2681 AudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvDst, cbDst, 0 /* fFlags */);
2682 }
2683
2684 RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
2685
2686 cbChunk = (uint32_t)cbDst; /* Update the current chunk size to what really has been written. */
2687 break;
2688 }
2689
2690 case AC97SOUNDSOURCE_PI_INDEX: /* Input */
2691 case AC97SOUNDSOURCE_MC_INDEX: /* Input */
2692 {
2693 void *pvSrc;
2694 size_t cbSrc;
2695
2696 RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvSrc, &cbSrc);
2697
2698 if (cbSrc)
2699 {
2700 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, pRegs->bd.addr, (uint8_t *)pvSrc, cbSrc);
2701 AssertRC(rc2);
2702
2703 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2704 { /* likely */ }
2705 else
2706 AudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvSrc, cbSrc, 0 /* fFlags */);
2707 }
2708
2709 RTCircBufReleaseReadBlock(pCircBuf, cbSrc);
2710
2711 cbChunk = (uint32_t)cbSrc; /* Update the current chunk size to what really has been read. */
2712 break;
2713 }
2714
2715 default:
2716 AssertMsgFailed(("Stream #%RU8 not supported\n", pStream->u8SD));
2717 rc = VERR_NOT_SUPPORTED;
2718 break;
2719 }
2720
2721 if (RT_FAILURE(rc))
2722 break;
2723
2724 if (cbChunk)
2725 {
2726 cbProcessedTotal += cbChunk;
2727 Assert(cbProcessedTotal <= cbToProcessMax);
2728 Assert(cbLeft >= cbChunk);
2729 cbLeft -= cbChunk;
2730 Assert((cbChunk & 1) == 0); /* Else the following shift won't work */
2731
2732 pRegs->picb -= (cbChunk >> 1); /** @todo r=andy Assumes 16bit samples. */
2733 pRegs->bd.addr += cbChunk;
2734 }
2735
2736 LogFlowFunc(("[SD%RU8] cbChunk=%RU32, cbLeft=%RU32, cbTotal=%RU32, rc=%Rrc\n",
2737 pStream->u8SD, cbChunk, cbLeft, cbProcessedTotal, rc));
2738
2739 if (!pRegs->picb)
2740 {
2741 uint32_t new_sr = pRegs->sr & ~AC97_SR_CELV;
2742
2743 if (pRegs->bd.ctl_len & AC97_BD_IOC)
2744 {
2745 new_sr |= AC97_SR_BCIS;
2746 }
2747
2748 if (pRegs->civ == pRegs->lvi)
2749 {
2750 /* Did we run out of data? */
2751 LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pRegs->civ, pRegs->lvi));
2752
2753 new_sr |= AC97_SR_LVBCI | AC97_SR_DCH | AC97_SR_CELV;
2754 pThis->bup_flag = (pRegs->bd.ctl_len & AC97_BD_BUP) ? BUP_LAST : 0;
2755
2756 rc = VINF_EOF;
2757 }
2758 else
2759 new_sr |= ichac97R3StreamFetchNextBdle(pDevIns, pStream, pStreamCC);
2760
2761 ichac97StreamUpdateSR(pDevIns, pThis, pStream, new_sr);
2762 }
2763
2764 if (/* All data processed? */
2765 rc == VINF_EOF
2766 /* ... or an error occurred? */
2767 || RT_FAILURE(rc))
2768 {
2769 break;
2770 }
2771 }
2772
2773 ichac97R3StreamUnlock(pStreamCC);
2774
2775 LogFlowFuncLeaveRC(rc);
2776 return rc;
2777}
2778
2779#endif /* IN_RING3 */
2780
2781
2782/**
2783 * @callback_method_impl{FNIOMIOPORTNEWIN}
2784 */
2785static DECLCALLBACK(VBOXSTRICTRC)
2786ichac97IoPortNabmRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2787{
2788 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2789 RT_NOREF(pvUser);
2790
2791 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
2792
2793 /* Get the index of the NABMBAR port. */
2794 if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
2795 && offPort != AC97_GLOB_CNT)
2796 {
2797 PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
2798 PAC97BMREGS pRegs = &pStream->Regs;
2799
2800 switch (cb)
2801 {
2802 case 1:
2803 switch (offPort & AC97_NABM_OFF_MASK)
2804 {
2805 case AC97_NABM_OFF_CIV:
2806 /* Current Index Value Register */
2807 *pu32 = pRegs->civ;
2808 Log3Func(("CIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2809 break;
2810 case AC97_NABM_OFF_LVI:
2811 /* Last Valid Index Register */
2812 *pu32 = pRegs->lvi;
2813 Log3Func(("LVI[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2814 break;
2815 case AC97_NABM_OFF_PIV:
2816 /* Prefetched Index Value Register */
2817 *pu32 = pRegs->piv;
2818 Log3Func(("PIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2819 break;
2820 case AC97_NABM_OFF_CR:
2821 /* Control Register */
2822 *pu32 = pRegs->cr;
2823 Log3Func(("CR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2824 break;
2825 case AC97_NABM_OFF_SR:
2826 /* Status Register (lower part) */
2827 *pu32 = RT_LO_U8(pRegs->sr);
2828 Log3Func(("SRb[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2829 break;
2830 default:
2831 *pu32 = UINT32_MAX;
2832 LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
2833 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2834 break;
2835 }
2836 break;
2837
2838 case 2:
2839 switch (offPort & AC97_NABM_OFF_MASK)
2840 {
2841 case AC97_NABM_OFF_SR:
2842 /* Status Register */
2843 *pu32 = pRegs->sr;
2844 Log3Func(("SR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2845 break;
2846 case AC97_NABM_OFF_PICB:
2847 /* Position in Current Buffer */
2848 *pu32 = pRegs->picb;
2849 Log3Func(("PICB[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2850 break;
2851 default:
2852 *pu32 = UINT32_MAX;
2853 LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
2854 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2855 break;
2856 }
2857 break;
2858
2859 case 4:
2860 switch (offPort & AC97_NABM_OFF_MASK)
2861 {
2862 case AC97_NABM_OFF_BDBAR:
2863 /* Buffer Descriptor Base Address Register */
2864 *pu32 = pRegs->bdbar;
2865 Log3Func(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2866 break;
2867 case AC97_NABM_OFF_CIV:
2868 /* 32-bit access: Current Index Value Register +
2869 * Last Valid Index Register +
2870 * Status Register */
2871 *pu32 = pRegs->civ | ((uint32_t)pRegs->lvi << 8) | ((uint32_t)pRegs->sr << 16);
2872 Log3Func(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
2873 AC97_PORT2IDX(offPort), pRegs->civ, pRegs->lvi, pRegs->sr));
2874 break;
2875 case AC97_NABM_OFF_PICB:
2876 /* 32-bit access: Position in Current Buffer Register +
2877 * Prefetched Index Value Register +
2878 * Control Register */
2879 *pu32 = pRegs->picb | ((uint32_t)pRegs->piv << 16) | ((uint32_t)pRegs->cr << 24);
2880 Log3Func(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
2881 AC97_PORT2IDX(offPort), *pu32, pRegs->picb, pRegs->piv, pRegs->cr));
2882 break;
2883
2884 default:
2885 *pu32 = UINT32_MAX;
2886 LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
2887 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2888 break;
2889 }
2890 break;
2891
2892 default:
2893 DEVAC97_UNLOCK(pDevIns, pThis);
2894 AssertFailed();
2895 return VERR_IOM_IOPORT_UNUSED;
2896 }
2897 }
2898 else
2899 {
2900 switch (cb)
2901 {
2902 case 1:
2903 switch (offPort)
2904 {
2905 case AC97_CAS:
2906 /* Codec Access Semaphore Register */
2907 Log3Func(("CAS %d\n", pThis->cas));
2908 *pu32 = pThis->cas;
2909 pThis->cas = 1;
2910 break;
2911 default:
2912 *pu32 = UINT32_MAX;
2913 LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX));
2914 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2915 break;
2916 }
2917 break;
2918
2919 case 2:
2920 *pu32 = UINT32_MAX;
2921 LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX));
2922 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2923 break;
2924
2925 case 4:
2926 switch (offPort)
2927 {
2928 case AC97_GLOB_CNT:
2929 /* Global Control */
2930 *pu32 = pThis->glob_cnt;
2931 Log3Func(("glob_cnt -> %#x\n", *pu32));
2932 break;
2933 case AC97_GLOB_STA:
2934 /* Global Status */
2935 *pu32 = pThis->glob_sta | AC97_GS_S0CR;
2936 Log3Func(("glob_sta -> %#x\n", *pu32));
2937 break;
2938 default:
2939 *pu32 = UINT32_MAX;
2940 LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX));
2941 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2942 break;
2943 }
2944 break;
2945
2946 default:
2947 DEVAC97_UNLOCK(pDevIns, pThis);
2948 AssertFailed();
2949 return VERR_IOM_IOPORT_UNUSED;
2950 }
2951 }
2952
2953 DEVAC97_UNLOCK(pDevIns, pThis);
2954 return VINF_SUCCESS;
2955}
2956
2957/**
2958 * @callback_method_impl{FNIOMIOPORTNEWOUT}
2959 */
2960static DECLCALLBACK(VBOXSTRICTRC)
2961ichac97IoPortNabmWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2962{
2963 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2964#ifdef IN_RING3
2965 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
2966#endif
2967 RT_NOREF(pvUser);
2968
2969 VBOXSTRICTRC rc = VINF_SUCCESS;
2970 if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
2971 && offPort != AC97_GLOB_CNT)
2972 {
2973#ifdef IN_RING3
2974 PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[AC97_PORT2IDX(offPort)];
2975#endif
2976 PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
2977 PAC97BMREGS pRegs = &pStream->Regs;
2978
2979 DEVAC97_LOCK_BOTH_RETURN(pDevIns, pThis, pStream, VINF_IOM_R3_IOPORT_WRITE);
2980 switch (cb)
2981 {
2982 case 1:
2983 switch (offPort & AC97_NABM_OFF_MASK)
2984 {
2985 /*
2986 * Last Valid Index.
2987 */
2988 case AC97_NABM_OFF_LVI:
2989 if ( (pRegs->cr & AC97_CR_RPBM)
2990 && (pRegs->sr & AC97_SR_DCH))
2991 {
2992#ifdef IN_RING3 /** @todo r=bird: What kind of unexplained non-sense is this ifdef?!? */
2993 pRegs->sr &= ~(AC97_SR_DCH | AC97_SR_CELV);
2994 pRegs->civ = pRegs->piv;
2995 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE;
2996#else
2997 rc = VINF_IOM_R3_IOPORT_WRITE;
2998#endif
2999 }
3000 pRegs->lvi = u32 % AC97_MAX_BDLE;
3001 Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32));
3002 break;
3003
3004 /*
3005 * Control Registers.
3006 */
3007 case AC97_NABM_OFF_CR:
3008#ifdef IN_RING3
3009 Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32, pRegs->cr));
3010 if (u32 & AC97_CR_RR) /* Busmaster reset. */
3011 {
3012 Log3Func(("[SD%RU8] Reset\n", pStream->u8SD));
3013
3014 /* Make sure that Run/Pause Bus Master bit (RPBM) is cleared (0). */
3015 Assert((pRegs->cr & AC97_CR_RPBM) == 0);
3016 if (pRegs->cr & AC97_CR_RPBM)
3017 ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3018
3019 ichac97R3StreamReset(pThis, pStream, pStreamCC);
3020
3021 ichac97StreamUpdateSR(pDevIns, pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */
3022 }
3023 else
3024 {
3025 pRegs->cr = u32 & AC97_CR_VALID_MASK;
3026
3027 if (!(pRegs->cr & AC97_CR_RPBM))
3028 {
3029 Log3Func(("[SD%RU8] Disable\n", pStream->u8SD));
3030
3031 ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
3032
3033 pRegs->sr |= AC97_SR_DCH;
3034 }
3035 else
3036 {
3037 Log3Func(("[SD%RU8] Enable\n", pStream->u8SD));
3038
3039 pRegs->sr &= ~AC97_SR_DCH;
3040
3041 if (ichac97R3StreamFetchNextBdle(pDevIns, pStream, pStreamCC))
3042 ichac97StreamUpdateSR(pDevIns, pThis, pStream, pRegs->sr | AC97_SR_BCIS);
3043# ifdef LOG_ENABLED
3044 if (LogIsFlowEnabled())
3045 ichac97R3DbgPrintBdl(pDevIns, pThis, pStream, DBGFR3InfoLogHlp(), "ichac97IoPortNabmWrite: ");
3046# endif
3047 ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, true /* fEnable */);
3048
3049 /* Arm the timer for this stream. */
3050 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3051 }
3052 }
3053#else /* !IN_RING3 */
3054 rc = VINF_IOM_R3_IOPORT_WRITE;
3055#endif
3056 break;
3057
3058 /*
3059 * Status Registers.
3060 */
3061 case AC97_NABM_OFF_SR:
3062 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3063 break;
3064
3065 default:
3066 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3067 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3068 break;
3069 }
3070 break;
3071
3072 case 2:
3073 switch (offPort & AC97_NABM_OFF_MASK)
3074 {
3075 case AC97_NABM_OFF_SR:
3076 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
3077 break;
3078 default:
3079 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3080 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3081 break;
3082 }
3083 break;
3084
3085 case 4:
3086 switch (offPort & AC97_NABM_OFF_MASK)
3087 {
3088 case AC97_NABM_OFF_BDBAR:
3089 /* Buffer Descriptor list Base Address Register */
3090 pRegs->bdbar = u32 & ~(uint32_t)3;
3091 Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(offPort), u32, pRegs->bdbar));
3092 break;
3093 default:
3094 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3095 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3096 break;
3097 }
3098 break;
3099
3100 default:
3101 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3102 break;
3103 }
3104 DEVAC97_UNLOCK_BOTH(pDevIns, pThis, pStream);
3105 }
3106 else
3107 {
3108 switch (cb)
3109 {
3110 case 1:
3111 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32));
3112 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3113 break;
3114
3115 case 2:
3116 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32));
3117 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3118 break;
3119
3120 case 4:
3121 switch (offPort)
3122 {
3123 case AC97_GLOB_CNT:
3124 /* Global Control */
3125 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3126 if (u32 & AC97_GC_WR)
3127 ichac97WarmReset(pThis);
3128 if (u32 & AC97_GC_CR)
3129 ichac97ColdReset(pThis);
3130 if (!(u32 & (AC97_GC_WR | AC97_GC_CR)))
3131 pThis->glob_cnt = u32 & AC97_GC_VALID_MASK;
3132 Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt));
3133 DEVAC97_UNLOCK(pDevIns, pThis);
3134 break;
3135 case AC97_GLOB_STA:
3136 /* Global Status */
3137 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3138 pThis->glob_sta &= ~(u32 & AC97_GS_WCLEAR_MASK);
3139 pThis->glob_sta |= (u32 & ~(AC97_GS_WCLEAR_MASK | AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK;
3140 Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta));
3141 DEVAC97_UNLOCK(pDevIns, pThis);
3142 break;
3143 default:
3144 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32));
3145 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
3146 break;
3147 }
3148 break;
3149
3150 default:
3151 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
3152 break;
3153 }
3154 }
3155
3156 return rc;
3157}
3158
3159/**
3160 * @callback_method_impl{FNIOMIOPORTNEWIN}
3161 */
3162static DECLCALLBACK(VBOXSTRICTRC)
3163ichac97IoPortNamRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
3164{
3165 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3166 RT_NOREF(pvUser);
3167 Assert(offPort < 256);
3168
3169 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3170
3171 VBOXSTRICTRC rc = VINF_SUCCESS;
3172 switch (cb)
3173 {
3174 case 1:
3175 {
3176 LogRel2(("AC97: Warning: Unimplemented read (1 byte) offPort=%#x\n", offPort));
3177 pThis->cas = 0;
3178 *pu32 = UINT32_MAX;
3179 break;
3180 }
3181
3182 case 2:
3183 {
3184 pThis->cas = 0;
3185 *pu32 = ichac97MixerGet(pThis, offPort);
3186 break;
3187 }
3188
3189 case 4:
3190 {
3191 LogRel2(("AC97: Warning: Unimplemented read (4 bytes) offPort=%#x\n", offPort));
3192 pThis->cas = 0;
3193 *pu32 = UINT32_MAX;
3194 break;
3195 }
3196
3197 default:
3198 {
3199 AssertFailed();
3200 rc = VERR_IOM_IOPORT_UNUSED;
3201 }
3202 }
3203
3204 DEVAC97_UNLOCK(pDevIns, pThis);
3205 return rc;
3206}
3207
3208/**
3209 * @callback_method_impl{FNIOMIOPORTNEWOUT}
3210 */
3211static DECLCALLBACK(VBOXSTRICTRC)
3212ichac97IoPortNamWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3213{
3214 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3215#ifdef IN_RING3
3216 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3217#endif
3218 RT_NOREF(pvUser);
3219
3220 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3221
3222 VBOXSTRICTRC rc = VINF_SUCCESS;
3223 switch (cb)
3224 {
3225 case 1:
3226 {
3227 LogRel2(("AC97: Warning: Unimplemented NAMWrite (1 byte) offPort=%#x <- %#x\n", offPort, u32));
3228 pThis->cas = 0;
3229 break;
3230 }
3231
3232 case 2:
3233 {
3234 pThis->cas = 0;
3235 switch (offPort)
3236 {
3237 case AC97_Reset:
3238#ifdef IN_RING3
3239 ichac97R3Reset(pDevIns);
3240#else
3241 rc = VINF_IOM_R3_IOPORT_WRITE;
3242#endif
3243 break;
3244 case AC97_Powerdown_Ctrl_Stat:
3245 u32 &= ~0xf;
3246 u32 |= ichac97MixerGet(pThis, offPort) & 0xf;
3247 ichac97MixerSet(pThis, offPort, u32);
3248 break;
3249 case AC97_Master_Volume_Mute:
3250 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3251 {
3252 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_LOSEL)
3253 break; /* Register controls surround (rear), do nothing. */
3254 }
3255#ifdef IN_RING3
3256 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3257#else
3258 rc = VINF_IOM_R3_IOPORT_WRITE;
3259#endif
3260 break;
3261 case AC97_Headphone_Volume_Mute:
3262 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3263 {
3264 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3265 {
3266 /* Register controls PCM (front) outputs. */
3267#ifdef IN_RING3
3268 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3269#else
3270 rc = VINF_IOM_R3_IOPORT_WRITE;
3271#endif
3272 }
3273 }
3274 break;
3275 case AC97_PCM_Out_Volume_Mute:
3276#ifdef IN_RING3
3277 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_FRONT, u32);
3278#else
3279 rc = VINF_IOM_R3_IOPORT_WRITE;
3280#endif
3281 break;
3282 case AC97_Line_In_Volume_Mute:
3283#ifdef IN_RING3
3284 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3285#else
3286 rc = VINF_IOM_R3_IOPORT_WRITE;
3287#endif
3288 break;
3289 case AC97_Record_Select:
3290#ifdef IN_RING3
3291 ichac97R3MixerRecordSelect(pThis, u32);
3292#else
3293 rc = VINF_IOM_R3_IOPORT_WRITE;
3294#endif
3295 break;
3296 case AC97_Record_Gain_Mute:
3297#ifdef IN_RING3
3298 /* Newer Ubuntu guests rely on that when controlling gain and muting
3299 * the recording (capturing) levels. */
3300 ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3301#else
3302 rc = VINF_IOM_R3_IOPORT_WRITE;
3303#endif
3304 break;
3305 case AC97_Record_Gain_Mic_Mute:
3306#ifdef IN_RING3
3307 /* Ditto; see note above. */
3308 ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_MIC_IN, u32);
3309#else
3310 rc = VINF_IOM_R3_IOPORT_WRITE;
3311#endif
3312 break;
3313 case AC97_Vendor_ID1:
3314 case AC97_Vendor_ID2:
3315 LogFunc(("Attempt to write vendor ID to %#x\n", u32));
3316 break;
3317 case AC97_Extended_Audio_ID:
3318 LogFunc(("Attempt to write extended audio ID to %#x\n", u32));
3319 break;
3320 case AC97_Extended_Audio_Ctrl_Stat:
3321#ifdef IN_RING3
3322 /*
3323 * Handle VRA bits.
3324 */
3325 if (!(u32 & AC97_EACS_VRA)) /* Check if VRA bit is not set. */
3326 {
3327 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 0xbb80); /* Set default (48000 Hz). */
3328 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3329 * actually used? */
3330 ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3331 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3332
3333 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3334 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3335 * actually used? */
3336 ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3337 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3338 }
3339 else
3340 LogRel2(("AC97: Variable rate audio (VRA) is not supported\n"));
3341
3342 /*
3343 * Handle VRM bits.
3344 */
3345 if (!(u32 & AC97_EACS_VRM)) /* Check if VRM bit is not set. */
3346 {
3347 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3348 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3349 * actually used? */
3350 ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3351 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3352 }
3353 else
3354 LogRel2(("AC97: Variable rate microphone audio (VRM) is not supported\n"));
3355
3356 LogRel2(("AC97: Setting extended audio control to %#x\n", u32));
3357 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32);
3358#else /* !IN_RING3 */
3359 rc = VINF_IOM_R3_IOPORT_WRITE;
3360#endif
3361 break;
3362 case AC97_PCM_Front_DAC_Rate: /* Output slots 3, 4, 6. */
3363#ifdef IN_RING3
3364 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3365 {
3366 LogRel2(("AC97: Setting front DAC rate to 0x%x\n", u32));
3367 ichac97MixerSet(pThis, offPort, u32);
3368 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3369 * actually used? */
3370 ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3371 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3372 }
3373 else
3374 LogRel2(("AC97: Setting front DAC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3375#else
3376 rc = VINF_IOM_R3_IOPORT_WRITE;
3377#endif
3378 break;
3379 case AC97_MIC_ADC_Rate: /* Input slot 6. */
3380#ifdef IN_RING3
3381 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRM)
3382 {
3383 LogRel2(("AC97: Setting microphone ADC rate to 0x%x\n", u32));
3384 ichac97MixerSet(pThis, offPort, u32);
3385 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3386 * actually used? */
3387 ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3388 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3389 }
3390 else
3391 LogRel2(("AC97: Setting microphone ADC rate (0x%x) when VRM is not set is forbidden, ignoring\n", u32));
3392#else
3393 rc = VINF_IOM_R3_IOPORT_WRITE;
3394#endif
3395 break;
3396 case AC97_PCM_LR_ADC_Rate: /* Input slots 3, 4. */
3397#ifdef IN_RING3
3398 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3399 {
3400 LogRel2(("AC97: Setting line-in ADC rate to 0x%x\n", u32));
3401 ichac97MixerSet(pThis, offPort, u32);
3402 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3403 * actually used? */
3404 ichac97R3StreamReOpen(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3405 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3406 }
3407 else
3408 LogRel2(("AC97: Setting line-in ADC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3409#else
3410 rc = VINF_IOM_R3_IOPORT_WRITE;
3411#endif
3412 break;
3413 default:
3414 LogRel2(("AC97: Warning: Unimplemented NAMWrite (2 bytes) offPort=%#x <- %#x\n", offPort, u32));
3415 ichac97MixerSet(pThis, offPort, u32);
3416 break;
3417 }
3418 break;
3419 }
3420
3421 case 4:
3422 {
3423 LogRel2(("AC97: Warning: Unimplemented 4 byte NAMWrite: offPort=%#x <- %#x\n", offPort, u32));
3424 pThis->cas = 0;
3425 break;
3426 }
3427
3428 default:
3429 AssertMsgFailed(("Unhandled NAMWrite offPort=%#x, cb=%u u32=%#x\n", offPort, cb, u32));
3430 break;
3431 }
3432
3433 DEVAC97_UNLOCK(pDevIns, pThis);
3434 return rc;
3435}
3436
3437#ifdef IN_RING3
3438
3439
3440/*********************************************************************************************************************************
3441* State Saving & Loading *
3442*********************************************************************************************************************************/
3443
3444/**
3445 * Saves (serializes) an AC'97 stream using SSM.
3446 *
3447 * @param pDevIns Device instance.
3448 * @param pSSM Saved state manager (SSM) handle to use.
3449 * @param pStream AC'97 stream to save.
3450 */
3451static void ichac97R3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3452{
3453 PAC97BMREGS pRegs = &pStream->Regs;
3454 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3455
3456 pHlp->pfnSSMPutU32(pSSM, pRegs->bdbar);
3457 pHlp->pfnSSMPutU8( pSSM, pRegs->civ);
3458 pHlp->pfnSSMPutU8( pSSM, pRegs->lvi);
3459 pHlp->pfnSSMPutU16(pSSM, pRegs->sr);
3460 pHlp->pfnSSMPutU16(pSSM, pRegs->picb);
3461 pHlp->pfnSSMPutU8( pSSM, pRegs->piv);
3462 pHlp->pfnSSMPutU8( pSSM, pRegs->cr);
3463 pHlp->pfnSSMPutS32(pSSM, pRegs->bd_valid);
3464 pHlp->pfnSSMPutU32(pSSM, pRegs->bd.addr);
3465 pHlp->pfnSSMPutU32(pSSM, pRegs->bd.ctl_len);
3466}
3467
3468/**
3469 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3470 */
3471static DECLCALLBACK(int) ichac97R3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3472{
3473 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3474 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3475 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3476 LogFlowFuncEnter();
3477
3478 pHlp->pfnSSMPutU32(pSSM, pThis->glob_cnt);
3479 pHlp->pfnSSMPutU32(pSSM, pThis->glob_sta);
3480 pHlp->pfnSSMPutU32(pSSM, pThis->cas);
3481
3482 /*
3483 * The order that the streams are saved here is fixed, so don't change.
3484 */
3485 /** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
3486 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3487 ichac97R3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3488
3489 pHlp->pfnSSMPutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3490
3491 /* The stream order is against fixed and set in stone. */
3492 uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3493 afActiveStrms[AC97SOUNDSOURCE_PI_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX]);
3494 afActiveStrms[AC97SOUNDSOURCE_PO_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX]);
3495 afActiveStrms[AC97SOUNDSOURCE_MC_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX]);
3496 AssertCompile(RT_ELEMENTS(afActiveStrms) == 3);
3497 pHlp->pfnSSMPutMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3498
3499 LogFlowFuncLeaveRC(VINF_SUCCESS);
3500 return VINF_SUCCESS;
3501}
3502
3503/**
3504 * Loads an AC'97 stream from SSM.
3505 *
3506 * @returns VBox status code.
3507 * @param pDevIns The device instance.
3508 * @param pSSM Saved state manager (SSM) handle to use.
3509 * @param pStream AC'97 stream to load.
3510 */
3511static int ichac97R3LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3512{
3513 PAC97BMREGS pRegs = &pStream->Regs;
3514 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3515
3516 pHlp->pfnSSMGetU32(pSSM, &pRegs->bdbar);
3517 pHlp->pfnSSMGetU8( pSSM, &pRegs->civ);
3518 pHlp->pfnSSMGetU8( pSSM, &pRegs->lvi);
3519 pHlp->pfnSSMGetU16(pSSM, &pRegs->sr);
3520 pHlp->pfnSSMGetU16(pSSM, &pRegs->picb);
3521 pHlp->pfnSSMGetU8( pSSM, &pRegs->piv);
3522 pHlp->pfnSSMGetU8( pSSM, &pRegs->cr);
3523 pHlp->pfnSSMGetS32(pSSM, &pRegs->bd_valid);
3524 pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.addr);
3525 return pHlp->pfnSSMGetU32(pSSM, &pRegs->bd.ctl_len);
3526}
3527
3528/**
3529 * @callback_method_impl{FNSSMDEVLOADEXEC}
3530 */
3531static DECLCALLBACK(int) ichac97R3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3532{
3533 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3534 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3535 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3536
3537 LogRel2(("ichac97LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3538
3539 AssertMsgReturn (uVersion == AC97_SAVED_STATE_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3540 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3541
3542 pHlp->pfnSSMGetU32(pSSM, &pThis->glob_cnt);
3543 pHlp->pfnSSMGetU32(pSSM, &pThis->glob_sta);
3544 pHlp->pfnSSMGetU32(pSSM, &pThis->cas);
3545
3546 /*
3547 * The order the streams are loaded here is critical (defined by
3548 * AC97SOUNDSOURCE_XX_INDEX), so don't touch!
3549 */
3550 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3551 {
3552 int rc2 = ichac97R3LoadStream(pDevIns, pSSM, &pThis->aStreams[i]);
3553 AssertRCReturn(rc2, rc2);
3554 }
3555
3556 pHlp->pfnSSMGetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3557
3558 ichac97R3MixerRecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
3559 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3560 ichac97MixerGet(pThis, AC97_Master_Volume_Mute));
3561 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT,
3562 ichac97MixerGet(pThis, AC97_PCM_Out_Volume_Mute));
3563 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3564 ichac97MixerGet(pThis, AC97_Line_In_Volume_Mute));
3565 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3566 ichac97MixerGet(pThis, AC97_Mic_Volume_Mute));
3567 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3568 ichac97MixerGet(pThis, AC97_Record_Gain_Mic_Mute));
3569 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3570 ichac97MixerGet(pThis, AC97_Record_Gain_Mute));
3571 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3572 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3573 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3574 ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
3575
3576 /*
3577 * Again the stream order is set is stone.
3578 */
3579 uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3580 int rc2 = pHlp->pfnSSMGetMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3581 AssertRCReturn(rc2, rc2);
3582
3583 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3584 {
3585 const bool fEnable = RT_BOOL(afActiveStrms[i]);
3586 const PAC97STREAM pStream = &pThis->aStreams[i];
3587 const PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[i];
3588
3589 rc2 = ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, fEnable);
3590 AssertRC(rc2);
3591 if ( fEnable
3592 && RT_SUCCESS(rc2))
3593 {
3594 /* Re-arm the timer for this stream. */
3595 /** @todo r=aeichner This causes a VM hang upon saved state resume when NetBSD is used as a guest
3596 * Stopping the timer if cTransferTicks is 0 is a workaround but needs further investigation,
3597 * see @bugref{9759} for more information. */
3598 if (pStreamCC->State.cTransferTicks)
3599 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks);
3600 else
3601 PDMDevHlpTimerStop(pDevIns, pStream->hTimer);
3602 }
3603
3604 /* Keep going. */
3605 }
3606
3607 pThis->bup_flag = 0;
3608 pThis->last_samp = 0;
3609
3610 return VINF_SUCCESS;
3611}
3612
3613
3614/*********************************************************************************************************************************
3615* Debug Info Items *
3616*********************************************************************************************************************************/
3617
3618/** Used by ichac97R3DbgInfoStream and ichac97R3DbgInfoBDL. */
3619static int ichac97R3DbgLookupStrmIdx(PCDBGFINFOHLP pHlp, const char *pszArgs)
3620{
3621 if (pszArgs && *pszArgs)
3622 {
3623 int32_t idxStream;
3624 int rc = RTStrToInt32Full(pszArgs, 0, &idxStream);
3625 if (RT_SUCCESS(rc) && idxStream >= -1 && idxStream < AC97_MAX_STREAMS)
3626 return idxStream;
3627 pHlp->pfnPrintf(pHlp, "Argument '%s' is not a valid stream number!\n", pszArgs);
3628 }
3629 return -1;
3630}
3631
3632
3633/**
3634 * Generic buffer descriptor list dumper.
3635 */
3636static void ichac97R3DbgPrintBdl(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
3637 PCDBGFINFOHLP pHlp, const char *pszPrefix)
3638{
3639 uint8_t const bLvi = pStream->Regs.lvi;
3640 uint8_t const bCiv = pStream->Regs.civ;
3641 pHlp->pfnPrintf(pHlp, "%sBDL for stream #%u: @ %#RX32 LB 0x100; CIV=%#04x LVI=%#04x:\n",
3642 pszPrefix, pStream->u8SD, pStream->Regs.bdbar, bCiv, bLvi);
3643 if (pStream->Regs.bdbar != 0)
3644 {
3645 /* Read all in one go. */
3646 AC97BDLE aBdl[AC97_MAX_BDLE];
3647 RT_ZERO(aBdl);
3648 PDMDevHlpPCIPhysRead(pDevIns, pStream->Regs.bdbar, aBdl, sizeof(aBdl));
3649
3650 /* Get the audio props for the stream so we can translate the sizes correctly. */
3651 PDMAUDIOPCMPROPS Props;
3652 ichach97R3CalcStreamProps(pThis, pStream->u8SD, &Props);
3653
3654 /* Dump them. */
3655 uint64_t cbTotal = 0;
3656 uint64_t cbValid = 0;
3657 for (unsigned i = 0; i < RT_ELEMENTS(aBdl); i++)
3658 {
3659 aBdl[i].addr = RT_LE2H_U32(aBdl[i].addr);
3660 aBdl[i].ctl_len = RT_LE2H_U32(aBdl[i].ctl_len);
3661
3662 bool const fValid = bCiv <= bLvi
3663 ? i >= bCiv && i <= bLvi
3664 : i >= bCiv || i <= bLvi;
3665
3666 uint32_t const cb = (aBdl[i].ctl_len & AC97_BD_LEN_MASK) * PDMAudioPropsSampleSize(&Props); /** @todo or frame size? OSDev says frame... */
3667 cbTotal += cb;
3668 if (fValid)
3669 cbValid += cb;
3670
3671 char szFlags[64];
3672 szFlags[0] = '\0';
3673 if (aBdl[i].ctl_len & ~(AC97_BD_LEN_MASK | AC97_BD_IOC | AC97_BD_BUP))
3674 RTStrPrintf(szFlags, sizeof(szFlags), " !!fFlags=%#x!!\n", aBdl[i].ctl_len & ~AC97_BD_LEN_MASK);
3675
3676 pHlp->pfnPrintf(pHlp, "%s %cBDLE%02u: %#010RX32 L %#06x / LB %#RX32 / %RU64ms%s%s%s%s\n",
3677 pszPrefix, fValid ? ' ' : '?', i, aBdl[i].addr,
3678 aBdl[i].ctl_len & AC97_BD_LEN_MASK, cb, PDMAudioPropsBytesToMilli(&Props, cb),
3679 aBdl[i].ctl_len & AC97_BD_IOC ? " ioc" : "",
3680 aBdl[i].ctl_len & AC97_BD_BUP ? " bup" : "",
3681 szFlags, !(aBdl[i].addr & 3) ? "" : " !!Addr!!");
3682 }
3683
3684 pHlp->pfnPrintf(pHlp, "%sTotal: %#RX64 bytes (%RU64), %RU64 ms; Valid: %#RX64 bytes (%RU64), %RU64 ms\n", pszPrefix,
3685 cbTotal, cbTotal, PDMAudioPropsBytesToMilli(&Props, cbTotal),
3686 cbValid, cbValid, PDMAudioPropsBytesToMilli(&Props, cbValid) );
3687 }
3688}
3689
3690
3691/**
3692 * @callback_method_impl{FNDBGFHANDLERDEV, ac97bdl}
3693 */
3694static DECLCALLBACK(void) ichac97R3DbgInfoBDL(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3695{
3696 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3697 int idxStream = ichac97R3DbgLookupStrmIdx(pHlp, pszArgs);
3698 if (idxStream != -1)
3699 ichac97R3DbgPrintBdl(pDevIns, pThis, &pThis->aStreams[idxStream], pHlp, "");
3700 else
3701 for (idxStream = 0; idxStream < AC97_MAX_STREAMS; ++idxStream)
3702 ichac97R3DbgPrintBdl(pDevIns, pThis, &pThis->aStreams[idxStream], pHlp, "");
3703}
3704
3705
3706/** Worker for ichac97R3DbgInfoStream. */
3707static void ichac97R3DbgPrintStream(PCDBGFINFOHLP pHlp, PAC97STREAM pStream, PAC97STREAMR3 pStreamR3)
3708{
3709 char szTmp[PDMAUDIOSTRMCFGTOSTRING_MAX];
3710 pHlp->pfnPrintf(pHlp, "Stream #%d: %s\n", pStream->u8SD,
3711 PDMAudioStrmCfgToString(&pStreamR3->State.Cfg, szTmp, sizeof(szTmp)));
3712 pHlp->pfnPrintf(pHlp, " BDBAR %#010RX32\n", pStream->Regs.bdbar);
3713 pHlp->pfnPrintf(pHlp, " CIV %#04RX8\n", pStream->Regs.civ);
3714 pHlp->pfnPrintf(pHlp, " LVI %#04RX8\n", pStream->Regs.lvi);
3715 pHlp->pfnPrintf(pHlp, " SR %#06RX16\n", pStream->Regs.sr);
3716 pHlp->pfnPrintf(pHlp, " PICB %#06RX16\n", pStream->Regs.picb);
3717 pHlp->pfnPrintf(pHlp, " PIV %#04RX8\n", pStream->Regs.piv);
3718 pHlp->pfnPrintf(pHlp, " CR %#04RX8\n", pStream->Regs.cr);
3719 if (pStream->Regs.bd_valid)
3720 {
3721 pHlp->pfnPrintf(pHlp, " BD.ADDR %#010RX32\n", pStream->Regs.bd.addr);
3722 pHlp->pfnPrintf(pHlp, " BD.LEN %#04RX16\n", (uint16_t)pStream->Regs.bd.ctl_len);
3723 pHlp->pfnPrintf(pHlp, " BD.CTL %#04RX16\n", (uint16_t)(pStream->Regs.bd.ctl_len >> 16));
3724 }
3725
3726 pHlp->pfnPrintf(pHlp, " offRead %#RX64\n", pStreamR3->State.offRead);
3727 pHlp->pfnPrintf(pHlp, " offWrite %#RX64\n", pStreamR3->State.offWrite);
3728 pHlp->pfnPrintf(pHlp, " uTimerHz %RU16\n", pStreamR3->State.uTimerHz);
3729 pHlp->pfnPrintf(pHlp, " cTransferTicks %RU64\n", pStreamR3->State.cTransferTicks);
3730 pHlp->pfnPrintf(pHlp, " cbTransferChunk %#RX32\n", pStreamR3->State.cbTransferChunk);
3731}
3732
3733
3734/**
3735 * @callback_method_impl{FNDBGFHANDLERDEV, ac97stream}
3736 */
3737static DECLCALLBACK(void) ichac97R3DbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3738{
3739 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3740 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3741 int idxStream = ichac97R3DbgLookupStrmIdx(pHlp, pszArgs);
3742 if (idxStream != -1)
3743 ichac97R3DbgPrintStream(pHlp, &pThis->aStreams[idxStream], &pThisCC->aStreams[idxStream]);
3744 else
3745 for (idxStream = 0; idxStream < AC97_MAX_STREAMS; ++idxStream)
3746 ichac97R3DbgPrintStream(pHlp, &pThis->aStreams[idxStream], &pThisCC->aStreams[idxStream]);
3747}
3748
3749
3750/*********************************************************************************************************************************
3751* PDMIBASE *
3752*********************************************************************************************************************************/
3753
3754/**
3755 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3756 */
3757static DECLCALLBACK(void *) ichac97R3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3758{
3759 PAC97STATER3 pThisCC = RT_FROM_MEMBER(pInterface, AC97STATER3, IBase);
3760 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
3761 return NULL;
3762}
3763
3764
3765/*********************************************************************************************************************************
3766* PDMDEVREG *
3767*********************************************************************************************************************************/
3768
3769/**
3770 * Powers off the device.
3771 *
3772 * @param pDevIns Device instance to power off.
3773 */
3774static DECLCALLBACK(void) ichac97R3PowerOff(PPDMDEVINS pDevIns)
3775{
3776 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3777 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3778
3779 LogRel2(("AC97: Powering off ...\n"));
3780
3781 /* Note: Involves mixer stream / sink destruction, so also do this here
3782 * instead of in ichac97R3Destruct(). */
3783 ichac97R3StreamsDestroy(pDevIns, pThis, pThisCC);
3784
3785 /*
3786 * Note: Destroy the mixer while powering off and *not* in ichac97R3Destruct,
3787 * giving the mixer the chance to release any references held to
3788 * PDM audio streams it maintains.
3789 */
3790 if (pThisCC->pMixer)
3791 {
3792 AudioMixerDestroy(pThisCC->pMixer, pDevIns);
3793 pThisCC->pMixer = NULL;
3794 }
3795}
3796
3797
3798/**
3799 * @interface_method_impl{PDMDEVREG,pfnReset}
3800 *
3801 * @remarks The original sources didn't install a reset handler, but it seems to
3802 * make sense to me so we'll do it.
3803 */
3804static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns)
3805{
3806 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3807 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3808
3809 LogRel(("AC97: Reset\n"));
3810
3811 /*
3812 * Reset the mixer too. The Windows XP driver seems to rely on
3813 * this. At least it wants to read the vendor id before it resets
3814 * the codec manually.
3815 */
3816 ichac97R3MixerReset(pThis, pThisCC);
3817
3818 /*
3819 * Reset all streams.
3820 */
3821 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3822 {
3823 ichac97R3StreamEnable(pDevIns, pThis, pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], false /* fEnable */);
3824 ichac97R3StreamReset(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
3825 }
3826
3827 /*
3828 * Reset mixer sinks.
3829 *
3830 * Do the reset here instead of in ichac97R3StreamReset();
3831 * the mixer sink(s) might still have data to be processed when an audio stream gets reset.
3832 */
3833 AudioMixerSinkReset(pThisCC->pSinkLineIn);
3834 AudioMixerSinkReset(pThisCC->pSinkMicIn);
3835 AudioMixerSinkReset(pThisCC->pSinkOut);
3836}
3837
3838
3839/**
3840 * Worker for ichac97R3Construct() and ichac97R3Attach().
3841 *
3842 * @returns VBox status code.
3843 * @param pDevIns The device instance.
3844 * @param pThisCC The ring-3 AC'97 device state.
3845 * @param iLun The logical unit which is being attached.
3846 * @param ppDrv Attached driver instance on success. Optional.
3847 */
3848static int ichac97R3AttachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned iLun, PAC97DRIVER *ppDrv)
3849{
3850 /*
3851 * Attach driver.
3852 */
3853 char *pszDesc = RTStrAPrintf2("Audio driver port (AC'97) for LUN #%u", iLun);
3854 AssertLogRelReturn(pszDesc, VERR_NO_STR_MEMORY);
3855
3856 PPDMIBASE pDrvBase;
3857 int rc = PDMDevHlpDriverAttach(pDevIns, iLun, &pThisCC->IBase, &pDrvBase, pszDesc);
3858 if (RT_SUCCESS(rc))
3859 {
3860 PAC97DRIVER pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
3861 if (pDrv)
3862 {
3863 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
3864 AssertPtr(pDrv->pConnector);
3865 if (RT_VALID_PTR(pDrv->pConnector))
3866 {
3867 pDrv->pDrvBase = pDrvBase;
3868 pDrv->uLUN = iLun;
3869 pDrv->pszDesc = pszDesc;
3870
3871 /* Attach to driver list if not attached yet. */
3872 if (!pDrv->fAttached)
3873 {
3874 RTListAppend(&pThisCC->lstDrv, &pDrv->Node);
3875 pDrv->fAttached = true;
3876 }
3877
3878 if (ppDrv)
3879 *ppDrv = pDrv;
3880 LogFunc(("LUN#%u: returns VINF_SUCCESS (pCon=%p)\n", iLun, pDrv->pConnector));
3881 return VINF_SUCCESS;
3882 }
3883 RTMemFree(pDrv);
3884 rc = VERR_PDM_MISSING_INTERFACE_BELOW;
3885 }
3886 else
3887 rc = VERR_NO_MEMORY;
3888 }
3889 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3890 LogFunc(("No attached driver for LUN #%u\n", iLun));
3891 else
3892 LogFunc(("Attached driver for LUN #%u failed: %Rrc\n", iLun, rc));
3893
3894 RTStrFree(pszDesc);
3895 LogFunc(("LUN#%u: rc=%Rrc\n", iLun, rc));
3896 return rc;
3897}
3898
3899/**
3900 * @interface_method_impl{PDMDEVREGR3,pfnAttach}
3901 */
3902static DECLCALLBACK(int) ichac97R3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3903{
3904 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3905 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3906 RT_NOREF(fFlags);
3907 LogFunc(("iLUN=%u, fFlags=%#x\n", iLUN, fFlags));
3908
3909 DEVAC97_LOCK(pDevIns, pThis);
3910
3911 PAC97DRIVER pDrv;
3912 int rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLUN, &pDrv);
3913 if (RT_SUCCESS(rc))
3914 {
3915 int rc2 = ichac97R3MixerAddDrv(pDevIns, pThisCC, pDrv);
3916 if (RT_FAILURE(rc2))
3917 LogFunc(("ichac97R3MixerAddDrv failed with %Rrc (ignored)\n", rc2));
3918 }
3919
3920 DEVAC97_UNLOCK(pDevIns, pThis);
3921
3922 return rc;
3923}
3924
3925/**
3926 * Worker for ichac97R3Detach that does all but freeing the pDrv structure.
3927 *
3928 * This is called to let the device detach from a driver for a specified LUN
3929 * at runtime.
3930 *
3931 * @param pDevIns The device instance.
3932 * @param pThisCC The ring-3 AC'97 device state.
3933 * @param pDrv Driver to detach from device.
3934 */
3935static void ichac97R3DetachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
3936{
3937 /* Remove the driver from our list and destory it's associated streams.
3938 This also will un-set the driver as a recording source (if associated). */
3939 ichac97R3MixerRemoveDrv(pDevIns, pThisCC, pDrv);
3940 LogFunc(("Detached LUN#%u\n", pDrv->uLUN));
3941}
3942
3943/**
3944 * @interface_method_impl{PDMDEVREG,pfnDetach}
3945 */
3946static DECLCALLBACK(void) ichac97R3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3947{
3948 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3949 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3950 RT_NOREF(fFlags);
3951
3952 LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
3953
3954 DEVAC97_LOCK(pDevIns, pThis);
3955
3956 PAC97DRIVER pDrv;
3957 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
3958 {
3959 if (pDrv->uLUN == iLUN)
3960 {
3961 ichac97R3DetachInternal(pDevIns, pThisCC, pDrv);
3962 RTStrFree(pDrv->pszDesc);
3963 RTMemFree(pDrv);
3964 DEVAC97_UNLOCK(pDevIns, pThis);
3965 return;
3966 }
3967 }
3968
3969 DEVAC97_UNLOCK(pDevIns, pThis);
3970 LogFunc(("LUN#%u was not found\n", iLUN));
3971}
3972
3973
3974/**
3975 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3976 */
3977static DECLCALLBACK(int) ichac97R3Destruct(PPDMDEVINS pDevIns)
3978{
3979 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
3980 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3981
3982 LogFlowFuncEnter();
3983
3984 PAC97DRIVER pDrv, pDrvNext;
3985 RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
3986 {
3987 RTListNodeRemove(&pDrv->Node);
3988 RTMemFree(pDrv->pszDesc);
3989 RTMemFree(pDrv);
3990 }
3991
3992 /* Sanity. */
3993 Assert(RTListIsEmpty(&pThisCC->lstDrv));
3994
3995 /* We don't always go via PowerOff, so make sure the mixer is destroyed. */
3996 if (pThisCC->pMixer)
3997 {
3998 AudioMixerDestroy(pThisCC->pMixer, pDevIns);
3999 pThisCC->pMixer = NULL;
4000 }
4001
4002 return VINF_SUCCESS;
4003}
4004
4005/**
4006 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4007 */
4008static DECLCALLBACK(int) ichac97R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4009{
4010 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4011 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4012 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4013 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4014 Assert(iInstance == 0); RT_NOREF(iInstance);
4015
4016 /*
4017 * Initialize data so we can run the destructor without scewing up.
4018 */
4019 pThisCC->pDevIns = pDevIns;
4020 pThisCC->IBase.pfnQueryInterface = ichac97R3QueryInterface;
4021 RTListInit(&pThisCC->lstDrv);
4022
4023 /*
4024 * Validate and read configuration.
4025 */
4026 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "BufSizeInMs|BufSizeOutMs|Codec|TimerHz|DebugEnabled|DebugPathOut", "");
4027
4028 /** @devcfgm{ac97,BufSizeInMs,uint16_t,0,2000,0,ms}
4029 * The size of the DMA buffer for input streams expressed in milliseconds. */
4030 int rc = pHlp->pfnCFGMQueryU16Def(pCfg, "BufSizeInMs", &pThis->cMsCircBufIn, 0);
4031 if (RT_FAILURE(rc))
4032 return PDMDEV_SET_ERROR(pDevIns, rc,
4033 N_("AC97 configuration error: failed to read 'BufSizeInMs' as 16-bit unsigned integer"));
4034 if (pThis->cMsCircBufIn > 2000)
4035 return PDMDEV_SET_ERROR(pDevIns, VERR_OUT_OF_RANGE,
4036 N_("AC97 configuration error: 'BufSizeInMs' is out of bound, max 2000 ms"));
4037
4038 /** @devcfgm{ac97,BufSizeOutMs,uint16_t,0,2000,0,ms}
4039 * The size of the DMA buffer for output streams expressed in milliseconds. */
4040 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "BufSizeOutMs", &pThis->cMsCircBufOut, 0);
4041 if (RT_FAILURE(rc))
4042 return PDMDEV_SET_ERROR(pDevIns, rc,
4043 N_("AC97 configuration error: failed to read 'BufSizeOutMs' as 16-bit unsigned integer"));
4044 if (pThis->cMsCircBufOut > 2000)
4045 return PDMDEV_SET_ERROR(pDevIns, VERR_OUT_OF_RANGE,
4046 N_("AC97 configuration error: 'BufSizeOutMs' is out of bound, max 2000 ms"));
4047
4048 /** @devcfgm{ac97,TimerHz,uint16_t,10,1000,100,ms}
4049 * Currently the approximate rate at which the asynchronous I/O threads move
4050 * data from/to the DMA buffer, thru the mixer and drivers stack, and
4051 * to/from the host device/whatever. (It does NOT govern any DMA timer rate any
4052 * more as might be hinted at by the name.) */
4053 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, AC97_TIMER_HZ_DEFAULT);
4054 if (RT_FAILURE(rc))
4055 return PDMDEV_SET_ERROR(pDevIns, rc,
4056 N_("AC'97 configuration error: failed to read 'TimerHz' as a 16-bit unsigned integer"));
4057 if (pThis->uTimerHz < 10 || pThis->uTimerHz > 1000)
4058 return PDMDEV_SET_ERROR(pDevIns, VERR_OUT_OF_RANGE,
4059 N_("AC'97 configuration error: 'TimerHz' is out of range (10-1000 Hz)"));
4060
4061 if (pThis->uTimerHz != AC97_TIMER_HZ_DEFAULT)
4062 LogRel(("AC97: Using custom device timer rate: %RU16 Hz\n", pThis->uTimerHz));
4063
4064 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "DebugEnabled", &pThisCC->Dbg.fEnabled, false);
4065 if (RT_FAILURE(rc))
4066 return PDMDEV_SET_ERROR(pDevIns, rc,
4067 N_("AC97 configuration error: failed to read debugging enabled flag as boolean"));
4068
4069 rc = pHlp->pfnCFGMQueryStringAllocDef(pCfg, "DebugPathOut", &pThisCC->Dbg.pszOutPath, NULL);
4070 if (RT_FAILURE(rc))
4071 return PDMDEV_SET_ERROR(pDevIns, rc,
4072 N_("AC97 configuration error: failed to read debugging output path flag as string"));
4073
4074 if (pThisCC->Dbg.fEnabled)
4075 LogRel2(("AC97: Debug output will be saved to '%s'\n", pThisCC->Dbg.pszOutPath));
4076
4077 /*
4078 * The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
4079 * in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
4080 * 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
4081 */
4082 char szCodec[20];
4083 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
4084 if (RT_FAILURE(rc))
4085 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4086 N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
4087 if (!strcmp(szCodec, "STAC9700"))
4088 pThis->enmCodecModel = AC97CODEC_STAC9700;
4089 else if (!strcmp(szCodec, "AD1980"))
4090 pThis->enmCodecModel = AC97CODEC_AD1980;
4091 else if (!strcmp(szCodec, "AD1981B"))
4092 pThis->enmCodecModel = AC97CODEC_AD1981B;
4093 else
4094 return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
4095 N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"), szCodec);
4096
4097 LogRel(("AC97: Using codec '%s'\n", szCodec));
4098
4099 /*
4100 * Use an own critical section for the device instead of the default
4101 * one provided by PDM. This allows fine-grained locking in combination
4102 * with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4103 */
4104 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "AC'97");
4105 AssertRCReturn(rc, rc);
4106
4107 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4108 AssertRCReturn(rc, rc);
4109
4110 /*
4111 * Initialize data (most of it anyway).
4112 */
4113 /* PCI Device */
4114 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4115 PCIDevSetVendorId(pPciDev, 0x8086); /* 00 ro - intel. */ Assert(pPciDev->abConfig[0x00] == 0x86); Assert(pPciDev->abConfig[0x01] == 0x80);
4116 PCIDevSetDeviceId(pPciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pPciDev->abConfig[0x02] == 0x15); Assert(pPciDev->abConfig[0x03] == 0x24);
4117 PCIDevSetCommand(pPciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pPciDev->abConfig[0x04] == 0x00); Assert(pPciDev->abConfig[0x05] == 0x00);
4118 PCIDevSetStatus(pPciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pPciDev->abConfig[0x06] == 0x80); Assert(pPciDev->abConfig[0x07] == 0x02);
4119 PCIDevSetRevisionId(pPciDev, 0x01); /* 08 ro - rid. */ Assert(pPciDev->abConfig[0x08] == 0x01);
4120 PCIDevSetClassProg(pPciDev, 0x00); /* 09 ro - pi. */ Assert(pPciDev->abConfig[0x09] == 0x00);
4121 PCIDevSetClassSub(pPciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pPciDev->abConfig[0x0a] == 0x01);
4122 PCIDevSetClassBase(pPciDev, 0x04); /* 0b ro - bcc; 04 == multimedia.*/Assert(pPciDev->abConfig[0x0b] == 0x04);
4123 PCIDevSetHeaderType(pPciDev, 0x00); /* 0e ro - headtyp. */ Assert(pPciDev->abConfig[0x0e] == 0x00);
4124 PCIDevSetBaseAddress(pPciDev, 0, /* 10 rw - nambar - native audio mixer base. */
4125 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x10] == 0x01); Assert(pPciDev->abConfig[0x11] == 0x00); Assert(pPciDev->abConfig[0x12] == 0x00); Assert(pPciDev->abConfig[0x13] == 0x00);
4126 PCIDevSetBaseAddress(pPciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
4127 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x14] == 0x01); Assert(pPciDev->abConfig[0x15] == 0x00); Assert(pPciDev->abConfig[0x16] == 0x00); Assert(pPciDev->abConfig[0x17] == 0x00);
4128 PCIDevSetInterruptLine(pPciDev, 0x00); /* 3c rw. */ Assert(pPciDev->abConfig[0x3c] == 0x00);
4129 PCIDevSetInterruptPin(pPciDev, 0x01); /* 3d ro - INTA#. */ Assert(pPciDev->abConfig[0x3d] == 0x01);
4130
4131 if (pThis->enmCodecModel == AC97CODEC_AD1980)
4132 {
4133 PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4134 PCIDevSetSubSystemId(pPciDev, 0x0177); /* 2e ro. */
4135 }
4136 else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
4137 {
4138 PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4139 PCIDevSetSubSystemId(pPciDev, 0x01ad); /* 2e ro. */
4140 }
4141 else
4142 {
4143 PCIDevSetSubSystemVendorId(pPciDev, 0x8086); /* 2c ro - Intel.) */
4144 PCIDevSetSubSystemId(pPciDev, 0x0000); /* 2e ro. */
4145 }
4146
4147 /*
4148 * Register the PCI device and associated I/O regions.
4149 */
4150 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4151 if (RT_FAILURE(rc))
4152 return rc;
4153
4154 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 0 /*iPciRegion*/, 256 /*cPorts*/,
4155 ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /*pvUser*/,
4156 "ICHAC97 NAM", NULL /*paExtDescs*/, &pThis->hIoPortsNam);
4157 AssertRCReturn(rc, rc);
4158
4159 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 1 /*iPciRegion*/, 64 /*cPorts*/,
4160 ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /*pvUser*/,
4161 "ICHAC97 NABM", g_aNabmPorts, &pThis->hIoPortsNabm);
4162 AssertRCReturn(rc, rc);
4163
4164 /*
4165 * Saved state.
4166 */
4167 rc = PDMDevHlpSSMRegister(pDevIns, AC97_SAVED_STATE_VERSION, sizeof(*pThis), ichac97R3SaveExec, ichac97R3LoadExec);
4168 if (RT_FAILURE(rc))
4169 return rc;
4170
4171 /*
4172 * Attach drivers. We ASSUME they are configured consecutively without any
4173 * gaps, so we stop when we hit the first LUN w/o a driver configured.
4174 */
4175 for (unsigned iLun = 0; ; iLun++)
4176 {
4177 AssertBreak(iLun < UINT8_MAX);
4178 LogFunc(("Trying to attach driver for LUN#%u ...\n", iLun));
4179 rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, NULL /* ppDrv */);
4180 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4181 {
4182 LogFunc(("cLUNs=%u\n", iLun));
4183 break;
4184 }
4185 AssertLogRelMsgReturn(RT_SUCCESS(rc), ("LUN#%u: rc=%Rrc\n", iLun, rc), rc);
4186 }
4187
4188 uint32_t fMixer = AUDMIXER_FLAGS_NONE;
4189 if (pThisCC->Dbg.fEnabled)
4190 fMixer |= AUDMIXER_FLAGS_DEBUG;
4191
4192 rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThisCC->pMixer);
4193 AssertRCReturn(rc, rc);
4194
4195 rc = AudioMixerCreateSink(pThisCC->pMixer, "Line In",
4196 PDMAUDIODIR_IN, pDevIns, &pThisCC->pSinkLineIn);
4197 AssertRCReturn(rc, rc);
4198 rc = AudioMixerCreateSink(pThisCC->pMixer, "Microphone In",
4199 PDMAUDIODIR_IN, pDevIns, &pThisCC->pSinkMicIn);
4200 AssertRCReturn(rc, rc);
4201 rc = AudioMixerCreateSink(pThisCC->pMixer, "PCM Output",
4202 PDMAUDIODIR_OUT, pDevIns, &pThisCC->pSinkOut);
4203 AssertRCReturn(rc, rc);
4204
4205 /*
4206 * Create all hardware streams.
4207 */
4208 AssertCompile(RT_ELEMENTS(pThis->aStreams) == AC97_MAX_STREAMS);
4209 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4210 {
4211 rc = ichac97R3StreamCreate(pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], i /* SD# */);
4212 AssertRCReturn(rc, rc);
4213 }
4214
4215 /*
4216 * Create the emulation timers (one per stream).
4217 *
4218 * We must the critical section for the timers as the device has a
4219 * noop section associated with it.
4220 *
4221 * Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's AC'97 driver
4222 * relies on exact (virtual) DMA timing and uses DMA Position Buffers
4223 * instead of the LPIB registers.
4224 */
4225 /** @todo r=bird: The need to use virtual sync is perhaps because TM
4226 * doesn't schedule regular TMCLOCK_VIRTUAL timers as accurately as it
4227 * should (VT-x preemption timer, etc). Hope to address that before
4228 * long. @bugref{9943}. */
4229 static const char * const s_apszNames[] = { "AC97 PI", "AC97 PO", "AC97 MC" };
4230 AssertCompile(RT_ELEMENTS(s_apszNames) == AC97_MAX_STREAMS);
4231 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4232 {
4233 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, ichac97R3Timer, &pThis->aStreams[i],
4234 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, s_apszNames[i], &pThis->aStreams[i].hTimer);
4235 AssertRCReturn(rc, rc);
4236
4237 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->aStreams[i].hTimer, &pThis->CritSect);
4238 AssertRCReturn(rc, rc);
4239 }
4240
4241 ichac97R3Reset(pDevIns);
4242
4243 /*
4244 * Info items.
4245 */
4246 //PDMDevHlpDBGFInfoRegister(pDevIns, "ac97", "AC'97 registers. (ac97 [register case-insensitive])", ichac97R3DbgInfo);
4247 PDMDevHlpDBGFInfoRegister(pDevIns, "ac97bdl", "AC'97 buffer descriptor list (BDL). (ac97bdl [stream number])",
4248 ichac97R3DbgInfoBDL);
4249 PDMDevHlpDBGFInfoRegister(pDevIns, "ac97stream", "AC'97 stream info. (ac97stream [stream number])", ichac97R3DbgInfoStream);
4250 //PDMDevHlpDBGFInfoRegister(pDevIns, "ac97mixer", "AC'97 mixer state.", ichac97R3DbgInfoMixer);
4251
4252 /*
4253 * Register statistics.
4254 */
4255 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmReads, STAMTYPE_COUNTER, "UnimplementedNabmReads", STAMUNIT_OCCURENCES, "Unimplemented NABM register reads.");
4256 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmWrites, STAMTYPE_COUNTER, "UnimplementedNabmWrites", STAMUNIT_OCCURENCES, "Unimplemented NABM register writes.");
4257# ifdef VBOX_WITH_STATISTICS
4258 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
4259 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
4260 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
4261 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "BytesRead" , STAMUNIT_BYTES, "Bytes read from AC97 emulation.");
4262 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "BytesWritten", STAMUNIT_BYTES, "Bytes written to AC97 emulation.");
4263# endif
4264 for (unsigned idxStream = 0; idxStream < RT_ELEMENTS(pThis->aStreams); idxStream++)
4265 {
4266 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.offRead, STAMTYPE_U64, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4267 "Virtual internal buffer read position.", "Stream%u/offRead", idxStream);
4268 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.offWrite, STAMTYPE_U64, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4269 "Virtual internal buffer write position.", "Stream%u/offWrite", idxStream);
4270 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaBufSize, STAMTYPE_U32, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4271 "Size of the internal DMA buffer.", "Stream%u/DMABufSize", idxStream);
4272 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaBufUsed, STAMTYPE_U32, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4273 "Number of bytes used in the internal DMA buffer.", "Stream%u/DMABufUsed", idxStream);
4274 }
4275
4276 LogFlowFuncLeaveRC(VINF_SUCCESS);
4277 return VINF_SUCCESS;
4278}
4279
4280#else /* !IN_RING3 */
4281
4282/**
4283 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4284 */
4285static DECLCALLBACK(int) ichac97RZConstruct(PPDMDEVINS pDevIns)
4286{
4287 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4288 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4289
4290 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4291 AssertRCReturn(rc, rc);
4292
4293 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNam, ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /*pvUser*/);
4294 AssertRCReturn(rc, rc);
4295 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNabm, ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /*pvUser*/);
4296 AssertRCReturn(rc, rc);
4297
4298 return VINF_SUCCESS;
4299}
4300
4301#endif /* !IN_RING3 */
4302
4303/**
4304 * The device registration structure.
4305 */
4306const PDMDEVREG g_DeviceICHAC97 =
4307{
4308 /* .u32Version = */ PDM_DEVREG_VERSION,
4309 /* .uReserved0 = */ 0,
4310 /* .szName = */ "ichac97",
4311 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE
4312 | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION /* stream clearnup with working drivers */,
4313 /* .fClass = */ PDM_DEVREG_CLASS_AUDIO,
4314 /* .cMaxInstances = */ 1,
4315 /* .uSharedVersion = */ 42,
4316 /* .cbInstanceShared = */ sizeof(AC97STATE),
4317 /* .cbInstanceCC = */ CTX_EXPR(sizeof(AC97STATER3), 0, 0),
4318 /* .cbInstanceRC = */ 0,
4319 /* .cMaxPciDevices = */ 1,
4320 /* .cMaxMsixVectors = */ 0,
4321 /* .pszDescription = */ "ICH AC'97 Audio Controller",
4322#if defined(IN_RING3)
4323 /* .pszRCMod = */ "VBoxDDRC.rc",
4324 /* .pszR0Mod = */ "VBoxDDR0.r0",
4325 /* .pfnConstruct = */ ichac97R3Construct,
4326 /* .pfnDestruct = */ ichac97R3Destruct,
4327 /* .pfnRelocate = */ NULL,
4328 /* .pfnMemSetup = */ NULL,
4329 /* .pfnPowerOn = */ NULL,
4330 /* .pfnReset = */ ichac97R3Reset,
4331 /* .pfnSuspend = */ NULL,
4332 /* .pfnResume = */ NULL,
4333 /* .pfnAttach = */ ichac97R3Attach,
4334 /* .pfnDetach = */ ichac97R3Detach,
4335 /* .pfnQueryInterface = */ NULL,
4336 /* .pfnInitComplete = */ NULL,
4337 /* .pfnPowerOff = */ ichac97R3PowerOff,
4338 /* .pfnSoftReset = */ NULL,
4339 /* .pfnReserved0 = */ NULL,
4340 /* .pfnReserved1 = */ NULL,
4341 /* .pfnReserved2 = */ NULL,
4342 /* .pfnReserved3 = */ NULL,
4343 /* .pfnReserved4 = */ NULL,
4344 /* .pfnReserved5 = */ NULL,
4345 /* .pfnReserved6 = */ NULL,
4346 /* .pfnReserved7 = */ NULL,
4347#elif defined(IN_RING0)
4348 /* .pfnEarlyConstruct = */ NULL,
4349 /* .pfnConstruct = */ ichac97RZConstruct,
4350 /* .pfnDestruct = */ NULL,
4351 /* .pfnFinalDestruct = */ NULL,
4352 /* .pfnRequest = */ NULL,
4353 /* .pfnReserved0 = */ NULL,
4354 /* .pfnReserved1 = */ NULL,
4355 /* .pfnReserved2 = */ NULL,
4356 /* .pfnReserved3 = */ NULL,
4357 /* .pfnReserved4 = */ NULL,
4358 /* .pfnReserved5 = */ NULL,
4359 /* .pfnReserved6 = */ NULL,
4360 /* .pfnReserved7 = */ NULL,
4361#elif defined(IN_RC)
4362 /* .pfnConstruct = */ ichac97RZConstruct,
4363 /* .pfnReserved0 = */ NULL,
4364 /* .pfnReserved1 = */ NULL,
4365 /* .pfnReserved2 = */ NULL,
4366 /* .pfnReserved3 = */ NULL,
4367 /* .pfnReserved4 = */ NULL,
4368 /* .pfnReserved5 = */ NULL,
4369 /* .pfnReserved6 = */ NULL,
4370 /* .pfnReserved7 = */ NULL,
4371#else
4372# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4373#endif
4374 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4375};
4376
4377#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4378
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