VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchAc97.cpp@ 98625

Last change on this file since 98625 was 98625, checked in by vboxsync, 2 years ago

DevIchAc97: Locking fix.
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1/* $Id: DevIchAc97.cpp 98625 2023-02-17 21:06:39Z vboxsync $ */
2/** @file
3 * DevIchAc97 - VBox ICH AC97 Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_AC97
33#include <VBox/log.h>
34#include <VBox/vmm/pdmdev.h>
35#include <VBox/vmm/pdmaudioifs.h>
36#include <VBox/vmm/pdmaudioinline.h>
37#include <VBox/AssertGuest.h>
38
39#include <iprt/assert.h>
40#ifdef IN_RING3
41# ifdef DEBUG
42# include <iprt/file.h>
43# endif
44# include <iprt/mem.h>
45# include <iprt/semaphore.h>
46# include <iprt/string.h>
47# include <iprt/uuid.h>
48# include <iprt/zero.h>
49#endif
50
51#include "VBoxDD.h"
52
53#include "AudioMixBuffer.h"
54#include "AudioMixer.h"
55#include "AudioHlp.h"
56
57
58/*********************************************************************************************************************************
59* Defined Constants And Macros *
60*********************************************************************************************************************************/
61/** Current saved state version. */
62#define AC97_SAVED_STATE_VERSION 1
63
64/** Default timer frequency (in Hz). */
65#define AC97_TIMER_HZ_DEFAULT 100
66
67/** Maximum number of streams we support. */
68#define AC97_MAX_STREAMS 3
69
70/** Maximum FIFO size (in bytes) - unused. */
71#define AC97_FIFO_MAX 256
72
73/** @name AC97_SR_XXX - Status Register Bits (AC97_NABM_OFF_SR, PI_SR, PO_SR, MC_SR).
74 * @{ */
75#define AC97_SR_FIFOE RT_BIT(4) /**< rwc, FIFO error. */
76#define AC97_SR_BCIS RT_BIT(3) /**< rwc, Buffer completion interrupt status. */
77#define AC97_SR_LVBCI RT_BIT(2) /**< rwc, Last valid buffer completion interrupt. */
78#define AC97_SR_CELV RT_BIT(1) /**< ro, Current equals last valid. */
79#define AC97_SR_DCH RT_BIT(0) /**< ro, Controller halted. */
80#define AC97_SR_VALID_MASK (RT_BIT(5) - 1)
81#define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)
82#define AC97_SR_RO_MASK (AC97_SR_DCH | AC97_SR_CELV)
83#define AC97_SR_INT_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)
84/** @} */
85
86/** @name AC97_CR_XXX - Control Register Bits (AC97_NABM_OFF_CR, PI_CR, PO_CR, MC_CR).
87 * @{ */
88#define AC97_CR_IOCE RT_BIT(4) /**< rw, Interrupt On Completion Enable. */
89#define AC97_CR_FEIE RT_BIT(3) /**< rw FIFO Error Interrupt Enable. */
90#define AC97_CR_LVBIE RT_BIT(2) /**< rw Last Valid Buffer Interrupt Enable. */
91#define AC97_CR_RR RT_BIT(1) /**< rw Reset Registers. */
92#define AC97_CR_RPBM RT_BIT(0) /**< rw Run/Pause Bus Master. */
93#define AC97_CR_VALID_MASK (RT_BIT(5) - 1)
94#define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE | AC97_CR_FEIE | AC97_CR_LVBIE)
95/** @} */
96
97/** @name AC97_GC_XXX - Global Control Bits (see AC97_GLOB_CNT).
98 * @{ */
99#define AC97_GC_WR 4 /**< rw Warm reset. */
100#define AC97_GC_CR 2 /**< rw Cold reset. */
101#define AC97_GC_VALID_MASK (RT_BIT(6) - 1)
102/** @} */
103
104/** @name AC97_GS_XXX - Global Status Bits (AC97_GLOB_STA).
105 * @{ */
106#define AC97_GS_MD3 RT_BIT(17) /**< rw */
107#define AC97_GS_AD3 RT_BIT(16) /**< rw */
108#define AC97_GS_RCS RT_BIT(15) /**< rwc */
109#define AC97_GS_B3S12 RT_BIT(14) /**< ro */
110#define AC97_GS_B2S12 RT_BIT(13) /**< ro */
111#define AC97_GS_B1S12 RT_BIT(12) /**< ro */
112#define AC97_GS_S1R1 RT_BIT(11) /**< rwc */
113#define AC97_GS_S0R1 RT_BIT(10) /**< rwc */
114#define AC97_GS_S1CR RT_BIT(9) /**< ro */
115#define AC97_GS_S0CR RT_BIT(8) /**< ro */
116#define AC97_GS_MINT RT_BIT(7) /**< ro */
117#define AC97_GS_POINT RT_BIT(6) /**< ro */
118#define AC97_GS_PIINT RT_BIT(5) /**< ro */
119#define AC97_GS_RSRVD (RT_BIT(4) | RT_BIT(3))
120#define AC97_GS_MOINT RT_BIT(2) /**< ro */
121#define AC97_GS_MIINT RT_BIT(1) /**< ro */
122#define AC97_GS_GSCI RT_BIT(0) /**< rwc */
123#define AC97_GS_RO_MASK ( AC97_GS_B3S12 \
124 | AC97_GS_B2S12 \
125 | AC97_GS_B1S12 \
126 | AC97_GS_S1CR \
127 | AC97_GS_S0CR \
128 | AC97_GS_MINT \
129 | AC97_GS_POINT \
130 | AC97_GS_PIINT \
131 | AC97_GS_RSRVD \
132 | AC97_GS_MOINT \
133 | AC97_GS_MIINT)
134#define AC97_GS_VALID_MASK (RT_BIT(18) - 1)
135#define AC97_GS_WCLEAR_MASK (AC97_GS_RCS | AC97_GS_S1R1 | AC97_GS_S0R1 | AC97_GS_GSCI)
136/** @} */
137
138/** @name Buffer Descriptor (BDLE, BDL).
139 * @{ */
140#define AC97_BD_IOC RT_BIT(31) /**< Interrupt on Completion. */
141#define AC97_BD_BUP RT_BIT(30) /**< Buffer Underrun Policy. */
142
143#define AC97_BD_LEN_MASK 0xFFFF /**< Mask for the BDL buffer length. */
144
145#define AC97_BD_LEN_CTL_MBZ UINT32_C(0x3fff0000) /**< Must-be-zero mask for AC97BDLE.ctl_len. */
146
147#define AC97_MAX_BDLE 32 /**< Maximum number of BDLEs. */
148/** @} */
149
150/** @name Extended Audio ID Register (EAID).
151 * @{ */
152#define AC97_EAID_VRA RT_BIT(0) /**< Variable Rate Audio. */
153#define AC97_EAID_VRM RT_BIT(3) /**< Variable Rate Mic Audio. */
154#define AC97_EAID_REV0 RT_BIT(10) /**< AC'97 revision compliance. */
155#define AC97_EAID_REV1 RT_BIT(11) /**< AC'97 revision compliance. */
156/** @} */
157
158/** @name Extended Audio Control and Status Register (EACS).
159 * @{ */
160#define AC97_EACS_VRA RT_BIT(0) /**< Variable Rate Audio (4.2.1.1). */
161#define AC97_EACS_VRM RT_BIT(3) /**< Variable Rate Mic Audio (4.2.1.1). */
162/** @} */
163
164/** @name Baseline Audio Register Set (BARS).
165 * @{ */
166#define AC97_BARS_VOL_MASK 0x1f /**< Volume mask for the Baseline Audio Register Set (5.7.2). */
167#define AC97_BARS_GAIN_MASK 0x0f /**< Gain mask for the Baseline Audio Register Set. */
168#define AC97_BARS_VOL_MUTE_SHIFT 15 /**< Mute bit shift for the Baseline Audio Register Set (5.7.2). */
169/** @} */
170
171/** AC'97 uses 1.5dB steps, we use 0.375dB steps: 1 AC'97 step equals 4 PDM steps. */
172#define AC97_DB_FACTOR 4
173
174/** @name Recording inputs?
175 * @{ */
176#define AC97_REC_MIC UINT8_C(0)
177#define AC97_REC_CD UINT8_C(1)
178#define AC97_REC_VIDEO UINT8_C(2)
179#define AC97_REC_AUX UINT8_C(3)
180#define AC97_REC_LINE_IN UINT8_C(4)
181#define AC97_REC_STEREO_MIX UINT8_C(5)
182#define AC97_REC_MONO_MIX UINT8_C(6)
183#define AC97_REC_PHONE UINT8_C(7)
184#define AC97_REC_MASK UINT8_C(7)
185/** @} */
186
187/** @name Mixer registers / NAM BAR registers?
188 * @{ */
189#define AC97_Reset 0x00
190#define AC97_Master_Volume_Mute 0x02
191#define AC97_Headphone_Volume_Mute 0x04 /**< Also known as AUX, see table 16, section 5.7. */
192#define AC97_Master_Volume_Mono_Mute 0x06
193#define AC97_Master_Tone_RL 0x08
194#define AC97_PC_BEEP_Volume_Mute 0x0a
195#define AC97_Phone_Volume_Mute 0x0c
196#define AC97_Mic_Volume_Mute 0x0e
197#define AC97_Line_In_Volume_Mute 0x10
198#define AC97_CD_Volume_Mute 0x12
199#define AC97_Video_Volume_Mute 0x14
200#define AC97_Aux_Volume_Mute 0x16
201#define AC97_PCM_Out_Volume_Mute 0x18
202#define AC97_Record_Select 0x1a
203#define AC97_Record_Gain_Mute 0x1c
204#define AC97_Record_Gain_Mic_Mute 0x1e
205#define AC97_General_Purpose 0x20
206#define AC97_3D_Control 0x22
207#define AC97_AC_97_RESERVED 0x24
208#define AC97_Powerdown_Ctrl_Stat 0x26
209#define AC97_Extended_Audio_ID 0x28
210#define AC97_Extended_Audio_Ctrl_Stat 0x2a
211#define AC97_PCM_Front_DAC_Rate 0x2c
212#define AC97_PCM_Surround_DAC_Rate 0x2e
213#define AC97_PCM_LFE_DAC_Rate 0x30
214#define AC97_PCM_LR_ADC_Rate 0x32
215#define AC97_MIC_ADC_Rate 0x34
216#define AC97_6Ch_Vol_C_LFE_Mute 0x36
217#define AC97_6Ch_Vol_L_R_Surround_Mute 0x38
218#define AC97_Vendor_Reserved 0x58
219#define AC97_AD_Misc 0x76
220#define AC97_Vendor_ID1 0x7c
221#define AC97_Vendor_ID2 0x7e
222/** @} */
223
224/** @name Analog Devices miscellaneous regiter bits used in AD1980.
225 * @{ */
226#define AC97_AD_MISC_LOSEL RT_BIT(5) /**< Surround (rear) goes to line out outputs. */
227#define AC97_AD_MISC_HPSEL RT_BIT(10) /**< PCM (front) goes to headphone outputs. */
228/** @} */
229
230
231/** @name BUP flag values.
232 * @{ */
233#define BUP_SET RT_BIT_32(0)
234#define BUP_LAST RT_BIT_32(1)
235/** @} */
236
237/** @name AC'97 source indices.
238 * @note The order of these indices is fixed (also applies for saved states) for
239 * the moment. So make sure you know what you're done when altering this!
240 * @{
241 */
242#define AC97SOUNDSOURCE_PI_INDEX 0 /**< PCM in */
243#define AC97SOUNDSOURCE_PO_INDEX 1 /**< PCM out */
244#define AC97SOUNDSOURCE_MC_INDEX 2 /**< Mic in */
245#define AC97SOUNDSOURCE_MAX 3 /**< Max sound sources. */
246/** @} */
247
248/** Port number (offset into NABM BAR) to stream index. */
249#define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
250/** Port number (offset into NABM BAR) to stream index, but no masking. */
251#define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
252
253/** @name Stream offsets
254 * @{ */
255#define AC97_NABM_OFF_BDBAR 0x0 /**< Buffer Descriptor Base Address */
256#define AC97_NABM_OFF_CIV 0x4 /**< Current Index Value */
257#define AC97_NABM_OFF_LVI 0x5 /**< Last Valid Index */
258#define AC97_NABM_OFF_SR 0x6 /**< Status Register */
259#define AC97_NABM_OFF_PICB 0x8 /**< Position in Current Buffer */
260#define AC97_NABM_OFF_PIV 0xa /**< Prefetched Index Value */
261#define AC97_NABM_OFF_CR 0xb /**< Control Register */
262#define AC97_NABM_OFF_MASK 0xf /**< Mask for getting the the per-stream register. */
263/** @} */
264
265
266/** @name PCM in NABM BAR registers (0x00..0x0f).
267 * @{ */
268#define PI_BDBAR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x0) /**< PCM in: Buffer Descriptor Base Address */
269#define PI_CIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x4) /**< PCM in: Current Index Value */
270#define PI_LVI (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x5) /**< PCM in: Last Valid Index */
271#define PI_SR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x6) /**< PCM in: Status Register */
272#define PI_PICB (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0x8) /**< PCM in: Position in Current Buffer */
273#define PI_PIV (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xa) /**< PCM in: Prefetched Index Value */
274#define PI_CR (AC97SOUNDSOURCE_PI_INDEX * 0x10 + 0xb) /**< PCM in: Control Register */
275/** @} */
276
277/** @name PCM out NABM BAR registers (0x10..0x1f).
278 * @{ */
279#define PO_BDBAR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x0) /**< PCM out: Buffer Descriptor Base Address */
280#define PO_CIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x4) /**< PCM out: Current Index Value */
281#define PO_LVI (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x5) /**< PCM out: Last Valid Index */
282#define PO_SR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x6) /**< PCM out: Status Register */
283#define PO_PICB (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0x8) /**< PCM out: Position in Current Buffer */
284#define PO_PIV (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xa) /**< PCM out: Prefetched Index Value */
285#define PO_CR (AC97SOUNDSOURCE_PO_INDEX * 0x10 + 0xb) /**< PCM out: Control Register */
286/** @} */
287
288/** @name Mic in NABM BAR registers (0x20..0x2f).
289 * @{ */
290#define MC_BDBAR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x0) /**< PCM in: Buffer Descriptor Base Address */
291#define MC_CIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x4) /**< PCM in: Current Index Value */
292#define MC_LVI (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x5) /**< PCM in: Last Valid Index */
293#define MC_SR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x6) /**< PCM in: Status Register */
294#define MC_PICB (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0x8) /**< PCM in: Position in Current Buffer */
295#define MC_PIV (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xa) /**< PCM in: Prefetched Index Value */
296#define MC_CR (AC97SOUNDSOURCE_MC_INDEX * 0x10 + 0xb) /**< PCM in: Control Register */
297/** @} */
298
299/** @name Misc NABM BAR registers.
300 * @{ */
301/** NABMBAR: Global Control Register.
302 * @note This is kind of in the MIC IN area. */
303#define AC97_GLOB_CNT 0x2c
304/** NABMBAR: Global Status. */
305#define AC97_GLOB_STA 0x30
306/** Codec Access Semaphore Register. */
307#define AC97_CAS 0x34
308/** @} */
309
310
311/*********************************************************************************************************************************
312* Structures and Typedefs *
313*********************************************************************************************************************************/
314/** The ICH AC'97 (Intel) controller (shared). */
315typedef struct AC97STATE *PAC97STATE;
316/** The ICH AC'97 (Intel) controller (ring-3). */
317typedef struct AC97STATER3 *PAC97STATER3;
318
319/**
320 * Buffer Descriptor List Entry (BDLE).
321 *
322 * (See section 3.2.1 in Intel document number 252751-001, or section 1.2.2.1 in
323 * Intel document number 302349-003.)
324 */
325typedef struct AC97BDLE
326{
327 /** Location of data buffer (bits 31:1). */
328 uint32_t addr;
329 /** Flags (bits 31 + 30) and length (bits 15:0) of data buffer (in audio samples).
330 * @todo split up into two 16-bit fields. */
331 uint32_t ctl_len;
332} AC97BDLE;
333AssertCompileSize(AC97BDLE, 8);
334/** Pointer to BDLE. */
335typedef AC97BDLE *PAC97BDLE;
336
337/**
338 * Bus master register set for an audio stream.
339 *
340 * (See section 16.2 in Intel document 301473-002, or section 2.2 in Intel
341 * document 302349-003.)
342 */
343typedef struct AC97BMREGS
344{
345 uint32_t bdbar; /**< rw 0, Buffer Descriptor List: BAR (Base Address Register). */
346 uint8_t civ; /**< ro 0, Current index value. */
347 uint8_t lvi; /**< rw 0, Last valid index. */
348 uint16_t sr; /**< rw 1, Status register. */
349 uint16_t picb; /**< ro 0, Position in current buffer (samples left to process). */
350 uint8_t piv; /**< ro 0, Prefetched index value. */
351 uint8_t cr; /**< rw 0, Control register. */
352 int32_t bd_valid; /**< Whether current BDLE is initialized or not. */
353 AC97BDLE bd; /**< Current Buffer Descriptor List Entry (BDLE). */
354} AC97BMREGS;
355AssertCompileSizeAlignment(AC97BMREGS, 8);
356/** Pointer to the BM registers of an audio stream. */
357typedef AC97BMREGS *PAC97BMREGS;
358
359/**
360 * The internal state of an AC'97 stream.
361 */
362typedef struct AC97STREAMSTATE
363{
364 /** Critical section for this stream. */
365 RTCRITSECT CritSect;
366 /** Circular buffer (FIFO) for holding DMA'ed data. */
367 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
368#if HC_ARCH_BITS == 32
369 uint32_t Padding;
370#endif
371 /** Current circular buffer read offset (for tracing & logging). */
372 uint64_t offRead;
373 /** Current circular buffer write offset (for tracing & logging). */
374 uint64_t offWrite;
375 /** The stream's current configuration. */
376 PDMAUDIOSTREAMCFG Cfg; //+108
377 /** Timestamp of the last DMA data transfer. */
378 uint64_t tsTransferLast;
379 /** Timestamp of the next DMA data transfer.
380 * Next for determining the next scheduling window.
381 * Can be 0 if no next transfer is scheduled. */
382 uint64_t tsTransferNext;
383 /** The stream's timer Hz rate.
384 * This value can can be different from the device's default Hz rate,
385 * depending on the rate the stream expects (e.g. for 5.1 speaker setups).
386 * Set in R3StreamInit(). */
387 uint16_t uTimerHz;
388 /** Set if we've registered the asynchronous update job. */
389 bool fRegisteredAsyncUpdateJob;
390 /** Input streams only: Set when we switch from feeding the guest silence and
391 * commits to proving actual audio input bytes. */
392 bool fInputPreBuffered;
393 /** This is ZERO if stream setup succeeded, otherwise it's the RTTimeNanoTS() at
394 * which to retry setting it up. The latter applies only to same
395 * parameters. */
396 uint64_t nsRetrySetup;
397 /** Timestamp (in ns) of last stream update. */
398 uint64_t tsLastUpdateNs;
399
400 /** Size of the DMA buffer (pCircBuf) in bytes. */
401 uint32_t StatDmaBufSize;
402 /** Number of used bytes in the DMA buffer (pCircBuf). */
403 uint32_t StatDmaBufUsed;
404 /** Counter for all under/overflows problems. */
405 STAMCOUNTER StatDmaFlowProblems;
406 /** Counter for unresovled under/overflows problems. */
407 STAMCOUNTER StatDmaFlowErrors;
408 /** Number of bytes involved in unresolved flow errors. */
409 STAMCOUNTER StatDmaFlowErrorBytes;
410 STAMCOUNTER StatDmaSkippedDch;
411 STAMCOUNTER StatDmaSkippedPendingBcis;
412 STAMPROFILE StatStart;
413 STAMPROFILE StatReset;
414 STAMPROFILE StatStop;
415 STAMPROFILE StatReSetUpChanged;
416 STAMPROFILE StatReSetUpSame;
417 STAMCOUNTER StatWriteLviRecover;
418 STAMCOUNTER StatWriteCr;
419} AC97STREAMSTATE;
420AssertCompileSizeAlignment(AC97STREAMSTATE, 8);
421/** Pointer to internal state of an AC'97 stream. */
422typedef AC97STREAMSTATE *PAC97STREAMSTATE;
423
424/**
425 * Runtime configurable debug stuff for an AC'97 stream.
426 */
427typedef struct AC97STREAMDEBUGRT
428{
429 /** Whether debugging is enabled or not. */
430 bool fEnabled;
431 uint8_t Padding[7];
432 /** File for dumping stream reads / writes.
433 * For input streams, this dumps data being written to the device FIFO,
434 * whereas for output streams this dumps data being read from the device FIFO. */
435 R3PTRTYPE(PAUDIOHLPFILE) pFileStream;
436 /** File for dumping DMA reads / writes.
437 * For input streams, this dumps data being written to the device DMA,
438 * whereas for output streams this dumps data being read from the device DMA. */
439 R3PTRTYPE(PAUDIOHLPFILE) pFileDMA;
440} AC97STREAMDEBUGRT;
441
442/**
443 * Debug stuff for an AC'97 stream.
444 */
445typedef struct AC97STREAMDEBUG
446{
447 /** Runtime debug stuff. */
448 AC97STREAMDEBUGRT Runtime;
449} AC97STREAMDEBUG;
450
451/**
452 * The shared AC'97 stream state.
453 */
454typedef struct AC97STREAM
455{
456 /** Bus master registers of this stream. */
457 AC97BMREGS Regs;
458 /** Stream number (SDn). */
459 uint8_t u8SD;
460 uint8_t abPadding0[7];
461
462 /** The timer for pumping data thru the attached LUN drivers. */
463 TMTIMERHANDLE hTimer;
464 /** When the timer was armed (timer clock). */
465 uint64_t uArmedTs;
466 /** (Virtual) clock ticks per transfer. */
467 uint64_t cDmaPeriodTicks;
468 /** Transfer chunk size (in bytes) of a transfer period. */
469 uint32_t cbDmaPeriod;
470 /** DMA period counter (for logging). */
471 uint32_t uDmaPeriod;
472
473 STAMCOUNTER StatWriteLvi;
474 STAMCOUNTER StatWriteSr1;
475 STAMCOUNTER StatWriteSr2;
476 STAMCOUNTER StatWriteBdBar;
477} AC97STREAM;
478AssertCompileSizeAlignment(AC97STREAM, 8);
479/** Pointer to a shared AC'97 stream state. */
480typedef AC97STREAM *PAC97STREAM;
481
482
483/**
484 * The ring-3 AC'97 stream state.
485 */
486typedef struct AC97STREAMR3
487{
488 /** Stream number (SDn). */
489 uint8_t u8SD;
490 uint8_t abPadding0[7];
491 /** Internal state of this stream. */
492 AC97STREAMSTATE State;
493 /** Debug stuff. */
494 AC97STREAMDEBUG Dbg;
495} AC97STREAMR3;
496AssertCompileSizeAlignment(AC97STREAMR3, 8);
497/** Pointer to an AC'97 stream state for ring-3. */
498typedef AC97STREAMR3 *PAC97STREAMR3;
499
500
501/**
502 * A driver stream (host backend).
503 *
504 * Each driver has its own instances of audio mixer streams, which then
505 * can go into the same (or even different) audio mixer sinks.
506 */
507typedef struct AC97DRIVERSTREAM
508{
509 /** Associated mixer stream handle. */
510 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
511} AC97DRIVERSTREAM;
512/** Pointer to a driver stream. */
513typedef AC97DRIVERSTREAM *PAC97DRIVERSTREAM;
514
515/**
516 * A host backend driver (LUN).
517 */
518typedef struct AC97DRIVER
519{
520 /** Node for storing this driver in our device driver list of AC97STATE. */
521 RTLISTNODER3 Node;
522 /** LUN # to which this driver has been assigned. */
523 uint8_t uLUN;
524 /** Whether this driver is in an attached state or not. */
525 bool fAttached;
526 uint8_t abPadding[6];
527 /** Pointer to attached driver base interface. */
528 R3PTRTYPE(PPDMIBASE) pDrvBase;
529 /** Audio connector interface to the underlying host backend. */
530 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
531 /** Driver stream for line input. */
532 AC97DRIVERSTREAM LineIn;
533 /** Driver stream for mic input. */
534 AC97DRIVERSTREAM MicIn;
535 /** Driver stream for output. */
536 AC97DRIVERSTREAM Out;
537 /** The LUN description. */
538 char szDesc[48 - 2];
539} AC97DRIVER;
540/** Pointer to a host backend driver (LUN). */
541typedef AC97DRIVER *PAC97DRIVER;
542
543/**
544 * Debug settings.
545 */
546typedef struct AC97STATEDEBUG
547{
548 /** Whether debugging is enabled or not. */
549 bool fEnabled;
550 bool afAlignment[7];
551 /** Path where to dump the debug output to.
552 * Can be NULL, in which the system's temporary directory will be used then. */
553 R3PTRTYPE(char *) pszOutPath;
554} AC97STATEDEBUG;
555
556
557/* Codec models. */
558typedef enum AC97CODEC
559{
560 AC97CODEC_INVALID = 0, /**< Customary illegal zero value. */
561 AC97CODEC_STAC9700, /**< SigmaTel STAC9700 */
562 AC97CODEC_AD1980, /**< Analog Devices AD1980 */
563 AC97CODEC_AD1981B, /**< Analog Devices AD1981B */
564 AC97CODEC_32BIT_HACK = 0x7fffffff
565} AC97CODEC;
566
567
568/**
569 * The shared AC'97 device state.
570 */
571typedef struct AC97STATE
572{
573 /** Critical section protecting the AC'97 state. */
574 PDMCRITSECT CritSect;
575 /** Global Control (Bus Master Control Register). */
576 uint32_t glob_cnt;
577 /** Global Status (Bus Master Control Register). */
578 uint32_t glob_sta;
579 /** Codec Access Semaphore Register (Bus Master Control Register). */
580 uint32_t cas;
581 uint32_t last_samp;
582 uint8_t mixer_data[256];
583 /** Array of AC'97 streams (parallel to AC97STATER3::aStreams). */
584 AC97STREAM aStreams[AC97_MAX_STREAMS];
585 /** The device timer Hz rate. Defaults to AC97_TIMER_HZ_DEFAULT_DEFAULT. */
586 uint16_t uTimerHz;
587 /** Config: Internal input DMA buffer size override, specified in milliseconds.
588 * Zero means default size according to buffer and stream config.
589 * @sa BufSizeInMs config value. */
590 uint16_t cMsCircBufIn;
591 /** Config: Internal output DMA buffer size override, specified in milliseconds.
592 * Zero means default size according to buffer and stream config.
593 * @sa BufSizeOutMs config value. */
594 uint16_t cMsCircBufOut;
595 uint16_t au16Padding1[1];
596 uint8_t silence[128];
597 uint32_t bup_flag;
598 /** Codec model. */
599 AC97CODEC enmCodecModel;
600
601 /** PCI region \#0: NAM I/O ports. */
602 IOMIOPORTHANDLE hIoPortsNam;
603 /** PCI region \#0: NANM I/O ports. */
604 IOMIOPORTHANDLE hIoPortsNabm;
605
606 STAMCOUNTER StatUnimplementedNabmReads;
607 STAMCOUNTER StatUnimplementedNabmWrites;
608 STAMCOUNTER StatUnimplementedNamReads;
609 STAMCOUNTER StatUnimplementedNamWrites;
610#ifdef VBOX_WITH_STATISTICS
611 STAMPROFILE StatTimer;
612#endif
613} AC97STATE;
614AssertCompileMemberAlignment(AC97STATE, aStreams, 8);
615AssertCompileMemberAlignment(AC97STATE, StatUnimplementedNabmReads, 8);
616
617
618/**
619 * The ring-3 AC'97 device state.
620 */
621typedef struct AC97STATER3
622{
623 /** Array of AC'97 streams (parallel to AC97STATE:aStreams). */
624 AC97STREAMR3 aStreams[AC97_MAX_STREAMS];
625 /** R3 pointer to the device instance. */
626 PPDMDEVINSR3 pDevIns;
627 /** List of associated LUN drivers (AC97DRIVER). */
628 RTLISTANCHORR3 lstDrv;
629 /** The device's software mixer. */
630 R3PTRTYPE(PAUDIOMIXER) pMixer;
631 /** Audio sink for PCM output. */
632 R3PTRTYPE(PAUDMIXSINK) pSinkOut;
633 /** Audio sink for line input. */
634 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
635 /** Audio sink for microphone input. */
636 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
637 /** The base interface for LUN\#0. */
638 PDMIBASE IBase;
639 /** Debug settings. */
640 AC97STATEDEBUG Dbg;
641} AC97STATER3;
642AssertCompileMemberAlignment(AC97STATER3, aStreams, 8);
643/** Pointer to the ring-3 AC'97 device state. */
644typedef AC97STATER3 *PAC97STATER3;
645
646
647/**
648 * Acquires the AC'97 lock.
649 */
650#define DEVAC97_LOCK(a_pDevIns, a_pThis) \
651 do { \
652 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
653 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), &(a_pThis)->CritSect, rcLock); \
654 } while (0)
655
656/**
657 * Acquires the AC'97 lock or returns.
658 */
659# define DEVAC97_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
660 do { \
661 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, a_rcBusy); \
662 if (rcLock == VINF_SUCCESS) \
663 { /* likely */ } \
664 else \
665 { \
666 AssertRC(rcLock); \
667 return rcLock; \
668 } \
669 } while (0)
670
671/**
672 * Releases the AC'97 lock.
673 */
674#define DEVAC97_UNLOCK(a_pDevIns, a_pThis) \
675 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
676
677
678#ifndef VBOX_DEVICE_STRUCT_TESTCASE
679
680
681/*********************************************************************************************************************************
682* Internal Functions *
683*********************************************************************************************************************************/
684static void ichac97StreamUpdateSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr);
685static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t uMixerIdx);
686#ifdef IN_RING3
687DECLINLINE(void) ichac97R3StreamLock(PAC97STREAMR3 pStreamCC);
688DECLINLINE(void) ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC);
689static void ichac97R3DbgPrintBdl(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
690 PCDBGFINFOHLP pHlp, const char *pszPrefix);
691static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns);
692#endif
693
694
695/*********************************************************************************************************************************
696* Global Variables *
697*********************************************************************************************************************************/
698#ifdef IN_RING3
699/** NABM I/O port descriptions. */
700static const IOMIOPORTDESC g_aNabmPorts[] =
701{
702 { "PCM IN - BDBAR", "PCM IN - BDBAR", NULL, NULL },
703 { "", NULL, NULL, NULL },
704 { "", NULL, NULL, NULL },
705 { "", NULL, NULL, NULL },
706 { "PCM IN - CIV", "PCM IN - CIV", NULL, NULL },
707 { "PCM IN - LVI", "PCM IN - LIV", NULL, NULL },
708 { "PCM IN - SR", "PCM IN - SR", NULL, NULL },
709 { "", NULL, NULL, NULL },
710 { "PCM IN - PICB", "PCM IN - PICB", NULL, NULL },
711 { "", NULL, NULL, NULL },
712 { "PCM IN - PIV", "PCM IN - PIV", NULL, NULL },
713 { "PCM IN - CR", "PCM IN - CR", NULL, NULL },
714 { "", NULL, NULL, NULL },
715 { "", NULL, NULL, NULL },
716 { "", NULL, NULL, NULL },
717 { "", NULL, NULL, NULL },
718
719 { "PCM OUT - BDBAR", "PCM OUT - BDBAR", NULL, NULL },
720 { "", NULL, NULL, NULL },
721 { "", NULL, NULL, NULL },
722 { "", NULL, NULL, NULL },
723 { "PCM OUT - CIV", "PCM OUT - CIV", NULL, NULL },
724 { "PCM OUT - LVI", "PCM OUT - LIV", NULL, NULL },
725 { "PCM OUT - SR", "PCM OUT - SR", NULL, NULL },
726 { "", NULL, NULL, NULL },
727 { "PCM OUT - PICB", "PCM OUT - PICB", NULL, NULL },
728 { "", NULL, NULL, NULL },
729 { "PCM OUT - PIV", "PCM OUT - PIV", NULL, NULL },
730 { "PCM OUT - CR", "PCM IN - CR", NULL, NULL },
731 { "", NULL, NULL, NULL },
732 { "", NULL, NULL, NULL },
733 { "", NULL, NULL, NULL },
734 { "", NULL, NULL, NULL },
735
736 { "MIC IN - BDBAR", "MIC IN - BDBAR", NULL, NULL },
737 { "", NULL, NULL, NULL },
738 { "", NULL, NULL, NULL },
739 { "", NULL, NULL, NULL },
740 { "MIC IN - CIV", "MIC IN - CIV", NULL, NULL },
741 { "MIC IN - LVI", "MIC IN - LIV", NULL, NULL },
742 { "MIC IN - SR", "MIC IN - SR", NULL, NULL },
743 { "", NULL, NULL, NULL },
744 { "MIC IN - PICB", "MIC IN - PICB", NULL, NULL },
745 { "", NULL, NULL, NULL },
746 { "MIC IN - PIV", "MIC IN - PIV", NULL, NULL },
747 { "MIC IN - CR", "MIC IN - CR", NULL, NULL },
748 { "GLOB CNT", "GLOB CNT", NULL, NULL },
749 { "", NULL, NULL, NULL },
750 { "", NULL, NULL, NULL },
751 { "", NULL, NULL, NULL },
752
753 { "GLOB STA", "GLOB STA", NULL, NULL },
754 { "", NULL, NULL, NULL },
755 { "", NULL, NULL, NULL },
756 { "", NULL, NULL, NULL },
757 { "CAS", "CAS", NULL, NULL },
758 { NULL, NULL, NULL, NULL },
759};
760
761/** @name Source indices
762 * @{ */
763# define AC97SOUNDSOURCE_PI_INDEX 0 /**< PCM in */
764# define AC97SOUNDSOURCE_PO_INDEX 1 /**< PCM out */
765# define AC97SOUNDSOURCE_MC_INDEX 2 /**< Mic in */
766# define AC97SOUNDSOURCE_MAX 3 /**< Max sound sources. */
767/** @} */
768
769/** Port number (offset into NABM BAR) to stream index. */
770# define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 )
771/** Port number (offset into NABM BAR) to stream index, but no masking. */
772# define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) )
773
774/** @name Stream offsets
775 * @{ */
776# define AC97_NABM_OFF_BDBAR 0x0 /**< Buffer Descriptor Base Address */
777# define AC97_NABM_OFF_CIV 0x4 /**< Current Index Value */
778# define AC97_NABM_OFF_LVI 0x5 /**< Last Valid Index */
779# define AC97_NABM_OFF_SR 0x6 /**< Status Register */
780# define AC97_NABM_OFF_PICB 0x8 /**< Position in Current Buffer */
781# define AC97_NABM_OFF_PIV 0xa /**< Prefetched Index Value */
782# define AC97_NABM_OFF_CR 0xb /**< Control Register */
783# define AC97_NABM_OFF_MASK 0xf /**< Mask for getting the the per-stream register. */
784/** @} */
785
786#endif /* IN_RING3 */
787
788
789
790static void ichac97WarmReset(PAC97STATE pThis)
791{
792 NOREF(pThis);
793}
794
795static void ichac97ColdReset(PAC97STATE pThis)
796{
797 NOREF(pThis);
798}
799
800
801#ifdef IN_RING3
802
803/**
804 * Returns the audio direction of a specified stream descriptor.
805 *
806 * @return Audio direction.
807 */
808DECLINLINE(PDMAUDIODIR) ichac97R3GetDirFromSD(uint8_t uSD)
809{
810 switch (uSD)
811 {
812 case AC97SOUNDSOURCE_PI_INDEX: return PDMAUDIODIR_IN;
813 case AC97SOUNDSOURCE_PO_INDEX: return PDMAUDIODIR_OUT;
814 case AC97SOUNDSOURCE_MC_INDEX: return PDMAUDIODIR_IN;
815 }
816
817 AssertFailed();
818 return PDMAUDIODIR_UNKNOWN;
819}
820
821
822/**
823 * Retrieves the audio mixer sink of a corresponding AC'97 stream index.
824 *
825 * @returns Pointer to audio mixer sink if found, or NULL if not found / invalid.
826 * @param pThisCC The ring-3 AC'97 state.
827 * @param uIndex Stream index to get audio mixer sink for.
828 */
829DECLINLINE(PAUDMIXSINK) ichac97R3IndexToSink(PAC97STATER3 pThisCC, uint8_t uIndex)
830{
831 switch (uIndex)
832 {
833 case AC97SOUNDSOURCE_PI_INDEX: return pThisCC->pSinkLineIn;
834 case AC97SOUNDSOURCE_PO_INDEX: return pThisCC->pSinkOut;
835 case AC97SOUNDSOURCE_MC_INDEX: return pThisCC->pSinkMicIn;
836 default:
837 AssertMsgFailedReturn(("Wrong index %RU8\n", uIndex), NULL);
838 }
839}
840
841
842/*********************************************************************************************************************************
843* Stream DMA *
844*********************************************************************************************************************************/
845
846/**
847 * Retrieves the available size of (buffered) audio data (in bytes) of a given AC'97 stream.
848 *
849 * @returns Available data (in bytes).
850 * @param pStreamCC The AC'97 stream to retrieve size for (ring-3).
851 */
852DECLINLINE(uint32_t) ichac97R3StreamGetUsed(PAC97STREAMR3 pStreamCC)
853{
854 PRTCIRCBUF const pCircBuf = pStreamCC->State.pCircBuf;
855 if (pCircBuf)
856 return (uint32_t)RTCircBufUsed(pCircBuf);
857 return 0;
858}
859
860
861/**
862 * Retrieves the free size of audio data (in bytes) of a given AC'97 stream.
863 *
864 * @returns Free data (in bytes).
865 * @param pStreamCC AC'97 stream to retrieve size for (ring-3).
866 */
867DECLINLINE(uint32_t) ichac97R3StreamGetFree(PAC97STREAMR3 pStreamCC)
868{
869 PRTCIRCBUF const pCircBuf = pStreamCC->State.pCircBuf;
870 if (pCircBuf)
871 return (uint32_t)RTCircBufFree(pCircBuf);
872 return 0;
873}
874
875
876# if 0 /* Unused */
877static void ichac97R3WriteBUP(PAC97STATE pThis, uint32_t cbElapsed)
878{
879 LogFlowFunc(("cbElapsed=%RU32\n", cbElapsed));
880
881 if (!(pThis->bup_flag & BUP_SET))
882 {
883 if (pThis->bup_flag & BUP_LAST)
884 {
885 unsigned int i;
886 uint32_t *p = (uint32_t*)pThis->silence;
887 for (i = 0; i < sizeof(pThis->silence) / 4; i++) /** @todo r=andy Assumes 16-bit samples, stereo. */
888 *p++ = pThis->last_samp;
889 }
890 else
891 RT_ZERO(pThis->silence);
892
893 pThis->bup_flag |= BUP_SET;
894 }
895
896 while (cbElapsed)
897 {
898 uint32_t cbToWrite = RT_MIN(cbElapsed, (uint32_t)sizeof(pThis->silence));
899 uint32_t cbWrittenToStream;
900
901 int rc2 = AudioMixerSinkWrite(pThisCC->pSinkOut, AUDMIXOP_COPY,
902 pThis->silence, cbToWrite, &cbWrittenToStream);
903 if (RT_SUCCESS(rc2))
904 {
905 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
906 LogFlowFunc(("Warning: Only written %RU32 / %RU32 bytes, expect lags\n", cbWrittenToStream, cbToWrite));
907 }
908
909 /* Always report all data as being written;
910 * backends who were not able to catch up have to deal with it themselves. */
911 Assert(cbElapsed >= cbToWrite);
912 cbElapsed -= cbToWrite;
913 }
914}
915# endif /* Unused */
916
917
918/**
919 * Fetches the next buffer descriptor (BDLE) updating the stream registers.
920 *
921 * This will skip zero length descriptors.
922 *
923 * @returns Zero, or AC97_SR_BCIS if skipped zero length buffer with IOC set.
924 * @param pDevIns The device instance.
925 * @param pStream AC'97 stream to fetch BDLE for.
926 * @param pStreamCC The AC'97 stream, ring-3 state.
927 *
928 * @remarks Updates CIV, PIV, BD and PICB.
929 *
930 * @note Both PIV and CIV will be zero after a stream reset, so the first
931 * time we advance the buffer position afterwards, CIV will remain zero
932 * and PIV becomes 1. Thus we will start processing from BDLE00 and
933 * not BDLE01 as CIV=0 may lead you to think.
934 */
935static uint32_t ichac97R3StreamFetchNextBdle(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
936{
937 RT_NOREF(pStreamCC);
938 uint32_t fSrBcis = 0;
939 uint32_t cbTotal = 0; /* Counts the total length (in bytes) of the buffer descriptor list (BDL). */
940
941 /*
942 * Loop for skipping zero length entries.
943 */
944 for (;;)
945 {
946 /* Advance the buffer. */
947 pStream->Regs.civ = pStream->Regs.piv % AC97_MAX_BDLE /* (paranoia) */;
948 pStream->Regs.piv = (pStream->Regs.piv + 1) % AC97_MAX_BDLE;
949
950 /* Load it. */
951 AC97BDLE Bdle = { 0, 0 };
952 PDMDevHlpPCIPhysRead(pDevIns, pStream->Regs.bdbar + pStream->Regs.civ * sizeof(AC97BDLE), &Bdle, sizeof(AC97BDLE));
953 pStream->Regs.bd_valid = 1;
954 pStream->Regs.bd.addr = RT_H2LE_U32(Bdle.addr) & ~3;
955 pStream->Regs.bd.ctl_len = RT_H2LE_U32(Bdle.ctl_len);
956 pStream->Regs.picb = pStream->Regs.bd.ctl_len & AC97_BD_LEN_MASK;
957
958 cbTotal += pStream->Regs.bd.ctl_len & AC97_BD_LEN_MASK;
959
960 LogFlowFunc(("BDLE%02u: %#RX32 L %#x / LB %#x, ctl=%#06x%s%s\n",
961 pStream->Regs.civ, pStream->Regs.bd.addr, pStream->Regs.bd.ctl_len & AC97_BD_LEN_MASK,
962 (pStream->Regs.bd.ctl_len & AC97_BD_LEN_MASK) * PDMAudioPropsSampleSize(&pStreamCC->State.Cfg.Props),
963 pStream->Regs.bd.ctl_len >> 16,
964 pStream->Regs.bd.ctl_len & AC97_BD_IOC ? " ioc" : "",
965 pStream->Regs.bd.ctl_len & AC97_BD_BUP ? " bup" : ""));
966
967 /* Complain about any reserved bits set in CTL and ADDR: */
968 ASSERT_GUEST_MSG(!(pStream->Regs.bd.ctl_len & AC97_BD_LEN_CTL_MBZ),
969 ("Reserved bits set: %#RX32\n", pStream->Regs.bd.ctl_len));
970 ASSERT_GUEST_MSG(!(RT_H2LE_U32(Bdle.addr) & 3),
971 ("Reserved addr bits set: %#RX32\n", RT_H2LE_U32(Bdle.addr) ));
972
973 /* If the length is non-zero or if we've reached LVI, we're done regardless
974 of what's been loaded. Otherwise, we skip zero length buffers. */
975 if (pStream->Regs.picb)
976 break;
977 if (pStream->Regs.civ == (pStream->Regs.lvi % AC97_MAX_BDLE /* (paranoia) */))
978 {
979 LogFunc(("BDLE%02u is zero length! Can't skip (CIV=LVI). %#RX32 %#RX32\n", pStream->Regs.civ, Bdle.addr, Bdle.ctl_len));
980 break;
981 }
982 LogFunc(("BDLE%02u is zero length! Skipping. %#RX32 %#RX32\n", pStream->Regs.civ, Bdle.addr, Bdle.ctl_len));
983
984 /* If the buffer has IOC set, make sure it's triggered by the caller. */
985 if (pStream->Regs.bd.ctl_len & AC97_BD_IOC)
986 fSrBcis |= AC97_SR_BCIS;
987 }
988
989 /* 1.2.4.2 PCM Buffer Restrictions (in 302349-003) - #1 */
990 ASSERT_GUEST_MSG(!(pStream->Regs.picb & 1),
991 ("Odd lengths buffers are not allowed: %#x (%d) samples\n", pStream->Regs.picb, pStream->Regs.picb));
992
993 /* 1.2.4.2 PCM Buffer Restrictions (in 302349-003) - #2
994 *
995 * Note: Some guests (like older NetBSDs) first seem to set up the BDL a tad later so that cbTotal is 0.
996 * This means that the BDL is not set up at all.
997 * In such cases pStream->Regs.picb also will be 0 here and (debug) asserts here, which is annoying for debug builds.
998 * So first check if we have *any* BDLE set up before checking if PICB is > 0.
999 */
1000 ASSERT_GUEST_MSG(cbTotal == 0 || pStream->Regs.picb > 0, ("Zero length buffers not allowed to terminate list (LVI=%u CIV=%u, cbTotal=%zu)\n",
1001 pStream->Regs.lvi, pStream->Regs.civ, cbTotal));
1002
1003 return fSrBcis;
1004}
1005
1006
1007/**
1008 * Transfers data of an AC'97 stream according to its usage (input / output).
1009 *
1010 * For an SDO (output) stream this means reading DMA data from the device to
1011 * the AC'97 stream's internal FIFO buffer.
1012 *
1013 * For an SDI (input) stream this is reading audio data from the AC'97 stream's
1014 * internal FIFO buffer and writing it as DMA data to the device.
1015 *
1016 * @returns VBox status code.
1017 * @param pDevIns The device instance.
1018 * @param pThis The shared AC'97 state.
1019 * @param pStream The AC'97 stream to update (shared).
1020 * @param pStreamCC The AC'97 stream to update (ring-3).
1021 * @param cbToProcess The max amount of data to process (i.e.
1022 * put into / remove from the circular buffer).
1023 * Unless something is going seriously wrong, this
1024 * will always be transfer size for the current
1025 * period. The current period will never be
1026 * larger than what can be stored in the current
1027 * buffer (i.e. what PICB indicates).
1028 * @param fWriteSilence Whether to write silence if this is an input
1029 * stream (done while waiting for backend to get
1030 * going).
1031 * @param fInput Set if input, clear if output.
1032 */
1033static int ichac97R3StreamTransfer(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
1034 PAC97STREAMR3 pStreamCC, uint32_t cbToProcess, bool fWriteSilence, bool fInput)
1035{
1036 if (RT_LIKELY(cbToProcess > 0))
1037 Assert(PDMAudioPropsIsSizeAligned(&pStreamCC->State.Cfg.Props, cbToProcess));
1038 else
1039 return VINF_SUCCESS;
1040
1041 ichac97R3StreamLock(pStreamCC);
1042
1043 /*
1044 * Check that the controller is not halted (DCH) and that the buffer
1045 * completion interrupt isn't pending.
1046 */
1047 /** @todo r=bird: Why do we not just barge ahead even when BCIS is set? Can't
1048 * find anything in spec indicating that we shouldn't. Linux shouldn't
1049 * care if be bundle IOCs, as it checks how many steps we've taken using
1050 * CIV. The Windows AC'97 sample driver doesn't care at all, since it
1051 * just sets LIV to CIV-1 (thought that's probably not what the real
1052 * windows driver does)...
1053 *
1054 * This is not going to sound good if it happens often enough, because
1055 * each time we'll lose one DMA period (exact length depends on the
1056 * buffer here).
1057 *
1058 * If we're going to keep this hack, there should be a
1059 * PDMDevHlpTimerSetRelative call arm-ing the DMA timer to fire shortly
1060 * after BCIS is cleared. Otherwise, we might lag behind even more
1061 * before we get stuff going again.
1062 *
1063 * I just wish there was some clear reasoning in the source code for
1064 * weird shit like this. This is just random voodoo. Sigh^3! */
1065 if (!(pStream->Regs.sr & (AC97_SR_DCH | AC97_SR_BCIS))) /* Controller halted? */
1066 { /* not halted nor does it have pending interrupt - likely */ }
1067 else
1068 {
1069 /** @todo Stop DMA timer when DCH is set. */
1070 if (pStream->Regs.sr & AC97_SR_DCH)
1071 {
1072 STAM_REL_COUNTER_INC(&pStreamCC->State.StatDmaSkippedDch);
1073 LogFunc(("[SD%RU8] DCH set\n", pStream->u8SD));
1074 }
1075 if (pStream->Regs.sr & AC97_SR_BCIS)
1076 {
1077 STAM_REL_COUNTER_INC(&pStreamCC->State.StatDmaSkippedPendingBcis);
1078 LogFunc(("[SD%RU8] BCIS set\n", pStream->u8SD));
1079 }
1080 if ((pStream->Regs.cr & AC97_CR_RPBM) /* Bus master operation started. */ && !fInput)
1081 {
1082 /*ichac97R3WriteBUP(pThis, cbToProcess);*/
1083 }
1084
1085 ichac97R3StreamUnlock(pStreamCC);
1086 return VINF_SUCCESS;
1087 }
1088
1089 /* 0x1ba*2 = 0x374 (884) 0x3c0
1090 * Transfer loop.
1091 */
1092#ifdef LOG_ENABLED
1093 uint32_t cbProcessedTotal = 0;
1094#endif
1095 int rc = VINF_SUCCESS;
1096 PRTCIRCBUF pCircBuf = pStreamCC->State.pCircBuf;
1097 AssertReturnStmt(pCircBuf, ichac97R3StreamUnlock(pStreamCC), VINF_SUCCESS);
1098 Assert((uint32_t)pStream->Regs.picb * PDMAudioPropsSampleSize(&pStreamCC->State.Cfg.Props) >= cbToProcess);
1099 Log3Func(("[SD%RU8] cbToProcess=%#x PICB=%#x/%#x\n", pStream->u8SD, cbToProcess,
1100 pStream->Regs.picb, pStream->Regs.picb * PDMAudioPropsSampleSize(&pStreamCC->State.Cfg.Props)));
1101
1102 while (cbToProcess > 0)
1103 {
1104 uint32_t cbChunk = cbToProcess;
1105
1106 /*
1107 * Output.
1108 */
1109 if (!fInput)
1110 {
1111 void *pvDst = NULL;
1112 size_t cbDst = 0;
1113 RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvDst, &cbDst);
1114
1115 if (cbDst)
1116 {
1117 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, pStream->Regs.bd.addr, pvDst, cbDst);
1118 AssertRC(rc2);
1119
1120 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.pFileDMA))
1121 { /* likely */ }
1122 else
1123 AudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvDst, cbDst);
1124 }
1125
1126 RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
1127
1128 cbChunk = (uint32_t)cbDst; /* Update the current chunk size to what really has been written. */
1129 }
1130 /*
1131 * Input.
1132 */
1133 else if (!fWriteSilence)
1134 {
1135 void *pvSrc = NULL;
1136 size_t cbSrc = 0;
1137 RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvSrc, &cbSrc);
1138
1139 if (cbSrc)
1140 {
1141 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, pStream->Regs.bd.addr, pvSrc, cbSrc);
1142 AssertRC(rc2);
1143
1144 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.pFileDMA))
1145 { /* likely */ }
1146 else
1147 AudioHlpFileWrite(pStreamCC->Dbg.Runtime.pFileDMA, pvSrc, cbSrc);
1148 }
1149
1150 RTCircBufReleaseReadBlock(pCircBuf, cbSrc);
1151
1152 cbChunk = (uint32_t)cbSrc; /* Update the current chunk size to what really has been read. */
1153 }
1154 else
1155 {
1156 /* Since the format is signed 16-bit or 32-bit integer samples, we can
1157 use g_abRTZero64K as source and avoid some unnecessary bzero() work. */
1158 cbChunk = RT_MIN(cbChunk, sizeof(g_abRTZero64K));
1159 cbChunk = PDMAudioPropsFloorBytesToFrame(&pStreamCC->State.Cfg.Props, cbChunk);
1160
1161 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, pStream->Regs.bd.addr, g_abRTZero64K, cbChunk);
1162 AssertRC(rc2);
1163 }
1164
1165 Assert(PDMAudioPropsIsSizeAligned(&pStreamCC->State.Cfg.Props, cbChunk));
1166 Assert(cbChunk <= cbToProcess);
1167
1168 /*
1169 * Advance.
1170 */
1171 pStream->Regs.picb -= cbChunk / PDMAudioPropsSampleSize(&pStreamCC->State.Cfg.Props);
1172 pStream->Regs.bd.addr += cbChunk;
1173 cbToProcess -= cbChunk;
1174#ifdef LOG_ENABLED
1175 cbProcessedTotal += cbChunk;
1176#endif
1177 LogFlowFunc(("[SD%RU8] cbChunk=%#x, cbToProcess=%#x, cbTotal=%#x picb=%#x\n",
1178 pStream->u8SD, cbChunk, cbToProcess, cbProcessedTotal, pStream->Regs.picb));
1179 }
1180
1181 /*
1182 * Fetch a new buffer descriptor if we've exhausted the current one.
1183 */
1184 if (!pStream->Regs.picb)
1185 {
1186 uint32_t fNewSr = pStream->Regs.sr & ~AC97_SR_CELV;
1187
1188 if (pStream->Regs.bd.ctl_len & AC97_BD_IOC)
1189 fNewSr |= AC97_SR_BCIS;
1190
1191 if (pStream->Regs.civ != pStream->Regs.lvi)
1192 fNewSr |= ichac97R3StreamFetchNextBdle(pDevIns, pStream, pStreamCC);
1193 else
1194 {
1195 LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pStream->Regs.civ, pStream->Regs.lvi));
1196 fNewSr |= AC97_SR_LVBCI | AC97_SR_DCH | AC97_SR_CELV;
1197 pThis->bup_flag = (pStream->Regs.bd.ctl_len & AC97_BD_BUP) ? BUP_LAST : 0;
1198 /** @todo r=bird: The bup_flag isn't cleared anywhere else. We should probably
1199 * do what the spec says, and keep writing zeros (silence).
1200 * Alternatively, we could hope the guest will pause the DMA engine
1201 * immediately after seeing this condition, in which case we should
1202 * stop the DMA timer from being re-armed. */
1203 }
1204
1205 ichac97StreamUpdateSR(pDevIns, pThis, pStream, fNewSr);
1206 }
1207
1208 ichac97R3StreamUnlock(pStreamCC);
1209 LogFlowFuncLeaveRC(rc);
1210 return rc;
1211}
1212
1213
1214/**
1215 * Input streams: Pulls data from the mixer, putting it in the internal DMA
1216 * buffer.
1217 *
1218 * @param pStreamR3 The AC'97 stream (ring-3 bits).
1219 * @param pSink The mixer sink to pull from.
1220 */
1221static void ichac97R3StreamPullFromMixer(PAC97STREAMR3 pStreamR3, PAUDMIXSINK pSink)
1222{
1223# ifdef LOG_ENABLED
1224 uint64_t const offWriteOld = pStreamR3->State.offWrite;
1225# endif
1226 pStreamR3->State.offWrite = AudioMixerSinkTransferToCircBuf(pSink,
1227 pStreamR3->State.pCircBuf,
1228 pStreamR3->State.offWrite,
1229 pStreamR3->u8SD,
1230 pStreamR3->Dbg.Runtime.fEnabled
1231 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1232
1233 Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1234 pStreamR3->State.offWrite - offWriteOld, pStreamR3->State.offWrite));
1235
1236 /* Update buffer stats. */
1237 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1238}
1239
1240
1241/**
1242 * Output streams: Pushes data to the mixer.
1243 *
1244 * @param pStreamR3 The AC'97 stream (ring-3 bits).
1245 * @param pSink The mixer sink to push to.
1246 */
1247static void ichac97R3StreamPushToMixer(PAC97STREAMR3 pStreamR3, PAUDMIXSINK pSink)
1248{
1249# ifdef LOG_ENABLED
1250 uint64_t const offReadOld = pStreamR3->State.offRead;
1251# endif
1252 pStreamR3->State.offRead = AudioMixerSinkTransferFromCircBuf(pSink,
1253 pStreamR3->State.pCircBuf,
1254 pStreamR3->State.offRead,
1255 pStreamR3->u8SD,
1256 pStreamR3->Dbg.Runtime.fEnabled
1257 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1258
1259 Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1260 pStreamR3->State.offRead - offReadOld, pStreamR3->State.offRead));
1261
1262 /* Update buffer stats. */
1263 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1264}
1265
1266
1267/**
1268 * Updates an AC'97 stream by doing its DMA transfers.
1269 *
1270 * The host sink(s) set the overall pace (bird: no it doesn't, the DMA timer
1271 * does - we just hope like heck it matches the speed at which the *backend*
1272 * host audio driver processes samples).
1273 *
1274 * @param pDevIns The device instance.
1275 * @param pThis The shared AC'97 state.
1276 * @param pThisCC The ring-3 AC'97 state.
1277 * @param pStream The AC'97 stream to update (shared).
1278 * @param pStreamCC The AC'97 stream to update (ring-3).
1279 * @param pSink The sink being updated.
1280 */
1281static void ichac97R3StreamUpdateDma(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
1282 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, PAUDMIXSINK pSink)
1283{
1284 RT_NOREF(pThisCC);
1285 int rc2;
1286
1287 /* The amount we're supposed to be transfering in this DMA period. */
1288 uint32_t cbPeriod = pStream->cbDmaPeriod;
1289
1290 /*
1291 * Output streams (SDO).
1292 */
1293 if (pStreamCC->State.Cfg.enmDir == PDMAUDIODIR_OUT)
1294 {
1295 /*
1296 * Check how much room we have in our DMA buffer. There should be at
1297 * least one period worth of space there or we're in an overflow situation.
1298 */
1299 uint32_t cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1300 if (cbStreamFree >= cbPeriod)
1301 { /* likely */ }
1302 else
1303 {
1304 STAM_REL_COUNTER_INC(&pStreamCC->State.StatDmaFlowProblems);
1305 LogFunc(("Warning! Stream #%u has insufficient space free: %u bytes, need %u. Will try move data out of the buffer...\n",
1306 pStreamCC->u8SD, cbStreamFree, cbPeriod));
1307 int rc = AudioMixerSinkTryLock(pSink);
1308 if (RT_SUCCESS(rc))
1309 {
1310 ichac97R3StreamPushToMixer(pStreamCC, pSink);
1311 AudioMixerSinkUpdate(pSink, 0, 0);
1312 AudioMixerSinkUnlock(pSink);
1313 }
1314 else
1315 RTThreadYield();
1316 LogFunc(("Gained %u bytes.\n", ichac97R3StreamGetFree(pStreamCC) - cbStreamFree));
1317
1318 cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1319 if (cbStreamFree < cbPeriod)
1320 {
1321 /* Unable to make sufficient space. Drop the whole buffer content.
1322 * This is needed in order to keep the device emulation running at a constant rate,
1323 * at the cost of losing valid (but too much) data. */
1324 STAM_REL_COUNTER_INC(&pStreamCC->State.StatDmaFlowErrors);
1325 LogRel2(("AC97: Warning: Hit stream #%RU8 overflow, dropping %u bytes of audio data\n",
1326 pStreamCC->u8SD, ichac97R3StreamGetUsed(pStreamCC)));
1327# ifdef AC97_STRICT
1328 AssertMsgFailed(("Hit stream #%RU8 overflow -- timing bug?\n", pStreamCC->u8SD));
1329# endif
1330 RTCircBufReset(pStreamCC->State.pCircBuf);
1331 pStreamCC->State.offWrite = 0;
1332 pStreamCC->State.offRead = 0;
1333 cbStreamFree = ichac97R3StreamGetFree(pStreamCC);
1334 Assert(cbStreamFree >= cbPeriod);
1335 }
1336 }
1337
1338 /*
1339 * Do the DMA transfer.
1340 */
1341 Log3Func(("[SD%RU8] PICB=%#x samples / %RU64 ms, cbFree=%#x / %RU64 ms, cbTransferChunk=%#x / %RU64 ms\n", pStream->u8SD,
1342 pStream->Regs.picb, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props,
1343 PDMAudioPropsSampleSize(&pStreamCC->State.Cfg.Props)
1344 * pStream->Regs.picb),
1345 cbStreamFree, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, cbStreamFree),
1346 cbPeriod, PDMAudioPropsBytesToMilli(&pStreamCC->State.Cfg.Props, cbPeriod)));
1347
1348 rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC, RT_MIN(cbStreamFree, cbPeriod),
1349 false /*fWriteSilence*/, false /*fInput*/);
1350 AssertRC(rc2);
1351
1352 pStreamCC->State.tsLastUpdateNs = RTTimeNanoTS();
1353
1354
1355 /*
1356 * Notify the AIO thread.
1357 */
1358 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
1359 AssertRC(rc2);
1360 }
1361 /*
1362 * Input stream (SDI).
1363 */
1364 else
1365 {
1366 /*
1367 * See how much data we've got buffered...
1368 */
1369 bool fWriteSilence = false;
1370 uint32_t cbStreamUsed = ichac97R3StreamGetUsed(pStreamCC);
1371 if (pStreamCC->State.fInputPreBuffered && cbStreamUsed >= cbPeriod)
1372 { /*likely*/ }
1373 /*
1374 * Because it may take a while for the input stream to get going (at least
1375 * with pulseaudio), we feed the guest silence till we've pre-buffer a
1376 * couple of timer Hz periods. (This avoid lots of bogus buffer underruns
1377 * when starting an input stream and hogging the timer EMT.)
1378 */
1379 else if (!pStreamCC->State.fInputPreBuffered)
1380 {
1381 uint32_t const cbPreBuffer = PDMAudioPropsNanoToBytes(&pStreamCC->State.Cfg.Props,
1382 RT_NS_1SEC / pStreamCC->State.uTimerHz);
1383 if (cbStreamUsed < cbPreBuffer)
1384 {
1385 Log3Func(("Pre-buffering (got %#x out of %#x bytes)...\n", cbStreamUsed, cbPreBuffer));
1386 fWriteSilence = true;
1387 cbStreamUsed = cbPeriod;
1388 }
1389 else
1390 {
1391 Log3Func(("Completed pre-buffering (got %#x, needed %#x bytes).\n", cbStreamUsed, cbPreBuffer));
1392 pStreamCC->State.fInputPreBuffered = true;
1393 fWriteSilence = ichac97R3StreamGetFree(pStreamCC) >= cbPreBuffer + cbPreBuffer / 2;
1394 if (fWriteSilence)
1395 cbStreamUsed = cbPeriod;
1396 }
1397 }
1398 /*
1399 * When we're low on data, we must really try fetch some ourselves
1400 * as buffer underruns must not happen.
1401 */
1402 else
1403 {
1404 STAM_REL_COUNTER_INC(&pStreamCC->State.StatDmaFlowProblems);
1405 LogFunc(("Warning! Stream #%u has insufficient data available: %u bytes, need %u. Will try move pull more data into the buffer...\n",
1406 pStreamCC->u8SD, cbStreamUsed, cbPeriod));
1407 int rc = AudioMixerSinkTryLock(pSink);
1408 if (RT_SUCCESS(rc))
1409 {
1410 AudioMixerSinkUpdate(pSink, cbStreamUsed, cbPeriod);
1411 ichac97R3StreamPullFromMixer(pStreamCC, pSink);
1412 AudioMixerSinkUnlock(pSink);
1413 }
1414 else
1415 RTThreadYield();
1416 LogFunc(("Gained %u bytes.\n", ichac97R3StreamGetUsed(pStreamCC) - cbStreamUsed));
1417 cbStreamUsed = ichac97R3StreamGetUsed(pStreamCC);
1418 if (cbStreamUsed < cbPeriod)
1419 {
1420 /* Unable to find sufficient input data by simple prodding.
1421 In order to keep a constant byte stream following thru the DMA
1422 engine into the guest, we will try again and then fall back on
1423 filling the gap with silence. */
1424 uint32_t cbSilence = 0;
1425 do
1426 {
1427 AudioMixerSinkLock(pSink);
1428
1429 cbStreamUsed = ichac97R3StreamGetUsed(pStreamCC);
1430 if (cbStreamUsed < cbPeriod)
1431 {
1432 ichac97R3StreamPullFromMixer(pStreamCC, pSink);
1433 cbStreamUsed = ichac97R3StreamGetUsed(pStreamCC);
1434 while (cbStreamUsed < cbPeriod)
1435 {
1436 void *pvDstBuf;
1437 size_t cbDstBuf;
1438 RTCircBufAcquireWriteBlock(pStreamCC->State.pCircBuf, cbPeriod - cbStreamUsed,
1439 &pvDstBuf, &cbDstBuf);
1440 RT_BZERO(pvDstBuf, cbDstBuf);
1441 RTCircBufReleaseWriteBlock(pStreamCC->State.pCircBuf, cbDstBuf);
1442 cbSilence += (uint32_t)cbDstBuf;
1443 cbStreamUsed += (uint32_t)cbDstBuf;
1444 }
1445 }
1446
1447 AudioMixerSinkUnlock(pSink);
1448 } while (cbStreamUsed < cbPeriod);
1449 if (cbSilence > 0)
1450 {
1451 STAM_REL_COUNTER_INC(&pStreamCC->State.StatDmaFlowErrors);
1452 STAM_REL_COUNTER_ADD(&pStreamCC->State.StatDmaFlowErrorBytes, cbSilence);
1453 LogRel2(("AC97: Warning: Stream #%RU8 underrun, added %u bytes of silence (%u us)\n", pStreamCC->u8SD,
1454 cbSilence, PDMAudioPropsBytesToMicro(&pStreamCC->State.Cfg.Props, cbSilence)));
1455 }
1456 }
1457 }
1458
1459 /*
1460 * Do the DMA'ing.
1461 */
1462 if (cbStreamUsed)
1463 {
1464 rc2 = ichac97R3StreamTransfer(pDevIns, pThis, pStream, pStreamCC, RT_MIN(cbPeriod, cbStreamUsed),
1465 fWriteSilence, true /*fInput*/);
1466 AssertRC(rc2);
1467
1468 pStreamCC->State.tsLastUpdateNs = RTTimeNanoTS();
1469 }
1470
1471 /*
1472 * We should always kick the AIO thread.
1473 */
1474 /** @todo This isn't entirely ideal. If we get into an underrun situation,
1475 * we ideally want the AIO thread to run right before the DMA timer
1476 * rather than right after it ran. */
1477 Log5Func(("Notifying AIO thread\n"));
1478 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
1479 AssertRC(rc2);
1480 }
1481}
1482
1483
1484/**
1485 * @callback_method_impl{FNAUDMIXSINKUPDATE}
1486 *
1487 * For output streams this moves data from the internal DMA buffer (in which
1488 * ichac97R3StreamUpdateDma put it), thru the mixer and to the various backend
1489 * audio devices.
1490 *
1491 * For input streams this pulls data from the backend audio device(s), thru the
1492 * mixer and puts it in the internal DMA buffer ready for
1493 * ichac97R3StreamUpdateDma to pump into guest memory.
1494 */
1495static DECLCALLBACK(void) ichac97R3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser)
1496{
1497 PAC97STATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
1498 PAC97STREAMR3 const pStreamCC = (PAC97STREAMR3)pvUser;
1499 Assert(pStreamCC->u8SD == (uintptr_t)(pStreamCC - &pThisCC->aStreams[0]));
1500 Assert(pSink == ichac97R3IndexToSink(pThisCC, pStreamCC->u8SD));
1501 RT_NOREF(pThisCC);
1502
1503 /*
1504 * Output (SDO).
1505 */
1506 if (pStreamCC->State.Cfg.enmDir == PDMAUDIODIR_OUT)
1507 ichac97R3StreamPushToMixer(pStreamCC, pSink);
1508 /*
1509 * Input (SDI).
1510 */
1511 else
1512 ichac97R3StreamPullFromMixer(pStreamCC, pSink);
1513}
1514
1515
1516/**
1517 * Updates the next transfer based on a specific amount of bytes.
1518 *
1519 * @param pDevIns The device instance.
1520 * @param pStream The AC'97 stream to update (shared).
1521 * @param pStreamCC The AC'97 stream to update (ring-3).
1522 */
1523static void ichac97R3StreamTransferUpdate(PPDMDEVINS pDevIns, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1524{
1525 /*
1526 * Get the number of bytes left in the current buffer.
1527 *
1528 * This isn't entirely optimal iff the current entry doesn't have IOC set, in
1529 * that case we should use the number of bytes to the next IOC. Unfortuantely,
1530 * it seems the spec doesn't allow us to prefetch more than one BDLE, so we
1531 * probably cannot look ahead without violating that restriction. This is
1532 * probably a purely theoretical problem at this point.
1533 */
1534 uint32_t const cbLeftInBdle = pStream->Regs.picb * PDMAudioPropsSampleSize(&pStreamCC->State.Cfg.Props);
1535 if (cbLeftInBdle > 0) /** @todo r=bird: see todo about this in ichac97R3StreamFetchBDLE. */
1536 {
1537 /*
1538 * Since the buffer can be up to 0xfffe samples long (frame aligning stereo
1539 * prevents 0xffff), which translates to 743ms at a 44.1kHz rate, we must
1540 * also take the nominal timer frequency into account here so we keep
1541 * moving data at a steady rate. (In theory, I think the guest can even
1542 * set up just one buffer and anticipate where we are in the buffer
1543 * processing when it writes/reads from it. Linux seems to be doing such
1544 * configs when not playing or something.)
1545 */
1546 uint32_t const cbMaxPerHz = PDMAudioPropsNanoToBytes(&pStreamCC->State.Cfg.Props, RT_NS_1SEC / pStreamCC->State.uTimerHz);
1547
1548 if (cbLeftInBdle <= cbMaxPerHz)
1549 pStream->cbDmaPeriod = cbLeftInBdle;
1550 /* Try avoid leaving a very short period at the end of a buffer. */
1551 else if (cbLeftInBdle >= cbMaxPerHz + cbMaxPerHz / 2)
1552 pStream->cbDmaPeriod = cbMaxPerHz;
1553 else
1554 pStream->cbDmaPeriod = PDMAudioPropsFloorBytesToFrame(&pStreamCC->State.Cfg.Props, cbLeftInBdle / 2);
1555
1556 /*
1557 * Translate the chunk size to timer ticks.
1558 */
1559 uint64_t const cNsXferChunk = PDMAudioPropsBytesToNano(&pStreamCC->State.Cfg.Props, pStream->cbDmaPeriod);
1560 pStream->cDmaPeriodTicks = PDMDevHlpTimerFromNano(pDevIns, pStream->hTimer, cNsXferChunk);
1561 Assert(pStream->cDmaPeriodTicks > 0);
1562
1563 Log3Func(("[SD%RU8] cbLeftInBdle=%#RX32 cbMaxPerHz=%#RX32 (%RU16Hz) -> cbDmaPeriod=%#RX32 cDmaPeriodTicks=%RX64\n",
1564 pStream->u8SD, cbLeftInBdle, cbMaxPerHz, pStreamCC->State.uTimerHz, pStream->cbDmaPeriod, pStream->cDmaPeriodTicks));
1565 }
1566}
1567
1568
1569/**
1570 * Sets the virtual device timer to a new expiration time.
1571 *
1572 * @param pDevIns The device instance.
1573 * @param pStream AC'97 stream to set timer for.
1574 * @param cTicksToDeadline The number of ticks to the new deadline.
1575 *
1576 * @remarks This used to be more complicated a long time ago...
1577 */
1578DECLINLINE(void) ichac97R3TimerSet(PPDMDEVINS pDevIns, PAC97STREAM pStream, uint64_t cTicksToDeadline)
1579{
1580 int rc = PDMDevHlpTimerSetRelative(pDevIns, pStream->hTimer, cTicksToDeadline, &pStream->uArmedTs);
1581 AssertRC(rc);
1582}
1583
1584
1585/**
1586 * @callback_method_impl{FNTMTIMERDEV,
1587 * Timer callback which handles the audio data transfers on a periodic basis.}
1588 */
1589static DECLCALLBACK(void) ichac97R3Timer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1590{
1591 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
1592 STAM_PROFILE_START(&pThis->StatTimer, a);
1593 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
1594 PAC97STREAM pStream = (PAC97STREAM)pvUser;
1595 PAC97STREAMR3 pStreamCC = &RT_SAFE_SUBSCRIPT8(pThisCC->aStreams, pStream->u8SD);
1596 Assert(hTimer == pStream->hTimer); RT_NOREF(hTimer);
1597
1598 Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
1599 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1600 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStream->hTimer));
1601
1602 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
1603 if (pSink && AudioMixerSinkIsActive(pSink))
1604 {
1605 ichac97R3StreamUpdateDma(pDevIns, pThis, pThisCC, pStream, pStreamCC, pSink);
1606
1607 pStream->uDmaPeriod++;
1608 ichac97R3StreamTransferUpdate(pDevIns, pStream, pStreamCC);
1609 ichac97R3TimerSet(pDevIns, pStream, pStream->cDmaPeriodTicks);
1610 }
1611
1612 STAM_PROFILE_STOP(&pThis->StatTimer, a);
1613}
1614
1615#endif /* IN_RING3 */
1616
1617
1618/*********************************************************************************************************************************
1619* AC'97 Stream Management *
1620*********************************************************************************************************************************/
1621#ifdef IN_RING3
1622
1623/**
1624 * Locks an AC'97 stream for serialized access.
1625 *
1626 * @returns VBox status code.
1627 * @param pStreamCC The AC'97 stream to lock (ring-3).
1628 */
1629DECLINLINE(void) ichac97R3StreamLock(PAC97STREAMR3 pStreamCC)
1630{
1631 int rc2 = RTCritSectEnter(&pStreamCC->State.CritSect);
1632 AssertRC(rc2);
1633}
1634
1635/**
1636 * Unlocks a formerly locked AC'97 stream.
1637 *
1638 * @returns VBox status code.
1639 * @param pStreamCC The AC'97 stream to unlock (ring-3).
1640 */
1641DECLINLINE(void) ichac97R3StreamUnlock(PAC97STREAMR3 pStreamCC)
1642{
1643 int rc2 = RTCritSectLeave(&pStreamCC->State.CritSect);
1644 AssertRC(rc2);
1645}
1646
1647#endif /* IN_RING3 */
1648
1649/**
1650 * Updates the status register (SR) of an AC'97 audio stream.
1651 *
1652 * @param pDevIns The device instance.
1653 * @param pThis The shared AC'97 state.
1654 * @param pStream AC'97 stream to update SR for.
1655 * @param new_sr New value for status register (SR).
1656 */
1657static void ichac97StreamUpdateSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t new_sr)
1658{
1659 bool fSignal = false;
1660 int iIRQL = 0;
1661
1662 uint32_t new_mask = new_sr & AC97_SR_INT_MASK;
1663 uint32_t old_mask = pStream->Regs.sr & AC97_SR_INT_MASK;
1664
1665 if (new_mask ^ old_mask)
1666 {
1667 /** @todo Is IRQ deasserted when only one of status bits is cleared? */
1668 if (!new_mask)
1669 {
1670 fSignal = true;
1671 iIRQL = 0;
1672 }
1673 else if ((new_mask & AC97_SR_LVBCI) && (pStream->Regs.cr & AC97_CR_LVBIE))
1674 {
1675 fSignal = true;
1676 iIRQL = 1;
1677 }
1678 else if ((new_mask & AC97_SR_BCIS) && (pStream->Regs.cr & AC97_CR_IOCE))
1679 {
1680 fSignal = true;
1681 iIRQL = 1;
1682 }
1683 }
1684
1685 pStream->Regs.sr = new_sr;
1686
1687 LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n",
1688 pStream->Regs.sr & AC97_SR_BCIS, pStream->Regs.sr & AC97_SR_LVBCI, pStream->Regs.sr, fSignal, iIRQL));
1689
1690 if (fSignal)
1691 {
1692 static uint32_t const s_aMasks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT };
1693 Assert(pStream->u8SD < AC97_MAX_STREAMS);
1694 if (iIRQL)
1695 pThis->glob_sta |= s_aMasks[pStream->u8SD];
1696 else
1697 pThis->glob_sta &= ~s_aMasks[pStream->u8SD];
1698
1699 LogFlowFunc(("Setting IRQ level=%d\n", iIRQL));
1700 PDMDevHlpPCISetIrq(pDevIns, 0, iIRQL);
1701 }
1702}
1703
1704/**
1705 * Writes a new value to a stream's status register (SR).
1706 *
1707 * @param pDevIns The device instance.
1708 * @param pThis The shared AC'97 device state.
1709 * @param pStream Stream to update SR for.
1710 * @param u32Val New value to set the stream's SR to.
1711 */
1712static void ichac97StreamWriteSR(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream, uint32_t u32Val)
1713{
1714 Log3Func(("[SD%RU8] SR <- %#x (sr %#x)\n", pStream->u8SD, u32Val, pStream->Regs.sr));
1715
1716 pStream->Regs.sr |= u32Val & ~(AC97_SR_RO_MASK | AC97_SR_WCLEAR_MASK);
1717 ichac97StreamUpdateSR(pDevIns, pThis, pStream, pStream->Regs.sr & ~(u32Val & AC97_SR_WCLEAR_MASK));
1718}
1719
1720#ifdef IN_RING3
1721
1722/**
1723 * Resets an AC'97 stream.
1724 *
1725 * @param pThis The shared AC'97 state.
1726 * @param pStream The AC'97 stream to reset (shared).
1727 * @param pStreamCC The AC'97 stream to reset (ring-3).
1728 */
1729static void ichac97R3StreamReset(PAC97STATE pThis, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
1730{
1731 ichac97R3StreamLock(pStreamCC);
1732
1733 LogFunc(("[SD%RU8]\n", pStream->u8SD));
1734
1735 if (pStreamCC->State.pCircBuf)
1736 RTCircBufReset(pStreamCC->State.pCircBuf);
1737
1738 pStream->Regs.bdbar = 0;
1739 pStream->Regs.civ = 0;
1740 pStream->Regs.lvi = 0;
1741
1742 pStream->Regs.picb = 0;
1743 pStream->Regs.piv = 0; /* Note! Because this is also zero, we will actually start transferring with BDLE00. */
1744 pStream->Regs.cr &= AC97_CR_DONT_CLEAR_MASK;
1745 pStream->Regs.bd_valid = 0;
1746
1747 RT_ZERO(pThis->silence);
1748
1749 ichac97R3StreamUnlock(pStreamCC);
1750}
1751
1752/**
1753 * Retrieves a specific driver stream of a AC'97 driver.
1754 *
1755 * @returns Pointer to driver stream if found, or NULL if not found.
1756 * @param pDrv Driver to retrieve driver stream for.
1757 * @param enmDir Stream direction to retrieve.
1758 * @param enmPath Stream destination / source to retrieve.
1759 */
1760static PAC97DRIVERSTREAM ichac97R3MixerGetDrvStream(PAC97DRIVER pDrv, PDMAUDIODIR enmDir, PDMAUDIOPATH enmPath)
1761{
1762 if (enmDir == PDMAUDIODIR_IN)
1763 {
1764 LogFunc(("enmRecSource=%d\n", enmPath));
1765 switch (enmPath)
1766 {
1767 case PDMAUDIOPATH_IN_LINE:
1768 return &pDrv->LineIn;
1769 case PDMAUDIOPATH_IN_MIC:
1770 return &pDrv->MicIn;
1771 default:
1772 AssertFailedBreak();
1773 }
1774 }
1775 else if (enmDir == PDMAUDIODIR_OUT)
1776 {
1777 LogFunc(("enmPlaybackDst=%d\n", enmPath));
1778 switch (enmPath)
1779 {
1780 case PDMAUDIOPATH_OUT_FRONT:
1781 return &pDrv->Out;
1782 default:
1783 AssertFailedBreak();
1784 }
1785 }
1786 else
1787 AssertFailed();
1788
1789 return NULL;
1790}
1791
1792/**
1793 * Adds a driver stream to a specific mixer sink.
1794 *
1795 * Called by ichac97R3MixerAddDrvStreams() and ichac97R3MixerAddDrv().
1796 *
1797 * @returns VBox status code.
1798 * @param pDevIns The device instance.
1799 * @param pMixSink Mixer sink to add driver stream to.
1800 * @param pCfg Stream configuration to use.
1801 * @param pDrv Driver stream to add.
1802 */
1803static int ichac97R3MixerAddDrvStream(PPDMDEVINS pDevIns, PAUDMIXSINK pMixSink, PCPDMAUDIOSTREAMCFG pCfg, PAC97DRIVER pDrv)
1804{
1805 AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1806 LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pCfg->szName));
1807
1808 int rc;
1809 PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, pCfg->enmDir, pCfg->enmPath);
1810 if (pDrvStream)
1811 {
1812 AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
1813
1814 PAUDMIXSTREAM pMixStrm;
1815 rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pCfg, pDevIns, &pMixStrm);
1816 LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pCfg->szName, rc));
1817 if (RT_SUCCESS(rc))
1818 {
1819 rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
1820 LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pCfg->szName, rc));
1821 if (RT_SUCCESS(rc))
1822 pDrvStream->pMixStrm = pMixStrm;
1823 else
1824 AudioMixerStreamDestroy(pMixStrm, pDevIns, true /*fImmediate*/);
1825 }
1826 }
1827 else
1828 rc = VERR_INVALID_PARAMETER;
1829
1830 LogFlowFuncLeaveRC(rc);
1831 return rc;
1832}
1833
1834
1835/**
1836 * Adds all current driver streams to a specific mixer sink.
1837 *
1838 * Called by ichac97R3StreamSetUp().
1839 *
1840 * @returns VBox status code.
1841 * @param pDevIns The device instance.
1842 * @param pThisCC The ring-3 AC'97 state.
1843 * @param pMixSink Mixer sink to add stream to.
1844 * @param pCfg Stream configuration to use.
1845 */
1846static int ichac97R3MixerAddDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink, PCPDMAUDIOSTREAMCFG pCfg)
1847{
1848 AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
1849
1850 int rc;
1851 if (AudioHlpStreamCfgIsValid(pCfg))
1852 {
1853 rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props, pCfg->Device.cMsSchedulingHint);
1854 if (RT_SUCCESS(rc))
1855 {
1856 PAC97DRIVER pDrv;
1857 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
1858 {
1859 int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pMixSink, pCfg, pDrv);
1860 if (RT_FAILURE(rc2))
1861 LogFunc(("Attaching stream failed with %Rrc\n", rc2));
1862
1863 /* Do not pass failure to rc here, as there might be drivers which aren't
1864 configured / ready yet. */
1865 }
1866 }
1867 }
1868 else
1869 rc = VERR_INVALID_PARAMETER;
1870
1871 LogFlowFuncLeaveRC(rc);
1872 return rc;
1873}
1874
1875
1876/**
1877 * Removes a driver stream from a specific mixer sink.
1878 *
1879 * Worker for ichac97R3MixerRemoveDrvStreams.
1880 *
1881 * @param pDevIns The device instance.
1882 * @param pMixSink Mixer sink to remove audio streams from.
1883 * @param enmDir Stream direction to remove.
1884 * @param enmPath Stream destination / source to remove.
1885 * @param pDrv Driver stream to remove.
1886 */
1887static void ichac97R3MixerRemoveDrvStream(PPDMDEVINS pDevIns, PAUDMIXSINK pMixSink, PDMAUDIODIR enmDir,
1888 PDMAUDIOPATH enmPath, PAC97DRIVER pDrv)
1889{
1890 PAC97DRIVERSTREAM pDrvStream = ichac97R3MixerGetDrvStream(pDrv, enmDir, enmPath);
1891 if (pDrvStream)
1892 {
1893 if (pDrvStream->pMixStrm)
1894 {
1895 AudioMixerSinkRemoveStream(pMixSink, pDrvStream->pMixStrm);
1896
1897 AudioMixerStreamDestroy(pDrvStream->pMixStrm, pDevIns, false /*fImmediate*/);
1898 pDrvStream->pMixStrm = NULL;
1899 }
1900 }
1901}
1902
1903/**
1904 * Removes all driver streams from a specific mixer sink.
1905 *
1906 * Called by ichac97R3StreamSetUp() and ichac97R3StreamsDestroy().
1907 *
1908 * @param pDevIns The device instance.
1909 * @param pThisCC The ring-3 AC'97 state.
1910 * @param pMixSink Mixer sink to remove audio streams from.
1911 * @param enmDir Stream direction to remove.
1912 * @param enmPath Stream destination / source to remove.
1913 */
1914static void ichac97R3MixerRemoveDrvStreams(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAUDMIXSINK pMixSink,
1915 PDMAUDIODIR enmDir, PDMAUDIOPATH enmPath)
1916{
1917 AssertPtrReturnVoid(pMixSink);
1918
1919 PAC97DRIVER pDrv;
1920 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
1921 {
1922 ichac97R3MixerRemoveDrvStream(pDevIns, pMixSink, enmDir, enmPath, pDrv);
1923 }
1924}
1925
1926
1927/**
1928 * Gets the frequency of a given stream.
1929 *
1930 * @returns The frequency. Zero if invalid stream index.
1931 * @param pThis The shared AC'97 device state.
1932 * @param idxStream The stream.
1933 */
1934DECLINLINE(uint32_t) ichach97R3CalcStreamHz(PAC97STATE pThis, uint8_t idxStream)
1935{
1936 switch (idxStream)
1937 {
1938 case AC97SOUNDSOURCE_PI_INDEX:
1939 return ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate);
1940
1941 case AC97SOUNDSOURCE_MC_INDEX:
1942 return ichac97MixerGet(pThis, AC97_MIC_ADC_Rate);
1943
1944 case AC97SOUNDSOURCE_PO_INDEX:
1945 return ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate);
1946
1947 default:
1948 AssertMsgFailedReturn(("%d\n", idxStream), 0);
1949 }
1950}
1951
1952
1953/**
1954 * Gets the PCM properties for a given stream.
1955 *
1956 * @returns pProps.
1957 * @param pThis The shared AC'97 device state.
1958 * @param idxStream Which stream
1959 * @param pProps Where to return the stream properties.
1960 */
1961DECLINLINE(PPDMAUDIOPCMPROPS) ichach97R3CalcStreamProps(PAC97STATE pThis, uint8_t idxStream, PPDMAUDIOPCMPROPS pProps)
1962{
1963 PDMAudioPropsInit(pProps, 2 /*16-bit*/, true /*signed*/, 2 /*stereo*/, ichach97R3CalcStreamHz(pThis, idxStream));
1964 return pProps;
1965}
1966
1967
1968/**
1969 * Sets up an AC'97 stream with its current mixer settings.
1970 *
1971 * This will set up an AC'97 stream with 2 (stereo) channels, 16-bit samples and
1972 * the last set sample rate in the AC'97 mixer for this stream.
1973 *
1974 * @returns VBox status code.
1975 * @retval VINF_NO_CHANGE if the streams weren't re-created.
1976 *
1977 * @param pDevIns The device instance.
1978 * @param pThis The shared AC'97 device state (shared).
1979 * @param pThisCC The shared AC'97 device state (ring-3).
1980 * @param pStream The AC'97 stream to open (shared).
1981 * @param pStreamCC The AC'97 stream to open (ring-3).
1982 * @param fForce Whether to force re-opening the stream or not.
1983 * Otherwise re-opening only will happen if the PCM properties have changed.
1984 *
1985 * @remarks This is called holding:
1986 * -# The AC'97 device lock.
1987 * -# The AC'97 stream lock.
1988 * -# The mixer sink lock (to prevent racing AIO thread).
1989 */
1990static int ichac97R3StreamSetUp(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC, PAC97STREAM pStream,
1991 PAC97STREAMR3 pStreamCC, bool fForce)
1992{
1993 /*
1994 * Assemble the stream config and get the associated mixer sink.
1995 */
1996 PDMAUDIOPCMPROPS PropsTmp;
1997 PDMAUDIOSTREAMCFG Cfg;
1998 PDMAudioStrmCfgInitWithProps(&Cfg, ichach97R3CalcStreamProps(pThis, pStream->u8SD, &PropsTmp));
1999 Assert(Cfg.enmDir != PDMAUDIODIR_UNKNOWN);
2000
2001 PAUDMIXSINK pMixSink;
2002 switch (pStream->u8SD)
2003 {
2004 case AC97SOUNDSOURCE_PI_INDEX:
2005 Cfg.enmDir = PDMAUDIODIR_IN;
2006 Cfg.enmPath = PDMAUDIOPATH_IN_LINE;
2007 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Line-In");
2008
2009 pMixSink = pThisCC->pSinkLineIn;
2010 break;
2011
2012 case AC97SOUNDSOURCE_MC_INDEX:
2013 Cfg.enmDir = PDMAUDIODIR_IN;
2014 Cfg.enmPath = PDMAUDIOPATH_IN_MIC;
2015 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Mic-In");
2016
2017 pMixSink = pThisCC->pSinkMicIn;
2018 break;
2019
2020 case AC97SOUNDSOURCE_PO_INDEX:
2021 Cfg.enmDir = PDMAUDIODIR_OUT;
2022 Cfg.enmPath = PDMAUDIOPATH_OUT_FRONT;
2023 RTStrCopy(Cfg.szName, sizeof(Cfg.szName), "Output");
2024
2025 pMixSink = pThisCC->pSinkOut;
2026 break;
2027
2028 default:
2029 AssertMsgFailedReturn(("u8SD=%d\n", pStream->u8SD), VERR_INTERNAL_ERROR_3);
2030 }
2031
2032 /*
2033 * Don't continue if the frequency is out of range (the rest of the
2034 * properties should be okay).
2035 * Note! Don't assert on this as we may easily end up here with Hz=0.
2036 */
2037 char szTmp[PDMAUDIOSTRMCFGTOSTRING_MAX];
2038 if (AudioHlpStreamCfgIsValid(&Cfg))
2039 { }
2040 else
2041 {
2042 LogFunc(("Invalid stream #%u rate: %s\n", pStreamCC->u8SD, PDMAudioStrmCfgToString(&Cfg, szTmp, sizeof(szTmp)) ));
2043 return VERR_OUT_OF_RANGE;
2044 }
2045
2046 /*
2047 * Read the buffer descriptors and check what the max distance between
2048 * interrupts are, so we can more correctly size the internal DMA buffer.
2049 *
2050 * Note! The buffer list are not fixed once the stream starts running as
2051 * with HDA, so this is just a general idea of what the guest is
2052 * up to and we cannot really make much of a plan out of it.
2053 */
2054 uint8_t const bLvi = pStream->Regs.lvi % AC97_MAX_BDLE /* paranoia */;
2055 uint8_t const bCiv = pStream->Regs.civ % AC97_MAX_BDLE /* paranoia */;
2056 uint32_t const uAddrBdl = pStream->Regs.bdbar;
2057
2058 /* Linux does this a number of times while probing/whatever the device. The
2059 IOMMU usually does allow us to read address zero, so let's skip and hope
2060 for a better config before the guest actually wants to play/record.
2061 (Note that bLvi and bCiv are also zero then, but I'm not entirely sure if
2062 that can be taken to mean anything as such, as it still indicates that
2063 BDLE00 is valid (LVI == last valid index).) */
2064 /** @todo Instead of refusing to read address zero, we should probably allow
2065 * reading address zero if explicitly programmed. But, too much work now. */
2066 if (uAddrBdl != 0)
2067 LogFlowFunc(("bdbar=%#x bLvi=%#x bCiv=%#x\n", uAddrBdl, bLvi, bCiv));
2068 else
2069 {
2070 LogFunc(("Invalid stream #%u: bdbar=%#x bLvi=%#x bCiv=%#x (%s)\n", pStreamCC->u8SD, uAddrBdl, bLvi, bCiv,
2071 PDMAudioStrmCfgToString(&Cfg, szTmp, sizeof(szTmp))));
2072 return VERR_OUT_OF_RANGE;
2073 }
2074
2075 AC97BDLE aBdl[AC97_MAX_BDLE];
2076 RT_ZERO(aBdl);
2077 PDMDevHlpPCIPhysRead(pDevIns, uAddrBdl, aBdl, sizeof(aBdl));
2078
2079 uint32_t cSamplesMax = 0;
2080 uint32_t cSamplesMin = UINT32_MAX;
2081 uint32_t cSamplesCur = 0;
2082 uint32_t cSamplesTotal = 0;
2083 uint32_t cBuffers = 1;
2084 for (uintptr_t i = bCiv; ; cBuffers++)
2085 {
2086 Log2Func(("BDLE%02u: %#x LB %#x; %#x\n", i, aBdl[i].addr, aBdl[i].ctl_len & AC97_BD_LEN_MASK, aBdl[i].ctl_len >> 16));
2087 cSamplesTotal += aBdl[i].ctl_len & AC97_BD_LEN_MASK;
2088 cSamplesCur += aBdl[i].ctl_len & AC97_BD_LEN_MASK;
2089 if (aBdl[i].ctl_len & AC97_BD_IOC)
2090 {
2091 if (cSamplesCur > cSamplesMax)
2092 cSamplesMax = cSamplesCur;
2093 if (cSamplesCur < cSamplesMin)
2094 cSamplesMin = cSamplesCur;
2095 cSamplesCur = 0;
2096 }
2097
2098 /* Advance. */
2099 if (i != bLvi)
2100 i = (i + 1) % RT_ELEMENTS(aBdl);
2101 else
2102 break;
2103 }
2104 if (!cSamplesCur)
2105 { /* likely */ }
2106 else if (!cSamplesMax)
2107 {
2108 LogFlowFunc(("%u buffers without IOC set, assuming %#x samples as the IOC period.\n", cBuffers, cSamplesMax));
2109 cSamplesMin = cSamplesMax = cSamplesCur;
2110 }
2111 else if (cSamplesCur > cSamplesMax)
2112 {
2113 LogFlowFunc(("final buffer is without IOC, using open period as max (%#x vs current max %#x).\n", cSamplesCur, cSamplesMax));
2114 cSamplesMax = cSamplesCur;
2115 }
2116 else
2117 LogFlowFunc(("final buffer is without IOC, ignoring (%#x vs current max %#x).\n", cSamplesCur, cSamplesMax));
2118
2119 uint32_t const cbDmaMinBuf = cSamplesMax * PDMAudioPropsSampleSize(&Cfg.Props) * 3; /* see further down */
2120 uint32_t const cMsDmaMinBuf = PDMAudioPropsBytesToMilli(&Cfg.Props, cbDmaMinBuf);
2121 LogRel3(("AC97: [SD%RU8] buffer length stats: total=%#x in %u buffers, min=%#x, max=%#x => min DMA buffer %u ms / %#x bytes\n",
2122 pStream->u8SD, cSamplesTotal, cBuffers, cSamplesMin, cSamplesMax, cMsDmaMinBuf, cbDmaMinBuf));
2123
2124 /*
2125 * Calculate the timer Hz / scheduling hint based on the stream frame rate.
2126 */
2127 uint32_t uTimerHz;
2128 if (pThis->uTimerHz == AC97_TIMER_HZ_DEFAULT) /* Make sure that we don't have any custom Hz rate set we want to enforce */
2129 {
2130 if (Cfg.Props.uHz > 44100) /* E.g. 48000 Hz. */
2131 uTimerHz = 200;
2132 else
2133 uTimerHz = AC97_TIMER_HZ_DEFAULT;
2134 }
2135 else
2136 uTimerHz = pThis->uTimerHz;
2137
2138 if ( uTimerHz >= 10
2139 && uTimerHz <= 500)
2140 { /* likely */ }
2141 else
2142 {
2143 LogFunc(("[SD%RU8] Adjusting uTimerHz=%u to %u\n", pStream->u8SD, uTimerHz,
2144 Cfg.Props.uHz > 44100 ? 200 : AC97_TIMER_HZ_DEFAULT));
2145 uTimerHz = Cfg.Props.uHz > 44100 ? 200 : AC97_TIMER_HZ_DEFAULT;
2146 }
2147
2148 /* Translate it to a scheduling hint. */
2149 uint32_t const cMsSchedulingHint = RT_MS_1SEC / uTimerHz;
2150
2151 /*
2152 * Calculate the circular buffer size so we can decide whether to recreate
2153 * the stream or not.
2154 *
2155 * As mentioned in the HDA code, this should be at least able to hold the
2156 * data transferred in three DMA periods and in three AIO period (whichever
2157 * is higher). However, if we assume that the DMA code will engage the DMA
2158 * timer thread (currently EMT) if the AIO thread isn't getting schduled to
2159 * transfer data thru the stack, we don't need to go overboard and double
2160 * the minimums here. The less buffer the less possible delay can build when
2161 * TM is doing catch up.
2162 */
2163 uint32_t cMsCircBuf = Cfg.enmDir == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut;
2164 cMsCircBuf = RT_MAX(cMsCircBuf, cMsDmaMinBuf);
2165 cMsCircBuf = RT_MAX(cMsCircBuf, cMsSchedulingHint * 3);
2166 cMsCircBuf = RT_MIN(cMsCircBuf, RT_MS_1SEC * 2);
2167 uint32_t const cbCircBuf = PDMAudioPropsMilliToBytes(&Cfg.Props, cMsCircBuf);
2168
2169 LogFlowFunc(("Stream %u: uTimerHz: %u -> %u; cMsSchedulingHint: %u -> %u; cbCircBuf: %#zx -> %#x (%u ms, cMsDmaMinBuf=%u)%s\n",
2170 pStreamCC->u8SD, pStreamCC->State.uTimerHz, uTimerHz,
2171 pStreamCC->State.Cfg.Device.cMsSchedulingHint, cMsSchedulingHint,
2172 pStreamCC->State.pCircBuf ? RTCircBufSize(pStreamCC->State.pCircBuf) : 0, cbCircBuf, cMsCircBuf, cMsDmaMinBuf,
2173 !pStreamCC->State.pCircBuf || RTCircBufSize(pStreamCC->State.pCircBuf) != cbCircBuf ? " - re-creating DMA buffer" : ""));
2174
2175 /*
2176 * Update the stream's timer rate and scheduling hint, re-registering the AIO
2177 * update job if necessary.
2178 */
2179 if ( pStreamCC->State.Cfg.Device.cMsSchedulingHint != cMsSchedulingHint
2180 || !pStreamCC->State.fRegisteredAsyncUpdateJob)
2181 {
2182 if (pStreamCC->State.fRegisteredAsyncUpdateJob)
2183 AudioMixerSinkRemoveUpdateJob(pMixSink, ichac97R3StreamUpdateAsyncIoJob, pStreamCC);
2184 int rc2 = AudioMixerSinkAddUpdateJob(pMixSink, ichac97R3StreamUpdateAsyncIoJob, pStreamCC,
2185 pStreamCC->State.Cfg.Device.cMsSchedulingHint);
2186 AssertRC(rc2);
2187 pStreamCC->State.fRegisteredAsyncUpdateJob = RT_SUCCESS(rc2) || rc2 == VERR_ALREADY_EXISTS;
2188 }
2189
2190 pStreamCC->State.uTimerHz = uTimerHz;
2191 Cfg.Device.cMsSchedulingHint = cMsSchedulingHint;
2192
2193 /*
2194 * Re-create the circular buffer if necessary, resetting if not.
2195 */
2196 if ( pStreamCC->State.pCircBuf
2197 && RTCircBufSize(pStreamCC->State.pCircBuf) == cbCircBuf)
2198 RTCircBufReset(pStreamCC->State.pCircBuf);
2199 else
2200 {
2201 if (pStreamCC->State.pCircBuf)
2202 RTCircBufDestroy(pStreamCC->State.pCircBuf);
2203
2204 int rc = RTCircBufCreate(&pStreamCC->State.pCircBuf, cbCircBuf);
2205 AssertRCReturnStmt(rc, pStreamCC->State.pCircBuf = NULL, rc);
2206
2207 pStreamCC->State.StatDmaBufSize = (uint32_t)RTCircBufSize(pStreamCC->State.pCircBuf);
2208 }
2209 Assert(pStreamCC->State.StatDmaBufSize == cbCircBuf);
2210
2211 /*
2212 * Only (re-)create the stream (and driver chain) if we really have to.
2213 * Otherwise avoid this and just reuse it, as this costs performance.
2214 */
2215 int rc = VINF_SUCCESS;
2216 if ( fForce
2217 || !PDMAudioStrmCfgMatchesProps(&Cfg, &pStreamCC->State.Cfg.Props)
2218 || (pStreamCC->State.nsRetrySetup && RTTimeNanoTS() >= pStreamCC->State.nsRetrySetup))
2219 {
2220 LogRel2(("AC97: Setting up stream #%u: %s\n", pStreamCC->u8SD, PDMAudioStrmCfgToString(&Cfg, szTmp, sizeof(szTmp)) ));
2221
2222 ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pMixSink, Cfg.enmDir, Cfg.enmPath);
2223
2224 rc = ichac97R3MixerAddDrvStreams(pDevIns, pThisCC, pMixSink, &Cfg);
2225 if (RT_SUCCESS(rc))
2226 {
2227 PDMAudioStrmCfgCopy(&pStreamCC->State.Cfg, &Cfg);
2228 pStreamCC->State.nsRetrySetup = 0;
2229 LogFlowFunc(("[SD%RU8] success (uHz=%u)\n", pStreamCC->u8SD, PDMAudioPropsHz(&Cfg.Props)));
2230 }
2231 else
2232 {
2233 LogFunc(("[SD%RU8] ichac97R3MixerAddDrvStreams failed: %Rrc (uHz=%u)\n",
2234 pStreamCC->u8SD, rc, PDMAudioPropsHz(&Cfg.Props)));
2235 pStreamCC->State.nsRetrySetup = RTTimeNanoTS() + 5*RT_NS_1SEC_64; /* retry in 5 seconds, unless config changes. */
2236 }
2237 }
2238 else
2239 {
2240 LogFlowFunc(("[SD%RU8] Skipping set-up (unchanged: %s)\n",
2241 pStreamCC->u8SD, PDMAudioStrmCfgToString(&Cfg, szTmp, sizeof(szTmp))));
2242 rc = VINF_NO_CHANGE;
2243 }
2244 return rc;
2245}
2246
2247
2248/**
2249 * Tears down an AC'97 stream (counter part to ichac97R3StreamSetUp).
2250 *
2251 * Empty stub at present, nothing to do here as we reuse streams and only really
2252 * re-open them if parameters changed (seldom).
2253 *
2254 * @param pStream The AC'97 stream to close (shared).
2255 */
2256static void ichac97R3StreamTearDown(PAC97STREAM pStream)
2257{
2258 RT_NOREF(pStream);
2259 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2260}
2261
2262
2263/**
2264 * Tears down and sets up an AC'97 stream on the backend side with the current
2265 * AC'97 mixer settings for this stream.
2266 *
2267 * @returns VBox status code.
2268 * @param pDevIns The device instance.
2269 * @param pThis The shared AC'97 device state.
2270 * @param pThisCC The ring-3 AC'97 device state.
2271 * @param pStream The AC'97 stream to re-open (shared).
2272 * @param pStreamCC The AC'97 stream to re-open (ring-3).
2273 * @param fForce Whether to force re-opening the stream or not.
2274 * Otherwise re-opening only will happen if the PCM properties have changed.
2275 */
2276static int ichac97R3StreamReSetUp(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
2277 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fForce)
2278{
2279 STAM_REL_PROFILE_START_NS(&pStreamCC->State.StatReSetUpChanged, r);
2280 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2281 Assert(pStream->u8SD == pStreamCC->u8SD);
2282 Assert(pStream - &pThis->aStreams[0] == pStream->u8SD);
2283 Assert(pStreamCC - &pThisCC->aStreams[0] == pStream->u8SD);
2284
2285 ichac97R3StreamTearDown(pStream);
2286 int rc = ichac97R3StreamSetUp(pDevIns, pThis, pThisCC, pStream, pStreamCC, fForce);
2287 if (rc == VINF_NO_CHANGE)
2288 STAM_REL_PROFILE_STOP_NS(&pStreamCC->State.StatReSetUpSame, r);
2289 else
2290 STAM_REL_PROFILE_STOP_NS(&pStreamCC->State.StatReSetUpChanged, r);
2291 return rc;
2292}
2293
2294
2295/**
2296 * Enables or disables an AC'97 audio stream.
2297 *
2298 * @returns VBox status code.
2299 * @param pDevIns The device instance.
2300 * @param pThis The shared AC'97 state.
2301 * @param pThisCC The ring-3 AC'97 state.
2302 * @param pStream The AC'97 stream to enable or disable (shared state).
2303 * @param pStreamCC The ring-3 stream state (matching to @a pStream).
2304 * @param fEnable Whether to enable or disable the stream.
2305 *
2306 */
2307static int ichac97R3StreamEnable(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC,
2308 PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, bool fEnable)
2309{
2310 ichac97R3StreamLock(pStreamCC);
2311 PAUDMIXSINK const pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
2312 AudioMixerSinkLock(pSink);
2313
2314 int rc = VINF_SUCCESS;
2315 /*
2316 * Enable.
2317 */
2318 if (fEnable)
2319 {
2320 /* Reset the input pre-buffering state and DMA period counter. */
2321 pStreamCC->State.fInputPreBuffered = false;
2322 pStream->uDmaPeriod = 0;
2323
2324 /* Set up (update) the AC'97 stream as needed. */
2325 rc = ichac97R3StreamSetUp(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fForce */);
2326 if (RT_SUCCESS(rc))
2327 {
2328 /* Open debug files. */
2329 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2330 { /* likely */ }
2331 else
2332 {
2333 if (!AudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileStream))
2334 AudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
2335 &pStreamCC->State.Cfg.Props);
2336 if (!AudioHlpFileIsOpen(pStreamCC->Dbg.Runtime.pFileDMA))
2337 AudioHlpFileOpen(pStreamCC->Dbg.Runtime.pFileDMA, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
2338 &pStreamCC->State.Cfg.Props);
2339 }
2340
2341 /* Do the actual enabling (won't fail as long as pSink is valid). */
2342 rc = AudioMixerSinkStart(pSink);
2343 }
2344 }
2345 /*
2346 * Disable
2347 */
2348 else
2349 {
2350 rc = AudioMixerSinkDrainAndStop(pSink, pStreamCC->State.pCircBuf ? (uint32_t)RTCircBufUsed(pStreamCC->State.pCircBuf) : 0);
2351 ichac97R3StreamTearDown(pStream);
2352 }
2353
2354 /* Make sure to leave the lock before (eventually) starting the timer. */
2355 AudioMixerSinkUnlock(pSink);
2356 ichac97R3StreamUnlock(pStreamCC);
2357 LogFunc(("[SD%RU8] fEnable=%RTbool, rc=%Rrc\n", pStream->u8SD, fEnable, rc));
2358 return rc;
2359}
2360
2361
2362/**
2363 * Returns whether an AC'97 stream is enabled or not.
2364 *
2365 * Only used by ichac97R3SaveExec().
2366 *
2367 * @returns VBox status code.
2368 * @param pThisCC The ring-3 AC'97 device state.
2369 * @param pStream Stream to return status for.
2370 */
2371static bool ichac97R3StreamIsEnabled(PAC97STATER3 pThisCC, PAC97STREAM pStream)
2372{
2373 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
2374 bool fIsEnabled = pSink && (AudioMixerSinkGetStatus(pSink) & AUDMIXSINK_STS_RUNNING);
2375
2376 LogFunc(("[SD%RU8] fIsEnabled=%RTbool\n", pStream->u8SD, fIsEnabled));
2377 return fIsEnabled;
2378}
2379
2380
2381/**
2382 * Terminates an AC'97 audio stream (VM destroy).
2383 *
2384 * This is called by ichac97R3StreamsDestroy during VM poweroff & destruction.
2385 *
2386 * @returns VBox status code.
2387 * @param pThisCC The ring-3 AC'97 state.
2388 * @param pStream The AC'97 stream to destroy (shared).
2389 * @param pStreamCC The AC'97 stream to destroy (ring-3).
2390 * @sa ichac97R3StreamConstruct
2391 */
2392static void ichac97R3StreamDestroy(PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC)
2393{
2394 LogFlowFunc(("[SD%RU8]\n", pStream->u8SD));
2395
2396 ichac97R3StreamTearDown(pStream);
2397
2398 int rc2 = RTCritSectDelete(&pStreamCC->State.CritSect);
2399 AssertRC(rc2);
2400
2401 if (pStreamCC->State.fRegisteredAsyncUpdateJob)
2402 {
2403 PAUDMIXSINK pSink = ichac97R3IndexToSink(pThisCC, pStream->u8SD);
2404 if (pSink)
2405 AudioMixerSinkRemoveUpdateJob(pSink, ichac97R3StreamUpdateAsyncIoJob, pStreamCC);
2406 pStreamCC->State.fRegisteredAsyncUpdateJob = false;
2407 }
2408
2409 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2410 { /* likely */ }
2411 else
2412 {
2413 AudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileStream);
2414 pStreamCC->Dbg.Runtime.pFileStream = NULL;
2415
2416 AudioHlpFileDestroy(pStreamCC->Dbg.Runtime.pFileDMA);
2417 pStreamCC->Dbg.Runtime.pFileDMA = NULL;
2418 }
2419
2420 if (pStreamCC->State.pCircBuf)
2421 {
2422 RTCircBufDestroy(pStreamCC->State.pCircBuf);
2423 pStreamCC->State.pCircBuf = NULL;
2424 }
2425
2426 LogFlowFuncLeave();
2427}
2428
2429
2430/**
2431 * Initializes an AC'97 audio stream (VM construct).
2432 *
2433 * This is only called by ichac97R3Construct.
2434 *
2435 * @returns VBox status code.
2436 * @param pThisCC The ring-3 AC'97 state.
2437 * @param pStream The AC'97 stream to create (shared).
2438 * @param pStreamCC The AC'97 stream to create (ring-3).
2439 * @param u8SD Stream descriptor number to assign.
2440 * @sa ichac97R3StreamDestroy
2441 */
2442static int ichac97R3StreamConstruct(PAC97STATER3 pThisCC, PAC97STREAM pStream, PAC97STREAMR3 pStreamCC, uint8_t u8SD)
2443{
2444 LogFunc(("[SD%RU8] pStream=%p\n", u8SD, pStream));
2445
2446 AssertReturn(u8SD < AC97_MAX_STREAMS, VERR_INVALID_PARAMETER);
2447 pStream->u8SD = u8SD;
2448 pStreamCC->u8SD = u8SD;
2449
2450 int rc = RTCritSectInit(&pStreamCC->State.CritSect);
2451 AssertRCReturn(rc, rc);
2452
2453 pStreamCC->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
2454
2455 if (RT_LIKELY(!pStreamCC->Dbg.Runtime.fEnabled))
2456 { /* likely */ }
2457 else
2458 {
2459 int rc2 = AudioHlpFileCreateF(&pStreamCC->Dbg.Runtime.pFileStream, AUDIOHLPFILE_FLAGS_NONE, AUDIOHLPFILETYPE_WAV,
2460 pThisCC->Dbg.pszOutPath, AUDIOHLPFILENAME_FLAGS_NONE, 0 /*uInstance*/,
2461 ichac97R3GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN
2462 ? "ac97StreamWriteSD%RU8" : "ac97StreamReadSD%RU8", pStream->u8SD);
2463 AssertRC(rc2);
2464
2465 rc2 = AudioHlpFileCreateF(&pStreamCC->Dbg.Runtime.pFileDMA, AUDIOHLPFILE_FLAGS_NONE, AUDIOHLPFILETYPE_WAV,
2466 pThisCC->Dbg.pszOutPath, AUDIOHLPFILENAME_FLAGS_NONE, 0 /*uInstance*/,
2467 ichac97R3GetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN
2468 ? "ac97DMAWriteSD%RU8" : "ac97DMAReadSD%RU8", pStream->u8SD);
2469 AssertRC(rc2);
2470
2471 /* Delete stale debugging files from a former run. */
2472 AudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileStream);
2473 AudioHlpFileDelete(pStreamCC->Dbg.Runtime.pFileDMA);
2474 }
2475
2476 return rc;
2477}
2478
2479#endif /* IN_RING3 */
2480
2481
2482/*********************************************************************************************************************************
2483* NABM I/O Port Handlers (Global + Stream) *
2484*********************************************************************************************************************************/
2485
2486/**
2487 * @callback_method_impl{FNIOMIOPORTNEWIN}
2488 */
2489static DECLCALLBACK(VBOXSTRICTRC)
2490ichac97IoPortNabmRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2491{
2492 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2493 RT_NOREF(pvUser);
2494
2495 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
2496
2497 /* Get the index of the NABMBAR port. */
2498 if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
2499 && offPort != AC97_GLOB_CNT)
2500 {
2501 PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
2502
2503 switch (cb)
2504 {
2505 case 1:
2506 switch (offPort & AC97_NABM_OFF_MASK)
2507 {
2508 case AC97_NABM_OFF_CIV:
2509 /* Current Index Value Register */
2510 *pu32 = pStream->Regs.civ;
2511 Log3Func(("CIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2512 break;
2513 case AC97_NABM_OFF_LVI:
2514 /* Last Valid Index Register */
2515 *pu32 = pStream->Regs.lvi;
2516 Log3Func(("LVI[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2517 break;
2518 case AC97_NABM_OFF_PIV:
2519 /* Prefetched Index Value Register */
2520 *pu32 = pStream->Regs.piv;
2521 Log3Func(("PIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2522 break;
2523 case AC97_NABM_OFF_CR:
2524 /* Control Register */
2525 *pu32 = pStream->Regs.cr;
2526 Log3Func(("CR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2527 break;
2528 case AC97_NABM_OFF_SR:
2529 /* Status Register (lower part) */
2530 *pu32 = RT_LO_U8(pStream->Regs.sr);
2531 Log3Func(("SRb[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2532 break;
2533 default:
2534 *pu32 = UINT32_MAX;
2535 LogRel2(("AC97: Warning: Unimplemented NAMB read offPort=%#x LB 1 (line " RT_XSTR(__LINE__) ")\n", offPort));
2536 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2537 break;
2538 }
2539 break;
2540
2541 case 2:
2542 switch (offPort & AC97_NABM_OFF_MASK)
2543 {
2544 case AC97_NABM_OFF_SR:
2545 /* Status Register */
2546 *pu32 = pStream->Regs.sr;
2547 Log3Func(("SR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2548 break;
2549 case AC97_NABM_OFF_PICB:
2550 /* Position in Current Buffer
2551 * ---
2552 * We can do DMA work here if we want to give the guest a better impression of
2553 * the DMA engine of a real device. For ring-0 we'd have to add some buffering
2554 * to AC97STREAM (4K or so), only going to ring-3 if full. Ring-3 would commit
2555 * that buffer and write directly to the internal DMA pCircBuf.
2556 *
2557 * Checking a Linux guest (knoppix 8.6.2), I see some PIC reads each DMA cycle,
2558 * however most of these happen very very early, 1-10% into the buffer. So, I'm
2559 * not sure if it's worth it, as it'll be a big complication... */
2560#if 1
2561 *pu32 = pStream->Regs.picb;
2562# ifdef LOG_ENABLED
2563 if (LogIs3Enabled())
2564 {
2565 uint64_t offPeriod = PDMDevHlpTimerGet(pDevIns, pStream->hTimer) - pStream->uArmedTs;
2566 Log3Func(("PICB[%d] -> %#x (%RU64 of %RU64 ticks / %RU64%% into DMA period #%RU32)\n",
2567 AC97_PORT2IDX(offPort), *pu32, offPeriod, pStream->cDmaPeriodTicks,
2568 pStream->cDmaPeriodTicks ? offPeriod * 100 / pStream->cDmaPeriodTicks : 0,
2569 pStream->uDmaPeriod));
2570 }
2571# endif
2572#else /* For trying out sub-buffer PICB. Will cause distortions, but can be helpful to see if it help eliminate other issues. */
2573 if ( (pStream->Regs.cr & AC97_CR_RPBM)
2574 && !(pStream->Regs.sr & AC97_SR_DCH)
2575 && pStream->uArmedTs > 0
2576 && pStream->cDmaPeriodTicks > 0)
2577 {
2578 uint64_t const offPeriod = PDMDevHlpTimerGet(pDevIns, pStream->hTimer) - pStream->uArmedTs;
2579 uint32_t cSamples;
2580 if (offPeriod < pStream->cDmaPeriodTicks)
2581 cSamples = pStream->Regs.picb * offPeriod / pStream->cDmaPeriodTicks;
2582 else
2583 cSamples = pStream->Regs.picb;
2584 if (cSamples + 8 < pStream->Regs.picb)
2585 { /* likely */ }
2586 else if (pStream->Regs.picb > 8)
2587 cSamples = pStream->Regs.picb - 8;
2588 else
2589 cSamples = 0;
2590 *pu32 = pStream->Regs.picb - cSamples;
2591 Log3Func(("PICB[%d] -> %#x (PICB=%#x cSamples=%#x offPeriod=%RU64 of %RU64 / %RU64%%)\n",
2592 AC97_PORT2IDX(offPort), *pu32, pStream->Regs.picb, cSamples, offPeriod,
2593 pStream->cDmaPeriodTicks, offPeriod * 100 / pStream->cDmaPeriodTicks));
2594 }
2595 else
2596 {
2597 *pu32 = pStream->Regs.picb;
2598 Log3Func(("PICB[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2599 }
2600#endif
2601 break;
2602 default:
2603 *pu32 = UINT32_MAX;
2604 LogRel2(("AC97: Warning: Unimplemented NAMB read offPort=%#x LB 2 (line " RT_XSTR(__LINE__) ")\n", offPort));
2605 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2606 break;
2607 }
2608 break;
2609
2610 case 4:
2611 switch (offPort & AC97_NABM_OFF_MASK)
2612 {
2613 case AC97_NABM_OFF_BDBAR:
2614 /* Buffer Descriptor Base Address Register */
2615 *pu32 = pStream->Regs.bdbar;
2616 Log3Func(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32));
2617 break;
2618 case AC97_NABM_OFF_CIV:
2619 /* 32-bit access: Current Index Value Register +
2620 * Last Valid Index Register +
2621 * Status Register */
2622 *pu32 = pStream->Regs.civ | ((uint32_t)pStream->Regs.lvi << 8) | ((uint32_t)pStream->Regs.sr << 16);
2623 Log3Func(("CIV LVI SR[%d] -> %#x, %#x, %#x\n",
2624 AC97_PORT2IDX(offPort), pStream->Regs.civ, pStream->Regs.lvi, pStream->Regs.sr));
2625 break;
2626 case AC97_NABM_OFF_PICB:
2627 /* 32-bit access: Position in Current Buffer Register +
2628 * Prefetched Index Value Register +
2629 * Control Register */
2630 *pu32 = pStream->Regs.picb | ((uint32_t)pStream->Regs.piv << 16) | ((uint32_t)pStream->Regs.cr << 24);
2631 Log3Func(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n",
2632 AC97_PORT2IDX(offPort), *pu32, pStream->Regs.picb, pStream->Regs.piv, pStream->Regs.cr));
2633 break;
2634
2635 default:
2636 *pu32 = UINT32_MAX;
2637 LogRel2(("AC97: Warning: Unimplemented NAMB read offPort=%#x LB 4 (line " RT_XSTR(__LINE__) ")\n", offPort));
2638 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2639 break;
2640 }
2641 break;
2642
2643 default:
2644 DEVAC97_UNLOCK(pDevIns, pThis);
2645 AssertFailed();
2646 return VERR_IOM_IOPORT_UNUSED;
2647 }
2648 }
2649 else
2650 {
2651 switch (cb)
2652 {
2653 case 1:
2654 switch (offPort)
2655 {
2656 case AC97_CAS:
2657 /* Codec Access Semaphore Register */
2658 Log3Func(("CAS %d\n", pThis->cas));
2659 *pu32 = pThis->cas;
2660 pThis->cas = 1;
2661 break;
2662 default:
2663 *pu32 = UINT32_MAX;
2664 LogRel2(("AC97: Warning: Unimplemented NAMB read offPort=%#x LB 1 (line " RT_XSTR(__LINE__) ")\n", offPort));
2665 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2666 break;
2667 }
2668 break;
2669
2670 case 2:
2671 *pu32 = UINT32_MAX;
2672 LogRel2(("AC97: Warning: Unimplemented NAMB read offPort=%#x LB 2 (line " RT_XSTR(__LINE__) ")\n", offPort));
2673 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2674 break;
2675
2676 case 4:
2677 switch (offPort)
2678 {
2679 case AC97_GLOB_CNT:
2680 /* Global Control */
2681 *pu32 = pThis->glob_cnt;
2682 Log3Func(("glob_cnt -> %#x\n", *pu32));
2683 break;
2684 case AC97_GLOB_STA:
2685 /* Global Status */
2686 *pu32 = pThis->glob_sta | AC97_GS_S0CR;
2687 Log3Func(("glob_sta -> %#x\n", *pu32));
2688 break;
2689 default:
2690 *pu32 = UINT32_MAX;
2691 LogRel2(("AC97: Warning: Unimplemented NAMB read offPort=%#x LB 4 (line " RT_XSTR(__LINE__) ")\n", offPort));
2692 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads);
2693 break;
2694 }
2695 break;
2696
2697 default:
2698 DEVAC97_UNLOCK(pDevIns, pThis);
2699 AssertFailed();
2700 return VERR_IOM_IOPORT_UNUSED;
2701 }
2702 }
2703
2704 DEVAC97_UNLOCK(pDevIns, pThis);
2705 return VINF_SUCCESS;
2706}
2707
2708
2709/**
2710 * @callback_method_impl{FNIOMIOPORTNEWOUT}
2711 */
2712static DECLCALLBACK(VBOXSTRICTRC)
2713ichac97IoPortNabmWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2714{
2715 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
2716#ifdef IN_RING3
2717 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
2718#endif
2719 RT_NOREF(pvUser);
2720
2721 VBOXSTRICTRC rc = VINF_SUCCESS;
2722 if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS
2723 && offPort != AC97_GLOB_CNT)
2724 {
2725#ifdef IN_RING3
2726 PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[AC97_PORT2IDX(offPort)];
2727#endif
2728 PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)];
2729
2730 switch (cb)
2731 {
2732 case 1:
2733 switch (offPort & AC97_NABM_OFF_MASK)
2734 {
2735 /*
2736 * Last Valid Index.
2737 */
2738 case AC97_NABM_OFF_LVI:
2739 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
2740
2741 if ( !(pStream->Regs.sr & AC97_SR_DCH)
2742 || !(pStream->Regs.cr & AC97_CR_RPBM))
2743 {
2744 pStream->Regs.lvi = u32 % AC97_MAX_BDLE;
2745 STAM_REL_COUNTER_INC(&pStream->StatWriteLvi);
2746 DEVAC97_UNLOCK(pDevIns, pThis);
2747 Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32));
2748 }
2749 else
2750 {
2751#ifdef IN_RING3
2752 /* Recover from underflow situation where CIV caught up with LVI
2753 and the DMA processing stopped. We clear the status condition,
2754 update LVI and then try to load the next BDLE. Unfortunately,
2755 we cannot do this from ring-0 as much of the BDLE state is
2756 ring-3 only. */
2757 pStream->Regs.sr &= ~(AC97_SR_DCH | AC97_SR_CELV);
2758 pStream->Regs.lvi = u32 % AC97_MAX_BDLE;
2759 if (ichac97R3StreamFetchNextBdle(pDevIns, pStream, pStreamCC))
2760 ichac97StreamUpdateSR(pDevIns, pThis, pStream, pStream->Regs.sr | AC97_SR_BCIS);
2761
2762 /* We now have to re-arm the DMA timer according to the new BDLE length.
2763 This means leaving the device lock to avoid virtual sync lock order issues. */
2764 ichac97R3StreamTransferUpdate(pDevIns, pStream, pStreamCC);
2765 uint64_t const cTicksToDeadline = pStream->cDmaPeriodTicks;
2766
2767 /** @todo Stop the DMA timer when we get into the AC97_SR_CELV situation to
2768 * avoid potential race here. */
2769 STAM_REL_COUNTER_INC(&pStreamCC->State.StatWriteLviRecover);
2770 DEVAC97_UNLOCK(pDevIns, pThis);
2771
2772 LogFunc(("[SD%RU8] LVI <- %#x; CIV=%#x PIV=%#x SR=%#x cTicksToDeadline=%#RX64 [recovering]\n",
2773 pStream->u8SD, u32, pStream->Regs.civ, pStream->Regs.piv, pStream->Regs.sr, cTicksToDeadline));
2774
2775 int rc2 = PDMDevHlpTimerSetRelative(pDevIns, pStream->hTimer, cTicksToDeadline, &pStream->uArmedTs);
2776 AssertRC(rc2);
2777#else
2778 DEVAC97_UNLOCK(pDevIns, pThis);
2779 rc = VINF_IOM_R3_IOPORT_WRITE;
2780#endif
2781 }
2782 break;
2783
2784 /*
2785 * Control Registers.
2786 */
2787 case AC97_NABM_OFF_CR:
2788 {
2789#ifdef IN_RING3
2790 DEVAC97_LOCK(pDevIns, pThis);
2791 STAM_REL_COUNTER_INC(&pStreamCC->State.StatWriteCr);
2792
2793 uint32_t const fCrChanged = pStream->Regs.cr ^ u32;
2794 Log3Func(("[SD%RU8] CR <- %#x (was %#x; changed %#x)\n", pStream->u8SD, u32, pStream->Regs.cr, fCrChanged));
2795
2796 /*
2797 * Busmaster reset.
2798 */
2799 if (u32 & AC97_CR_RR)
2800 {
2801 STAM_REL_PROFILE_START_NS(&pStreamCC->State.StatReset, r);
2802 LogFunc(("[SD%RU8] Reset\n", pStream->u8SD));
2803
2804 /* Make sure that Run/Pause Bus Master bit (RPBM) is cleared (0).
2805 3.2.7 in 302349-003 says RPBM be must be clear when resetting
2806 and that behavior is undefined if it's set. */
2807 ASSERT_GUEST_STMT((pStream->Regs.cr & AC97_CR_RPBM) == 0,
2808 ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream,
2809 pStreamCC, false /* fEnable */));
2810
2811 ichac97R3StreamReset(pThis, pStream, pStreamCC);
2812
2813 ichac97StreamUpdateSR(pDevIns, pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */
2814
2815 DEVAC97_UNLOCK(pDevIns, pThis);
2816 STAM_REL_PROFILE_STOP_NS(&pStreamCC->State.StatReset, r);
2817 break;
2818 }
2819
2820 /*
2821 * Write the new value to the register and if RPBM didn't change we're done.
2822 */
2823 pStream->Regs.cr = u32 & AC97_CR_VALID_MASK;
2824
2825 if (!(fCrChanged & AC97_CR_RPBM))
2826 DEVAC97_UNLOCK(pDevIns, pThis); /* Probably not so likely, but avoid one extra intentation level. */
2827 /*
2828 * Pause busmaster.
2829 */
2830 else if (!(pStream->Regs.cr & AC97_CR_RPBM))
2831 {
2832 STAM_REL_PROFILE_START_NS(&pStreamCC->State.StatStop, p);
2833 LogFunc(("[SD%RU8] Pause busmaster (disable stream) SR=%#x -> %#x\n",
2834 pStream->u8SD, pStream->Regs.sr, pStream->Regs.sr | AC97_SR_DCH));
2835 ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, false /* fEnable */);
2836 pStream->Regs.sr |= AC97_SR_DCH;
2837
2838 DEVAC97_UNLOCK(pDevIns, pThis);
2839 STAM_REL_PROFILE_STOP_NS(&pStreamCC->State.StatStop, p);
2840 }
2841 /*
2842 * Run busmaster.
2843 */
2844 else
2845 {
2846 STAM_REL_PROFILE_START_NS(&pStreamCC->State.StatStart, r);
2847 LogFunc(("[SD%RU8] Run busmaster (enable stream) SR=%#x -> %#x\n",
2848 pStream->u8SD, pStream->Regs.sr, pStream->Regs.sr & ~AC97_SR_DCH));
2849 pStream->Regs.sr &= ~AC97_SR_DCH;
2850
2851 if (ichac97R3StreamFetchNextBdle(pDevIns, pStream, pStreamCC))
2852 ichac97StreamUpdateSR(pDevIns, pThis, pStream, pStream->Regs.sr | AC97_SR_BCIS);
2853# ifdef LOG_ENABLED
2854 if (LogIsFlowEnabled())
2855 ichac97R3DbgPrintBdl(pDevIns, pThis, pStream, PDMDevHlpDBGFInfoLogHlp(pDevIns), "ichac97IoPortNabmWrite: ");
2856# endif
2857 ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, true /* fEnable */);
2858
2859 /*
2860 * Arm the DMA timer. Must drop the AC'97 device lock first as it would
2861 * create a lock order violation with the virtual sync time lock otherwise.
2862 */
2863 ichac97R3StreamTransferUpdate(pDevIns, pStream, pStreamCC);
2864 uint64_t const cTicksToDeadline = pStream->cDmaPeriodTicks;
2865
2866 DEVAC97_UNLOCK(pDevIns, pThis);
2867
2868 /** @todo for output streams we could probably service this a little bit
2869 * earlier if we push it, just to reduce the lag... For HDA we do a
2870 * DMA run immediately after the stream is enabled. */
2871 int rc2 = PDMDevHlpTimerSetRelative(pDevIns, pStream->hTimer, cTicksToDeadline, &pStream->uArmedTs);
2872 AssertRC(rc2);
2873
2874 STAM_REL_PROFILE_STOP_NS(&pStreamCC->State.StatStart, r);
2875 }
2876#else /* !IN_RING3 */
2877 rc = VINF_IOM_R3_IOPORT_WRITE;
2878#endif
2879 break;
2880 }
2881
2882 /*
2883 * Status Registers.
2884 */
2885 case AC97_NABM_OFF_SR:
2886 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
2887 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
2888 STAM_REL_COUNTER_INC(&pStream->StatWriteSr1);
2889 DEVAC97_UNLOCK(pDevIns, pThis);
2890 break;
2891
2892 default:
2893 /* Linux tries to write CIV. */
2894 LogRel2(("AC97: Warning: Unimplemented NAMB write offPort=%#x%s <- %#x LB 1 (line " RT_XSTR(__LINE__) ")\n",
2895 offPort, (offPort & AC97_NABM_OFF_MASK) == AC97_NABM_OFF_CIV ? " (CIV)" : "" , u32));
2896 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
2897 break;
2898 }
2899 break;
2900
2901 case 2:
2902 switch (offPort & AC97_NABM_OFF_MASK)
2903 {
2904 case AC97_NABM_OFF_SR:
2905 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
2906 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32);
2907 STAM_REL_COUNTER_INC(&pStream->StatWriteSr2);
2908 DEVAC97_UNLOCK(pDevIns, pThis);
2909 break;
2910 default:
2911 LogRel2(("AC97: Warning: Unimplemented NAMB write offPort=%#x <- %#x LB 2 (line " RT_XSTR(__LINE__) ")\n", offPort, u32));
2912 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
2913 break;
2914 }
2915 break;
2916
2917 case 4:
2918 switch (offPort & AC97_NABM_OFF_MASK)
2919 {
2920 case AC97_NABM_OFF_BDBAR:
2921 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
2922 /* Buffer Descriptor list Base Address Register */
2923 pStream->Regs.bdbar = u32 & ~(uint32_t)3;
2924 Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(offPort), u32, pStream->Regs.bdbar));
2925 STAM_REL_COUNTER_INC(&pStream->StatWriteBdBar);
2926 DEVAC97_UNLOCK(pDevIns, pThis);
2927 break;
2928 default:
2929 LogRel2(("AC97: Warning: Unimplemented NAMB write offPort=%#x <- %#x LB 4 (line " RT_XSTR(__LINE__) ")\n", offPort, u32));
2930 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
2931 break;
2932 }
2933 break;
2934
2935 default:
2936 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
2937 break;
2938 }
2939 }
2940 else
2941 {
2942 switch (cb)
2943 {
2944 case 1:
2945 LogRel2(("AC97: Warning: Unimplemented NAMB write offPort=%#x <- %#x LB 1 (line " RT_XSTR(__LINE__) ")\n", offPort, u32));
2946 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
2947 break;
2948
2949 case 2:
2950 LogRel2(("AC97: Warning: Unimplemented NAMB write offPort=%#x <- %#x LB 2 (line " RT_XSTR(__LINE__) ")\n", offPort, u32));
2951 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
2952 break;
2953
2954 case 4:
2955 switch (offPort)
2956 {
2957 case AC97_GLOB_CNT:
2958 /* Global Control */
2959 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
2960 if (u32 & AC97_GC_WR)
2961 ichac97WarmReset(pThis);
2962 if (u32 & AC97_GC_CR)
2963 ichac97ColdReset(pThis);
2964 if (!(u32 & (AC97_GC_WR | AC97_GC_CR)))
2965 pThis->glob_cnt = u32 & AC97_GC_VALID_MASK;
2966 Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt));
2967 DEVAC97_UNLOCK(pDevIns, pThis);
2968 break;
2969 case AC97_GLOB_STA:
2970 /* Global Status */
2971 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
2972 pThis->glob_sta &= ~(u32 & AC97_GS_WCLEAR_MASK);
2973 pThis->glob_sta |= (u32 & ~(AC97_GS_WCLEAR_MASK | AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK;
2974 Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta));
2975 DEVAC97_UNLOCK(pDevIns, pThis);
2976 break;
2977 default:
2978 LogRel2(("AC97: Warning: Unimplemented NAMB write offPort=%#x <- %#x LB 4 (line " RT_XSTR(__LINE__) ")\n", offPort, u32));
2979 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites);
2980 break;
2981 }
2982 break;
2983
2984 default:
2985 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb));
2986 break;
2987 }
2988 }
2989
2990 return rc;
2991}
2992
2993
2994/*********************************************************************************************************************************
2995* Mixer & NAM I/O handlers *
2996*********************************************************************************************************************************/
2997
2998/**
2999 * Sets a AC'97 mixer control to a specific value.
3000 *
3001 * @returns VBox status code.
3002 * @param pThis The shared AC'97 state.
3003 * @param uMixerIdx Mixer control to set value for.
3004 * @param uVal Value to set.
3005 */
3006static void ichac97MixerSet(PAC97STATE pThis, uint8_t uMixerIdx, uint16_t uVal)
3007{
3008 AssertMsgReturnVoid(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
3009 ("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)));
3010
3011 LogRel2(("AC97: Setting mixer index #%RU8 to %RU16 (%RU8 %RU8)\n", uMixerIdx, uVal, RT_HI_U8(uVal), RT_LO_U8(uVal)));
3012
3013 pThis->mixer_data[uMixerIdx + 0] = RT_LO_U8(uVal);
3014 pThis->mixer_data[uMixerIdx + 1] = RT_HI_U8(uVal);
3015}
3016
3017
3018/**
3019 * Gets a value from a specific AC'97 mixer control.
3020 *
3021 * @returns Retrieved mixer control value.
3022 * @param pThis The shared AC'97 state.
3023 * @param uMixerIdx Mixer control to get value for.
3024 */
3025static uint16_t ichac97MixerGet(PAC97STATE pThis, uint32_t uMixerIdx)
3026{
3027 AssertMsgReturn(uMixerIdx + 2U <= sizeof(pThis->mixer_data),
3028 ("Index %RU8 out of bounds (%zu)\n", uMixerIdx, sizeof(pThis->mixer_data)),
3029 UINT16_MAX);
3030 return RT_MAKE_U16(pThis->mixer_data[uMixerIdx + 0], pThis->mixer_data[uMixerIdx + 1]);
3031}
3032
3033#ifdef IN_RING3
3034
3035/**
3036 * Sets the volume of a specific AC'97 mixer control.
3037 *
3038 * This currently only supports attenuation -- gain support is currently not implemented.
3039 *
3040 * @returns VBox status code.
3041 * @param pThis The shared AC'97 state.
3042 * @param pThisCC The ring-3 AC'97 state.
3043 * @param index AC'97 mixer index to set volume for.
3044 * @param enmMixerCtl Corresponding audio mixer sink.
3045 * @param uVal Volume value to set.
3046 */
3047static int ichac97R3MixerSetVolume(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
3048{
3049 /*
3050 * From AC'97 SoundMax Codec AD1981A/AD1981B:
3051 * "Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the
3052 * D5 or D13 bits are set to 1, their respective lower five volume bits are automatically
3053 * set to 1 by the Codec logic. On readback, all lower 5 bits will read ones whenever
3054 * these bits are set to 1."
3055 *
3056 * Linux ALSA depends on this behavior to detect that only 5 bits are used for volume
3057 * control and the optional 6th bit is not used. Note that this logic only applies to the
3058 * master volume controls.
3059 */
3060 if ( index == AC97_Master_Volume_Mute
3061 || index == AC97_Headphone_Volume_Mute
3062 || index == AC97_Master_Volume_Mono_Mute)
3063 {
3064 if (uVal & RT_BIT(5)) /* D5 bit set? */
3065 uVal |= RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0);
3066 if (uVal & RT_BIT(13)) /* D13 bit set? */
3067 uVal |= RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8);
3068 }
3069
3070 const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
3071 uint8_t uCtlAttLeft = (uVal >> 8) & AC97_BARS_VOL_MASK;
3072 uint8_t uCtlAttRight = uVal & AC97_BARS_VOL_MASK;
3073
3074 /* For the master and headphone volume, 0 corresponds to 0dB attenuation. For the other
3075 * volume controls, 0 means 12dB gain and 8 means unity gain.
3076 */
3077 if (index != AC97_Master_Volume_Mute && index != AC97_Headphone_Volume_Mute)
3078 {
3079# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
3080 /* NB: Currently there is no gain support, only attenuation. */
3081 uCtlAttLeft = uCtlAttLeft < 8 ? 0 : uCtlAttLeft - 8;
3082 uCtlAttRight = uCtlAttRight < 8 ? 0 : uCtlAttRight - 8;
3083# endif
3084 }
3085 Assert(uCtlAttLeft <= 255 / AC97_DB_FACTOR);
3086 Assert(uCtlAttRight <= 255 / AC97_DB_FACTOR);
3087
3088 LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
3089 LogFunc(("uCtlAttLeft=%RU8, uCtlAttRight=%RU8 ", uCtlAttLeft, uCtlAttRight));
3090
3091 /*
3092 * For AC'97 volume controls, each additional step means -1.5dB attenuation with
3093 * zero being maximum. In contrast, we're internally using 255 (PDMAUDIO_VOLUME_MAX)
3094 * steps, each -0.375dB, where 0 corresponds to -96dB and 255 corresponds to 0dB.
3095 */
3096 uint8_t lVol = PDMAUDIO_VOLUME_MAX - uCtlAttLeft * AC97_DB_FACTOR;
3097 uint8_t rVol = PDMAUDIO_VOLUME_MAX - uCtlAttRight * AC97_DB_FACTOR;
3098
3099 Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
3100
3101 int rc = VINF_SUCCESS;
3102
3103 if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
3104 {
3105 PDMAUDIOVOLUME Vol;
3106 PDMAudioVolumeInitFromStereo(&Vol, fCtlMuted, lVol, rVol);
3107
3108 PAUDMIXSINK pSink = NULL;
3109 switch (enmMixerCtl)
3110 {
3111 case PDMAUDIOMIXERCTL_VOLUME_MASTER:
3112 rc = AudioMixerSetMasterVolume(pThisCC->pMixer, &Vol);
3113 break;
3114
3115 case PDMAUDIOMIXERCTL_FRONT:
3116 pSink = pThisCC->pSinkOut;
3117 break;
3118
3119 case PDMAUDIOMIXERCTL_MIC_IN:
3120 case PDMAUDIOMIXERCTL_LINE_IN:
3121 /* These are recognized but do nothing. */
3122 break;
3123
3124 default:
3125 AssertFailed();
3126 rc = VERR_NOT_SUPPORTED;
3127 break;
3128 }
3129
3130 if (pSink)
3131 rc = AudioMixerSinkSetVolume(pSink, &Vol);
3132 }
3133
3134 ichac97MixerSet(pThis, index, uVal);
3135
3136 if (RT_FAILURE(rc))
3137 LogFlowFunc(("Failed with %Rrc\n", rc));
3138
3139 return rc;
3140}
3141
3142/**
3143 * Sets the gain of a specific AC'97 recording control.
3144 *
3145 * @note Gain support is currently not implemented in PDM audio.
3146 *
3147 * @returns VBox status code.
3148 * @param pThis The shared AC'97 state.
3149 * @param pThisCC The ring-3 AC'97 state.
3150 * @param index AC'97 mixer index to set volume for.
3151 * @param enmMixerCtl Corresponding audio mixer sink.
3152 * @param uVal Volume value to set.
3153 */
3154static int ichac97R3MixerSetGain(PAC97STATE pThis, PAC97STATER3 pThisCC, int index, PDMAUDIOMIXERCTL enmMixerCtl, uint32_t uVal)
3155{
3156 /*
3157 * For AC'97 recording controls, each additional step means +1.5dB gain with
3158 * zero being 0dB gain and 15 being +22.5dB gain.
3159 */
3160 bool const fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1;
3161 uint8_t uCtlGainLeft = (uVal >> 8) & AC97_BARS_GAIN_MASK;
3162 uint8_t uCtlGainRight = uVal & AC97_BARS_GAIN_MASK;
3163
3164 Assert(uCtlGainLeft <= 255 / AC97_DB_FACTOR);
3165 Assert(uCtlGainRight <= 255 / AC97_DB_FACTOR);
3166
3167 LogFunc(("index=0x%x, uVal=%RU32, enmMixerCtl=%RU32\n", index, uVal, enmMixerCtl));
3168 LogFunc(("uCtlGainLeft=%RU8, uCtlGainRight=%RU8 ", uCtlGainLeft, uCtlGainRight));
3169
3170 uint8_t lVol = PDMAUDIO_VOLUME_MAX + uCtlGainLeft * AC97_DB_FACTOR;
3171 uint8_t rVol = PDMAUDIO_VOLUME_MAX + uCtlGainRight * AC97_DB_FACTOR;
3172
3173 /* We do not currently support gain. Since AC'97 does not support attenuation
3174 * for the recording input, the best we can do is set the maximum volume.
3175 */
3176# ifndef VBOX_WITH_AC97_GAIN_SUPPORT
3177 /* NB: Currently there is no gain support, only attenuation. Since AC'97 does not
3178 * support attenuation for the recording inputs, the best we can do is set the
3179 * maximum volume.
3180 */
3181 lVol = rVol = PDMAUDIO_VOLUME_MAX;
3182# endif
3183
3184 Log(("-> fMuted=%RTbool, lVol=%RU8, rVol=%RU8\n", fCtlMuted, lVol, rVol));
3185
3186 int rc = VINF_SUCCESS;
3187
3188 if (pThisCC->pMixer) /* Device can be in reset state, so no mixer available. */
3189 {
3190 PDMAUDIOVOLUME Vol;
3191 PDMAudioVolumeInitFromStereo(&Vol, fCtlMuted, lVol, rVol);
3192
3193 PAUDMIXSINK pSink = NULL;
3194 switch (enmMixerCtl)
3195 {
3196 case PDMAUDIOMIXERCTL_MIC_IN:
3197 pSink = pThisCC->pSinkMicIn;
3198 break;
3199
3200 case PDMAUDIOMIXERCTL_LINE_IN:
3201 pSink = pThisCC->pSinkLineIn;
3202 break;
3203
3204 default:
3205 AssertFailed();
3206 rc = VERR_NOT_SUPPORTED;
3207 break;
3208 }
3209
3210 if (pSink)
3211 {
3212 rc = AudioMixerSinkSetVolume(pSink, &Vol);
3213 /* There is only one AC'97 recording gain control. If line in
3214 * is changed, also update the microphone. If the optional dedicated
3215 * microphone is changed, only change that.
3216 * NB: The codecs we support do not have the dedicated microphone control.
3217 */
3218 if (pSink == pThisCC->pSinkLineIn && pThisCC->pSinkMicIn)
3219 rc = AudioMixerSinkSetVolume(pSink, &Vol);
3220 }
3221 }
3222
3223 ichac97MixerSet(pThis, index, uVal);
3224
3225 if (RT_FAILURE(rc))
3226 LogFlowFunc(("Failed with %Rrc\n", rc));
3227
3228 return rc;
3229}
3230
3231
3232/**
3233 * Converts an AC'97 recording source index to a PDM audio recording source.
3234 *
3235 * @returns PDM audio recording source.
3236 * @param uIdx AC'97 index to convert.
3237 */
3238static PDMAUDIOPATH ichac97R3IdxToRecSource(uint8_t uIdx)
3239{
3240 switch (uIdx)
3241 {
3242 case AC97_REC_MIC: return PDMAUDIOPATH_IN_MIC;
3243 case AC97_REC_CD: return PDMAUDIOPATH_IN_CD;
3244 case AC97_REC_VIDEO: return PDMAUDIOPATH_IN_VIDEO;
3245 case AC97_REC_AUX: return PDMAUDIOPATH_IN_AUX;
3246 case AC97_REC_LINE_IN: return PDMAUDIOPATH_IN_LINE;
3247 case AC97_REC_PHONE: return PDMAUDIOPATH_IN_PHONE;
3248 default:
3249 break;
3250 }
3251
3252 LogFlowFunc(("Unknown record source %d, using MIC\n", uIdx));
3253 return PDMAUDIOPATH_IN_MIC;
3254}
3255
3256
3257/**
3258 * Converts a PDM audio recording source to an AC'97 recording source index.
3259 *
3260 * @returns AC'97 recording source index.
3261 * @param enmRecSrc PDM audio recording source to convert.
3262 */
3263static uint8_t ichac97R3RecSourceToIdx(PDMAUDIOPATH enmRecSrc)
3264{
3265 switch (enmRecSrc)
3266 {
3267 case PDMAUDIOPATH_IN_MIC: return AC97_REC_MIC;
3268 case PDMAUDIOPATH_IN_CD: return AC97_REC_CD;
3269 case PDMAUDIOPATH_IN_VIDEO: return AC97_REC_VIDEO;
3270 case PDMAUDIOPATH_IN_AUX: return AC97_REC_AUX;
3271 case PDMAUDIOPATH_IN_LINE: return AC97_REC_LINE_IN;
3272 case PDMAUDIOPATH_IN_PHONE: return AC97_REC_PHONE;
3273 default:
3274 AssertMsgFailedBreak(("%d\n", enmRecSrc));
3275 }
3276
3277 LogFlowFunc(("Unknown audio recording source %d using MIC\n", enmRecSrc));
3278 return AC97_REC_MIC;
3279}
3280
3281
3282/**
3283 * Performs an AC'97 mixer record select to switch to a different recording
3284 * source.
3285 *
3286 * @param pThis The shared AC'97 state.
3287 * @param val AC'97 recording source index to set.
3288 */
3289static void ichac97R3MixerRecordSelect(PAC97STATE pThis, uint32_t val)
3290{
3291 uint8_t rs = val & AC97_REC_MASK;
3292 uint8_t ls = (val >> 8) & AC97_REC_MASK;
3293
3294 PDMAUDIOPATH const ars = ichac97R3IdxToRecSource(rs);
3295 PDMAUDIOPATH const als = ichac97R3IdxToRecSource(ls);
3296
3297 rs = ichac97R3RecSourceToIdx(ars);
3298 ls = ichac97R3RecSourceToIdx(als);
3299
3300 LogRel(("AC97: Record select to left=%s, right=%s\n", PDMAudioPathGetName(ars), PDMAudioPathGetName(als)));
3301
3302 ichac97MixerSet(pThis, AC97_Record_Select, rs | (ls << 8));
3303}
3304
3305/**
3306 * Resets the AC'97 mixer.
3307 *
3308 * @returns VBox status code.
3309 * @param pThis The shared AC'97 state.
3310 * @param pThisCC The ring-3 AC'97 state.
3311 */
3312static int ichac97R3MixerReset(PAC97STATE pThis, PAC97STATER3 pThisCC)
3313{
3314 LogFlowFuncEnter();
3315
3316 RT_ZERO(pThis->mixer_data);
3317
3318 /* Note: Make sure to reset all registers first before bailing out on error. */
3319
3320 ichac97MixerSet(pThis, AC97_Reset , 0x0000); /* 6940 */
3321 ichac97MixerSet(pThis, AC97_Master_Volume_Mono_Mute , 0x8000);
3322 ichac97MixerSet(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000);
3323
3324 ichac97MixerSet(pThis, AC97_Phone_Volume_Mute , 0x8008);
3325 ichac97MixerSet(pThis, AC97_Mic_Volume_Mute , 0x8008);
3326 ichac97MixerSet(pThis, AC97_CD_Volume_Mute , 0x8808);
3327 ichac97MixerSet(pThis, AC97_Aux_Volume_Mute , 0x8808);
3328 ichac97MixerSet(pThis, AC97_Record_Gain_Mic_Mute , 0x8000);
3329 ichac97MixerSet(pThis, AC97_General_Purpose , 0x0000);
3330 ichac97MixerSet(pThis, AC97_3D_Control , 0x0000);
3331 ichac97MixerSet(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f);
3332
3333 /* Configure Extended Audio ID (EAID) + Control & Status (EACS) registers. */
3334 const uint16_t fEAID = AC97_EAID_REV1 | AC97_EACS_VRA | AC97_EACS_VRM; /* Our hardware is AC'97 rev2.3 compliant. */
3335 const uint16_t fEACS = AC97_EACS_VRA | AC97_EACS_VRM; /* Variable Rate PCM Audio (VRA) + Mic-In (VRM) capable. */
3336
3337 LogRel(("AC97: Mixer reset (EAID=0x%x, EACS=0x%x)\n", fEAID, fEACS));
3338
3339 ichac97MixerSet(pThis, AC97_Extended_Audio_ID, fEAID);
3340 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, fEACS);
3341 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
3342 ichac97MixerSet(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
3343 ichac97MixerSet(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80 /* 48000 Hz by default */);
3344 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
3345 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80 /* 48000 Hz by default */);
3346
3347 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3348 {
3349 /* Analog Devices 1980 (AD1980) */
3350 ichac97MixerSet(pThis, AC97_Reset , 0x0010); /* Headphones. */
3351 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
3352 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5370);
3353 ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000);
3354 }
3355 else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
3356 {
3357 /* Analog Devices 1981B (AD1981B) */
3358 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x4144);
3359 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x5374);
3360 }
3361 else
3362 {
3363 /* Sigmatel 9700 (STAC9700) */
3364 ichac97MixerSet(pThis, AC97_Vendor_ID1 , 0x8384);
3365 ichac97MixerSet(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */
3366 }
3367 ichac97R3MixerRecordSelect(pThis, 0);
3368
3369 /* The default value is 8000h, which corresponds to 0 dB attenuation with mute on. */
3370 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER, 0x8000);
3371
3372 /* The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on.*/
3373 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT, 0x8808);
3374 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8808);
3375 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8008);
3376
3377 /* The default for record controls is 0 dB gain with mute on. */
3378 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN, 0x8000);
3379 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN, 0x8000);
3380
3381 return VINF_SUCCESS;
3382}
3383
3384#endif /* IN_RING3 */
3385
3386/**
3387 * @callback_method_impl{FNIOMIOPORTNEWIN}
3388 */
3389static DECLCALLBACK(VBOXSTRICTRC)
3390ichac97IoPortNamRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
3391{
3392 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3393 RT_NOREF(pvUser);
3394 Assert(offPort < 256);
3395
3396 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
3397
3398 VBOXSTRICTRC rc = VINF_SUCCESS;
3399 switch (cb)
3400 {
3401 case 1:
3402 LogRel2(("AC97: Warning: Unimplemented NAM read offPort=%#x LB 1 (line " RT_XSTR(__LINE__) ")\n", offPort));
3403 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNamReads);
3404 pThis->cas = 0;
3405 *pu32 = UINT32_MAX;
3406 break;
3407
3408 case 2:
3409 pThis->cas = 0;
3410 *pu32 = ichac97MixerGet(pThis, offPort);
3411 break;
3412
3413 case 4:
3414 LogRel2(("AC97: Warning: Unimplemented NAM read offPort=%#x LB 4 (line " RT_XSTR(__LINE__) ")\n", offPort));
3415 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNamReads);
3416 pThis->cas = 0;
3417 *pu32 = UINT32_MAX;
3418 break;
3419
3420 default:
3421 AssertFailed();
3422 rc = VERR_IOM_IOPORT_UNUSED;
3423 break;
3424 }
3425
3426 DEVAC97_UNLOCK(pDevIns, pThis);
3427 return rc;
3428}
3429
3430/**
3431 * @callback_method_impl{FNIOMIOPORTNEWOUT}
3432 */
3433static DECLCALLBACK(VBOXSTRICTRC)
3434ichac97IoPortNamWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3435{
3436 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3437#ifdef IN_RING3
3438 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3439#endif
3440 RT_NOREF(pvUser);
3441
3442 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
3443
3444 VBOXSTRICTRC rc = VINF_SUCCESS;
3445 switch (cb)
3446 {
3447 case 1:
3448 LogRel2(("AC97: Warning: Unimplemented NAM write offPort=%#x <- %#x LB 1 (line " RT_XSTR(__LINE__) ")\n", offPort, u32));
3449 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNamWrites);
3450 pThis->cas = 0;
3451 break;
3452
3453 case 2:
3454 {
3455 pThis->cas = 0;
3456 switch (offPort)
3457 {
3458 case AC97_Reset:
3459#ifdef IN_RING3
3460 ichac97R3Reset(pDevIns);
3461#else
3462 rc = VINF_IOM_R3_IOPORT_WRITE;
3463#endif
3464 break;
3465 case AC97_Powerdown_Ctrl_Stat:
3466 u32 &= ~0xf;
3467 u32 |= ichac97MixerGet(pThis, offPort) & 0xf;
3468 ichac97MixerSet(pThis, offPort, u32);
3469 break;
3470 case AC97_Master_Volume_Mute:
3471 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3472 {
3473 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_LOSEL)
3474 break; /* Register controls surround (rear), do nothing. */
3475 }
3476#ifdef IN_RING3
3477 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3478#else
3479 rc = VINF_IOM_R3_IOPORT_WRITE;
3480#endif
3481 break;
3482 case AC97_Headphone_Volume_Mute:
3483 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3484 {
3485 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3486 {
3487 /* Register controls PCM (front) outputs. */
3488#ifdef IN_RING3
3489 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32);
3490#else
3491 rc = VINF_IOM_R3_IOPORT_WRITE;
3492#endif
3493 }
3494 }
3495 break;
3496 case AC97_PCM_Out_Volume_Mute:
3497#ifdef IN_RING3
3498 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_FRONT, u32);
3499#else
3500 rc = VINF_IOM_R3_IOPORT_WRITE;
3501#endif
3502 break;
3503 case AC97_Line_In_Volume_Mute:
3504#ifdef IN_RING3
3505 ichac97R3MixerSetVolume(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3506#else
3507 rc = VINF_IOM_R3_IOPORT_WRITE;
3508#endif
3509 break;
3510 case AC97_Record_Select:
3511#ifdef IN_RING3
3512 ichac97R3MixerRecordSelect(pThis, u32);
3513#else
3514 rc = VINF_IOM_R3_IOPORT_WRITE;
3515#endif
3516 break;
3517 case AC97_Record_Gain_Mute:
3518#ifdef IN_RING3
3519 /* Newer Ubuntu guests rely on that when controlling gain and muting
3520 * the recording (capturing) levels. */
3521 ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32);
3522#else
3523 rc = VINF_IOM_R3_IOPORT_WRITE;
3524#endif
3525 break;
3526 case AC97_Record_Gain_Mic_Mute:
3527#ifdef IN_RING3
3528 /* Ditto; see note above. */
3529 ichac97R3MixerSetGain(pThis, pThisCC, offPort, PDMAUDIOMIXERCTL_MIC_IN, u32);
3530#else
3531 rc = VINF_IOM_R3_IOPORT_WRITE;
3532#endif
3533 break;
3534 case AC97_Vendor_ID1:
3535 case AC97_Vendor_ID2:
3536 LogFunc(("Attempt to write vendor ID to %#x\n", u32));
3537 break;
3538 case AC97_Extended_Audio_ID:
3539 LogFunc(("Attempt to write extended audio ID to %#x\n", u32));
3540 break;
3541 case AC97_Extended_Audio_Ctrl_Stat:
3542#ifdef IN_RING3
3543 /*
3544 * Handle VRA bits.
3545 */
3546 if (!(u32 & AC97_EACS_VRA)) /* Check if VRA bit is not set. */
3547 {
3548 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 0xbb80); /* Set default (48000 Hz). */
3549 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3550 * actually used? */
3551 ichac97R3StreamReSetUp(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3552 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3553
3554 ichac97MixerSet(pThis, AC97_PCM_LR_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3555 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3556 * actually used? */
3557 ichac97R3StreamReSetUp(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3558 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3559 }
3560 else
3561 LogRel2(("AC97: Variable rate audio (VRA) is not supported\n"));
3562
3563 /*
3564 * Handle VRM bits.
3565 */
3566 if (!(u32 & AC97_EACS_VRM)) /* Check if VRM bit is not set. */
3567 {
3568 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */
3569 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3570 * actually used? */
3571 ichac97R3StreamReSetUp(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3572 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3573 }
3574 else
3575 LogRel2(("AC97: Variable rate microphone audio (VRM) is not supported\n"));
3576
3577 LogRel2(("AC97: Setting extended audio control to %#x\n", u32));
3578 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32);
3579#else /* !IN_RING3 */
3580 rc = VINF_IOM_R3_IOPORT_WRITE;
3581#endif
3582 break;
3583 case AC97_PCM_Front_DAC_Rate: /* Output slots 3, 4, 6. */
3584#ifdef IN_RING3
3585 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3586 {
3587 LogRel2(("AC97: Setting front DAC rate to 0x%x\n", u32));
3588 ichac97MixerSet(pThis, offPort, u32);
3589 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3590 * actually used? */
3591 ichac97R3StreamReSetUp(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX],
3592 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */);
3593 }
3594 else
3595 LogRel2(("AC97: Setting front DAC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3596#else
3597 rc = VINF_IOM_R3_IOPORT_WRITE;
3598#endif
3599 break;
3600 case AC97_MIC_ADC_Rate: /* Input slot 6. */
3601#ifdef IN_RING3
3602 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRM)
3603 {
3604 LogRel2(("AC97: Setting microphone ADC rate to 0x%x\n", u32));
3605 ichac97MixerSet(pThis, offPort, u32);
3606 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3607 * actually used? */
3608 ichac97R3StreamReSetUp(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX],
3609 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */);
3610 }
3611 else
3612 LogRel2(("AC97: Setting microphone ADC rate (0x%x) when VRM is not set is forbidden, ignoring\n", u32));
3613#else
3614 rc = VINF_IOM_R3_IOPORT_WRITE;
3615#endif
3616 break;
3617 case AC97_PCM_LR_ADC_Rate: /* Input slots 3, 4. */
3618#ifdef IN_RING3
3619 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA)
3620 {
3621 LogRel2(("AC97: Setting line-in ADC rate to 0x%x\n", u32));
3622 ichac97MixerSet(pThis, offPort, u32);
3623 /** @todo r=bird: Why reopen it now? Can't we put that off till it's
3624 * actually used? */
3625 ichac97R3StreamReSetUp(pDevIns, pThis, pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX],
3626 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */);
3627 }
3628 else
3629 LogRel2(("AC97: Setting line-in ADC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32));
3630#else
3631 rc = VINF_IOM_R3_IOPORT_WRITE;
3632#endif
3633 break;
3634 default:
3635 /* Most of these are to register we don't care about like AC97_CD_Volume_Mute
3636 and AC97_Master_Volume_Mono_Mute or things we don't need to handle specially.
3637 Thus this is not a 'warning' but an 'info log message. */
3638 LogRel2(("AC97: Info: Unimplemented NAM write offPort=%#x <- %#x LB 2 (line " RT_XSTR(__LINE__) ")\n", offPort, u32));
3639 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNamWrites);
3640 ichac97MixerSet(pThis, offPort, u32);
3641 break;
3642 }
3643 break;
3644 }
3645
3646 case 4:
3647 LogRel2(("AC97: Warning: Unimplemented NAM write offPort=%#x <- %#x LB 4 (line " RT_XSTR(__LINE__) ")\n", offPort, u32));
3648 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNamWrites);
3649 pThis->cas = 0;
3650 break;
3651
3652 default:
3653 AssertMsgFailed(("Unhandled NAM write offPort=%#x, cb=%u u32=%#x\n", offPort, cb, u32));
3654 break;
3655 }
3656
3657 DEVAC97_UNLOCK(pDevIns, pThis);
3658 return rc;
3659}
3660
3661#ifdef IN_RING3
3662
3663
3664/*********************************************************************************************************************************
3665* State Saving & Loading *
3666*********************************************************************************************************************************/
3667
3668/**
3669 * Saves (serializes) an AC'97 stream using SSM.
3670 *
3671 * @param pDevIns Device instance.
3672 * @param pSSM Saved state manager (SSM) handle to use.
3673 * @param pStream AC'97 stream to save.
3674 */
3675static void ichac97R3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3676{
3677 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3678
3679 pHlp->pfnSSMPutU32(pSSM, pStream->Regs.bdbar);
3680 pHlp->pfnSSMPutU8( pSSM, pStream->Regs.civ);
3681 pHlp->pfnSSMPutU8( pSSM, pStream->Regs.lvi);
3682 pHlp->pfnSSMPutU16(pSSM, pStream->Regs.sr);
3683 pHlp->pfnSSMPutU16(pSSM, pStream->Regs.picb);
3684 pHlp->pfnSSMPutU8( pSSM, pStream->Regs.piv);
3685 pHlp->pfnSSMPutU8( pSSM, pStream->Regs.cr);
3686 pHlp->pfnSSMPutS32(pSSM, pStream->Regs.bd_valid);
3687 pHlp->pfnSSMPutU32(pSSM, pStream->Regs.bd.addr);
3688 pHlp->pfnSSMPutU32(pSSM, pStream->Regs.bd.ctl_len);
3689}
3690
3691
3692/**
3693 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3694 */
3695static DECLCALLBACK(int) ichac97R3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3696{
3697 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3698 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3699 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3700 LogFlowFuncEnter();
3701
3702 pHlp->pfnSSMPutU32(pSSM, pThis->glob_cnt);
3703 pHlp->pfnSSMPutU32(pSSM, pThis->glob_sta);
3704 pHlp->pfnSSMPutU32(pSSM, pThis->cas);
3705
3706 /*
3707 * The order that the streams are saved here is fixed, so don't change.
3708 */
3709 /** @todo r=andy For the next saved state version, add unique stream identifiers and a stream count. */
3710 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3711 ichac97R3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3712
3713 pHlp->pfnSSMPutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3714
3715 /* The stream order is against fixed and set in stone. */
3716 uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3717 afActiveStrms[AC97SOUNDSOURCE_PI_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX]);
3718 afActiveStrms[AC97SOUNDSOURCE_PO_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX]);
3719 afActiveStrms[AC97SOUNDSOURCE_MC_INDEX] = ichac97R3StreamIsEnabled(pThisCC, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX]);
3720 AssertCompile(RT_ELEMENTS(afActiveStrms) == 3);
3721 pHlp->pfnSSMPutMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3722
3723 LogFlowFuncLeaveRC(VINF_SUCCESS);
3724 return VINF_SUCCESS;
3725}
3726
3727
3728/**
3729 * Loads an AC'97 stream from SSM.
3730 *
3731 * @returns VBox status code.
3732 * @param pDevIns The device instance.
3733 * @param pSSM Saved state manager (SSM) handle to use.
3734 * @param pStream AC'97 stream to load.
3735 */
3736static int ichac97R3LoadStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PAC97STREAM pStream)
3737{
3738 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3739
3740 pHlp->pfnSSMGetU32(pSSM, &pStream->Regs.bdbar);
3741 pHlp->pfnSSMGetU8( pSSM, &pStream->Regs.civ);
3742 pHlp->pfnSSMGetU8( pSSM, &pStream->Regs.lvi);
3743 pHlp->pfnSSMGetU16(pSSM, &pStream->Regs.sr);
3744 pHlp->pfnSSMGetU16(pSSM, &pStream->Regs.picb);
3745 pHlp->pfnSSMGetU8( pSSM, &pStream->Regs.piv);
3746 pHlp->pfnSSMGetU8( pSSM, &pStream->Regs.cr);
3747 pHlp->pfnSSMGetS32(pSSM, &pStream->Regs.bd_valid);
3748 pHlp->pfnSSMGetU32(pSSM, &pStream->Regs.bd.addr);
3749 return pHlp->pfnSSMGetU32(pSSM, &pStream->Regs.bd.ctl_len);
3750}
3751
3752
3753/**
3754 * @callback_method_impl{FNSSMDEVLOADEXEC}
3755 */
3756static DECLCALLBACK(int) ichac97R3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3757{
3758 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3759 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3760 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3761
3762 LogRel2(("ichac97LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3763
3764 AssertMsgReturn (uVersion == AC97_SAVED_STATE_VERSION, ("%RU32\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3765 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3766
3767 pHlp->pfnSSMGetU32(pSSM, &pThis->glob_cnt);
3768 pHlp->pfnSSMGetU32(pSSM, &pThis->glob_sta);
3769 pHlp->pfnSSMGetU32(pSSM, &pThis->cas);
3770
3771 /*
3772 * The order the streams are loaded here is critical (defined by
3773 * AC97SOUNDSOURCE_XX_INDEX), so don't touch!
3774 */
3775 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3776 {
3777 int rc = ichac97R3LoadStream(pDevIns, pSSM, &pThis->aStreams[i]);
3778 AssertRCReturn(rc, rc);
3779 }
3780
3781 pHlp->pfnSSMGetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data));
3782
3783 ichac97R3MixerRecordSelect(pThis, ichac97MixerGet(pThis, AC97_Record_Select));
3784 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Master_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3785 ichac97MixerGet(pThis, AC97_Master_Volume_Mute));
3786 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_PCM_Out_Volume_Mute, PDMAUDIOMIXERCTL_FRONT,
3787 ichac97MixerGet(pThis, AC97_PCM_Out_Volume_Mute));
3788 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Line_In_Volume_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3789 ichac97MixerGet(pThis, AC97_Line_In_Volume_Mute));
3790 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3791 ichac97MixerGet(pThis, AC97_Mic_Volume_Mute));
3792 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mic_Mute, PDMAUDIOMIXERCTL_MIC_IN,
3793 ichac97MixerGet(pThis, AC97_Record_Gain_Mic_Mute));
3794 ichac97R3MixerSetGain(pThis, pThisCC, AC97_Record_Gain_Mute, PDMAUDIOMIXERCTL_LINE_IN,
3795 ichac97MixerGet(pThis, AC97_Record_Gain_Mute));
3796 if (pThis->enmCodecModel == AC97CODEC_AD1980)
3797 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL)
3798 ichac97R3MixerSetVolume(pThis, pThisCC, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER,
3799 ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute));
3800
3801 /*
3802 * Again the stream order is set is stone.
3803 */
3804 uint8_t afActiveStrms[AC97SOUNDSOURCE_MAX];
3805 int rc = pHlp->pfnSSMGetMem(pSSM, afActiveStrms, sizeof(afActiveStrms));
3806 AssertRCReturn(rc, rc);
3807
3808 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
3809 {
3810 const bool fEnable = RT_BOOL(afActiveStrms[i]);
3811 const PAC97STREAM pStream = &pThis->aStreams[i];
3812 const PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[i];
3813
3814 rc = ichac97R3StreamEnable(pDevIns, pThis, pThisCC, pStream, pStreamCC, fEnable);
3815 AssertRC(rc);
3816 if ( fEnable
3817 && RT_SUCCESS(rc))
3818 {
3819 /*
3820 * We need to make sure to update the stream's next transfer (if any) when
3821 * restoring from a saved state.
3822 *
3823 * Otherwise pStream->cDmaPeriodTicks always will be 0 and thus streams won't
3824 * resume when running while the saved state has been taken.
3825 *
3826 * Also see oem2ticketref:52.
3827 */
3828 ichac97R3StreamTransferUpdate(pDevIns, pStream, pStreamCC);
3829
3830 /* Re-arm the timer for this stream. */
3831 /** @todo r=aeichner This causes a VM hang upon saved state resume when NetBSD is used as a guest
3832 * Stopping the timer if cDmaPeriodTicks is 0 is a workaround but needs further investigation,
3833 * see @bugref{9759} for more information. */
3834 if (pStream->cDmaPeriodTicks)
3835 ichac97R3TimerSet(pDevIns, pStream, pStream->cDmaPeriodTicks);
3836 else
3837 PDMDevHlpTimerStop(pDevIns, pStream->hTimer);
3838 }
3839
3840 /* Keep going. */
3841 }
3842
3843 pThis->bup_flag = 0;
3844 pThis->last_samp = 0;
3845
3846 return VINF_SUCCESS;
3847}
3848
3849
3850/*********************************************************************************************************************************
3851* Debug Info Items *
3852*********************************************************************************************************************************/
3853
3854/** Used by ichac97R3DbgInfoStream and ichac97R3DbgInfoBDL. */
3855static int ichac97R3DbgLookupStrmIdx(PCDBGFINFOHLP pHlp, const char *pszArgs)
3856{
3857 if (pszArgs && *pszArgs)
3858 {
3859 int32_t idxStream;
3860 int rc = RTStrToInt32Full(pszArgs, 0, &idxStream);
3861 if (RT_SUCCESS(rc) && idxStream >= -1 && idxStream < AC97_MAX_STREAMS)
3862 return idxStream;
3863 pHlp->pfnPrintf(pHlp, "Argument '%s' is not a valid stream number!\n", pszArgs);
3864 }
3865 return -1;
3866}
3867
3868
3869/**
3870 * Generic buffer descriptor list dumper.
3871 */
3872static void ichac97R3DbgPrintBdl(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STREAM pStream,
3873 PCDBGFINFOHLP pHlp, const char *pszPrefix)
3874{
3875 uint8_t const bLvi = pStream->Regs.lvi;
3876 uint8_t const bCiv = pStream->Regs.civ;
3877 pHlp->pfnPrintf(pHlp, "%sBDL for stream #%u: @ %#RX32 LB 0x100; CIV=%#04x LVI=%#04x:\n",
3878 pszPrefix, pStream->u8SD, pStream->Regs.bdbar, bCiv, bLvi);
3879 if (pStream->Regs.bdbar != 0)
3880 {
3881 /* Read all in one go. */
3882 AC97BDLE aBdl[AC97_MAX_BDLE];
3883 RT_ZERO(aBdl);
3884 PDMDevHlpPCIPhysRead(pDevIns, pStream->Regs.bdbar, aBdl, sizeof(aBdl));
3885
3886 /* Get the audio props for the stream so we can translate the sizes correctly. */
3887 PDMAUDIOPCMPROPS Props;
3888 ichach97R3CalcStreamProps(pThis, pStream->u8SD, &Props);
3889
3890 /* Dump them. */
3891 uint64_t cbTotal = 0;
3892 uint64_t cbValid = 0;
3893 for (unsigned i = 0; i < RT_ELEMENTS(aBdl); i++)
3894 {
3895 aBdl[i].addr = RT_LE2H_U32(aBdl[i].addr);
3896 aBdl[i].ctl_len = RT_LE2H_U32(aBdl[i].ctl_len);
3897
3898 bool const fValid = bCiv <= bLvi
3899 ? i >= bCiv && i <= bLvi
3900 : i >= bCiv || i <= bLvi;
3901
3902 uint32_t const cb = (aBdl[i].ctl_len & AC97_BD_LEN_MASK) * PDMAudioPropsSampleSize(&Props); /** @todo or frame size? OSDev says frame... */
3903 cbTotal += cb;
3904 if (fValid)
3905 cbValid += cb;
3906
3907 char szFlags[64];
3908 szFlags[0] = '\0';
3909 if (aBdl[i].ctl_len & ~(AC97_BD_LEN_MASK | AC97_BD_IOC | AC97_BD_BUP))
3910 RTStrPrintf(szFlags, sizeof(szFlags), " !!fFlags=%#x!!\n", aBdl[i].ctl_len & ~AC97_BD_LEN_MASK);
3911
3912 pHlp->pfnPrintf(pHlp, "%s %cBDLE%02u: %#010RX32 L %#06x / LB %#RX32 / %RU64ms%s%s%s%s\n",
3913 pszPrefix, fValid ? ' ' : '?', i, aBdl[i].addr,
3914 aBdl[i].ctl_len & AC97_BD_LEN_MASK, cb, PDMAudioPropsBytesToMilli(&Props, cb),
3915 aBdl[i].ctl_len & AC97_BD_IOC ? " ioc" : "",
3916 aBdl[i].ctl_len & AC97_BD_BUP ? " bup" : "",
3917 szFlags, !(aBdl[i].addr & 3) ? "" : " !!Addr!!");
3918 }
3919
3920 pHlp->pfnPrintf(pHlp, "%sTotal: %#RX64 bytes (%RU64), %RU64 ms; Valid: %#RX64 bytes (%RU64), %RU64 ms\n", pszPrefix,
3921 cbTotal, cbTotal, PDMAudioPropsBytesToMilli(&Props, cbTotal),
3922 cbValid, cbValid, PDMAudioPropsBytesToMilli(&Props, cbValid) );
3923 }
3924}
3925
3926
3927/**
3928 * @callback_method_impl{FNDBGFHANDLERDEV, ac97bdl}
3929 */
3930static DECLCALLBACK(void) ichac97R3DbgInfoBDL(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3931{
3932 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3933 int idxStream = ichac97R3DbgLookupStrmIdx(pHlp, pszArgs);
3934 if (idxStream != -1)
3935 ichac97R3DbgPrintBdl(pDevIns, pThis, &pThis->aStreams[idxStream], pHlp, "");
3936 else
3937 for (idxStream = 0; idxStream < AC97_MAX_STREAMS; ++idxStream)
3938 ichac97R3DbgPrintBdl(pDevIns, pThis, &pThis->aStreams[idxStream], pHlp, "");
3939}
3940
3941
3942/** Worker for ichac97R3DbgInfoStream. */
3943static void ichac97R3DbgPrintStream(PCDBGFINFOHLP pHlp, PAC97STREAM pStream, PAC97STREAMR3 pStreamR3)
3944{
3945 char szTmp[PDMAUDIOSTRMCFGTOSTRING_MAX];
3946 pHlp->pfnPrintf(pHlp, "Stream #%d: %s\n", pStream->u8SD,
3947 PDMAudioStrmCfgToString(&pStreamR3->State.Cfg, szTmp, sizeof(szTmp)));
3948 pHlp->pfnPrintf(pHlp, " BDBAR %#010RX32\n", pStream->Regs.bdbar);
3949 pHlp->pfnPrintf(pHlp, " CIV %#04RX8\n", pStream->Regs.civ);
3950 pHlp->pfnPrintf(pHlp, " LVI %#04RX8\n", pStream->Regs.lvi);
3951 pHlp->pfnPrintf(pHlp, " SR %#06RX16\n", pStream->Regs.sr);
3952 pHlp->pfnPrintf(pHlp, " PICB %#06RX16\n", pStream->Regs.picb);
3953 pHlp->pfnPrintf(pHlp, " PIV %#04RX8\n", pStream->Regs.piv);
3954 pHlp->pfnPrintf(pHlp, " CR %#04RX8\n", pStream->Regs.cr);
3955 if (pStream->Regs.bd_valid)
3956 {
3957 pHlp->pfnPrintf(pHlp, " BD.ADDR %#010RX32\n", pStream->Regs.bd.addr);
3958 pHlp->pfnPrintf(pHlp, " BD.LEN %#04RX16\n", (uint16_t)pStream->Regs.bd.ctl_len);
3959 pHlp->pfnPrintf(pHlp, " BD.CTL %#04RX16\n", (uint16_t)(pStream->Regs.bd.ctl_len >> 16));
3960 }
3961
3962 pHlp->pfnPrintf(pHlp, " offRead %#RX64\n", pStreamR3->State.offRead);
3963 pHlp->pfnPrintf(pHlp, " offWrite %#RX64\n", pStreamR3->State.offWrite);
3964 pHlp->pfnPrintf(pHlp, " uTimerHz %RU16\n", pStreamR3->State.uTimerHz);
3965 pHlp->pfnPrintf(pHlp, " cDmaPeriodTicks %RU64\n", pStream->cDmaPeriodTicks);
3966 pHlp->pfnPrintf(pHlp, " cbDmaPeriod %#RX32\n", pStream->cbDmaPeriod);
3967}
3968
3969
3970/**
3971 * @callback_method_impl{FNDBGFHANDLERDEV, ac97stream}
3972 */
3973static DECLCALLBACK(void) ichac97R3DbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3974{
3975 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
3976 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3977 int idxStream = ichac97R3DbgLookupStrmIdx(pHlp, pszArgs);
3978 if (idxStream != -1)
3979 ichac97R3DbgPrintStream(pHlp, &pThis->aStreams[idxStream], &pThisCC->aStreams[idxStream]);
3980 else
3981 for (idxStream = 0; idxStream < AC97_MAX_STREAMS; ++idxStream)
3982 ichac97R3DbgPrintStream(pHlp, &pThis->aStreams[idxStream], &pThisCC->aStreams[idxStream]);
3983}
3984
3985
3986/**
3987 * @callback_method_impl{FNDBGFHANDLERDEV, ac97mixer}
3988 */
3989static DECLCALLBACK(void) ichac97R3DbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3990{
3991 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
3992 if (pThisCC->pMixer)
3993 AudioMixerDebug(pThisCC->pMixer, pHlp, pszArgs);
3994 else
3995 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
3996}
3997
3998
3999/*********************************************************************************************************************************
4000* PDMIBASE *
4001*********************************************************************************************************************************/
4002
4003/**
4004 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
4005 */
4006static DECLCALLBACK(void *) ichac97R3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
4007{
4008 PAC97STATER3 pThisCC = RT_FROM_MEMBER(pInterface, AC97STATER3, IBase);
4009 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
4010 return NULL;
4011}
4012
4013
4014/*********************************************************************************************************************************
4015* PDMDEVREG *
4016*********************************************************************************************************************************/
4017
4018/**
4019 * Destroys all AC'97 audio streams of the device.
4020 *
4021 * @param pDevIns The device AC'97 instance.
4022 * @param pThis The shared AC'97 state.
4023 * @param pThisCC The ring-3 AC'97 state.
4024 */
4025static void ichac97R3StreamsDestroy(PPDMDEVINS pDevIns, PAC97STATE pThis, PAC97STATER3 pThisCC)
4026{
4027 LogFlowFuncEnter();
4028
4029 /*
4030 * Destroy all AC'97 streams.
4031 */
4032 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4033 ichac97R3StreamDestroy(pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i]);
4034
4035 /*
4036 * Destroy all sinks.
4037 */
4038 if (pThisCC->pSinkLineIn)
4039 {
4040 ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkLineIn, PDMAUDIODIR_IN, PDMAUDIOPATH_IN_LINE);
4041
4042 AudioMixerSinkDestroy(pThisCC->pSinkLineIn, pDevIns);
4043 pThisCC->pSinkLineIn = NULL;
4044 }
4045
4046 if (pThisCC->pSinkMicIn)
4047 {
4048 ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkMicIn, PDMAUDIODIR_IN, PDMAUDIOPATH_IN_MIC);
4049
4050 AudioMixerSinkDestroy(pThisCC->pSinkMicIn, pDevIns);
4051 pThisCC->pSinkMicIn = NULL;
4052 }
4053
4054 if (pThisCC->pSinkOut)
4055 {
4056 ichac97R3MixerRemoveDrvStreams(pDevIns, pThisCC, pThisCC->pSinkOut, PDMAUDIODIR_OUT, PDMAUDIOPATH_OUT_FRONT);
4057
4058 AudioMixerSinkDestroy(pThisCC->pSinkOut, pDevIns);
4059 pThisCC->pSinkOut = NULL;
4060 }
4061}
4062
4063
4064/**
4065 * Powers off the device.
4066 *
4067 * @param pDevIns Device instance to power off.
4068 */
4069static DECLCALLBACK(void) ichac97R3PowerOff(PPDMDEVINS pDevIns)
4070{
4071 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4072 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4073
4074 LogRel2(("AC97: Powering off ...\n"));
4075
4076 /* Note: Involves mixer stream / sink destruction, so also do this here
4077 * instead of in ichac97R3Destruct(). */
4078 ichac97R3StreamsDestroy(pDevIns, pThis, pThisCC);
4079
4080 /*
4081 * Note: Destroy the mixer while powering off and *not* in ichac97R3Destruct,
4082 * giving the mixer the chance to release any references held to
4083 * PDM audio streams it maintains.
4084 */
4085 if (pThisCC->pMixer)
4086 {
4087 AudioMixerDestroy(pThisCC->pMixer, pDevIns);
4088 pThisCC->pMixer = NULL;
4089 }
4090}
4091
4092
4093/**
4094 * @interface_method_impl{PDMDEVREG,pfnReset}
4095 *
4096 * @remarks The original sources didn't install a reset handler, but it seems to
4097 * make sense to me so we'll do it.
4098 */
4099static DECLCALLBACK(void) ichac97R3Reset(PPDMDEVINS pDevIns)
4100{
4101 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4102 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4103
4104 LogRel(("AC97: Reset\n"));
4105
4106 /*
4107 * Reset the mixer too. The Windows XP driver seems to rely on
4108 * this. At least it wants to read the vendor id before it resets
4109 * the codec manually.
4110 */
4111 ichac97R3MixerReset(pThis, pThisCC);
4112
4113 /*
4114 * Reset all streams.
4115 */
4116 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4117 {
4118 ichac97R3StreamEnable(pDevIns, pThis, pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], false /* fEnable */);
4119 ichac97R3StreamReset(pThis, &pThis->aStreams[i], &pThisCC->aStreams[i]);
4120 }
4121
4122 /*
4123 * Reset mixer sinks.
4124 *
4125 * Do the reset here instead of in ichac97R3StreamReset();
4126 * the mixer sink(s) might still have data to be processed when an audio stream gets reset.
4127 */
4128 AudioMixerSinkReset(pThisCC->pSinkLineIn);
4129 AudioMixerSinkReset(pThisCC->pSinkMicIn);
4130 AudioMixerSinkReset(pThisCC->pSinkOut);
4131}
4132
4133
4134/**
4135 * Adds a specific AC'97 driver to the driver chain.
4136 *
4137 * Only called from ichac97R3Attach().
4138 *
4139 * @returns VBox status code.
4140 * @param pDevIns The device instance.
4141 * @param pThisCC The ring-3 AC'97 device state.
4142 * @param pDrv The AC'97 driver to add.
4143 */
4144static int ichac97R3MixerAddDrv(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
4145{
4146 int rc = VINF_SUCCESS;
4147
4148 if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg))
4149 rc = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkLineIn,
4150 &pThisCC->aStreams[AC97SOUNDSOURCE_PI_INDEX].State.Cfg, pDrv);
4151
4152 if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg))
4153 {
4154 int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkOut,
4155 &pThisCC->aStreams[AC97SOUNDSOURCE_PO_INDEX].State.Cfg, pDrv);
4156 if (RT_SUCCESS(rc))
4157 rc = rc2;
4158 }
4159
4160 if (AudioHlpStreamCfgIsValid(&pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg))
4161 {
4162 int rc2 = ichac97R3MixerAddDrvStream(pDevIns, pThisCC->pSinkMicIn,
4163 &pThisCC->aStreams[AC97SOUNDSOURCE_MC_INDEX].State.Cfg, pDrv);
4164 if (RT_SUCCESS(rc))
4165 rc = rc2;
4166 }
4167
4168 return rc;
4169}
4170
4171
4172/**
4173 * Worker for ichac97R3Construct() and ichac97R3Attach().
4174 *
4175 * @returns VBox status code.
4176 * @param pDevIns The device instance.
4177 * @param pThisCC The ring-3 AC'97 device state.
4178 * @param uLUN The logical unit which is being attached.
4179 * @param ppDrv Attached driver instance on success. Optional.
4180 */
4181static int ichac97R3AttachInternal(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, unsigned uLUN, PAC97DRIVER *ppDrv)
4182{
4183 /*
4184 * Allocate a new driver structure and try attach the driver.
4185 */
4186 PAC97DRIVER pDrv = (PAC97DRIVER)RTMemAllocZ(sizeof(AC97DRIVER));
4187 AssertPtrReturn(pDrv, VERR_NO_MEMORY);
4188 RTStrPrintf(pDrv->szDesc, sizeof(pDrv->szDesc), "Audio driver port (AC'97) for LUN #%u", uLUN);
4189
4190 PPDMIBASE pDrvBase;
4191 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN, &pThisCC->IBase, &pDrvBase, pDrv->szDesc);
4192 if (RT_SUCCESS(rc))
4193 {
4194 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
4195 AssertPtr(pDrv->pConnector);
4196 if (RT_VALID_PTR(pDrv->pConnector))
4197 {
4198 pDrv->pDrvBase = pDrvBase;
4199 pDrv->uLUN = uLUN;
4200
4201 /* Attach to driver list if not attached yet. */
4202 if (!pDrv->fAttached)
4203 {
4204 RTListAppend(&pThisCC->lstDrv, &pDrv->Node);
4205 pDrv->fAttached = true;
4206 }
4207
4208 if (ppDrv)
4209 *ppDrv = pDrv;
4210
4211 /*
4212 * While we're here, give the windows backends a hint about our typical playback
4213 * configuration.
4214 */
4215 if ( pDrv->pConnector
4216 && pDrv->pConnector->pfnStreamConfigHint)
4217 {
4218 /* 48kHz */
4219 PDMAUDIOSTREAMCFG Cfg;
4220 RT_ZERO(Cfg);
4221 Cfg.enmDir = PDMAUDIODIR_OUT;
4222 Cfg.enmPath = PDMAUDIOPATH_OUT_FRONT;
4223 Cfg.Device.cMsSchedulingHint = 5;
4224 Cfg.Backend.cFramesPreBuffering = UINT32_MAX;
4225 PDMAudioPropsInit(&Cfg.Props, 2, true /*fSigned*/, 2, 48000);
4226 RTStrPrintf(Cfg.szName, sizeof(Cfg.szName), "output 48kHz 2ch S16 (HDA config hint)");
4227
4228 pDrv->pConnector->pfnStreamConfigHint(pDrv->pConnector, &Cfg); /* (may trash CfgReq) */
4229# if 0
4230 /* 44.1kHz */
4231 RT_ZERO(Cfg);
4232 Cfg.enmDir = PDMAUDIODIR_OUT;
4233 Cfg.enmPath = PDMAUDIOPATH_OUT_FRONT;
4234 Cfg.Device.cMsSchedulingHint = 10;
4235 Cfg.Backend.cFramesPreBuffering = UINT32_MAX;
4236 PDMAudioPropsInit(&Cfg.Props, 2, true /*fSigned*/, 2, 44100);
4237 RTStrPrintf(Cfg.szName, sizeof(Cfg.szName), "output 44.1kHz 2ch S16 (HDA config hint)");
4238
4239 pDrv->pConnector->pfnStreamConfigHint(pDrv->pConnector, &Cfg); /* (may trash CfgReq) */
4240# endif
4241 }
4242
4243 LogFunc(("LUN#%u: returns VINF_SUCCESS (pCon=%p)\n", uLUN, pDrv->pConnector));
4244 return VINF_SUCCESS;
4245 }
4246 RTMemFree(pDrv);
4247 rc = VERR_PDM_MISSING_INTERFACE_BELOW;
4248 }
4249 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4250 LogFunc(("No attached driver for LUN #%u\n", uLUN));
4251 else
4252 LogFunc(("Attached driver for LUN #%u failed: %Rrc\n", uLUN, rc));
4253 RTMemFree(pDrv);
4254
4255 LogFunc(("LUN#%u: rc=%Rrc\n", uLUN, rc));
4256 return rc;
4257}
4258
4259
4260/**
4261 * @interface_method_impl{PDMDEVREGR3,pfnAttach}
4262 */
4263static DECLCALLBACK(int) ichac97R3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4264{
4265 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4266 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4267 RT_NOREF(fFlags);
4268 LogFunc(("iLUN=%u, fFlags=%#x\n", iLUN, fFlags));
4269
4270 DEVAC97_LOCK(pDevIns, pThis);
4271
4272 PAC97DRIVER pDrv;
4273 int rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLUN, &pDrv);
4274 if (RT_SUCCESS(rc))
4275 {
4276 int rc2 = ichac97R3MixerAddDrv(pDevIns, pThisCC, pDrv);
4277 if (RT_FAILURE(rc2))
4278 LogFunc(("ichac97R3MixerAddDrv failed with %Rrc (ignored)\n", rc2));
4279 }
4280
4281 DEVAC97_UNLOCK(pDevIns, pThis);
4282
4283 return rc;
4284}
4285
4286
4287/**
4288 * Removes a specific AC'97 driver from the driver chain and destroys its
4289 * associated streams.
4290 *
4291 * Only called from ichac97R3Detach().
4292 *
4293 * @param pDevIns The device instance.
4294 * @param pThisCC The ring-3 AC'97 device state.
4295 * @param pDrv AC'97 driver to remove.
4296 */
4297static void ichac97R3MixerRemoveDrv(PPDMDEVINS pDevIns, PAC97STATER3 pThisCC, PAC97DRIVER pDrv)
4298{
4299 if (pDrv->MicIn.pMixStrm)
4300 {
4301 AudioMixerSinkRemoveStream(pThisCC->pSinkMicIn, pDrv->MicIn.pMixStrm);
4302 AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm, pDevIns, true /*fImmediate*/);
4303 pDrv->MicIn.pMixStrm = NULL;
4304 }
4305
4306 if (pDrv->LineIn.pMixStrm)
4307 {
4308 AudioMixerSinkRemoveStream(pThisCC->pSinkLineIn, pDrv->LineIn.pMixStrm);
4309 AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm, pDevIns, true /*fImmediate*/);
4310 pDrv->LineIn.pMixStrm = NULL;
4311 }
4312
4313 if (pDrv->Out.pMixStrm)
4314 {
4315 AudioMixerSinkRemoveStream(pThisCC->pSinkOut, pDrv->Out.pMixStrm);
4316 AudioMixerStreamDestroy(pDrv->Out.pMixStrm, pDevIns, true /*fImmediate*/);
4317 pDrv->Out.pMixStrm = NULL;
4318 }
4319
4320 RTListNodeRemove(&pDrv->Node);
4321}
4322
4323
4324/**
4325 * @interface_method_impl{PDMDEVREG,pfnDetach}
4326 */
4327static DECLCALLBACK(void) ichac97R3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4328{
4329 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4330 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4331 RT_NOREF(fFlags);
4332
4333 LogFunc(("iLUN=%u, fFlags=0x%x\n", iLUN, fFlags));
4334
4335 DEVAC97_LOCK(pDevIns, pThis);
4336
4337 PAC97DRIVER pDrv;
4338 RTListForEach(&pThisCC->lstDrv, pDrv, AC97DRIVER, Node)
4339 {
4340 if (pDrv->uLUN == iLUN)
4341 {
4342 /* Remove the driver from our list and destory it's associated streams.
4343 This also will un-set the driver as a recording source (if associated). */
4344 ichac97R3MixerRemoveDrv(pDevIns, pThisCC, pDrv);
4345 LogFunc(("Detached LUN#%u\n", pDrv->uLUN));
4346
4347 DEVAC97_UNLOCK(pDevIns, pThis);
4348
4349 RTMemFree(pDrv);
4350 return;
4351 }
4352 }
4353
4354 DEVAC97_UNLOCK(pDevIns, pThis);
4355 LogFunc(("LUN#%u was not found\n", iLUN));
4356}
4357
4358
4359/**
4360 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4361 */
4362static DECLCALLBACK(int) ichac97R3Destruct(PPDMDEVINS pDevIns)
4363{
4364 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4365 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4366
4367 LogFlowFuncEnter();
4368
4369 PAC97DRIVER pDrv, pDrvNext;
4370 RTListForEachSafe(&pThisCC->lstDrv, pDrv, pDrvNext, AC97DRIVER, Node)
4371 {
4372 RTListNodeRemove(&pDrv->Node);
4373 RTMemFree(pDrv);
4374 }
4375
4376 /* Sanity. */
4377 Assert(RTListIsEmpty(&pThisCC->lstDrv));
4378
4379 /* We don't always go via PowerOff, so make sure the mixer is destroyed. */
4380 if (pThisCC->pMixer)
4381 {
4382 AudioMixerDestroy(pThisCC->pMixer, pDevIns);
4383 pThisCC->pMixer = NULL;
4384 }
4385
4386 return VINF_SUCCESS;
4387}
4388
4389
4390/**
4391 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4392 */
4393static DECLCALLBACK(int) ichac97R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4394{
4395 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4396 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4397 PAC97STATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAC97STATER3);
4398 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4399 Assert(iInstance == 0); RT_NOREF(iInstance);
4400
4401 /*
4402 * Initialize data so we can run the destructor without scewing up.
4403 */
4404 pThisCC->pDevIns = pDevIns;
4405 pThisCC->IBase.pfnQueryInterface = ichac97R3QueryInterface;
4406 RTListInit(&pThisCC->lstDrv);
4407
4408 /*
4409 * Validate and read configuration.
4410 */
4411 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "BufSizeInMs|BufSizeOutMs|Codec|TimerHz|DebugEnabled|DebugPathOut", "");
4412
4413 /** @devcfgm{ac97,BufSizeInMs,uint16_t,0,2000,0,ms}
4414 * The size of the DMA buffer for input streams expressed in milliseconds. */
4415 int rc = pHlp->pfnCFGMQueryU16Def(pCfg, "BufSizeInMs", &pThis->cMsCircBufIn, 0);
4416 if (RT_FAILURE(rc))
4417 return PDMDEV_SET_ERROR(pDevIns, rc,
4418 N_("AC97 configuration error: failed to read 'BufSizeInMs' as 16-bit unsigned integer"));
4419 if (pThis->cMsCircBufIn > 2000)
4420 return PDMDEV_SET_ERROR(pDevIns, VERR_OUT_OF_RANGE,
4421 N_("AC97 configuration error: 'BufSizeInMs' is out of bound, max 2000 ms"));
4422
4423 /** @devcfgm{ac97,BufSizeOutMs,uint16_t,0,2000,0,ms}
4424 * The size of the DMA buffer for output streams expressed in milliseconds. */
4425 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "BufSizeOutMs", &pThis->cMsCircBufOut, 0);
4426 if (RT_FAILURE(rc))
4427 return PDMDEV_SET_ERROR(pDevIns, rc,
4428 N_("AC97 configuration error: failed to read 'BufSizeOutMs' as 16-bit unsigned integer"));
4429 if (pThis->cMsCircBufOut > 2000)
4430 return PDMDEV_SET_ERROR(pDevIns, VERR_OUT_OF_RANGE,
4431 N_("AC97 configuration error: 'BufSizeOutMs' is out of bound, max 2000 ms"));
4432
4433 /** @devcfgm{ac97,TimerHz,uint16_t,10,1000,100,ms}
4434 * Currently the approximate rate at which the asynchronous I/O threads move
4435 * data from/to the DMA buffer, thru the mixer and drivers stack, and
4436 * to/from the host device/whatever. (It does NOT govern any DMA timer rate any
4437 * more as might be hinted at by the name.) */
4438 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, AC97_TIMER_HZ_DEFAULT);
4439 if (RT_FAILURE(rc))
4440 return PDMDEV_SET_ERROR(pDevIns, rc,
4441 N_("AC'97 configuration error: failed to read 'TimerHz' as a 16-bit unsigned integer"));
4442 if (pThis->uTimerHz < 10 || pThis->uTimerHz > 1000)
4443 return PDMDEV_SET_ERROR(pDevIns, VERR_OUT_OF_RANGE,
4444 N_("AC'97 configuration error: 'TimerHz' is out of range (10-1000 Hz)"));
4445
4446 if (pThis->uTimerHz != AC97_TIMER_HZ_DEFAULT)
4447 LogRel(("AC97: Using custom device timer rate: %RU16 Hz\n", pThis->uTimerHz));
4448
4449 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "DebugEnabled", &pThisCC->Dbg.fEnabled, false);
4450 if (RT_FAILURE(rc))
4451 return PDMDEV_SET_ERROR(pDevIns, rc,
4452 N_("AC97 configuration error: failed to read debugging enabled flag as boolean"));
4453
4454 rc = pHlp->pfnCFGMQueryStringAllocDef(pCfg, "DebugPathOut", &pThisCC->Dbg.pszOutPath, NULL);
4455 if (RT_FAILURE(rc))
4456 return PDMDEV_SET_ERROR(pDevIns, rc,
4457 N_("AC97 configuration error: failed to read debugging output path flag as string"));
4458
4459 if (pThisCC->Dbg.fEnabled)
4460 LogRel2(("AC97: Debug output will be saved to '%s'\n", pThisCC->Dbg.pszOutPath));
4461
4462 /*
4463 * The AD1980 codec (with corresponding PCI subsystem vendor ID) is whitelisted
4464 * in the Linux kernel; Linux makes no attempt to measure the data rate and assumes
4465 * 48 kHz rate, which is exactly what we need. Same goes for AD1981B.
4466 */
4467 char szCodec[20];
4468 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "Codec", &szCodec[0], sizeof(szCodec), "STAC9700");
4469 if (RT_FAILURE(rc))
4470 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4471 N_("AC'97 configuration error: Querying \"Codec\" as string failed"));
4472 if (!strcmp(szCodec, "STAC9700"))
4473 pThis->enmCodecModel = AC97CODEC_STAC9700;
4474 else if (!strcmp(szCodec, "AD1980"))
4475 pThis->enmCodecModel = AC97CODEC_AD1980;
4476 else if (!strcmp(szCodec, "AD1981B"))
4477 pThis->enmCodecModel = AC97CODEC_AD1981B;
4478 else
4479 return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
4480 N_("AC'97 configuration error: The \"Codec\" value \"%s\" is unsupported"), szCodec);
4481
4482 LogRel(("AC97: Using codec '%s'\n", szCodec));
4483
4484 /*
4485 * Use an own critical section for the device instead of the default
4486 * one provided by PDM. This allows fine-grained locking in combination
4487 * with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4488 */
4489 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "AC'97");
4490 AssertRCReturn(rc, rc);
4491
4492 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4493 AssertRCReturn(rc, rc);
4494
4495 /*
4496 * Initialize data (most of it anyway).
4497 */
4498 /* PCI Device */
4499 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4500 PCIDevSetVendorId(pPciDev, 0x8086); /* 00 ro - intel. */ Assert(pPciDev->abConfig[0x00] == 0x86); Assert(pPciDev->abConfig[0x01] == 0x80);
4501 PCIDevSetDeviceId(pPciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pPciDev->abConfig[0x02] == 0x15); Assert(pPciDev->abConfig[0x03] == 0x24);
4502 PCIDevSetCommand(pPciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pPciDev->abConfig[0x04] == 0x00); Assert(pPciDev->abConfig[0x05] == 0x00);
4503 PCIDevSetStatus(pPciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pPciDev->abConfig[0x06] == 0x80); Assert(pPciDev->abConfig[0x07] == 0x02);
4504 PCIDevSetRevisionId(pPciDev, 0x01); /* 08 ro - rid. */ Assert(pPciDev->abConfig[0x08] == 0x01);
4505 PCIDevSetClassProg(pPciDev, 0x00); /* 09 ro - pi. */ Assert(pPciDev->abConfig[0x09] == 0x00);
4506 PCIDevSetClassSub(pPciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pPciDev->abConfig[0x0a] == 0x01);
4507 PCIDevSetClassBase(pPciDev, 0x04); /* 0b ro - bcc; 04 == multimedia.*/Assert(pPciDev->abConfig[0x0b] == 0x04);
4508 PCIDevSetHeaderType(pPciDev, 0x00); /* 0e ro - headtyp. */ Assert(pPciDev->abConfig[0x0e] == 0x00);
4509 PCIDevSetBaseAddress(pPciDev, 0, /* 10 rw - nambar - native audio mixer base. */
4510 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x10] == 0x01); Assert(pPciDev->abConfig[0x11] == 0x00); Assert(pPciDev->abConfig[0x12] == 0x00); Assert(pPciDev->abConfig[0x13] == 0x00);
4511 PCIDevSetBaseAddress(pPciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */
4512 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pPciDev->abConfig[0x14] == 0x01); Assert(pPciDev->abConfig[0x15] == 0x00); Assert(pPciDev->abConfig[0x16] == 0x00); Assert(pPciDev->abConfig[0x17] == 0x00);
4513 PCIDevSetInterruptLine(pPciDev, 0x00); /* 3c rw. */ Assert(pPciDev->abConfig[0x3c] == 0x00);
4514 PCIDevSetInterruptPin(pPciDev, 0x01); /* 3d ro - INTA#. */ Assert(pPciDev->abConfig[0x3d] == 0x01);
4515
4516 if (pThis->enmCodecModel == AC97CODEC_AD1980)
4517 {
4518 PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4519 PCIDevSetSubSystemId(pPciDev, 0x0177); /* 2e ro. */
4520 }
4521 else if (pThis->enmCodecModel == AC97CODEC_AD1981B)
4522 {
4523 PCIDevSetSubSystemVendorId(pPciDev, 0x1028); /* 2c ro - Dell.) */
4524 PCIDevSetSubSystemId(pPciDev, 0x01ad); /* 2e ro. */
4525 }
4526 else
4527 {
4528 PCIDevSetSubSystemVendorId(pPciDev, 0x8086); /* 2c ro - Intel.) */
4529 PCIDevSetSubSystemId(pPciDev, 0x0000); /* 2e ro. */
4530 }
4531
4532 /*
4533 * Register the PCI device and associated I/O regions.
4534 */
4535 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4536 if (RT_FAILURE(rc))
4537 return rc;
4538
4539 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 0 /*iPciRegion*/, 256 /*cPorts*/,
4540 ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /*pvUser*/,
4541 "ICHAC97 NAM", NULL /*paExtDescs*/, &pThis->hIoPortsNam);
4542 AssertRCReturn(rc, rc);
4543
4544 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 1 /*iPciRegion*/, 64 /*cPorts*/,
4545 ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /*pvUser*/,
4546 "ICHAC97 NABM", g_aNabmPorts, &pThis->hIoPortsNabm);
4547 AssertRCReturn(rc, rc);
4548
4549 /*
4550 * Saved state.
4551 */
4552 rc = PDMDevHlpSSMRegister(pDevIns, AC97_SAVED_STATE_VERSION, sizeof(*pThis), ichac97R3SaveExec, ichac97R3LoadExec);
4553 if (RT_FAILURE(rc))
4554 return rc;
4555
4556 /*
4557 * Attach drivers. We ASSUME they are configured consecutively without any
4558 * gaps, so we stop when we hit the first LUN w/o a driver configured.
4559 */
4560 for (unsigned iLun = 0; ; iLun++)
4561 {
4562 AssertBreak(iLun < UINT8_MAX);
4563 LogFunc(("Trying to attach driver for LUN#%u ...\n", iLun));
4564 rc = ichac97R3AttachInternal(pDevIns, pThisCC, iLun, NULL /* ppDrv */);
4565 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4566 {
4567 LogFunc(("cLUNs=%u\n", iLun));
4568 break;
4569 }
4570 AssertLogRelMsgReturn(RT_SUCCESS(rc), ("LUN#%u: rc=%Rrc\n", iLun, rc), rc);
4571 }
4572
4573 uint32_t fMixer = AUDMIXER_FLAGS_NONE;
4574 if (pThisCC->Dbg.fEnabled)
4575 fMixer |= AUDMIXER_FLAGS_DEBUG;
4576
4577 rc = AudioMixerCreate("AC'97 Mixer", 0 /* uFlags */, &pThisCC->pMixer);
4578 AssertRCReturn(rc, rc);
4579
4580 rc = AudioMixerCreateSink(pThisCC->pMixer, "Line In",
4581 PDMAUDIODIR_IN, pDevIns, &pThisCC->pSinkLineIn);
4582 AssertRCReturn(rc, rc);
4583 rc = AudioMixerCreateSink(pThisCC->pMixer, "Microphone In",
4584 PDMAUDIODIR_IN, pDevIns, &pThisCC->pSinkMicIn);
4585 AssertRCReturn(rc, rc);
4586 rc = AudioMixerCreateSink(pThisCC->pMixer, "PCM Output",
4587 PDMAUDIODIR_OUT, pDevIns, &pThisCC->pSinkOut);
4588 AssertRCReturn(rc, rc);
4589
4590 /*
4591 * Create all hardware streams.
4592 */
4593 AssertCompile(RT_ELEMENTS(pThis->aStreams) == AC97_MAX_STREAMS);
4594 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4595 {
4596 rc = ichac97R3StreamConstruct(pThisCC, &pThis->aStreams[i], &pThisCC->aStreams[i], i /* SD# */);
4597 AssertRCReturn(rc, rc);
4598 }
4599
4600 /*
4601 * Create the emulation timers (one per stream).
4602 *
4603 * We must the critical section for the timers as the device has a
4604 * noop section associated with it.
4605 *
4606 * Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's AC'97 driver
4607 * relies on exact (virtual) DMA timing and uses DMA Position Buffers
4608 * instead of the LPIB registers.
4609 */
4610 /** @todo r=bird: The need to use virtual sync is perhaps because TM
4611 * doesn't schedule regular TMCLOCK_VIRTUAL timers as accurately as it
4612 * should (VT-x preemption timer, etc). Hope to address that before
4613 * long. @bugref{9943}. */
4614 static const char * const s_apszNames[] = { "AC97 PI", "AC97 PO", "AC97 MC" };
4615 AssertCompile(RT_ELEMENTS(s_apszNames) == AC97_MAX_STREAMS);
4616 for (unsigned i = 0; i < AC97_MAX_STREAMS; i++)
4617 {
4618 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, ichac97R3Timer, &pThis->aStreams[i],
4619 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, s_apszNames[i], &pThis->aStreams[i].hTimer);
4620 AssertRCReturn(rc, rc);
4621
4622 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->aStreams[i].hTimer, &pThis->CritSect);
4623 AssertRCReturn(rc, rc);
4624 }
4625
4626 ichac97R3Reset(pDevIns);
4627
4628 /*
4629 * Info items.
4630 */
4631 //PDMDevHlpDBGFInfoRegister(pDevIns, "ac97", "AC'97 registers. (ac97 [register case-insensitive])", ichac97R3DbgInfo);
4632 PDMDevHlpDBGFInfoRegister(pDevIns, "ac97bdl", "AC'97 buffer descriptor list (BDL). (ac97bdl [stream number])",
4633 ichac97R3DbgInfoBDL);
4634 PDMDevHlpDBGFInfoRegister(pDevIns, "ac97stream", "AC'97 stream info. (ac97stream [stream number])", ichac97R3DbgInfoStream);
4635 PDMDevHlpDBGFInfoRegister(pDevIns, "ac97mixer", "AC'97 mixer state.", ichac97R3DbgInfoMixer);
4636
4637 /*
4638 * Register statistics.
4639 */
4640 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmReads, STAMTYPE_COUNTER, "UnimplementedNabmReads", STAMUNIT_OCCURENCES, "Unimplemented NABM register reads.");
4641 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmWrites, STAMTYPE_COUNTER, "UnimplementedNabmWrites", STAMUNIT_OCCURENCES, "Unimplemented NABM register writes.");
4642 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNamReads, STAMTYPE_COUNTER, "UnimplementedNamReads", STAMUNIT_OCCURENCES, "Unimplemented NAM register reads.");
4643 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNamWrites, STAMTYPE_COUNTER, "UnimplementedNamWrites", STAMUNIT_OCCURENCES, "Unimplemented NAM register writes.");
4644# ifdef VBOX_WITH_STATISTICS
4645 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
4646# endif
4647 for (unsigned idxStream = 0; idxStream < RT_ELEMENTS(pThis->aStreams); idxStream++)
4648 {
4649 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].cbDmaPeriod, STAMTYPE_U32, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4650 "Bytes to transfer in the current DMA period.", "Stream%u/cbTransferChunk", idxStream);
4651 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].Regs.cr, STAMTYPE_X8, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
4652 "Control register (CR), bit 0 is the run bit.", "Stream%u/reg-CR", idxStream);
4653 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].Regs.sr, STAMTYPE_X16, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
4654 "Status register (SR).", "Stream%u/reg-SR", idxStream);
4655 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.Cfg.Props.uHz, STAMTYPE_U32, STAMVISIBILITY_USED, STAMUNIT_HZ,
4656 "The stream frequency.", "Stream%u/Hz", idxStream);
4657 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.Cfg.Props.cbFrame, STAMTYPE_U8, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4658 "The frame size.", "Stream%u/FrameSize", idxStream);
4659 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.offRead, STAMTYPE_U64, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4660 "Virtual internal buffer read position.", "Stream%u/offRead", idxStream);
4661 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.offWrite, STAMTYPE_U64, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4662 "Virtual internal buffer write position.", "Stream%u/offWrite", idxStream);
4663 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaBufSize, STAMTYPE_U32, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4664 "Size of the internal DMA buffer.", "Stream%u/DMABufSize", idxStream);
4665 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaBufUsed, STAMTYPE_U32, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4666 "Number of bytes used in the internal DMA buffer.", "Stream%u/DMABufUsed", idxStream);
4667 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaFlowProblems, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
4668 "Number of internal DMA buffer problems.", "Stream%u/DMABufferProblems", idxStream);
4669 if (ichac97R3GetDirFromSD(idxStream) == PDMAUDIODIR_OUT)
4670 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaFlowErrors, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
4671 "Number of internal DMA buffer overflows.", "Stream%u/DMABufferOverflows", idxStream);
4672 else
4673 {
4674 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaFlowErrors, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
4675 "Number of internal DMA buffer underuns.", "Stream%u/DMABufferUnderruns", idxStream);
4676 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaFlowErrorBytes, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_BYTES,
4677 "Number of bytes of silence added to cope with underruns.", "Stream%u/DMABufferSilence", idxStream);
4678 }
4679 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaSkippedDch, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
4680 "DMA transfer period skipped, controller halted (DCH).", "Stream%u/DMASkippedDch", idxStream);
4681 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaSkippedPendingBcis, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
4682 "DMA transfer period skipped because of BCIS pending.", "Stream%u/DMASkippedPendingBCIS", idxStream);
4683
4684 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatStart, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
4685 "Starting the stream.", "Stream%u/Start", idxStream);
4686 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatStop, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
4687 "Stopping the stream.", "Stream%u/Stop", idxStream);
4688 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatReset, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
4689 "Resetting the stream.", "Stream%u/Reset", idxStream);
4690 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatReSetUpChanged, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
4691 "ichac97R3StreamReSetUp when recreating the streams.", "Stream%u/ReSetUp-Change", idxStream);
4692 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatReSetUpSame, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
4693 "ichac97R3StreamReSetUp when no change.", "Stream%u/ReSetUp-NoChange", idxStream);
4694 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatWriteCr, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
4695 "CR register writes.", "Stream%u/WriteCr", idxStream);
4696 PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatWriteLviRecover, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
4697 "LVI register writes recovering from underflow.", "Stream%u/WriteLviRecover", idxStream);
4698 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].StatWriteLvi, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
4699 "LVI register writes (non-recoving).", "Stream%u/WriteLvi", idxStream);
4700 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].StatWriteSr1, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
4701 "SR register 1-byte writes.", "Stream%u/WriteSr-1byte", idxStream);
4702 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].StatWriteSr2, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
4703 "SR register 2-byte writes.", "Stream%u/WriteSr-2byte", idxStream);
4704 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].StatWriteBdBar, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
4705 "BDBAR register writes.", "Stream%u/WriteBdBar", idxStream);
4706 }
4707
4708 LogFlowFuncLeaveRC(VINF_SUCCESS);
4709 return VINF_SUCCESS;
4710}
4711
4712#else /* !IN_RING3 */
4713
4714/**
4715 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4716 */
4717static DECLCALLBACK(int) ichac97RZConstruct(PPDMDEVINS pDevIns)
4718{
4719 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4720 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);
4721
4722 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4723 AssertRCReturn(rc, rc);
4724
4725 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNam, ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /*pvUser*/);
4726 AssertRCReturn(rc, rc);
4727 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsNabm, ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /*pvUser*/);
4728 AssertRCReturn(rc, rc);
4729
4730 return VINF_SUCCESS;
4731}
4732
4733#endif /* !IN_RING3 */
4734
4735/**
4736 * The device registration structure.
4737 */
4738const PDMDEVREG g_DeviceICHAC97 =
4739{
4740 /* .u32Version = */ PDM_DEVREG_VERSION,
4741 /* .uReserved0 = */ 0,
4742 /* .szName = */ "ichac97",
4743 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE
4744 | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION /* stream clearnup with working drivers */,
4745 /* .fClass = */ PDM_DEVREG_CLASS_AUDIO,
4746 /* .cMaxInstances = */ 1,
4747 /* .uSharedVersion = */ 42,
4748 /* .cbInstanceShared = */ sizeof(AC97STATE),
4749 /* .cbInstanceCC = */ CTX_EXPR(sizeof(AC97STATER3), 0, 0),
4750 /* .cbInstanceRC = */ 0,
4751 /* .cMaxPciDevices = */ 1,
4752 /* .cMaxMsixVectors = */ 0,
4753 /* .pszDescription = */ "ICH AC'97 Audio Controller",
4754#if defined(IN_RING3)
4755 /* .pszRCMod = */ "VBoxDDRC.rc",
4756 /* .pszR0Mod = */ "VBoxDDR0.r0",
4757 /* .pfnConstruct = */ ichac97R3Construct,
4758 /* .pfnDestruct = */ ichac97R3Destruct,
4759 /* .pfnRelocate = */ NULL,
4760 /* .pfnMemSetup = */ NULL,
4761 /* .pfnPowerOn = */ NULL,
4762 /* .pfnReset = */ ichac97R3Reset,
4763 /* .pfnSuspend = */ NULL,
4764 /* .pfnResume = */ NULL,
4765 /* .pfnAttach = */ ichac97R3Attach,
4766 /* .pfnDetach = */ ichac97R3Detach,
4767 /* .pfnQueryInterface = */ NULL,
4768 /* .pfnInitComplete = */ NULL,
4769 /* .pfnPowerOff = */ ichac97R3PowerOff,
4770 /* .pfnSoftReset = */ NULL,
4771 /* .pfnReserved0 = */ NULL,
4772 /* .pfnReserved1 = */ NULL,
4773 /* .pfnReserved2 = */ NULL,
4774 /* .pfnReserved3 = */ NULL,
4775 /* .pfnReserved4 = */ NULL,
4776 /* .pfnReserved5 = */ NULL,
4777 /* .pfnReserved6 = */ NULL,
4778 /* .pfnReserved7 = */ NULL,
4779#elif defined(IN_RING0)
4780 /* .pfnEarlyConstruct = */ NULL,
4781 /* .pfnConstruct = */ ichac97RZConstruct,
4782 /* .pfnDestruct = */ NULL,
4783 /* .pfnFinalDestruct = */ NULL,
4784 /* .pfnRequest = */ NULL,
4785 /* .pfnReserved0 = */ NULL,
4786 /* .pfnReserved1 = */ NULL,
4787 /* .pfnReserved2 = */ NULL,
4788 /* .pfnReserved3 = */ NULL,
4789 /* .pfnReserved4 = */ NULL,
4790 /* .pfnReserved5 = */ NULL,
4791 /* .pfnReserved6 = */ NULL,
4792 /* .pfnReserved7 = */ NULL,
4793#elif defined(IN_RC)
4794 /* .pfnConstruct = */ ichac97RZConstruct,
4795 /* .pfnReserved0 = */ NULL,
4796 /* .pfnReserved1 = */ NULL,
4797 /* .pfnReserved2 = */ NULL,
4798 /* .pfnReserved3 = */ NULL,
4799 /* .pfnReserved4 = */ NULL,
4800 /* .pfnReserved5 = */ NULL,
4801 /* .pfnReserved6 = */ NULL,
4802 /* .pfnReserved7 = */ NULL,
4803#else
4804# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4805#endif
4806 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4807};
4808
4809#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4810
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