VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 55043

Last change on this file since 55043 was 55005, checked in by vboxsync, 10 years ago

PDM/Audio: Added volume through virtual mixer.
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1/* $Id: DevIchHda.cpp 55005 2015-03-30 12:07:39Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2015 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/vmm/pdmaudioifs.h>
27#include <VBox/version.h>
28
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#ifdef IN_RING3
33# include <iprt/uuid.h>
34# include <iprt/string.h>
35# include <iprt/mem.h>
36#endif
37#include <iprt/list.h>
38
39#ifdef LOG_GROUP
40# undef LOG_GROUP
41#endif
42#define LOG_GROUP LOG_GROUP_DEV_AUDIO
43#include <VBox/log.h>
44
45#include "VBoxDD.h"
46
47#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
48# include "AudioMixer.h"
49#else
50 extern "C" {
51 #include "audio.h"
52 }
53#endif
54#include "DevIchHdaCodec.h"
55
56/*******************************************************************************
57* Defined Constants And Macros *
58*******************************************************************************/
59//#define HDA_AS_PCI_EXPRESS
60#define VBOX_WITH_INTEL_HDA
61
62#if (defined(DEBUG) && defined(DEBUG_andy))
63/* Enables experimental support for separate mic-in handling.
64 Do not enable this yet for regular builds, as this needs more testing first! */
65# define VBOX_WITH_HDA_MIC_IN
66#endif
67
68#if defined(VBOX_WITH_HP_HDA)
69/* HP Pavilion dv4t-1300 */
70# define HDA_PCI_VENDOR_ID 0x103c
71# define HDA_PCI_DEVICE_ID 0x30f7
72#elif defined(VBOX_WITH_INTEL_HDA)
73/* Intel HDA controller */
74# define HDA_PCI_VENDOR_ID 0x8086
75# define HDA_PCI_DEVICE_ID 0x2668
76#elif defined(VBOX_WITH_NVIDIA_HDA)
77/* nVidia HDA controller */
78# define HDA_PCI_VENDOR_ID 0x10de
79# define HDA_PCI_DEVICE_ID 0x0ac0
80#else
81# error "Please specify your HDA device vendor/device IDs"
82#endif
83
84/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
85 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
86 * is read only except for bit 15 like the HDA spec states.
87 *
88 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
89 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
90#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
91
92#define HDA_NREGS 114
93#define HDA_NREGS_SAVED 112
94
95/**
96 * NB: Register values stored in memory (au32Regs[]) are indexed through
97 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
98 * register descriptors in g_aHdaRegMap[] are indexed through the
99 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
100 *
101 * The au32Regs[] layout is kept unchanged for saved state
102 * compatibility. */
103
104/* Registers */
105#define HDA_REG_IND_NAME(x) HDA_REG_##x
106#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
107#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
108#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
109#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
110#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
111#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
112#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
113
114
115#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
116#define HDA_RMX_GCAP 0
117/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
118 * oss (15:12) - number of output streams supported
119 * iss (11:8) - number of input streams supported
120 * bss (7:3) - number of bidirectional streams supported
121 * bds (2:1) - number of serial data out signals supported
122 * b64sup (0) - 64 bit addressing supported.
123 */
124#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
125 ( (((oss) & 0xF) << 12) \
126 | (((iss) & 0xF) << 8) \
127 | (((bss) & 0x1F) << 3) \
128 | (((bds) & 0x3) << 2) \
129 | ((b64sup) & 1))
130
131#define HDA_REG_VMIN 1 /* 0x02 */
132#define HDA_RMX_VMIN 1
133
134#define HDA_REG_VMAJ 2 /* 0x03 */
135#define HDA_RMX_VMAJ 2
136
137#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
138#define HDA_RMX_OUTPAY 3
139
140#define HDA_REG_INPAY 4 /* 0x06-0x07 */
141#define HDA_RMX_INPAY 4
142
143#define HDA_REG_GCTL 5 /* 0x08-0x0B */
144#define HDA_RMX_GCTL 5
145#define HDA_GCTL_RST_SHIFT 0
146#define HDA_GCTL_FSH_SHIFT 1
147#define HDA_GCTL_UR_SHIFT 8
148
149#define HDA_REG_WAKEEN 6 /* 0x0C */
150#define HDA_RMX_WAKEEN 6
151
152#define HDA_REG_STATESTS 7 /* 0x0E */
153#define HDA_RMX_STATESTS 7
154#define HDA_STATES_SCSF 0x7
155
156#define HDA_REG_GSTS 8 /* 0x10-0x11*/
157#define HDA_RMX_GSTS 8
158#define HDA_GSTS_FSH_SHIFT 1
159
160#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
161#define HDA_RMX_OUTSTRMPAY 112
162
163#define HDA_REG_INSTRMPAY 10 /* 0x1a */
164#define HDA_RMX_INSTRMPAY 113
165
166#define HDA_REG_INTCTL 11 /* 0x20 */
167#define HDA_RMX_INTCTL 9
168#define HDA_INTCTL_GIE_SHIFT 31
169#define HDA_INTCTL_CIE_SHIFT 30
170#define HDA_INTCTL_S0_SHIFT 0
171#define HDA_INTCTL_S1_SHIFT 1
172#define HDA_INTCTL_S2_SHIFT 2
173#define HDA_INTCTL_S3_SHIFT 3
174#define HDA_INTCTL_S4_SHIFT 4
175#define HDA_INTCTL_S5_SHIFT 5
176#define HDA_INTCTL_S6_SHIFT 6
177#define HDA_INTCTL_S7_SHIFT 7
178#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
179
180#define HDA_REG_INTSTS 12 /* 0x24 */
181#define HDA_RMX_INTSTS 10
182#define HDA_INTSTS_GIS_SHIFT 31
183#define HDA_INTSTS_CIS_SHIFT 30
184#define HDA_INTSTS_S0_SHIFT 0
185#define HDA_INTSTS_S1_SHIFT 1
186#define HDA_INTSTS_S2_SHIFT 2
187#define HDA_INTSTS_S3_SHIFT 3
188#define HDA_INTSTS_S4_SHIFT 4
189#define HDA_INTSTS_S5_SHIFT 5
190#define HDA_INTSTS_S6_SHIFT 6
191#define HDA_INTSTS_S7_SHIFT 7
192#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
193
194#define HDA_REG_WALCLK 13 /* 0x24 */
195#define HDA_RMX_WALCLK /* Not defined! */
196
197/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
198 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
199 * the datasheet.
200 */
201#define HDA_REG_SSYNC 14 /* 0x34 */
202#define HDA_RMX_SSYNC 12
203
204#define HDA_REG_CORBLBASE 15 /* 0x40 */
205#define HDA_RMX_CORBLBASE 13
206
207#define HDA_REG_CORBUBASE 16 /* 0x44 */
208#define HDA_RMX_CORBUBASE 14
209
210#define HDA_REG_CORBWP 17 /* 0x48 */
211#define HDA_RMX_CORBWP 15
212
213#define HDA_REG_CORBRP 18 /* 0x4A */
214#define HDA_RMX_CORBRP 16
215#define HDA_CORBRP_RST_SHIFT 15
216#define HDA_CORBRP_WP_SHIFT 0
217#define HDA_CORBRP_WP_MASK 0xFF
218
219#define HDA_REG_CORBCTL 19 /* 0x4C */
220#define HDA_RMX_CORBCTL 17
221#define HDA_CORBCTL_DMA_SHIFT 1
222#define HDA_CORBCTL_CMEIE_SHIFT 0
223
224#define HDA_REG_CORBSTS 20 /* 0x4D */
225#define HDA_RMX_CORBSTS 18
226#define HDA_CORBSTS_CMEI_SHIFT 0
227
228#define HDA_REG_CORBSIZE 21 /* 0x4E */
229#define HDA_RMX_CORBSIZE 19
230#define HDA_CORBSIZE_SZ_CAP 0xF0
231#define HDA_CORBSIZE_SZ 0x3
232/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
233
234#define HDA_REG_RIRBLBASE 22 /* 0x50 */
235#define HDA_RMX_RIRBLBASE 20
236
237#define HDA_REG_RIRBUBASE 23 /* 0x54 */
238#define HDA_RMX_RIRBUBASE 21
239
240#define HDA_REG_RIRBWP 24 /* 0x58 */
241#define HDA_RMX_RIRBWP 22
242#define HDA_RIRBWP_RST_SHIFT 15
243#define HDA_RIRBWP_WP_MASK 0xFF
244
245#define HDA_REG_RINTCNT 25 /* 0x5A */
246#define HDA_RMX_RINTCNT 23
247#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
248
249#define HDA_REG_RIRBCTL 26 /* 0x5C */
250#define HDA_RMX_RIRBCTL 24
251#define HDA_RIRBCTL_RIC_SHIFT 0
252#define HDA_RIRBCTL_DMA_SHIFT 1
253#define HDA_ROI_DMA_SHIFT 2
254
255#define HDA_REG_RIRBSTS 27 /* 0x5D */
256#define HDA_RMX_RIRBSTS 25
257#define HDA_RIRBSTS_RINTFL_SHIFT 0
258#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
259
260#define HDA_REG_RIRBSIZE 28 /* 0x5E */
261#define HDA_RMX_RIRBSIZE 26
262#define HDA_RIRBSIZE_SZ_CAP 0xF0
263#define HDA_RIRBSIZE_SZ 0x3
264
265#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
266#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
267
268
269#define HDA_REG_IC 29 /* 0x60 */
270#define HDA_RMX_IC 27
271
272#define HDA_REG_IR 30 /* 0x64 */
273#define HDA_RMX_IR 28
274
275#define HDA_REG_IRS 31 /* 0x68 */
276#define HDA_RMX_IRS 29
277#define HDA_IRS_ICB_SHIFT 0
278#define HDA_IRS_IRV_SHIFT 1
279
280#define HDA_REG_DPLBASE 32 /* 0x70 */
281#define HDA_RMX_DPLBASE 30
282#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
283
284#define HDA_REG_DPUBASE 33 /* 0x74 */
285#define HDA_RMX_DPUBASE 31
286#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
287#define DPBASE_ENABLED 1
288#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
289
290#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
291#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
292/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
293#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
294
295#define HDA_REG_SD0CTL 34 /* 0x80 */
296#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
297#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
298#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
299#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
300#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
301#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
302#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
303#define HDA_RMX_SD0CTL 32
304#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
305#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
306#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
307#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
308#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
309#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
310#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
311
312#define SD(func, num) SD##num##func
313#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
314#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
315#define HDA_SDCTL_NUM_MASK 0xF
316#define HDA_SDCTL_NUM_SHIFT 20
317#define HDA_SDCTL_DIR_SHIFT 19
318#define HDA_SDCTL_TP_SHIFT 18
319#define HDA_SDCTL_STRIPE_MASK 0x3
320#define HDA_SDCTL_STRIPE_SHIFT 16
321#define HDA_SDCTL_DEIE_SHIFT 4
322#define HDA_SDCTL_FEIE_SHIFT 3
323#define HDA_SDCTL_ICE_SHIFT 2
324#define HDA_SDCTL_RUN_SHIFT 1
325#define HDA_SDCTL_SRST_SHIFT 0
326
327#define HDA_REG_SD0STS 35 /* 0x83 */
328#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
329#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
330#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
331#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
332#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
333#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
334#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
335#define HDA_RMX_SD0STS 33
336#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
337#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
338#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
339#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
340#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
341#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
342#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
343
344#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
345#define HDA_SDSTS_FIFORDY_SHIFT 5
346#define HDA_SDSTS_DE_SHIFT 4
347#define HDA_SDSTS_FE_SHIFT 3
348#define HDA_SDSTS_BCIS_SHIFT 2
349
350#define HDA_REG_SD0LPIB 36 /* 0x84 */
351#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
352#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
353#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
354#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
355#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
356#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
357#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
358#define HDA_RMX_SD0LPIB 34
359#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
360#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
361#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
362#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
363#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
364#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
365#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
366
367#define HDA_REG_SD0CBL 37 /* 0x88 */
368#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
369#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
370#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
371#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
372#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
373#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
374#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
375#define HDA_RMX_SD0CBL 35
376#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
377#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
378#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
379#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
380#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
381#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
382#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
383
384
385#define HDA_REG_SD0LVI 38 /* 0x8C */
386#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
387#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
388#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
389#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
390#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
391#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
392#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
393#define HDA_RMX_SD0LVI 36
394#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
395#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
396#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
397#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
398#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
399#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
400#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
401
402#define HDA_REG_SD0FIFOW 39 /* 0x8E */
403#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
404#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
405#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
406#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
407#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
408#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
409#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
410#define HDA_RMX_SD0FIFOW 37
411#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
412#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
413#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
414#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
415#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
416#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
417#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
418
419/*
420 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
421 */
422#define HDA_SDFIFOW_8B 0x2
423#define HDA_SDFIFOW_16B 0x3
424#define HDA_SDFIFOW_32B 0x4
425
426#define HDA_REG_SD0FIFOS 40 /* 0x90 */
427#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
428#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
429#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
430#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
431#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
432#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
433#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
434#define HDA_RMX_SD0FIFOS 38
435#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
436#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
437#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
438#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
439#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
440#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
441#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
442
443/*
444 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
445 * formula: size - 1
446 * Other values not listed are not supported.
447 */
448#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
449#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
450#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
451#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
452#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
453#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
454#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
455#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
456#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
457
458#define HDA_REG_SD0FMT 41 /* 0x92 */
459#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
460#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
461#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
462#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
463#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
464#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
465#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
466#define HDA_RMX_SD0FMT 39
467#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
468#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
469#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
470#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
471#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
472#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
473#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
474
475#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
476#define HDA_SDFMT_BASE_RATE_SHIFT 14
477#define HDA_SDFMT_MULT_SHIFT 11
478#define HDA_SDFMT_MULT_MASK 0x7
479#define HDA_SDFMT_DIV_SHIFT 8
480#define HDA_SDFMT_DIV_MASK 0x7
481#define HDA_SDFMT_BITS_SHIFT 4
482#define HDA_SDFMT_BITS_MASK 0x7
483#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
484#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
485#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
486
487#define HDA_REG_SD0BDPL 42 /* 0x98 */
488#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
489#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
490#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
491#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
492#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
493#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
494#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
495#define HDA_RMX_SD0BDPL 40
496#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
497#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
498#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
499#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
500#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
501#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
502#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
503
504#define HDA_REG_SD0BDPU 43 /* 0x9C */
505#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
506#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
507#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
508#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
509#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
510#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
511#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
512#define HDA_RMX_SD0BDPU 41
513#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
514#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
515#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
516#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
517#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
518#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
519#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
520
521#define HDA_CODEC_CAD_SHIFT 28
522/* Encodes the (required) LUN into a codec command. */
523#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
524
525
526
527/*******************************************************************************
528* Structures and Typedefs *
529*******************************************************************************/
530typedef struct HDABDLEDESC
531{
532 uint64_t u64BdleCviAddr;
533 uint32_t u32BdleMaxCvi;
534 uint32_t u32BdleCvi;
535 uint32_t u32BdleCviLen;
536 uint32_t u32BdleCviPos;
537 bool fBdleCviIoc;
538 uint32_t cbUnderFifoW;
539 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
540} HDABDLEDESC, *PHDABDLEDESC;
541
542typedef struct HDASTREAMTRANSFERDESC
543{
544 uint64_t u64BaseDMA;
545 uint32_t u32Ctl;
546 uint32_t *pu32Sts;
547 uint8_t u8Strm;
548 uint32_t *pu32Lpib;
549 uint32_t u32Cbl;
550 uint32_t u32Fifos;
551} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
552
553#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
554typedef struct HDAINPUTSTREAM
555{
556 /** PCM line input stream. */
557 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
558 /** Mixer handle for line input stream. */
559 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
560} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
561
562typedef struct HDAOUTPUTSTREAM
563{
564 /** PCM output stream. */
565 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
566} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
567
568/**
569 * Struct for maintaining a host backend driver.
570 * This driver must be associated to one, and only one,
571 * HDA codec. The HDA controller does the actual multiplexing
572 * of HDA codec data to various host backend drivers then.
573 *
574 * This HDA device uses a timer in order to synchronize all
575 * read/write accesses across all attached LUNs / backends.
576 */
577typedef struct HDADRIVER
578{
579 union
580 {
581 /** Node for storing this driver in our device driver
582 * list of HDASTATE. */
583 RTLISTNODE Node;
584 struct
585 {
586 R3PTRTYPE(void *) dummy1;
587 R3PTRTYPE(void *) dummy2;
588 } dummy;
589 };
590
591 /** Pointer to HDA controller (state). */
592 R3PTRTYPE(PHDASTATE) pHDAState;
593 /** Driver flags. */
594 PDMAUDIODRVFLAGS Flags;
595 uint8_t u32Padding0[3];
596 /** LUN to which this driver has been assigned. */
597 uint8_t uLUN;
598 /** Audio connector interface to the underlying
599 * host backend. */
600 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
601 /** Stream for line input. */
602 HDAINPUTSTREAM LineIn;
603 /** Stream for mic input. */
604 HDAINPUTSTREAM MicIn;
605 /** Stream for output. */
606 HDAOUTPUTSTREAM Out;
607} HDADRIVER, *PHDADRIVER;
608#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
609
610/**
611 * ICH Intel HD Audio Controller state.
612 */
613typedef struct HDASTATE
614{
615 /** The PCI device structure. */
616 PCIDevice PciDev;
617 /** R3 Pointer to the device instance. */
618 PPDMDEVINSR3 pDevInsR3;
619 /** R0 Pointer to the device instance. */
620 PPDMDEVINSR0 pDevInsR0;
621 /** R0 Pointer to the device instance. */
622 PPDMDEVINSRC pDevInsRC;
623
624 uint32_t u32Padding;
625
626 /** Pointer to the attached audio driver. */
627 R3PTRTYPE(PPDMIBASE) pDrvBase;
628 /** The base interface for LUN\#0. */
629 PDMIBASE IBase;
630 RTGCPHYS MMIOBaseAddr;
631 uint32_t au32Regs[HDA_NREGS];
632 HDABDLEDESC StInBdle;
633 HDABDLEDESC StOutBdle;
634 HDABDLEDESC StMicBdle;
635 uint64_t u64CORBBase;
636 uint64_t u64RIRBBase;
637 uint64_t u64DPBase;
638 /** Pointer to CORB buffer. */
639 R3PTRTYPE(uint32_t *) pu32CorbBuf;
640 /** Size in bytes of CORB buffer. */
641 uint32_t cbCorbBuf;
642 uint32_t u32Padding2;
643 /** Pointer to RIRB buffer. */
644 R3PTRTYPE(uint64_t *) pu64RirbBuf;
645 /** Size in bytes of RIRB buffer. */
646 uint32_t cbRirbBuf;
647 /** Indicates if HDA is in reset. */
648 bool fInReset;
649 /** Interrupt on completion */
650 bool fCviIoc;
651 /** Flag whether the R0 part is enabled. */
652 bool fR0Enabled;
653 /** Flag whether the RC part is enabled. */
654 bool fRCEnabled;
655#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
656 /** The emulation timer for handling the attached
657 * LUN drivers. */
658 PTMTIMERR3 pTimer;
659 /** Timer ticks for handling the LUN drivers. */
660 uint64_t uTicks;
661# ifdef VBOX_WITH_STATISTICS
662 STAMPROFILE StatTimer;
663 STAMCOUNTER StatBytesRead;
664 STAMCOUNTER StatBytesWritten;
665# endif
666 /** Pointer to HDA codec to use. */
667 R3PTRTYPE(PHDACODEC) pCodec;
668 union
669 {
670 /** List of associated LUN drivers. */
671 RTLISTANCHOR lstDrv;
672 struct
673 {
674 R3PTRTYPE(void *) dummy1;
675 R3PTRTYPE(void *) dummy2;
676 } dummy;
677 };
678 /** The device' software mixer. */
679 R3PTRTYPE(PAUDIOMIXER) pMixer;
680 /** Audio sink for PCM output. */
681 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
682 /** Audio mixer sink for line input. */
683 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
684 /** Audio mixer sink for microphone input. */
685 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
686#else /* !VBOX_WITH_PDM_AUDIO_DRIVER */
687 /** The HDA codec to use. */
688 R3PTRTYPE(PHDACODEC) pCodec;
689#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
690 uint64_t u64BaseTS;
691 /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
692 uint8_t u8Counter;
693#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
694 uint8_t au8Padding[7];
695#else
696 uint8_t au8Padding[7];
697#endif
698} HDASTATE;
699/** Pointer to the ICH Intel HD Audio Controller state. */
700typedef HDASTATE *PHDASTATE;
701
702#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
703 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
704#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
705 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
706
707
708/*******************************************************************************
709* Internal Functions *
710*******************************************************************************/
711#ifndef VBOX_DEVICE_STRUCT_TESTCASE
712static FNPDMDEVRESET hdaReset;
713
714static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
715static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
716static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
717static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
718static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
719static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
720static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
721static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
722static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
723static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
724static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
725static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
726static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
727static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
728static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
729static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
730static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
731
732static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
733static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
734static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
735static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
736static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
737static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
738static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
739static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
740static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
741static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
742static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
743static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
744static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
745static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
746static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
747static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
748
749#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
750static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
751static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail);
752#else
753static int hdaTransfer(PHDACODEC pCodec, ENMSOUNDSOURCE enmSource, int cbAvail);
754#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
755
756#ifdef IN_RING3
757DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
758 PHDASTREAMTRANSFERDESC pStreamDesc);
759static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
760#ifdef LOG_ENABLED
761static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
762#endif
763#endif
764
765
766/*******************************************************************************
767* Global Variables *
768*******************************************************************************/
769
770/* see 302349 p 6.2*/
771static const struct HDAREGDESC
772{
773 /** Register offset in the register space. */
774 uint32_t offset;
775 /** Size in bytes. Registers of size > 4 are in fact tables. */
776 uint32_t size;
777 /** Readable bits. */
778 uint32_t readable;
779 /** Writable bits. */
780 uint32_t writable;
781 /** Read callback. */
782 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
783 /** Write callback. */
784 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
785 /** Index into the register storage array. */
786 uint32_t mem_idx;
787 /** Abbreviated name. */
788 const char *abbrev;
789} g_aHdaRegMap[HDA_NREGS] =
790
791/* Turn a short register name into an memory index and a stringized name. */
792#define RA(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
793/* Same as above for an input stream ('I' prefixed). */
794#define IA(abbrev) HDA_MEM_IND_NAME(abbrev), "I"#abbrev
795/* Same as above for an output stream ('O' prefixed). */
796#define OA(abbrev) HDA_MEM_IND_NAME(abbrev), "O"#abbrev
797/* Same as above for a register *not* stored in memory. */
798#define UA(abbrev) 0, #abbrev
799
800{
801 /* offset size read mask write mask read callback write callback abbrev */
802 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- */
803 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(GCAP) }, /* Global Capabilities */
804 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMIN) }, /* Minor Version */
805 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMAJ) }, /* Major Version */
806 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTPAY) }, /* Output Payload Capabilities */
807 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INPAY) }, /* Input Payload Capabilities */
808 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , RA(GCTL) }, /* Global Control */
809 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , RA(WAKEEN) }, /* Wake Enable */
810 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , RA(STATESTS) }, /* State Change Status */
811 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , RA(GSTS) }, /* Global Status */
812 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTSTRMPAY)}, /* Output Stream Payload Capability */
813 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INSTRMPAY) }, /* Input Stream Payload Capability */
814 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(INTCTL) }, /* Interrupt Control */
815 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , RA(INTSTS) }, /* Interrupt Status */
816 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , UA(WALCLK) }, /* Wall Clock Counter */
817 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
818 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(SSYNC) }, /* Stream Synchronization */
819 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(CORBLBASE) }, /* CORB Lower Base Address */
820 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(CORBUBASE) }, /* CORB Upper Base Address */
821 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , RA(CORBWP) }, /* CORB Write Pointer */
822 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , RA(CORBRP) }, /* CORB Read Pointer */
823 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , RA(CORBCTL) }, /* CORB Control */
824 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , RA(CORBSTS) }, /* CORB Status */
825 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(CORBSIZE) }, /* CORB Size */
826 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBLBASE) }, /* RIRB Lower Base Address */
827 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBUBASE) }, /* RIRB Upper Base Address */
828 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , RA(RIRBWP) }, /* RIRB Write Pointer */
829 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , RA(RINTCNT) }, /* Response Interrupt Count */
830 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , RA(RIRBCTL) }, /* RIRB Control */
831 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , RA(RIRBSTS) }, /* RIRB Status */
832 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(RIRBSIZE) }, /* RIRB Size */
833 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , RA(IC) }, /* Immediate Command */
834 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , RA(IR) }, /* Immediate Response */
835 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , RA(IRS) }, /* Immediate Command Status */
836 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , RA(DPLBASE) }, /* MA Position Lower Base */
837 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(DPUBASE) }, /* DMA Position Upper Base */
838
839 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD0CTL) }, /* Input Stream Descriptor 0 (ICD0) Control */
840 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD0STS) }, /* ISD0 Status */
841 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0LPIB) }, /* ISD0 Link Position In Buffer */
842 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0CBL) }, /* ISD0 Cyclic Buffer Length */
843 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD0LVI) }, /* ISD0 Last Valid Index */
844 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD0FIFOW) }, /* ISD0 FIFO Watermark */
845 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD0FIFOS) }, /* ISD0 FIFO Size */
846 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD0FMT) }, /* ISD0 Format */
847 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD0BDPL) }, /* ISD0 Buffer Descriptor List Pointer-Lower Base Address */
848 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD0BDPU) }, /* ISD0 Buffer Descriptor List Pointer-Upper Base Address */
849
850 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD1CTL) }, /* Input Stream Descriptor 1 (ISD1) Control */
851 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD1STS) }, /* ISD1 Status */
852 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1LPIB) }, /* ISD1 Link Position In Buffer */
853 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1CBL) }, /* ISD1 Cyclic Buffer Length */
854 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD1LVI) }, /* ISD1 Last Valid Index */
855 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD1FIFOW) }, /* ISD1 FIFO Watermark */
856 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD1FIFOS) }, /* ISD1 FIFO Size */
857 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD1FMT) }, /* ISD1 Format */
858 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD1BDPL) }, /* ISD1 Buffer Descriptor List Pointer-Lower Base Address */
859 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD1BDPU) }, /* ISD1 Buffer Descriptor List Pointer-Upper Base Address */
860
861 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD2CTL) }, /* Input Stream Descriptor 2 (ISD2) Control */
862 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD2STS) }, /* ISD2 Status */
863 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2LPIB) }, /* ISD2 Link Position In Buffer */
864 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2CBL) }, /* ISD2 Cyclic Buffer Length */
865 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD2LVI) }, /* ISD2 Last Valid Index */
866 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD2FIFOW) }, /* ISD2 FIFO Watermark */
867 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD2FIFOS) }, /* ISD2 FIFO Size */
868 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD2FMT) }, /* ISD2 Format */
869 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD2BDPL) }, /* ISD2 Buffer Descriptor List Pointer-Lower Base Address */
870 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD2BDPU) }, /* ISD2 Buffer Descriptor List Pointer-Upper Base Address */
871
872 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD3CTL) }, /* Input Stream Descriptor 3 (ISD3) Control */
873 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD3STS) }, /* ISD3 Status */
874 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3LPIB) }, /* ISD3 Link Position In Buffer */
875 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3CBL) }, /* ISD3 Cyclic Buffer Length */
876 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD3LVI) }, /* ISD3 Last Valid Index */
877 { 0x000EE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD3FIFOW) }, /* ISD3 FIFO Watermark */
878 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD3FIFOS) }, /* ISD3 FIFO Size */
879 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD3FMT) }, /* ISD3 Format */
880 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD3BDPL) }, /* ISD3 Buffer Descriptor List Pointer-Lower Base Address */
881 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD3BDPU) }, /* ISD3 Buffer Descriptor List Pointer-Upper Base Address */
882
883 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD4CTL) }, /* Output Stream Descriptor 4 (OSD4) Control */
884 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD4STS) }, /* OSD4 Status */
885 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4LPIB) }, /* OSD4 Link Position In Buffer */
886 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4CBL) }, /* OSD4 Cyclic Buffer Length */
887 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD4LVI) }, /* OSD4 Last Valid Index */
888 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD4FIFOW) }, /* OSD4 FIFO Watermark */
889 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD4FIFOS) }, /* OSD4 FIFO Size */
890 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD4FMT) }, /* OSD4 Format */
891 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD4BDPL) }, /* OSD4 Buffer Descriptor List Pointer-Lower Base Address */
892 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD4BDPU) }, /* OSD4 Buffer Descriptor List Pointer-Upper Base Address */
893
894 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD5CTL) }, /* Output Stream Descriptor 5 (OSD5) Control */
895 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD5STS) }, /* OSD5 Status */
896 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5LPIB) }, /* OSD5 Link Position In Buffer */
897 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5CBL) }, /* OSD5 Cyclic Buffer Length */
898 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD5LVI) }, /* OSD5 Last Valid Index */
899 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD5FIFOW) }, /* OSD5 FIFO Watermark */
900 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD5FIFOS) }, /* OSD5 FIFO Size */
901 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD5FMT) }, /* OSD5 Format */
902 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD5BDPL) }, /* OSD5 Buffer Descriptor List Pointer-Lower Base Address */
903 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD5BDPU) }, /* OSD5 Buffer Descriptor List Pointer-Upper Base Address */
904
905 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD6CTL) }, /* Output Stream Descriptor 6 (OSD6) Control */
906 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD6STS) }, /* OSD6 Status */
907 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6LPIB) }, /* OSD6 Link Position In Buffer */
908 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6CBL) }, /* OSD6 Cyclic Buffer Length */
909 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD6LVI) }, /* OSD6 Last Valid Index */
910 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD6FIFOW) }, /* OSD6 FIFO Watermark */
911 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD6FIFOS) }, /* OSD6 FIFO Size */
912 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD6FMT) }, /* OSD6 Format */
913 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD6BDPL) }, /* OSD6 Buffer Descriptor List Pointer-Lower Base Address */
914 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD6BDPU) }, /* OSD6 Buffer Descriptor List Pointer-Upper Base Address */
915
916 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD7CTL) }, /* Output Stream Descriptor 7 (OSD7) Control */
917 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD7STS) }, /* OSD7 Status */
918 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7LPIB) }, /* OSD7 Link Position In Buffer */
919 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7CBL) }, /* OSD7 Cyclic Buffer Length */
920 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD7LVI) }, /* OSD7 Last Valid Index */
921 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD7FIFOW) }, /* OSD7 FIFO Watermark */
922 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD7FIFOS) }, /* OSD7 FIFO Size */
923 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD7FMT) }, /* OSD7 Format */
924 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD7BDPL) }, /* OSD7 Buffer Descriptor List Pointer-Lower Base Address */
925 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD7BDPU) }, /* OSD7 Buffer Descriptor List Pointer-Upper Base Address */
926};
927
928/**
929 * HDA register aliases (HDA spec 3.3.45).
930 * @remarks Sorted by offReg.
931 */
932static const struct
933{
934 /** The alias register offset. */
935 uint32_t offReg;
936 /** The register index. */
937 int idxAlias;
938} g_aHdaRegAliases[] =
939{
940 { 0x2084, HDA_REG_SD0LPIB },
941 { 0x20a4, HDA_REG_SD1LPIB },
942 { 0x20c4, HDA_REG_SD2LPIB },
943 { 0x20e4, HDA_REG_SD3LPIB },
944 { 0x2104, HDA_REG_SD4LPIB },
945 { 0x2124, HDA_REG_SD5LPIB },
946 { 0x2144, HDA_REG_SD6LPIB },
947 { 0x2164, HDA_REG_SD7LPIB },
948};
949
950#ifdef IN_RING3
951/** HDABDLEDESC field descriptors the v3+ saved state. */
952static SSMFIELD const g_aHdaBDLEDescFields[] =
953{
954 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
955 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
956 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
957 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
958 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
959 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
960 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
961 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
962 SSMFIELD_ENTRY_TERM()
963};
964
965/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
966static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
967{
968 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
969 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
970 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
971 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
972 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
973 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
974 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
975 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
976 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
977 SSMFIELD_ENTRY_TERM()
978};
979#endif
980
981/**
982 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
983 */
984static uint32_t const g_afMasks[5] =
985{
986 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
987};
988
989#ifdef IN_RING3
990DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
991{
992 if (pThis->u64DPBase & DPBASE_ENABLED)
993 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
994 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
995 pStreamDesc->pu32Lpib, sizeof(uint32_t));
996}
997#endif
998
999DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
1000{
1001#if 0
1002 switch(HDA_STREAM_REG(pThis, FIFOW, pStreamDesc->u8Strm))
1003 {
1004 case HDA_SDFIFOW_8B: return 8;
1005 case HDA_SDFIFOW_16B: return 16;
1006 case HDA_SDFIFOW_32B: return 32;
1007 default:
1008 AssertMsgFailed(("unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
1009 }
1010#endif
1011 return 0;
1012}
1013
1014static int hdaProcessInterrupt(PHDASTATE pThis)
1015{
1016#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1017 ( INTCTL_SX((pThis), num) \
1018 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1019 bool fIrq = false;
1020 if ( HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1021 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1022 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1023 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1024 fIrq = true;
1025
1026 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1027 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1028 fIrq = true;
1029
1030 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1031 {
1032 LogFunc(("irq %s\n", fIrq ? "asserted" : "deasserted"));
1033 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1034 }
1035 return VINF_SUCCESS;
1036}
1037
1038/**
1039 * Looks up a register at the exact offset given by @a offReg.
1040 *
1041 * @returns Register index on success, -1 if not found.
1042 * @param pThis The HDA device state.
1043 * @param offReg The register offset.
1044 */
1045static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1046{
1047 /*
1048 * Aliases.
1049 */
1050 if (offReg >= g_aHdaRegAliases[0].offReg)
1051 {
1052 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1053 if (offReg == g_aHdaRegAliases[i].offReg)
1054 return g_aHdaRegAliases[i].idxAlias;
1055 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1056 return -1;
1057 }
1058
1059 /*
1060 * Binary search the
1061 */
1062 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1063 int idxLow = 0;
1064 for (;;)
1065 {
1066 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1067 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1068 {
1069 if (idxLow == idxMiddle)
1070 break;
1071 idxEnd = idxMiddle;
1072 }
1073 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1074 {
1075 idxLow = idxMiddle + 1;
1076 if (idxLow >= idxEnd)
1077 break;
1078 }
1079 else
1080 return idxMiddle;
1081 }
1082
1083#ifdef RT_STRICT
1084 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1085 Assert(g_aHdaRegMap[i].offset != offReg);
1086#endif
1087 return -1;
1088}
1089
1090/**
1091 * Looks up a register covering the offset given by @a offReg.
1092 *
1093 * @returns Register index on success, -1 if not found.
1094 * @param pThis The HDA device state.
1095 * @param offReg The register offset.
1096 */
1097static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1098{
1099 /*
1100 * Aliases.
1101 */
1102 if (offReg >= g_aHdaRegAliases[0].offReg)
1103 {
1104 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1105 {
1106 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1107 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1108 return g_aHdaRegAliases[i].idxAlias;
1109 }
1110 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1111 return -1;
1112 }
1113
1114 /*
1115 * Binary search the
1116 */
1117 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1118 int idxLow = 0;
1119 for (;;)
1120 {
1121 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1122 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1123 {
1124 if (idxLow == idxMiddle)
1125 break;
1126 idxEnd = idxMiddle;
1127 }
1128 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1129 {
1130 idxLow = idxMiddle + 1;
1131 if (idxLow >= idxEnd)
1132 break;
1133 }
1134 else
1135 return idxMiddle;
1136 }
1137
1138#ifdef RT_STRICT
1139 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1140 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1141#endif
1142 return -1;
1143}
1144
1145#ifdef IN_RING3
1146static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1147{
1148 int rc = VINF_SUCCESS;
1149 if (fLocal)
1150 {
1151 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1152 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1153 if (RT_FAILURE(rc))
1154 AssertRCReturn(rc, rc);
1155#ifdef DEBUG_CMD_BUFFER
1156 uint8_t i = 0;
1157 do
1158 {
1159 LogFunc(("corb%02x: ", i));
1160 uint8_t j = 0;
1161 do
1162 {
1163 const char *prefix;
1164 if ((i + j) == HDA_REG(pThis, CORBRP);
1165 prefix = "[R]";
1166 else if ((i + j) == HDA_REG(pThis, CORBWP);
1167 prefix = "[W]";
1168 else
1169 prefix = " "; /* three spaces */
1170 LogFunc(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
1171 j++;
1172 } while (j < 8);
1173 LogFunc(("\n"));
1174 i += 8;
1175 } while(i != 0);
1176#endif
1177 }
1178 else
1179 {
1180 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1181 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1182 if (RT_FAILURE(rc))
1183 AssertRCReturn(rc, rc);
1184#ifdef DEBUG_CMD_BUFFER
1185 uint8_t i = 0;
1186 do {
1187 LogFunc(("rirb%02x: ", i));
1188 uint8_t j = 0;
1189 do {
1190 const char *prefix;
1191 if ((i + j) == HDA_REG(pThis, RIRBWP))
1192 prefix = "[W]";
1193 else
1194 prefix = " ";
1195 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1196 } while (++j < 8);
1197 LogFunc(("\n"));
1198 i += 8;
1199 } while (i != 0);
1200#endif
1201 }
1202 return rc;
1203}
1204
1205static int hdaCORBCmdProcess(PHDASTATE pThis)
1206{
1207 int rc;
1208 uint8_t corbRp;
1209 uint8_t corbWp;
1210 uint8_t rirbWp;
1211
1212 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1213
1214 rc = hdaCmdSync(pThis, true);
1215 if (RT_FAILURE(rc))
1216 AssertRCReturn(rc, rc);
1217 corbRp = HDA_REG(pThis, CORBRP);
1218 corbWp = HDA_REG(pThis, CORBWP);
1219 rirbWp = HDA_REG(pThis, RIRBWP);
1220 Assert((corbWp != corbRp));
1221 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1222 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1223 while (corbRp != corbWp)
1224 {
1225 uint32_t cmd;
1226 uint64_t resp;
1227 pfn = NULL;
1228 corbRp++;
1229 cmd = pThis->pu32CorbBuf[corbRp];
1230
1231 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1232 HDA_CODEC_CMD(cmd, 0 /* Codec index */),
1233 &pfn);
1234 if (RT_SUCCESS(rc))
1235 {
1236 rc = pfn(pThis->pCodec,
1237 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1238 }
1239
1240 if (RT_FAILURE(rc))
1241 AssertRCReturn(rc, rc);
1242 Assert(pfn);
1243 (rirbWp)++;
1244
1245 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1246 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1247 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1248 {
1249 LogFunc(("unexpected unsolicited response.\n"));
1250 HDA_REG(pThis, CORBRP) = corbRp;
1251 return rc;
1252 }
1253 pThis->pu64RirbBuf[rirbWp] = resp;
1254 pThis->u8Counter++;
1255 if (pThis->u8Counter == RINTCNT_N(pThis))
1256 break;
1257 }
1258 HDA_REG(pThis, CORBRP) = corbRp;
1259 HDA_REG(pThis, RIRBWP) = rirbWp;
1260 rc = hdaCmdSync(pThis, false);
1261 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1262 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1263 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1264 {
1265 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1266 pThis->u8Counter = 0;
1267 rc = hdaProcessInterrupt(pThis);
1268 }
1269 if (RT_FAILURE(rc))
1270 AssertRCReturn(rc, rc);
1271 return rc;
1272}
1273#endif
1274
1275static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
1276{
1277 LogFunc(("reset of stream (%d) started\n", u8Strm));
1278 Assert(( pThis
1279 && pBdle
1280 && pStreamDesc
1281 && u8Strm <= 7));
1282 RT_BZERO(pBdle, sizeof(HDABDLEDESC));
1283 *pStreamDesc->pu32Lpib = 0;
1284 *pStreamDesc->pu32Sts = 0;
1285 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1286 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
1287 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1288
1289 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1290 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1291 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
1292 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1293 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1294 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1295 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1296 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1297 LogFunc(("reset of stream (%d) finished\n", u8Strm));
1298}
1299
1300/* Register access handlers. */
1301
1302static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1303{
1304 *pu32Value = 0;
1305 return VINF_SUCCESS;
1306}
1307
1308static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1309{
1310 return VINF_SUCCESS;
1311}
1312
1313/* U8 */
1314static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1315{
1316 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1317 return hdaRegReadU32(pThis, iReg, pu32Value);
1318}
1319
1320static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1321{
1322 Assert((u32Value & 0xffffff00) == 0);
1323 return hdaRegWriteU32(pThis, iReg, u32Value);
1324}
1325
1326/* U16 */
1327static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1328{
1329 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1330 return hdaRegReadU32(pThis, iReg, pu32Value);
1331}
1332
1333static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1334{
1335 Assert((u32Value & 0xffff0000) == 0);
1336 return hdaRegWriteU32(pThis, iReg, u32Value);
1337}
1338
1339/* U24 */
1340static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1341{
1342 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1343 return hdaRegReadU32(pThis, iReg, pu32Value);
1344}
1345
1346static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1347{
1348 Assert((u32Value & 0xff000000) == 0);
1349 return hdaRegWriteU32(pThis, iReg, u32Value);
1350}
1351
1352/* U32 */
1353static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1354{
1355 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1356
1357 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1358 return VINF_SUCCESS;
1359}
1360
1361static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1362{
1363 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1364
1365 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1366 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1367 return VINF_SUCCESS;
1368}
1369
1370static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1371{
1372 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1373 {
1374 /* exit reset state */
1375 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1376 pThis->fInReset = false;
1377 }
1378 else
1379 {
1380#ifdef IN_RING3
1381 /* enter reset state*/
1382 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1383 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1384 {
1385 LogFunc(("HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1386 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1387 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1388 }
1389 hdaReset(pThis->CTX_SUFF(pDevIns));
1390 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1391 pThis->fInReset = true;
1392#else
1393 return VINF_IOM_R3_MMIO_WRITE;
1394#endif
1395 }
1396 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1397 {
1398 /* Flush: GSTS:1 set, see 6.2.6*/
1399 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1400 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1401 }
1402 return VINF_SUCCESS;
1403}
1404
1405static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1406{
1407 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1408
1409 uint32_t v = pThis->au32Regs[iRegMem];
1410 uint32_t nv = u32Value & HDA_STATES_SCSF;
1411 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1412 return VINF_SUCCESS;
1413}
1414
1415static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1416{
1417 uint32_t v = 0;
1418 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1419 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1420 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1421 || HDA_REG(pThis, STATESTS))
1422 v |= RT_BIT(30);
1423#define HDA_IS_STREAM_EVENT(pThis, stream) \
1424 ( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1425 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1426 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1427#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
1428 MARK_STREAM(pThis, 0, v);
1429 MARK_STREAM(pThis, 1, v);
1430 MARK_STREAM(pThis, 2, v);
1431 MARK_STREAM(pThis, 3, v);
1432 MARK_STREAM(pThis, 4, v);
1433 MARK_STREAM(pThis, 5, v);
1434 MARK_STREAM(pThis, 6, v);
1435 MARK_STREAM(pThis, 7, v);
1436 v |= v ? RT_BIT(31) : 0;
1437 *pu32Value = v;
1438 return VINF_SUCCESS;
1439}
1440
1441static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1442{
1443 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1444 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1445 - pThis->u64BaseTS, 24, 1000);
1446 return VINF_SUCCESS;
1447}
1448
1449static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1450{
1451 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1452 HDA_REG(pThis, CORBRP) = 0;
1453#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1454 else
1455 return hdaRegWriteU8(pThis, iReg, u32Value);
1456#endif
1457 return VINF_SUCCESS;
1458}
1459
1460static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1461{
1462#ifdef IN_RING3
1463 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1464 AssertRC(rc);
1465 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1466 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1467 return hdaCORBCmdProcess(pThis);
1468 return rc;
1469#else
1470 return VINF_IOM_R3_MMIO_WRITE;
1471#endif
1472}
1473
1474static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1475{
1476 uint32_t v = HDA_REG(pThis, CORBSTS);
1477 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1478 return VINF_SUCCESS;
1479}
1480
1481static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1482{
1483#ifdef IN_RING3
1484 int rc;
1485 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1486 if (RT_FAILURE(rc))
1487 AssertRCReturn(rc, rc);
1488 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1489 return VINF_SUCCESS;
1490 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1491 return VINF_SUCCESS;
1492 rc = hdaCORBCmdProcess(pThis);
1493 return rc;
1494#else
1495 return VINF_IOM_R3_MMIO_WRITE;
1496#endif
1497}
1498
1499static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1500{
1501 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1502 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1503 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1504 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1505
1506 if (fInReset)
1507 {
1508 /*
1509 * Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1510 * from reset
1511 */
1512 Assert((!fReset));
1513 LogFunc(("guest initiated exit of stream reset.\n"));
1514 }
1515 else if (fReset)
1516 {
1517#ifdef IN_RING3
1518 /*
1519 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1520 */
1521 uint8_t u8Strm = 0;
1522 PHDABDLEDESC pBdle = NULL;
1523 HDASTREAMTRANSFERDESC StreamDesc;
1524 Assert((!fInRun && !fRun));
1525 switch (iReg)
1526 {
1527 case HDA_REG_SD0CTL:
1528 u8Strm = 0;
1529 pBdle = &pThis->StInBdle;
1530 break;
1531#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1532# ifdef VBOX_WITH_HDA_MIC_IN
1533 case HDA_REG_SD2CTL:
1534 u8Strm = 2;
1535 pBdle = &pThis->StMicBdle;
1536 break;
1537# endif
1538#endif
1539 case HDA_REG_SD4CTL:
1540 u8Strm = 4;
1541 pBdle = &pThis->StOutBdle;
1542 break;
1543 default:
1544 LogFunc(("changing SRST bit on non-attached stream\n"));
1545 return hdaRegWriteU24(pThis, iReg, u32Value);
1546 }
1547 LogFunc(("guest initiated enter to stream reset.\n"));
1548 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1549 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
1550#else
1551 return VINF_IOM_R3_MMIO_WRITE;
1552#endif
1553 }
1554 else
1555 {
1556#ifdef IN_RING3
1557 /* we enter here to change DMA states only */
1558 if ( (fInRun && !fRun)
1559 || (fRun && !fInRun))
1560 {
1561 Assert((!fReset && !fInReset));
1562
1563# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1564 PHDADRIVER pDrv;
1565# endif
1566 switch (iReg)
1567 {
1568 case HDA_REG_SD0CTL:
1569# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1570 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1571 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1572 pDrv->LineIn.pStrmIn, fRun);
1573# else
1574 AUD_set_active_in(pThis->pCodec->SwVoiceIn, fRun);
1575# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1576 break;
1577# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1578# ifdef VBOX_WITH_HDA_MIC_IN
1579 case HDA_REG_SD2CTL:
1580 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1581 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1582 pDrv->MicIn.pStrmIn, fRun);
1583# endif
1584# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1585 break;
1586 case HDA_REG_SD4CTL:
1587# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1588 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1589 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1590 pDrv->Out.pStrmOut, fRun);
1591# else
1592 AUD_set_active_out(pThis->pCodec->SwVoiceOut, fRun);
1593# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1594 break;
1595 default:
1596 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1597 break;
1598 }
1599 }
1600#else /* !IN_RING3 */
1601 return VINF_IOM_R3_MMIO_WRITE;
1602#endif /* IN_RING3 */
1603 }
1604
1605 return hdaRegWriteU24(pThis, iReg, u32Value);
1606}
1607
1608static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1609{
1610 uint32_t v = HDA_REG_IND(pThis, iReg);
1611 v &= ~(u32Value & v);
1612 HDA_REG_IND(pThis, iReg) = v;
1613 hdaProcessInterrupt(pThis);
1614 return VINF_SUCCESS;
1615}
1616
1617static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1618{
1619 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1620 if (RT_FAILURE(rc))
1621 AssertRCReturn(rc, VINF_SUCCESS);
1622 return rc;
1623}
1624
1625static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1626{
1627 switch (u32Value)
1628 {
1629 case HDA_SDFIFOW_8B:
1630 case HDA_SDFIFOW_16B:
1631 case HDA_SDFIFOW_32B:
1632 return hdaRegWriteU16(pThis, iReg, u32Value);
1633 default:
1634 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1635 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1636 }
1637 return VINF_SUCCESS;
1638}
1639
1640/**
1641 * @note This method could be called for changing value on Output Streams
1642 * only (ICH6 datasheet 18.2.39)
1643 */
1644static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1645{
1646 switch (iReg)
1647 {
1648 /* SDInFIFOS is RO, n=0-3 */
1649 case HDA_REG_SD0FIFOS:
1650 case HDA_REG_SD1FIFOS:
1651 case HDA_REG_SD2FIFOS:
1652 case HDA_REG_SD3FIFOS:
1653 LogFunc(("Guest tries change value of FIFO size of input stream\n"));
1654 break;
1655 case HDA_REG_SD4FIFOS:
1656 case HDA_REG_SD5FIFOS:
1657 case HDA_REG_SD6FIFOS:
1658 case HDA_REG_SD7FIFOS:
1659 switch(u32Value)
1660 {
1661 case HDA_SDONFIFO_16B:
1662 case HDA_SDONFIFO_32B:
1663 case HDA_SDONFIFO_64B:
1664 case HDA_SDONFIFO_128B:
1665 case HDA_SDONFIFO_192B:
1666 return hdaRegWriteU16(pThis, iReg, u32Value);
1667
1668 case HDA_SDONFIFO_256B:
1669 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1670 default:
1671 return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);
1672 }
1673 break;
1674 default:
1675 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
1676 }
1677
1678 return VINF_SUCCESS;
1679}
1680
1681#ifdef IN_RING3
1682#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1683static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
1684#else
1685static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pCfg)
1686#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1687{
1688 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1689
1690# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1691
1692 int rc = VINF_SUCCESS;
1693
1694 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1695 uint32_t u32HzMult = 1;
1696 uint32_t u32HzDiv = 1;
1697
1698 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
1699 {
1700 case 0: u32HzMult = 1; break;
1701 case 1: u32HzMult = 2; break;
1702 case 2: u32HzMult = 3; break;
1703 case 3: u32HzMult = 4; break;
1704 default:
1705 LogFunc(("Unsupported multiplier %x\n",
1706 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
1707 rc = VERR_NOT_SUPPORTED;
1708 break;
1709 }
1710 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
1711 {
1712 case 0: u32HzDiv = 1; break;
1713 case 1: u32HzDiv = 2; break;
1714 case 2: u32HzDiv = 3; break;
1715 case 3: u32HzDiv = 4; break;
1716 case 4: u32HzDiv = 5; break;
1717 case 5: u32HzDiv = 6; break;
1718 case 6: u32HzDiv = 7; break;
1719 case 7: u32HzDiv = 8; break;
1720 default:
1721 LogFunc(("Unsupported divisor %x\n",
1722 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
1723 rc = VERR_NOT_SUPPORTED;
1724 break;
1725 }
1726
1727#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1728 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1729#else
1730 audfmt_e enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1731#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1732
1733 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
1734 {
1735 case 0:
1736 LogFunc(("%s requested 8-bit\n", __FUNCTION__));
1737#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1738 enmFmt = AUD_FMT_S8;
1739#else
1740 enmFmt = AUD_FMT_S8;
1741#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1742 break;
1743 case 1:
1744 LogFunc(("%s requested 16-bit\n", __FUNCTION__));
1745#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1746 enmFmt = AUD_FMT_S16;
1747#else
1748 enmFmt = AUD_FMT_S16;
1749#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1750 break;
1751 case 2:
1752 LogFunc(("%s requested 20-bit\n", __FUNCTION__));
1753 break;
1754 case 3:
1755 LogFunc(("%s requested 24-bit\n", __FUNCTION__));
1756 break;
1757 case 4:
1758 LogFunc(("%s requested 32-bit\n", __FUNCTION__));
1759#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1760 enmFmt = AUD_FMT_S32;
1761#else
1762 enmFmt = AUD_FMT_S32;
1763#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1764 break;
1765 default:
1766 AssertMsgFailed(("Unsupported bits shift %x\n",
1767 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
1768 rc = VERR_NOT_SUPPORTED;
1769 break;
1770 }
1771
1772 if (RT_SUCCESS(rc))
1773 {
1774#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1775 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
1776 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
1777 pCfg->enmFormat = enmFmt;
1778 pCfg->enmEndianness = PDMAUDIOHOSTENDIANESS;
1779#else
1780 pCfg->nchannels = (u32SdFmt & 0xf) + 1;
1781 pCfg->fmt = enmFmt;
1782 pCfg->endianness = 0;
1783#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1784 }
1785
1786# undef EXTRACT_VALUE
1787
1788 return rc;
1789}
1790#endif
1791
1792static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1793{
1794#ifdef IN_RING3
1795# ifdef VBOX_WITH_HDA_CODEC_EMU
1796 /* No reason to reopen voice with same settings. */
1797 if (u32Value == HDA_REG_IND(pThis, iReg))
1798 return VINF_SUCCESS;
1799
1800 PDMAUDIOSTREAMCFG as;
1801 int rc = hdaSdFmtToAudSettings(u32Value, &as);
1802 if (RT_FAILURE(rc))
1803 return rc;
1804
1805 PHDADRIVER pDrv;
1806 switch (iReg)
1807 {
1808 case HDA_REG_SD0FMT:
1809 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1810 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &as);
1811 break;
1812#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1813# ifdef VBOX_WITH_HDA_MIC_IN
1814 case HDA_REG_SD2FMT:
1815 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1816 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &as);
1817 break;
1818# endif
1819#endif
1820 default:
1821 LogFunc(("Warning: Attempt to change format on register %d\n", iReg));
1822 break;
1823 }
1824
1825 /** @todo r=andy rc gets lost; needs fixing. */
1826 return hdaRegWriteU16(pThis, iReg, u32Value);
1827# else
1828 return hdaRegWriteU16(pThis, iReg, u32Value);
1829# endif
1830#else
1831 return VINF_IOM_R3_MMIO_WRITE;
1832#endif
1833}
1834
1835static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1836{
1837 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1838 if (RT_FAILURE(rc))
1839 AssertRCReturn(rc, VINF_SUCCESS);
1840 return rc;
1841}
1842
1843static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1844{
1845 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1846 if (RT_FAILURE(rc))
1847 AssertRCReturn(rc, VINF_SUCCESS);
1848 return rc;
1849}
1850
1851static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1852{
1853 int rc = VINF_SUCCESS;
1854 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1855 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1856 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1857 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1858
1859 rc = hdaRegReadU32(pThis, iReg, pu32Value);
1860 return rc;
1861}
1862
1863static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1864{
1865 int rc = VINF_SUCCESS;
1866
1867 /*
1868 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1869 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1870 */
1871 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1872 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
1873 {
1874#ifdef IN_RING3
1875 PFNHDACODECVERBPROCESSOR pfn = NULL;
1876 uint64_t resp;
1877 uint32_t cmd = HDA_REG(pThis, IC);
1878 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
1879 {
1880 /*
1881 * 3.4.3 defines behavior of immediate Command status register.
1882 */
1883 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
1884 return rc;
1885 }
1886 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1887 LogFunc(("IC:%x\n", cmd));
1888
1889 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1890 HDA_CODEC_CMD(cmd, 0 /* LUN */),
1891 &pfn);
1892 if (RT_FAILURE(rc))
1893 AssertRCReturn(rc, rc);
1894 rc = pfn(pThis->pCodec,
1895 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1896 if (RT_FAILURE(rc))
1897 AssertRCReturn(rc, rc);
1898
1899 HDA_REG(pThis, IR) = (uint32_t)resp;
1900 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
1901 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1902 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1903#else /* !IN_RING3 */
1904 rc = VINF_IOM_R3_MMIO_WRITE;
1905#endif
1906 return rc;
1907 }
1908 /*
1909 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1910 */
1911 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1912 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
1913 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1914 return rc;
1915}
1916
1917static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1918{
1919 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1920 {
1921 HDA_REG(pThis, RIRBWP) = 0;
1922 }
1923 /* The remaining bits are O, see 6.2.22 */
1924 return VINF_SUCCESS;
1925}
1926
1927static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1928{
1929 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1930 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1931 if (RT_FAILURE(rc))
1932 AssertRCReturn(rc, rc);
1933
1934 switch(iReg)
1935 {
1936 case HDA_REG_CORBLBASE:
1937 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
1938 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
1939 break;
1940 case HDA_REG_CORBUBASE:
1941 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
1942 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1943 break;
1944 case HDA_REG_RIRBLBASE:
1945 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
1946 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
1947 break;
1948 case HDA_REG_RIRBUBASE:
1949 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
1950 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1951 break;
1952 case HDA_REG_DPLBASE:
1953 /** @todo: first bit has special meaning */
1954 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
1955 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
1956 break;
1957 case HDA_REG_DPUBASE:
1958 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
1959 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1960 break;
1961 default:
1962 AssertMsgFailed(("Invalid index"));
1963 break;
1964 }
1965
1966 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
1967 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
1968 return rc;
1969}
1970
1971static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1972{
1973 uint8_t v = HDA_REG(pThis, RIRBSTS);
1974 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
1975
1976 return hdaProcessInterrupt(pThis);
1977}
1978
1979#ifdef IN_RING3
1980#ifdef LOG_ENABLED
1981static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1982{
1983#if 0
1984 uint64_t addr;
1985 uint32_t len;
1986 uint32_t ioc;
1987 uint8_t bdle[16];
1988 uint32_t counter;
1989 uint32_t i;
1990 uint32_t sum = 0;
1991 Assert(pBdle && pBdle->u32BdleMaxCvi);
1992 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1993 {
1994 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i*16, bdle, 16);
1995 addr = *(uint64_t *)bdle;
1996 len = *(uint32_t *)&bdle[8];
1997 ioc = *(uint32_t *)&bdle[12];
1998 LogFunc(("%s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1999 sum += len;
2000 }
2001 LogFunc(("sum: %d\n", sum));
2002 for (i = 0; i < 8; ++i)
2003 {
2004 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
2005 LogFunc(("%s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
2006 i , counter));
2007 }
2008#endif
2009}
2010#endif
2011
2012static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2013{
2014 uint8_t bdle[16];
2015 Assert(( pStreamDesc->u64BaseDMA
2016 && pBdle
2017 && pBdle->u32BdleMaxCvi));
2018 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
2019 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
2020 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
2021 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
2022#ifdef LOG_ENABLED
2023 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2024#endif
2025}
2026
2027DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2028 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
2029{
2030 /*
2031 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
2032 */
2033 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
2034 uint32_t cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
2035 /*
2036 * we may increase the counter in range of [0, FIFOS + 1]
2037 */
2038 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
2039 Assert((u32SoundBackendBufferBytesAvail > 0));
2040
2041 /* sanity check to avoid overriding the backend audio buffer */
2042 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
2043 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
2044
2045 if (cb2Copy <= pBdle->cbUnderFifoW)
2046 return 0;
2047 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
2048 return cb2Copy;
2049}
2050
2051DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2052 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2053{
2054 LogFunc(("cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2055 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2056 Assert((cbCopied));
2057 AssertPtr(pu32DMACursor);
2058 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
2059 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
2060 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2061 * where it might happen.
2062 */
2063 AssertMsg((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy), /* we assume that we write the entire buffer including unreported bytes */
2064 ("cbCopied=%RU32 != pBdle->cbUnderFifoW=%RU32 + cbArranged2Copy=%RU32\n",
2065 cbCopied, pBdle->cbUnderFifoW, cbArranged2Copy));
2066 if ( pBdle->cbUnderFifoW
2067 && pBdle->cbUnderFifoW <= cbCopied)
2068 {
2069 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n",
2070 pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2071 }
2072
2073 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
2074 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
2075
2076 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
2077 pBdle->u32BdleCviPos += cbArranged2Copy;
2078
2079 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
2080 /* We report all bytes (including previously unreported bytes) */
2081 *pu32DMACursor += cbCopied;
2082 /* Decrease the backend counter by the number of bytes we copied to the backend */
2083 *pu32BackendBufferCapacity -= cbCopied;
2084 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2085 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
2086}
2087
2088DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2089 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2090{
2091 Assert((cbCopied, cbArranged2Copy));
2092 *pu32BackendBufferCapacity -= cbCopied;
2093 pBdle->u32BdleCviPos += cbCopied;
2094 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2095 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
2096 pBdle->cbUnderFifoW = 0;
2097 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2098 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2099}
2100
2101DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2102 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
2103{
2104 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2105 pBdle->u32BdleCviPos += cbCopied;
2106 pBdle->cbUnderFifoW += cbCopied;
2107 /* In case of a read transaction we're always copying from the backend buffer */
2108 if (pu32BackendBufferCapacity)
2109 *pu32BackendBufferCapacity -= cbCopied;
2110 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2111 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
2112}
2113
2114DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2115{
2116 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
2117 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
2118
2119 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2120
2121 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2122 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
2123 hdaUpdatePosBuf(pThis, pStreamDesc);
2124
2125 /* don't touch BdleCvi counter on uninitialized descriptor */
2126 if ( pBdle->u32BdleCviPos
2127 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
2128 {
2129 pBdle->u32BdleCviPos = 0;
2130 pBdle->u32BdleCvi++;
2131 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
2132 pBdle->u32BdleCvi = 0;
2133 }
2134 return fOnBufferEdge;
2135}
2136
2137DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2138 uint32_t cbInc)
2139{
2140 /*
2141 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
2142 * (ICH6 datasheet 18.2.38)
2143 */
2144 if (!pBdle->cbUnderFifoW)
2145 {
2146 *pStreamDesc->pu32Lpib += cbInc;
2147
2148 /*
2149 * Assert. The buffer counters should never overlap.
2150 */
2151 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2152
2153 hdaUpdatePosBuf(pThis, pStreamDesc);
2154 }
2155}
2156
2157static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2158{
2159 bool fDoNextTransferLoop = true;
2160 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
2161 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2162 {
2163 if ( !pBdle->cbUnderFifoW
2164 && pBdle->fBdleCviIoc)
2165 {
2166 /**
2167 * @todo - more carefully investigate BCIS flag.
2168 * Speech synthesis works fine on Mac Guest if this bit isn't set
2169 * but in general sound quality gets worse.
2170 */
2171 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2172
2173 /*
2174 * we should generate the interrupt if ICE bit of SDCTL register is set.
2175 */
2176 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2177 hdaProcessInterrupt(pThis);
2178 }
2179 fDoNextTransferLoop = false;
2180 }
2181 return fDoNextTransferLoop;
2182}
2183
2184#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2185/**
2186 * hdaReadAudio - copies samples from audio backend to DMA.
2187 * Note: This function writes to the DMA buffer immediately,
2188 * but "reports bytes" when all conditions are met (FIFOW).
2189 */
2190static int hdaReadAudio(PHDASTATE pThis, PAUDMIXSINK pSink,
2191 PHDASTREAMTRANSFERDESC pStreamDesc,
2192 uint32_t u32CblLimit, uint32_t *pcbAvail, uint32_t *pcbRead)
2193{
2194 PHDABDLEDESC pBdle = &pThis->StInBdle; /** @todo Add support for mic in. */
2195
2196 int rc;
2197 uint32_t cbTransferred = 0;
2198
2199 LogFlowFunc(("CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2200
2201 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2202 if (!cb2Copy)
2203 {
2204 /* If we enter here we can't report "unreported bits". */
2205 rc = VERR_NO_DATA;
2206 }
2207 else
2208 {
2209 uint32_t cbRead = 0;
2210 rc = audioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pBdle->au8HdaBuffer, cb2Copy, &cbRead);
2211 if (RT_SUCCESS(rc))
2212 {
2213 Assert(cbRead);
2214
2215 /*
2216 * Write the HDA DMA buffer.
2217 */
2218 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2219 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2220 pBdle->au8HdaBuffer, cbRead);
2221
2222 /* Don't see any reason why cb2Copy would differ from cbRead. */
2223 Assert((cbRead == cb2Copy && (*pcbAvail) >= cb2Copy)); /* sanity */
2224
2225 if (pBdle->cbUnderFifoW + cbRead > hdaFifoWToSz(pThis, 0))
2226 hdaBackendReadTransferReported(pBdle, cb2Copy, cbRead, &cbTransferred, pcbAvail);
2227 else
2228 {
2229 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbRead, pcbAvail);
2230 rc = VERR_NO_DATA;
2231 }
2232 }
2233 }
2234
2235 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2236 LogFunc(("CVI(pos:%RU32, len:%RU32), cbTransferred=%RU32, rc=%Rrc\n",
2237 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2238
2239 if (RT_SUCCESS(rc))
2240 *pcbRead = cbTransferred;
2241
2242 return rc;
2243}
2244#else
2245static int hdaReadAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc,
2246 uint32_t u32CblLimit, uint32_t *pu32Avail, uint32_t *pcbRead)
2247{
2248 PHDABDLEDESC pBdle = &pThis->StInBdle;
2249
2250 uint32_t cbTransferred = 0;
2251 uint32_t cb2Copy = 0;
2252 uint32_t cbBackendCopy = 0;
2253
2254 int rc;
2255
2256 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2257
2258 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
2259 if (!cb2Copy)
2260 {
2261 /* if we enter here we can't report "unreported bits" */
2262 rc = VINF_EOF;
2263 }
2264 else
2265 {
2266 /*
2267 * read from backend input line to the last unreported position or at the begining.
2268 */
2269 cbBackendCopy = AUD_read(pThis->pCodec->SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
2270
2271 /*
2272 * write the HDA DMA buffer
2273 */
2274 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer,
2275 cbBackendCopy);
2276
2277 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
2278 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
2279
2280 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pThis, 0))
2281 {
2282 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
2283 rc = VINF_SUCCESS;
2284 }
2285 else
2286 {
2287 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
2288 rc = VINF_EOF;
2289 }
2290 }
2291
2292 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2293 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
2294
2295 if (pcbRead)
2296 *pcbRead = cbTransferred;
2297
2298 return rc;
2299}
2300#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2301
2302static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32CblLimit,
2303 uint32_t *pcbAvail, uint32_t *pcbWritten)
2304{
2305 PHDABDLEDESC pBdle = &pThis->StOutBdle;
2306
2307 int rc = VINF_SUCCESS;
2308
2309 uint32_t cbTransferred = 0;
2310 uint32_t cbWrittenMin = 0; /* local byte counter, how many bytes copied to backend */
2311
2312 LogFunc(("CVI(cvi:%RU32, pos:%RU32, len:%RU32)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2313
2314 /* Local byte counter (on local buffer). */
2315 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2316
2317 /*
2318 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
2319 * previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
2320 */
2321 if (!cb2Copy)
2322 {
2323 rc = VINF_EOF;
2324 }
2325 else
2326 {
2327 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2328 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2329 pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
2330#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2331 STAM_COUNTER_ADD(&pThis->StatBytesRead, cb2Copy);
2332#endif
2333
2334 /*
2335 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2336 */
2337 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
2338 {
2339#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2340 uint32_t cbWritten;
2341 cbWrittenMin = UINT32_MAX;
2342
2343 PHDADRIVER pDrv;
2344 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2345 {
2346 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2347 {
2348 int rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2349 pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW,
2350 &cbWritten);
2351 if (RT_FAILURE(rc2))
2352 continue;
2353 }
2354 else /* Stream disabled, just assume all was copied. */
2355 cbWritten = cb2Copy;
2356
2357 cbWrittenMin = RT_MIN(cbWrittenMin, cbWritten);
2358 LogFlowFunc(("\tLUN#%RU8: cbWritten=%RU32, cWrittenMin=%RU32\n", pDrv->uLUN, cbWritten, cbWrittenMin));
2359 }
2360
2361 if (cbWrittenMin == UINT32_MAX)
2362 cbWrittenMin = 0;
2363#else
2364 cbWrittenMin = AUD_write (pThis->pCodec->SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
2365#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2366
2367 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbWrittenMin, &cbTransferred, pcbAvail);
2368 }
2369 else
2370 {
2371 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2372 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
2373 rc = VINF_EOF;
2374 }
2375 }
2376
2377 Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
2378 LogFunc(("CVI(pos:%RU32, len:%RU32, cbTransferred:%RU32), rc=%Rrc\n",
2379 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2380
2381 if (RT_SUCCESS(rc))
2382 *pcbWritten = cbTransferred;
2383
2384 return rc;
2385}
2386
2387/**
2388 * @interface_method_impl{HDACODEC,pfnReset}
2389 */
2390DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2391{
2392 PHDASTATE pThis = pCodec->pHDAState;
2393 NOREF(pThis);
2394 return VINF_SUCCESS;
2395}
2396
2397DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
2398 PHDASTREAMTRANSFERDESC pStreamDesc)
2399{
2400 Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
2401
2402 RT_BZERO(pStreamDesc, sizeof(HDASTREAMTRANSFERDESC));
2403 pStreamDesc->u8Strm = u8Strm;
2404 pStreamDesc->u32Ctl = HDA_STREAM_REG(pThis, CTL, u8Strm);
2405 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2406 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2407 pStreamDesc->pu32Lpib = &HDA_STREAM_REG(pThis, LPIB, u8Strm);
2408 pStreamDesc->pu32Sts = &HDA_STREAM_REG(pThis, STS, u8Strm);
2409 pStreamDesc->u32Cbl = HDA_STREAM_REG(pThis, CBL, u8Strm);
2410 pStreamDesc->u32Fifos = HDA_STREAM_REG(pThis, FIFOS, u8Strm);
2411
2412 pBdle->u32BdleMaxCvi = HDA_STREAM_REG(pThis, LVI, u8Strm);
2413
2414#ifdef LOG_ENABLED
2415 if ( pBdle
2416 && pBdle->u32BdleMaxCvi)
2417 {
2418 LogFunc(("Initialization of transfer descriptor:\n"));
2419 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2420 }
2421#endif
2422}
2423
2424static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2425{
2426 NOREF(pThis);
2427 NOREF(enmRecSource);
2428 LogFlowFuncEnter();
2429}
2430
2431static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2432{
2433 NOREF(pThis);
2434 LogFlowFuncEnter();
2435}
2436
2437#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2438static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2439 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2440 PPDMAUDIOSTREAMCFG pCfg)
2441{
2442 PAUDMIXSINK pSink;
2443
2444 switch (enmRecSource)
2445 {
2446# ifdef VBOX_WITH_HDA_MIC_IN
2447 case PDMAUDIORECSOURCE_MIC:
2448 pSink = pThis->pSinkMicIn;
2449 break;
2450# endif
2451 case PDMAUDIORECSOURCE_LINE_IN:
2452 pSink = pThis->pSinkLineIn;
2453 break;
2454 default:
2455 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2456 return VERR_NOT_SUPPORTED;
2457 }
2458
2459 int rc;
2460 char *pszDesc;
2461
2462 PHDADRIVER pDrv;
2463 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2464 {
2465 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2466 {
2467 rc = VERR_NO_MEMORY;
2468 break;
2469 }
2470
2471 rc = pDrv->pConnector->pfnOpenIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2472 LogFlowFunc(("LUN#%RU8: Opened input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2473 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2474 {
2475 audioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2476 rc = audioMixerAddStreamIn(pSink,
2477 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2478 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2479 }
2480
2481 RTStrFree(pszDesc);
2482 }
2483
2484 LogFlowFuncLeaveRC(rc);
2485 return rc;
2486}
2487
2488static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2489 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2490{
2491 int rc = VINF_SUCCESS;
2492
2493 PHDADRIVER pDrv;
2494 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2495 {
2496 int rc2 = pDrv->pConnector->pfnOpenOut(pDrv->pConnector, pszName, pCfg, &pDrv->Out.pStrmOut);
2497 if (RT_FAILURE(rc2))
2498 {
2499 LogFunc(("LUN#%RU8: Opening stream \"%s\" failed, rc=%Rrc\n", pDrv->uLUN, pszName, rc2));
2500 if (RT_SUCCESS(rc))
2501 rc = rc2;
2502 /* Keep going. */
2503 }
2504 }
2505
2506 LogFlowFuncLeaveRC(rc);
2507 return rc;
2508}
2509
2510static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis,
2511 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2512{
2513 int rc = VINF_SUCCESS;
2514
2515 PDMAUDIOVOLUME vol = { fMute, uVolLeft, uVolRight };
2516 audioMixerSetMasterVolume(pThis->pMixer, &vol);
2517
2518 LogFlowFuncLeaveRC(rc);
2519 return rc;
2520}
2521#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2522
2523#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2524static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2525{
2526 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2527 AssertPtr(pThis);
2528
2529 STAM_PROFILE_START(&pThis->StatTimer, a);
2530
2531 int rc = VINF_SUCCESS;
2532
2533 uint32_t cbInMax = 0;
2534 uint32_t cbOutMin = UINT32_MAX;
2535
2536 PHDADRIVER pDrv;
2537
2538 LogFlowFuncEnter();
2539
2540 uint32_t cbIn, cbOut, cSamplesLive;
2541 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2542 {
2543 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2544 &cbIn, &cbOut, &cSamplesLive);
2545 if (RT_SUCCESS(rc))
2546 {
2547 LogFlowFunc(("\tLUN#%RU8: [1] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2548
2549 if (cSamplesLive)
2550 {
2551 uint32_t cSamplesPlayed;
2552 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2553 if (RT_SUCCESS(rc2))
2554 LogFlowFunc(("LUN#%RU8: cSamplesLive=%RU32, cSamplesPlayed=%RU32\n",
2555 pDrv->uLUN, cSamplesLive, cSamplesPlayed));
2556
2557 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2558 &cbIn, &cbOut, &cSamplesLive);
2559 if (RT_SUCCESS(rc))
2560 LogFlowFunc(("\tLUN#%RU8: [2] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2561 }
2562
2563 cbInMax = RT_MAX(cbInMax, cbIn);
2564 cbOutMin = RT_MIN(cbOutMin, cbOut);
2565 }
2566 }
2567
2568 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
2569
2570 if (cbOutMin == UINT32_MAX)
2571 cbOutMin = 0;
2572
2573 /*
2574 * Playback.
2575 */
2576 if (cbOutMin)
2577 {
2578 Assert(cbOutMin != UINT32_MAX);
2579 hdaTransfer(pThis, PO_INDEX, cbOutMin); /** @todo Add rc! */
2580 }
2581
2582 /*
2583 * Recording.
2584 */
2585 if (cbInMax)
2586 hdaTransfer(pThis, PI_INDEX, cbInMax); /** @todo Add rc! */
2587
2588 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
2589
2590 LogFlowFuncLeave();
2591
2592 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2593}
2594
2595static DECLCALLBACK(int) hdaTransfer(PHDASTATE pThis,
2596 ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2597{
2598 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2599
2600 LogFlowFunc(("pThis=%p, cbAvail=%RU32\n", pThis, cbAvail));
2601#else
2602static DECLCALLBACK(int) hdaTransfer(PHDACODEC pCodec, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2603{
2604 AssertPtrReturn(pCodec, VERR_INVALID_POINTER);
2605 PHDASTATE pThis = pCodec->pHDAState;
2606 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2607#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2608 int rc;
2609
2610 uint8_t u8Strm;
2611 PHDABDLEDESC pBdle;
2612
2613 switch (enmSrc)
2614 {
2615 case PI_INDEX:
2616 {
2617 u8Strm = 0;
2618 pBdle = &pThis->StInBdle;
2619 break;
2620 }
2621
2622#ifdef VBOX_WITH_HDA_MIC_IN
2623 case MC_INDEX:
2624 {
2625 u8Strm = 2;
2626 pBdle = &pThis->StMicBdle;
2627 break;
2628 }
2629#endif
2630 case PO_INDEX:
2631 {
2632 u8Strm = 4;
2633 pBdle = &pThis->StOutBdle;
2634 break;
2635 }
2636
2637 default:
2638 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
2639 return VERR_NOT_SUPPORTED;
2640 }
2641
2642 HDASTREAMTRANSFERDESC StreamDesc;
2643 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2644
2645 while (cbAvail)
2646 {
2647 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
2648 && cbAvail
2649 && StreamDesc.u64BaseDMA);
2650
2651 /* Fetch the Buffer Descriptor Entry (BDE). */
2652 if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
2653 hdaFetchBdle(pThis, pBdle, &StreamDesc);
2654
2655 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2656 Assert((StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib))); /* sanity */
2657 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
2658 Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
2659
2660 LogFunc(("CBL=%RU32, LPIB=%RU32\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
2661
2662#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2663 PAUDMIXSINK pSink;
2664#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2665 uint32_t cbWritten = 0;
2666 switch (enmSrc)
2667 {
2668 case PI_INDEX:
2669#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2670 pSink = pThis->pSinkLineIn;
2671 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2672#else
2673 rc = hdaReadAudio(pThis, &StreamDesc, u32CblLimit, (uint32_t *)&cbAvail, &cbWritten);
2674#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2675 break;
2676 case PO_INDEX:
2677 rc = hdaWriteAudio(pThis, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2678 break;
2679#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2680# ifdef VBOX_WITH_HDA_MIC_IN
2681 case MC_INDEX:
2682 pSink = pThis->pSinkMicIn;
2683 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2684 break;
2685# endif
2686#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2687 default:
2688 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
2689 rc = VERR_NOT_SUPPORTED;
2690 break;
2691 }
2692 Assert(cbWritten <= StreamDesc.u32Fifos + 1);
2693 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2694
2695 /* Process end of buffer condition. */
2696 hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cbWritten);
2697
2698 if (!hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc))
2699 break;
2700
2701 if ( RT_FAILURE(rc)
2702 || rc == VINF_EOF) /* All data processed? */
2703 {
2704 break;
2705 }
2706 }
2707
2708 return rc;
2709}
2710#endif /* IN_RING3 */
2711
2712/* MMIO callbacks */
2713
2714/**
2715 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
2716 *
2717 * @note During implementation, we discovered so-called "forgotten" or "hole"
2718 * registers whose description is not listed in the RPM, datasheet, or
2719 * spec.
2720 */
2721PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2722{
2723 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2724 int rc;
2725
2726 /*
2727 * Look up and log.
2728 */
2729 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2730 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
2731#ifdef LOG_ENABLED
2732 unsigned const cbLog = cb;
2733 uint32_t offRegLog = offReg;
2734#endif
2735
2736 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
2737#define NEW_READ_CODE
2738#ifdef NEW_READ_CODE
2739 Assert(cb == 4); Assert((offReg & 3) == 0);
2740
2741 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2742 LogFunc(("access to registers except GCTL is blocked while reset\n"));
2743
2744 if (idxRegDsc == -1)
2745 LogRel(("Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
2746
2747 if (idxRegDsc != -1)
2748 {
2749 /* ASSUMES gapless DWORD at end of map. */
2750 if (g_aHdaRegMap[idxRegDsc].size == 4)
2751 {
2752 /*
2753 * Straight forward DWORD access.
2754 */
2755 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
2756 LogFunc(("read %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
2757 }
2758 else
2759 {
2760 /*
2761 * Multi register read (unless there are trailing gaps).
2762 * ASSUMES that only DWORD reads have sideeffects.
2763 */
2764 uint32_t u32Value = 0;
2765 unsigned cbLeft = 4;
2766 do
2767 {
2768 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
2769 uint32_t u32Tmp = 0;
2770
2771 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
2772 LogFunc(("read %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
2773 if (rc != VINF_SUCCESS)
2774 break;
2775 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
2776
2777 cbLeft -= cbReg;
2778 offReg += cbReg;
2779 idxRegDsc++;
2780 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
2781
2782 if (rc == VINF_SUCCESS)
2783 *(uint32_t *)pv = u32Value;
2784 else
2785 Assert(!IOM_SUCCESS(rc));
2786 }
2787 }
2788 else
2789 {
2790 rc = VINF_IOM_MMIO_UNUSED_FF;
2791 LogFunc(("hole at %x is accessed for read\n", offReg));
2792 }
2793#else
2794 if (idxRegDsc != -1)
2795 {
2796 /** @todo r=bird: Accesses crossing register boundraries aren't handled
2797 * right from what I can tell? If they are, please explain
2798 * what the rules are. */
2799 uint32_t mask = 0;
2800 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2801 uint32_t u32Value = 0;
2802 switch(cb)
2803 {
2804 case 1: mask = 0x000000ff; break;
2805 case 2: mask = 0x0000ffff; break;
2806 case 4:
2807 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2808 case 8:
2809 mask = 0xffffffff;
2810 cb = 4;
2811 break;
2812 }
2813#if 0
2814 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
2815 */
2816 //Assert((cb <= g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset)));
2817 if (cb > g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset))
2818 {
2819 int off = cb - (g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset));
2820 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2821 if (RT_FAILURE(rc))
2822 AssertRCReturn (rc, rc);
2823 }
2824 //Assert(((offReg - g_aHdaRegMap[idxRegDsc].offset) == 0));
2825#endif
2826 mask <<= shift;
2827 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Value);
2828 *(uint32_t *)pv |= (u32Value & mask);
2829 LogFunc(("read %s[%x/%x]\n", g_aHdaRegMap[idxRegDsc].abbrev, u32Value, *(uint32_t *)pv));
2830 }
2831 else
2832 {
2833 *(uint32_t *)pv = 0xFF;
2834 LogFunc(("hole at %x is accessed for read\n", offReg));
2835 rc = VINF_SUCCESS;
2836 }
2837#endif
2838
2839 /*
2840 * Log the outcome.
2841 */
2842#ifdef LOG_ENABLED
2843 if (cbLog == 4)
2844 LogFunc(("@%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
2845 else if (cbLog == 2)
2846 LogFunc(("@%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
2847 else if (cbLog == 1)
2848 LogFunc(("@%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
2849#endif
2850 return rc;
2851}
2852
2853
2854DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
2855{
2856 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2857 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
2858
2859 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2860#ifdef LOG_ENABLED
2861 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
2862#endif
2863 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
2864 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
2865 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
2866 return rc;
2867}
2868
2869
2870/**
2871 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
2872 */
2873PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2874{
2875 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2876 int rc;
2877
2878 /*
2879 * The behavior of accesses that aren't aligned on natural boundraries is
2880 * undefined. Just reject them outright.
2881 */
2882 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
2883 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
2884 if (GCPhysAddr & (cb - 1))
2885 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
2886
2887 /*
2888 * Look up and log the access.
2889 */
2890 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2891 int idxRegDsc = hdaRegLookup(pThis, offReg);
2892 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
2893 uint64_t u64Value;
2894 if (cb == 4) u64Value = *(uint32_t const *)pv;
2895 else if (cb == 2) u64Value = *(uint16_t const *)pv;
2896 else if (cb == 1) u64Value = *(uint8_t const *)pv;
2897 else if (cb == 8) u64Value = *(uint64_t const *)pv;
2898 else
2899 {
2900 u64Value = 0; /* shut up gcc. */
2901 AssertReleaseMsgFailed(("%d\n", cb));
2902 }
2903
2904#ifdef LOG_ENABLED
2905 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
2906 uint32_t const offRegLog = offReg;
2907 int const idxRegLog = idxRegMem;
2908 if (idxRegDsc == -1)
2909 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
2910 else if (cb == 4)
2911 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2912 else if (cb == 2)
2913 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2914 else if (cb == 1)
2915 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2916 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
2917 LogFunc(("size=%d != cb=%d!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
2918#endif
2919
2920#define NEW_WRITE_CODE
2921#ifdef NEW_WRITE_CODE
2922 /*
2923 * Try for a direct hit first.
2924 */
2925 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
2926 {
2927 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
2928 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2929 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2930 }
2931 /*
2932 * Partial or multiple register access, loop thru the requested memory.
2933 */
2934 else
2935 {
2936 /* If it's an access beyond the start of the register, shift the input
2937 value and fill in missing bits. Natural alignment rules means we
2938 will only see 1 or 2 byte accesses of this kind, so no risk of
2939 shifting out input values. */
2940 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
2941 {
2942 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
2943 offReg -= cbBefore;
2944 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2945 u64Value <<= cbBefore * 8;
2946 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
2947 LogFunc(("Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
2948 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
2949 }
2950
2951 /* Loop thru the write area, it may cover multiple registers. */
2952 rc = VINF_SUCCESS;
2953 for (;;)
2954 {
2955 uint32_t cbReg;
2956 if (idxRegDsc != -1)
2957 {
2958 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2959 cbReg = g_aHdaRegMap[idxRegDsc].size;
2960 if (cb < cbReg)
2961 {
2962 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
2963 LogFunc(("Supplying missing bits (%#x): %#llx -> %#llx ...\n",
2964 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
2965 }
2966 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
2967 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
2968 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldVal,
2969 pThis->au32Regs[idxRegMem]));
2970 }
2971 else
2972 {
2973 LogRel(("HDA: Invalid write access @0x%x!\n", offReg));
2974 cbReg = 1;
2975 }
2976 if (rc != VINF_SUCCESS)
2977 break;
2978 if (cbReg >= cb)
2979 break;
2980
2981 /* advance */
2982 offReg += cbReg;
2983 cb -= cbReg;
2984 u64Value >>= cbReg * 8;
2985 if (idxRegDsc == -1)
2986 idxRegDsc = hdaRegLookup(pThis, offReg);
2987 else
2988 {
2989 idxRegDsc++;
2990 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
2991 || g_aHdaRegMap[idxRegDsc].offset != offReg)
2992 idxRegDsc = -1;
2993 }
2994 }
2995 }
2996#else
2997 if (idxRegDsc != -1)
2998 {
2999 /** @todo r=bird: This looks like code for handling unaligned register
3000 * accesses. If it isn't, then add a comment explaining what you're
3001 * trying to do here. OTOH, if it is then it has the following
3002 * issues:
3003 * -# You're calculating the wrong new value for the register.
3004 * -# You're not handling cross register accesses. Imagine a
3005 * 4-byte write starting at CORBCTL, or a 8-byte write.
3006 *
3007 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
3008 * nobody seems to be using it and it just adds complexity when reading
3009 * the code.
3010 *
3011 */
3012 uint32_t u32CurValue = pThis->au32Regs[idxRegMem];
3013 uint32_t u32NewValue;
3014 uint32_t mask;
3015 switch (cb)
3016 {
3017 case 1:
3018 u32NewValue = *(uint8_t const *)pv;
3019 mask = 0xff;
3020 break;
3021 case 2:
3022 u32NewValue = *(uint16_t const *)pv;
3023 mask = 0xffff;
3024 break;
3025 case 4:
3026 case 8:
3027 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
3028 u32NewValue = *(uint32_t const *)pv;
3029 mask = 0xffffffff;
3030 cb = 4;
3031 break;
3032 default:
3033 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
3034 }
3035 /* cross-register access, see corresponding comment in hdaMMIORead */
3036 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
3037 mask <<= shift;
3038 u32NewValue <<= shift;
3039 u32NewValue &= mask;
3040 u32NewValue |= (u32CurValue & ~mask);
3041
3042 rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32NewValue);
3043 LogFunc(("write %s:(%x) %x => %x\n", g_aHdaRegMap[idxRegDsc].abbrev, u32NewValue,
3044 u32CurValue, pThis->au32Regs[idxRegMem]));
3045 }
3046 else
3047 rc = VINF_SUCCESS;
3048
3049 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
3050 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
3051#endif
3052 return rc;
3053}
3054
3055
3056/* PCI callback. */
3057
3058#ifdef IN_RING3
3059/**
3060 * @callback_method_impl{FNPCIIOREGIONMAP}
3061 */
3062static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
3063 PCIADDRESSSPACE enmType)
3064{
3065 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3066 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3067 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3068 int rc;
3069
3070 /*
3071 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3072 *
3073 * Let IOM talk DWORDs when reading, saves a lot of complications. On
3074 * writing though, we have to do it all ourselves because of sideeffects.
3075 */
3076 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3077 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
3078#ifdef NEW_READ_CODE
3079 IOMMMIO_FLAGS_READ_DWORD |
3080#else
3081 IOMMMIO_FLAGS_READ_PASSTHRU |
3082#endif
3083 IOMMMIO_FLAGS_WRITE_PASSTHRU,
3084 hdaMMIOWrite, hdaMMIORead, "HDA");
3085
3086 if (RT_FAILURE(rc))
3087 return rc;
3088
3089 if (pThis->fR0Enabled)
3090 {
3091 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
3092 "hdaMMIOWrite", "hdaMMIORead");
3093 if (RT_FAILURE(rc))
3094 return rc;
3095 }
3096
3097 if (pThis->fRCEnabled)
3098 {
3099 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
3100 "hdaMMIOWrite", "hdaMMIORead");
3101 if (RT_FAILURE(rc))
3102 return rc;
3103 }
3104
3105 pThis->MMIOBaseAddr = GCPhysAddress;
3106 return VINF_SUCCESS;
3107}
3108
3109
3110/* Saved state callbacks. */
3111
3112/**
3113 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3114 */
3115static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3116{
3117 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3118
3119 /* Save Codec nodes states */
3120 hdaCodecSaveState(pThis->pCodec, pSSM);
3121
3122 /* Save MMIO registers */
3123 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3124 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3125 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3126
3127 /* Save HDA dma counters */
3128 SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3129 SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3130 SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3131 return VINF_SUCCESS;
3132}
3133
3134
3135/**
3136 * @callback_method_impl{FNSSMDEVLOADEXEC}
3137 */
3138static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3139{
3140 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3141
3142 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3143
3144 /*
3145 * Load Codec nodes states.
3146 */
3147 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3148 if (RT_FAILURE(rc))
3149 return rc;
3150
3151 /*
3152 * Load MMIO registers.
3153 */
3154 uint32_t cRegs;
3155 switch (uVersion)
3156 {
3157 case HDA_SSM_VERSION_1:
3158 /* Starting with r71199, we would save 112 instead of 113
3159 registers due to some code cleanups. This only affected trunk
3160 builds in the 4.1 development period. */
3161 cRegs = 113;
3162 if (SSMR3HandleRevision(pSSM) >= 71199)
3163 {
3164 uint32_t uVer = SSMR3HandleVersion(pSSM);
3165 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3166 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3167 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3168 cRegs = 112;
3169 }
3170 break;
3171
3172 case HDA_SSM_VERSION_2:
3173 case HDA_SSM_VERSION_3:
3174 cRegs = 112;
3175 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3176 break;
3177
3178 case HDA_SSM_VERSION:
3179 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3180 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3181 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3182 break;
3183
3184 default:
3185 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3186 }
3187
3188 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3189 {
3190 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3191 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3192 }
3193 else
3194 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3195
3196 /*
3197 * Load HDA DMA counters.
3198 */
3199 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
3200 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
3201 rc = SSMR3GetStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), fFlags, paFields, NULL);
3202 AssertRCReturn(rc, rc);
3203 rc = SSMR3GetStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), fFlags, paFields, NULL);
3204 AssertRCReturn(rc, rc);
3205 rc = SSMR3GetStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), fFlags, paFields, NULL);
3206 AssertRCReturn(rc, rc);
3207
3208 /*
3209 * Update stuff after the state changes.
3210 */
3211 bool fEnableIn = RT_BOOL(SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3212#ifdef VBOX_WITH_HDA_MIC_IN
3213 bool fEnableMicIn = RT_BOOL(SDCTL(pThis, 2) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3214#else
3215 bool fEnableMicIn = fEnableIn; /* Mic In == Line In */
3216#endif
3217 bool fEnableOut = RT_BOOL(SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3218
3219#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3220 PHDADRIVER pDrv;
3221 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3222 {
3223 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, fEnableIn);
3224 if (RT_FAILURE(rc))
3225 break;
3226 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, fEnableMicIn);
3227 if (RT_FAILURE(rc))
3228 break;
3229 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, fEnableOut);
3230 if (RT_FAILURE(rc))
3231 break;
3232 }
3233#else
3234 AUD_set_active_in(pThis->pCodec->SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3235 AUD_set_active_out(pThis->pCodec->SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3236#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3237
3238 if (RT_SUCCESS(rc))
3239 {
3240 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3241 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3242 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3243 }
3244
3245 LogFlowFuncLeaveRC(rc);
3246 return rc;
3247}
3248
3249
3250/* Debug and log type formatters. */
3251
3252/**
3253 * @callback_method_impl{FNRTSTRFORMATTYPE}
3254 */
3255static DECLCALLBACK(size_t)
3256hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3257 const char *pszType, void const *pvValue,
3258 int cchWidth, int cchPrecision, unsigned fFlags,
3259 void *pvUser)
3260{
3261 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
3262 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3263 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
3264 sdCtl,
3265 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> HDA_SDCTL_NUM_SHIFT,
3266 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
3267 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3268 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3269 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3270 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3271 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3272 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3273}
3274
3275/**
3276 * @callback_method_impl{FNRTSTRFORMATTYPE}
3277 */
3278static DECLCALLBACK(size_t)
3279hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3280 const char *pszType, void const *pvValue,
3281 int cchWidth, int cchPrecision, unsigned fFlags,
3282 void *pvUser)
3283{
3284 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3285 uint32_t cb;
3286 switch (uSdFifos)
3287 {
3288 case HDA_SDONFIFO_16B: cb = 16; break;
3289 case HDA_SDONFIFO_32B: cb = 32; break;
3290 case HDA_SDONFIFO_64B: cb = 64; break;
3291 case HDA_SDONFIFO_128B: cb = 128; break;
3292 case HDA_SDONFIFO_192B: cb = 192; break;
3293 case HDA_SDONFIFO_256B: cb = 256; break;
3294 case HDA_SDINFIFO_120B: cb = 120; break;
3295 case HDA_SDINFIFO_160B: cb = 160; break;
3296 default: cb = 0; break;
3297 }
3298 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
3299}
3300
3301/**
3302 * @callback_method_impl{FNRTSTRFORMATTYPE}
3303 */
3304static DECLCALLBACK(size_t)
3305hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3306 const char *pszType, void const *pvValue,
3307 int cchWidth, int cchPrecision, unsigned fFlags,
3308 void *pvUser)
3309{
3310 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3311 uint32_t cb;
3312 switch (uSdFifos)
3313 {
3314 case HDA_SDFIFOW_8B: cb = 8; break;
3315 case HDA_SDFIFOW_16B: cb = 16; break;
3316 case HDA_SDFIFOW_32B: cb = 32; break;
3317 default: cb = 0; break;
3318 }
3319 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
3320}
3321
3322/**
3323 * @callback_method_impl{FNRTSTRFORMATTYPE}
3324 */
3325static DECLCALLBACK(size_t)
3326hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3327 const char *pszType, void const *pvValue,
3328 int cchWidth, int cchPrecision, unsigned fFlags,
3329 void *pvUser)
3330{
3331 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3332 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3333 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3334 uSdSts,
3335 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3336 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3337 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3338 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3339}
3340
3341
3342static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3343{
3344 int iReg = 0;
3345 for (; iReg < HDA_NREGS; ++iReg)
3346 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3347 return iReg;
3348 return -1;
3349}
3350
3351
3352static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
3353{
3354 Assert( pThis
3355 && iHdaIndex >= 0
3356 && iHdaIndex < HDA_NREGS);
3357 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
3358}
3359
3360
3361/**
3362 * @callback_method_impl{FNDBGFHANDLERDEV}
3363 */
3364static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3365{
3366 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3367 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
3368 if (iHdaRegisterIndex != -1)
3369 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3370 else
3371 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
3372 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3373}
3374
3375
3376static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
3377{
3378 Assert( pThis
3379 && iHdaStrmIndex >= 0
3380 && iHdaStrmIndex < 7);
3381 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
3382 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
3383 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
3384 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
3385 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
3386}
3387
3388
3389static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
3390{
3391 /* todo: add args parsing */
3392 return -1;
3393}
3394
3395
3396/**
3397 * @callback_method_impl{FNDBGFHANDLERDEV}
3398 */
3399static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3400{
3401 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3402 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
3403 if (iHdaStrmIndex != -1)
3404 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3405 else
3406 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
3407 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3408}
3409
3410
3411/**
3412 * @callback_method_impl{FNDBGFHANDLERDEV}
3413 */
3414static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3415{
3416 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3417
3418 if (pThis->pCodec->pfnCodecDbgListNodes)
3419 pThis->pCodec->pfnCodecDbgListNodes(pThis->pCodec, pHlp, pszArgs);
3420 else
3421 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3422}
3423
3424
3425/**
3426 * @callback_method_impl{FNDBGFHANDLERDEV}
3427 */
3428static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3429{
3430 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3431
3432 if (pThis->pCodec->pfnCodecDbgSelector)
3433 pThis->pCodec->pfnCodecDbgSelector(pThis->pCodec, pHlp, pszArgs);
3434 else
3435 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3436}
3437
3438
3439/* PDMIBASE */
3440
3441/**
3442 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3443 */
3444static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3445{
3446 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
3447 Assert(&pThis->IBase == pInterface);
3448
3449 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3450 return NULL;
3451}
3452
3453
3454/* PDMDEVREG */
3455
3456/**
3457 * Reset notification.
3458 *
3459 * @returns VBox status.
3460 * @param pDevIns The device instance data.
3461 *
3462 * @remark The original sources didn't install a reset handler, but it seems to
3463 * make sense to me so we'll do it.
3464 */
3465static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
3466{
3467 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3468 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
3469 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3470 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3471 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3472 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3473 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
3474 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
3475 HDA_REG(pThis, CORBRP) = 0x0;
3476 HDA_REG(pThis, RIRBWP) = 0x0;
3477
3478 LogFunc(("Resetting ...\n"));
3479
3480#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3481 /* Stop any audio currently playing. */
3482 PHDADRIVER pDrv;
3483 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3484 {
3485 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
3486 /* Ignore rc. */
3487 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
3488 /* Ditto. */
3489 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
3490 /* Ditto. */
3491 }
3492#else
3493 AUD_set_active_in(pThis->pCodec->SwVoiceIn, false);
3494 AUD_set_active_out(pThis->pCodec->SwVoiceOut, false);
3495#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3496
3497 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
3498
3499 if (pThis->pu32CorbBuf)
3500 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3501 else
3502 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3503
3504 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
3505 if (pThis->pu64RirbBuf)
3506 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3507 else
3508 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3509
3510 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
3511
3512 HDABDLEDESC StEmptyBdle;
3513 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
3514 {
3515 HDASTREAMTRANSFERDESC StreamDesc;
3516 PHDABDLEDESC pBdle = NULL;
3517 if (u8Strm == 0)
3518 pBdle = &pThis->StInBdle;
3519# ifdef VBOX_WITH_HDA_MIC_IN
3520 else if (u8Strm == 2)
3521 pBdle = &pThis->StMicBdle;
3522# endif
3523 else if(u8Strm == 4)
3524 pBdle = &pThis->StOutBdle;
3525 else
3526 {
3527 RT_ZERO(StEmptyBdle);
3528 pBdle = &StEmptyBdle;
3529 }
3530 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
3531 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
3532 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
3533 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
3534 }
3535
3536 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3537 HDA_REG(pThis, STATESTS) = 0x1;
3538
3539 LogRel(("HDA: Reset\n"));
3540}
3541
3542/**
3543 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3544 */
3545static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
3546{
3547 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3548
3549#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3550 PHDADRIVER pDrv;
3551 while (!RTListIsEmpty(&pThis->lstDrv))
3552 {
3553 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
3554
3555 RTListNodeRemove(&pDrv->Node);
3556 RTMemFree(pDrv);
3557 }
3558
3559 if (pThis->pMixer)
3560 {
3561 audioMixerDestroy(pThis->pMixer);
3562 pThis->pMixer = NULL;
3563 }
3564#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3565
3566 if (pThis->pCodec)
3567 {
3568 int rc = hdaCodecDestruct(pThis->pCodec);
3569 AssertRC(rc);
3570
3571 RTMemFree(pThis->pCodec);
3572 pThis->pCodec = NULL;
3573 }
3574
3575 RTMemFree(pThis->pu32CorbBuf);
3576 pThis->pu32CorbBuf = NULL;
3577
3578 RTMemFree(pThis->pu64RirbBuf);
3579 pThis->pu64RirbBuf = NULL;
3580
3581 return VINF_SUCCESS;
3582}
3583
3584#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3585/**
3586 * Attach command.
3587 *
3588 * This is called to let the device attach to a driver for a specified LUN
3589 * during runtime. This is not called during VM construction, the device
3590 * constructor have to attach to all the available drivers.
3591 *
3592 * @returns VBox status code.
3593 * @param pDevIns The device instance.
3594 * @param uLUN The logical unit which is being detached.
3595 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3596 */
3597static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
3598{
3599 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3600
3601 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3602 ("HDA device does not support hotplugging\n"),
3603 VERR_INVALID_PARAMETER);
3604
3605 /*
3606 * Attach driver.
3607 */
3608 char *pszDesc = NULL;
3609 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
3610 AssertMsgReturn(pszDesc,
3611 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
3612 VERR_NO_MEMORY);
3613
3614 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
3615 &pThis->IBase, &pThis->pDrvBase, pszDesc);
3616 if (RT_SUCCESS(rc))
3617 {
3618 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
3619 if (pDrv)
3620 {
3621 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
3622 AssertMsg(pDrv->pConnector != NULL,
3623 ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n",
3624 uLUN, rc));
3625 pDrv->pHDAState = pThis;
3626 pDrv->uLUN = uLUN;
3627
3628 /*
3629 * For now we always set the driver at LUN 0 as our primary
3630 * host backend. This might change in the future.
3631 */
3632 if (pDrv->uLUN == 0)
3633 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
3634
3635 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
3636
3637 /* Attach to driver list. */
3638 RTListAppend(&pThis->lstDrv, &pDrv->Node);
3639 }
3640 else
3641 rc = VERR_NO_MEMORY;
3642 }
3643 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
3644 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
3645 {
3646 LogFunc(("No attached driver for LUN #%u\n", uLUN));
3647 }
3648 else if (RT_FAILURE(rc))
3649 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
3650 uLUN, pszDesc, rc));
3651
3652 RTStrFree(pszDesc);
3653
3654 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
3655 return rc;
3656}
3657
3658static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3659{
3660 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
3661
3662 LogFlowFuncEnter();
3663}
3664#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3665
3666/**
3667 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3668 */
3669static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
3670{
3671 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3672 Assert(iInstance == 0);
3673 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3674
3675 /*
3676 * Validations.
3677 */
3678 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
3679 "RCEnabled\0"))
3680 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3681 N_ ("Invalid configuration for the Intel HDA device"));
3682
3683 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
3684 if (RT_FAILURE(rc))
3685 return PDMDEV_SET_ERROR(pDevIns, rc,
3686 N_("HDA configuration error: failed to read RCEnabled as boolean"));
3687 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
3688 if (RT_FAILURE(rc))
3689 return PDMDEV_SET_ERROR(pDevIns, rc,
3690 N_("HDA configuration error: failed to read R0Enabled as boolean"));
3691
3692 /*
3693 * Initialize data (most of it anyway).
3694 */
3695 pThis->pDevInsR3 = pDevIns;
3696 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3697 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3698 /* IBase */
3699 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
3700
3701 /* PCI Device */
3702 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
3703 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
3704
3705 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
3706 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
3707 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
3708 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
3709 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
3710 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
3711 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
3712 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
3713 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
3714 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
3715 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
3716
3717#if defined(HDA_AS_PCI_EXPRESS)
3718 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
3719#elif defined(VBOX_WITH_MSI_DEVICES)
3720 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
3721#else
3722 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
3723#endif
3724
3725 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
3726 /// of these values needs to be properly documented!
3727 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
3728 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
3729
3730 /* Power Management */
3731 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
3732 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
3733 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
3734
3735#ifdef HDA_AS_PCI_EXPRESS
3736 /* PCI Express */
3737 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
3738 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
3739 /* Device flags */
3740 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
3741 /* version */ 0x1 |
3742 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
3743 /* MSI */ (100) << 9 );
3744 /* Device capabilities */
3745 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
3746 /* Device control */
3747 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
3748 /* Device status */
3749 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
3750 /* Link caps */
3751 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
3752 /* Link control */
3753 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
3754 /* Link status */
3755 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
3756 /* Slot capabilities */
3757 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
3758 /* Slot control */
3759 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
3760 /* Slot status */
3761 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
3762 /* Root control */
3763 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
3764 /* Root capabilities */
3765 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
3766 /* Root status */
3767 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
3768 /* Device capabilities 2 */
3769 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
3770 /* Device control 2 */
3771 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
3772 /* Link control 2 */
3773 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
3774 /* Slot control 2 */
3775 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
3776#endif
3777
3778 /*
3779 * Register the PCI device.
3780 */
3781 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
3782 if (RT_FAILURE(rc))
3783 return rc;
3784
3785 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
3786 if (RT_FAILURE(rc))
3787 return rc;
3788
3789#ifdef VBOX_WITH_MSI_DEVICES
3790 PDMMSIREG MsiReg;
3791 RT_ZERO(MsiReg);
3792 MsiReg.cMsiVectors = 1;
3793 MsiReg.iMsiCapOffset = 0x60;
3794 MsiReg.iMsiNextOffset = 0x50;
3795 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3796 if (RT_FAILURE(rc))
3797 {
3798 /* That's OK, we can work without MSI */
3799 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
3800 }
3801#endif
3802
3803 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
3804 if (RT_FAILURE(rc))
3805 return rc;
3806
3807#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3808 RTListInit(&pThis->lstDrv);
3809
3810 uint8_t uLUN;
3811 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
3812 {
3813 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
3814 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
3815 if (RT_FAILURE(rc))
3816 {
3817 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3818 rc = VINF_SUCCESS;
3819
3820 break;
3821 }
3822
3823 uLUN++;
3824 }
3825
3826 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3827
3828 if (RT_SUCCESS(rc))
3829 {
3830 rc = audioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
3831 if (RT_SUCCESS(rc))
3832 {
3833 /* Set a default audio format for our mixer. */
3834 PDMAUDIOSTREAMCFG streamCfg;
3835 streamCfg.uHz = 41000;
3836 streamCfg.cChannels = 2;
3837 streamCfg.enmFormat = AUD_FMT_S16;
3838 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANESS;
3839
3840 rc = audioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
3841 AssertRC(rc);
3842
3843 /* Add all required audio sinks. */
3844 rc = audioMixerAddSink(pThis->pMixer, "[Playback] PCM Output",
3845 AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
3846 AssertRC(rc);
3847
3848 rc = audioMixerAddSink(pThis->pMixer, "[Recording] Line In",
3849 AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
3850 AssertRC(rc);
3851
3852 rc = audioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
3853 AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
3854 AssertRC(rc);
3855 }
3856 }
3857
3858 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3859#else
3860 /*
3861 * Attach driver.
3862 */
3863 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Audio Driver Port");
3864 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3865 Log(("hda: No attached driver!\n"));
3866 else if (RT_FAILURE(rc))
3867 {
3868 AssertMsgFailed(("Failed to attach Intel HDA LUN #0! rc=%Rrc\n", rc));
3869 return rc;
3870 }
3871#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3872
3873 if (RT_SUCCESS(rc))
3874 {
3875 /* Construct codec. */
3876 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
3877 if (!pThis->pCodec)
3878 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
3879
3880#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3881 /* Audio driver callbacks for multiplexing. */
3882 pThis->pCodec->pfnCloseIn = hdaCloseIn;
3883 pThis->pCodec->pfnCloseOut = hdaCloseOut;
3884 pThis->pCodec->pfnOpenIn = hdaOpenIn;
3885 pThis->pCodec->pfnOpenOut = hdaOpenOut;
3886 pThis->pCodec->pfnSetVolume = hdaSetVolume;
3887#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3888
3889 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
3890
3891 /* Construct the codec. */
3892 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
3893 if (RT_FAILURE(rc))
3894 AssertRCReturn(rc, rc);
3895
3896 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
3897 verb F20 should provide device/codec recognition. */
3898 Assert(pThis->pCodec->u16VendorId);
3899 Assert(pThis->pCodec->u16DeviceId);
3900 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
3901 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
3902
3903#ifndef VBOX_WITH_PDM_AUDIO_DRIVER
3904 pThis->pCodec->pfnTransfer = hdaTransfer;
3905#endif
3906 pThis->pCodec->pfnReset = hdaCodecReset;
3907 }
3908
3909 if (RT_SUCCESS(rc))
3910 {
3911 hdaReset(pDevIns);
3912
3913 /*
3914 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
3915 * hdaReset shouldn't affects these registers.
3916 */
3917 HDA_REG(pThis, WAKEEN) = 0x0;
3918 HDA_REG(pThis, STATESTS) = 0x0;
3919
3920 /*
3921 * Debug and string formatter types.
3922 */
3923 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
3924 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
3925 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
3926 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
3927
3928 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
3929 AssertRC(rc);
3930 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
3931 AssertRC(rc);
3932 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
3933 AssertRC(rc);
3934 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
3935 AssertRC(rc);
3936 #if 0
3937 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
3938 AssertRC(rc);
3939 #endif
3940
3941 /*
3942 * Some debug assertions.
3943 */
3944 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
3945 {
3946 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
3947 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
3948
3949 /* binary search order. */
3950 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
3951 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3952 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3953
3954 /* alignment. */
3955 AssertReleaseMsg( pReg->size == 1
3956 || (pReg->size == 2 && (pReg->offset & 1) == 0)
3957 || (pReg->size == 3 && (pReg->offset & 3) == 0)
3958 || (pReg->size == 4 && (pReg->offset & 3) == 0),
3959 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3960
3961 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
3962 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
3963 if (pReg->offset & 3)
3964 {
3965 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
3966 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3967 if (pPrevReg)
3968 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
3969 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3970 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
3971 }
3972 #if 0
3973 if ((pReg->offset + pReg->size) & 3)
3974 {
3975 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3976 if (pNextReg)
3977 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
3978 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3979 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3980 }
3981 #endif
3982
3983 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
3984 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
3985 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3986 }
3987 }
3988
3989#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3990 if (RT_SUCCESS(rc))
3991 {
3992 /* Start the emulation timer. */
3993 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
3994 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
3995 AssertRCReturn(rc, rc);
3996
3997 if (RT_SUCCESS(rc))
3998 {
3999 /** @todo Investigate why sounds is getting corrupted if the "ticks" value is too
4000 * low, e.g. "PDMDevHlpTMTimeVirtGetFreq / 200". */
4001 pThis->uTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 500; /** @todo Make this configurable! */
4002 if (pThis->uTicks < 100)
4003 pThis->uTicks = 100;
4004 LogFunc(("Timer ticks=%RU64\n", pThis->uTicks));
4005
4006 /* Fire off timer. */
4007 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
4008 }
4009 }
4010
4011# ifdef VBOX_WITH_STATISTICS
4012 if (RT_SUCCESS(rc))
4013 {
4014 /*
4015 * Register statistics.
4016 */
4017 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
4018 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
4019 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
4020 }
4021# endif
4022
4023#endif
4024
4025 LogFlowFuncLeaveRC(rc);
4026 return rc;
4027}
4028
4029/**
4030 * The device registration structure.
4031 */
4032const PDMDEVREG g_DeviceICH6_HDA =
4033{
4034 /* u32Version */
4035 PDM_DEVREG_VERSION,
4036 /* szName */
4037 "hda",
4038 /* szRCMod */
4039 "VBoxDDGC.gc",
4040 /* szR0Mod */
4041 "VBoxDDR0.r0",
4042 /* pszDescription */
4043 "Intel HD Audio Controller",
4044 /* fFlags */
4045 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
4046 /* fClass */
4047 PDM_DEVREG_CLASS_AUDIO,
4048 /* cMaxInstances */
4049 1,
4050 /* cbInstance */
4051 sizeof(HDASTATE),
4052 /* pfnConstruct */
4053 hdaConstruct,
4054 /* pfnDestruct */
4055 hdaDestruct,
4056 /* pfnRelocate */
4057 NULL,
4058 /* pfnMemSetup */
4059 NULL,
4060 /* pfnPowerOn */
4061 NULL,
4062 /* pfnReset */
4063 hdaReset,
4064 /* pfnSuspend */
4065 NULL,
4066 /* pfnResume */
4067 NULL,
4068 /* pfnAttach */
4069 NULL,
4070 /* pfnDetach */
4071 NULL,
4072 /* pfnQueryInterface. */
4073 NULL,
4074 /* pfnInitComplete */
4075 NULL,
4076 /* pfnPowerOff */
4077 NULL,
4078 /* pfnSoftReset */
4079 NULL,
4080 /* u32VersionEnd */
4081 PDM_DEVREG_VERSION
4082};
4083
4084#endif /* IN_RING3 */
4085#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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