VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 55998

Last change on this file since 55998 was 55920, checked in by vboxsync, 10 years ago

PDM/Audio: AudioMixBuffer documentation, renaming.
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1/* $Id: DevIchHda.cpp 55920 2015-05-18 19:11:51Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2015 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/vmm/pdmaudioifs.h>
27#include <VBox/version.h>
28
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#ifdef IN_RING3
33# include <iprt/uuid.h>
34# include <iprt/string.h>
35# include <iprt/mem.h>
36#endif
37#include <iprt/list.h>
38
39#ifdef LOG_GROUP
40# undef LOG_GROUP
41#endif
42#define LOG_GROUP LOG_GROUP_DEV_AUDIO
43#include <VBox/log.h>
44
45#include "VBoxDD.h"
46
47#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
48# include "AudioMixer.h"
49#else
50 extern "C" {
51 #include "audio.h"
52 }
53#endif
54#include "DevIchHdaCodec.h"
55
56/*******************************************************************************
57* Defined Constants And Macros *
58*******************************************************************************/
59//#define HDA_AS_PCI_EXPRESS
60#define VBOX_WITH_INTEL_HDA
61
62#if (defined(DEBUG) && defined(DEBUG_andy))
63/* Enables experimental support for separate mic-in handling.
64 Do not enable this yet for regular builds, as this needs more testing first! */
65# define VBOX_WITH_HDA_MIC_IN
66#endif
67
68#if defined(VBOX_WITH_HP_HDA)
69/* HP Pavilion dv4t-1300 */
70# define HDA_PCI_VENDOR_ID 0x103c
71# define HDA_PCI_DEVICE_ID 0x30f7
72#elif defined(VBOX_WITH_INTEL_HDA)
73/* Intel HDA controller */
74# define HDA_PCI_VENDOR_ID 0x8086
75# define HDA_PCI_DEVICE_ID 0x2668
76#elif defined(VBOX_WITH_NVIDIA_HDA)
77/* nVidia HDA controller */
78# define HDA_PCI_VENDOR_ID 0x10de
79# define HDA_PCI_DEVICE_ID 0x0ac0
80#else
81# error "Please specify your HDA device vendor/device IDs"
82#endif
83
84/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
85 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
86 * is read only except for bit 15 like the HDA spec states.
87 *
88 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
89 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
90#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
91
92#define HDA_NREGS 114
93#define HDA_NREGS_SAVED 112
94
95/**
96 * NB: Register values stored in memory (au32Regs[]) are indexed through
97 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
98 * register descriptors in g_aHdaRegMap[] are indexed through the
99 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
100 *
101 * The au32Regs[] layout is kept unchanged for saved state
102 * compatibility. */
103
104/* Registers */
105#define HDA_REG_IND_NAME(x) HDA_REG_##x
106#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
107#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
108#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
109#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
110#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
111#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
112#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
113
114
115#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
116#define HDA_RMX_GCAP 0
117/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
118 * oss (15:12) - number of output streams supported
119 * iss (11:8) - number of input streams supported
120 * bss (7:3) - number of bidirectional streams supported
121 * bds (2:1) - number of serial data out signals supported
122 * b64sup (0) - 64 bit addressing supported.
123 */
124#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
125 ( (((oss) & 0xF) << 12) \
126 | (((iss) & 0xF) << 8) \
127 | (((bss) & 0x1F) << 3) \
128 | (((bds) & 0x3) << 2) \
129 | ((b64sup) & 1))
130
131#define HDA_REG_VMIN 1 /* 0x02 */
132#define HDA_RMX_VMIN 1
133
134#define HDA_REG_VMAJ 2 /* 0x03 */
135#define HDA_RMX_VMAJ 2
136
137#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
138#define HDA_RMX_OUTPAY 3
139
140#define HDA_REG_INPAY 4 /* 0x06-0x07 */
141#define HDA_RMX_INPAY 4
142
143#define HDA_REG_GCTL 5 /* 0x08-0x0B */
144#define HDA_RMX_GCTL 5
145#define HDA_GCTL_RST_SHIFT 0
146#define HDA_GCTL_FSH_SHIFT 1
147#define HDA_GCTL_UR_SHIFT 8
148
149#define HDA_REG_WAKEEN 6 /* 0x0C */
150#define HDA_RMX_WAKEEN 6
151
152#define HDA_REG_STATESTS 7 /* 0x0E */
153#define HDA_RMX_STATESTS 7
154#define HDA_STATES_SCSF 0x7
155
156#define HDA_REG_GSTS 8 /* 0x10-0x11*/
157#define HDA_RMX_GSTS 8
158#define HDA_GSTS_FSH_SHIFT 1
159
160#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
161#define HDA_RMX_OUTSTRMPAY 112
162
163#define HDA_REG_INSTRMPAY 10 /* 0x1a */
164#define HDA_RMX_INSTRMPAY 113
165
166#define HDA_REG_INTCTL 11 /* 0x20 */
167#define HDA_RMX_INTCTL 9
168#define HDA_INTCTL_GIE_SHIFT 31
169#define HDA_INTCTL_CIE_SHIFT 30
170#define HDA_INTCTL_S0_SHIFT 0
171#define HDA_INTCTL_S1_SHIFT 1
172#define HDA_INTCTL_S2_SHIFT 2
173#define HDA_INTCTL_S3_SHIFT 3
174#define HDA_INTCTL_S4_SHIFT 4
175#define HDA_INTCTL_S5_SHIFT 5
176#define HDA_INTCTL_S6_SHIFT 6
177#define HDA_INTCTL_S7_SHIFT 7
178#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
179
180#define HDA_REG_INTSTS 12 /* 0x24 */
181#define HDA_RMX_INTSTS 10
182#define HDA_INTSTS_GIS_SHIFT 31
183#define HDA_INTSTS_CIS_SHIFT 30
184#define HDA_INTSTS_S0_SHIFT 0
185#define HDA_INTSTS_S1_SHIFT 1
186#define HDA_INTSTS_S2_SHIFT 2
187#define HDA_INTSTS_S3_SHIFT 3
188#define HDA_INTSTS_S4_SHIFT 4
189#define HDA_INTSTS_S5_SHIFT 5
190#define HDA_INTSTS_S6_SHIFT 6
191#define HDA_INTSTS_S7_SHIFT 7
192#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
193
194#define HDA_REG_WALCLK 13 /* 0x24 */
195#define HDA_RMX_WALCLK /* Not defined! */
196
197/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
198 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
199 * the datasheet.
200 */
201#define HDA_REG_SSYNC 14 /* 0x34 */
202#define HDA_RMX_SSYNC 12
203
204#define HDA_REG_CORBLBASE 15 /* 0x40 */
205#define HDA_RMX_CORBLBASE 13
206
207#define HDA_REG_CORBUBASE 16 /* 0x44 */
208#define HDA_RMX_CORBUBASE 14
209
210#define HDA_REG_CORBWP 17 /* 0x48 */
211#define HDA_RMX_CORBWP 15
212
213#define HDA_REG_CORBRP 18 /* 0x4A */
214#define HDA_RMX_CORBRP 16
215#define HDA_CORBRP_RST_SHIFT 15
216#define HDA_CORBRP_WP_SHIFT 0
217#define HDA_CORBRP_WP_MASK 0xFF
218
219#define HDA_REG_CORBCTL 19 /* 0x4C */
220#define HDA_RMX_CORBCTL 17
221#define HDA_CORBCTL_DMA_SHIFT 1
222#define HDA_CORBCTL_CMEIE_SHIFT 0
223
224#define HDA_REG_CORBSTS 20 /* 0x4D */
225#define HDA_RMX_CORBSTS 18
226#define HDA_CORBSTS_CMEI_SHIFT 0
227
228#define HDA_REG_CORBSIZE 21 /* 0x4E */
229#define HDA_RMX_CORBSIZE 19
230#define HDA_CORBSIZE_SZ_CAP 0xF0
231#define HDA_CORBSIZE_SZ 0x3
232/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
233
234#define HDA_REG_RIRBLBASE 22 /* 0x50 */
235#define HDA_RMX_RIRBLBASE 20
236
237#define HDA_REG_RIRBUBASE 23 /* 0x54 */
238#define HDA_RMX_RIRBUBASE 21
239
240#define HDA_REG_RIRBWP 24 /* 0x58 */
241#define HDA_RMX_RIRBWP 22
242#define HDA_RIRBWP_RST_SHIFT 15
243#define HDA_RIRBWP_WP_MASK 0xFF
244
245#define HDA_REG_RINTCNT 25 /* 0x5A */
246#define HDA_RMX_RINTCNT 23
247#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
248
249#define HDA_REG_RIRBCTL 26 /* 0x5C */
250#define HDA_RMX_RIRBCTL 24
251#define HDA_RIRBCTL_RIC_SHIFT 0
252#define HDA_RIRBCTL_DMA_SHIFT 1
253#define HDA_ROI_DMA_SHIFT 2
254
255#define HDA_REG_RIRBSTS 27 /* 0x5D */
256#define HDA_RMX_RIRBSTS 25
257#define HDA_RIRBSTS_RINTFL_SHIFT 0
258#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
259
260#define HDA_REG_RIRBSIZE 28 /* 0x5E */
261#define HDA_RMX_RIRBSIZE 26
262#define HDA_RIRBSIZE_SZ_CAP 0xF0
263#define HDA_RIRBSIZE_SZ 0x3
264
265#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
266#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
267
268
269#define HDA_REG_IC 29 /* 0x60 */
270#define HDA_RMX_IC 27
271
272#define HDA_REG_IR 30 /* 0x64 */
273#define HDA_RMX_IR 28
274
275#define HDA_REG_IRS 31 /* 0x68 */
276#define HDA_RMX_IRS 29
277#define HDA_IRS_ICB_SHIFT 0
278#define HDA_IRS_IRV_SHIFT 1
279
280#define HDA_REG_DPLBASE 32 /* 0x70 */
281#define HDA_RMX_DPLBASE 30
282#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
283
284#define HDA_REG_DPUBASE 33 /* 0x74 */
285#define HDA_RMX_DPUBASE 31
286#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
287#define DPBASE_ENABLED 1
288#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
289
290#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
291#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
292/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
293#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
294
295#define HDA_REG_SD0CTL 34 /* 0x80 */
296#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
297#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
298#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
299#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
300#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
301#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
302#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
303#define HDA_RMX_SD0CTL 32
304#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
305#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
306#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
307#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
308#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
309#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
310#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
311
312#define SD(func, num) SD##num##func
313#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
314#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
315#define HDA_SDCTL_NUM_MASK 0xF
316#define HDA_SDCTL_NUM_SHIFT 20
317#define HDA_SDCTL_DIR_SHIFT 19
318#define HDA_SDCTL_TP_SHIFT 18
319#define HDA_SDCTL_STRIPE_MASK 0x3
320#define HDA_SDCTL_STRIPE_SHIFT 16
321#define HDA_SDCTL_DEIE_SHIFT 4
322#define HDA_SDCTL_FEIE_SHIFT 3
323#define HDA_SDCTL_ICE_SHIFT 2
324#define HDA_SDCTL_RUN_SHIFT 1
325#define HDA_SDCTL_SRST_SHIFT 0
326
327#define HDA_REG_SD0STS 35 /* 0x83 */
328#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
329#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
330#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
331#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
332#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
333#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
334#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
335#define HDA_RMX_SD0STS 33
336#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
337#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
338#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
339#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
340#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
341#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
342#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
343
344#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
345#define HDA_SDSTS_FIFORDY_SHIFT 5
346#define HDA_SDSTS_DE_SHIFT 4
347#define HDA_SDSTS_FE_SHIFT 3
348#define HDA_SDSTS_BCIS_SHIFT 2
349
350#define HDA_REG_SD0LPIB 36 /* 0x84 */
351#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
352#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
353#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
354#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
355#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
356#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
357#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
358#define HDA_RMX_SD0LPIB 34
359#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
360#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
361#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
362#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
363#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
364#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
365#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
366
367#define HDA_REG_SD0CBL 37 /* 0x88 */
368#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
369#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
370#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
371#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
372#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
373#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
374#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
375#define HDA_RMX_SD0CBL 35
376#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
377#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
378#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
379#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
380#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
381#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
382#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
383
384
385#define HDA_REG_SD0LVI 38 /* 0x8C */
386#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
387#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
388#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
389#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
390#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
391#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
392#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
393#define HDA_RMX_SD0LVI 36
394#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
395#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
396#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
397#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
398#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
399#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
400#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
401
402#define HDA_REG_SD0FIFOW 39 /* 0x8E */
403#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
404#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
405#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
406#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
407#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
408#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
409#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
410#define HDA_RMX_SD0FIFOW 37
411#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
412#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
413#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
414#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
415#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
416#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
417#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
418
419/*
420 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
421 */
422#define HDA_SDFIFOW_8B 0x2
423#define HDA_SDFIFOW_16B 0x3
424#define HDA_SDFIFOW_32B 0x4
425
426#define HDA_REG_SD0FIFOS 40 /* 0x90 */
427#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
428#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
429#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
430#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
431#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
432#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
433#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
434#define HDA_RMX_SD0FIFOS 38
435#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
436#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
437#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
438#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
439#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
440#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
441#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
442
443/*
444 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
445 * formula: size - 1
446 * Other values not listed are not supported.
447 */
448#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
449#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
450#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
451#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
452#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
453#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
454#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
455#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
456#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
457
458#define HDA_REG_SD0FMT 41 /* 0x92 */
459#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
460#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
461#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
462#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
463#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
464#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
465#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
466#define HDA_RMX_SD0FMT 39
467#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
468#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
469#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
470#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
471#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
472#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
473#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
474
475#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
476#define HDA_SDFMT_BASE_RATE_SHIFT 14
477#define HDA_SDFMT_MULT_SHIFT 11
478#define HDA_SDFMT_MULT_MASK 0x7
479#define HDA_SDFMT_DIV_SHIFT 8
480#define HDA_SDFMT_DIV_MASK 0x7
481#define HDA_SDFMT_BITS_SHIFT 4
482#define HDA_SDFMT_BITS_MASK 0x7
483#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
484#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
485#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
486
487#define HDA_REG_SD0BDPL 42 /* 0x98 */
488#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
489#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
490#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
491#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
492#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
493#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
494#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
495#define HDA_RMX_SD0BDPL 40
496#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
497#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
498#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
499#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
500#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
501#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
502#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
503
504#define HDA_REG_SD0BDPU 43 /* 0x9C */
505#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
506#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
507#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
508#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
509#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
510#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
511#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
512#define HDA_RMX_SD0BDPU 41
513#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
514#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
515#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
516#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
517#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
518#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
519#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
520
521#define HDA_CODEC_CAD_SHIFT 28
522/* Encodes the (required) LUN into a codec command. */
523#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
524
525
526
527/*******************************************************************************
528* Structures and Typedefs *
529*******************************************************************************/
530typedef struct HDABDLEDESC
531{
532 uint64_t u64BdleCviAddr;
533 uint32_t u32BdleMaxCvi;
534 uint32_t u32BdleCvi;
535 uint32_t u32BdleCviLen;
536 uint32_t u32BdleCviPos;
537 bool fBdleCviIoc;
538 uint32_t cbUnderFifoW;
539 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
540} HDABDLEDESC, *PHDABDLEDESC;
541
542typedef struct HDASTREAMTRANSFERDESC
543{
544 uint64_t u64BaseDMA;
545 uint32_t u32Ctl;
546 uint32_t *pu32Sts;
547 uint8_t u8Strm;
548 uint32_t *pu32Lpib;
549 uint32_t u32Cbl;
550 uint32_t u32Fifos;
551} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
552
553#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
554typedef struct HDAINPUTSTREAM
555{
556 /** PCM line input stream. */
557 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
558 /** Mixer handle for line input stream. */
559 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
560} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
561
562typedef struct HDAOUTPUTSTREAM
563{
564 /** PCM output stream. */
565 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
566 /** Mixer handle for line output stream. */
567 R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
568} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
569
570/**
571 * Struct for maintaining a host backend driver.
572 * This driver must be associated to one, and only one,
573 * HDA codec. The HDA controller does the actual multiplexing
574 * of HDA codec data to various host backend drivers then.
575 *
576 * This HDA device uses a timer in order to synchronize all
577 * read/write accesses across all attached LUNs / backends.
578 */
579typedef struct HDADRIVER
580{
581 union
582 {
583 /** Node for storing this driver in our device driver
584 * list of HDASTATE. */
585 RTLISTNODE Node;
586 struct
587 {
588 R3PTRTYPE(void *) dummy1;
589 R3PTRTYPE(void *) dummy2;
590 } dummy;
591 };
592
593 /** Pointer to HDA controller (state). */
594 R3PTRTYPE(PHDASTATE) pHDAState;
595 /** Driver flags. */
596 PDMAUDIODRVFLAGS Flags;
597 uint8_t u32Padding0[3];
598 /** LUN to which this driver has been assigned. */
599 uint8_t uLUN;
600 /** Audio connector interface to the underlying
601 * host backend. */
602 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
603 /** Stream for line input. */
604 HDAINPUTSTREAM LineIn;
605 /** Stream for mic input. */
606 HDAINPUTSTREAM MicIn;
607 /** Stream for output. */
608 HDAOUTPUTSTREAM Out;
609} HDADRIVER, *PHDADRIVER;
610#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
611
612/**
613 * ICH Intel HD Audio Controller state.
614 */
615typedef struct HDASTATE
616{
617 /** The PCI device structure. */
618 PCIDevice PciDev;
619 /** R3 Pointer to the device instance. */
620 PPDMDEVINSR3 pDevInsR3;
621 /** R0 Pointer to the device instance. */
622 PPDMDEVINSR0 pDevInsR0;
623 /** R0 Pointer to the device instance. */
624 PPDMDEVINSRC pDevInsRC;
625
626 uint32_t u32Padding;
627
628 /** Pointer to the attached audio driver. */
629 R3PTRTYPE(PPDMIBASE) pDrvBase;
630 /** The base interface for LUN\#0. */
631 PDMIBASE IBase;
632 RTGCPHYS MMIOBaseAddr;
633 uint32_t au32Regs[HDA_NREGS];
634 HDABDLEDESC StInBdle;
635 HDABDLEDESC StOutBdle;
636 HDABDLEDESC StMicBdle;
637 uint64_t u64CORBBase;
638 uint64_t u64RIRBBase;
639 uint64_t u64DPBase;
640 /** Pointer to CORB buffer. */
641 R3PTRTYPE(uint32_t *) pu32CorbBuf;
642 /** Size in bytes of CORB buffer. */
643 uint32_t cbCorbBuf;
644 uint32_t u32Padding2;
645 /** Pointer to RIRB buffer. */
646 R3PTRTYPE(uint64_t *) pu64RirbBuf;
647 /** Size in bytes of RIRB buffer. */
648 uint32_t cbRirbBuf;
649 /** Indicates if HDA is in reset. */
650 bool fInReset;
651 /** Interrupt on completion */
652 bool fCviIoc;
653 /** Flag whether the R0 part is enabled. */
654 bool fR0Enabled;
655 /** Flag whether the RC part is enabled. */
656 bool fRCEnabled;
657#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
658 /** The emulation timer for handling the attached
659 * LUN drivers. */
660 PTMTIMERR3 pTimer;
661 /** Timer ticks for handling the LUN drivers. */
662 uint64_t uTicks;
663# ifdef VBOX_WITH_STATISTICS
664 STAMPROFILE StatTimer;
665 STAMCOUNTER StatBytesRead;
666 STAMCOUNTER StatBytesWritten;
667# endif
668 /** Pointer to HDA codec to use. */
669 R3PTRTYPE(PHDACODEC) pCodec;
670 union
671 {
672 /** List of associated LUN drivers. */
673 RTLISTANCHOR lstDrv;
674 struct
675 {
676 R3PTRTYPE(void *) dummy1;
677 R3PTRTYPE(void *) dummy2;
678 } dummy;
679 };
680 /** The device' software mixer. */
681 R3PTRTYPE(PAUDIOMIXER) pMixer;
682 /** Audio sink for PCM output. */
683 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
684 /** Audio mixer sink for line input. */
685 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
686 /** Audio mixer sink for microphone input. */
687 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
688#else /* !VBOX_WITH_PDM_AUDIO_DRIVER */
689 /** The HDA codec to use. */
690 R3PTRTYPE(PHDACODEC) pCodec;
691#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
692 uint64_t u64BaseTS;
693 /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
694 uint8_t u8Counter;
695#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
696 uint8_t au8Padding[7];
697#else
698 uint8_t au8Padding[7];
699#endif
700} HDASTATE;
701/** Pointer to the ICH Intel HD Audio Controller state. */
702typedef HDASTATE *PHDASTATE;
703
704#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
705 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
706#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
707 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
708
709
710/*******************************************************************************
711* Internal Functions *
712*******************************************************************************/
713#ifndef VBOX_DEVICE_STRUCT_TESTCASE
714static FNPDMDEVRESET hdaReset;
715
716static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
717static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
718static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
719static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
720static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
721static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
722static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
723static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
724static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
725static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
726static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
727static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
728static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
729static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
730static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
731static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
732static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
733
734static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
735static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
736static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
737static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
738static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
739static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
740static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
741static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
742static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
743static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
744static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
745static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
746static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
747static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
748static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
749static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
750
751#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
752static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
753static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail);
754#else
755static int hdaTransfer(PHDACODEC pCodec, ENMSOUNDSOURCE enmSource, int cbAvail);
756#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
757
758#ifdef IN_RING3
759DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
760 PHDASTREAMTRANSFERDESC pStreamDesc);
761static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
762#ifdef LOG_ENABLED
763static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
764#endif
765#endif
766
767
768/*******************************************************************************
769* Global Variables *
770*******************************************************************************/
771
772/* see 302349 p 6.2*/
773static const struct HDAREGDESC
774{
775 /** Register offset in the register space. */
776 uint32_t offset;
777 /** Size in bytes. Registers of size > 4 are in fact tables. */
778 uint32_t size;
779 /** Readable bits. */
780 uint32_t readable;
781 /** Writable bits. */
782 uint32_t writable;
783 /** Read callback. */
784 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
785 /** Write callback. */
786 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
787 /** Index into the register storage array. */
788 uint32_t mem_idx;
789 /** Abbreviated name. */
790 const char *abbrev;
791} g_aHdaRegMap[HDA_NREGS] =
792
793/* Turn a short register name into an memory index and a stringized name. */
794#define RA(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
795/* Same as above for an input stream ('I' prefixed). */
796#define IA(abbrev) HDA_MEM_IND_NAME(abbrev), "I"#abbrev
797/* Same as above for an output stream ('O' prefixed). */
798#define OA(abbrev) HDA_MEM_IND_NAME(abbrev), "O"#abbrev
799/* Same as above for a register *not* stored in memory. */
800#define UA(abbrev) 0, #abbrev
801
802{
803 /* offset size read mask write mask read callback write callback abbrev */
804 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- */
805 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(GCAP) }, /* Global Capabilities */
806 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMIN) }, /* Minor Version */
807 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMAJ) }, /* Major Version */
808 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTPAY) }, /* Output Payload Capabilities */
809 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INPAY) }, /* Input Payload Capabilities */
810 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , RA(GCTL) }, /* Global Control */
811 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , RA(WAKEEN) }, /* Wake Enable */
812 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , RA(STATESTS) }, /* State Change Status */
813 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , RA(GSTS) }, /* Global Status */
814 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTSTRMPAY)}, /* Output Stream Payload Capability */
815 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INSTRMPAY) }, /* Input Stream Payload Capability */
816 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(INTCTL) }, /* Interrupt Control */
817 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , RA(INTSTS) }, /* Interrupt Status */
818 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , UA(WALCLK) }, /* Wall Clock Counter */
819 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
820 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(SSYNC) }, /* Stream Synchronization */
821 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(CORBLBASE) }, /* CORB Lower Base Address */
822 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(CORBUBASE) }, /* CORB Upper Base Address */
823 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , RA(CORBWP) }, /* CORB Write Pointer */
824 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , RA(CORBRP) }, /* CORB Read Pointer */
825 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , RA(CORBCTL) }, /* CORB Control */
826 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , RA(CORBSTS) }, /* CORB Status */
827 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(CORBSIZE) }, /* CORB Size */
828 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBLBASE) }, /* RIRB Lower Base Address */
829 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBUBASE) }, /* RIRB Upper Base Address */
830 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , RA(RIRBWP) }, /* RIRB Write Pointer */
831 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , RA(RINTCNT) }, /* Response Interrupt Count */
832 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , RA(RIRBCTL) }, /* RIRB Control */
833 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , RA(RIRBSTS) }, /* RIRB Status */
834 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(RIRBSIZE) }, /* RIRB Size */
835 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , RA(IC) }, /* Immediate Command */
836 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , RA(IR) }, /* Immediate Response */
837 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , RA(IRS) }, /* Immediate Command Status */
838 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , RA(DPLBASE) }, /* MA Position Lower Base */
839 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(DPUBASE) }, /* DMA Position Upper Base */
840
841 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD0CTL) }, /* Input Stream Descriptor 0 (ICD0) Control */
842 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD0STS) }, /* ISD0 Status */
843 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0LPIB) }, /* ISD0 Link Position In Buffer */
844 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0CBL) }, /* ISD0 Cyclic Buffer Length */
845 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD0LVI) }, /* ISD0 Last Valid Index */
846 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD0FIFOW) }, /* ISD0 FIFO Watermark */
847 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD0FIFOS) }, /* ISD0 FIFO Size */
848 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD0FMT) }, /* ISD0 Format */
849 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD0BDPL) }, /* ISD0 Buffer Descriptor List Pointer-Lower Base Address */
850 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD0BDPU) }, /* ISD0 Buffer Descriptor List Pointer-Upper Base Address */
851
852 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD1CTL) }, /* Input Stream Descriptor 1 (ISD1) Control */
853 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD1STS) }, /* ISD1 Status */
854 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1LPIB) }, /* ISD1 Link Position In Buffer */
855 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1CBL) }, /* ISD1 Cyclic Buffer Length */
856 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD1LVI) }, /* ISD1 Last Valid Index */
857 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD1FIFOW) }, /* ISD1 FIFO Watermark */
858 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD1FIFOS) }, /* ISD1 FIFO Size */
859 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD1FMT) }, /* ISD1 Format */
860 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD1BDPL) }, /* ISD1 Buffer Descriptor List Pointer-Lower Base Address */
861 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD1BDPU) }, /* ISD1 Buffer Descriptor List Pointer-Upper Base Address */
862
863 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD2CTL) }, /* Input Stream Descriptor 2 (ISD2) Control */
864 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD2STS) }, /* ISD2 Status */
865 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2LPIB) }, /* ISD2 Link Position In Buffer */
866 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2CBL) }, /* ISD2 Cyclic Buffer Length */
867 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD2LVI) }, /* ISD2 Last Valid Index */
868 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD2FIFOW) }, /* ISD2 FIFO Watermark */
869 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD2FIFOS) }, /* ISD2 FIFO Size */
870 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD2FMT) }, /* ISD2 Format */
871 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD2BDPL) }, /* ISD2 Buffer Descriptor List Pointer-Lower Base Address */
872 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD2BDPU) }, /* ISD2 Buffer Descriptor List Pointer-Upper Base Address */
873
874 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD3CTL) }, /* Input Stream Descriptor 3 (ISD3) Control */
875 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD3STS) }, /* ISD3 Status */
876 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3LPIB) }, /* ISD3 Link Position In Buffer */
877 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3CBL) }, /* ISD3 Cyclic Buffer Length */
878 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD3LVI) }, /* ISD3 Last Valid Index */
879 { 0x000EE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD3FIFOW) }, /* ISD3 FIFO Watermark */
880 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD3FIFOS) }, /* ISD3 FIFO Size */
881 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD3FMT) }, /* ISD3 Format */
882 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD3BDPL) }, /* ISD3 Buffer Descriptor List Pointer-Lower Base Address */
883 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD3BDPU) }, /* ISD3 Buffer Descriptor List Pointer-Upper Base Address */
884
885 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD4CTL) }, /* Output Stream Descriptor 4 (OSD4) Control */
886 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD4STS) }, /* OSD4 Status */
887 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4LPIB) }, /* OSD4 Link Position In Buffer */
888 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4CBL) }, /* OSD4 Cyclic Buffer Length */
889 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD4LVI) }, /* OSD4 Last Valid Index */
890 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD4FIFOW) }, /* OSD4 FIFO Watermark */
891 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD4FIFOS) }, /* OSD4 FIFO Size */
892 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD4FMT) }, /* OSD4 Format */
893 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD4BDPL) }, /* OSD4 Buffer Descriptor List Pointer-Lower Base Address */
894 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD4BDPU) }, /* OSD4 Buffer Descriptor List Pointer-Upper Base Address */
895
896 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD5CTL) }, /* Output Stream Descriptor 5 (OSD5) Control */
897 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD5STS) }, /* OSD5 Status */
898 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5LPIB) }, /* OSD5 Link Position In Buffer */
899 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5CBL) }, /* OSD5 Cyclic Buffer Length */
900 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD5LVI) }, /* OSD5 Last Valid Index */
901 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD5FIFOW) }, /* OSD5 FIFO Watermark */
902 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD5FIFOS) }, /* OSD5 FIFO Size */
903 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD5FMT) }, /* OSD5 Format */
904 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD5BDPL) }, /* OSD5 Buffer Descriptor List Pointer-Lower Base Address */
905 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD5BDPU) }, /* OSD5 Buffer Descriptor List Pointer-Upper Base Address */
906
907 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD6CTL) }, /* Output Stream Descriptor 6 (OSD6) Control */
908 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD6STS) }, /* OSD6 Status */
909 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6LPIB) }, /* OSD6 Link Position In Buffer */
910 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6CBL) }, /* OSD6 Cyclic Buffer Length */
911 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD6LVI) }, /* OSD6 Last Valid Index */
912 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD6FIFOW) }, /* OSD6 FIFO Watermark */
913 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD6FIFOS) }, /* OSD6 FIFO Size */
914 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD6FMT) }, /* OSD6 Format */
915 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD6BDPL) }, /* OSD6 Buffer Descriptor List Pointer-Lower Base Address */
916 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD6BDPU) }, /* OSD6 Buffer Descriptor List Pointer-Upper Base Address */
917
918 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD7CTL) }, /* Output Stream Descriptor 7 (OSD7) Control */
919 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD7STS) }, /* OSD7 Status */
920 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7LPIB) }, /* OSD7 Link Position In Buffer */
921 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7CBL) }, /* OSD7 Cyclic Buffer Length */
922 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD7LVI) }, /* OSD7 Last Valid Index */
923 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD7FIFOW) }, /* OSD7 FIFO Watermark */
924 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD7FIFOS) }, /* OSD7 FIFO Size */
925 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD7FMT) }, /* OSD7 Format */
926 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD7BDPL) }, /* OSD7 Buffer Descriptor List Pointer-Lower Base Address */
927 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD7BDPU) }, /* OSD7 Buffer Descriptor List Pointer-Upper Base Address */
928};
929
930/**
931 * HDA register aliases (HDA spec 3.3.45).
932 * @remarks Sorted by offReg.
933 */
934static const struct
935{
936 /** The alias register offset. */
937 uint32_t offReg;
938 /** The register index. */
939 int idxAlias;
940} g_aHdaRegAliases[] =
941{
942 { 0x2084, HDA_REG_SD0LPIB },
943 { 0x20a4, HDA_REG_SD1LPIB },
944 { 0x20c4, HDA_REG_SD2LPIB },
945 { 0x20e4, HDA_REG_SD3LPIB },
946 { 0x2104, HDA_REG_SD4LPIB },
947 { 0x2124, HDA_REG_SD5LPIB },
948 { 0x2144, HDA_REG_SD6LPIB },
949 { 0x2164, HDA_REG_SD7LPIB },
950};
951
952#ifdef IN_RING3
953/** HDABDLEDESC field descriptors the v3+ saved state. */
954static SSMFIELD const g_aHdaBDLEDescFields[] =
955{
956 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
957 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
958 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
959 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
960 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
961 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
962 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
963 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
964 SSMFIELD_ENTRY_TERM()
965};
966
967/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
968static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
969{
970 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
971 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
972 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
973 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
974 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
975 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
976 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
977 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
978 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
979 SSMFIELD_ENTRY_TERM()
980};
981#endif
982
983/**
984 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
985 */
986static uint32_t const g_afMasks[5] =
987{
988 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
989};
990
991#ifdef IN_RING3
992DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
993{
994 if (pThis->u64DPBase & DPBASE_ENABLED)
995 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
996 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
997 pStreamDesc->pu32Lpib, sizeof(uint32_t));
998}
999#endif
1000
1001DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
1002{
1003#if 0
1004 switch(HDA_STREAM_REG(pThis, FIFOW, pStreamDesc->u8Strm))
1005 {
1006 case HDA_SDFIFOW_8B: return 8;
1007 case HDA_SDFIFOW_16B: return 16;
1008 case HDA_SDFIFOW_32B: return 32;
1009 default:
1010 AssertMsgFailed(("unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
1011 }
1012#endif
1013 return 0;
1014}
1015
1016static int hdaProcessInterrupt(PHDASTATE pThis)
1017{
1018#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1019 ( INTCTL_SX((pThis), num) \
1020 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1021 bool fIrq = false;
1022 if ( HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1023 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1024 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1025 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1026 fIrq = true;
1027
1028 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1029 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1030 fIrq = true;
1031
1032 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1033 {
1034 LogFunc(("irq %s\n", fIrq ? "asserted" : "deasserted"));
1035 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1036 }
1037 return VINF_SUCCESS;
1038}
1039
1040/**
1041 * Looks up a register at the exact offset given by @a offReg.
1042 *
1043 * @returns Register index on success, -1 if not found.
1044 * @param pThis The HDA device state.
1045 * @param offReg The register offset.
1046 */
1047static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1048{
1049 /*
1050 * Aliases.
1051 */
1052 if (offReg >= g_aHdaRegAliases[0].offReg)
1053 {
1054 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1055 if (offReg == g_aHdaRegAliases[i].offReg)
1056 return g_aHdaRegAliases[i].idxAlias;
1057 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1058 return -1;
1059 }
1060
1061 /*
1062 * Binary search the
1063 */
1064 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1065 int idxLow = 0;
1066 for (;;)
1067 {
1068 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1069 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1070 {
1071 if (idxLow == idxMiddle)
1072 break;
1073 idxEnd = idxMiddle;
1074 }
1075 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1076 {
1077 idxLow = idxMiddle + 1;
1078 if (idxLow >= idxEnd)
1079 break;
1080 }
1081 else
1082 return idxMiddle;
1083 }
1084
1085#ifdef RT_STRICT
1086 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1087 Assert(g_aHdaRegMap[i].offset != offReg);
1088#endif
1089 return -1;
1090}
1091
1092/**
1093 * Looks up a register covering the offset given by @a offReg.
1094 *
1095 * @returns Register index on success, -1 if not found.
1096 * @param pThis The HDA device state.
1097 * @param offReg The register offset.
1098 */
1099static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1100{
1101 /*
1102 * Aliases.
1103 */
1104 if (offReg >= g_aHdaRegAliases[0].offReg)
1105 {
1106 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1107 {
1108 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1109 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1110 return g_aHdaRegAliases[i].idxAlias;
1111 }
1112 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1113 return -1;
1114 }
1115
1116 /*
1117 * Binary search the
1118 */
1119 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1120 int idxLow = 0;
1121 for (;;)
1122 {
1123 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1124 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1125 {
1126 if (idxLow == idxMiddle)
1127 break;
1128 idxEnd = idxMiddle;
1129 }
1130 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1131 {
1132 idxLow = idxMiddle + 1;
1133 if (idxLow >= idxEnd)
1134 break;
1135 }
1136 else
1137 return idxMiddle;
1138 }
1139
1140#ifdef RT_STRICT
1141 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1142 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1143#endif
1144 return -1;
1145}
1146
1147#ifdef IN_RING3
1148static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1149{
1150 int rc = VINF_SUCCESS;
1151 if (fLocal)
1152 {
1153 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1154 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1155 if (RT_FAILURE(rc))
1156 AssertRCReturn(rc, rc);
1157#ifdef DEBUG_CMD_BUFFER
1158 uint8_t i = 0;
1159 do
1160 {
1161 LogFunc(("corb%02x: ", i));
1162 uint8_t j = 0;
1163 do
1164 {
1165 const char *prefix;
1166 if ((i + j) == HDA_REG(pThis, CORBRP));
1167 prefix = "[R]";
1168 else if ((i + j) == HDA_REG(pThis, CORBWP));
1169 prefix = "[W]";
1170 else
1171 prefix = " "; /* three spaces */
1172 LogFunc(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
1173 j++;
1174 } while (j < 8);
1175 LogFunc(("\n"));
1176 i += 8;
1177 } while(i != 0);
1178#endif
1179 }
1180 else
1181 {
1182 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1183 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1184 if (RT_FAILURE(rc))
1185 AssertRCReturn(rc, rc);
1186#ifdef DEBUG_CMD_BUFFER
1187 uint8_t i = 0;
1188 do {
1189 LogFunc(("rirb%02x: ", i));
1190 uint8_t j = 0;
1191 do {
1192 const char *prefix;
1193 if ((i + j) == HDA_REG(pThis, RIRBWP))
1194 prefix = "[W]";
1195 else
1196 prefix = " ";
1197 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1198 } while (++j < 8);
1199 LogFunc(("\n"));
1200 i += 8;
1201 } while (i != 0);
1202#endif
1203 }
1204 return rc;
1205}
1206
1207static int hdaCORBCmdProcess(PHDASTATE pThis)
1208{
1209 int rc;
1210 uint8_t corbRp;
1211 uint8_t corbWp;
1212 uint8_t rirbWp;
1213
1214 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1215
1216 rc = hdaCmdSync(pThis, true);
1217 if (RT_FAILURE(rc))
1218 AssertRCReturn(rc, rc);
1219 corbRp = HDA_REG(pThis, CORBRP);
1220 corbWp = HDA_REG(pThis, CORBWP);
1221 rirbWp = HDA_REG(pThis, RIRBWP);
1222 Assert((corbWp != corbRp));
1223 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1224 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1225 while (corbRp != corbWp)
1226 {
1227 uint32_t cmd;
1228 uint64_t resp;
1229 pfn = NULL;
1230 corbRp++;
1231 cmd = pThis->pu32CorbBuf[corbRp];
1232
1233 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1234 HDA_CODEC_CMD(cmd, 0 /* Codec index */),
1235 &pfn);
1236 if (RT_SUCCESS(rc))
1237 {
1238 rc = pfn(pThis->pCodec,
1239 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1240 }
1241
1242 if (RT_FAILURE(rc))
1243 AssertRCReturn(rc, rc);
1244 Assert(pfn);
1245 (rirbWp)++;
1246
1247 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1248 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1249 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1250 {
1251 LogFunc(("unexpected unsolicited response.\n"));
1252 HDA_REG(pThis, CORBRP) = corbRp;
1253 return rc;
1254 }
1255 pThis->pu64RirbBuf[rirbWp] = resp;
1256 pThis->u8Counter++;
1257 if (pThis->u8Counter == RINTCNT_N(pThis))
1258 break;
1259 }
1260 HDA_REG(pThis, CORBRP) = corbRp;
1261 HDA_REG(pThis, RIRBWP) = rirbWp;
1262 rc = hdaCmdSync(pThis, false);
1263 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1264 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1265 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1266 {
1267 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1268 pThis->u8Counter = 0;
1269 rc = hdaProcessInterrupt(pThis);
1270 }
1271 if (RT_FAILURE(rc))
1272 AssertRCReturn(rc, rc);
1273 return rc;
1274}
1275#endif
1276
1277static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
1278{
1279 LogFunc(("reset of stream (%d) started\n", u8Strm));
1280 Assert(( pThis
1281 && pBdle
1282 && pStreamDesc
1283 && u8Strm <= 7));
1284 RT_BZERO(pBdle, sizeof(HDABDLEDESC));
1285 *pStreamDesc->pu32Lpib = 0;
1286 *pStreamDesc->pu32Sts = 0;
1287 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1288 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
1289 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1290
1291 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1292 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1293 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
1294 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1295 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1296 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1297 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1298 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1299 LogFunc(("reset of stream (%d) finished\n", u8Strm));
1300}
1301
1302/* Register access handlers. */
1303
1304static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1305{
1306 *pu32Value = 0;
1307 return VINF_SUCCESS;
1308}
1309
1310static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1311{
1312 return VINF_SUCCESS;
1313}
1314
1315/* U8 */
1316static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1317{
1318 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1319 return hdaRegReadU32(pThis, iReg, pu32Value);
1320}
1321
1322static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1323{
1324 Assert((u32Value & 0xffffff00) == 0);
1325 return hdaRegWriteU32(pThis, iReg, u32Value);
1326}
1327
1328/* U16 */
1329static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1330{
1331 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1332 return hdaRegReadU32(pThis, iReg, pu32Value);
1333}
1334
1335static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1336{
1337 Assert((u32Value & 0xffff0000) == 0);
1338 return hdaRegWriteU32(pThis, iReg, u32Value);
1339}
1340
1341/* U24 */
1342static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1343{
1344 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1345 return hdaRegReadU32(pThis, iReg, pu32Value);
1346}
1347
1348static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1349{
1350 Assert((u32Value & 0xff000000) == 0);
1351 return hdaRegWriteU32(pThis, iReg, u32Value);
1352}
1353
1354/* U32 */
1355static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1356{
1357 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1358
1359 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1360 return VINF_SUCCESS;
1361}
1362
1363static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1364{
1365 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1366
1367 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1368 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1369 return VINF_SUCCESS;
1370}
1371
1372static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1373{
1374 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1375 {
1376 /* exit reset state */
1377 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1378 pThis->fInReset = false;
1379 }
1380 else
1381 {
1382#ifdef IN_RING3
1383 /* enter reset state*/
1384 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1385 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1386 {
1387 LogFunc(("HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1388 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1389 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1390 }
1391 hdaReset(pThis->CTX_SUFF(pDevIns));
1392 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1393 pThis->fInReset = true;
1394#else
1395 return VINF_IOM_R3_MMIO_WRITE;
1396#endif
1397 }
1398 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1399 {
1400 /* Flush: GSTS:1 set, see 6.2.6*/
1401 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1402 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1403 }
1404 return VINF_SUCCESS;
1405}
1406
1407static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1408{
1409 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1410
1411 uint32_t v = pThis->au32Regs[iRegMem];
1412 uint32_t nv = u32Value & HDA_STATES_SCSF;
1413 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1414 return VINF_SUCCESS;
1415}
1416
1417static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1418{
1419 uint32_t v = 0;
1420 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1421 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1422 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1423 || HDA_REG(pThis, STATESTS))
1424 v |= RT_BIT(30);
1425#define HDA_IS_STREAM_EVENT(pThis, stream) \
1426 ( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1427 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1428 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1429#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
1430 MARK_STREAM(pThis, 0, v);
1431 MARK_STREAM(pThis, 1, v);
1432 MARK_STREAM(pThis, 2, v);
1433 MARK_STREAM(pThis, 3, v);
1434 MARK_STREAM(pThis, 4, v);
1435 MARK_STREAM(pThis, 5, v);
1436 MARK_STREAM(pThis, 6, v);
1437 MARK_STREAM(pThis, 7, v);
1438 v |= v ? RT_BIT(31) : 0;
1439 *pu32Value = v;
1440 return VINF_SUCCESS;
1441}
1442
1443static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1444{
1445 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1446 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1447 - pThis->u64BaseTS, 24, 1000);
1448 return VINF_SUCCESS;
1449}
1450
1451static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1452{
1453 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1454 HDA_REG(pThis, CORBRP) = 0;
1455#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1456 else
1457 return hdaRegWriteU8(pThis, iReg, u32Value);
1458#endif
1459 return VINF_SUCCESS;
1460}
1461
1462static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1463{
1464#ifdef IN_RING3
1465 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1466 AssertRC(rc);
1467 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1468 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1469 return hdaCORBCmdProcess(pThis);
1470 return rc;
1471#else
1472 return VINF_IOM_R3_MMIO_WRITE;
1473#endif
1474}
1475
1476static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1477{
1478 uint32_t v = HDA_REG(pThis, CORBSTS);
1479 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1480 return VINF_SUCCESS;
1481}
1482
1483static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1484{
1485#ifdef IN_RING3
1486 int rc;
1487 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1488 if (RT_FAILURE(rc))
1489 AssertRCReturn(rc, rc);
1490 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1491 return VINF_SUCCESS;
1492 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1493 return VINF_SUCCESS;
1494 rc = hdaCORBCmdProcess(pThis);
1495 return rc;
1496#else
1497 return VINF_IOM_R3_MMIO_WRITE;
1498#endif
1499}
1500
1501static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1502{
1503 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1504 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1505 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1506 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1507
1508 if (fInReset)
1509 {
1510 /*
1511 * Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1512 * from reset
1513 */
1514 Assert((!fReset));
1515 LogFunc(("guest initiated exit of stream reset.\n"));
1516 }
1517 else if (fReset)
1518 {
1519#ifdef IN_RING3
1520 /*
1521 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1522 */
1523 uint8_t u8Strm = 0;
1524 PHDABDLEDESC pBdle = NULL;
1525 HDASTREAMTRANSFERDESC StreamDesc;
1526 Assert((!fInRun && !fRun));
1527 switch (iReg)
1528 {
1529 case HDA_REG_SD0CTL:
1530 u8Strm = 0;
1531 pBdle = &pThis->StInBdle;
1532 break;
1533#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1534# ifdef VBOX_WITH_HDA_MIC_IN
1535 case HDA_REG_SD2CTL:
1536 u8Strm = 2;
1537 pBdle = &pThis->StMicBdle;
1538 break;
1539# endif
1540#endif
1541 case HDA_REG_SD4CTL:
1542 u8Strm = 4;
1543 pBdle = &pThis->StOutBdle;
1544 break;
1545 default:
1546 LogFunc(("changing SRST bit on non-attached stream\n"));
1547 return hdaRegWriteU24(pThis, iReg, u32Value);
1548 }
1549 LogFunc(("guest initiated enter to stream reset.\n"));
1550 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1551 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
1552#else
1553 return VINF_IOM_R3_MMIO_WRITE;
1554#endif
1555 }
1556 else
1557 {
1558#ifdef IN_RING3
1559 /* we enter here to change DMA states only */
1560 if ( (fInRun && !fRun)
1561 || (fRun && !fInRun))
1562 {
1563 Assert((!fReset && !fInReset));
1564
1565# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1566 PHDADRIVER pDrv;
1567# endif
1568 switch (iReg)
1569 {
1570 case HDA_REG_SD0CTL:
1571# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1572 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1573 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1574 pDrv->LineIn.pStrmIn, fRun);
1575# else
1576 AUD_set_active_in(pThis->pCodec->SwVoiceIn, fRun);
1577# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1578 break;
1579# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1580# ifdef VBOX_WITH_HDA_MIC_IN
1581 case HDA_REG_SD2CTL:
1582 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1583 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1584 pDrv->MicIn.pStrmIn, fRun);
1585# endif
1586# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1587 break;
1588 case HDA_REG_SD4CTL:
1589# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1590 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1591 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1592 pDrv->Out.pStrmOut, fRun);
1593# else
1594 AUD_set_active_out(pThis->pCodec->SwVoiceOut, fRun);
1595# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1596 break;
1597 default:
1598 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1599 break;
1600 }
1601 }
1602#else /* !IN_RING3 */
1603 return VINF_IOM_R3_MMIO_WRITE;
1604#endif /* IN_RING3 */
1605 }
1606
1607 return hdaRegWriteU24(pThis, iReg, u32Value);
1608}
1609
1610static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1611{
1612 uint32_t v = HDA_REG_IND(pThis, iReg);
1613 v &= ~(u32Value & v);
1614 HDA_REG_IND(pThis, iReg) = v;
1615 hdaProcessInterrupt(pThis);
1616 return VINF_SUCCESS;
1617}
1618
1619static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1620{
1621 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1622 if (RT_FAILURE(rc))
1623 AssertRCReturn(rc, VINF_SUCCESS);
1624 return rc;
1625}
1626
1627static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1628{
1629 switch (u32Value)
1630 {
1631 case HDA_SDFIFOW_8B:
1632 case HDA_SDFIFOW_16B:
1633 case HDA_SDFIFOW_32B:
1634 return hdaRegWriteU16(pThis, iReg, u32Value);
1635 default:
1636 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1637 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1638 }
1639 return VINF_SUCCESS;
1640}
1641
1642/**
1643 * @note This method could be called for changing value on Output Streams
1644 * only (ICH6 datasheet 18.2.39)
1645 */
1646static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1647{
1648 switch (iReg)
1649 {
1650 /* SDInFIFOS is RO, n=0-3 */
1651 case HDA_REG_SD0FIFOS:
1652 case HDA_REG_SD1FIFOS:
1653 case HDA_REG_SD2FIFOS:
1654 case HDA_REG_SD3FIFOS:
1655 LogFunc(("Guest tries change value of FIFO size of input stream\n"));
1656 break;
1657 case HDA_REG_SD4FIFOS:
1658 case HDA_REG_SD5FIFOS:
1659 case HDA_REG_SD6FIFOS:
1660 case HDA_REG_SD7FIFOS:
1661 switch(u32Value)
1662 {
1663 case HDA_SDONFIFO_16B:
1664 case HDA_SDONFIFO_32B:
1665 case HDA_SDONFIFO_64B:
1666 case HDA_SDONFIFO_128B:
1667 case HDA_SDONFIFO_192B:
1668 return hdaRegWriteU16(pThis, iReg, u32Value);
1669
1670 case HDA_SDONFIFO_256B:
1671 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1672 default:
1673 return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);
1674 }
1675 break;
1676 default:
1677 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
1678 }
1679
1680 return VINF_SUCCESS;
1681}
1682
1683#ifdef IN_RING3
1684#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1685static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
1686#else
1687static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pCfg)
1688#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1689{
1690 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1691
1692# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1693
1694 int rc = VINF_SUCCESS;
1695
1696 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1697 uint32_t u32HzMult = 1;
1698 uint32_t u32HzDiv = 1;
1699
1700 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
1701 {
1702 case 0: u32HzMult = 1; break;
1703 case 1: u32HzMult = 2; break;
1704 case 2: u32HzMult = 3; break;
1705 case 3: u32HzMult = 4; break;
1706 default:
1707 LogFunc(("Unsupported multiplier %x\n",
1708 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
1709 rc = VERR_NOT_SUPPORTED;
1710 break;
1711 }
1712 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
1713 {
1714 case 0: u32HzDiv = 1; break;
1715 case 1: u32HzDiv = 2; break;
1716 case 2: u32HzDiv = 3; break;
1717 case 3: u32HzDiv = 4; break;
1718 case 4: u32HzDiv = 5; break;
1719 case 5: u32HzDiv = 6; break;
1720 case 6: u32HzDiv = 7; break;
1721 case 7: u32HzDiv = 8; break;
1722 default:
1723 LogFunc(("Unsupported divisor %x\n",
1724 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
1725 rc = VERR_NOT_SUPPORTED;
1726 break;
1727 }
1728
1729#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1730 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1731#else
1732 audfmt_e enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1733#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1734
1735 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
1736 {
1737 case 0:
1738 LogFunc(("%s requested 8-bit\n", __FUNCTION__));
1739#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1740 enmFmt = AUD_FMT_S8;
1741#else
1742 enmFmt = AUD_FMT_S8;
1743#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1744 break;
1745 case 1:
1746 LogFunc(("%s requested 16-bit\n", __FUNCTION__));
1747#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1748 enmFmt = AUD_FMT_S16;
1749#else
1750 enmFmt = AUD_FMT_S16;
1751#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1752 break;
1753 case 2:
1754 LogFunc(("%s requested 20-bit\n", __FUNCTION__));
1755 break;
1756 case 3:
1757 LogFunc(("%s requested 24-bit\n", __FUNCTION__));
1758 break;
1759 case 4:
1760 LogFunc(("%s requested 32-bit\n", __FUNCTION__));
1761#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1762 enmFmt = AUD_FMT_S32;
1763#else
1764 enmFmt = AUD_FMT_S32;
1765#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1766 break;
1767 default:
1768 AssertMsgFailed(("Unsupported bits shift %x\n",
1769 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
1770 rc = VERR_NOT_SUPPORTED;
1771 break;
1772 }
1773
1774 if (RT_SUCCESS(rc))
1775 {
1776#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1777 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
1778 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
1779 pCfg->enmFormat = enmFmt;
1780 pCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
1781#else
1782 pCfg->nchannels = (u32SdFmt & 0xf) + 1;
1783 pCfg->fmt = enmFmt;
1784 pCfg->endianness = 0;
1785#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1786 }
1787
1788# undef EXTRACT_VALUE
1789
1790 return rc;
1791}
1792#endif
1793
1794static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1795{
1796#ifdef IN_RING3
1797# ifdef VBOX_WITH_HDA_CODEC_EMU
1798 /* No reason to reopen voice with same settings. */
1799 if (u32Value == HDA_REG_IND(pThis, iReg))
1800 return VINF_SUCCESS;
1801
1802 PDMAUDIOSTREAMCFG as;
1803 int rc = hdaSdFmtToAudSettings(u32Value, &as);
1804 if (RT_FAILURE(rc))
1805 return rc;
1806
1807 PHDADRIVER pDrv;
1808 switch (iReg)
1809 {
1810 case HDA_REG_SD0FMT:
1811 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1812 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &as);
1813 break;
1814#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1815# ifdef VBOX_WITH_HDA_MIC_IN
1816 case HDA_REG_SD2FMT:
1817 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1818 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &as);
1819 break;
1820# endif
1821#endif
1822 default:
1823 LogFunc(("Warning: Attempt to change format on register %d\n", iReg));
1824 break;
1825 }
1826
1827 /** @todo r=andy rc gets lost; needs fixing. */
1828 return hdaRegWriteU16(pThis, iReg, u32Value);
1829# else
1830 return hdaRegWriteU16(pThis, iReg, u32Value);
1831# endif
1832#else
1833 return VINF_IOM_R3_MMIO_WRITE;
1834#endif
1835}
1836
1837static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1838{
1839 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1840 if (RT_FAILURE(rc))
1841 AssertRCReturn(rc, VINF_SUCCESS);
1842 return rc;
1843}
1844
1845static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1846{
1847 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1848 if (RT_FAILURE(rc))
1849 AssertRCReturn(rc, VINF_SUCCESS);
1850 return rc;
1851}
1852
1853static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1854{
1855 int rc = VINF_SUCCESS;
1856 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1857 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1858 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1859 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1860
1861 rc = hdaRegReadU32(pThis, iReg, pu32Value);
1862 return rc;
1863}
1864
1865static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1866{
1867 int rc = VINF_SUCCESS;
1868
1869 /*
1870 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1871 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1872 */
1873 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1874 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
1875 {
1876#ifdef IN_RING3
1877 PFNHDACODECVERBPROCESSOR pfn = NULL;
1878 uint64_t resp;
1879 uint32_t cmd = HDA_REG(pThis, IC);
1880 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
1881 {
1882 /*
1883 * 3.4.3 defines behavior of immediate Command status register.
1884 */
1885 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
1886 return rc;
1887 }
1888 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1889 LogFunc(("IC:%x\n", cmd));
1890
1891 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1892 HDA_CODEC_CMD(cmd, 0 /* LUN */),
1893 &pfn);
1894 if (RT_FAILURE(rc))
1895 AssertRCReturn(rc, rc);
1896 rc = pfn(pThis->pCodec,
1897 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1898 if (RT_FAILURE(rc))
1899 AssertRCReturn(rc, rc);
1900
1901 HDA_REG(pThis, IR) = (uint32_t)resp;
1902 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
1903 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1904 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1905#else /* !IN_RING3 */
1906 rc = VINF_IOM_R3_MMIO_WRITE;
1907#endif
1908 return rc;
1909 }
1910 /*
1911 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1912 */
1913 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1914 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
1915 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1916 return rc;
1917}
1918
1919static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1920{
1921 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1922 {
1923 HDA_REG(pThis, RIRBWP) = 0;
1924 }
1925 /* The remaining bits are O, see 6.2.22 */
1926 return VINF_SUCCESS;
1927}
1928
1929static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1930{
1931 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1932 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1933 if (RT_FAILURE(rc))
1934 AssertRCReturn(rc, rc);
1935
1936 switch(iReg)
1937 {
1938 case HDA_REG_CORBLBASE:
1939 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
1940 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
1941 break;
1942 case HDA_REG_CORBUBASE:
1943 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
1944 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1945 break;
1946 case HDA_REG_RIRBLBASE:
1947 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
1948 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
1949 break;
1950 case HDA_REG_RIRBUBASE:
1951 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
1952 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1953 break;
1954 case HDA_REG_DPLBASE:
1955 /** @todo: first bit has special meaning */
1956 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
1957 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
1958 break;
1959 case HDA_REG_DPUBASE:
1960 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
1961 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1962 break;
1963 default:
1964 AssertMsgFailed(("Invalid index"));
1965 break;
1966 }
1967
1968 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
1969 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
1970 return rc;
1971}
1972
1973static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1974{
1975 uint8_t v = HDA_REG(pThis, RIRBSTS);
1976 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
1977
1978 return hdaProcessInterrupt(pThis);
1979}
1980
1981#ifdef IN_RING3
1982#ifdef LOG_ENABLED
1983static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1984{
1985#if 0
1986 uint64_t addr;
1987 uint32_t len;
1988 uint32_t ioc;
1989 uint8_t bdle[16];
1990 uint32_t counter;
1991 uint32_t i;
1992 uint32_t sum = 0;
1993 Assert(pBdle && pBdle->u32BdleMaxCvi);
1994 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1995 {
1996 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i*16, bdle, 16);
1997 addr = *(uint64_t *)bdle;
1998 len = *(uint32_t *)&bdle[8];
1999 ioc = *(uint32_t *)&bdle[12];
2000 LogFunc(("%s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
2001 sum += len;
2002 }
2003 LogFunc(("sum: %d\n", sum));
2004 for (i = 0; i < 8; ++i)
2005 {
2006 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
2007 LogFunc(("%s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
2008 i , counter));
2009 }
2010#endif
2011}
2012#endif
2013
2014static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2015{
2016 uint8_t bdle[16];
2017 Assert(( pStreamDesc->u64BaseDMA
2018 && pBdle
2019 && pBdle->u32BdleMaxCvi));
2020 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
2021 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
2022 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
2023 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
2024#ifdef LOG_ENABLED
2025 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2026#endif
2027}
2028
2029DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2030 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
2031{
2032 /*
2033 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
2034 */
2035 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
2036 uint32_t cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
2037 /*
2038 * we may increase the counter in range of [0, FIFOS + 1]
2039 */
2040 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
2041 Assert((u32SoundBackendBufferBytesAvail > 0));
2042
2043 /* sanity check to avoid overriding the backend audio buffer */
2044 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
2045 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
2046
2047 if (cb2Copy <= pBdle->cbUnderFifoW)
2048 return 0;
2049 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
2050 return cb2Copy;
2051}
2052
2053DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2054 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2055{
2056 LogFunc(("cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2057 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2058 Assert((cbCopied));
2059 AssertPtr(pu32DMACursor);
2060 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
2061 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
2062 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2063 * where it might happen.
2064 */
2065 AssertMsg((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy), /* we assume that we write the entire buffer including unreported bytes */
2066 ("cbCopied=%RU32 != pBdle->cbUnderFifoW=%RU32 + cbArranged2Copy=%RU32\n",
2067 cbCopied, pBdle->cbUnderFifoW, cbArranged2Copy));
2068 if ( pBdle->cbUnderFifoW
2069 && pBdle->cbUnderFifoW <= cbCopied)
2070 {
2071 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n",
2072 pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2073 }
2074
2075 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
2076 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
2077
2078 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
2079 pBdle->u32BdleCviPos += cbArranged2Copy;
2080
2081 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
2082 /* We report all bytes (including previously unreported bytes) */
2083 *pu32DMACursor += cbCopied;
2084 /* Decrease the backend counter by the number of bytes we copied to the backend */
2085 *pu32BackendBufferCapacity -= cbCopied;
2086 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2087 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
2088}
2089
2090DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2091 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2092{
2093 Assert((cbCopied, cbArranged2Copy));
2094 *pu32BackendBufferCapacity -= cbCopied;
2095 pBdle->u32BdleCviPos += cbCopied;
2096 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2097 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
2098 pBdle->cbUnderFifoW = 0;
2099 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2100 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2101}
2102
2103DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2104 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
2105{
2106 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2107 pBdle->u32BdleCviPos += cbCopied;
2108 pBdle->cbUnderFifoW += cbCopied;
2109 /* In case of a read transaction we're always copying from the backend buffer */
2110 if (pu32BackendBufferCapacity)
2111 *pu32BackendBufferCapacity -= cbCopied;
2112 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2113 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
2114}
2115
2116DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2117{
2118 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
2119 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
2120
2121 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2122
2123 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2124 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
2125 hdaUpdatePosBuf(pThis, pStreamDesc);
2126
2127 /* don't touch BdleCvi counter on uninitialized descriptor */
2128 if ( pBdle->u32BdleCviPos
2129 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
2130 {
2131 pBdle->u32BdleCviPos = 0;
2132 pBdle->u32BdleCvi++;
2133 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
2134 pBdle->u32BdleCvi = 0;
2135 }
2136 return fOnBufferEdge;
2137}
2138
2139DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2140 uint32_t cbInc)
2141{
2142 /*
2143 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
2144 * (ICH6 datasheet 18.2.38)
2145 */
2146 if (!pBdle->cbUnderFifoW)
2147 {
2148 *pStreamDesc->pu32Lpib += cbInc;
2149
2150 /*
2151 * Assert. The buffer counters should never overlap.
2152 */
2153 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2154
2155 hdaUpdatePosBuf(pThis, pStreamDesc);
2156 }
2157}
2158
2159static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2160{
2161 bool fDoNextTransferLoop = true;
2162 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
2163 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2164 {
2165 if ( !pBdle->cbUnderFifoW
2166 && pBdle->fBdleCviIoc)
2167 {
2168 /**
2169 * @todo - more carefully investigate BCIS flag.
2170 * Speech synthesis works fine on Mac Guest if this bit isn't set
2171 * but in general sound quality gets worse.
2172 */
2173 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2174
2175 /*
2176 * we should generate the interrupt if ICE bit of SDCTL register is set.
2177 */
2178 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2179 hdaProcessInterrupt(pThis);
2180 }
2181 fDoNextTransferLoop = false;
2182 }
2183 return fDoNextTransferLoop;
2184}
2185
2186#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2187/**
2188 * hdaReadAudio - copies samples from audio backend to DMA.
2189 * Note: This function writes to the DMA buffer immediately,
2190 * but "reports bytes" when all conditions are met (FIFOW).
2191 */
2192static int hdaReadAudio(PHDASTATE pThis, PAUDMIXSINK pSink,
2193 PHDASTREAMTRANSFERDESC pStreamDesc,
2194 uint32_t u32CblLimit, uint32_t *pcbAvail, uint32_t *pcbRead)
2195{
2196 PHDABDLEDESC pBdle = &pThis->StInBdle; /** @todo Add support for mic in. */
2197
2198 int rc;
2199 uint32_t cbTransferred = 0;
2200
2201 LogFlowFunc(("CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2202
2203 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2204 if (!cb2Copy)
2205 {
2206 /* If we enter here we can't report "unreported bits". */
2207 rc = VERR_NO_DATA;
2208 }
2209 else
2210 {
2211 uint32_t cbRead = 0;
2212 rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pBdle->au8HdaBuffer, cb2Copy, &cbRead);
2213 if (RT_SUCCESS(rc))
2214 {
2215 Assert(cbRead);
2216
2217 /*
2218 * Write the HDA DMA buffer.
2219 */
2220 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2221 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2222 pBdle->au8HdaBuffer, cbRead);
2223
2224 /* Don't see any reason why cb2Copy would differ from cbRead. */
2225 Assert((cbRead == cb2Copy && (*pcbAvail) >= cb2Copy)); /* sanity */
2226
2227 if (pBdle->cbUnderFifoW + cbRead > hdaFifoWToSz(pThis, 0))
2228 hdaBackendReadTransferReported(pBdle, cb2Copy, cbRead, &cbTransferred, pcbAvail);
2229 else
2230 {
2231 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbRead, pcbAvail);
2232 rc = VERR_NO_DATA;
2233 }
2234 }
2235 }
2236
2237 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2238 LogFunc(("CVI(pos:%RU32, len:%RU32), cbTransferred=%RU32, rc=%Rrc\n",
2239 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2240
2241 if (RT_SUCCESS(rc))
2242 *pcbRead = cbTransferred;
2243
2244 return rc;
2245}
2246#else
2247static int hdaReadAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc,
2248 uint32_t u32CblLimit, uint32_t *pu32Avail, uint32_t *pcbRead)
2249{
2250 PHDABDLEDESC pBdle = &pThis->StInBdle;
2251
2252 uint32_t cbTransferred = 0;
2253 uint32_t cb2Copy = 0;
2254 uint32_t cbBackendCopy = 0;
2255
2256 int rc;
2257
2258 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2259
2260 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
2261 if (!cb2Copy)
2262 {
2263 /* if we enter here we can't report "unreported bits" */
2264 rc = VINF_EOF;
2265 }
2266 else
2267 {
2268 /*
2269 * read from backend input line to the last unreported position or at the begining.
2270 */
2271 cbBackendCopy = AUD_read(pThis->pCodec->SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
2272
2273 /*
2274 * write the HDA DMA buffer
2275 */
2276 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer,
2277 cbBackendCopy);
2278
2279 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
2280 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
2281
2282 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pThis, 0))
2283 {
2284 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
2285 rc = VINF_SUCCESS;
2286 }
2287 else
2288 {
2289 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
2290 rc = VINF_EOF;
2291 }
2292 }
2293
2294 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2295 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
2296
2297 if (pcbRead)
2298 *pcbRead = cbTransferred;
2299
2300 return rc;
2301}
2302#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2303
2304static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32CblLimit,
2305 uint32_t *pcbAvail, uint32_t *pcbWritten)
2306{
2307 PHDABDLEDESC pBdle = &pThis->StOutBdle;
2308
2309 int rc = VINF_SUCCESS;
2310
2311 uint32_t cbTransferred = 0;
2312 uint32_t cbWrittenMin = 0; /* local byte counter, how many bytes copied to backend */
2313
2314 LogFunc(("CVI(cvi:%RU32, pos:%RU32, len:%RU32)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2315
2316 /* Local byte counter (on local buffer). */
2317 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2318
2319 /*
2320 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
2321 * previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
2322 */
2323 if (!cb2Copy)
2324 {
2325 rc = VINF_EOF;
2326 }
2327 else
2328 {
2329 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2330 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2331 pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
2332#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2333 STAM_COUNTER_ADD(&pThis->StatBytesRead, cb2Copy);
2334#endif
2335
2336 /*
2337 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2338 */
2339 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
2340 {
2341#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2342 uint32_t cbWritten;
2343 cbWrittenMin = UINT32_MAX;
2344
2345 PHDADRIVER pDrv;
2346 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2347 {
2348 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2349 {
2350 int rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2351 pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW,
2352 &cbWritten);
2353 if (RT_FAILURE(rc2))
2354 continue;
2355 }
2356 else /* Stream disabled, just assume all was copied. */
2357 cbWritten = cb2Copy;
2358
2359 cbWrittenMin = RT_MIN(cbWrittenMin, cbWritten);
2360 LogFlowFunc(("\tLUN#%RU8: cbWritten=%RU32, cWrittenMin=%RU32\n", pDrv->uLUN, cbWritten, cbWrittenMin));
2361 }
2362
2363 if (cbWrittenMin == UINT32_MAX)
2364 cbWrittenMin = 0;
2365#else
2366 cbWrittenMin = AUD_write (pThis->pCodec->SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
2367#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2368
2369 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbWrittenMin, &cbTransferred, pcbAvail);
2370 }
2371 else
2372 {
2373 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2374 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
2375 rc = VINF_EOF;
2376 }
2377 }
2378
2379 Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
2380 LogFunc(("CVI(pos:%RU32, len:%RU32, cbTransferred:%RU32), rc=%Rrc\n",
2381 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2382
2383 if (RT_SUCCESS(rc))
2384 *pcbWritten = cbTransferred;
2385
2386 return rc;
2387}
2388
2389/**
2390 * @interface_method_impl{HDACODEC,pfnReset}
2391 */
2392DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2393{
2394 PHDASTATE pThis = pCodec->pHDAState;
2395 NOREF(pThis);
2396 return VINF_SUCCESS;
2397}
2398
2399DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
2400 PHDASTREAMTRANSFERDESC pStreamDesc)
2401{
2402 Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
2403
2404 RT_BZERO(pStreamDesc, sizeof(HDASTREAMTRANSFERDESC));
2405 pStreamDesc->u8Strm = u8Strm;
2406 pStreamDesc->u32Ctl = HDA_STREAM_REG(pThis, CTL, u8Strm);
2407 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2408 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2409 pStreamDesc->pu32Lpib = &HDA_STREAM_REG(pThis, LPIB, u8Strm);
2410 pStreamDesc->pu32Sts = &HDA_STREAM_REG(pThis, STS, u8Strm);
2411 pStreamDesc->u32Cbl = HDA_STREAM_REG(pThis, CBL, u8Strm);
2412 pStreamDesc->u32Fifos = HDA_STREAM_REG(pThis, FIFOS, u8Strm);
2413
2414 pBdle->u32BdleMaxCvi = HDA_STREAM_REG(pThis, LVI, u8Strm);
2415
2416#ifdef LOG_ENABLED
2417 if ( pBdle
2418 && pBdle->u32BdleMaxCvi)
2419 {
2420 LogFunc(("Initialization of transfer descriptor:\n"));
2421 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2422 }
2423#endif
2424}
2425
2426static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2427{
2428 NOREF(pThis);
2429 NOREF(enmRecSource);
2430 LogFlowFuncEnter();
2431}
2432
2433static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2434{
2435 NOREF(pThis);
2436 LogFlowFuncEnter();
2437}
2438
2439#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2440static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2441 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2442 PPDMAUDIOSTREAMCFG pCfg)
2443{
2444 PAUDMIXSINK pSink;
2445
2446 switch (enmRecSource)
2447 {
2448# ifdef VBOX_WITH_HDA_MIC_IN
2449 case PDMAUDIORECSOURCE_MIC:
2450 pSink = pThis->pSinkMicIn;
2451 break;
2452# endif
2453 case PDMAUDIORECSOURCE_LINE_IN:
2454 pSink = pThis->pSinkLineIn;
2455 break;
2456 default:
2457 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2458 return VERR_NOT_SUPPORTED;
2459 }
2460
2461 int rc = VINF_SUCCESS;
2462 char *pszDesc;
2463
2464 PHDADRIVER pDrv;
2465 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2466 {
2467 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2468 {
2469 rc = VERR_NO_MEMORY;
2470 break;
2471 }
2472
2473 rc = pDrv->pConnector->pfnOpenIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2474 LogFlowFunc(("LUN#%RU8: Opened input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2475 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2476 {
2477 AudioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2478 rc = AudioMixerAddStreamIn(pSink,
2479 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2480 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2481 }
2482
2483 RTStrFree(pszDesc);
2484 }
2485
2486 LogFlowFuncLeaveRC(rc);
2487 return rc;
2488}
2489
2490static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2491 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2492{
2493 int rc = VINF_SUCCESS;
2494 char *pszDesc;
2495
2496 PHDADRIVER pDrv;
2497 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2498 {
2499 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2500 {
2501 rc = VERR_NO_MEMORY;
2502 break;
2503 }
2504
2505 rc = pDrv->pConnector->pfnOpenOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
2506 LogFlowFunc(("LUN#%RU8: Opened output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2507 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2508 {
2509 AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
2510 rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
2511 pDrv->pConnector, pDrv->Out.pStrmOut,
2512 0 /* uFlags */, &pDrv->Out.phStrmOut);
2513 }
2514
2515 RTStrFree(pszDesc);
2516 }
2517
2518 LogFlowFuncLeaveRC(rc);
2519 return rc;
2520}
2521
2522static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis, ENMSOUNDSOURCE enmSource,
2523 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2524{
2525 int rc = VINF_SUCCESS;
2526 PDMAUDIOVOLUME vol = { fMute, uVolLeft, uVolRight };
2527 PAUDMIXSINK pSink;
2528
2529 /* Convert the audio source to corresponding sink. */
2530 switch (enmSource) {
2531 case PO_INDEX:
2532 pSink = pThis->pSinkOutput;
2533 break;
2534 case PI_INDEX:
2535 pSink = pThis->pSinkLineIn;
2536 break;
2537 case MC_INDEX:
2538 pSink = pThis->pSinkMicIn;
2539 break;
2540 default:
2541 AssertFailedReturn(VERR_INVALID_PARAMETER);
2542 }
2543
2544 /* Set the volume. Codec already converted it to the correct range. */
2545 AudioMixerSetSinkVolume(pSink, &vol);
2546
2547 LogFlowFuncLeaveRC(rc);
2548 return rc;
2549}
2550#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2551
2552#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2553static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2554{
2555 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2556 AssertPtr(pThis);
2557
2558 STAM_PROFILE_START(&pThis->StatTimer, a);
2559
2560 int rc = VINF_SUCCESS;
2561
2562 uint32_t cbInMax = 0;
2563 uint32_t cbOutMin = UINT32_MAX;
2564
2565 PHDADRIVER pDrv;
2566
2567 uint32_t cbIn, cbOut, cSamplesLive;
2568 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2569 {
2570 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2571 &cbIn, &cbOut, &cSamplesLive);
2572 if (RT_SUCCESS(rc))
2573 {
2574#ifdef DEBUG_TIMER
2575 LogFlowFunc(("\tLUN#%RU8: [1] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2576#endif
2577 if (cSamplesLive)
2578 {
2579 uint32_t cSamplesPlayed;
2580 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2581 if (RT_SUCCESS(rc2))
2582 LogFlowFunc(("LUN#%RU8: cSamplesLive=%RU32, cSamplesPlayed=%RU32\n",
2583 pDrv->uLUN, cSamplesLive, cSamplesPlayed));
2584
2585 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2586 &cbIn, &cbOut, &cSamplesLive);
2587#ifdef DEBUG_TIMER
2588 if (RT_SUCCESS(rc))
2589 LogFlowFunc(("\tLUN#%RU8: [2] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2590#endif
2591 }
2592
2593 cbInMax = RT_MAX(cbInMax, cbIn);
2594 cbOutMin = RT_MIN(cbOutMin, cbOut);
2595 }
2596 }
2597
2598#ifdef DEBUG_TIMER
2599 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
2600#endif
2601
2602 if (cbOutMin == UINT32_MAX)
2603 cbOutMin = 0;
2604
2605 /*
2606 * Playback.
2607 */
2608 if (cbOutMin)
2609 {
2610 Assert(cbOutMin != UINT32_MAX);
2611 hdaTransfer(pThis, PO_INDEX, cbOutMin); /** @todo Add rc! */
2612 }
2613
2614 /*
2615 * Recording.
2616 */
2617 if (cbInMax)
2618 hdaTransfer(pThis, PI_INDEX, cbInMax); /** @todo Add rc! */
2619
2620 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
2621
2622 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2623}
2624
2625static DECLCALLBACK(int) hdaTransfer(PHDASTATE pThis,
2626 ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2627{
2628 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2629
2630 LogFlowFunc(("pThis=%p, cbAvail=%RU32\n", pThis, cbAvail));
2631#else
2632static DECLCALLBACK(int) hdaTransfer(PHDACODEC pCodec, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2633{
2634 AssertPtrReturn(pCodec, VERR_INVALID_POINTER);
2635 PHDASTATE pThis = pCodec->pHDAState;
2636 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2637#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2638
2639 uint8_t u8Strm;
2640 PHDABDLEDESC pBdle;
2641
2642 switch (enmSrc)
2643 {
2644 case PI_INDEX:
2645 {
2646 u8Strm = 0;
2647 pBdle = &pThis->StInBdle;
2648 break;
2649 }
2650
2651#ifdef VBOX_WITH_HDA_MIC_IN
2652 case MC_INDEX:
2653 {
2654 u8Strm = 2;
2655 pBdle = &pThis->StMicBdle;
2656 break;
2657 }
2658#endif
2659 case PO_INDEX:
2660 {
2661 u8Strm = 4;
2662 pBdle = &pThis->StOutBdle;
2663 break;
2664 }
2665
2666 default:
2667 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
2668 return VERR_NOT_SUPPORTED;
2669 }
2670
2671 HDASTREAMTRANSFERDESC StreamDesc;
2672 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2673
2674 int rc = VINF_EOF;
2675 while (cbAvail)
2676 {
2677 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
2678 && cbAvail
2679 && StreamDesc.u64BaseDMA);
2680
2681 /* Fetch the Buffer Descriptor Entry (BDE). */
2682 if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
2683 hdaFetchBdle(pThis, pBdle, &StreamDesc);
2684
2685 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2686 Assert((StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib))); /* sanity */
2687 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
2688 Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
2689
2690 LogFunc(("CBL=%RU32, LPIB=%RU32\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
2691
2692#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2693 PAUDMIXSINK pSink;
2694#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2695 uint32_t cbWritten = 0;
2696 switch (enmSrc)
2697 {
2698 case PI_INDEX:
2699#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2700 pSink = pThis->pSinkLineIn;
2701 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2702#else
2703 rc = hdaReadAudio(pThis, &StreamDesc, u32CblLimit, (uint32_t *)&cbAvail, &cbWritten);
2704#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2705 break;
2706 case PO_INDEX:
2707 rc = hdaWriteAudio(pThis, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2708 break;
2709#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2710# ifdef VBOX_WITH_HDA_MIC_IN
2711 case MC_INDEX:
2712 pSink = pThis->pSinkMicIn;
2713 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2714 break;
2715# endif
2716#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2717 default:
2718 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
2719 rc = VERR_NOT_SUPPORTED;
2720 break;
2721 }
2722 Assert(cbWritten <= StreamDesc.u32Fifos + 1);
2723 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2724
2725 /* Process end of buffer condition. */
2726 hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cbWritten);
2727
2728 if (!hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc))
2729 break;
2730
2731 if ( RT_FAILURE(rc)
2732 || rc == VINF_EOF) /* All data processed? */
2733 {
2734 break;
2735 }
2736 }
2737
2738 return rc;
2739}
2740#endif /* IN_RING3 */
2741
2742/* MMIO callbacks */
2743
2744/**
2745 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
2746 *
2747 * @note During implementation, we discovered so-called "forgotten" or "hole"
2748 * registers whose description is not listed in the RPM, datasheet, or
2749 * spec.
2750 */
2751PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2752{
2753 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2754 int rc;
2755
2756 /*
2757 * Look up and log.
2758 */
2759 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2760 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
2761#ifdef LOG_ENABLED
2762 unsigned const cbLog = cb;
2763 uint32_t offRegLog = offReg;
2764#endif
2765
2766 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
2767#define NEW_READ_CODE
2768#ifdef NEW_READ_CODE
2769 Assert(cb == 4); Assert((offReg & 3) == 0);
2770
2771 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2772 LogFunc(("access to registers except GCTL is blocked while reset\n"));
2773
2774 if (idxRegDsc == -1)
2775 LogRel(("Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
2776
2777 if (idxRegDsc != -1)
2778 {
2779 /* ASSUMES gapless DWORD at end of map. */
2780 if (g_aHdaRegMap[idxRegDsc].size == 4)
2781 {
2782 /*
2783 * Straight forward DWORD access.
2784 */
2785 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
2786 LogFunc(("read %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
2787 }
2788 else
2789 {
2790 /*
2791 * Multi register read (unless there are trailing gaps).
2792 * ASSUMES that only DWORD reads have sideeffects.
2793 */
2794 uint32_t u32Value = 0;
2795 unsigned cbLeft = 4;
2796 do
2797 {
2798 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
2799 uint32_t u32Tmp = 0;
2800
2801 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
2802 LogFunc(("read %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
2803 if (rc != VINF_SUCCESS)
2804 break;
2805 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
2806
2807 cbLeft -= cbReg;
2808 offReg += cbReg;
2809 idxRegDsc++;
2810 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
2811
2812 if (rc == VINF_SUCCESS)
2813 *(uint32_t *)pv = u32Value;
2814 else
2815 Assert(!IOM_SUCCESS(rc));
2816 }
2817 }
2818 else
2819 {
2820 rc = VINF_IOM_MMIO_UNUSED_FF;
2821 LogFunc(("hole at %x is accessed for read\n", offReg));
2822 }
2823#else
2824 if (idxRegDsc != -1)
2825 {
2826 /** @todo r=bird: Accesses crossing register boundraries aren't handled
2827 * right from what I can tell? If they are, please explain
2828 * what the rules are. */
2829 uint32_t mask = 0;
2830 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2831 uint32_t u32Value = 0;
2832 switch(cb)
2833 {
2834 case 1: mask = 0x000000ff; break;
2835 case 2: mask = 0x0000ffff; break;
2836 case 4:
2837 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2838 case 8:
2839 mask = 0xffffffff;
2840 cb = 4;
2841 break;
2842 }
2843#if 0
2844 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
2845 */
2846 //Assert((cb <= g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset)));
2847 if (cb > g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset))
2848 {
2849 int off = cb - (g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset));
2850 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2851 if (RT_FAILURE(rc))
2852 AssertRCReturn (rc, rc);
2853 }
2854 //Assert(((offReg - g_aHdaRegMap[idxRegDsc].offset) == 0));
2855#endif
2856 mask <<= shift;
2857 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Value);
2858 *(uint32_t *)pv |= (u32Value & mask);
2859 LogFunc(("read %s[%x/%x]\n", g_aHdaRegMap[idxRegDsc].abbrev, u32Value, *(uint32_t *)pv));
2860 }
2861 else
2862 {
2863 *(uint32_t *)pv = 0xFF;
2864 LogFunc(("hole at %x is accessed for read\n", offReg));
2865 rc = VINF_SUCCESS;
2866 }
2867#endif
2868
2869 /*
2870 * Log the outcome.
2871 */
2872#ifdef LOG_ENABLED
2873 if (cbLog == 4)
2874 LogFunc(("@%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
2875 else if (cbLog == 2)
2876 LogFunc(("@%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
2877 else if (cbLog == 1)
2878 LogFunc(("@%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
2879#endif
2880 return rc;
2881}
2882
2883
2884DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
2885{
2886 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2887 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
2888
2889 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2890#ifdef LOG_ENABLED
2891 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
2892#endif
2893 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
2894 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
2895 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
2896 return rc;
2897}
2898
2899
2900/**
2901 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
2902 */
2903PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2904{
2905 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2906 int rc;
2907
2908 /*
2909 * The behavior of accesses that aren't aligned on natural boundraries is
2910 * undefined. Just reject them outright.
2911 */
2912 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
2913 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
2914 if (GCPhysAddr & (cb - 1))
2915 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
2916
2917 /*
2918 * Look up and log the access.
2919 */
2920 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2921 int idxRegDsc = hdaRegLookup(pThis, offReg);
2922 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
2923 uint64_t u64Value;
2924 if (cb == 4) u64Value = *(uint32_t const *)pv;
2925 else if (cb == 2) u64Value = *(uint16_t const *)pv;
2926 else if (cb == 1) u64Value = *(uint8_t const *)pv;
2927 else if (cb == 8) u64Value = *(uint64_t const *)pv;
2928 else
2929 {
2930 u64Value = 0; /* shut up gcc. */
2931 AssertReleaseMsgFailed(("%d\n", cb));
2932 }
2933
2934#ifdef LOG_ENABLED
2935 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
2936 uint32_t const offRegLog = offReg;
2937 int const idxRegLog = idxRegMem;
2938 if (idxRegDsc == -1)
2939 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
2940 else if (cb == 4)
2941 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2942 else if (cb == 2)
2943 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2944 else if (cb == 1)
2945 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2946 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
2947 LogFunc(("size=%d != cb=%d!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
2948#endif
2949
2950#define NEW_WRITE_CODE
2951#ifdef NEW_WRITE_CODE
2952 /*
2953 * Try for a direct hit first.
2954 */
2955 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
2956 {
2957 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
2958 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2959 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2960 }
2961 /*
2962 * Partial or multiple register access, loop thru the requested memory.
2963 */
2964 else
2965 {
2966 /* If it's an access beyond the start of the register, shift the input
2967 value and fill in missing bits. Natural alignment rules means we
2968 will only see 1 or 2 byte accesses of this kind, so no risk of
2969 shifting out input values. */
2970 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
2971 {
2972 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
2973 offReg -= cbBefore;
2974 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2975 u64Value <<= cbBefore * 8;
2976 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
2977 LogFunc(("Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
2978 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
2979 }
2980
2981 /* Loop thru the write area, it may cover multiple registers. */
2982 rc = VINF_SUCCESS;
2983 for (;;)
2984 {
2985 uint32_t cbReg;
2986 if (idxRegDsc != -1)
2987 {
2988 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2989 cbReg = g_aHdaRegMap[idxRegDsc].size;
2990 if (cb < cbReg)
2991 {
2992 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
2993 LogFunc(("Supplying missing bits (%#x): %#llx -> %#llx ...\n",
2994 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
2995 }
2996 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
2997 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
2998 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldVal,
2999 pThis->au32Regs[idxRegMem]));
3000 }
3001 else
3002 {
3003 LogRel(("HDA: Invalid write access @0x%x!\n", offReg));
3004 cbReg = 1;
3005 }
3006 if (rc != VINF_SUCCESS)
3007 break;
3008 if (cbReg >= cb)
3009 break;
3010
3011 /* advance */
3012 offReg += cbReg;
3013 cb -= cbReg;
3014 u64Value >>= cbReg * 8;
3015 if (idxRegDsc == -1)
3016 idxRegDsc = hdaRegLookup(pThis, offReg);
3017 else
3018 {
3019 idxRegDsc++;
3020 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3021 || g_aHdaRegMap[idxRegDsc].offset != offReg)
3022 idxRegDsc = -1;
3023 }
3024 }
3025 }
3026#else
3027 if (idxRegDsc != -1)
3028 {
3029 /** @todo r=bird: This looks like code for handling unaligned register
3030 * accesses. If it isn't, then add a comment explaining what you're
3031 * trying to do here. OTOH, if it is then it has the following
3032 * issues:
3033 * -# You're calculating the wrong new value for the register.
3034 * -# You're not handling cross register accesses. Imagine a
3035 * 4-byte write starting at CORBCTL, or a 8-byte write.
3036 *
3037 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
3038 * nobody seems to be using it and it just adds complexity when reading
3039 * the code.
3040 *
3041 */
3042 uint32_t u32CurValue = pThis->au32Regs[idxRegMem];
3043 uint32_t u32NewValue;
3044 uint32_t mask;
3045 switch (cb)
3046 {
3047 case 1:
3048 u32NewValue = *(uint8_t const *)pv;
3049 mask = 0xff;
3050 break;
3051 case 2:
3052 u32NewValue = *(uint16_t const *)pv;
3053 mask = 0xffff;
3054 break;
3055 case 4:
3056 case 8:
3057 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
3058 u32NewValue = *(uint32_t const *)pv;
3059 mask = 0xffffffff;
3060 cb = 4;
3061 break;
3062 default:
3063 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
3064 }
3065 /* cross-register access, see corresponding comment in hdaMMIORead */
3066 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
3067 mask <<= shift;
3068 u32NewValue <<= shift;
3069 u32NewValue &= mask;
3070 u32NewValue |= (u32CurValue & ~mask);
3071
3072 rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32NewValue);
3073 LogFunc(("write %s:(%x) %x => %x\n", g_aHdaRegMap[idxRegDsc].abbrev, u32NewValue,
3074 u32CurValue, pThis->au32Regs[idxRegMem]));
3075 }
3076 else
3077 rc = VINF_SUCCESS;
3078
3079 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
3080 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
3081#endif
3082 return rc;
3083}
3084
3085
3086/* PCI callback. */
3087
3088#ifdef IN_RING3
3089/**
3090 * @callback_method_impl{FNPCIIOREGIONMAP}
3091 */
3092static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
3093 PCIADDRESSSPACE enmType)
3094{
3095 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3096 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3097 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3098 int rc;
3099
3100 /*
3101 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3102 *
3103 * Let IOM talk DWORDs when reading, saves a lot of complications. On
3104 * writing though, we have to do it all ourselves because of sideeffects.
3105 */
3106 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3107 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
3108#ifdef NEW_READ_CODE
3109 IOMMMIO_FLAGS_READ_DWORD |
3110#else
3111 IOMMMIO_FLAGS_READ_PASSTHRU |
3112#endif
3113 IOMMMIO_FLAGS_WRITE_PASSTHRU,
3114 hdaMMIOWrite, hdaMMIORead, "HDA");
3115
3116 if (RT_FAILURE(rc))
3117 return rc;
3118
3119 if (pThis->fR0Enabled)
3120 {
3121 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
3122 "hdaMMIOWrite", "hdaMMIORead");
3123 if (RT_FAILURE(rc))
3124 return rc;
3125 }
3126
3127 if (pThis->fRCEnabled)
3128 {
3129 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
3130 "hdaMMIOWrite", "hdaMMIORead");
3131 if (RT_FAILURE(rc))
3132 return rc;
3133 }
3134
3135 pThis->MMIOBaseAddr = GCPhysAddress;
3136 return VINF_SUCCESS;
3137}
3138
3139
3140/* Saved state callbacks. */
3141
3142/**
3143 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3144 */
3145static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3146{
3147 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3148
3149 /* Save Codec nodes states */
3150 hdaCodecSaveState(pThis->pCodec, pSSM);
3151
3152 /* Save MMIO registers */
3153 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3154 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3155 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3156
3157 /* Save HDA dma counters */
3158 SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3159 SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3160 SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3161 return VINF_SUCCESS;
3162}
3163
3164
3165/**
3166 * @callback_method_impl{FNSSMDEVLOADEXEC}
3167 */
3168static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3169{
3170 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3171
3172 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3173
3174 /*
3175 * Load Codec nodes states.
3176 */
3177 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3178 if (RT_FAILURE(rc))
3179 return rc;
3180
3181 /*
3182 * Load MMIO registers.
3183 */
3184 uint32_t cRegs;
3185 switch (uVersion)
3186 {
3187 case HDA_SSM_VERSION_1:
3188 /* Starting with r71199, we would save 112 instead of 113
3189 registers due to some code cleanups. This only affected trunk
3190 builds in the 4.1 development period. */
3191 cRegs = 113;
3192 if (SSMR3HandleRevision(pSSM) >= 71199)
3193 {
3194 uint32_t uVer = SSMR3HandleVersion(pSSM);
3195 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3196 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3197 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3198 cRegs = 112;
3199 }
3200 break;
3201
3202 case HDA_SSM_VERSION_2:
3203 case HDA_SSM_VERSION_3:
3204 cRegs = 112;
3205 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3206 break;
3207
3208 case HDA_SSM_VERSION:
3209 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3210 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3211 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3212 break;
3213
3214 default:
3215 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3216 }
3217
3218 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3219 {
3220 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3221 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3222 }
3223 else
3224 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3225
3226 /*
3227 * Load HDA DMA counters.
3228 */
3229 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
3230 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
3231 rc = SSMR3GetStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), fFlags, paFields, NULL);
3232 AssertRCReturn(rc, rc);
3233 rc = SSMR3GetStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), fFlags, paFields, NULL);
3234 AssertRCReturn(rc, rc);
3235 rc = SSMR3GetStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), fFlags, paFields, NULL);
3236 AssertRCReturn(rc, rc);
3237
3238 /*
3239 * Update stuff after the state changes.
3240 */
3241 bool fEnableIn = RT_BOOL(SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3242#ifdef VBOX_WITH_HDA_MIC_IN
3243 bool fEnableMicIn = RT_BOOL(SDCTL(pThis, 2) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3244#else
3245 bool fEnableMicIn = fEnableIn; /* Mic In == Line In */
3246#endif
3247 bool fEnableOut = RT_BOOL(SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3248
3249#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3250 PHDADRIVER pDrv;
3251 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3252 {
3253 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, fEnableIn);
3254 if (RT_FAILURE(rc))
3255 break;
3256 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, fEnableMicIn);
3257 if (RT_FAILURE(rc))
3258 break;
3259 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, fEnableOut);
3260 if (RT_FAILURE(rc))
3261 break;
3262 }
3263#else
3264 AUD_set_active_in(pThis->pCodec->SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3265 AUD_set_active_out(pThis->pCodec->SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3266#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3267
3268 if (RT_SUCCESS(rc))
3269 {
3270 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3271 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3272 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3273 }
3274
3275 LogFlowFuncLeaveRC(rc);
3276 return rc;
3277}
3278
3279
3280/* Debug and log type formatters. */
3281
3282/**
3283 * @callback_method_impl{FNRTSTRFORMATTYPE}
3284 */
3285static DECLCALLBACK(size_t)
3286hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3287 const char *pszType, void const *pvValue,
3288 int cchWidth, int cchPrecision, unsigned fFlags,
3289 void *pvUser)
3290{
3291 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
3292 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3293 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
3294 sdCtl,
3295 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> HDA_SDCTL_NUM_SHIFT,
3296 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
3297 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3298 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3299 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3300 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3301 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3302 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3303}
3304
3305/**
3306 * @callback_method_impl{FNRTSTRFORMATTYPE}
3307 */
3308static DECLCALLBACK(size_t)
3309hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3310 const char *pszType, void const *pvValue,
3311 int cchWidth, int cchPrecision, unsigned fFlags,
3312 void *pvUser)
3313{
3314 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3315 uint32_t cb;
3316 switch (uSdFifos)
3317 {
3318 case HDA_SDONFIFO_16B: cb = 16; break;
3319 case HDA_SDONFIFO_32B: cb = 32; break;
3320 case HDA_SDONFIFO_64B: cb = 64; break;
3321 case HDA_SDONFIFO_128B: cb = 128; break;
3322 case HDA_SDONFIFO_192B: cb = 192; break;
3323 case HDA_SDONFIFO_256B: cb = 256; break;
3324 case HDA_SDINFIFO_120B: cb = 120; break;
3325 case HDA_SDINFIFO_160B: cb = 160; break;
3326 default: cb = 0; break;
3327 }
3328 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
3329}
3330
3331/**
3332 * @callback_method_impl{FNRTSTRFORMATTYPE}
3333 */
3334static DECLCALLBACK(size_t)
3335hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3336 const char *pszType, void const *pvValue,
3337 int cchWidth, int cchPrecision, unsigned fFlags,
3338 void *pvUser)
3339{
3340 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3341 uint32_t cb;
3342 switch (uSdFifos)
3343 {
3344 case HDA_SDFIFOW_8B: cb = 8; break;
3345 case HDA_SDFIFOW_16B: cb = 16; break;
3346 case HDA_SDFIFOW_32B: cb = 32; break;
3347 default: cb = 0; break;
3348 }
3349 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
3350}
3351
3352/**
3353 * @callback_method_impl{FNRTSTRFORMATTYPE}
3354 */
3355static DECLCALLBACK(size_t)
3356hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3357 const char *pszType, void const *pvValue,
3358 int cchWidth, int cchPrecision, unsigned fFlags,
3359 void *pvUser)
3360{
3361 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3362 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3363 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3364 uSdSts,
3365 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3366 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3367 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3368 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3369}
3370
3371
3372static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3373{
3374 int iReg = 0;
3375 for (; iReg < HDA_NREGS; ++iReg)
3376 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3377 return iReg;
3378 return -1;
3379}
3380
3381
3382static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
3383{
3384 Assert( pThis
3385 && iHdaIndex >= 0
3386 && iHdaIndex < HDA_NREGS);
3387 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
3388}
3389
3390
3391/**
3392 * @callback_method_impl{FNDBGFHANDLERDEV}
3393 */
3394static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3395{
3396 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3397 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
3398 if (iHdaRegisterIndex != -1)
3399 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3400 else
3401 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
3402 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3403}
3404
3405
3406static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
3407{
3408 Assert( pThis
3409 && iHdaStrmIndex >= 0
3410 && iHdaStrmIndex < 7);
3411 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
3412 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
3413 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
3414 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
3415 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
3416}
3417
3418
3419static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
3420{
3421 /* todo: add args parsing */
3422 return -1;
3423}
3424
3425
3426/**
3427 * @callback_method_impl{FNDBGFHANDLERDEV}
3428 */
3429static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3430{
3431 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3432 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
3433 if (iHdaStrmIndex != -1)
3434 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3435 else
3436 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
3437 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3438}
3439
3440
3441/**
3442 * @callback_method_impl{FNDBGFHANDLERDEV}
3443 */
3444static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3445{
3446 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3447
3448 if (pThis->pCodec->pfnCodecDbgListNodes)
3449 pThis->pCodec->pfnCodecDbgListNodes(pThis->pCodec, pHlp, pszArgs);
3450 else
3451 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3452}
3453
3454
3455/**
3456 * @callback_method_impl{FNDBGFHANDLERDEV}
3457 */
3458static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3459{
3460 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3461
3462 if (pThis->pCodec->pfnCodecDbgSelector)
3463 pThis->pCodec->pfnCodecDbgSelector(pThis->pCodec, pHlp, pszArgs);
3464 else
3465 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3466}
3467
3468
3469/* PDMIBASE */
3470
3471/**
3472 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3473 */
3474static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3475{
3476 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
3477 Assert(&pThis->IBase == pInterface);
3478
3479 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3480 return NULL;
3481}
3482
3483
3484/* PDMDEVREG */
3485
3486/**
3487 * Reset notification.
3488 *
3489 * @returns VBox status.
3490 * @param pDevIns The device instance data.
3491 *
3492 * @remark The original sources didn't install a reset handler, but it seems to
3493 * make sense to me so we'll do it.
3494 */
3495static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
3496{
3497 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3498 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
3499 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3500 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3501 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3502 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3503 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
3504 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
3505 HDA_REG(pThis, CORBRP) = 0x0;
3506 HDA_REG(pThis, RIRBWP) = 0x0;
3507
3508 LogFunc(("Resetting ...\n"));
3509
3510#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3511 /* Stop any audio currently playing. */
3512 PHDADRIVER pDrv;
3513 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3514 {
3515 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
3516 /* Ignore rc. */
3517 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
3518 /* Ditto. */
3519 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
3520 /* Ditto. */
3521 }
3522#else
3523 AUD_set_active_in(pThis->pCodec->SwVoiceIn, false);
3524 AUD_set_active_out(pThis->pCodec->SwVoiceOut, false);
3525#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3526
3527 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
3528
3529 if (pThis->pu32CorbBuf)
3530 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3531 else
3532 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3533
3534 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
3535 if (pThis->pu64RirbBuf)
3536 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3537 else
3538 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3539
3540 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
3541
3542 HDABDLEDESC StEmptyBdle;
3543 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
3544 {
3545 HDASTREAMTRANSFERDESC StreamDesc;
3546 PHDABDLEDESC pBdle = NULL;
3547 if (u8Strm == 0)
3548 pBdle = &pThis->StInBdle;
3549# ifdef VBOX_WITH_HDA_MIC_IN
3550 else if (u8Strm == 2)
3551 pBdle = &pThis->StMicBdle;
3552# endif
3553 else if(u8Strm == 4)
3554 pBdle = &pThis->StOutBdle;
3555 else
3556 {
3557 RT_ZERO(StEmptyBdle);
3558 pBdle = &StEmptyBdle;
3559 }
3560 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
3561 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
3562 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
3563 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
3564 }
3565
3566 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3567 HDA_REG(pThis, STATESTS) = 0x1;
3568
3569 LogRel(("HDA: Reset\n"));
3570}
3571
3572/**
3573 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3574 */
3575static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
3576{
3577 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3578
3579#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3580 PHDADRIVER pDrv;
3581 while (!RTListIsEmpty(&pThis->lstDrv))
3582 {
3583 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
3584
3585 RTListNodeRemove(&pDrv->Node);
3586 RTMemFree(pDrv);
3587 }
3588
3589 if (pThis->pMixer)
3590 {
3591 AudioMixerDestroy(pThis->pMixer);
3592 pThis->pMixer = NULL;
3593 }
3594#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3595
3596 if (pThis->pCodec)
3597 {
3598 int rc = hdaCodecDestruct(pThis->pCodec);
3599 AssertRC(rc);
3600
3601 RTMemFree(pThis->pCodec);
3602 pThis->pCodec = NULL;
3603 }
3604
3605 RTMemFree(pThis->pu32CorbBuf);
3606 pThis->pu32CorbBuf = NULL;
3607
3608 RTMemFree(pThis->pu64RirbBuf);
3609 pThis->pu64RirbBuf = NULL;
3610
3611 return VINF_SUCCESS;
3612}
3613
3614#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3615/**
3616 * Attach command.
3617 *
3618 * This is called to let the device attach to a driver for a specified LUN
3619 * during runtime. This is not called during VM construction, the device
3620 * constructor have to attach to all the available drivers.
3621 *
3622 * @returns VBox status code.
3623 * @param pDevIns The device instance.
3624 * @param uLUN The logical unit which is being detached.
3625 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3626 */
3627static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
3628{
3629 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3630
3631 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3632 ("HDA device does not support hotplugging\n"),
3633 VERR_INVALID_PARAMETER);
3634
3635 /*
3636 * Attach driver.
3637 */
3638 char *pszDesc = NULL;
3639 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
3640 AssertMsgReturn(pszDesc,
3641 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
3642 VERR_NO_MEMORY);
3643
3644 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
3645 &pThis->IBase, &pThis->pDrvBase, pszDesc);
3646 if (RT_SUCCESS(rc))
3647 {
3648 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
3649 if (pDrv)
3650 {
3651 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
3652 AssertMsg(pDrv->pConnector != NULL,
3653 ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n",
3654 uLUN, rc));
3655 pDrv->pHDAState = pThis;
3656 pDrv->uLUN = uLUN;
3657
3658 /*
3659 * For now we always set the driver at LUN 0 as our primary
3660 * host backend. This might change in the future.
3661 */
3662 if (pDrv->uLUN == 0)
3663 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
3664
3665 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
3666
3667 /* Attach to driver list. */
3668 RTListAppend(&pThis->lstDrv, &pDrv->Node);
3669 }
3670 else
3671 rc = VERR_NO_MEMORY;
3672 }
3673 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
3674 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
3675 {
3676 LogFunc(("No attached driver for LUN #%u\n", uLUN));
3677 }
3678 else if (RT_FAILURE(rc))
3679 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
3680 uLUN, pszDesc, rc));
3681
3682 RTStrFree(pszDesc);
3683
3684 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
3685 return rc;
3686}
3687
3688static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3689{
3690 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
3691
3692 LogFlowFuncEnter();
3693}
3694#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3695
3696/**
3697 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3698 */
3699static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
3700{
3701 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3702 Assert(iInstance == 0);
3703 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3704
3705 /*
3706 * Validations.
3707 */
3708 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
3709 "RCEnabled\0"))
3710 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3711 N_ ("Invalid configuration for the Intel HDA device"));
3712
3713 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
3714 if (RT_FAILURE(rc))
3715 return PDMDEV_SET_ERROR(pDevIns, rc,
3716 N_("HDA configuration error: failed to read RCEnabled as boolean"));
3717 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
3718 if (RT_FAILURE(rc))
3719 return PDMDEV_SET_ERROR(pDevIns, rc,
3720 N_("HDA configuration error: failed to read R0Enabled as boolean"));
3721
3722 /*
3723 * Initialize data (most of it anyway).
3724 */
3725 pThis->pDevInsR3 = pDevIns;
3726 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3727 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3728 /* IBase */
3729 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
3730
3731 /* PCI Device */
3732 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
3733 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
3734
3735 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
3736 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
3737 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
3738 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
3739 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
3740 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
3741 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
3742 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
3743 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
3744 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
3745 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
3746
3747#if defined(HDA_AS_PCI_EXPRESS)
3748 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
3749#elif defined(VBOX_WITH_MSI_DEVICES)
3750 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
3751#else
3752 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
3753#endif
3754
3755 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
3756 /// of these values needs to be properly documented!
3757 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
3758 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
3759
3760 /* Power Management */
3761 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
3762 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
3763 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
3764
3765#ifdef HDA_AS_PCI_EXPRESS
3766 /* PCI Express */
3767 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
3768 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
3769 /* Device flags */
3770 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
3771 /* version */ 0x1 |
3772 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
3773 /* MSI */ (100) << 9 );
3774 /* Device capabilities */
3775 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
3776 /* Device control */
3777 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
3778 /* Device status */
3779 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
3780 /* Link caps */
3781 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
3782 /* Link control */
3783 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
3784 /* Link status */
3785 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
3786 /* Slot capabilities */
3787 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
3788 /* Slot control */
3789 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
3790 /* Slot status */
3791 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
3792 /* Root control */
3793 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
3794 /* Root capabilities */
3795 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
3796 /* Root status */
3797 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
3798 /* Device capabilities 2 */
3799 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
3800 /* Device control 2 */
3801 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
3802 /* Link control 2 */
3803 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
3804 /* Slot control 2 */
3805 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
3806#endif
3807
3808 /*
3809 * Register the PCI device.
3810 */
3811 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
3812 if (RT_FAILURE(rc))
3813 return rc;
3814
3815 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
3816 if (RT_FAILURE(rc))
3817 return rc;
3818
3819#ifdef VBOX_WITH_MSI_DEVICES
3820 PDMMSIREG MsiReg;
3821 RT_ZERO(MsiReg);
3822 MsiReg.cMsiVectors = 1;
3823 MsiReg.iMsiCapOffset = 0x60;
3824 MsiReg.iMsiNextOffset = 0x50;
3825 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3826 if (RT_FAILURE(rc))
3827 {
3828 /* That's OK, we can work without MSI */
3829 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
3830 }
3831#endif
3832
3833 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
3834 if (RT_FAILURE(rc))
3835 return rc;
3836
3837#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3838 RTListInit(&pThis->lstDrv);
3839
3840 uint8_t uLUN;
3841 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
3842 {
3843 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
3844 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
3845 if (RT_FAILURE(rc))
3846 {
3847 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3848 rc = VINF_SUCCESS;
3849
3850 break;
3851 }
3852
3853 uLUN++;
3854 }
3855
3856 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3857
3858 if (RT_SUCCESS(rc))
3859 {
3860 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
3861 if (RT_SUCCESS(rc))
3862 {
3863 /* Set a default audio format for our mixer. */
3864 PDMAUDIOSTREAMCFG streamCfg;
3865 streamCfg.uHz = 41000;
3866 streamCfg.cChannels = 2;
3867 streamCfg.enmFormat = AUD_FMT_S16;
3868 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
3869
3870 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
3871 AssertRC(rc);
3872
3873 /* Add all required audio sinks. */
3874 rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output",
3875 AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
3876 AssertRC(rc);
3877
3878 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In",
3879 AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
3880 AssertRC(rc);
3881
3882 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
3883 AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
3884 AssertRC(rc);
3885
3886 /* There is no master volume control. Set the master to max. */
3887 PDMAUDIOVOLUME vol = { false, 255, 255 };
3888 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
3889 AssertRC(rc);
3890 }
3891 }
3892
3893 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3894#else
3895 /*
3896 * Attach driver.
3897 */
3898 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Audio Driver Port");
3899 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3900 Log(("hda: No attached driver!\n"));
3901 else if (RT_FAILURE(rc))
3902 {
3903 AssertMsgFailed(("Failed to attach Intel HDA LUN #0! rc=%Rrc\n", rc));
3904 return rc;
3905 }
3906#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3907
3908 if (RT_SUCCESS(rc))
3909 {
3910 /* Construct codec. */
3911 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
3912 if (!pThis->pCodec)
3913 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
3914
3915#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3916 /* Audio driver callbacks for multiplexing. */
3917 pThis->pCodec->pfnCloseIn = hdaCloseIn;
3918 pThis->pCodec->pfnCloseOut = hdaCloseOut;
3919 pThis->pCodec->pfnOpenIn = hdaOpenIn;
3920 pThis->pCodec->pfnOpenOut = hdaOpenOut;
3921 pThis->pCodec->pfnSetVolume = hdaSetVolume;
3922#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3923
3924 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
3925
3926 /* Construct the codec. */
3927 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
3928 if (RT_FAILURE(rc))
3929 AssertRCReturn(rc, rc);
3930
3931 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
3932 verb F20 should provide device/codec recognition. */
3933 Assert(pThis->pCodec->u16VendorId);
3934 Assert(pThis->pCodec->u16DeviceId);
3935 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
3936 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
3937
3938#ifndef VBOX_WITH_PDM_AUDIO_DRIVER
3939 pThis->pCodec->pfnTransfer = hdaTransfer;
3940#endif
3941 pThis->pCodec->pfnReset = hdaCodecReset;
3942 }
3943
3944 if (RT_SUCCESS(rc))
3945 {
3946 hdaReset(pDevIns);
3947
3948 /*
3949 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
3950 * hdaReset shouldn't affects these registers.
3951 */
3952 HDA_REG(pThis, WAKEEN) = 0x0;
3953 HDA_REG(pThis, STATESTS) = 0x0;
3954
3955 /*
3956 * Debug and string formatter types.
3957 */
3958 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
3959 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
3960 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
3961 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
3962
3963 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
3964 AssertRC(rc);
3965 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
3966 AssertRC(rc);
3967 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
3968 AssertRC(rc);
3969 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
3970 AssertRC(rc);
3971 #if 0
3972 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
3973 AssertRC(rc);
3974 #endif
3975
3976 /*
3977 * Some debug assertions.
3978 */
3979 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
3980 {
3981 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
3982 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
3983
3984 /* binary search order. */
3985 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
3986 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3987 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3988
3989 /* alignment. */
3990 AssertReleaseMsg( pReg->size == 1
3991 || (pReg->size == 2 && (pReg->offset & 1) == 0)
3992 || (pReg->size == 3 && (pReg->offset & 3) == 0)
3993 || (pReg->size == 4 && (pReg->offset & 3) == 0),
3994 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3995
3996 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
3997 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
3998 if (pReg->offset & 3)
3999 {
4000 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
4001 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4002 if (pPrevReg)
4003 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
4004 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4005 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
4006 }
4007 #if 0
4008 if ((pReg->offset + pReg->size) & 3)
4009 {
4010 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4011 if (pNextReg)
4012 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
4013 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4014 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4015 }
4016 #endif
4017
4018 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
4019 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
4020 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4021 }
4022 }
4023
4024#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
4025 if (RT_SUCCESS(rc))
4026 {
4027 /* Start the emulation timer. */
4028 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
4029 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
4030 AssertRCReturn(rc, rc);
4031
4032 if (RT_SUCCESS(rc))
4033 {
4034 /** @todo Investigate why sounds is getting corrupted if the "ticks" value is too
4035 * low, e.g. "PDMDevHlpTMTimeVirtGetFreq / 200". */
4036 pThis->uTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 500; /** @todo Make this configurable! */
4037 if (pThis->uTicks < 100)
4038 pThis->uTicks = 100;
4039 LogFunc(("Timer ticks=%RU64\n", pThis->uTicks));
4040
4041 /* Fire off timer. */
4042 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
4043 }
4044 }
4045
4046# ifdef VBOX_WITH_STATISTICS
4047 if (RT_SUCCESS(rc))
4048 {
4049 /*
4050 * Register statistics.
4051 */
4052 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
4053 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
4054 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
4055 }
4056# endif
4057
4058#endif
4059
4060 LogFlowFuncLeaveRC(rc);
4061 return rc;
4062}
4063
4064/**
4065 * The device registration structure.
4066 */
4067const PDMDEVREG g_DeviceICH6_HDA =
4068{
4069 /* u32Version */
4070 PDM_DEVREG_VERSION,
4071 /* szName */
4072 "hda",
4073 /* szRCMod */
4074 "VBoxDDGC.gc",
4075 /* szR0Mod */
4076 "VBoxDDR0.r0",
4077 /* pszDescription */
4078 "Intel HD Audio Controller",
4079 /* fFlags */
4080 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
4081 /* fClass */
4082 PDM_DEVREG_CLASS_AUDIO,
4083 /* cMaxInstances */
4084 1,
4085 /* cbInstance */
4086 sizeof(HDASTATE),
4087 /* pfnConstruct */
4088 hdaConstruct,
4089 /* pfnDestruct */
4090 hdaDestruct,
4091 /* pfnRelocate */
4092 NULL,
4093 /* pfnMemSetup */
4094 NULL,
4095 /* pfnPowerOn */
4096 NULL,
4097 /* pfnReset */
4098 hdaReset,
4099 /* pfnSuspend */
4100 NULL,
4101 /* pfnResume */
4102 NULL,
4103 /* pfnAttach */
4104 NULL,
4105 /* pfnDetach */
4106 NULL,
4107 /* pfnQueryInterface. */
4108 NULL,
4109 /* pfnInitComplete */
4110 NULL,
4111 /* pfnPowerOff */
4112 NULL,
4113 /* pfnSoftReset */
4114 NULL,
4115 /* u32VersionEnd */
4116 PDM_DEVREG_VERSION
4117};
4118
4119#endif /* IN_RING3 */
4120#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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