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source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 61648

Last change on this file since 61648 was 61609, checked in by vboxsync, 9 years ago

Audio: Update.
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1/* $Id: DevIchHda.cpp 61609 2016-06-09 10:22:39Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2016 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/file.h>
36#include <iprt/list.h>
37#ifdef IN_RING3
38# include <iprt/mem.h>
39# include <iprt/semaphore.h>
40# include <iprt/string.h>
41# include <iprt/uuid.h>
42#endif
43
44#include "VBoxDD.h"
45
46#include "AudioMixBuffer.h"
47#include "AudioMixer.h"
48#include "DevIchHdaCodec.h"
49#include "DevIchHdaCommon.h"
50#include "DrvAudio.h"
51
52
53/*********************************************************************************************************************************
54* Defined Constants And Macros *
55*********************************************************************************************************************************/
56//#define HDA_AS_PCI_EXPRESS
57#define VBOX_WITH_INTEL_HDA
58
59#ifdef DEBUG_andy
60/*
61 * HDA_DEBUG_DUMP_PCM_DATA enables dumping the raw PCM data
62 * to a file on the host. Be sure to adjust HDA_DEBUG_DUMP_PCM_DATA_PATH
63 * to your needs before using this!
64 */
65# define HDA_DEBUG_DUMP_PCM_DATA
66# ifdef RT_OS_WINDOWS
67# define HDA_DEBUG_DUMP_PCM_DATA_PATH "c:\\temp\\"
68# else
69# define HDA_DEBUG_DUMP_PCM_DATA_PATH "/tmp/"
70# endif
71
72/* Enables experimental support for separate mic-in handling.
73 Do not enable this yet for regular builds, as this needs more testing first! */
74//# define VBOX_WITH_HDA_MIC_IN
75#endif
76
77#if defined(VBOX_WITH_HP_HDA)
78/* HP Pavilion dv4t-1300 */
79# define HDA_PCI_VENDOR_ID 0x103c
80# define HDA_PCI_DEVICE_ID 0x30f7
81#elif defined(VBOX_WITH_INTEL_HDA)
82/* Intel HDA controller */
83# define HDA_PCI_VENDOR_ID 0x8086
84# define HDA_PCI_DEVICE_ID 0x2668
85#elif defined(VBOX_WITH_NVIDIA_HDA)
86/* nVidia HDA controller */
87# define HDA_PCI_VENDOR_ID 0x10de
88# define HDA_PCI_DEVICE_ID 0x0ac0
89#else
90# error "Please specify your HDA device vendor/device IDs"
91#endif
92
93/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
94 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
95 * is read only except for bit 15 like the HDA spec states.
96 *
97 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
98 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
99#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
100
101/* Make sure that interleaving streams support is enabled if the 5.1 code is being used. */
102#if defined (VBOX_WITH_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT)
103# define VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
104#endif
105
106/**
107 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
108 * Bidirectional streams are currently *not* supported.
109 *
110 * Note: When changing any of those values, be prepared for some saved state
111 * fixups / trouble!
112 */
113#define HDA_MAX_SDI 4
114#define HDA_MAX_SDO 4
115#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
116AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
117
118/** Number of general registers. */
119#define HDA_NUM_GENERAL_REGS 34
120/** Number of total registers in the HDA's register map. */
121#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
122/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
123#define HDA_MAX_TAGS 16
124
125/**
126 * NB: Register values stored in memory (au32Regs[]) are indexed through
127 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
128 * register descriptors in g_aHdaRegMap[] are indexed through the
129 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
130 *
131 * The au32Regs[] layout is kept unchanged for saved state
132 * compatibility.
133 */
134
135/* Registers */
136#define HDA_REG_IND_NAME(x) HDA_REG_##x
137#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
138#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
139#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
140#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
141#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
142#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
143#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
144
145
146#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
147#define HDA_RMX_GCAP 0
148/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
149 * oss (15:12) - number of output streams supported
150 * iss (11:8) - number of input streams supported
151 * bss (7:3) - number of bidirectional streams supported
152 * bds (2:1) - number of serial data out (SDO) signals supported
153 * b64sup (0) - 64 bit addressing supported.
154 */
155#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
156 ( (((oss) & 0xF) << 12) \
157 | (((iss) & 0xF) << 8) \
158 | (((bss) & 0x1F) << 3) \
159 | (((bds) & 0x3) << 1) \
160 | ((b64sup) & 1))
161
162#define HDA_REG_VMIN 1 /* 0x02 */
163#define HDA_RMX_VMIN 1
164
165#define HDA_REG_VMAJ 2 /* 0x03 */
166#define HDA_RMX_VMAJ 2
167
168#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
169#define HDA_RMX_OUTPAY 3
170
171#define HDA_REG_INPAY 4 /* 0x06-0x07 */
172#define HDA_RMX_INPAY 4
173
174#define HDA_REG_GCTL 5 /* 0x08-0x0B */
175#define HDA_RMX_GCTL 5
176#define HDA_GCTL_RST_SHIFT 0
177#define HDA_GCTL_FSH_SHIFT 1
178#define HDA_GCTL_UR_SHIFT 8
179
180#define HDA_REG_WAKEEN 6 /* 0x0C */
181#define HDA_RMX_WAKEEN 6
182
183#define HDA_REG_STATESTS 7 /* 0x0E */
184#define HDA_RMX_STATESTS 7
185#define HDA_STATES_SCSF 0x7
186
187#define HDA_REG_GSTS 8 /* 0x10-0x11*/
188#define HDA_RMX_GSTS 8
189#define HDA_GSTS_FSH_SHIFT 1
190
191#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
192#define HDA_RMX_OUTSTRMPAY 112
193
194#define HDA_REG_INSTRMPAY 10 /* 0x1a */
195#define HDA_RMX_INSTRMPAY 113
196
197#define HDA_REG_INTCTL 11 /* 0x20 */
198#define HDA_RMX_INTCTL 9
199#define HDA_INTCTL_GIE_SHIFT 31
200#define HDA_INTCTL_CIE_SHIFT 30
201#define HDA_INTCTL_S0_SHIFT 0
202#define HDA_INTCTL_S1_SHIFT 1
203#define HDA_INTCTL_S2_SHIFT 2
204#define HDA_INTCTL_S3_SHIFT 3
205#define HDA_INTCTL_S4_SHIFT 4
206#define HDA_INTCTL_S5_SHIFT 5
207#define HDA_INTCTL_S6_SHIFT 6
208#define HDA_INTCTL_S7_SHIFT 7
209#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
210
211#define HDA_REG_INTSTS 12 /* 0x24 */
212#define HDA_RMX_INTSTS 10
213#define HDA_INTSTS_GIS_SHIFT 31
214#define HDA_INTSTS_CIS_SHIFT 30
215#define HDA_INTSTS_S0_SHIFT 0
216#define HDA_INTSTS_S1_SHIFT 1
217#define HDA_INTSTS_S2_SHIFT 2
218#define HDA_INTSTS_S3_SHIFT 3
219#define HDA_INTSTS_S4_SHIFT 4
220#define HDA_INTSTS_S5_SHIFT 5
221#define HDA_INTSTS_S6_SHIFT 6
222#define HDA_INTSTS_S7_SHIFT 7
223#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
224
225#define HDA_REG_WALCLK 13 /* 0x30 */
226#define HDA_RMX_WALCLK /* Not defined! */
227
228/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
229 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
230 * the datasheet.
231 */
232#define HDA_REG_SSYNC 14 /* 0x38 */
233#define HDA_RMX_SSYNC 12
234
235#define HDA_REG_CORBLBASE 15 /* 0x40 */
236#define HDA_RMX_CORBLBASE 13
237
238#define HDA_REG_CORBUBASE 16 /* 0x44 */
239#define HDA_RMX_CORBUBASE 14
240
241#define HDA_REG_CORBWP 17 /* 0x48 */
242#define HDA_RMX_CORBWP 15
243
244#define HDA_REG_CORBRP 18 /* 0x4A */
245#define HDA_RMX_CORBRP 16
246#define HDA_CORBRP_RST_SHIFT 15
247#define HDA_CORBRP_WP_SHIFT 0
248#define HDA_CORBRP_WP_MASK 0xFF
249
250#define HDA_REG_CORBCTL 19 /* 0x4C */
251#define HDA_RMX_CORBCTL 17
252#define HDA_CORBCTL_DMA_SHIFT 1
253#define HDA_CORBCTL_CMEIE_SHIFT 0
254
255#define HDA_REG_CORBSTS 20 /* 0x4D */
256#define HDA_RMX_CORBSTS 18
257#define HDA_CORBSTS_CMEI_SHIFT 0
258
259#define HDA_REG_CORBSIZE 21 /* 0x4E */
260#define HDA_RMX_CORBSIZE 19
261#define HDA_CORBSIZE_SZ_CAP 0xF0
262#define HDA_CORBSIZE_SZ 0x3
263/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
264
265#define HDA_REG_RIRBLBASE 22 /* 0x50 */
266#define HDA_RMX_RIRBLBASE 20
267
268#define HDA_REG_RIRBUBASE 23 /* 0x54 */
269#define HDA_RMX_RIRBUBASE 21
270
271#define HDA_REG_RIRBWP 24 /* 0x58 */
272#define HDA_RMX_RIRBWP 22
273#define HDA_RIRBWP_RST_SHIFT 15
274#define HDA_RIRBWP_WP_MASK 0xFF
275
276#define HDA_REG_RINTCNT 25 /* 0x5A */
277#define HDA_RMX_RINTCNT 23
278#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
279
280#define HDA_REG_RIRBCTL 26 /* 0x5C */
281#define HDA_RMX_RIRBCTL 24
282#define HDA_RIRBCTL_RIC_SHIFT 0
283#define HDA_RIRBCTL_DMA_SHIFT 1
284#define HDA_ROI_DMA_SHIFT 2
285
286#define HDA_REG_RIRBSTS 27 /* 0x5D */
287#define HDA_RMX_RIRBSTS 25
288#define HDA_RIRBSTS_RINTFL_SHIFT 0
289#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
290
291#define HDA_REG_RIRBSIZE 28 /* 0x5E */
292#define HDA_RMX_RIRBSIZE 26
293#define HDA_RIRBSIZE_SZ_CAP 0xF0
294#define HDA_RIRBSIZE_SZ 0x3
295
296#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
297#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
298
299
300#define HDA_REG_IC 29 /* 0x60 */
301#define HDA_RMX_IC 27
302
303#define HDA_REG_IR 30 /* 0x64 */
304#define HDA_RMX_IR 28
305
306#define HDA_REG_IRS 31 /* 0x68 */
307#define HDA_RMX_IRS 29
308#define HDA_IRS_ICB_SHIFT 0
309#define HDA_IRS_IRV_SHIFT 1
310
311#define HDA_REG_DPLBASE 32 /* 0x70 */
312#define HDA_RMX_DPLBASE 30
313#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
314
315#define HDA_REG_DPUBASE 33 /* 0x74 */
316#define HDA_RMX_DPUBASE 31
317#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
318
319#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
320
321#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
322#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
323/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
324#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
325
326#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
327
328/** @todo Condense marcos! */
329
330#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80 */
331#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
332#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
333#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
334#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
335#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
336#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
337#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
338#define HDA_RMX_SD0CTL 32
339#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
340#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
341#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
342#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
343#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
344#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
345#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
346
347#define SD(func, num) SD##num##func
348
349#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
350#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
351#define HDA_SDCTL_NUM_MASK 0xF
352#define HDA_SDCTL_NUM_SHIFT 20
353#define HDA_SDCTL_DIR_SHIFT 19
354#define HDA_SDCTL_TP_SHIFT 18
355#define HDA_SDCTL_STRIPE_MASK 0x3
356#define HDA_SDCTL_STRIPE_SHIFT 16
357#define HDA_SDCTL_DEIE_SHIFT 4
358#define HDA_SDCTL_FEIE_SHIFT 3
359#define HDA_SDCTL_ICE_SHIFT 2
360#define HDA_SDCTL_RUN_SHIFT 1
361#define HDA_SDCTL_SRST_SHIFT 0
362
363#define HDA_REG_SD0STS 35 /* 0x83 */
364#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
365#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
366#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
367#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
368#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
369#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
370#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
371#define HDA_RMX_SD0STS 33
372#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
373#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
374#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
375#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
376#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
377#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
378#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
379
380#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
381#define HDA_SDSTS_FIFORDY_SHIFT 5
382#define HDA_SDSTS_DE_SHIFT 4
383#define HDA_SDSTS_FE_SHIFT 3
384#define HDA_SDSTS_BCIS_SHIFT 2
385
386#define HDA_REG_SD0LPIB 36 /* 0x84 */
387#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
388#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
389#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
390#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
391#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
392#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
393#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
394#define HDA_RMX_SD0LPIB 34
395#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
396#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
397#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
398#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
399#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
400#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
401#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
402
403#define HDA_REG_SD0CBL 37 /* 0x88 */
404#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
405#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
406#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
407#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
408#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
409#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
410#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
411#define HDA_RMX_SD0CBL 35
412#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
413#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
414#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
415#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
416#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
417#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
418#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
419
420#define HDA_REG_SD0LVI 38 /* 0x8C */
421#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
422#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
423#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
424#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
425#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
426#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
427#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
428#define HDA_RMX_SD0LVI 36
429#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
430#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
431#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
432#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
433#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
434#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
435#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
436
437#define HDA_REG_SD0FIFOW 39 /* 0x8E */
438#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
439#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
440#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
441#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
442#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
443#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
444#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
445#define HDA_RMX_SD0FIFOW 37
446#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
447#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
448#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
449#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
450#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
451#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
452#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
453
454/*
455 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
456 */
457#define HDA_SDFIFOW_8B 0x2
458#define HDA_SDFIFOW_16B 0x3
459#define HDA_SDFIFOW_32B 0x4
460
461#define HDA_REG_SD0FIFOS 40 /* 0x90 */
462#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
463#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
464#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
465#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
466#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
467#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
468#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
469#define HDA_RMX_SD0FIFOS 38
470#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
471#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
472#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
473#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
474#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
475#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
476#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
477
478/*
479 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
480 * formula: size - 1
481 * Other values not listed are not supported.
482 */
483#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
484#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
485
486#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
487#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
488#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
489#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
490#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
491#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
492#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
493
494#define HDA_REG_SD0FMT 41 /* 0x92 */
495#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
496#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
497#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
498#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
499#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
500#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
501#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
502#define HDA_RMX_SD0FMT 39
503#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
504#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
505#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
506#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
507#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
508#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
509#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
510
511#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
512#define HDA_SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
513#define HDA_SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
514#define HDA_SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
515
516#define HDA_REG_SD0BDPL 42 /* 0x98 */
517#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
518#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
519#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
520#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
521#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
522#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
523#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
524#define HDA_RMX_SD0BDPL 40
525#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
526#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
527#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
528#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
529#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
530#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
531#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
532
533#define HDA_REG_SD0BDPU 43 /* 0x9C */
534#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
535#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
536#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
537#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
538#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
539#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
540#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
541#define HDA_RMX_SD0BDPU 41
542#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
543#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
544#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
545#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
546#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
547#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
548#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
549
550#define HDA_CODEC_CAD_SHIFT 28
551/* Encodes the (required) LUN into a codec command. */
552#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
553
554
555
556/*********************************************************************************************************************************
557* Structures and Typedefs *
558*********************************************************************************************************************************/
559
560/**
561 * Internal state of a Buffer Descriptor List Entry (BDLE),
562 * needed to keep track of the data needed for the actual device
563 * emulation.
564 */
565typedef struct HDABDLESTATE
566{
567 /** Own index within the BDL (Buffer Descriptor List). */
568 uint32_t u32BDLIndex;
569 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
570 * Used to check if we need fill up the FIFO again. */
571 uint32_t cbBelowFIFOW;
572 /** The buffer descriptor's internal DMA buffer. */
573 uint8_t au8FIFO[HDA_SDOFIFO_256B + 1];
574 /** Current offset in DMA buffer (in bytes).*/
575 uint32_t u32BufOff;
576 uint32_t Padding;
577} HDABDLESTATE, *PHDABDLESTATE;
578
579/**
580 * Buffer Descriptor List Entry (BDLE) (3.6.3).
581 *
582 * Contains only register values which do *not* change until a
583 * stream reset occurs.
584 */
585typedef struct HDABDLE
586{
587 /** Starting address of the actual buffer. Must be 128-bit aligned. */
588 uint64_t u64BufAdr;
589 /** Size of the actual buffer (in bytes). */
590 uint32_t u32BufSize;
591 /** Interrupt on completion; the controller will generate
592 * an interrupt when the last byte of the buffer has been
593 * fetched by the DMA engine. */
594 bool fIntOnCompletion;
595 /** Internal state of this BDLE.
596 * Not part of the actual BDLE registers. */
597 HDABDLESTATE State;
598} HDABDLE, *PHDABDLE;
599
600/**
601 * Structure for keeping an audio stream data mapping.
602 */
603typedef struct HDASTREAMMAPPING
604{
605 /** The stream's layout. */
606 PDMAUDIOSTREAMLAYOUT enmLayout;
607 /** Number of audio channels in this stream. */
608 uint8_t cChannels;
609 /** Array audio channels. */
610 R3PTRTYPE(PPDMAUDIOSTREAMCHANNEL) paChannels;
611 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
612} HDASTREAMMAPPING, *PHDASTREAMMAPPING;
613
614/**
615 * Internal state of a HDA stream.
616 */
617typedef struct HDASTREAMSTATE
618{
619 /** Current BDLE to use. Wraps around to 0 if
620 * maximum (cBDLE) is reached. */
621 uint16_t uCurBDLE;
622 /** Stop indicator. */
623 volatile bool fDoStop;
624 /** Flag indicating whether this stream is in an
625 * active (operative) state or not. */
626 volatile bool fActive;
627 /** Flag indicating whether this stream currently is
628 * in reset mode and therefore not acccessible by the guest. */
629 volatile bool fInReset;
630 /** Unused, padding. */
631 bool fPadding;
632 /** Mutex semaphore handle to serialize access. */
633 RTSEMMUTEX hMtx;
634 /** Event signalling that the stream's state has been changed. */
635 RTSEMEVENT hStateChangedEvent;
636 /** This stream's data mapping. */
637 HDASTREAMMAPPING Mapping;
638 /** Current BDLE (Buffer Descriptor List Entry). */
639 HDABDLE BDLE;
640} HDASTREAMSTATE, *PHDASTREAMSTATE;
641
642/**
643 * Structure defining an HDA mixer sink.
644 * Its purpose is to know which audio mixer sink is bound to
645 * which SDn (SDI/SDO) device stream.
646 *
647 * This is needed in order to handle interleaved streams
648 * (that is, multiple channels in one stream) or non-interleaved
649 * streams (each channel has a dedicated stream).
650 *
651 * This is only known to the actual device emulation level.
652 */
653typedef struct HDAMIXERSINK
654{
655 /** SDn ID this sink is assigned to. 0 if not assigned. */
656 uint8_t uSD;
657 /** Channel ID of SDn ID. Only valid if SDn ID is valid. */
658 uint8_t uChannel;
659 uint8_t Padding[3];
660 /** Pointer to the actual audio mixer sink. */
661 R3PTRTYPE(PAUDMIXSINK) pMixSink;
662} HDAMIXERSINK, *PHDAMIXERSINK;
663
664/**
665 * Structure for keeping a HDA stream state.
666 *
667 * Contains only register values which do *not* change until a
668 * stream reset occurs.
669 */
670typedef struct HDASTREAM
671{
672 /** Stream descriptor number (SDn). */
673 uint8_t u8SD;
674 uint8_t Padding0[7];
675 /** DMA base address (SDnBDPU - SDnBDPL). */
676 uint64_t u64BDLBase;
677 /** Cyclic Buffer Length (SDnCBL).
678 * Represents the size of the ring buffer. */
679 uint32_t u32CBL;
680 /** Format (SDnFMT). */
681 uint16_t u16FMT;
682 /** FIFO Size (FIFOS).
683 * Maximum number of bytes that may have been DMA'd into
684 * memory but not yet transmitted on the link.
685 *
686 * Must be a power of two. */
687 uint16_t u16FIFOS;
688 /** Last Valid Index (SDnLVI). */
689 uint16_t u16LVI;
690 uint16_t Padding1[3];
691 /** Pointer to HDA sink this stream is attached to. */
692 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
693 /** Internal state of this stream. */
694 HDASTREAMSTATE State;
695} HDASTREAM, *PHDASTREAM;
696
697/**
698 * Structure for mapping a stream tag to an HDA stream.
699 */
700typedef struct HDATAG
701{
702 /** Own stream tag. */
703 uint8_t uTag;
704 uint8_t Padding[7];
705 /** Pointer to associated stream. */
706 R3PTRTYPE(PHDASTREAM) pStrm;
707} HDATAG, *PHDATAG;
708
709/**
710 * Structure defining an HDA mixer stream.
711 * This is being used together with an audio mixer instance.
712 */
713typedef struct HDAMIXERSTREAM
714{
715 union
716 {
717 /** Desired playback destination (for an output stream). */
718 PDMAUDIOPLAYBACKDEST Dest;
719 /** Desired recording source (for an input stream). */
720 PDMAUDIORECSOURCE Source;
721 } DestSource;
722 uint8_t Padding1[4];
723 /** Associated mixer handle. */
724 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
725} HDAMIXERSTREAM, *PHDAMIXERSTREAM;
726
727/**
728 * Struct for maintaining a host backend driver.
729 * This driver must be associated to one, and only one,
730 * HDA codec. The HDA controller does the actual multiplexing
731 * of HDA codec data to various host backend drivers then.
732 *
733 * This HDA device uses a timer in order to synchronize all
734 * read/write accesses across all attached LUNs / backends.
735 */
736typedef struct HDADRIVER
737{
738 /** Node for storing this driver in our device driver list of HDASTATE. */
739 RTLISTNODER3 Node;
740 /** Pointer to HDA controller (state). */
741 R3PTRTYPE(PHDASTATE) pHDAState;
742 /** Driver flags. */
743 PDMAUDIODRVFLAGS Flags;
744 uint8_t u32Padding0[2];
745 /** LUN to which this driver has been assigned. */
746 uint8_t uLUN;
747 /** Whether this driver is in an attached state or not. */
748 bool fAttached;
749 /** Pointer to attached driver base interface. */
750 R3PTRTYPE(PPDMIBASE) pDrvBase;
751 /** Audio connector interface to the underlying host backend. */
752 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
753 /** Mixer stream for line input. */
754 HDAMIXERSTREAM LineIn;
755#ifdef VBOX_WITH_HDA_MIC_IN
756 /** Mixer stream for mic input. */
757 HDAMIXERSTREAM MicIn;
758#endif
759 /** Mixer stream for front output. */
760 HDAMIXERSTREAM Front;
761#ifdef VBOX_WITH_HDA_51_SURROUND
762 /** Mixer stream for center/LFE output. */
763 HDAMIXERSTREAM CenterLFE;
764 /** Mixer stream for rear output. */
765 HDAMIXERSTREAM Rear;
766#endif
767} HDADRIVER;
768
769/**
770 * ICH Intel HD Audio Controller state.
771 */
772typedef struct HDASTATE
773{
774 /** The PCI device structure. */
775 PCIDevice PciDev;
776 /** R3 Pointer to the device instance. */
777 PPDMDEVINSR3 pDevInsR3;
778 /** R0 Pointer to the device instance. */
779 PPDMDEVINSR0 pDevInsR0;
780 /** R0 Pointer to the device instance. */
781 PPDMDEVINSRC pDevInsRC;
782 /** Padding for alignment. */
783 uint32_t u32Padding;
784 /** The base interface for LUN\#0. */
785 PDMIBASE IBase;
786 RTGCPHYS MMIOBaseAddr;
787 /** The HDA's register set. */
788 uint32_t au32Regs[HDA_NUM_REGS];
789 /** Internal stream states. */
790 HDASTREAM aStreams[HDA_MAX_STREAMS];
791 /** Mapping table between stream tags and stream states. */
792 HDATAG aTags[HDA_MAX_TAGS];
793 /** CORB buffer base address. */
794 uint64_t u64CORBBase;
795 /** RIRB buffer base address. */
796 uint64_t u64RIRBBase;
797 /** DMA base address.
798 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
799 uint64_t u64DPBase;
800 /** DMA position buffer enable bit. */
801 bool fDMAPosition;
802 /** Padding for alignment. */
803 uint8_t u8Padding0[7];
804 /** Pointer to CORB buffer. */
805 R3PTRTYPE(uint32_t *) pu32CorbBuf;
806 /** Size in bytes of CORB buffer. */
807 uint32_t cbCorbBuf;
808 /** Padding for alignment. */
809 uint32_t u32Padding1;
810 /** Pointer to RIRB buffer. */
811 R3PTRTYPE(uint64_t *) pu64RirbBuf;
812 /** Size in bytes of RIRB buffer. */
813 uint32_t cbRirbBuf;
814 /** Indicates if HDA controller is in reset mode. */
815 bool fInReset;
816 /** Flag whether the R0 part is enabled. */
817 bool fR0Enabled;
818 /** Flag whether the RC part is enabled. */
819 bool fRCEnabled;
820 /** Number of active (running) SDn streams. */
821 uint8_t cStreamsActive;
822#ifndef VBOX_WITH_AUDIO_CALLBACKS
823 /** The timer for pumping data thru the attached LUN drivers. */
824 PTMTIMERR3 pTimer;
825 /** Flag indicating whether the timer is active or not. */
826 bool fTimerActive;
827 uint8_t u8Padding1[7];
828 /** Timer ticks per Hz. */
829 uint64_t cTimerTicks;
830 /** Timestamp of the last timer callback (hdaTimer).
831 * Used to calculate the time actually elapsed between two timer callbacks. */
832 uint64_t uTimerTS;
833#endif
834#ifdef VBOX_WITH_STATISTICS
835# ifndef VBOX_WITH_AUDIO_CALLBACKS
836 STAMPROFILE StatTimer;
837# endif
838 STAMCOUNTER StatBytesRead;
839 STAMCOUNTER StatBytesWritten;
840#endif
841 /** Pointer to HDA codec to use. */
842 R3PTRTYPE(PHDACODEC) pCodec;
843 /** List of associated LUN drivers (HDADRIVER). */
844 RTLISTANCHORR3 lstDrv;
845 /** The device' software mixer. */
846 R3PTRTYPE(PAUDIOMIXER) pMixer;
847 /** HDA sink for (front) output. */
848 HDAMIXERSINK SinkFront;
849#ifdef VBOX_WITH_HDA_51_SURROUND
850 /** HDA sink for center / LFE output. */
851 HDAMIXERSINK SinkCenterLFE;
852 /** HDA sink for rear output. */
853 HDAMIXERSINK SinkRear;
854#endif
855 /** HDA mixer sink for line input. */
856 HDAMIXERSINK SinkLineIn;
857#ifdef VBOX_WITH_HDA_MIC_IN
858 /** Audio mixer sink for microphone input. */
859 HDAMIXERSINK SinkMicIn;
860#endif
861 uint64_t u64BaseTS;
862 /** Response Interrupt Count (RINTCNT). */
863 uint8_t u8RespIntCnt;
864 /** Padding for alignment. */
865 uint8_t au8Padding2[7];
866} HDASTATE;
867/** Pointer to the ICH Intel HD Audio Controller state. */
868typedef HDASTATE *PHDASTATE;
869
870#ifdef VBOX_WITH_AUDIO_CALLBACKS
871typedef struct HDACALLBACKCTX
872{
873 PHDASTATE pThis;
874 PHDADRIVER pDriver;
875} HDACALLBACKCTX, *PHDACALLBACKCTX;
876#endif
877
878/*********************************************************************************************************************************
879* Internal Functions *
880*********************************************************************************************************************************/
881#ifndef VBOX_DEVICE_STRUCT_TESTCASE
882static FNPDMDEVRESET hdaReset;
883
884/*
885 * Stubs.
886 */
887static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
888static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
889
890/*
891 * Global register set read/write functions.
892 */
893static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
894static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
895static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
896static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
897static int hdaRegReadSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
898static int hdaRegWriteSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
899static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
900static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
901static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
902static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
903static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
904static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
905static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
906static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
907static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
908static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
909static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
910
911/*
912 * {IOB}SDn read/write functions.
913 */
914static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
915static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
916static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
917static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
918static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
919static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
920static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
921static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
922static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
923DECLINLINE(int) hdaRegWriteSDLock(PHDASTATE pThis, PHDASTREAM pStream, uint32_t iReg, uint32_t u32Value);
924DECLINLINE(void) hdaRegWriteSDUnlock(PHDASTREAM pStream);
925
926/*
927 * Generic register read/write functions.
928 */
929static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
930static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
931static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
932static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
933static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
934static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
935static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
936static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
937
938#ifdef IN_RING3
939static void hdaStreamDestroy(PHDASTREAM pStream);
940static int hdaStreamSetActive(PHDASTATE pThis, PHDASTREAM pStream, bool fActive);
941static int hdaStreamStart(PHDASTREAM pStream);
942static int hdaStreamStop(PHDASTREAM pStream);
943static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout);
944static int hdaTransfer(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToProcess, uint32_t *pcbProcessed);
945#endif
946
947#ifdef IN_RING3
948static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg);
949static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping);
950static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping);
951#endif
952
953#ifdef IN_RING3
954static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
955DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB);
956# ifdef LOG_ENABLED
957static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE);
958# endif
959#endif
960static int hdaProcessInterrupt(PHDASTATE pThis);
961
962/*
963 * Timer routines.
964 */
965#ifndef VBOX_WITH_AUDIO_CALLBACKS
966static void hdaTimerMaybeStart(PHDASTATE pThis);
967static void hdaTimerMaybeStop(PHDASTATE pThis);
968#endif
969
970/*********************************************************************************************************************************
971* Global Variables *
972*********************************************************************************************************************************/
973
974/** Offset of the SD0 register map. */
975#define HDA_REG_DESC_SD0_BASE 0x80
976
977/** Turn a short global register name into an memory index and a stringized name. */
978#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
979
980/** Turns a short stream register name into an memory index and a stringized name. */
981#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
982
983/** Same as above for a register *not* stored in memory. */
984#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
985
986/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
987#define HDA_REG_MAP_STRM(offset, name) \
988 /* offset size read mask write mask read callback write callback index + abbrev description */ \
989 /* ------- ------- ---------- ---------- -------------- ----------------- ------------------------------ ----------- */ \
990 /* Offset 0x80 (SD0) */ \
991 { offset, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
992 /* Offset 0x83 (SD0) */ \
993 { offset + 0x3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
994 /* Offset 0x84 (SD0) */ \
995 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
996 /* Offset 0x88 (SD0) */ \
997 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
998 /* Offset 0x8C (SD0) */ \
999 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
1000 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
1001 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteU16, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
1002 /* Offset 0x90 (SD0) */ \
1003 { offset + 0x10, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16, hdaRegWriteU16, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
1004 /* Offset 0x92 (SD0) */ \
1005 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
1006 /* Reserved: 0x94 - 0x98. */ \
1007 /* Offset 0x98 (SD0) */ \
1008 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
1009 /* Offset 0x9C (SD0) */ \
1010 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
1011
1012/** Defines a single audio stream register set (e.g. OSD0). */
1013#define HDA_REG_MAP_DEF_STREAM(index, name) \
1014 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
1015
1016/* See 302349 p 6.2. */
1017static const struct HDAREGDESC
1018{
1019 /** Register offset in the register space. */
1020 uint32_t offset;
1021 /** Size in bytes. Registers of size > 4 are in fact tables. */
1022 uint32_t size;
1023 /** Readable bits. */
1024 uint32_t readable;
1025 /** Writable bits. */
1026 uint32_t writable;
1027 /** Read callback. */
1028 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
1029 /** Write callback. */
1030 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
1031 /** Index into the register storage array. */
1032 uint32_t mem_idx;
1033 /** Abbreviated name. */
1034 const char *abbrev;
1035 /** Descripton. */
1036 const char *desc;
1037} g_aHdaRegMap[HDA_NUM_REGS] =
1038
1039{
1040 /* offset size read mask write mask read callback write callback index + abbrev */
1041 /*------- ------- ---------- ---------- ----------------------- ---------------------- ---------------- */
1042 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
1043 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
1044 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
1045 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
1046 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
1047 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
1048 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
1049 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , HDA_REG_IDX(STATESTS) }, /* State Change Status */
1050 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
1051 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
1052 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
1053 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
1054 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
1055 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
1056 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
1057 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
1058 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
1059 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
1060 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
1061 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
1062 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
1063 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
1064 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
1065 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
1066 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
1067 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
1068 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
1069 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
1070 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
1071 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
1072 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
1073 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
1074 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
1075 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
1076 /* 4 Serial Data In (SDI). */
1077 HDA_REG_MAP_DEF_STREAM(0, SD0),
1078 HDA_REG_MAP_DEF_STREAM(1, SD1),
1079 HDA_REG_MAP_DEF_STREAM(2, SD2),
1080 HDA_REG_MAP_DEF_STREAM(3, SD3),
1081 /* 4 Serial Data Out (SDO). */
1082 HDA_REG_MAP_DEF_STREAM(4, SD4),
1083 HDA_REG_MAP_DEF_STREAM(5, SD5),
1084 HDA_REG_MAP_DEF_STREAM(6, SD6),
1085 HDA_REG_MAP_DEF_STREAM(7, SD7)
1086};
1087
1088/**
1089 * HDA register aliases (HDA spec 3.3.45).
1090 * @remarks Sorted by offReg.
1091 */
1092static const struct
1093{
1094 /** The alias register offset. */
1095 uint32_t offReg;
1096 /** The register index. */
1097 int idxAlias;
1098} g_aHdaRegAliases[] =
1099{
1100 { 0x2084, HDA_REG_SD0LPIB },
1101 { 0x20a4, HDA_REG_SD1LPIB },
1102 { 0x20c4, HDA_REG_SD2LPIB },
1103 { 0x20e4, HDA_REG_SD3LPIB },
1104 { 0x2104, HDA_REG_SD4LPIB },
1105 { 0x2124, HDA_REG_SD5LPIB },
1106 { 0x2144, HDA_REG_SD6LPIB },
1107 { 0x2164, HDA_REG_SD7LPIB },
1108};
1109
1110#ifdef IN_RING3
1111/** HDABDLE field descriptors for the v6+ saved state. */
1112static SSMFIELD const g_aSSMBDLEFields6[] =
1113{
1114 SSMFIELD_ENTRY(HDABDLE, u64BufAdr),
1115 SSMFIELD_ENTRY(HDABDLE, u32BufSize),
1116 SSMFIELD_ENTRY(HDABDLE, fIntOnCompletion),
1117 SSMFIELD_ENTRY_TERM()
1118};
1119
1120/** HDABDLESTATE field descriptors for the v6+ saved state. */
1121static SSMFIELD const g_aSSMBDLEStateFields6[] =
1122{
1123 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
1124 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
1125 SSMFIELD_ENTRY(HDABDLESTATE, au8FIFO),
1126 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
1127 SSMFIELD_ENTRY_TERM()
1128};
1129
1130/** HDASTREAMSTATE field descriptors for the v6+ saved state. */
1131static SSMFIELD const g_aSSMStreamStateFields6[] =
1132{
1133 SSMFIELD_ENTRY_OLD(cBDLE, 2),
1134 SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
1135 SSMFIELD_ENTRY(HDASTREAMSTATE, fDoStop),
1136 SSMFIELD_ENTRY(HDASTREAMSTATE, fActive),
1137 SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
1138 SSMFIELD_ENTRY_TERM()
1139};
1140#endif
1141
1142/**
1143 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1144 */
1145static uint32_t const g_afMasks[5] =
1146{
1147 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1148};
1149
1150#ifdef IN_RING3
1151DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB)
1152{
1153 AssertPtrReturn(pThis, 0);
1154 AssertPtrReturn(pStream, 0);
1155
1156 Assert(u32LPIB <= pStream->u32CBL);
1157
1158 LogFlowFunc(("[SD%RU8]: LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1159 pStream->u8SD, u32LPIB, pThis->fDMAPosition));
1160
1161 /* Update LPIB in any case. */
1162 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) = u32LPIB;
1163
1164 /* Do we need to tell the current DMA position? */
1165 if (pThis->fDMAPosition)
1166 {
1167 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1168 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStream->u8SD * 2 * sizeof(uint32_t)),
1169 (void *)&u32LPIB, sizeof(uint32_t));
1170 AssertRC(rc2);
1171 }
1172
1173 return u32LPIB;
1174}
1175#endif
1176
1177/**
1178 * Retrieves the number of bytes of a FIFOS register.
1179 *
1180 * @return Number of bytes of a given FIFOS register.
1181 */
1182DECLINLINE(uint16_t) hdaSDFIFOSToBytes(uint32_t u32RegFIFOS)
1183{
1184 uint16_t cb;
1185 switch (u32RegFIFOS)
1186 {
1187 /* Input */
1188 case HDA_SDIFIFO_120B: cb = 120; break;
1189 case HDA_SDIFIFO_160B: cb = 160; break;
1190
1191 /* Output */
1192 case HDA_SDOFIFO_16B: cb = 16; break;
1193 case HDA_SDOFIFO_32B: cb = 32; break;
1194 case HDA_SDOFIFO_64B: cb = 64; break;
1195 case HDA_SDOFIFO_128B: cb = 128; break;
1196 case HDA_SDOFIFO_192B: cb = 192; break;
1197 case HDA_SDOFIFO_256B: cb = 256; break;
1198 default:
1199 {
1200 cb = 0; /* Can happen on stream reset. */
1201 break;
1202 }
1203 }
1204
1205 return cb;
1206}
1207
1208/**
1209 * Retrieves the number of bytes of a FIFOW register.
1210 *
1211 * @return Number of bytes of a given FIFOW register.
1212 */
1213DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1214{
1215 uint32_t cb;
1216 switch (u32RegFIFOW)
1217 {
1218 case HDA_SDFIFOW_8B: cb = 8; break;
1219 case HDA_SDFIFOW_16B: cb = 16; break;
1220 case HDA_SDFIFOW_32B: cb = 32; break;
1221 default: cb = 0; break;
1222 }
1223
1224#ifdef RT_STRICT
1225 Assert(RT_IS_POWER_OF_TWO(cb));
1226#endif
1227 return cb;
1228}
1229
1230#ifdef IN_RING3
1231/**
1232 * Fetches the next BDLE to use for a stream.
1233 *
1234 * @return IPRT status code.
1235 */
1236DECLINLINE(int) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
1237{
1238 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1239 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1240
1241 NOREF(pThis);
1242
1243 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1244
1245 LogFlowFuncEnter();
1246
1247#ifdef DEBUG
1248 uint32_t uOldBDLE = pStream->State.uCurBDLE;
1249#endif
1250
1251 PHDABDLE pBDLE = &pStream->State.BDLE;
1252
1253 /*
1254 * Switch to the next BDLE entry and do a wrap around
1255 * if we reached the end of the Buffer Descriptor List (BDL).
1256 */
1257 pStream->State.uCurBDLE++;
1258 if (pStream->State.uCurBDLE == pStream->u16LVI + 1)
1259 {
1260 pStream->State.uCurBDLE = 0;
1261
1262 hdaStreamUpdateLPIB(pThis, pStream, 0);
1263 }
1264
1265 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1266
1267 /* Fetch the next BDLE entry. */
1268 int rc = hdaBDLEFetch(pThis, pBDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
1269
1270#ifdef DEBUG
1271 LogFlowFunc(("[SD%RU8]: uOldBDLE=%RU16, uCurBDLE=%RU16, LVI=%RU32, rc=%Rrc, %R[bdle]\n",
1272 pStream->u8SD, uOldBDLE, pStream->State.uCurBDLE, pStream->u16LVI, rc, pBDLE));
1273#endif
1274
1275 return rc;
1276}
1277#endif /* IN_RING3 */
1278
1279/**
1280 * Returns the audio direction of a specified stream descriptor.
1281 *
1282 * The register layout specifies that input streams (SDI) come first,
1283 * followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
1284 * is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
1285 *
1286 * Note: SDnFMT register does not provide that information, so we have to judge
1287 * for ourselves.
1288 *
1289 * @return Audio direction.
1290 */
1291DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
1292{
1293 AssertReturn(uSD <= HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
1294
1295 if (uSD < HDA_MAX_SDI)
1296 return PDMAUDIODIR_IN;
1297
1298 return PDMAUDIODIR_OUT;
1299}
1300
1301/**
1302 * Returns the HDA stream of specified stream descriptor number.
1303 *
1304 * @return Pointer to HDA stream, or NULL if none found.
1305 */
1306DECLINLINE(PHDASTREAM) hdaStreamFromSD(PHDASTATE pThis, uint8_t uSD)
1307{
1308 AssertPtrReturn(pThis, NULL);
1309 AssertReturn(uSD <= HDA_MAX_STREAMS, NULL);
1310
1311 if (uSD >= HDA_MAX_STREAMS)
1312 return NULL;
1313
1314 return &pThis->aStreams[uSD];
1315}
1316
1317/**
1318 * Returns the HDA stream of specified HDA sink.
1319 *
1320 * @return Pointer to HDA stream, or NULL if none found.
1321 */
1322DECLINLINE(PHDASTREAM) hdaGetStreamFromSink(PHDASTATE pThis, PHDAMIXERSINK pSink)
1323{
1324 AssertPtrReturn(pThis, NULL);
1325 AssertPtrReturn(pSink, NULL);
1326
1327 /** @todo Do something with the channel mapping here? */
1328 return hdaStreamFromSD(pThis, pSink->uSD);
1329}
1330
1331/**
1332 * Retrieves the minimum number of bytes accumulated/free in the
1333 * FIFO before the controller will start a fetch/eviction of data.
1334 *
1335 * Uses SDFIFOW (FIFO Watermark Register).
1336 *
1337 * @return Number of bytes accumulated/free in the FIFO.
1338 */
1339DECLINLINE(uint8_t) hdaStreamGetFIFOW(PHDASTATE pThis, PHDASTREAM pStream)
1340{
1341 AssertPtrReturn(pThis, 0);
1342 AssertPtrReturn(pStream, 0);
1343
1344#ifdef VBOX_HDA_WITH_FIFO
1345 return hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, pStream->u8SD));
1346#else
1347 return 0;
1348#endif
1349}
1350
1351static int hdaProcessInterrupt(PHDASTATE pThis)
1352{
1353#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1354 ( INTCTL_SX((pThis), num) \
1355 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1356
1357 int iLevel = 0;
1358
1359 /** @todo Optimize IRQ handling. */
1360
1361 if (/* Controller Interrupt Enable (CIE). */
1362 HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1363 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1364 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1365 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1366 {
1367 iLevel = 1;
1368 }
1369
1370 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1371 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 1)
1372 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 2)
1373 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 3)
1374 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4)
1375 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 5)
1376 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 6)
1377 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 7))
1378 {
1379 iLevel = 1;
1380 }
1381
1382 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1383 {
1384 Log3Func(("Level=%d\n", iLevel));
1385 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , iLevel);
1386 }
1387
1388#undef IS_INTERRUPT_OCCURED_AND_ENABLED
1389
1390 return VINF_SUCCESS;
1391}
1392
1393/**
1394 * Looks up a register at the exact offset given by @a offReg.
1395 *
1396 * @returns Register index on success, -1 if not found.
1397 * @param pThis The HDA device state.
1398 * @param offReg The register offset.
1399 */
1400static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1401{
1402 /*
1403 * Aliases.
1404 */
1405 if (offReg >= g_aHdaRegAliases[0].offReg)
1406 {
1407 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1408 if (offReg == g_aHdaRegAliases[i].offReg)
1409 return g_aHdaRegAliases[i].idxAlias;
1410 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1411 return -1;
1412 }
1413
1414 /*
1415 * Binary search the
1416 */
1417 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1418 int idxLow = 0;
1419 for (;;)
1420 {
1421 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1422 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1423 {
1424 if (idxLow == idxMiddle)
1425 break;
1426 idxEnd = idxMiddle;
1427 }
1428 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1429 {
1430 idxLow = idxMiddle + 1;
1431 if (idxLow >= idxEnd)
1432 break;
1433 }
1434 else
1435 return idxMiddle;
1436 }
1437
1438#ifdef RT_STRICT
1439 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1440 Assert(g_aHdaRegMap[i].offset != offReg);
1441#endif
1442 return -1;
1443}
1444
1445/**
1446 * Looks up a register covering the offset given by @a offReg.
1447 *
1448 * @returns Register index on success, -1 if not found.
1449 * @param pThis The HDA device state.
1450 * @param offReg The register offset.
1451 */
1452static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1453{
1454 /*
1455 * Aliases.
1456 */
1457 if (offReg >= g_aHdaRegAliases[0].offReg)
1458 {
1459 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1460 {
1461 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1462 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1463 return g_aHdaRegAliases[i].idxAlias;
1464 }
1465 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1466 return -1;
1467 }
1468
1469 /*
1470 * Binary search the register map.
1471 */
1472 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1473 int idxLow = 0;
1474 for (;;)
1475 {
1476 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1477 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1478 {
1479 if (idxLow == idxMiddle)
1480 break;
1481 idxEnd = idxMiddle;
1482 }
1483 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1484 {
1485 idxLow = idxMiddle + 1;
1486 if (idxLow >= idxEnd)
1487 break;
1488 }
1489 else
1490 return idxMiddle;
1491 }
1492
1493#ifdef RT_STRICT
1494 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1495 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1496#endif
1497 return -1;
1498}
1499
1500#ifdef IN_RING3
1501static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1502{
1503 int rc = VINF_SUCCESS;
1504 if (fLocal)
1505 {
1506 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1507 Assert(pThis->u64CORBBase);
1508 AssertPtr(pThis->pu32CorbBuf);
1509 Assert(pThis->cbCorbBuf);
1510
1511 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1512 if (RT_FAILURE(rc))
1513 AssertRCReturn(rc, rc);
1514#ifdef DEBUG_CMD_BUFFER
1515 uint8_t i = 0;
1516 do
1517 {
1518 LogFunc(("CORB%02x: ", i));
1519 uint8_t j = 0;
1520 do
1521 {
1522 const char *pszPrefix;
1523 if ((i + j) == HDA_REG(pThis, CORBRP));
1524 pszPrefix = "[R]";
1525 else if ((i + j) == HDA_REG(pThis, CORBWP));
1526 pszPrefix = "[W]";
1527 else
1528 pszPrefix = " "; /* three spaces */
1529 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1530 j++;
1531 } while (j < 8);
1532 LogFunc(("\n"));
1533 i += 8;
1534 } while(i != 0);
1535#endif
1536 }
1537 else
1538 {
1539 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1540 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1541 if (RT_FAILURE(rc))
1542 AssertRCReturn(rc, rc);
1543#ifdef DEBUG_CMD_BUFFER
1544 uint8_t i = 0;
1545 do {
1546 LogFunc(("RIRB%02x: ", i));
1547 uint8_t j = 0;
1548 do {
1549 const char *prefix;
1550 if ((i + j) == HDA_REG(pThis, RIRBWP))
1551 prefix = "[W]";
1552 else
1553 prefix = " ";
1554 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1555 } while (++j < 8);
1556 LogFunc(("\n"));
1557 i += 8;
1558 } while (i != 0);
1559#endif
1560 }
1561 return rc;
1562}
1563
1564static int hdaCORBCmdProcess(PHDASTATE pThis)
1565{
1566 int rc = hdaCmdSync(pThis, true);
1567 if (RT_FAILURE(rc))
1568 AssertRCReturn(rc, rc);
1569
1570 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1571 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1572 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1573
1574 Assert((corbWp != corbRp));
1575 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1576
1577 while (corbRp != corbWp)
1578 {
1579 uint64_t uResp;
1580 uint32_t uCmd = pThis->pu32CorbBuf[++corbRp];
1581
1582 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
1583 if (RT_FAILURE(rc2))
1584 LogFunc(("Codec lookup failed with rc=%Rrc\n", rc2));
1585
1586 (rirbWp)++;
1587
1588 if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
1589 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1590 {
1591 LogFunc(("Unexpected unsolicited response\n"));
1592 HDA_REG(pThis, CORBRP) = corbRp;
1593 return rc;
1594 }
1595
1596 pThis->pu64RirbBuf[rirbWp] = uResp;
1597
1598 pThis->u8RespIntCnt++;
1599 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1600 break;
1601 }
1602
1603 HDA_REG(pThis, CORBRP) = corbRp;
1604 HDA_REG(pThis, RIRBWP) = rirbWp;
1605
1606 rc = hdaCmdSync(pThis, false);
1607
1608 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1609
1610 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1611 {
1612 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1613
1614 pThis->u8RespIntCnt = 0;
1615 rc = hdaProcessInterrupt(pThis);
1616 }
1617
1618 if (RT_FAILURE(rc))
1619 AssertRCReturn(rc, rc);
1620 return rc;
1621}
1622
1623static int hdaStreamCreate(PHDASTREAM pStream, uint8_t uSD)
1624{
1625 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1626 AssertReturn(uSD <= HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
1627
1628 int rc = RTSemEventCreate(&pStream->State.hStateChangedEvent);
1629 if (RT_SUCCESS(rc))
1630 rc = RTSemMutexCreate(&pStream->State.hMtx);
1631
1632 if (RT_SUCCESS(rc))
1633 {
1634 pStream->u8SD = uSD;
1635 pStream->pMixSink = NULL;
1636
1637 pStream->State.fActive = false;
1638 pStream->State.fInReset = false;
1639 pStream->State.fDoStop = false;
1640 }
1641
1642 LogFlowFunc(("uSD=%RU8\n", uSD));
1643 return rc;
1644}
1645
1646static void hdaStreamDestroy(PHDASTREAM pStream)
1647{
1648 AssertPtrReturnVoid(pStream);
1649
1650 LogFlowFunc(("[SD%RU8]: Destroying ...\n", pStream->u8SD));
1651
1652 int rc2 = hdaStreamStop(pStream);
1653 AssertRC(rc2);
1654
1655 hdaStreamMapDestroy(&pStream->State.Mapping);
1656
1657 if (pStream->State.hMtx != NIL_RTSEMMUTEX)
1658 {
1659 rc2 = RTSemMutexDestroy(pStream->State.hMtx);
1660 AssertRC(rc2);
1661 pStream->State.hMtx = NIL_RTSEMMUTEX;
1662 }
1663
1664 if (pStream->State.hStateChangedEvent != NIL_RTSEMEVENT)
1665 {
1666 rc2 = RTSemEventDestroy(pStream->State.hStateChangedEvent);
1667 AssertRC(rc2);
1668 pStream->State.hStateChangedEvent = NIL_RTSEMEVENT;
1669 }
1670
1671 LogFlowFuncLeave();
1672}
1673
1674static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStream, uint8_t u8SD)
1675{
1676 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1677 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1678
1679 pStream->u8SD = u8SD;
1680 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1681 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1682 pStream->u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1683 pStream->u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1684 pStream->u16FIFOS = hdaSDFIFOSToBytes(HDA_STREAM_REG(pThis, FIFOS, pStream->u8SD));
1685
1686 RT_ZERO(pStream->State.BDLE);
1687 pStream->State.uCurBDLE = 0;
1688
1689 hdaStreamMapReset(&pStream->State.Mapping);
1690
1691 LogFlowFunc(("[SD%RU8]: DMA @ 0x%x (%RU32 bytes), LVI=%RU16, FIFOS=%RU16\n",
1692 pStream->u8SD, pStream->u64BDLBase, pStream->u32CBL, pStream->u16LVI, pStream->u16FIFOS));
1693
1694#ifdef DEBUG
1695 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1696 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1697 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1698 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1699
1700 LogFlowFunc(("\t-> DMA @ 0x%x, LVI=%RU16, CBL=%RU32\n", u64BaseDMA, u16LVI, u32CBL));
1701
1702 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
1703#endif
1704
1705 return VINF_SUCCESS;
1706}
1707
1708static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStream)
1709{
1710 AssertPtrReturnVoid(pThis);
1711 AssertPtrReturnVoid(pStream);
1712
1713 const uint8_t uSD = pStream->u8SD;
1714
1715#ifdef VBOX_STRICT
1716 AssertReleaseMsg(!RT_BOOL(HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
1717 ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
1718#endif
1719
1720 LogFunc(("[SD%RU8]: Reset\n", uSD));
1721
1722 /*
1723 * Set reset state.
1724 */
1725 Assert(ASMAtomicReadBool(&pStream->State.fInReset) == false); /* No nested calls. */
1726 ASMAtomicXchgBool(&pStream->State.fInReset, true);
1727
1728 /*
1729 * First, reset the internal stream state.
1730 */
1731 RT_ZERO(pStream->State.BDLE);
1732 pStream->State.uCurBDLE = 0;
1733
1734 /*
1735 * Second, initialize the registers.
1736 */
1737 HDA_STREAM_REG(pThis, STS, uSD) = HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1738 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1739 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1740 HDA_STREAM_REG(pThis, CTL, uSD) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1741 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39. */
1742 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
1743 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1744 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
1745 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
1746 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
1747 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
1748 HDA_STREAM_REG(pThis, FMT, uSD) = HDA_SDFMT_MAKE(HDA_SDFMT_TYPE_PCM, HDA_SDFMT_BASE_44KHZ,
1749 HDA_SDFMT_MULT_1X, HDA_SDFMT_DIV_1X, HDA_SDFMT_16_BIT,
1750 HDA_SDFMT_CHAN_STEREO);
1751 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
1752 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
1753
1754 int rc2 = hdaStreamInit(pThis, pStream, uSD);
1755 AssertRC(rc2);
1756
1757 /* Report that we're done resetting this stream. */
1758 HDA_STREAM_REG(pThis, CTL, uSD) = 0;
1759
1760 /* Exit reset state. */
1761 ASMAtomicXchgBool(&pStream->State.fInReset, false);
1762}
1763
1764static bool hdaStreamIsActive(PHDASTATE pThis, PHDASTREAM pStream)
1765{
1766 AssertPtrReturn(pThis, false);
1767 AssertPtrReturn(pStream, false);
1768
1769 bool fActive = pStream->State.fActive;
1770
1771 LogFlowFunc(("SD=%RU8, fActive=%RTbool\n", pStream->u8SD, fActive));
1772 return fActive;
1773}
1774
1775static int hdaStreamSetActive(PHDASTATE pThis, PHDASTREAM pStream, bool fActive)
1776{
1777 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1778 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1779
1780 LogFlowFunc(("[SD%RU8]: fActive=%RTbool, pMixSink=%p\n", pStream->u8SD, fActive, pStream->pMixSink));
1781
1782 if (pStream->State.fActive == fActive) /* No change required? */
1783 {
1784 LogFlowFunc(("[SD%RU8]: No change\n", pStream->u8SD));
1785 return VINF_SUCCESS;
1786 }
1787
1788 int rc;
1789
1790 if (pStream->pMixSink) /* Stream attached to a sink? */
1791 {
1792 AUDMIXSINKCMD enmCmd = fActive
1793 ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE;
1794
1795 /* First, enable or disable the stream and the stream's sink, if any. */
1796 if (pStream->pMixSink->pMixSink)
1797 rc = AudioMixerSinkCtl(pStream->pMixSink->pMixSink, enmCmd);
1798 }
1799 else
1800 rc = VINF_SUCCESS;
1801
1802 if (RT_FAILURE(rc))
1803 {
1804 LogFlowFunc(("Failed with rc=%Rrc\n", rc));
1805 return rc;
1806 }
1807
1808 pStream->State.fActive = fActive;
1809
1810 /* Second, see if we need to start or stop the timer. */
1811 if (!fActive)
1812 {
1813 if (pThis->cStreamsActive) /* Disable can be called mupltiple times. */
1814 pThis->cStreamsActive--;
1815
1816#ifndef VBOX_WITH_AUDIO_CALLBACKS
1817 hdaTimerMaybeStop(pThis);
1818#endif
1819 }
1820 else
1821 {
1822 pThis->cStreamsActive++;
1823#ifndef VBOX_WITH_AUDIO_CALLBACKS
1824 hdaTimerMaybeStart(pThis);
1825#endif
1826 }
1827
1828 LogFlowFunc(("u8Strm=%RU8, fActive=%RTbool, cStreamsActive=%RU8\n", pStream->u8SD, fActive, pThis->cStreamsActive));
1829 return VINF_SUCCESS;
1830}
1831
1832static void hdaStreamAssignToSink(PHDASTREAM pStream, PHDAMIXERSINK pMixSink)
1833{
1834 AssertPtrReturnVoid(pStream);
1835
1836 int rc2 = RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
1837 if (RT_SUCCESS(rc2))
1838 {
1839 pStream->pMixSink = pMixSink;
1840
1841 rc2 = RTSemMutexRelease(pStream->State.hMtx);
1842 AssertRC(rc2);
1843 }
1844}
1845
1846static int hdaStreamStart(PHDASTREAM pStream)
1847{
1848 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1849
1850 ASMAtomicXchgBool(&pStream->State.fDoStop, false);
1851 ASMAtomicXchgBool(&pStream->State.fActive, true);
1852
1853 LogFlowFuncLeave();
1854 return VINF_SUCCESS;
1855}
1856
1857static int hdaStreamStop(PHDASTREAM pStream)
1858{
1859 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1860
1861 /* Already in stopped state? */
1862 bool fActive = ASMAtomicReadBool(&pStream->State.fActive);
1863 if (!fActive)
1864 return VINF_SUCCESS;
1865
1866#if 0 /** @todo Does not work (yet), as EMT deadlocks then. */
1867 /*
1868 * Wait for the stream to stop.
1869 */
1870 ASMAtomicXchgBool(&pStream->State.fDoStop, true);
1871
1872 int rc = hdaStreamWaitForStateChange(pStream, 60 * 1000 /* ms timeout */);
1873 fActive = ASMAtomicReadBool(&pStream->State.fActive);
1874 if ( /* Waiting failed? */
1875 RT_FAILURE(rc)
1876 /* Stream is still active? */
1877 || fActive)
1878 {
1879 AssertRC(rc);
1880 LogRel(("HDA: Warning: Unable to stop stream %RU8 (state: %s), rc=%Rrc\n",
1881 pStream->u8Strm, fActive ? "active" : "stopped", rc));
1882 }
1883#else
1884 int rc = VINF_SUCCESS;
1885#endif
1886
1887 LogFlowFuncLeaveRC(rc);
1888 return rc;
1889}
1890
1891static int hdaStreamChannelExtract(PPDMAUDIOSTREAMCHANNEL pChan, const void *pvBuf, size_t cbBuf)
1892{
1893 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1894 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
1895 AssertReturn(cbBuf, VERR_INVALID_PARAMETER);
1896
1897 AssertRelease(pChan->cbOff <= cbBuf);
1898
1899 const uint8_t *pu8Buf = (const uint8_t *)pvBuf;
1900
1901 size_t cbSrc = cbBuf - pChan->cbOff;
1902 const uint8_t *pvSrc = &pu8Buf[pChan->cbOff];
1903
1904 size_t cbDst;
1905 uint8_t *pvDst;
1906 RTCircBufAcquireWriteBlock(pChan->Data.pCircBuf, cbBuf, (void **)&pvDst, &cbDst);
1907
1908 cbSrc = RT_MIN(cbSrc, cbDst);
1909
1910 while (cbSrc)
1911 {
1912 AssertBreak(cbDst >= cbSrc);
1913
1914 /* Enough data for at least one next frame? */
1915 if (cbSrc < pChan->cbFrame)
1916 break;
1917
1918 memcpy(pvDst, pvSrc, pChan->cbFrame);
1919
1920 /* Advance to next channel frame in stream. */
1921 pvSrc += pChan->cbStep;
1922 Assert(cbSrc >= pChan->cbStep);
1923 cbSrc -= pChan->cbStep;
1924
1925 /* Advance destination by one frame. */
1926 pvDst += pChan->cbFrame;
1927 Assert(cbDst >= pChan->cbFrame);
1928 cbDst -= pChan->cbFrame;
1929
1930 /* Adjust offset. */
1931 pChan->cbOff += pChan->cbFrame;
1932 }
1933
1934 RTCircBufReleaseWriteBlock(pChan->Data.pCircBuf, cbDst);
1935
1936 return VINF_SUCCESS;
1937}
1938
1939static int hdaStreamChannelAdvance(PPDMAUDIOSTREAMCHANNEL pChan, size_t cbAdv)
1940{
1941 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1942
1943 if (!cbAdv)
1944 return VINF_SUCCESS;
1945
1946 return VINF_SUCCESS;
1947}
1948
1949static int hdaStreamChannelDataInit(PPDMAUDIOSTREAMCHANNELDATA pChanData, uint32_t fFlags)
1950{
1951 int rc = RTCircBufCreate(&pChanData->pCircBuf, 256); /** @todo Make this configurable? */
1952 if (RT_SUCCESS(rc))
1953 {
1954 pChanData->fFlags = fFlags;
1955 }
1956
1957 return rc;
1958}
1959
1960/**
1961 * Frees a stream channel data block again.
1962 *
1963 * @param pChanData Pointer to channel data to free.
1964 */
1965static void hdaStreamChannelDataDestroy(PPDMAUDIOSTREAMCHANNELDATA pChanData)
1966{
1967 if (!pChanData)
1968 return;
1969
1970 if (pChanData->pCircBuf)
1971 {
1972 RTCircBufDestroy(pChanData->pCircBuf);
1973 pChanData->pCircBuf = NULL;
1974 }
1975
1976 pChanData->fFlags = PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE;
1977}
1978
1979static int hdaStreamChannelAcquireData(PPDMAUDIOSTREAMCHANNELDATA pChanData, void *pvData, size_t *pcbData)
1980{
1981 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
1982 AssertPtrReturn(pvData, VERR_INVALID_POINTER);
1983 AssertPtrReturn(pcbData, VERR_INVALID_POINTER);
1984
1985 RTCircBufAcquireReadBlock(pChanData->pCircBuf, 256 /** @todo Make this configurarble? */, &pvData, &pChanData->cbAcq);
1986
1987 *pcbData = pChanData->cbAcq;
1988 return VINF_SUCCESS;
1989}
1990
1991static int hdaStreamChannelReleaseData(PPDMAUDIOSTREAMCHANNELDATA pChanData)
1992{
1993 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
1994 RTCircBufReleaseReadBlock(pChanData->pCircBuf, pChanData->cbAcq);
1995
1996 return VINF_SUCCESS;
1997}
1998
1999static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout)
2000{
2001 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
2002
2003 LogFlowFunc(("[SD%RU8]: msTimeout=%RU32\n", pStream->u8SD, msTimeout));
2004 return RTSemEventWait(pStream->State.hStateChangedEvent, msTimeout);
2005}
2006#endif /* IN_RING3 */
2007
2008/* Register access handlers. */
2009
2010static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2011{
2012 *pu32Value = 0;
2013 return VINF_SUCCESS;
2014}
2015
2016static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2017{
2018 return VINF_SUCCESS;
2019}
2020
2021/* U8 */
2022static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2023{
2024 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
2025 return hdaRegReadU32(pThis, iReg, pu32Value);
2026}
2027
2028static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2029{
2030 Assert((u32Value & 0xffffff00) == 0);
2031 return hdaRegWriteU32(pThis, iReg, u32Value);
2032}
2033
2034/* U16 */
2035static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2036{
2037 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
2038 return hdaRegReadU32(pThis, iReg, pu32Value);
2039}
2040
2041static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2042{
2043 Assert((u32Value & 0xffff0000) == 0);
2044 return hdaRegWriteU32(pThis, iReg, u32Value);
2045}
2046
2047/* U24 */
2048static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2049{
2050 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
2051 return hdaRegReadU32(pThis, iReg, pu32Value);
2052}
2053
2054static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2055{
2056 Assert((u32Value & 0xff000000) == 0);
2057 return hdaRegWriteU32(pThis, iReg, u32Value);
2058}
2059
2060/* U32 */
2061static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2062{
2063 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2064
2065 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
2066 return VINF_SUCCESS;
2067}
2068
2069static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2070{
2071 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2072
2073 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
2074 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
2075 return VINF_SUCCESS;
2076}
2077
2078static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2079{
2080 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
2081 {
2082 /* Set the CRST bit to indicate that we're leaving reset mode. */
2083 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2084
2085 if (pThis->fInReset)
2086 {
2087 LogFunc(("Guest leaving HDA reset\n"));
2088 pThis->fInReset = false;
2089 }
2090 }
2091 else
2092 {
2093#ifdef IN_RING3
2094 /* Enter reset state. */
2095 LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
2096 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
2097 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
2098
2099 /* Clear the CRST bit to indicate that we're in reset state. */
2100 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2101 pThis->fInReset = true;
2102
2103 hdaReset(pThis->CTX_SUFF(pDevIns));
2104#else
2105 return VINF_IOM_R3_MMIO_WRITE;
2106#endif
2107 }
2108
2109 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
2110 {
2111 /* Flush: GSTS:1 set, see 6.2.6. */
2112 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
2113 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
2114 }
2115 return VINF_SUCCESS;
2116}
2117
2118static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2119{
2120 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2121
2122 uint32_t v = pThis->au32Regs[iRegMem];
2123 uint32_t nv = u32Value & HDA_STATES_SCSF;
2124 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
2125 return VINF_SUCCESS;
2126}
2127
2128static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2129{
2130 uint32_t v = 0;
2131 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
2132 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
2133 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
2134 || HDA_REG(pThis, STATESTS))
2135 {
2136 v |= RT_BIT(30); /* Touch CIS. */
2137 }
2138
2139#define HDA_MARK_STREAM(x) \
2140 if (/* Descriptor Error */ \
2141 (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
2142 /* FIFO Error */ \
2143 || (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
2144 /* Buffer Completion Interrupt Status */ \
2145 || (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))) \
2146 { \
2147 Log3Func(("[SD%RU8] BCIS: Marked\n", x)); \
2148 v |= RT_BIT(x); \
2149 }
2150
2151 HDA_MARK_STREAM(0);
2152 HDA_MARK_STREAM(1);
2153 HDA_MARK_STREAM(2);
2154 HDA_MARK_STREAM(3);
2155 HDA_MARK_STREAM(4);
2156 HDA_MARK_STREAM(5);
2157 HDA_MARK_STREAM(6);
2158 HDA_MARK_STREAM(7);
2159
2160#undef HDA_MARK_STREAM
2161
2162 /* "OR" bit of all interrupt status bits. */
2163 v |= v ? RT_BIT(31) : 0;
2164
2165 *pu32Value = v;
2166 return VINF_SUCCESS;
2167}
2168
2169static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2170{
2171 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
2172 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
2173 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
2174
2175 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
2176
2177 *pu32Value = u32LPIB;
2178 return VINF_SUCCESS;
2179}
2180
2181static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2182{
2183 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2184 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
2185 - pThis->u64BaseTS, 24, 1000);
2186 LogFlowFunc(("%RU32\n", *pu32Value));
2187 return VINF_SUCCESS;
2188}
2189
2190static int hdaRegReadSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2191{
2192 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2193 *pu32Value = HDA_REG(pThis, SSYNC);
2194 LogFlowFunc(("%RU32\n", *pu32Value));
2195 return VINF_SUCCESS;
2196}
2197
2198static int hdaRegWriteSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2199{
2200 LogFlowFunc(("%RU32\n", u32Value));
2201 return hdaRegWriteU32(pThis, iReg, u32Value);
2202}
2203
2204static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2205{
2206 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
2207 {
2208 HDA_REG(pThis, CORBRP) = 0;
2209 }
2210#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
2211 else
2212 return hdaRegWriteU8(pThis, iReg, u32Value);
2213#endif
2214 return VINF_SUCCESS;
2215}
2216
2217static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2218{
2219#ifdef IN_RING3
2220 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
2221 AssertRC(rc);
2222 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2223 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
2224 {
2225 return hdaCORBCmdProcess(pThis);
2226 }
2227 return rc;
2228#else
2229 return VINF_IOM_R3_MMIO_WRITE;
2230#endif
2231}
2232
2233static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2234{
2235 uint32_t v = HDA_REG(pThis, CORBSTS);
2236 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
2237 return VINF_SUCCESS;
2238}
2239
2240static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2241{
2242#ifdef IN_RING3
2243 int rc;
2244 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2245 if (RT_FAILURE(rc))
2246 AssertRCReturn(rc, rc);
2247 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
2248 return VINF_SUCCESS;
2249 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2250 return VINF_SUCCESS;
2251 rc = hdaCORBCmdProcess(pThis);
2252 return rc;
2253#else /* !IN_RING3 */
2254 return VINF_IOM_R3_MMIO_WRITE;
2255#endif /* IN_RING3 */
2256}
2257
2258static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2259{
2260#ifdef IN_RING3
2261 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2262 return VINF_SUCCESS;
2263
2264 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
2265 if (!pStream)
2266 {
2267 LogFunc(("[SD%RU8]: Warning: Changing SDCBL on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2268 return hdaRegWriteU32(pThis, iReg, u32Value);
2269 }
2270
2271 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2272 AssertRC(rc2);
2273
2274 pStream->u32CBL = u32Value;
2275
2276 /* Reset BDLE state. */
2277 RT_ZERO(pStream->State.BDLE);
2278 pStream->State.uCurBDLE = 0;
2279
2280 rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2281 AssertRC(rc2);
2282
2283 LogFlowFunc(("[SD%RU8]: CBL=%RU32\n", pStream->u8SD, u32Value));
2284 hdaRegWriteSDUnlock(pStream);
2285
2286 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2287#else /* !IN_RING3 */
2288 return VINF_IOM_R3_MMIO_WRITE;
2289#endif /* IN_RING3 */
2290}
2291
2292static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2293{
2294 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2295 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2296 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2297 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2298
2299 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2300 return VINF_SUCCESS;
2301
2302 /* Get the stream descriptor. */
2303 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
2304
2305 /*
2306 * Extract the stream tag the guest wants to use for this specific
2307 * stream descriptor (SDn). This only can happen if the stream is in a non-running
2308 * state, so we're doing the lookup and assignment here.
2309 *
2310 * So depending on the guest OS, SD3 can use stream tag 4, for example.
2311 */
2312 uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
2313 if (uTag > HDA_MAX_TAGS)
2314 {
2315 LogFunc(("[SD%RU8]: Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
2316 return hdaRegWriteU24(pThis, iReg, u32Value);
2317 }
2318
2319#ifdef IN_RING3
2320 PHDATAG pTag = &pThis->aTags[uTag];
2321 AssertPtr(pTag);
2322
2323 LogFunc(("[SD%RU8]: Using stream tag=%RU8\n", uSD, uTag));
2324
2325 /* Assign new values. */
2326 pTag->uTag = uTag;
2327 pTag->pStrm = hdaStreamFromSD(pThis, uSD);
2328
2329 PHDASTREAM pStream = pTag->pStrm;
2330 AssertPtr(pStream);
2331
2332 /* Note: Do not use hdaRegWriteSDLock() here, as SDnCTL might change the RUN bit. */
2333 int rc2 = RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
2334 AssertRC(rc2);
2335#endif /* IN_RING3 */
2336
2337 LogFunc(("[SD%RU8]: fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
2338 uSD, fRun, fInRun, fReset, fInReset, u32Value));
2339
2340 if (fInReset)
2341 {
2342 Assert(!fReset);
2343 Assert(!fInRun && !fRun);
2344
2345 /* Report that we're done resetting this stream by clearing SRST. */
2346 HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
2347
2348 LogFunc(("[SD%RU8]: Guest initiated exit of stream reset\n", uSD));
2349 }
2350 else if (fReset)
2351 {
2352#ifdef IN_RING3
2353 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
2354 Assert(!fInRun && !fRun);
2355
2356 LogFunc(("[SD%RU8]: Guest initiated enter to stream reset\n", pStream->u8SD));
2357 hdaStreamReset(pThis, pStream);
2358#endif
2359 }
2360 else
2361 {
2362#ifdef IN_RING3
2363 /*
2364 * We enter here to change DMA states only.
2365 */
2366 if (fInRun != fRun)
2367 {
2368 Assert(!fReset && !fInReset);
2369 LogFunc(("[SD%RU8]: fRun=%RTbool\n", pStream->u8SD, fRun));
2370
2371 hdaStreamSetActive(pThis, pStream, fRun);
2372
2373 if (fRun)
2374 {
2375 /* (Re-)Fetch the current BDLE entry. */
2376 rc2 = hdaBDLEFetch(pThis, &pStream->State.BDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
2377 AssertRC(rc2);
2378 }
2379 }
2380
2381 if (!fInRun && !fRun)
2382 hdaStreamInit(pThis, pStream, pStream->u8SD);
2383#endif /* IN_RING3 */
2384 }
2385
2386 /* Make sure to handle interrupts here as well. */
2387 hdaProcessInterrupt(pThis);
2388
2389#ifdef IN_RING3
2390 rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
2391 AssertRC(rc2);
2392
2393 hdaRegWriteSDUnlock(pStream);
2394 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2395#else
2396 return VINF_IOM_R3_MMIO_WRITE;
2397#endif
2398}
2399
2400static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2401{
2402 uint32_t v = HDA_REG_IND(pThis, iReg);
2403 /* Clear (zero) FIFOE and DESE bits when writing 1 to it. */
2404 v &= ~(u32Value & v);
2405
2406 HDA_REG_IND(pThis, iReg) = v;
2407
2408 hdaProcessInterrupt(pThis);
2409 return VINF_SUCCESS;
2410}
2411
2412static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2413{
2414#ifdef IN_RING3
2415 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2416 return VINF_SUCCESS;
2417
2418 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, LVI, iReg));
2419 if (!pStream)
2420 {
2421 LogFunc(("[SD%RU8]: Warning: Changing SDLVI on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2422 return hdaRegWriteU16(pThis, iReg, u32Value);
2423 }
2424
2425 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2426 AssertRC(rc2);
2427
2428 /** @todo Validate LVI. */
2429 pStream->u16LVI = u32Value;
2430
2431 /* Reset BDLE state. */
2432 RT_ZERO(pStream->State.BDLE);
2433 pStream->State.uCurBDLE = 0;
2434
2435 rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
2436 AssertRC(rc2);
2437
2438 LogFlowFunc(("[SD%RU8]: LVI=%RU32\n", pStream->u8SD, u32Value));
2439 hdaRegWriteSDUnlock(pStream);
2440
2441 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2442#else /* !IN_RING3 */
2443 return VINF_IOM_R3_MMIO_WRITE;
2444#endif /* IN_RING3 */
2445}
2446
2447static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2448{
2449 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
2450 /** @todo Only allow updating FIFOS if RUN bit is 0? */
2451 uint32_t u32FIFOW = 0;
2452
2453 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
2454 {
2455 LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to stream #%RU8, ignoring\n", uSD));
2456 return VINF_SUCCESS;
2457 }
2458
2459 switch (u32Value)
2460 {
2461 case HDA_SDFIFOW_8B:
2462 case HDA_SDFIFOW_16B:
2463 case HDA_SDFIFOW_32B:
2464 u32FIFOW = u32Value;
2465 break;
2466 default:
2467 LogRel(("HDA: Warning: Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
2468 u32Value, uSD));
2469 u32FIFOW = HDA_SDFIFOW_32B;
2470 break;
2471 }
2472
2473 if (u32FIFOW)
2474 {
2475 LogFunc(("[SD%RU8]: Updating FIFOW to %RU32 bytes\n", uSD, hdaSDFIFOSToBytes(u32FIFOW)));
2476 /** @todo Update internal stream state with new FIFOS. */
2477
2478 return hdaRegWriteU16(pThis, iReg, u32FIFOW);
2479 }
2480
2481 return VINF_SUCCESS; /* Never reached. */
2482}
2483
2484/**
2485 * @note This method could be called for changing value on Output Streams
2486 * only (ICH6 datasheet 18.2.39).
2487 */
2488static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2489{
2490 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
2491 /** @todo Only allow updating FIFOS if RUN bit is 0? */
2492 uint32_t u32FIFOS = 0;
2493
2494 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
2495 {
2496 LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to stream #%RU8, ignoring\n", uSD));
2497 return VINF_SUCCESS;
2498 }
2499
2500 switch(u32Value)
2501 {
2502 case HDA_SDOFIFO_16B:
2503 case HDA_SDOFIFO_32B:
2504 case HDA_SDOFIFO_64B:
2505 case HDA_SDOFIFO_128B:
2506 case HDA_SDOFIFO_192B:
2507 u32FIFOS = u32Value;
2508 break;
2509
2510 case HDA_SDOFIFO_256B: /** @todo r=andy Investigate this. */
2511 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
2512 /* Fall through is intentional. */
2513 default:
2514 LogRel(("HDA: Warning: Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
2515 u32Value, uSD));
2516 u32FIFOS = HDA_SDOFIFO_192B;
2517 break;
2518 }
2519
2520 if (u32FIFOS)
2521 {
2522 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n",
2523 HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg), hdaSDFIFOSToBytes(u32FIFOS)));
2524 /** @todo Update internal stream state with new FIFOS. */
2525
2526 return hdaRegWriteU16(pThis, iReg, u32FIFOS);
2527 }
2528
2529 return VINF_SUCCESS;
2530}
2531
2532#ifdef IN_RING3
2533static int hdaSDFMTToStrmCfg(uint32_t u32SDFMT, PPDMAUDIOSTREAMCFG pStrmCfg)
2534{
2535 AssertPtrReturn(pStrmCfg, VERR_INVALID_POINTER);
2536
2537# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2538
2539 int rc = VINF_SUCCESS;
2540
2541 uint32_t u32Hz = EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BASE_RATE_MASK, HDA_SDFMT_BASE_RATE_SHIFT)
2542 ? 44100 : 48000;
2543 uint32_t u32HzMult = 1;
2544 uint32_t u32HzDiv = 1;
2545
2546 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2547 {
2548 case 0: u32HzMult = 1; break;
2549 case 1: u32HzMult = 2; break;
2550 case 2: u32HzMult = 3; break;
2551 case 3: u32HzMult = 4; break;
2552 default:
2553 LogFunc(("Unsupported multiplier %x\n",
2554 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2555 rc = VERR_NOT_SUPPORTED;
2556 break;
2557 }
2558 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2559 {
2560 case 0: u32HzDiv = 1; break;
2561 case 1: u32HzDiv = 2; break;
2562 case 2: u32HzDiv = 3; break;
2563 case 3: u32HzDiv = 4; break;
2564 case 4: u32HzDiv = 5; break;
2565 case 5: u32HzDiv = 6; break;
2566 case 6: u32HzDiv = 7; break;
2567 case 7: u32HzDiv = 8; break;
2568 default:
2569 LogFunc(("Unsupported divisor %x\n",
2570 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2571 rc = VERR_NOT_SUPPORTED;
2572 break;
2573 }
2574
2575 PDMAUDIOFMT enmFmt;
2576 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2577 {
2578 case 0:
2579 enmFmt = PDMAUDIOFMT_S8;
2580 break;
2581 case 1:
2582 enmFmt = PDMAUDIOFMT_S16;
2583 break;
2584 case 4:
2585 enmFmt = PDMAUDIOFMT_S32;
2586 break;
2587 default:
2588 AssertMsgFailed(("Unsupported bits per sample %x\n",
2589 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2590 rc = VERR_NOT_SUPPORTED;
2591 break;
2592 }
2593
2594 if (RT_SUCCESS(rc))
2595 {
2596 pStrmCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2597 pStrmCfg->cChannels = (u32SDFMT & 0xf) + 1;
2598 pStrmCfg->enmFormat = enmFmt;
2599 pStrmCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2600 }
2601
2602# undef EXTRACT_VALUE
2603 return rc;
2604}
2605
2606static int hdaAddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2607{
2608 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2609 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2610
2611 AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
2612
2613 LogFlowFunc(("Stream=%s\n", pCfg->szName));
2614
2615 int rc = VINF_SUCCESS;
2616
2617 bool fUseFront = true; /* Always use front out by default. */
2618#ifdef VBOX_WITH_HDA_51_SURROUND
2619 bool fUseRear;
2620 bool fUseCenter;
2621 bool fUseLFE;
2622
2623 fUseRear = fUseCenter = fUseLFE = false;
2624
2625 /*
2626 * Use commonly used setups for speaker configurations.
2627 */
2628
2629 /** @todo Make the following configurable through mixer API and/or CFGM? */
2630 switch (pCfg->cChannels)
2631 {
2632 case 3: /* 2.1: Front (Stereo) + LFE. */
2633 {
2634 fUseLFE = true;
2635 break;
2636 }
2637
2638 case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
2639 {
2640 fUseRear = true;
2641 break;
2642 }
2643
2644 case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
2645 {
2646 fUseRear = true;
2647 fUseLFE = true;
2648 break;
2649 }
2650
2651 case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
2652 {
2653 fUseRear = true;
2654 fUseCenter = true;
2655 fUseLFE = true;
2656 break;
2657 }
2658
2659 default: /* Unknown; fall back to 2 front channels (stereo). */
2660 {
2661 rc = VERR_NOT_SUPPORTED;
2662 break;
2663 }
2664 }
2665#else /* !VBOX_WITH_HDA_51_SURROUND */
2666 /* Only support mono or stereo channels. */
2667 if ( pCfg->cChannels != 1 /* Mono */
2668 && pCfg->cChannels != 2 /* Stereo */)
2669 {
2670 rc = VERR_NOT_SUPPORTED;
2671 }
2672#endif
2673
2674 if (rc == VERR_NOT_SUPPORTED)
2675 {
2676 LogRel(("HDA: Unsupported channel count (%RU8), falling back to stereo channels\n", pCfg->cChannels));
2677 pCfg->cChannels = 2;
2678
2679 rc = VINF_SUCCESS;
2680 }
2681
2682 do
2683 {
2684 if (RT_FAILURE(rc))
2685 break;
2686
2687 if (fUseFront)
2688 {
2689 if (!RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front"))
2690 {
2691 rc = VERR_BUFFER_OVERFLOW;
2692 break;
2693 }
2694
2695 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
2696 pCfg->cChannels = 2;
2697 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT);
2698 if (RT_SUCCESS(rc))
2699 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
2700 }
2701
2702#ifdef VBOX_WITH_HDA_51_SURROUND
2703 if ( RT_SUCCESS(rc)
2704 && (fUseCenter || fUseLFE))
2705 {
2706 if (!RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE"))
2707 {
2708 rc = VERR_BUFFER_OVERFLOW;
2709 break;
2710 }
2711
2712 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
2713 pCfg->cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
2714 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE);
2715 if (RT_SUCCESS(rc))
2716 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
2717 }
2718
2719 if ( RT_SUCCESS(rc)
2720 && fUseRear)
2721 {
2722 if (!RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear"))
2723 {
2724 rc = VERR_BUFFER_OVERFLOW;
2725 break;
2726 }
2727
2728 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
2729 pCfg->cChannels = 2;
2730 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR);
2731 if (RT_SUCCESS(rc))
2732 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
2733 }
2734#endif /* VBOX_WITH_HDA_51_SURROUND */
2735
2736 } while (0);
2737
2738 LogFlowFuncLeaveRC(rc);
2739 return rc;
2740}
2741
2742static int hdaAddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2743{
2744 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2745 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2746
2747 AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
2748
2749 LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
2750
2751 int rc;
2752
2753 switch (pCfg->DestSource.Source)
2754 {
2755 case PDMAUDIORECSOURCE_LINE:
2756 {
2757 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN);
2758 if (RT_SUCCESS(rc))
2759 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
2760 break;
2761 }
2762#ifdef VBOX_WITH_HDA_MIC_IN
2763 case PDMAUDIORECSOURCE_MIC:
2764 {
2765 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN);
2766 if (RT_SUCCESS(rc))
2767 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
2768 break;
2769 }
2770#endif
2771 default:
2772 rc = VERR_NOT_SUPPORTED;
2773 break;
2774 }
2775
2776 LogFlowFuncLeaveRC(rc);
2777 return rc;
2778}
2779#endif /* IN_RING3 */
2780
2781static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2782{
2783#ifdef IN_RING3
2784 PDMAUDIOSTREAMCFG strmCfg;
2785 RT_ZERO(strmCfg);
2786
2787 int rc = hdaSDFMTToStrmCfg(u32Value, &strmCfg);
2788 if (RT_FAILURE(rc))
2789 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2790
2791 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg));
2792 if (!pStream)
2793 {
2794 LogFunc(("[SD%RU8]: Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2795 HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2796 return hdaRegWriteU16(pThis, iReg, u32Value);
2797 }
2798
2799 rc = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2800 AssertRC(rc);
2801
2802 LogFunc(("[SD%RU8]: Hz=%RU32, Channels=%RU8, enmFmt=%RU32\n",
2803 pStream->u8SD, strmCfg.uHz, strmCfg.cChannels, strmCfg.enmFormat));
2804
2805 /* Set audio direction. */
2806 strmCfg.enmDir = hdaGetDirFromSD(pStream->u8SD);
2807 switch (strmCfg.enmDir)
2808 {
2809 case PDMAUDIODIR_IN:
2810#ifdef VBOX_WITH_HDA_MIC_IN
2811# error "Implement me!"
2812#else
2813 strmCfg.DestSource.Source = PDMAUDIORECSOURCE_LINE;
2814#endif
2815 break;
2816
2817 case PDMAUDIODIR_OUT:
2818 /* Destination(s) will be set in hdaAddStreamOut(),
2819 * based on the channels / stream layout. */
2820 break;
2821
2822 default:
2823 rc = VERR_NOT_SUPPORTED;
2824 break;
2825 }
2826
2827 /*
2828 * Initialize the stream mapping in any case, regardless if
2829 * we support surround audio or not. This is needed to handle
2830 * the supported channels within a single audio stream, e.g. mono/stereo.
2831 *
2832 * In other words, the stream mapping *always* knowns the real
2833 * number of channels in a single audio stream.
2834 */
2835 if (RT_SUCCESS(rc))
2836 {
2837 rc = hdaStreamMapInit(&pStream->State.Mapping, &strmCfg);
2838 AssertRC(rc);
2839 }
2840
2841 if (RT_SUCCESS(rc))
2842 {
2843 int rc2;
2844 PHDADRIVER pDrv;
2845 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2846 {
2847 switch (strmCfg.enmDir)
2848 {
2849 case PDMAUDIODIR_OUT:
2850 rc2 = hdaAddStreamOut(pThis, &strmCfg);
2851 break;
2852
2853 case PDMAUDIODIR_IN:
2854 rc2 = hdaAddStreamIn(pThis, &strmCfg);
2855 break;
2856
2857 default:
2858 rc2 = VERR_NOT_SUPPORTED;
2859 AssertFailed();
2860 break;
2861 }
2862
2863 if ( RT_FAILURE(rc2)
2864 && (pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY)) /* We only care about primary drivers here, the rest may fail. */
2865 {
2866 if (RT_SUCCESS(rc))
2867 rc = rc2;
2868 /* Keep going. */
2869 }
2870 }
2871
2872 /* If (re-)opening the stream by the codec above failed, don't write the new
2873 * format to the register so that the guest is aware it didn't work. */
2874 if (RT_SUCCESS(rc))
2875 {
2876 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2877 AssertRC(rc);
2878 }
2879 else
2880 LogFunc(("[SD%RU8]: (Re-)Opening stream failed with rc=%Rrc\n", pStream->u8SD, rc));
2881
2882 hdaRegWriteSDUnlock(pStream);
2883 }
2884
2885 return VINF_SUCCESS; /* Never return failure. */
2886#else /* !IN_RING3 */
2887 return VINF_IOM_R3_MMIO_WRITE;
2888#endif
2889}
2890
2891/* Note: Will be called for both, BDPL and BDPU, registers. */
2892DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t u8Strm)
2893{
2894#ifdef IN_RING3
2895 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2896 return VINF_SUCCESS;
2897
2898 PHDASTREAM pStream = hdaStreamFromSD(pThis, u8Strm);
2899 if (!pStream)
2900 {
2901 LogFunc(("[SD%RU8]: Warning: Changing SDBPL/SDBPU on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2902 return hdaRegWriteU32(pThis, iReg, u32Value);
2903 }
2904
2905 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2906 AssertRC(rc2);
2907
2908 rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2909 AssertRC(rc2);
2910
2911 /* Update BDL base. */
2912 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2913 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2914 /* Reset BDLE state. */
2915 RT_ZERO(pStream->State.BDLE);
2916 pStream->State.uCurBDLE = 0;
2917
2918 LogFlowFunc(("[SD%RU8]: BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2919 hdaRegWriteSDUnlock(pStream);
2920
2921 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2922#else /* !IN_RING3 */
2923 return VINF_IOM_R3_MMIO_WRITE;
2924#endif /* IN_RING3 */
2925}
2926
2927static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2928{
2929 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2930}
2931
2932static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2933{
2934 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2935}
2936
2937#ifdef IN_RING3
2938/**
2939 * XXX
2940 *
2941 * @return bool Returns @true if write is allowed, @false if not.
2942 * @param pThis Pointer to HDA state.
2943 * @param iReg Register to write.
2944 * @param u32Value Value to write.
2945 */
2946DECLINLINE(int) hdaRegWriteSDLock(PHDASTATE pThis, PHDASTREAM pStream, uint32_t iReg, uint32_t u32Value)
2947{
2948 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2949 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
2950
2951#ifdef VBOX_STRICT
2952 /* Check if the SD's RUN bit is set. */
2953 uint32_t u32SDCTL = HDA_STREAM_REG(pThis, CTL, pStream->u8SD);
2954 bool fIsRunning = RT_BOOL(u32SDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2955 if (fIsRunning)
2956 {
2957 LogFunc(("[SD%RU8]: Warning: Cannot write to register 0x%x (0x%x) when RUN bit is set (%R[sdctl])\n",
2958 pStream->u8SD, iReg, u32Value, u32SDCTL));
2959# ifdef DEBUG_andy
2960 AssertFailed();
2961# endif
2962 return VERR_ACCESS_DENIED;
2963 }
2964#endif
2965
2966 return RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
2967}
2968
2969DECLINLINE(void) hdaRegWriteSDUnlock(PHDASTREAM pStream)
2970{
2971 AssertPtrReturnVoid(pStream);
2972
2973 int rc2 = RTSemMutexRelease(pStream->State.hMtx);
2974 AssertRC(rc2);
2975}
2976#endif /* IN_RING3 */
2977
2978static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2979{
2980 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2981 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2982 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2983 {
2984 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2985 }
2986
2987 return hdaRegReadU32(pThis, iReg, pu32Value);
2988}
2989
2990static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2991{
2992 int rc = VINF_SUCCESS;
2993
2994 /*
2995 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2996 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2997 */
2998 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
2999 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
3000 {
3001#ifdef IN_RING3
3002 uint32_t uCmd = HDA_REG(pThis, IC);
3003
3004 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
3005 {
3006 /*
3007 * 3.4.3: Defines behavior of immediate Command status register.
3008 */
3009 LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
3010 return rc;
3011 }
3012
3013 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
3014
3015 uint64_t uResp;
3016 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
3017 HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
3018 if (RT_FAILURE(rc2))
3019 LogFunc(("Codec lookup failed with rc=%Rrc\n", rc2));
3020
3021 HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
3022 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
3023 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
3024#else /* !IN_RING3 */
3025 rc = VINF_IOM_R3_MMIO_WRITE;
3026#endif
3027 return rc;
3028 }
3029
3030 /*
3031 * Once the guest read the response, it should clean the IRV bit of the IRS register.
3032 */
3033 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
3034 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
3035 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
3036 return rc;
3037}
3038
3039static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3040{
3041 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
3042 HDA_REG(pThis, RIRBWP) = 0;
3043
3044 /* The remaining bits are O, see 6.2.22. */
3045 return VINF_SUCCESS;
3046}
3047
3048static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3049{
3050 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
3051 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
3052 if (RT_FAILURE(rc))
3053 AssertRCReturn(rc, rc);
3054
3055 switch(iReg)
3056 {
3057 case HDA_REG_CORBLBASE:
3058 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
3059 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
3060 break;
3061 case HDA_REG_CORBUBASE:
3062 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
3063 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3064 break;
3065 case HDA_REG_RIRBLBASE:
3066 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
3067 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
3068 break;
3069 case HDA_REG_RIRBUBASE:
3070 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
3071 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3072 break;
3073 case HDA_REG_DPLBASE:
3074 {
3075 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
3076 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
3077
3078 /* Also make sure to handle the DMA position enable bit. */
3079 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
3080 LogRel(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
3081 break;
3082 }
3083 case HDA_REG_DPUBASE:
3084 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
3085 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3086 break;
3087 default:
3088 AssertMsgFailed(("Invalid index\n"));
3089 break;
3090 }
3091
3092 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
3093 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
3094 return rc;
3095}
3096
3097static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3098{
3099 uint8_t v = HDA_REG(pThis, RIRBSTS);
3100 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
3101
3102 return hdaProcessInterrupt(pThis);
3103}
3104
3105#ifdef IN_RING3
3106#ifdef LOG_ENABLED
3107static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE)
3108{
3109 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
3110 if (!u64BDLBase)
3111 return;
3112
3113 uint32_t cbBDLE = 0;
3114 for (uint16_t i = 0; i < cBDLE; i++)
3115 {
3116 uint8_t bdle[16]; /** @todo Use a define. */
3117 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BDLBase + i * 16, bdle, 16); /** @todo Use a define. */
3118
3119 uint64_t addr = *(uint64_t *)bdle;
3120 uint32_t len = *(uint32_t *)&bdle[8];
3121 uint32_t ioc = *(uint32_t *)&bdle[12];
3122
3123 LogFlowFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
3124 i, addr, len, RT_BOOL(ioc & 0x1)));
3125
3126 cbBDLE += len;
3127 }
3128
3129 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
3130
3131 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
3132 return;
3133
3134 LogFlowFunc(("DMA counters:\n"));
3135
3136 for (int i = 0; i < cBDLE; i++)
3137 {
3138 uint32_t uDMACnt;
3139 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
3140 &uDMACnt, sizeof(uDMACnt));
3141
3142 LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
3143 }
3144}
3145#endif
3146
3147/**
3148 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
3149 *
3150 * @param pThis Pointer to HDA state.
3151 * @param pBDLE Where to store the fetched result.
3152 * @param u64BaseDMA Address base of DMA engine to use.
3153 * @param u16Entry BDLE entry to fetch.
3154 */
3155static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
3156{
3157 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3158 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
3159 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
3160
3161 if (!u64BaseDMA)
3162 {
3163 LogRel2(("HDA: Unable to fetch BDLE #%RU16 - no base DMA address set (yet)\n", u16Entry));
3164 return VERR_NOT_FOUND;
3165 }
3166 /** @todo Compare u16Entry with LVI. */
3167
3168 uint8_t uBundleEntry[16]; /** @todo Define a BDLE length. */
3169 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * 16, /** @todo Define a BDLE length. */
3170 uBundleEntry, RT_ELEMENTS(uBundleEntry));
3171 if (RT_FAILURE(rc))
3172 return rc;
3173
3174 RT_BZERO(pBDLE, sizeof(HDABDLE));
3175
3176 pBDLE->State.u32BDLIndex = u16Entry;
3177 pBDLE->u64BufAdr = *(uint64_t *) uBundleEntry;
3178 pBDLE->u32BufSize = *(uint32_t *)&uBundleEntry[8];
3179 if (pBDLE->u32BufSize < sizeof(uint16_t)) /* Must be at least one word. */
3180 return VERR_INVALID_STATE;
3181
3182 pBDLE->fIntOnCompletion = (*(uint32_t *)&uBundleEntry[12]) & RT_BIT(0);
3183
3184 return VINF_SUCCESS;
3185}
3186
3187/**
3188 * Returns the number of outstanding stream data bytes which need to be processed
3189 * by the DMA engine assigned to this stream.
3190 *
3191 * @return Number of bytes for the DMA engine to process.
3192 */
3193DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax)
3194{
3195 AssertPtrReturn(pThis, 0);
3196 AssertPtrReturn(pStream, 0);
3197
3198 if (!cbMax)
3199 return 0;
3200
3201 PHDABDLE pBDLE = &pStream->State.BDLE;
3202
3203 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3204 Assert(u32LPIB <= pStream->u32CBL);
3205
3206 uint32_t cbFree = pStream->u32CBL - u32LPIB;
3207 if (cbFree)
3208 {
3209 /* Limit to the available free space of the current BDLE. */
3210 cbFree = RT_MIN(cbFree, pBDLE->u32BufSize - pBDLE->State.u32BufOff);
3211
3212 /* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
3213 cbFree = RT_MIN(cbFree, uint32_t(pStream->u16FIFOS));
3214
3215 /* Make sure we only transfer as many bytes as requested. */
3216 cbFree = RT_MIN(cbFree, cbMax);
3217
3218 if (pBDLE->State.cbBelowFIFOW)
3219 {
3220 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
3221 * No need to read data from DMA then. */
3222 if (cbFree > pBDLE->State.cbBelowFIFOW)
3223 {
3224 /* Subtract the amount of bytes that still would fit in the stream's FIFO
3225 * and therefore do not need to be processed by DMA. */
3226 cbFree -= pBDLE->State.cbBelowFIFOW;
3227 }
3228 }
3229 }
3230
3231 LogFlowFunc(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, FIFOS=%RU16, cbFree=%RU32, %R[bdle]\n", pStream->u8SD,
3232 pStream->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), pStream->u16FIFOS, cbFree, pBDLE));
3233 return cbFree;
3234}
3235
3236DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
3237{
3238 AssertPtrReturnVoid(pBDLE);
3239
3240 if (!cbData || !cbProcessed)
3241 return;
3242
3243 /* Fewer than cbBelowFIFOW bytes were copied.
3244 * Probably we need to move the buffer, but it is rather hard to imagine a situation
3245 * where it might happen. */
3246 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
3247 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
3248 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
3249
3250#if 0
3251 if ( pBDLE->State.cbBelowFIFOW
3252 && pBDLE->State.cbBelowFIFOW <= cbWritten)
3253 {
3254 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
3255 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->u32BufSize));
3256 }
3257#endif
3258
3259 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
3260 Assert(pBDLE->State.cbBelowFIFOW == 0);
3261
3262 /* We always increment the position of DMA buffer counter because we're always reading
3263 * into an intermediate buffer. */
3264 pBDLE->State.u32BufOff += cbData;
3265 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3266
3267 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
3268}
3269
3270#ifdef IN_RING3
3271/**
3272 * Initializes a stream mapping structure according to the given stream configuration.
3273 *
3274 * @return IPRT status code.
3275 * @param pMapping Pointer to mapping to initialize.
3276 * @param pCfg Pointer to stream configuration to use.
3277 */
3278static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg)
3279{
3280 AssertPtrReturn(pMapping, VERR_INVALID_POINTER);
3281 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3282
3283 AssertReturn(pCfg->cChannels, VERR_INVALID_PARAMETER);
3284
3285 hdaStreamMapReset(pMapping);
3286
3287 pMapping->paChannels = (PPDMAUDIOSTREAMCHANNEL)RTMemAlloc(sizeof(PDMAUDIOSTREAMCHANNEL) * pCfg->cChannels);
3288 if (!pMapping->paChannels)
3289 return VERR_NO_MEMORY;
3290
3291 PDMPCMPROPS Props;
3292 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &Props);
3293 if (RT_FAILURE(rc))
3294 return rc;
3295
3296 Assert(RT_IS_POWER_OF_TWO(Props.cBits));
3297
3298 /** @todo We assume all channels in a stream have the same format. */
3299 PPDMAUDIOSTREAMCHANNEL pChan = pMapping->paChannels;
3300 for (uint8_t i = 0; i < pCfg->cChannels; i++)
3301 {
3302 pChan->uChannel = i;
3303 pChan->cbStep = (Props.cBits / 2);
3304 pChan->cbFrame = pChan->cbStep * pCfg->cChannels;
3305 pChan->cbFirst = i * pChan->cbStep;
3306 pChan->cbOff = pChan->cbFirst;
3307
3308 int rc2 = hdaStreamChannelDataInit(&pChan->Data, PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE);
3309 if (RT_SUCCESS(rc))
3310 rc = rc2;
3311
3312 if (RT_FAILURE(rc))
3313 break;
3314
3315 pChan++;
3316 }
3317
3318 if ( RT_SUCCESS(rc)
3319 /* Create circular buffer if not created yet. */
3320 && !pMapping->pCircBuf)
3321 {
3322 rc = RTCircBufCreate(&pMapping->pCircBuf, _4K); /** @todo Make size configurable? */
3323 }
3324
3325 if (RT_SUCCESS(rc))
3326 {
3327 pMapping->cChannels = pCfg->cChannels;
3328#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3329 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_INTERLEAVED;
3330#else
3331 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
3332#endif
3333 }
3334
3335 return rc;
3336}
3337
3338/**
3339 * Destroys a given stream mapping.
3340 *
3341 * @param pMapping Pointer to mapping to destroy.
3342 */
3343static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping)
3344{
3345 hdaStreamMapReset(pMapping);
3346
3347 if (pMapping->pCircBuf)
3348 {
3349 RTCircBufDestroy(pMapping->pCircBuf);
3350 pMapping->pCircBuf = NULL;
3351 }
3352}
3353
3354/**
3355 * Resets a given stream mapping.
3356 *
3357 * @param pMapping Pointer to mapping to reset.
3358 */
3359static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping)
3360{
3361 AssertPtrReturnVoid(pMapping);
3362
3363 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_UNKNOWN;
3364
3365 if (pMapping->cChannels)
3366 {
3367 for (uint8_t i = 0; i < pMapping->cChannels; i++)
3368 hdaStreamChannelDataDestroy(&pMapping->paChannels[i].Data);
3369
3370 AssertPtr(pMapping->paChannels);
3371 RTMemFree(pMapping->paChannels);
3372 pMapping->paChannels = NULL;
3373
3374 pMapping->cChannels = 0;
3375 }
3376}
3377#endif /* IN_RING3 */
3378
3379DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
3380{
3381 AssertPtrReturn(pThis, false);
3382 AssertPtrReturn(pStream, false);
3383
3384 PHDABDLE pBDLE = &pStream->State.BDLE;
3385 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3386
3387 /* Did we reach the CBL (Cyclic Buffer List) limit? */
3388 bool fCBLLimitReached = u32LPIB >= pStream->u32CBL;
3389
3390 /* Do we need to use the next BDLE entry? Either because we reached
3391 * the CBL limit or our internal DMA buffer is full. */
3392 bool fNeedsNextBDLE = ( fCBLLimitReached
3393 || (pBDLE->State.u32BufOff >= pBDLE->u32BufSize));
3394
3395 Assert(u32LPIB <= pStream->u32CBL);
3396 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3397
3398 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
3399 pStream->u8SD, u32LPIB, pStream->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
3400
3401 return fNeedsNextBDLE;
3402}
3403
3404DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbInc)
3405{
3406 AssertPtrReturnVoid(pThis);
3407 AssertPtrReturnVoid(pStream);
3408
3409 LogFlowFunc(("[SD%RU8]: cbInc=%RU32\n", pStream->u8SD, cbInc));
3410
3411 //Assert(cbInc <= pStream->u16FIFOS);
3412
3413 if (!cbInc) /* Nothing to do? Bail out early. */
3414 return;
3415
3416 PHDABDLE pBDLE = &pStream->State.BDLE;
3417
3418 /*
3419 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
3420 * doesn't fetch anything via DMA, so just update LPIB.
3421 * (ICH6 datasheet 18.2.38).
3422 */
3423 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
3424 {
3425 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3426
3427 AssertMsg(((u32LPIB + cbInc) <= pStream->u32CBL),
3428 ("[SD%RU8] Increment (%RU32) exceeds CBL (%RU32): LPIB (%RU32)\n",
3429 pStream->u8SD, cbInc, pStream->u32CBL, u32LPIB));
3430
3431 u32LPIB = RT_MIN(u32LPIB + cbInc, pStream->u32CBL);
3432
3433 LogFlowFunc(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
3434 pStream->u8SD,
3435 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) + cbInc,
3436 pStream->u32CBL));
3437
3438 hdaStreamUpdateLPIB(pThis, pStream, u32LPIB);
3439 }
3440}
3441
3442static bool hdaStreamTransferIsComplete(PHDASTATE pThis, PHDASTREAM pStream, bool *pfInterrupt)
3443{
3444 AssertPtrReturn(pThis, true);
3445 AssertPtrReturn(pStream, true);
3446
3447 bool fInterrupt = false;
3448 bool fIsComplete = false;
3449
3450 PHDABDLE pBDLE = &pStream->State.BDLE;
3451 const uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3452
3453 /* Check if the current BDLE entry is complete (full). */
3454 if (pBDLE->State.u32BufOff >= pBDLE->u32BufSize)
3455 {
3456 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3457
3458 if (/* IOC (Interrupt On Completion) bit set? */
3459 pBDLE->fIntOnCompletion
3460 /* All data put into the DMA FIFO? */
3461 && pBDLE->State.cbBelowFIFOW == 0
3462 )
3463 {
3464 LogFlowFunc(("[SD%RU8]: %R[bdle] => COMPLETE\n", pStream->u8SD, pBDLE));
3465
3466 /*
3467 * If the ICE (IOCE, "Interrupt On Completion Enable") bit of the SDCTL register is set
3468 * we need to generate an interrupt.
3469 */
3470 if (HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
3471 fInterrupt = true;
3472 }
3473
3474 fIsComplete = true;
3475 }
3476
3477 if (pfInterrupt)
3478 *pfInterrupt = fInterrupt;
3479
3480 LogFlowFunc(("[SD%RU8]: u32LPIB=%RU32, CBL=%RU32, fIsComplete=%RTbool, fInterrupt=%RTbool, %R[bdle]\n",
3481 pStream->u8SD, u32LPIB, pStream->u32CBL, fIsComplete, fInterrupt, pBDLE));
3482
3483 return fIsComplete;
3484}
3485
3486/**
3487 * hdaReadAudio - copies samples from audio backend to DMA.
3488 * Note: This function writes to the DMA buffer immediately,
3489 * but "reports bytes" when all conditions are met (FIFOW).
3490 */
3491static int hdaReadAudio(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToRead, uint32_t *pcbRead)
3492{
3493 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3494 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
3495 /* pcbRead is optional. */
3496
3497 int rc;
3498 uint32_t cbRead = 0;
3499
3500 do
3501 {
3502 PHDABDLE pBDLE = &pStream->State.BDLE;
3503
3504 if (!cbToRead)
3505 {
3506 rc = VINF_EOF;
3507 break;
3508 }
3509
3510 AssertPtr(pStream->pMixSink);
3511 AssertPtr(pStream->pMixSink->pMixSink);
3512 rc = AudioMixerSinkRead(pStream->pMixSink->pMixSink, AUDMIXOP_BLEND, pBDLE->State.au8FIFO, cbToRead, &cbRead);
3513 if (RT_FAILURE(rc))
3514 break;
3515
3516 if (!cbRead)
3517 {
3518 rc = VINF_EOF;
3519 break;
3520 }
3521
3522 /* Sanity checks. */
3523 Assert(cbRead <= cbToRead);
3524 Assert(cbRead <= sizeof(pBDLE->State.au8FIFO));
3525 Assert(cbRead <= pBDLE->u32BufSize - pBDLE->State.u32BufOff);
3526
3527 /*
3528 * Write to the BDLE's DMA buffer.
3529 */
3530 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
3531 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
3532 pBDLE->State.au8FIFO, cbRead);
3533 AssertRC(rc);
3534
3535 if (pBDLE->State.cbBelowFIFOW + cbRead > hdaStreamGetFIFOW(pThis, pStream))
3536 {
3537 Assert(pBDLE->State.u32BufOff + cbRead <= pBDLE->u32BufSize);
3538 pBDLE->State.u32BufOff += cbRead;
3539 pBDLE->State.cbBelowFIFOW = 0;
3540 //hdaBackendReadTransferReported(pBDLE, cbDMAData, cbRead, &cbRead, pcbAvail);
3541 }
3542 else
3543 {
3544 Assert(pBDLE->State.u32BufOff + cbRead <= pBDLE->u32BufSize);
3545 pBDLE->State.u32BufOff += cbRead;
3546 pBDLE->State.cbBelowFIFOW += cbRead;
3547 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStream));
3548 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbRead, pcbAvail);
3549
3550 rc = VERR_NO_DATA;
3551 }
3552
3553 } while (0);
3554
3555 if (RT_SUCCESS(rc))
3556 {
3557 if (pcbRead)
3558 *pcbRead = cbRead;
3559 }
3560
3561 if (RT_FAILURE(rc))
3562 LogFlowFunc(("Failed with %Rrc\n", rc));
3563
3564 return rc;
3565}
3566
3567static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToWrite, uint32_t *pcbWritten)
3568{
3569 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3570 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
3571 /* pcbWritten is optional. */
3572
3573 PHDABDLE pBDLE = &pStream->State.BDLE;
3574
3575 uint32_t cbWritten = 0;
3576
3577 /*
3578 * Copy from DMA to the corresponding stream buffer (if there are any bytes from the
3579 * previous unreported transfer we write at offset 'pBDLE->State.cbUnderFifoW').
3580 */
3581 int rc;
3582 if (!cbToWrite)
3583 {
3584 rc = VINF_EOF;
3585 }
3586 else
3587 {
3588 void *pvBuf = pBDLE->State.au8FIFO + pBDLE->State.cbBelowFIFOW;
3589 Assert(cbToWrite >= pBDLE->State.cbBelowFIFOW);
3590 uint32_t cbBuf = cbToWrite - pBDLE->State.cbBelowFIFOW;
3591
3592 /*
3593 * Read from the current BDLE's DMA buffer.
3594 */
3595 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3596 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
3597 pvBuf, cbBuf);
3598 AssertRC(rc);
3599
3600#ifdef HDA_DEBUG_DUMP_PCM_DATA
3601 RTFILE fh;
3602 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaWriteAudio-hda.pcm",
3603 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
3604 RTFileWrite(fh, pvBuf, cbBuf, NULL);
3605 RTFileClose(fh);
3606#endif
3607
3608#ifdef VBOX_WITH_STATISTICS
3609 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBuf);
3610#endif
3611 /*
3612 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
3613 */
3614 if (cbBuf >= hdaStreamGetFIFOW(pThis, pStream))
3615 {
3616 PHDASTREAMMAPPING pMapping = &pStream->State.Mapping;
3617
3618 /** @todo Which channel is which? */
3619#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3620 PPDMAUDIOSTREAMCHANNEL pChanFront = &pMapping->paChannels[0];
3621#endif
3622#ifdef VBOX_WITH_HDA_51_SURROUND
3623 PPDMAUDIOSTREAMCHANNEL pChanCenterLFE = &pMapping->paChannels[2]; /** @todo FIX! */
3624 PPDMAUDIOSTREAMCHANNEL pChanRear = &pMapping->paChannels[4]; /** @todo FIX! */
3625#endif
3626 int rc2;
3627
3628 void *pvDataFront = NULL;
3629 size_t cbDataFront;
3630#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3631 rc2 = hdaStreamChannelExtract(pChanFront, pvBuf, cbBuf);
3632 AssertRC(rc2);
3633
3634 rc2 = hdaStreamChannelAcquireData(&pChanFront->Data, pvDataFront, &cbDataFront);
3635 AssertRC(rc2);
3636#else
3637 /* Use stuff in the whole FIFO to use for the channel data. */
3638 pvDataFront = pvBuf;
3639 cbDataFront = cbBuf;
3640#endif
3641#ifdef VBOX_WITH_HDA_51_SURROUND
3642 void *pvDataCenterLFE;
3643 size_t cbDataCenterLFE;
3644 rc2 = hdaStreamChannelExtract(pChanCenterLFE, pvBuf, cbBuf);
3645 AssertRC(rc2);
3646
3647 rc2 = hdaStreamChannelAcquireData(&pChanCenterLFE->Data, pvDataCenterLFE, &cbDataCenterLFE);
3648 AssertRC(rc2);
3649
3650 void *pvDataRear;
3651 size_t cbDataRear;
3652 rc2 = hdaStreamChannelExtract(pChanRear, pvBuf, cbBuf);
3653 AssertRC(rc2);
3654
3655 rc2 = hdaStreamChannelAcquireData(&pChanRear->Data, pvDataRear, &cbDataRear);
3656 AssertRC(rc2);
3657#endif
3658 /*
3659 * Write data to according mixer sinks.
3660 */
3661 rc2 = AudioMixerSinkWrite(pThis->SinkFront.pMixSink, AUDMIXOP_COPY, pvDataFront, cbDataFront,
3662 NULL /* pcbWritten */);
3663 AssertRC(rc2);
3664#ifdef VBOX_WITH_HDA_51_SURROUND
3665 rc2 = AudioMixerSinkWrite(pThis->SinkCenterLFE, AUDMIXOP_COPY, pvDataCenterLFE, cbDataCenterLFE,
3666 NULL /* pcbWritten */);
3667 AssertRC(rc2);
3668 rc2 = AudioMixerSinkWrite(pThis->SinkRear, AUDMIXOP_COPY, pvDataRear, cbDataRear,
3669 NULL /* pcbWritten */);
3670 AssertRC(rc2);
3671#endif
3672
3673#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3674 hdaStreamChannelReleaseData(&pChanFront->Data);
3675#endif
3676#ifdef VBOX_WITH_HDA_51_SURROUND
3677 hdaStreamChannelReleaseData(&pChanCenterLFE->Data);
3678 hdaStreamChannelReleaseData(&pChanRear->Data);
3679#endif
3680
3681 /* Always report all data as being written;
3682 * backends who were not able to catch up have to deal with it themselves. */
3683 cbWritten = cbToWrite;
3684
3685 hdaBDLEUpdate(pBDLE, cbToWrite, cbWritten);
3686 }
3687 else
3688 {
3689 Assert(pBDLE->State.u32BufOff + cbWritten <= pBDLE->u32BufSize);
3690 pBDLE->State.u32BufOff += cbWritten;
3691 pBDLE->State.cbBelowFIFOW += cbWritten;
3692 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStream));
3693
3694 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
3695 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbAvail, NULL);
3696 rc = VINF_EOF;
3697 }
3698 }
3699
3700 //Assert(cbWritten <= pStream->u16FIFOS);
3701
3702 if (RT_SUCCESS(rc))
3703 {
3704 if (pcbWritten)
3705 *pcbWritten = cbWritten;
3706 }
3707
3708 if (RT_FAILURE(rc))
3709 LogFlowFunc(("Failed with %Rrc\n", rc));
3710
3711 return rc;
3712}
3713
3714/**
3715 * @interface_method_impl{HDACODEC,pfnReset}
3716 */
3717static DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
3718{
3719 PHDASTATE pThis = pCodec->pHDAState;
3720 NOREF(pThis);
3721 return VINF_SUCCESS;
3722}
3723
3724/**
3725 * Retrieves a corresponding sink for a given mixer control.
3726 * Returns NULL if no sink is found.
3727 *
3728 * @return PHDAMIXERSINK
3729 * @param pThis HDA state.
3730 * @param enmMixerCtl Mixer control to get the corresponding sink for.
3731 */
3732static PHDAMIXERSINK hdaMixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3733{
3734 PHDAMIXERSINK pSink;
3735
3736 switch (enmMixerCtl)
3737 {
3738 case PDMAUDIOMIXERCTL_VOLUME:
3739 /* Fall through is intentional. */
3740 case PDMAUDIOMIXERCTL_FRONT:
3741 pSink = &pThis->SinkFront;
3742 break;
3743#ifdef VBOX_WITH_HDA_51_SURROUND
3744 case PDMAUDIOMIXERCTL_CENTER_LFE:
3745 pSink = &pThis->SinkCenterLFE;
3746 break;
3747 case PDMAUDIOMIXERCTL_REAR:
3748 pSink = &pThis->SinkRear;
3749 break;
3750#endif
3751 case PDMAUDIOMIXERCTL_LINE_IN:
3752 pSink = &pThis->SinkLineIn;
3753 break;
3754#ifdef VBOX_WITH_HDA_MIC_IN
3755 case PDMAUDIOMIXERCTL_MIC_IN:
3756 pSink = &pThis->SinkMicIn;
3757 break;
3758#endif
3759 default:
3760 pSink = NULL;
3761 AssertMsgFailed(("Unhandled mixer control\n"));
3762 break;
3763 }
3764
3765 return pSink;
3766}
3767
3768static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PHDAMIXERSINK pSink, PPDMAUDIOSTREAMCFG pCfg)
3769{
3770 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3771 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
3772 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3773
3774 LogFunc(("Sink=%s, Stream=%s\n", pSink->pMixSink->pszName, pCfg->szName));
3775
3776 /* Update the sink's format. */
3777 PDMPCMPROPS PCMProps;
3778 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &PCMProps);
3779 if (RT_SUCCESS(rc))
3780 rc = AudioMixerSinkSetFormat(pSink->pMixSink, &PCMProps);
3781
3782 if (RT_FAILURE(rc))
3783 return rc;
3784
3785 PHDADRIVER pDrv;
3786 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3787 {
3788 int rc2 = VINF_SUCCESS;
3789 PHDAMIXERSTREAM pStream;
3790
3791 if (pCfg->enmDir == PDMAUDIODIR_IN)
3792 {
3793 switch (pCfg->DestSource.Source)
3794 {
3795 case PDMAUDIORECSOURCE_LINE:
3796 pStream = &pDrv->LineIn;
3797 break;
3798#ifdef VBOX_WITH_HDA_MIC_IN
3799 case PDMAUDIORECSOURCE_MIC:
3800 pStream = &pDrv->MicIn;
3801 break;
3802#endif
3803 default:
3804 rc2 = VERR_NOT_SUPPORTED;
3805 break;
3806 }
3807 }
3808 else if (pCfg->enmDir == PDMAUDIODIR_OUT)
3809 {
3810 switch (pCfg->DestSource.Dest)
3811 {
3812 case PDMAUDIOPLAYBACKDEST_FRONT:
3813 pStream = &pDrv->Front;
3814 break;
3815#ifdef VBOX_WITH_HDA_51_SURROUND
3816 case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
3817 pStream = &pDrv->CenterLFE;
3818 break;
3819 case PDMAUDIOPLAYBACKDEST_REAR:
3820 pStream = &pDrv->Rear;
3821 break;
3822#endif
3823 default:
3824 rc2 = VERR_NOT_SUPPORTED;
3825 break;
3826 }
3827 }
3828 else
3829 rc2 = VERR_NOT_SUPPORTED;
3830
3831 if (RT_SUCCESS(rc2))
3832 {
3833 AudioMixerSinkRemoveStream(pSink->pMixSink, pStream->pMixStrm);
3834
3835 AudioMixerStreamDestroy(pStream->pMixStrm);
3836 pStream->pMixStrm = NULL;
3837
3838 PAUDMIXSTREAM pMixStrm;
3839 rc2 = AudioMixerSinkCreateStream(pSink->pMixSink, pDrv->pConnector, pCfg, 0 /* fFlags */, &pMixStrm);
3840 if (RT_SUCCESS(rc2))
3841 {
3842 rc2 = AudioMixerSinkAddStream(pSink->pMixSink, pMixStrm);
3843 LogFlowFunc(("LUN#%RU8: Added \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pCfg->szName , rc2));
3844 }
3845
3846 if (RT_SUCCESS(rc2))
3847 pStream->pMixStrm = pMixStrm;
3848 }
3849
3850 if (RT_SUCCESS(rc))
3851 rc = rc2;
3852 }
3853
3854 LogFlowFuncLeaveRC(rc);
3855 return rc;
3856}
3857
3858/**
3859 * Adds a new audio stream to a specific mixer control.
3860 * Depending on the mixer control the stream then gets assigned to one of the internal
3861 * mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
3862 *
3863 * @return IPRT status code.
3864 * @param pThis HDA state.
3865 * @param enmMixerCtl Mixer control to assign new stream to.
3866 * @param pCfg Stream configuration for the new stream.
3867 */
3868static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
3869{
3870 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3871 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3872
3873 int rc;
3874
3875 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3876 if (pSink)
3877 {
3878 rc = hdaMixerAddStream(pThis, pSink, pCfg);
3879
3880 AssertPtr(pSink->pMixSink);
3881 LogFlowFunc(("Sink=%s, enmMixerCtl=%ld\n", pSink->pMixSink->pszName, enmMixerCtl));
3882 }
3883 else
3884 rc = VERR_NOT_FOUND;
3885
3886 LogFlowFuncLeaveRC(rc);
3887 return rc;
3888}
3889
3890/**
3891 * Removes a specified mixer control from the HDA's mixer.
3892 *
3893 * @return IPRT status code.
3894 * @param pThis HDA state.
3895 * @param enmMixerCtl Mixer control to remove.
3896 */
3897static DECLCALLBACK(int) hdaMixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3898{
3899 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3900
3901 int rc;
3902
3903 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3904 if (pSink)
3905 {
3906 PHDADRIVER pDrv;
3907 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3908 {
3909 PAUDMIXSTREAM pMixStream = NULL;
3910 switch (enmMixerCtl)
3911 {
3912 /*
3913 * Input.
3914 */
3915 case PDMAUDIOMIXERCTL_LINE_IN:
3916 pMixStream = pDrv->LineIn.pMixStrm;
3917 pDrv->LineIn.pMixStrm = NULL;
3918 break;
3919#ifdef VBOX_WITH_HDA_MIC_IN
3920 case PDMAUDIOMIXERCTL_MIC_IN:
3921 pMixStream = pDrv->MicIn.pMixStrm;
3922 pDrv->MicIn.pMixStrm = NULL;
3923 break;
3924#endif
3925 /*
3926 * Output.
3927 */
3928 case PDMAUDIOMIXERCTL_FRONT:
3929 pMixStream = pDrv->Front.pMixStrm;
3930 pDrv->Front.pMixStrm = NULL;
3931 break;
3932#ifdef VBOX_WITH_HDA_51_SURROUND
3933 case PDMAUDIOMIXERCTL_CENTER_LFE:
3934 pMixStream = pDrv->CenterLFE.pMixStrm;
3935 pDrv->CenterLFE.pMixStrm = NULL;
3936 break;
3937 case PDMAUDIOMIXERCTL_REAR:
3938 pMixStream = pDrv->Rear.pMixStrm;
3939 pDrv->Rear.pMixStrm = NULL;
3940 break;
3941#endif
3942 default:
3943 AssertMsgFailed(("Mixer control %ld not implemented\n", enmMixerCtl));
3944 break;
3945 }
3946
3947 if (pMixStream)
3948 {
3949 AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
3950 AudioMixerStreamDestroy(pMixStream);
3951
3952 pMixStream = NULL;
3953 }
3954 }
3955
3956 AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
3957 rc = VINF_SUCCESS;
3958 }
3959 else
3960 rc = VERR_NOT_FOUND;
3961
3962 LogFlowFunc(("enmMixerCtl=%ld, rc=%Rrc\n", enmMixerCtl, rc));
3963 return rc;
3964}
3965
3966/**
3967 * Sets a SDn stream number and channel to a particular mixer control.
3968 *
3969 * @returns IPRT status code.
3970 * @param pThis HDA State.
3971 * @param enmMixerCtl Mixer control to set SD stream number and channel for.
3972 * @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
3973 * @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
3974 */
3975static DECLCALLBACK(int) hdaMixerSetStream(PHDASTATE pThis,
3976 PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
3977{
3978 LogFlowFunc(("enmMixerCtl=%RU32, uSD=%RU8, uChannel=%RU8\n", enmMixerCtl, uSD, uChannel));
3979
3980 if (uSD == 0) /* Stream number 0 is reserved. */
3981 {
3982 LogFlowFunc(("Invalid SDn (%RU8) number for mixer control %ld, ignoring\n", uSD, enmMixerCtl));
3983 return VINF_SUCCESS;
3984 }
3985 /* uChannel is optional. */
3986
3987 /* SDn0 starts as 1. */
3988 Assert(uSD);
3989 uSD--;
3990
3991 int rc;
3992
3993 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3994 if (pSink)
3995 {
3996 if ( (uSD < HDA_MAX_SDI)
3997 && AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
3998 {
3999 uSD += HDA_MAX_SDI;
4000 }
4001
4002 LogFlowFunc(("%s: Setting to stream ID=%RU8, channel=%RU8, enmMixerCtl=%RU32\n",
4003 pSink->pMixSink->pszName, uSD, uChannel, enmMixerCtl));
4004
4005 Assert(uSD < HDA_MAX_STREAMS);
4006
4007 PHDASTREAM pStream = hdaStreamFromSD(pThis, uSD);
4008 if (pStream)
4009 {
4010 pSink->uSD = uSD;
4011 pSink->uChannel = uChannel;
4012
4013 /* Make sure that the stream also has this sink set. */
4014 hdaStreamAssignToSink(pStream, pSink);
4015
4016 rc = VINF_SUCCESS;
4017 }
4018 else
4019 {
4020 LogRel(("HDA: Guest wanted to assign invalid stream ID=%RU8 (channel %RU8) to mixer control %RU32, skipping\n",
4021 uSD, uChannel, enmMixerCtl));
4022 rc = VERR_INVALID_PARAMETER;
4023 }
4024 }
4025 else
4026 rc = VERR_NOT_FOUND;
4027
4028 LogFlowFuncLeaveRC(rc);
4029 return rc;
4030}
4031
4032/**
4033 * Sets the volume of a specified mixer control.
4034 *
4035 * @return IPRT status code.
4036 * @param pThis HDA State.
4037 * @param enmMixerCtl Mixer control to set volume for.
4038 * @param pVol Pointer to volume data to set.
4039 */
4040static DECLCALLBACK(int) hdaMixerSetVolume(PHDASTATE pThis,
4041 PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
4042{
4043 int rc;
4044
4045 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
4046 if (pSink)
4047 {
4048 /* Set the volume.
4049 * We assume that the codec already converted it to the correct range. */
4050 rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
4051 }
4052 else
4053 rc = VERR_NOT_FOUND;
4054
4055 LogFlowFuncLeaveRC(rc);
4056 return rc;
4057}
4058
4059#ifndef VBOX_WITH_AUDIO_CALLBACKS
4060
4061static void hdaTimerMaybeStart(PHDASTATE pThis)
4062{
4063 if (pThis->cStreamsActive == 0) /* Only start the timer if there are no active streams. */
4064 return;
4065
4066 if (!pThis->pTimer)
4067 return;
4068
4069 LogFlowFuncEnter();
4070
4071 LogFlowFunc(("Starting timer\n"));
4072
4073 /* Set timer flag. */
4074 ASMAtomicXchgBool(&pThis->fTimerActive, true);
4075
4076 /* Update current time timestamp. */
4077 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
4078
4079 /* Fire off timer. */
4080 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
4081}
4082
4083static void hdaTimerMaybeStop(PHDASTATE pThis)
4084{
4085 if (pThis->cStreamsActive) /* Some streams still active? Bail out. */
4086 return;
4087
4088 if (!pThis->pTimer)
4089 return;
4090
4091 LogFlowFunc(("Stopping timer\n"));
4092
4093 /* Set timer flag. */
4094 ASMAtomicXchgBool(&pThis->fTimerActive, false);
4095}
4096
4097static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
4098{
4099 PHDASTATE pThis = (PHDASTATE)pvUser;
4100 Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
4101 AssertPtr(pThis);
4102
4103 STAM_PROFILE_START(&pThis->StatTimer, a);
4104
4105 uint64_t cTicksNow = TMTimerGet(pTimer);
4106 uint64_t cTicksElapsed = cTicksNow - pThis->uTimerTS;
4107
4108 LogFlowFuncEnter();
4109
4110 /* Update current time timestamp. */
4111 pThis->uTimerTS = cTicksNow;
4112
4113 /* Flag indicating whether to kick the timer again for a
4114 * new data processing round. */
4115 bool fKickTimer = false;
4116
4117 PHDASTREAM pStreamLineIn = hdaGetStreamFromSink(pThis, &pThis->SinkLineIn);
4118#ifdef VBOX_WITH_HDA_MIC_IN
4119 PHDASTREAM pStreamMicIn = hdaGetStreamFromSink(pThis, &pThis->SinkMicIn);
4120#endif
4121 PHDASTREAM pStreamFront = hdaGetStreamFromSink(pThis, &pThis->SinkFront);
4122#ifdef VBOX_WITH_HDA_51_SURROUND
4123 /** @todo See note below. */
4124#endif
4125
4126 uint32_t cbToProcess;
4127 int rc = AudioMixerSinkUpdate(pThis->SinkLineIn.pMixSink);
4128 if (RT_SUCCESS(rc))
4129 {
4130 cbToProcess = AudioMixerSinkGetReadable(pThis->SinkLineIn.pMixSink);
4131 if (cbToProcess)
4132 {
4133 rc = hdaTransfer(pThis, pStreamLineIn, cbToProcess, NULL /* pcbProcessed */);
4134 fKickTimer = RT_SUCCESS(rc);
4135 }
4136 }
4137
4138#ifdef VBOX_WITH_HDA_MIC_IN
4139 rc = AudioMixerSinkUpdate(pThis->SinkMicIn.pMixSink);
4140 if (RT_SUCCESS(rc))
4141 {
4142 cbToProcess = AudioMixerSinkGetReadable(pThis->SinkMicIn.pMixSink);
4143 if (cbToProcess)
4144 {
4145 rc = hdaTransfer(pThis, pStreamMicIn, cbToProcess, NULL /* pcbProcessed */);
4146 fKickTimer = RT_SUCCESS(rc);
4147 }
4148 }
4149#endif
4150
4151#ifdef VBOX_WITH_HDA_51_SURROUND
4152 rc = AudioMixerSinkUpdate(pThis->SinkCenterLFE.pMixSink);
4153 if (RT_SUCCESS(rc))
4154 {
4155
4156 }
4157
4158 rc = AudioMixerSinkUpdate(pThis->SinkRear.pMixSink);
4159 if (RT_SUCCESS(rc))
4160 {
4161
4162 }
4163 /** @todo Check for stream interleaving and only call hdaTransfer() if required! */
4164
4165 /*
4166 * Only call hdaTransfer if CenterLFE and/or Rear are on different SDs,
4167 * otherwise we have to use the interleaved streams support for getting the data
4168 * out of the Front sink (depending on the mapping layout).
4169 */
4170#endif
4171 rc = AudioMixerSinkUpdate(pThis->SinkFront.pMixSink);
4172 if (RT_SUCCESS(rc))
4173 {
4174 cbToProcess = AudioMixerSinkGetWritable(pThis->SinkFront.pMixSink);
4175 if (cbToProcess)
4176 {
4177 rc = hdaTransfer(pThis, pStreamFront, cbToProcess, NULL /* pcbProcessed */);
4178 fKickTimer = RT_SUCCESS(rc);
4179 }
4180 }
4181
4182 if ( ASMAtomicReadBool(&pThis->fTimerActive)
4183 || fKickTimer)
4184 {
4185 /* Kick the timer again. */
4186 uint64_t cTicks = pThis->cTimerTicks;
4187 /** @todo adjust cTicks down by now much cbOutMin represents. */
4188 TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
4189 }
4190
4191 LogFlowFuncLeave();
4192
4193 STAM_PROFILE_STOP(&pThis->StatTimer, a);
4194}
4195
4196#else /* VBOX_WITH_AUDIO_CALLBACKS */
4197
4198static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4199{
4200 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
4201 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4202 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4203 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4204 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4205
4206 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4207 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4208
4209 PPDMAUDIOCALLBACKDATAIN pData = (PPDMAUDIOCALLBACKDATAIN)pvUser;
4210 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAIN), VERR_INVALID_PARAMETER);
4211
4212 return hdaTransfer(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
4213}
4214
4215static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4216{
4217 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
4218 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4219 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4220 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4221 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4222
4223 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4224 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4225
4226 PPDMAUDIOCALLBACKDATAOUT pData = (PPDMAUDIOCALLBACKDATAOUT)pvUser;
4227 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAOUT), VERR_INVALID_PARAMETER);
4228
4229 PHDASTATE pThis = pCtx->pThis;
4230
4231 int rc = hdaTransfer(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
4232 if ( RT_SUCCESS(rc)
4233 && pData->cbOutWritten)
4234 {
4235 PHDADRIVER pDrv;
4236 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4237 {
4238 uint32_t cSamplesPlayed;
4239 int rc2 = pDrv->pConnector->pfnPlay(pDrv->pConnector, &cSamplesPlayed);
4240 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
4241 }
4242 }
4243}
4244#endif /* VBOX_WITH_AUDIO_CALLBACKS */
4245
4246static int hdaTransfer(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToProcess, uint32_t *pcbProcessed)
4247{
4248 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4249 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4250 /* pcbProcessed is optional. */
4251
4252 if (ASMAtomicReadBool(&pThis->fInReset)) /* HDA controller in reset mode? Bail out. */
4253 {
4254 LogFlowFunc(("HDA in reset mode, skipping\n"));
4255
4256 if (pcbProcessed)
4257 *pcbProcessed = 0;
4258 return VINF_SUCCESS;
4259 }
4260
4261 bool fProceed = true;
4262 int rc = RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
4263 if (RT_FAILURE(rc))
4264 return rc;
4265
4266 Log3Func(("[SD%RU8] fActive=%RTbool\n", pStream->u8SD, pStream->State.fActive));
4267
4268 /* Stop request received? */
4269 if ( !pStream->State.fActive
4270 || pStream->State.fDoStop)
4271 {
4272 pStream->State.fActive = false;
4273
4274 rc = RTSemEventSignal(pStream->State.hStateChangedEvent);
4275 AssertRC(rc);
4276
4277 fProceed = false;
4278 }
4279 /* Is the stream not in a running state currently? */
4280 else if (!(HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)))
4281 fProceed = false;
4282 /* Nothing to process? */
4283 else if (!cbToProcess)
4284 fProceed = false;
4285
4286 if ((HDA_STREAM_REG(pThis, STS, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
4287 {
4288 Log3Func(("[SD%RU8]: BCIS set\n", pStream->u8SD));
4289 fProceed = false;
4290 }
4291
4292 if (!fProceed)
4293 {
4294 Log3Func(("[SD%RU8]: Skipping\n", pStream->u8SD));
4295
4296 rc = RTSemMutexRelease(pStream->State.hMtx);
4297 AssertRC(rc);
4298
4299 if (pcbProcessed)
4300 *pcbProcessed = 0;
4301 return VINF_SUCCESS;
4302 }
4303
4304 /* Sanity checks. */
4305 Assert(pStream->u8SD <= HDA_MAX_STREAMS);
4306 Assert(pStream->u64BDLBase);
4307 Assert(pStream->u32CBL);
4308
4309 /* State sanity checks. */
4310 Assert(pStream->State.fInReset == false);
4311
4312 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
4313 Assert(u32LPIB <= pStream->u32CBL);
4314
4315 bool fInterrupt = false;
4316
4317#ifdef DEBUG_andy
4318//# define DEBUG_SIMPLE
4319#endif
4320
4321#ifdef DEBUG_SIMPLE
4322 uint8_t u8FIFO[_16K+1];
4323 size_t u8FIFOff = 0;
4324#endif
4325
4326 uint32_t cbLeft = cbToProcess;
4327 uint32_t cbTotal = 0;
4328 uint32_t cbChunk = 0;
4329 uint32_t cbChunkProcessed = 0;
4330
4331 /* Set the FIFORDY bit on the stream while doing the transfer. */
4332 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
4333
4334 while (cbLeft)
4335 {
4336 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
4337 if (hdaStreamNeedsNextBDLE(pThis, pStream))
4338 {
4339 rc = hdaStreamGetNextBDLE(pThis, pStream);
4340 if (RT_FAILURE(rc))
4341 break;
4342 }
4343
4344 cbChunk = hdaStreamGetTransferSize(pThis, pStream, cbLeft);
4345 cbChunkProcessed = 0;
4346
4347 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
4348 rc = hdaReadAudio(pThis, pStream, cbChunk, &cbChunkProcessed);
4349 else
4350 {
4351#ifndef DEBUG_SIMPLE
4352 rc = hdaWriteAudio(pThis, pStream, cbChunk, &cbChunkProcessed);
4353#else
4354 void *pvBuf = u8FIFO + u8FIFOff;
4355 int32_t cbBuf = cbChunk;
4356
4357 PHDABDLE pBDLE = &pStream->State.BDLE;
4358
4359 if (cbBuf)
4360 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
4361 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
4362 pvBuf, cbBuf);
4363
4364 cbChunkProcessed = cbChunk;
4365
4366 hdaBDLEUpdate(pBDLE, cbChunkProcessed, cbChunkProcessed);
4367
4368 u8FIFOff += cbChunkProcessed;
4369 Assert((u8FIFOff & 1) == 0);
4370 Assert(u8FIFOff <= sizeof(u8FIFO));
4371#endif
4372 }
4373
4374 if (RT_FAILURE(rc))
4375 break;
4376
4377 hdaStreamTransferUpdate(pThis, pStream, cbChunkProcessed);
4378
4379 Assert(cbLeft >= cbChunkProcessed);
4380 cbLeft -= cbChunkProcessed;
4381 cbTotal += cbChunkProcessed;
4382
4383 if (rc == VINF_EOF)
4384 break;
4385
4386 if (hdaStreamTransferIsComplete(pThis, pStream, &fInterrupt))
4387 break;
4388 }
4389
4390 /* Remove the FIFORDY bit again. */
4391 HDA_STREAM_REG(pThis, STS, pStream->u8SD) &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
4392
4393 LogFlowFunc(("[SD%RU8]: %RU32 / %RU32, rc=%Rrc\n", pStream->u8SD, cbTotal, cbToProcess, rc));
4394
4395#ifdef DEBUG_SIMPLE
4396# ifdef HDA_DEBUG_DUMP_PCM_DATA
4397 RTFILE fh;
4398 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaWriteAudio.pcm",
4399 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4400 RTFileWrite(fh, u8FIFO, u8FIFOff, NULL);
4401 RTFileClose(fh);
4402# endif
4403
4404 AudioMixerSinkWrite(pThis->SinkFront.pMixSink, AUDMIXOP_COPY, u8FIFO, u8FIFOff,
4405 NULL /* pcbWritten */);
4406#endif /* DEBUG_SIMPLE */
4407
4408 if (fInterrupt)
4409 {
4410 /**
4411 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
4412 * last byte of data for the current descriptor has been fetched
4413 * from memory and put into the DMA FIFO.
4414 *
4415 * Speech synthesis works fine on Mac Guest if this bit isn't set
4416 * but in general sound quality gets worse.
4417 *
4418 * This must be set in *any* case.
4419 */
4420 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
4421 Log3Func(("[SD%RU8]: BCIS: Set\n", pStream->u8SD));
4422
4423 hdaProcessInterrupt(pThis);
4424 }
4425
4426 if (RT_SUCCESS(rc))
4427 {
4428 if (pcbProcessed)
4429 *pcbProcessed = cbTotal;
4430 }
4431
4432 int rc2 = RTSemMutexRelease(pStream->State.hMtx);
4433 if (RT_SUCCESS(rc))
4434 rc = rc2;
4435
4436 return rc;
4437}
4438#endif /* IN_RING3 */
4439
4440/* MMIO callbacks */
4441
4442/**
4443 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
4444 *
4445 * @note During implementation, we discovered so-called "forgotten" or "hole"
4446 * registers whose description is not listed in the RPM, datasheet, or
4447 * spec.
4448 */
4449PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4450{
4451 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4452 int rc;
4453
4454 /*
4455 * Look up and log.
4456 */
4457 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4458 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
4459#ifdef LOG_ENABLED
4460 unsigned const cbLog = cb;
4461 uint32_t offRegLog = offReg;
4462#endif
4463
4464 Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
4465 Assert(cb == 4); Assert((offReg & 3) == 0);
4466
4467 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4468 LogFunc(("Access to registers except GCTL is blocked while reset\n"));
4469
4470 if (idxRegDsc == -1)
4471 LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
4472
4473 if (idxRegDsc != -1)
4474 {
4475 /* ASSUMES gapless DWORD at end of map. */
4476 if (g_aHdaRegMap[idxRegDsc].size == 4)
4477 {
4478 /*
4479 * Straight forward DWORD access.
4480 */
4481 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
4482 Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
4483 }
4484 else
4485 {
4486 /*
4487 * Multi register read (unless there are trailing gaps).
4488 * ASSUMES that only DWORD reads have sideeffects.
4489 */
4490 uint32_t u32Value = 0;
4491 unsigned cbLeft = 4;
4492 do
4493 {
4494 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
4495 uint32_t u32Tmp = 0;
4496
4497 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
4498 Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
4499 if (rc != VINF_SUCCESS)
4500 break;
4501 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
4502
4503 cbLeft -= cbReg;
4504 offReg += cbReg;
4505 idxRegDsc++;
4506 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
4507
4508 if (rc == VINF_SUCCESS)
4509 *(uint32_t *)pv = u32Value;
4510 else
4511 Assert(!IOM_SUCCESS(rc));
4512 }
4513 }
4514 else
4515 {
4516 rc = VINF_IOM_MMIO_UNUSED_FF;
4517 Log3Func(("\tHole at %x is accessed for read\n", offReg));
4518 }
4519
4520 /*
4521 * Log the outcome.
4522 */
4523#ifdef LOG_ENABLED
4524 if (cbLog == 4)
4525 Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
4526 else if (cbLog == 2)
4527 Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
4528 else if (cbLog == 1)
4529 Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
4530#endif
4531 return rc;
4532}
4533
4534
4535DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
4536{
4537 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4538 {
4539 LogRel2(("HDA: Warning: Access to register 0x%x is blocked while reset\n", idxRegDsc));
4540 return VINF_SUCCESS;
4541 }
4542
4543 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4544#ifdef LOG_ENABLED
4545 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
4546#endif
4547 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
4548 Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
4549 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
4550 return rc;
4551}
4552
4553
4554/**
4555 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
4556 */
4557PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
4558{
4559 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4560 int rc;
4561
4562 /*
4563 * The behavior of accesses that aren't aligned on natural boundraries is
4564 * undefined. Just reject them outright.
4565 */
4566 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
4567 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
4568 if (GCPhysAddr & (cb - 1))
4569 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
4570
4571 /*
4572 * Look up and log the access.
4573 */
4574 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4575 int idxRegDsc = hdaRegLookup(pThis, offReg);
4576 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
4577 uint64_t u64Value;
4578 if (cb == 4) u64Value = *(uint32_t const *)pv;
4579 else if (cb == 2) u64Value = *(uint16_t const *)pv;
4580 else if (cb == 1) u64Value = *(uint8_t const *)pv;
4581 else if (cb == 8) u64Value = *(uint64_t const *)pv;
4582 else
4583 {
4584 u64Value = 0; /* shut up gcc. */
4585 AssertReleaseMsgFailed(("%u\n", cb));
4586 }
4587
4588#ifdef LOG_ENABLED
4589 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
4590 if (idxRegDsc == -1)
4591 Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
4592 else if (cb == 4)
4593 Log3Func(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4594 else if (cb == 2)
4595 Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4596 else if (cb == 1)
4597 Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4598
4599 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
4600 Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
4601#endif
4602
4603 /*
4604 * Try for a direct hit first.
4605 */
4606 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
4607 {
4608 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
4609 Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
4610 }
4611 /*
4612 * Partial or multiple register access, loop thru the requested memory.
4613 */
4614 else
4615 {
4616 /*
4617 * If it's an access beyond the start of the register, shift the input
4618 * value and fill in missing bits. Natural alignment rules means we
4619 * will only see 1 or 2 byte accesses of this kind, so no risk of
4620 * shifting out input values.
4621 */
4622 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
4623 {
4624 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
4625 offReg -= cbBefore;
4626 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4627 u64Value <<= cbBefore * 8;
4628 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
4629 Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
4630 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
4631 }
4632
4633 /* Loop thru the write area, it may cover multiple registers. */
4634 rc = VINF_SUCCESS;
4635 for (;;)
4636 {
4637 uint32_t cbReg;
4638 if (idxRegDsc != -1)
4639 {
4640 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4641 cbReg = g_aHdaRegMap[idxRegDsc].size;
4642 if (cb < cbReg)
4643 {
4644 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
4645 Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
4646 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
4647 }
4648 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
4649 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
4650 Log3Func(("\t%#x -> %#x\n", u32LogOldVal, pThis->au32Regs[idxRegMem]));
4651 }
4652 else
4653 {
4654 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
4655 cbReg = 1;
4656 }
4657 if (rc != VINF_SUCCESS)
4658 break;
4659 if (cbReg >= cb)
4660 break;
4661
4662 /* Advance. */
4663 offReg += cbReg;
4664 cb -= cbReg;
4665 u64Value >>= cbReg * 8;
4666 if (idxRegDsc == -1)
4667 idxRegDsc = hdaRegLookup(pThis, offReg);
4668 else
4669 {
4670 idxRegDsc++;
4671 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
4672 || g_aHdaRegMap[idxRegDsc].offset != offReg)
4673 {
4674 idxRegDsc = -1;
4675 }
4676 }
4677 }
4678 }
4679
4680 return rc;
4681}
4682
4683
4684/* PCI callback. */
4685
4686#ifdef IN_RING3
4687/**
4688 * @callback_method_impl{FNPCIIOREGIONMAP}
4689 */
4690static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
4691 PCIADDRESSSPACE enmType)
4692{
4693 PPDMDEVINS pDevIns = pPciDev->pDevIns;
4694 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
4695 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
4696 int rc;
4697
4698 /*
4699 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
4700 *
4701 * Let IOM talk DWORDs when reading, saves a lot of complications. On
4702 * writing though, we have to do it all ourselves because of sideeffects.
4703 */
4704 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
4705 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
4706 IOMMMIO_FLAGS_READ_DWORD
4707 | IOMMMIO_FLAGS_WRITE_PASSTHRU,
4708 hdaMMIOWrite, hdaMMIORead, "HDA");
4709
4710 if (RT_FAILURE(rc))
4711 return rc;
4712
4713 if (pThis->fR0Enabled)
4714 {
4715 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
4716 "hdaMMIOWrite", "hdaMMIORead");
4717 if (RT_FAILURE(rc))
4718 return rc;
4719 }
4720
4721 if (pThis->fRCEnabled)
4722 {
4723 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
4724 "hdaMMIOWrite", "hdaMMIORead");
4725 if (RT_FAILURE(rc))
4726 return rc;
4727 }
4728
4729 pThis->MMIOBaseAddr = GCPhysAddress;
4730 return VINF_SUCCESS;
4731}
4732
4733
4734/* Saved state callbacks. */
4735
4736static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
4737{
4738 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4739
4740 LogFlowFunc(("[SD%RU8]\n", pStrm->u8SD));
4741
4742 /* Save stream ID. */
4743 int rc = SSMR3PutU8(pSSM, pStrm->u8SD);
4744 AssertRCReturn(rc, rc);
4745 Assert(pStrm->u8SD <= HDA_MAX_STREAMS);
4746
4747 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields6, NULL);
4748 AssertRCReturn(rc, rc);
4749
4750#ifdef DEBUG /* Sanity checks. */
4751 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrm->u8SD),
4752 HDA_STREAM_REG(pThis, BDPU, pStrm->u8SD));
4753 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStrm->u8SD);
4754 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStrm->u8SD);
4755
4756 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
4757
4758 Assert(u64BaseDMA == pStrm->u64BDLBase);
4759 Assert(u16LVI == pStrm->u16LVI);
4760 Assert(u32CBL == pStrm->u32CBL);
4761#endif
4762
4763 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
4764 0 /*fFlags*/, g_aSSMBDLEFields6, NULL);
4765 AssertRCReturn(rc, rc);
4766
4767 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
4768 0 /*fFlags*/, g_aSSMBDLEStateFields6, NULL);
4769 AssertRCReturn(rc, rc);
4770
4771#ifdef DEBUG /* Sanity checks. */
4772 PHDABDLE pBDLE = &pStrm->State.BDLE;
4773 if (u64BaseDMA)
4774 {
4775 Assert(pStrm->State.uCurBDLE <= u16LVI + 1);
4776
4777 HDABDLE curBDLE;
4778 rc = hdaBDLEFetch(pThis, &curBDLE, u64BaseDMA, pStrm->State.uCurBDLE);
4779 AssertRC(rc);
4780
4781 Assert(curBDLE.u32BufSize == pBDLE->u32BufSize);
4782 Assert(curBDLE.u64BufAdr == pBDLE->u64BufAdr);
4783 Assert(curBDLE.fIntOnCompletion == pBDLE->fIntOnCompletion);
4784 }
4785 else
4786 {
4787 Assert(pBDLE->u64BufAdr == 0);
4788 Assert(pBDLE->u32BufSize == 0);
4789 }
4790#endif
4791 return rc;
4792}
4793
4794/**
4795 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4796 */
4797static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4798{
4799 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4800
4801 /* Save Codec nodes states. */
4802 hdaCodecSaveState(pThis->pCodec, pSSM);
4803
4804 /* Save MMIO registers. */
4805 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
4806 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4807
4808 /* Save number of streams. */
4809 SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
4810
4811 /* Save stream states. */
4812 int rc;
4813 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4814 {
4815 rc = hdaSaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
4816 AssertRCReturn(rc, rc);
4817 }
4818
4819 return rc;
4820}
4821
4822
4823/**
4824 * @callback_method_impl{FNSSMDEVLOADEXEC}
4825 */
4826static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4827{
4828 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4829
4830 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
4831
4832 LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
4833
4834 /*
4835 * Load Codec nodes states.
4836 */
4837 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
4838 if (RT_FAILURE(rc))
4839 {
4840 LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
4841 return rc;
4842 }
4843
4844 /*
4845 * Load MMIO registers.
4846 */
4847 uint32_t cRegs;
4848 switch (uVersion)
4849 {
4850 case HDA_SSM_VERSION_1:
4851 /* Starting with r71199, we would save 112 instead of 113
4852 registers due to some code cleanups. This only affected trunk
4853 builds in the 4.1 development period. */
4854 cRegs = 113;
4855 if (SSMR3HandleRevision(pSSM) >= 71199)
4856 {
4857 uint32_t uVer = SSMR3HandleVersion(pSSM);
4858 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
4859 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
4860 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
4861 cRegs = 112;
4862 }
4863 break;
4864
4865 case HDA_SSM_VERSION_2:
4866 case HDA_SSM_VERSION_3:
4867 cRegs = 112;
4868 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
4869 break;
4870
4871 /* Since version 4 we store the register count to stay flexible. */
4872 case HDA_SSM_VERSION_4:
4873 case HDA_SSM_VERSION_5:
4874 case HDA_SSM_VERSION:
4875 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
4876 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
4877 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
4878 break;
4879
4880 default:
4881 LogRel(("HDA: Unsupported / too new saved state version (%RU32)\n", uVersion));
4882 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4883 }
4884
4885 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
4886 {
4887 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4888 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
4889 }
4890 else
4891 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
4892
4893 /*
4894 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
4895 * *every* BDLE state, whereas it only needs to be stored
4896 * *once* for every stream. Most of the BDLE state we can
4897 * get out of the registers anyway, so just ignore those values.
4898 *
4899 * Also, only the current BDLE was saved, regardless whether
4900 * there were more than one (and there are at least two entries,
4901 * according to the spec).
4902 */
4903#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
4904 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
4905 AssertRCReturn(rc, rc); \
4906 rc = SSMR3GetU64(pSSM, &x.u64BufAdr); /* u64BdleCviAddr */ \
4907 AssertRCReturn(rc, rc); \
4908 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
4909 AssertRCReturn(rc, rc); \
4910 rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
4911 AssertRCReturn(rc, rc); \
4912 rc = SSMR3GetU32(pSSM, &x.u32BufSize); /* u32BdleCviLen */ \
4913 AssertRCReturn(rc, rc); \
4914 rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
4915 AssertRCReturn(rc, rc); \
4916 rc = SSMR3GetBool(pSSM, &x.fIntOnCompletion); /* fBdleCviIoc */ \
4917 AssertRCReturn(rc, rc); \
4918 rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
4919 AssertRCReturn(rc, rc); \
4920 rc = SSMR3GetMem(pSSM, &x.State.au8FIFO, sizeof(x.State.au8FIFO)); \
4921 AssertRCReturn(rc, rc); \
4922 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
4923 AssertRCReturn(rc, rc); \
4924
4925 /*
4926 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
4927 */
4928 switch (uVersion)
4929 {
4930 case HDA_SSM_VERSION_1:
4931 case HDA_SSM_VERSION_2:
4932 case HDA_SSM_VERSION_3:
4933 case HDA_SSM_VERSION_4:
4934 {
4935 /* Only load the internal states.
4936 * The rest will be initialized from the saved registers later. */
4937
4938 /* Note 1: Only the *current* BDLE for a stream was saved! */
4939 /* Note 2: The stream's saving order is/was fixed, so don't touch! */
4940
4941 /* Output */
4942 PHDASTREAM pStream = &pThis->aStreams[4];
4943 rc = hdaStreamInit(pThis, pStream, 4 /* Stream descriptor, hardcoded */);
4944 if (RT_FAILURE(rc))
4945 break;
4946 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
4947 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
4948
4949 /* Microphone-In */
4950 pStream = &pThis->aStreams[2];
4951 rc = hdaStreamInit(pThis, pStream, 2 /* Stream descriptor, hardcoded */);
4952 if (RT_FAILURE(rc))
4953 break;
4954 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
4955 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
4956
4957 /* Line-In */
4958 pStream = &pThis->aStreams[0];
4959 rc = hdaStreamInit(pThis, pStream, 0 /* Stream descriptor, hardcoded */);
4960 if (RT_FAILURE(rc))
4961 break;
4962 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
4963 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
4964 break;
4965 }
4966
4967 /* Since v5 we support flexible stream and BDLE counts. */
4968 case HDA_SSM_VERSION_5:
4969 case HDA_SSM_VERSION:
4970 {
4971 uint32_t cStreams;
4972 rc = SSMR3GetU32(pSSM, &cStreams);
4973 if (RT_FAILURE(rc))
4974 break;
4975
4976 LogRel2(("hdaLoadExec: cStreams=%RU32\n", cStreams));
4977
4978 /* Load stream states. */
4979 for (uint32_t i = 0; i < cStreams; i++)
4980 {
4981 uint8_t uSD;
4982 rc = SSMR3GetU8(pSSM, &uSD);
4983 if (RT_FAILURE(rc))
4984 break;
4985
4986 PHDASTREAM pStrm = hdaStreamFromSD(pThis, uSD);
4987 HDASTREAM StreamDummy;
4988
4989 if (!pStrm)
4990 {
4991 RT_ZERO(StreamDummy);
4992 pStrm = &StreamDummy;
4993 LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uSD));
4994 break;
4995 }
4996
4997 rc = hdaStreamInit(pThis, pStrm, uSD);
4998 if (RT_FAILURE(rc))
4999 {
5000 LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uSD, rc));
5001 break;
5002 }
5003
5004 if (uVersion == HDA_SSM_VERSION_5)
5005 {
5006 /* Get the current BDLE entry and skip the rest. */
5007 uint16_t cBDLE;
5008
5009 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5010 AssertRC(rc);
5011 rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
5012 AssertRC(rc);
5013 rc = SSMR3GetU16(pSSM, &pStrm->State.uCurBDLE); /* uCurBDLE */
5014 AssertRC(rc);
5015 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5016 AssertRC(rc);
5017
5018 uint32_t u32BDLEIndex;
5019 for (uint16_t a = 0; a < cBDLE; a++)
5020 {
5021 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5022 AssertRC(rc);
5023 rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
5024 AssertRC(rc);
5025
5026 /* Does the current BDLE index match the current BDLE to process? */
5027 if (u32BDLEIndex == pStrm->State.uCurBDLE)
5028 {
5029 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
5030 AssertRC(rc);
5031 rc = SSMR3GetMem(pSSM,
5032 &pStrm->State.BDLE.State.au8FIFO,
5033 sizeof(pStrm->State.BDLE.State.au8FIFO)); /* au8FIFO */
5034 AssertRC(rc);
5035 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.u32BufOff); /* u32BufOff */
5036 AssertRC(rc);
5037 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5038 AssertRC(rc);
5039 }
5040 else /* Skip not current BDLEs. */
5041 {
5042 rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
5043 + sizeof(uint8_t) * 256 /* au8FIFO */
5044 + sizeof(uint32_t) /* u32BufOff */
5045 + sizeof(uint32_t)); /* End marker */
5046 AssertRC(rc);
5047 }
5048 }
5049 }
5050 else
5051 {
5052 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE),
5053 0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
5054 if (RT_FAILURE(rc))
5055 break;
5056
5057 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
5058 0 /* fFlags */, g_aSSMBDLEFields6, NULL);
5059 if (RT_FAILURE(rc))
5060 break;
5061
5062 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
5063 0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
5064 if (RT_FAILURE(rc))
5065 break;
5066 }
5067 }
5068 break;
5069 }
5070
5071 default:
5072 AssertReleaseFailed(); /* Never reached. */
5073 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5074 }
5075
5076#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
5077
5078 if (RT_SUCCESS(rc))
5079 {
5080 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
5081 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
5082 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
5083
5084 /* Also make sure to update the DMA position bit if this was enabled when saving the state. */
5085 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
5086 }
5087
5088 if (RT_SUCCESS(rc))
5089 {
5090 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5091 {
5092 PHDASTREAM pStream = hdaStreamFromSD(pThis, i);
5093 if (pStream)
5094 {
5095 /* Deactive first. */
5096 int rc2 = hdaStreamSetActive(pThis, pStream, false);
5097 AssertRC(rc2);
5098
5099 bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
5100
5101 /* Activate, if needed. */
5102 rc2 = hdaStreamSetActive(pThis, pStream, fActive);
5103 AssertRC(rc2);
5104 }
5105 }
5106 }
5107
5108 if (RT_FAILURE(rc))
5109 LogRel(("HDA: Failed loading device state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5110
5111 LogFlowFuncLeaveRC(rc);
5112 return rc;
5113}
5114
5115#ifdef DEBUG
5116/* Debug and log type formatters. */
5117
5118/**
5119 * @callback_method_impl{FNRTSTRFORMATTYPE}
5120 */
5121static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5122 const char *pszType, void const *pvValue,
5123 int cchWidth, int cchPrecision, unsigned fFlags,
5124 void *pvUser)
5125{
5126 PHDABDLE pBDLE = (PHDABDLE)pvValue;
5127 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5128 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
5129 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW, pBDLE->fIntOnCompletion,
5130 pBDLE->u32BufSize, pBDLE->u64BufAdr);
5131}
5132
5133/**
5134 * @callback_method_impl{FNRTSTRFORMATTYPE}
5135 */
5136static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5137 const char *pszType, void const *pvValue,
5138 int cchWidth, int cchPrecision, unsigned fFlags,
5139 void *pvUser)
5140{
5141 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
5142 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5143 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
5144 uSDCTL,
5145 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
5146 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
5147 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
5148 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
5149 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
5150 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
5151 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
5152 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
5153}
5154
5155/**
5156 * @callback_method_impl{FNRTSTRFORMATTYPE}
5157 */
5158static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5159 const char *pszType, void const *pvValue,
5160 int cchWidth, int cchPrecision, unsigned fFlags,
5161 void *pvUser)
5162{
5163 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
5164 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, hdaSDFIFOSToBytes(uSDFIFOS));
5165}
5166
5167/**
5168 * @callback_method_impl{FNRTSTRFORMATTYPE}
5169 */
5170static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5171 const char *pszType, void const *pvValue,
5172 int cchWidth, int cchPrecision, unsigned fFlags,
5173 void *pvUser)
5174{
5175 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
5176 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
5177}
5178
5179/**
5180 * @callback_method_impl{FNRTSTRFORMATTYPE}
5181 */
5182static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5183 const char *pszType, void const *pvValue,
5184 int cchWidth, int cchPrecision, unsigned fFlags,
5185 void *pvUser)
5186{
5187 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
5188 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5189 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
5190 uSdSts,
5191 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
5192 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
5193 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
5194 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
5195}
5196
5197static int hdaDbgLookupRegByName(PHDASTATE pThis, const char *pszArgs)
5198{
5199 int iReg = 0;
5200 for (; iReg < HDA_NUM_REGS; ++iReg)
5201 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
5202 return iReg;
5203 return -1;
5204}
5205
5206
5207static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
5208{
5209 Assert( pThis
5210 && iHdaIndex >= 0
5211 && iHdaIndex < HDA_NUM_REGS);
5212 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
5213}
5214
5215/**
5216 * @callback_method_impl{FNDBGFHANDLERDEV}
5217 */
5218static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5219{
5220 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5221 int iHdaRegisterIndex = hdaDbgLookupRegByName(pThis, pszArgs);
5222 if (iHdaRegisterIndex != -1)
5223 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5224 else
5225 {
5226 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
5227 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5228 }
5229}
5230
5231static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5232{
5233 Assert( pThis
5234 && iIdx >= 0
5235 && iIdx < HDA_MAX_STREAMS);
5236
5237 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5238
5239 pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
5240 pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
5241 pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
5242 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
5243 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
5244 pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStrm->State.BDLE);
5245}
5246
5247static void hdaDbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5248{
5249 Assert( pThis
5250 && iIdx >= 0
5251 && iIdx < HDA_MAX_STREAMS);
5252
5253 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5254 const PHDABDLE pBDLE = &pStrm->State.BDLE;
5255
5256 pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
5257 pHlp->pfnPrintf(pHlp, "\t%R[bdle]\n", pBDLE);
5258
5259 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
5260 HDA_STREAM_REG(pThis, BDPU, iIdx));
5261 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
5262 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
5263
5264 if (!u64BaseDMA)
5265 return;
5266
5267 uint32_t cbBDLE = 0;
5268 for (uint16_t i = 0; i < u16LVI + 1; i++)
5269 {
5270 uint8_t bdle[16]; /** @todo Use a define. */
5271 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * 16, bdle, 16); /** @todo Use a define. */
5272
5273 uint64_t addr = *(uint64_t *)bdle;
5274 uint32_t len = *(uint32_t *)&bdle[8];
5275 uint32_t ioc = *(uint32_t *)&bdle[12];
5276
5277 pHlp->pfnPrintf(pHlp, "\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
5278 i, addr, len, RT_BOOL(ioc & 0x1));
5279
5280 cbBDLE += len;
5281 }
5282
5283 pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
5284
5285 pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", pThis->u64DPBase);
5286 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
5287 {
5288 pHlp->pfnPrintf(pHlp, "No counters found\n");
5289 return;
5290 }
5291
5292 for (int i = 0; i < u16LVI + 1; i++)
5293 {
5294 uint32_t uDMACnt;
5295 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
5296 &uDMACnt, sizeof(uDMACnt));
5297
5298 pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
5299 }
5300}
5301
5302static int hdaDbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
5303{
5304 /** @todo Add args parsing. */
5305 return -1;
5306}
5307
5308/**
5309 * @callback_method_impl{FNDBGFHANDLERDEV}
5310 */
5311static DECLCALLBACK(void) hdaDbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5312{
5313 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5314 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5315 if (iHdaStreamdex != -1)
5316 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5317 else
5318 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5319 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5320}
5321
5322/**
5323 * @callback_method_impl{FNDBGFHANDLERDEV}
5324 */
5325static DECLCALLBACK(void) hdaDbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5326{
5327 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5328 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5329 if (iHdaStreamdex != -1)
5330 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5331 else
5332 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5333 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5334}
5335
5336/**
5337 * @callback_method_impl{FNDBGFHANDLERDEV}
5338 */
5339static DECLCALLBACK(void) hdaDbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5340{
5341 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5342
5343 if (pThis->pCodec->pfnDbgListNodes)
5344 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
5345 else
5346 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5347}
5348
5349/**
5350 * @callback_method_impl{FNDBGFHANDLERDEV}
5351 */
5352static DECLCALLBACK(void) hdaDbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5353{
5354 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5355
5356 if (pThis->pCodec->pfnDbgSelector)
5357 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
5358 else
5359 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5360}
5361
5362/**
5363 * @callback_method_impl{FNDBGFHANDLERDEV}
5364 */
5365static DECLCALLBACK(void) hdaDbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5366{
5367 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5368
5369 if (pThis->pMixer)
5370 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
5371 else
5372 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
5373}
5374#endif /* DEBUG */
5375
5376/* PDMIBASE */
5377
5378/**
5379 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5380 */
5381static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
5382{
5383 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
5384 Assert(&pThis->IBase == pInterface);
5385
5386 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5387 return NULL;
5388}
5389
5390
5391/* PDMDEVREG */
5392
5393/**
5394 * Reset notification.
5395 *
5396 * @returns VBox status code.
5397 * @param pDevIns The device instance data.
5398 *
5399 * @remark The original sources didn't install a reset handler, but it seems to
5400 * make sense to me so we'll do it.
5401 */
5402static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
5403{
5404 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5405
5406 LogFlowFuncEnter();
5407
5408# ifndef VBOX_WITH_AUDIO_CALLBACKS
5409 /*
5410 * Stop the timer, if any.
5411 */
5412 hdaTimerMaybeStop(pThis);
5413# endif
5414
5415 /* See 6.2.1. */
5416 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO /* Ouput streams */,
5417 HDA_MAX_SDI /* Input streams */,
5418 0 /* Bidirectional output streams */,
5419 0 /* Serial data out signals */,
5420 1 /* 64-bit */);
5421 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
5422 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
5423 /* Announce the full 60 words output payload. */
5424 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
5425 /* Announce the full 29 words input payload. */
5426 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
5427 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
5428 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
5429 HDA_REG(pThis, CORBRP) = 0x0;
5430 HDA_REG(pThis, RIRBWP) = 0x0;
5431
5432 /*
5433 * Stop any audio currently playing and/or recording.
5434 */
5435 AudioMixerSinkCtl(pThis->SinkFront.pMixSink, AUDMIXSINKCMD_DISABLE);
5436# ifdef VBOX_WITH_HDA_MIC_IN
5437 AudioMixerSinkCtl(pThis->SinkMicIn.pMixSink, AUDMIXSINKCMD_DISABLE);
5438# endif
5439 AudioMixerSinkCtl(pThis->SinkLineIn.pMixSink, AUDMIXSINKCMD_DISABLE);
5440# ifdef VBOX_WITH_HDA_51_SURROUND
5441 AudioMixerSinkCtl(pThis->SinkCenterLFE.pMixSink, AUDMIXSINKCMD_DISABLE);
5442 AudioMixerSinkCtl(pThis->SinkRear.pMixSink, AUDMIXSINKCMD_DISABLE);
5443# endif
5444
5445 /*
5446 * Set some sensible defaults for which HDA sinks
5447 * are connected to which stream number.
5448 *
5449 * We use SD0 for input and SD4 for output by default.
5450 * These stream numbers can be changed by the guest dynamically lateron.
5451 */
5452#ifdef VBOX_WITH_HDA_MIC_IN
5453 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 */, 0 /* Channel */);
5454#endif
5455 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 */, 0 /* Channel */);
5456
5457 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 */, 0 /* Channel */);
5458#ifdef VBOX_WITH_HDA_51_SURROUND
5459 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 */, 0 /* Channel */);
5460 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 */, 0 /* Channel */);
5461#endif
5462
5463 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
5464
5465 if (pThis->pu32CorbBuf)
5466 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
5467 else
5468 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5469
5470 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
5471 if (pThis->pu64RirbBuf)
5472 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
5473 else
5474 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5475
5476 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
5477
5478 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5479 {
5480 /* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
5481 HDA_STREAM_REG(pThis, CTL, i) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN);
5482 hdaStreamReset(pThis, &pThis->aStreams[i]);
5483 }
5484
5485 /* Clear stream tags <-> objects mapping table. */
5486 RT_ZERO(pThis->aTags);
5487
5488 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
5489 HDA_REG(pThis, STATESTS) = 0x1;
5490
5491# ifndef VBOX_WITH_AUDIO_CALLBACKS
5492 hdaTimerMaybeStart(pThis);
5493# endif
5494
5495 LogFlowFuncLeave();
5496 LogRel(("HDA: Reset\n"));
5497}
5498
5499/**
5500 * @interface_method_impl{PDMDEVREG,pfnDestruct}
5501 */
5502static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
5503{
5504 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5505
5506 PHDADRIVER pDrv;
5507 while (!RTListIsEmpty(&pThis->lstDrv))
5508 {
5509 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
5510
5511 RTListNodeRemove(&pDrv->Node);
5512 RTMemFree(pDrv);
5513 }
5514
5515 if (pThis->pCodec)
5516 {
5517 hdaCodecDestruct(pThis->pCodec);
5518
5519 RTMemFree(pThis->pCodec);
5520 pThis->pCodec = NULL;
5521 }
5522
5523 RTMemFree(pThis->pu32CorbBuf);
5524 pThis->pu32CorbBuf = NULL;
5525
5526 RTMemFree(pThis->pu64RirbBuf);
5527 pThis->pu64RirbBuf = NULL;
5528
5529 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5530 hdaStreamDestroy(&pThis->aStreams[i]);
5531
5532 return VINF_SUCCESS;
5533}
5534
5535
5536/**
5537 * Attach command, internal version.
5538 *
5539 * This is called to let the device attach to a driver for a specified LUN
5540 * during runtime. This is not called during VM construction, the device
5541 * constructor has to attach to all the available drivers.
5542 *
5543 * @returns VBox status code.
5544 * @param pDevIns The device instance.
5545 * @param pDrv Driver to (re-)use for (re-)attaching to.
5546 * If NULL is specified, a new driver will be created and appended
5547 * to the driver list.
5548 * @param uLUN The logical unit which is being detached.
5549 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5550 */
5551static int hdaAttachInternal(PPDMDEVINS pDevIns, PHDADRIVER pDrv, unsigned uLUN, uint32_t fFlags)
5552{
5553 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5554
5555 /*
5556 * Attach driver.
5557 */
5558 char *pszDesc = NULL;
5559 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
5560 AssertReleaseMsgReturn(pszDesc,
5561 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
5562 VERR_NO_MEMORY);
5563
5564 PPDMIBASE pDrvBase;
5565 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
5566 &pThis->IBase, &pDrvBase, pszDesc);
5567 if (RT_SUCCESS(rc))
5568 {
5569 if (pDrv == NULL)
5570 pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
5571 if (pDrv)
5572 {
5573 pDrv->pDrvBase = pDrvBase;
5574 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
5575 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
5576 pDrv->pHDAState = pThis;
5577 pDrv->uLUN = uLUN;
5578
5579 /*
5580 * For now we always set the driver at LUN 0 as our primary
5581 * host backend. This might change in the future.
5582 */
5583 if (pDrv->uLUN == 0)
5584 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
5585
5586 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
5587
5588 /* Attach to driver list if not attached yet. */
5589 if (!pDrv->fAttached)
5590 {
5591 RTListAppend(&pThis->lstDrv, &pDrv->Node);
5592 pDrv->fAttached = true;
5593 }
5594 }
5595 else
5596 rc = VERR_NO_MEMORY;
5597 }
5598 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5599 LogFunc(("No attached driver for LUN #%u\n", uLUN));
5600
5601 if (RT_FAILURE(rc))
5602 {
5603 /* Only free this string on failure;
5604 * must remain valid for the live of the driver instance. */
5605 RTStrFree(pszDesc);
5606 }
5607
5608 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
5609 return rc;
5610}
5611
5612/**
5613 * Attach command.
5614 *
5615 * This is called to let the device attach to a driver for a specified LUN
5616 * during runtime. This is not called during VM construction, the device
5617 * constructor has to attach to all the available drivers.
5618 *
5619 * @returns VBox status code.
5620 * @param pDevIns The device instance.
5621 * @param uLUN The logical unit which is being detached.
5622 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5623 */
5624static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5625{
5626 return hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
5627}
5628
5629static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5630{
5631 LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
5632}
5633
5634/**
5635 * Powers off the device.
5636 *
5637 * @param pDevIns Device instance to power off.
5638 */
5639static DECLCALLBACK(void) hdaPowerOff(PPDMDEVINS pDevIns)
5640{
5641 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5642
5643 LogRel2(("HDA: Powering off ...\n"));
5644
5645 /* Ditto goes for the codec, which in turn uses the mixer. */
5646 hdaCodecPowerOff(pThis->pCodec);
5647
5648 /**
5649 * Note: Destroy the mixer while powering off and *not* in hdaDestruct,
5650 * giving the mixer the chance to release any references held to
5651 * PDM audio streams it maintains.
5652 */
5653 if (pThis->pMixer)
5654 {
5655 AudioMixerDestroy(pThis->pMixer);
5656 pThis->pMixer = NULL;
5657 }
5658}
5659
5660/**
5661 * Re-attaches a new driver to the device's driver chain.
5662 *
5663 * @returns VBox status code.
5664 * @param pThis Device instance to re-attach driver to.
5665 * @param pDrv Driver instance used for attaching to.
5666 * If NULL is specified, a new driver will be created and appended
5667 * to the driver list.
5668 * @param uLUN The logical unit which is being re-detached.
5669 * @param pszDriver Driver name.
5670 */
5671static int hdaReattach(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
5672{
5673 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
5674 AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
5675
5676 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
5677 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
5678 PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
5679
5680 /* Remove LUN branch. */
5681 CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
5682
5683 if (pDrv)
5684 {
5685 /* Re-use a driver instance => detach the driver before. */
5686 int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
5687 if (RT_FAILURE(rc))
5688 return rc;
5689 }
5690
5691#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
5692
5693 int rc = VINF_SUCCESS;
5694 do
5695 {
5696 PCFGMNODE pLunL0;
5697 rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
5698 rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
5699 rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
5700
5701 PCFGMNODE pLunL1, pLunL2;
5702 rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
5703 rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
5704 rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
5705
5706 rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
5707
5708 } while (0);
5709
5710 if (RT_SUCCESS(rc))
5711 rc = hdaAttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
5712
5713 LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
5714
5715#undef RC_CHECK
5716
5717 return rc;
5718}
5719
5720/**
5721 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5722 */
5723static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5724{
5725 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5726 Assert(iInstance == 0);
5727 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5728
5729 /*
5730 * Validations.
5731 */
5732 if (!CFGMR3AreValuesValid(pCfg, "R0Enabled\0"
5733 "RCEnabled\0"
5734 "TimerHz\0"))
5735 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5736 N_ ("Invalid configuration for the Intel HDA device"));
5737
5738 int rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &pThis->fRCEnabled, false);
5739 if (RT_FAILURE(rc))
5740 return PDMDEV_SET_ERROR(pDevIns, rc,
5741 N_("HDA configuration error: failed to read RCEnabled as boolean"));
5742 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
5743 if (RT_FAILURE(rc))
5744 return PDMDEV_SET_ERROR(pDevIns, rc,
5745 N_("HDA configuration error: failed to read R0Enabled as boolean"));
5746#ifndef VBOX_WITH_AUDIO_CALLBACKS
5747 uint16_t uTimerHz;
5748 rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, 200 /* Hz */);
5749 if (RT_FAILURE(rc))
5750 return PDMDEV_SET_ERROR(pDevIns, rc,
5751 N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
5752#endif
5753
5754 /*
5755 * Initialize data (most of it anyway).
5756 */
5757 pThis->pDevInsR3 = pDevIns;
5758 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5759 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5760 /* IBase */
5761 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
5762
5763 /* PCI Device */
5764 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
5765 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
5766
5767 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
5768 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
5769 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
5770 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
5771 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
5772 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
5773 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
5774 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
5775 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
5776 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
5777 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
5778
5779#if defined(HDA_AS_PCI_EXPRESS)
5780 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
5781#elif defined(VBOX_WITH_MSI_DEVICES)
5782 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
5783#else
5784 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
5785#endif
5786
5787 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
5788 /// of these values needs to be properly documented!
5789 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
5790 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
5791
5792 /* Power Management */
5793 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
5794 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
5795 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
5796
5797#ifdef HDA_AS_PCI_EXPRESS
5798 /* PCI Express */
5799 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
5800 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
5801 /* Device flags */
5802 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
5803 /* version */ 0x1 |
5804 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
5805 /* MSI */ (100) << 9 );
5806 /* Device capabilities */
5807 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
5808 /* Device control */
5809 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
5810 /* Device status */
5811 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
5812 /* Link caps */
5813 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
5814 /* Link control */
5815 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
5816 /* Link status */
5817 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
5818 /* Slot capabilities */
5819 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
5820 /* Slot control */
5821 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
5822 /* Slot status */
5823 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
5824 /* Root control */
5825 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
5826 /* Root capabilities */
5827 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
5828 /* Root status */
5829 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
5830 /* Device capabilities 2 */
5831 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
5832 /* Device control 2 */
5833 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
5834 /* Link control 2 */
5835 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
5836 /* Slot control 2 */
5837 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
5838#endif
5839
5840 /*
5841 * Register the PCI device.
5842 */
5843 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5844 if (RT_FAILURE(rc))
5845 return rc;
5846
5847 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
5848 if (RT_FAILURE(rc))
5849 return rc;
5850
5851#ifdef VBOX_WITH_MSI_DEVICES
5852 PDMMSIREG MsiReg;
5853 RT_ZERO(MsiReg);
5854 MsiReg.cMsiVectors = 1;
5855 MsiReg.iMsiCapOffset = 0x60;
5856 MsiReg.iMsiNextOffset = 0x50;
5857 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5858 if (RT_FAILURE(rc))
5859 {
5860 /* That's OK, we can work without MSI */
5861 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
5862 }
5863#endif
5864
5865 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
5866 if (RT_FAILURE(rc))
5867 return rc;
5868
5869 RTListInit(&pThis->lstDrv);
5870
5871 uint8_t uLUN;
5872 for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
5873 {
5874 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
5875 rc = hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, 0 /* fFlags */);
5876 if (RT_FAILURE(rc))
5877 {
5878 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5879 rc = VINF_SUCCESS;
5880 else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
5881 {
5882 hdaReattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
5883 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
5884 N_("No audio devices could be opened. Selecting the NULL audio backend "
5885 "with the consequence that no sound is audible"));
5886 /* attaching to the NULL audio backend will never fail */
5887 rc = VINF_SUCCESS;
5888 }
5889 break;
5890 }
5891 }
5892
5893 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
5894
5895 if (RT_SUCCESS(rc))
5896 {
5897 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
5898 if (RT_SUCCESS(rc))
5899 {
5900 /* Set a default audio format for our mixer. */
5901 PDMAUDIOSTREAMCFG streamCfg;
5902 streamCfg.uHz = 44100;
5903 streamCfg.cChannels = 2;
5904 streamCfg.enmFormat = PDMAUDIOFMT_S16;
5905 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
5906
5907 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
5908 AssertRC(rc);
5909
5910 /*
5911 * Add mixer output sinks.
5912 */
5913#ifdef VBOX_WITH_HDA_51_SURROUND
5914 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
5915 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5916 AssertRC(rc);
5917 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
5918 AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
5919 AssertRC(rc);
5920 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
5921 AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
5922 AssertRC(rc);
5923#else
5924 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
5925 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5926 AssertRC(rc);
5927#endif
5928 /*
5929 * Add mixer input sinks.
5930 */
5931 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
5932 AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
5933 AssertRC(rc);
5934#ifdef VBOX_WITH_HDA_MIC_IN
5935 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
5936 AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
5937 AssertRC(rc);
5938#endif
5939 /* There is no master volume control. Set the master to max. */
5940 PDMAUDIOVOLUME vol = { false, 255, 255 };
5941 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
5942 AssertRC(rc);
5943 }
5944 }
5945
5946 if (RT_SUCCESS(rc))
5947 {
5948 /* Construct codec. */
5949 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
5950 if (!pThis->pCodec)
5951 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
5952
5953 /* Set codec callbacks. */
5954 pThis->pCodec->pfnMixerAddStream = hdaMixerAddStream;
5955 pThis->pCodec->pfnMixerRemoveStream = hdaMixerRemoveStream;
5956 pThis->pCodec->pfnMixerSetStream = hdaMixerSetStream;
5957 pThis->pCodec->pfnMixerSetVolume = hdaMixerSetVolume;
5958 pThis->pCodec->pfnReset = hdaCodecReset;
5959
5960 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
5961
5962 /* Construct the codec. */
5963 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
5964 if (RT_FAILURE(rc))
5965 AssertRCReturn(rc, rc);
5966
5967 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
5968 verb F20 should provide device/codec recognition. */
5969 Assert(pThis->pCodec->u16VendorId);
5970 Assert(pThis->pCodec->u16DeviceId);
5971 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
5972 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
5973 }
5974
5975 if (RT_SUCCESS(rc))
5976 {
5977 /*
5978 * Create all hardware streams.
5979 */
5980 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5981 {
5982 rc = hdaStreamCreate(&pThis->aStreams[i], i /* uSD */);
5983 AssertRC(rc);
5984 }
5985
5986 /*
5987 * Initialize the driver chain.
5988 */
5989 PHDADRIVER pDrv;
5990 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
5991 {
5992 /*
5993 * Only primary drivers are critical for the VM to run. Everything else
5994 * might not worth showing an own error message box in the GUI.
5995 */
5996 if (!(pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY))
5997 continue;
5998
5999 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
6000 AssertPtr(pCon);
6001
6002 bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
6003#ifdef VBOX_WITH_HDA_MIC_IN
6004 bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
6005#endif
6006 bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
6007#ifdef VBOX_WITH_HDA_51_SURROUND
6008 /** @todo Anything to do here? */
6009#endif
6010
6011 if ( !fValidLineIn
6012#ifdef VBOX_WITH_HDA_MIC_IN
6013 && !fValidMicIn
6014#endif
6015 && !fValidOut)
6016 {
6017 LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
6018
6019 hdaReset(pDevIns);
6020 hdaReattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
6021
6022 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6023 N_("No audio devices could be opened. Selecting the NULL audio backend "
6024 "with the consequence that no sound is audible"));
6025 }
6026 else
6027 {
6028 bool fWarn = false;
6029
6030 PDMAUDIOBACKENDCFG backendCfg;
6031 int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
6032 if (RT_SUCCESS(rc2))
6033 {
6034 if (backendCfg.cSources)
6035 {
6036#ifdef VBOX_WITH_HDA_MIC_IN
6037 /* If the audio backend supports two or more input streams at once,
6038 * warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
6039 if (backendCfg.cMaxStreamsIn >= 2)
6040 fWarn = !fValidLineIn || !fValidMicIn;
6041 /* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
6042 * *not* ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
6043 * One of the two simply is not in use then. */
6044 else if (backendCfg.cMaxStreamsIn == 1)
6045 fWarn = !fValidLineIn && !fValidMicIn;
6046 /* Don't warn if our backend is not able of supporting any input streams at all. */
6047#else
6048 /* We only have line-in as input source. */
6049 fWarn = !fValidLineIn;
6050#endif
6051 }
6052
6053 if ( !fWarn
6054 && backendCfg.cSinks)
6055 {
6056 fWarn = !fValidOut;
6057 }
6058 }
6059 else
6060 {
6061 LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
6062 fWarn = true;
6063 }
6064
6065 if (fWarn)
6066 {
6067 char szMissingStreams[255];
6068 size_t len = 0;
6069 if (!fValidLineIn)
6070 {
6071 LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
6072 len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
6073 }
6074#ifdef VBOX_WITH_HDA_MIC_IN
6075 if (!fValidMicIn)
6076 {
6077 LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
6078 len += RTStrPrintf(szMissingStreams + len,
6079 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
6080 }
6081#endif
6082 if (!fValidOut)
6083 {
6084 LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
6085 len += RTStrPrintf(szMissingStreams + len,
6086 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
6087 }
6088
6089 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6090 N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
6091 "output or depending on audio input may hang. Make sure your host audio device "
6092 "is working properly. Check the logfile for error messages of the audio "
6093 "subsystem"), szMissingStreams);
6094 }
6095 }
6096 }
6097 }
6098
6099 if (RT_SUCCESS(rc))
6100 {
6101 hdaReset(pDevIns);
6102
6103 /*
6104 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
6105 * hdaReset shouldn't affects these registers.
6106 */
6107 HDA_REG(pThis, WAKEEN) = 0x0;
6108 HDA_REG(pThis, STATESTS) = 0x0;
6109
6110#ifdef DEBUG
6111 /*
6112 * Debug and string formatter types.
6113 */
6114 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
6115 PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaDbgInfoBDLE);
6116 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgInfoStream);
6117 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaDbgInfoCodecNodes);
6118 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaDbgInfoCodecSelector);
6119 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaDbgInfoMixer);
6120
6121 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
6122 AssertRC(rc);
6123 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
6124 AssertRC(rc);
6125 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
6126 AssertRC(rc);
6127 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
6128 AssertRC(rc);
6129 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
6130 AssertRC(rc);
6131#endif /* DEBUG */
6132
6133 /*
6134 * Some debug assertions.
6135 */
6136 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
6137 {
6138 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
6139 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
6140
6141 /* binary search order. */
6142 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
6143 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6144 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6145
6146 /* alignment. */
6147 AssertReleaseMsg( pReg->size == 1
6148 || (pReg->size == 2 && (pReg->offset & 1) == 0)
6149 || (pReg->size == 3 && (pReg->offset & 3) == 0)
6150 || (pReg->size == 4 && (pReg->offset & 3) == 0),
6151 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6152
6153 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
6154 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
6155 if (pReg->offset & 3)
6156 {
6157 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
6158 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6159 if (pPrevReg)
6160 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
6161 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6162 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
6163 }
6164#if 0
6165 if ((pReg->offset + pReg->size) & 3)
6166 {
6167 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6168 if (pNextReg)
6169 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
6170 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6171 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6172 }
6173#endif
6174 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
6175 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
6176 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6177 }
6178 }
6179
6180# ifndef VBOX_WITH_AUDIO_CALLBACKS
6181 if (RT_SUCCESS(rc))
6182 {
6183 /* Start the emulation timer. */
6184 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
6185 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
6186 AssertRCReturn(rc, rc);
6187
6188 if (RT_SUCCESS(rc))
6189 {
6190 pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
6191 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
6192 LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
6193
6194 hdaTimerMaybeStart(pThis);
6195 }
6196 }
6197# else
6198 if (RT_SUCCESS(rc))
6199 {
6200 PHDADRIVER pDrv;
6201 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6202 {
6203 /* Only register primary driver.
6204 * The device emulation does the output multiplexing then. */
6205 if (pDrv->Flags != PDMAUDIODRVFLAG_PRIMARY)
6206 continue;
6207
6208 PDMAUDIOCALLBACK AudioCallbacks[2];
6209
6210 HDACALLBACKCTX Ctx = { pThis, pDrv };
6211
6212 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
6213 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
6214 AudioCallbacks[0].pvCtx = &Ctx;
6215 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
6216
6217 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
6218 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
6219 AudioCallbacks[1].pvCtx = &Ctx;
6220 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
6221
6222 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
6223 if (RT_FAILURE(rc))
6224 break;
6225 }
6226 }
6227# endif
6228
6229# ifdef VBOX_WITH_STATISTICS
6230 if (RT_SUCCESS(rc))
6231 {
6232 /*
6233 * Register statistics.
6234 */
6235# ifndef VBOX_WITH_AUDIO_CALLBACKS
6236 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
6237# endif
6238 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
6239 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
6240 }
6241# endif
6242
6243 LogFlowFuncLeaveRC(rc);
6244 return rc;
6245}
6246
6247/**
6248 * The device registration structure.
6249 */
6250const PDMDEVREG g_DeviceICH6_HDA =
6251{
6252 /* u32Version */
6253 PDM_DEVREG_VERSION,
6254 /* szName */
6255 "hda",
6256 /* szRCMod */
6257 "VBoxDDRC.rc",
6258 /* szR0Mod */
6259 "VBoxDDR0.r0",
6260 /* pszDescription */
6261 "Intel HD Audio Controller",
6262 /* fFlags */
6263 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
6264 /* fClass */
6265 PDM_DEVREG_CLASS_AUDIO,
6266 /* cMaxInstances */
6267 1,
6268 /* cbInstance */
6269 sizeof(HDASTATE),
6270 /* pfnConstruct */
6271 hdaConstruct,
6272 /* pfnDestruct */
6273 hdaDestruct,
6274 /* pfnRelocate */
6275 NULL,
6276 /* pfnMemSetup */
6277 NULL,
6278 /* pfnPowerOn */
6279 NULL,
6280 /* pfnReset */
6281 hdaReset,
6282 /* pfnSuspend */
6283 NULL,
6284 /* pfnResume */
6285 NULL,
6286 /* pfnAttach */
6287 hdaAttach,
6288 /* pfnDetach */
6289 hdaDetach,
6290 /* pfnQueryInterface. */
6291 NULL,
6292 /* pfnInitComplete */
6293 NULL,
6294 /* pfnPowerOff */
6295 hdaPowerOff,
6296 /* pfnSoftReset */
6297 NULL,
6298 /* u32VersionEnd */
6299 PDM_DEVREG_VERSION
6300};
6301
6302#endif /* IN_RING3 */
6303#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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