VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 49493

Last change on this file since 49493 was 49305, checked in by vboxsync, 11 years ago

HDA: State loading fixes. Don't zero regs not in the saved state, just use the reset values.
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1/* $Id: DevIchHda.cpp 49305 2013-10-28 10:27:14Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2013 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_DEV_AUDIO
26#include <VBox/vmm/pdmdev.h>
27#include <VBox/version.h>
28
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#ifdef IN_RING3
33# include <iprt/uuid.h>
34# include <iprt/string.h>
35# include <iprt/mem.h>
36#endif
37
38#include "VBoxDD.h"
39
40extern "C" {
41#include "audio.h"
42}
43#include "DevIchHdaCodec.h"
44
45
46/*******************************************************************************
47* Defined Constants And Macros *
48*******************************************************************************/
49//#define HDA_AS_PCI_EXPRESS
50#define VBOX_WITH_INTEL_HDA
51
52#if defined(VBOX_WITH_HP_HDA)
53/* HP Pavilion dv4t-1300 */
54# define HDA_PCI_VENDOR_ID 0x103c
55# define HDA_PCI_DEVICE_ID 0x30f7
56#elif defined(VBOX_WITH_INTEL_HDA)
57/* Intel HDA controller */
58# define HDA_PCI_VENDOR_ID 0x8086
59# define HDA_PCI_DEVICE_ID 0x2668
60#elif defined(VBOX_WITH_NVIDIA_HDA)
61/* nVidia HDA controller */
62# define HDA_PCI_VENDOR_ID 0x10de
63# define HDA_PCI_DEVICE_ID 0x0ac0
64#else
65# error "Please specify your HDA device vendor/device IDs"
66#endif
67
68/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
69 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
70 * is read only except for bit 15 like the HDA spec states.
71 *
72 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
73 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
74#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
75
76#define HDA_NREGS 114
77#define HDA_NREGS_SAVED 112
78
79/**
80 * NB: Register values stored in memory (au32Regs[]) are indexed through
81 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
82 * register descriptors in g_aHdaRegMap[] are indexed through the
83 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
84 *
85 * The au32Regs[] layout is kept unchanged for saved state
86 * compatibility. */
87
88/* Registers */
89#define HDA_REG_IND_NAME(x) HDA_REG_##x
90#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
91#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
92#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
93#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
94#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
95#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
96#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
97
98
99#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
100#define HDA_RMX_GCAP 0
101/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
102 * oss (15:12) - number of output streams supported
103 * iss (11:8) - number of input streams supported
104 * bss (7:3) - number of bidirectional streams supported
105 * bds (2:1) - number of serial data out signals supported
106 * b64sup (0) - 64 bit addressing supported.
107 */
108#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
109 ( (((oss) & 0xF) << 12) \
110 | (((iss) & 0xF) << 8) \
111 | (((bss) & 0x1F) << 3) \
112 | (((bds) & 0x3) << 2) \
113 | ((b64sup) & 1))
114
115#define HDA_REG_VMIN 1 /* 0x02 */
116#define HDA_RMX_VMIN 1
117
118#define HDA_REG_VMAJ 2 /* 0x03 */
119#define HDA_RMX_VMAJ 2
120
121#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
122#define HDA_RMX_OUTPAY 3
123
124#define HDA_REG_INPAY 4 /* 0x06-0x07 */
125#define HDA_RMX_INPAY 4
126
127#define HDA_REG_GCTL 5 /* 0x08-0x0B */
128#define HDA_RMX_GCTL 5
129#define HDA_GCTL_RST_SHIFT 0
130#define HDA_GCTL_FSH_SHIFT 1
131#define HDA_GCTL_UR_SHIFT 8
132
133#define HDA_REG_WAKEEN 6 /* 0x0C */
134#define HDA_RMX_WAKEEN 6
135
136#define HDA_REG_STATESTS 7 /* 0x0E */
137#define HDA_RMX_STATESTS 7
138#define HDA_STATES_SCSF 0x7
139
140#define HDA_REG_GSTS 8 /* 0x10-0x11*/
141#define HDA_RMX_GSTS 8
142#define HDA_GSTS_FSH_SHIFT 1
143
144#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
145#define HDA_RMX_OUTSTRMPAY 112
146
147#define HDA_REG_INSTRMPAY 10 /* 0x1a */
148#define HDA_RMX_INSTRMPAY 113
149
150#define HDA_REG_INTCTL 11 /* 0x20 */
151#define HDA_RMX_INTCTL 9
152#define HDA_INTCTL_GIE_SHIFT 31
153#define HDA_INTCTL_CIE_SHIFT 30
154#define HDA_INTCTL_S0_SHIFT 0
155#define HDA_INTCTL_S1_SHIFT 1
156#define HDA_INTCTL_S2_SHIFT 2
157#define HDA_INTCTL_S3_SHIFT 3
158#define HDA_INTCTL_S4_SHIFT 4
159#define HDA_INTCTL_S5_SHIFT 5
160#define HDA_INTCTL_S6_SHIFT 6
161#define HDA_INTCTL_S7_SHIFT 7
162#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
163
164#define HDA_REG_INTSTS 12 /* 0x24 */
165#define HDA_RMX_INTSTS 10
166#define HDA_INTSTS_GIS_SHIFT 31
167#define HDA_INTSTS_CIS_SHIFT 30
168#define HDA_INTSTS_S0_SHIFT 0
169#define HDA_INTSTS_S1_SHIFT 1
170#define HDA_INTSTS_S2_SHIFT 2
171#define HDA_INTSTS_S3_SHIFT 3
172#define HDA_INTSTS_S4_SHIFT 4
173#define HDA_INTSTS_S5_SHIFT 5
174#define HDA_INTSTS_S6_SHIFT 6
175#define HDA_INTSTS_S7_SHIFT 7
176#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
177
178#define HDA_REG_WALCLK 13 /* 0x24 */
179#define HDA_RMX_WALCLK /* Not defined! */
180
181/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
182 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
183 * the datasheet.
184 */
185#define HDA_REG_SSYNC 14 /* 0x34 */
186#define HDA_RMX_SSYNC 12
187
188#define HDA_REG_CORBLBASE 15 /* 0x40 */
189#define HDA_RMX_CORBLBASE 13
190
191#define HDA_REG_CORBUBASE 16 /* 0x44 */
192#define HDA_RMX_CORBUBASE 14
193
194#define HDA_REG_CORBWP 17 /* 0x48 */
195#define HDA_RMX_CORBWP 15
196
197#define HDA_REG_CORBRP 18 /* 0x4A */
198#define HDA_RMX_CORBRP 16
199#define HDA_CORBRP_RST_SHIFT 15
200#define HDA_CORBRP_WP_SHIFT 0
201#define HDA_CORBRP_WP_MASK 0xFF
202
203#define HDA_REG_CORBCTL 19 /* 0x4C */
204#define HDA_RMX_CORBCTL 17
205#define HDA_CORBCTL_DMA_SHIFT 1
206#define HDA_CORBCTL_CMEIE_SHIFT 0
207
208#define HDA_REG_CORBSTS 20 /* 0x4D */
209#define HDA_RMX_CORBSTS 18
210#define HDA_CORBSTS_CMEI_SHIFT 0
211
212#define HDA_REG_CORBSIZE 21 /* 0x4E */
213#define HDA_RMX_CORBSIZE 19
214#define HDA_CORBSIZE_SZ_CAP 0xF0
215#define HDA_CORBSIZE_SZ 0x3
216/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
217
218#define HDA_REG_RIRBLBASE 22 /* 0x50 */
219#define HDA_RMX_RIRBLBASE 20
220
221#define HDA_REG_RIRBUBASE 23 /* 0x54 */
222#define HDA_RMX_RIRBUBASE 21
223
224#define HDA_REG_RIRBWP 24 /* 0x58 */
225#define HDA_RMX_RIRBWP 22
226#define HDA_RIRBWP_RST_SHIFT 15
227#define HDA_RIRBWP_WP_MASK 0xFF
228
229#define HDA_REG_RINTCNT 25 /* 0x5A */
230#define HDA_RMX_RINTCNT 23
231#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
232
233#define HDA_REG_RIRBCTL 26 /* 0x5C */
234#define HDA_RMX_RIRBCTL 24
235#define HDA_RIRBCTL_RIC_SHIFT 0
236#define HDA_RIRBCTL_DMA_SHIFT 1
237#define HDA_ROI_DMA_SHIFT 2
238
239#define HDA_REG_RIRBSTS 27 /* 0x5D */
240#define HDA_RMX_RIRBSTS 25
241#define HDA_RIRBSTS_RINTFL_SHIFT 0
242#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
243
244#define HDA_REG_RIRBSIZE 28 /* 0x5E */
245#define HDA_RMX_RIRBSIZE 26
246#define HDA_RIRBSIZE_SZ_CAP 0xF0
247#define HDA_RIRBSIZE_SZ 0x3
248
249#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
250#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
251
252
253#define HDA_REG_IC 29 /* 0x60 */
254#define HDA_RMX_IC 27
255
256#define HDA_REG_IR 30 /* 0x64 */
257#define HDA_RMX_IR 28
258
259#define HDA_REG_IRS 31 /* 0x68 */
260#define HDA_RMX_IRS 29
261#define HDA_IRS_ICB_SHIFT 0
262#define HDA_IRS_IRV_SHIFT 1
263
264#define HDA_REG_DPLBASE 32 /* 0x70 */
265#define HDA_RMX_DPLBASE 30
266#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
267
268#define HDA_REG_DPUBASE 33 /* 0x74 */
269#define HDA_RMX_DPUBASE 31
270#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
271#define DPBASE_ENABLED 1
272#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
273
274#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
275#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
276/* Note: sdnum here _MUST_ be stream reg number [0,7] */
277#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
278
279#define HDA_REG_SD0CTL 34 /* 0x80 */
280#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
281#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
282#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
283#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
284#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
285#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
286#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
287#define HDA_RMX_SD0CTL 32
288#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
289#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
290#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
291#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
292#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
293#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
294#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
295
296#define SD(func, num) SD##num##func
297#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
298#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
299#define HDA_SDCTL_NUM_MASK 0xF
300#define HDA_SDCTL_NUM_SHIFT 20
301#define HDA_SDCTL_DIR_SHIFT 19
302#define HDA_SDCTL_TP_SHIFT 18
303#define HDA_SDCTL_STRIPE_MASK 0x3
304#define HDA_SDCTL_STRIPE_SHIFT 16
305#define HDA_SDCTL_DEIE_SHIFT 4
306#define HDA_SDCTL_FEIE_SHIFT 3
307#define HDA_SDCTL_ICE_SHIFT 2
308#define HDA_SDCTL_RUN_SHIFT 1
309#define HDA_SDCTL_SRST_SHIFT 0
310
311#define HDA_REG_SD0STS 35 /* 0x83 */
312#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
313#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
314#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
315#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
316#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
317#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
318#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
319#define HDA_RMX_SD0STS 33
320#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
321#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
322#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
323#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
324#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
325#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
326#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
327
328#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
329#define HDA_SDSTS_FIFORDY_SHIFT 5
330#define HDA_SDSTS_DE_SHIFT 4
331#define HDA_SDSTS_FE_SHIFT 3
332#define HDA_SDSTS_BCIS_SHIFT 2
333
334#define HDA_REG_SD0LPIB 36 /* 0x84 */
335#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
336#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
337#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
338#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
339#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
340#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
341#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
342#define HDA_RMX_SD0LPIB 34
343#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
344#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
345#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
346#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
347#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
348#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
349#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
350
351#define HDA_REG_SD0CBL 37 /* 0x88 */
352#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
353#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
354#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
355#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
356#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
357#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
358#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
359#define HDA_RMX_SD0CBL 35
360#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
361#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
362#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
363#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
364#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
365#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
366#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
367
368
369#define HDA_REG_SD0LVI 38 /* 0x8C */
370#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
371#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
372#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
373#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
374#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
375#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
376#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
377#define HDA_RMX_SD0LVI 36
378#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
379#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
380#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
381#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
382#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
383#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
384#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
385
386#define HDA_REG_SD0FIFOW 39 /* 0x8E */
387#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
388#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
389#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
390#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
391#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
392#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
393#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
394#define HDA_RMX_SD0FIFOW 37
395#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
396#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
397#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
398#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
399#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
400#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
401#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
402
403/*
404 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
405 */
406#define HDA_SDFIFOW_8B 0x2
407#define HDA_SDFIFOW_16B 0x3
408#define HDA_SDFIFOW_32B 0x4
409
410#define HDA_REG_SD0FIFOS 40 /* 0x90 */
411#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
412#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
413#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
414#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
415#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
416#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
417#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
418#define HDA_RMX_SD0FIFOS 38
419#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
420#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
421#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
422#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
423#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
424#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
425#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
426
427/*
428 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
429 * formula: size - 1
430 * Other values not listed are not supported.
431 */
432#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
433#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
434#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
435#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
436#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
437#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
438#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
439#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
440#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
441
442#define HDA_REG_SD0FMT 41 /* 0x92 */
443#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
444#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
445#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
446#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
447#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
448#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
449#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
450#define HDA_RMX_SD0FMT 39
451#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
452#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
453#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
454#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
455#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
456#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
457#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
458
459#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
460#define HDA_SDFMT_BASE_RATE_SHIFT 14
461#define HDA_SDFMT_MULT_SHIFT 11
462#define HDA_SDFMT_MULT_MASK 0x7
463#define HDA_SDFMT_DIV_SHIFT 8
464#define HDA_SDFMT_DIV_MASK 0x7
465#define HDA_SDFMT_BITS_SHIFT 4
466#define HDA_SDFMT_BITS_MASK 0x7
467#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
468#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
469#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
470
471#define HDA_REG_SD0BDPL 42 /* 0x98 */
472#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
473#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
474#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
475#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
476#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
477#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
478#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
479#define HDA_RMX_SD0BDPL 40
480#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
481#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
482#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
483#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
484#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
485#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
486#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
487
488#define HDA_REG_SD0BDPU 43 /* 0x9C */
489#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
490#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
491#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
492#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
493#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
494#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
495#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
496#define HDA_RMX_SD0BDPU 41
497#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
498#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
499#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
500#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
501#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
502#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
503#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
504
505
506/*******************************************************************************
507* Structures and Typedefs *
508*******************************************************************************/
509typedef struct HDABDLEDESC
510{
511 uint64_t u64BdleCviAddr;
512 uint32_t u32BdleMaxCvi;
513 uint32_t u32BdleCvi;
514 uint32_t u32BdleCviLen;
515 uint32_t u32BdleCviPos;
516 bool fBdleCviIoc;
517 uint32_t cbUnderFifoW;
518 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
519} HDABDLEDESC, *PHDABDLEDESC;
520
521typedef struct HDASTREAMTRANSFERDESC
522{
523 uint64_t u64BaseDMA;
524 uint32_t u32Ctl;
525 uint32_t *pu32Sts;
526 uint8_t u8Strm;
527 uint32_t *pu32Lpib;
528 uint32_t u32Cbl;
529 uint32_t u32Fifos;
530} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
531
532/**
533 * ICH Intel HD Audio Controller state.
534 */
535typedef struct HDASTATE
536{
537 /** The PCI device structure. */
538 PCIDevice PciDev;
539 /** R3 Pointer to the device instance. */
540 PPDMDEVINSR3 pDevInsR3;
541 /** R0 Pointer to the device instance. */
542 PPDMDEVINSR0 pDevInsR0;
543 /** R0 Pointer to the device instance. */
544 PPDMDEVINSRC pDevInsRC;
545
546 uint32_t u32Padding;
547
548 /** Pointer to the connector of the attached audio driver. */
549 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pDrv;
550 /** Pointer to the attached audio driver. */
551 R3PTRTYPE(PPDMIBASE) pDrvBase;
552 /** The base interface for LUN\#0. */
553 PDMIBASE IBase;
554 RTGCPHYS MMIOBaseAddr;
555 uint32_t au32Regs[HDA_NREGS];
556 HDABDLEDESC StInBdle;
557 HDABDLEDESC StOutBdle;
558 HDABDLEDESC StMicBdle;
559 uint64_t u64CORBBase;
560 uint64_t u64RIRBBase;
561 uint64_t u64DPBase;
562 /** pointer to CORB buf */
563 R3PTRTYPE(uint32_t *) pu32CorbBuf;
564 /** size in bytes of CORB buf */
565 uint32_t cbCorbBuf;
566 uint32_t u32Padding2;
567 /** pointer on RIRB buf */
568 R3PTRTYPE(uint64_t *) pu64RirbBuf;
569 /** size in bytes of RIRB buf */
570 uint32_t cbRirbBuf;
571 /** indicates if HDA in reset. */
572 bool fInReset;
573 /** Interrupt on completion */
574 bool fCviIoc;
575 /** Flag whether the R0 part is enabled. */
576 bool fR0Enabled;
577 /** Flag whether the RC part is enabled. */
578 bool fRCEnabled;
579 /** The HDA codec state. */
580 R3PTRTYPE(PHDACODEC) pCodec;
581 uint64_t u64BaseTS;
582 /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
583 uint8_t u8Counter;
584 uint8_t au8Padding[7];
585} HDASTATE;
586/** Pointer to the ICH Intel HD Audio Controller state. */
587typedef HDASTATE *PHDASTATE;
588
589#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
590 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
591#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
592 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
593
594
595/*******************************************************************************
596* Internal Functions *
597*******************************************************************************/
598#ifndef VBOX_DEVICE_STRUCT_TESTCASE
599static FNPDMDEVRESET hdaReset;
600
601static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
602static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
603static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
604static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
605static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
606static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
607static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
608static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
609static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
610static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
611static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
612static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
613static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
614static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
615static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
616static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
617static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
618
619static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
620static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
621static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
622static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
623static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
624static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
625static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
626static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
627static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
628static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
629static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
630static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
631static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
632static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
633static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
634static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
635
636#ifdef IN_RING3
637DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
638 PHDASTREAMTRANSFERDESC pStreamDesc);
639static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
640#ifdef LOG_ENABLED
641static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
642#endif
643#endif
644
645
646/*******************************************************************************
647* Global Variables *
648*******************************************************************************/
649
650/* see 302349 p 6.2*/
651static const struct HDAREGDESC
652{
653 /** Register offset in the register space. */
654 uint32_t offset;
655 /** Size in bytes. Registers of size > 4 are in fact tables. */
656 uint32_t size;
657 /** Readable bits. */
658 uint32_t readable;
659 /** Writable bits. */
660 uint32_t writable;
661 /** Read callback. */
662 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
663 /** Write callback. */
664 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
665 /** Index into the register storage array. */
666 uint32_t mem_idx;
667 /** Abbreviated name. */
668 const char *abbrev;
669} g_aHdaRegMap[HDA_NREGS] =
670
671/* Turn a short register name into an memory index and a stringized name. */
672#define RA(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
673/* Same as above for an input stream ('I' prefixed). */
674#define IA(abbrev) HDA_MEM_IND_NAME(abbrev), "I"#abbrev
675/* Same as above for an output stream ('O' prefixed). */
676#define OA(abbrev) HDA_MEM_IND_NAME(abbrev), "O"#abbrev
677/* Same as above for a register *not* stored in memory. */
678#define UA(abbrev) 0, #abbrev
679
680{
681 /* offset size read mask write mask read callback write callback abbrev */
682 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- */
683 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(GCAP) }, /* Global Capabilities */
684 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMIN) }, /* Minor Version */
685 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMAJ) }, /* Major Version */
686 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTPAY) }, /* Output Payload Capabilities */
687 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INPAY) }, /* Input Payload Capabilities */
688 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , RA(GCTL) }, /* Global Control */
689 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , RA(WAKEEN) }, /* Wake Enable */
690 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , RA(STATESTS) }, /* State Change Status */
691 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , RA(GSTS) }, /* Global Status */
692 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTSTRMPAY)}, /* Output Stream Payload Capability */
693 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INSTRMPAY) }, /* Input Stream Payload Capability */
694 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(INTCTL) }, /* Interrupt Control */
695 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , RA(INTSTS) }, /* Interrupt Status */
696 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , UA(WALCLK) }, /* Wall Clock Counter */
697 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
698 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(SSYNC) }, /* Stream Synchronization */
699 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(CORBLBASE) }, /* CORB Lower Base Address */
700 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(CORBUBASE) }, /* CORB Upper Base Address */
701 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , RA(CORBWP) }, /* CORB Write Pointer */
702 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , RA(CORBRP) }, /* CORB Read Pointer */
703 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , RA(CORBCTL) }, /* CORB Control */
704 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , RA(CORBSTS) }, /* CORB Status */
705 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(CORBSIZE) }, /* CORB Size */
706 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBLBASE) }, /* RIRB Lower Base Address */
707 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBUBASE) }, /* RIRB Upper Base Address */
708 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , RA(RIRBWP) }, /* RIRB Write Pointer */
709 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , RA(RINTCNT) }, /* Response Interrupt Count */
710 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , RA(RIRBCTL) }, /* RIRB Control */
711 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , RA(RIRBSTS) }, /* RIRB Status */
712 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(RIRBSIZE) }, /* RIRB Size */
713 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , RA(IC) }, /* Immediate Command */
714 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , RA(IR) }, /* Immediate Response */
715 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , RA(IRS) }, /* Immediate Command Status */
716 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , RA(DPLBASE) }, /* MA Position Lower Base */
717 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(DPUBASE) }, /* DMA Position Upper Base */
718
719 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD0CTL) }, /* Input Stream Descriptor 0 (ICD0) Control */
720 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD0STS) }, /* ISD0 Status */
721 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0LPIB) }, /* ISD0 Link Position In Buffer */
722 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0CBL) }, /* ISD0 Cyclic Buffer Length */
723 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD0LVI) }, /* ISD0 Last Valid Index */
724 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD0FIFOW) }, /* ISD0 FIFO Watermark */
725 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD0FIFOS) }, /* ISD0 FIFO Size */
726 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD0FMT) }, /* ISD0 Format */
727 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD0BDPL) }, /* ISD0 Buffer Descriptor List Pointer-Lower Base Address */
728 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD0BDPU) }, /* ISD0 Buffer Descriptor List Pointer-Upper Base Address */
729
730 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD1CTL) }, /* Input Stream Descriptor 1 (ISD1) Control */
731 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD1STS) }, /* ISD1 Status */
732 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1LPIB) }, /* ISD1 Link Position In Buffer */
733 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1CBL) }, /* ISD1 Cyclic Buffer Length */
734 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD1LVI) }, /* ISD1 Last Valid Index */
735 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD1FIFOW) }, /* ISD1 FIFO Watermark */
736 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD1FIFOS) }, /* ISD1 FIFO Size */
737 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD1FMT) }, /* ISD1 Format */
738 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD1BDPL) }, /* ISD1 Buffer Descriptor List Pointer-Lower Base Address */
739 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD1BDPU) }, /* ISD1 Buffer Descriptor List Pointer-Upper Base Address */
740
741 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD2CTL) }, /* Input Stream Descriptor 2 (ISD2) Control */
742 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD2STS) }, /* ISD2 Status */
743 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2LPIB) }, /* ISD2 Link Position In Buffer */
744 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2CBL) }, /* ISD2 Cyclic Buffer Length */
745 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD2LVI) }, /* ISD2 Last Valid Index */
746 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD2FIFOW) }, /* ISD2 FIFO Watermark */
747 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD2FIFOS) }, /* ISD2 FIFO Size */
748 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD2FMT) }, /* ISD2 Format */
749 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD2BDPL) }, /* ISD2 Buffer Descriptor List Pointer-Lower Base Address */
750 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD2BDPU) }, /* ISD2 Buffer Descriptor List Pointer-Upper Base Address */
751
752 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD3CTL) }, /* Input Stream Descriptor 3 (ISD3) Control */
753 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD3STS) }, /* ISD3 Status */
754 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3LPIB) }, /* ISD3 Link Position In Buffer */
755 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3CBL) }, /* ISD3 Cyclic Buffer Length */
756 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD3LVI) }, /* ISD3 Last Valid Index */
757 { 0x000EE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD3FIFOW) }, /* ISD3 FIFO Watermark */
758 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD3FIFOS) }, /* ISD3 FIFO Size */
759 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD3FMT) }, /* ISD3 Format */
760 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD3BDPL) }, /* ISD3 Buffer Descriptor List Pointer-Lower Base Address */
761 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD3BDPU) }, /* ISD3 Buffer Descriptor List Pointer-Upper Base Address */
762
763 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD4CTL) }, /* Output Stream Descriptor 0 (OSD0) Control */
764 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD4STS) }, /* OSD0 Status */
765 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4LPIB) }, /* OSD0 Link Position In Buffer */
766 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4CBL) }, /* OSD0 Cyclic Buffer Length */
767 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD4LVI) }, /* OSD0 Last Valid Index */
768 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD4FIFOW) }, /* OSD0 FIFO Watermark */
769 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD4FIFOS) }, /* OSD0 FIFO Size */
770 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD4FMT) }, /* OSD0 Format */
771 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD4BDPL) }, /* OSD0 Buffer Descriptor List Pointer-Lower Base Address */
772 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD4BDPU) }, /* OSD0 Buffer Descriptor List Pointer-Upper Base Address */
773
774 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD5CTL) }, /* Output Stream Descriptor 0 (OSD1) Control */
775 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD5STS) }, /* OSD1 Status */
776 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5LPIB) }, /* OSD1 Link Position In Buffer */
777 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5CBL) }, /* OSD1 Cyclic Buffer Length */
778 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD5LVI) }, /* OSD1 Last Valid Index */
779 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD5FIFOW) }, /* OSD1 FIFO Watermark */
780 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD5FIFOS) }, /* OSD1 FIFO Size */
781 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD5FMT) }, /* OSD1 Format */
782 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD5BDPL) }, /* OSD1 Buffer Descriptor List Pointer-Lower Base Address */
783 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD5BDPU) }, /* OSD1 Buffer Descriptor List Pointer-Upper Base Address */
784
785 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD6CTL) }, /* Output Stream Descriptor 0 (OSD2) Control */
786 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD6STS) }, /* OSD2 Status */
787 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6LPIB) }, /* OSD2 Link Position In Buffer */
788 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6CBL) }, /* OSD2 Cyclic Buffer Length */
789 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD6LVI) }, /* OSD2 Last Valid Index */
790 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD6FIFOW) }, /* OSD2 FIFO Watermark */
791 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD6FIFOS) }, /* OSD2 FIFO Size */
792 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD6FMT) }, /* OSD2 Format */
793 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD6BDPL) }, /* OSD2 Buffer Descriptor List Pointer-Lower Base Address */
794 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD6BDPU) }, /* OSD2 Buffer Descriptor List Pointer-Upper Base Address */
795
796 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD7CTL) }, /* Output Stream Descriptor 0 (OSD3) Control */
797 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD7STS) }, /* OSD3 Status */
798 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7LPIB) }, /* OSD3 Link Position In Buffer */
799 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7CBL) }, /* OSD3 Cyclic Buffer Length */
800 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD7LVI) }, /* OSD3 Last Valid Index */
801 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD7FIFOW) }, /* OSD3 FIFO Watermark */
802 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD7FIFOS) }, /* OSD3 FIFO Size */
803 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD7FMT) }, /* OSD3 Format */
804 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD7BDPL) }, /* OSD3 Buffer Descriptor List Pointer-Lower Base Address */
805 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD7BDPU) }, /* OSD3 Buffer Descriptor List Pointer-Upper Base Address */
806};
807
808/**
809 * HDA register aliases (HDA spec 3.3.45).
810 * @remarks Sorted by offReg.
811 */
812static const struct
813{
814 /** The alias register offset. */
815 uint32_t offReg;
816 /** The register index. */
817 int idxAlias;
818} g_aHdaRegAliases[] =
819{
820 { 0x2084, HDA_REG_SD0LPIB },
821 { 0x20a4, HDA_REG_SD1LPIB },
822 { 0x20c4, HDA_REG_SD2LPIB },
823 { 0x20e4, HDA_REG_SD3LPIB },
824 { 0x2104, HDA_REG_SD4LPIB },
825 { 0x2124, HDA_REG_SD5LPIB },
826 { 0x2144, HDA_REG_SD6LPIB },
827 { 0x2164, HDA_REG_SD7LPIB },
828};
829
830#ifdef IN_RING3
831/** HDABDLEDESC field descriptors the v3+ saved state. */
832static SSMFIELD const g_aHdaBDLEDescFields[] =
833{
834 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
835 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
836 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
837 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
838 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
839 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
840 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
841 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
842 SSMFIELD_ENTRY_TERM()
843};
844
845/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
846static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
847{
848 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
849 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
850 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
851 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
852 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
853 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
854 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
855 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
856 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
857 SSMFIELD_ENTRY_TERM()
858};
859#endif
860
861/**
862 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
863 */
864static uint32_t const g_afMasks[5] =
865{
866 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
867};
868
869#ifdef IN_RING3
870DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
871{
872 if (pThis->u64DPBase & DPBASE_ENABLED)
873 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
874 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
875 pStreamDesc->pu32Lpib, sizeof(uint32_t));
876}
877#endif
878
879DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
880{
881#if 0
882 switch(HDA_STREAM_REG(pThis, FIFOW, pStreamDesc->u8Strm))
883 {
884 case HDA_SDFIFOW_8B: return 8;
885 case HDA_SDFIFOW_16B: return 16;
886 case HDA_SDFIFOW_32B: return 32;
887 default:
888 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
889 }
890#endif
891 return 0;
892}
893
894static int hdaProcessInterrupt(PHDASTATE pThis)
895{
896#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
897 ( INTCTL_SX((pThis), num) \
898 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
899 bool fIrq = false;
900 if ( HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
901 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
902 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
903 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
904 fIrq = true;
905
906 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
907 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
908 fIrq = true;
909
910 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
911 {
912 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
913 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
914 }
915 return VINF_SUCCESS;
916}
917
918/**
919 * Looks up a register at the exact offset given by @a offReg.
920 *
921 * @returns Register index on success, -1 if not found.
922 * @param pThis The HDA device state.
923 * @param offReg The register offset.
924 */
925static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
926{
927 /*
928 * Aliases.
929 */
930 if (offReg >= g_aHdaRegAliases[0].offReg)
931 {
932 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
933 if (offReg == g_aHdaRegAliases[i].offReg)
934 return g_aHdaRegAliases[i].idxAlias;
935 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
936 return -1;
937 }
938
939 /*
940 * Binary search the
941 */
942 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
943 int idxLow = 0;
944 for (;;)
945 {
946 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
947 if (offReg < g_aHdaRegMap[idxMiddle].offset)
948 {
949 if (idxLow == idxMiddle)
950 break;
951 idxEnd = idxMiddle;
952 }
953 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
954 {
955 idxLow = idxMiddle + 1;
956 if (idxLow >= idxEnd)
957 break;
958 }
959 else
960 return idxMiddle;
961 }
962
963#ifdef RT_STRICT
964 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
965 Assert(g_aHdaRegMap[i].offset != offReg);
966#endif
967 return -1;
968}
969
970/**
971 * Looks up a register covering the offset given by @a offReg.
972 *
973 * @returns Register index on success, -1 if not found.
974 * @param pThis The HDA device state.
975 * @param offReg The register offset.
976 */
977static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
978{
979 /*
980 * Aliases.
981 */
982 if (offReg >= g_aHdaRegAliases[0].offReg)
983 {
984 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
985 {
986 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
987 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
988 return g_aHdaRegAliases[i].idxAlias;
989 }
990 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
991 return -1;
992 }
993
994 /*
995 * Binary search the
996 */
997 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
998 int idxLow = 0;
999 for (;;)
1000 {
1001 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1002 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1003 {
1004 if (idxLow == idxMiddle)
1005 break;
1006 idxEnd = idxMiddle;
1007 }
1008 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1009 {
1010 idxLow = idxMiddle + 1;
1011 if (idxLow >= idxEnd)
1012 break;
1013 }
1014 else
1015 return idxMiddle;
1016 }
1017
1018#ifdef RT_STRICT
1019 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1020 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1021#endif
1022 return -1;
1023}
1024
1025#ifdef IN_RING3
1026static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1027{
1028 int rc = VINF_SUCCESS;
1029 if (fLocal)
1030 {
1031 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1032 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1033 if (RT_FAILURE(rc))
1034 AssertRCReturn(rc, rc);
1035#ifdef DEBUG_CMD_BUFFER
1036 uint8_t i = 0;
1037 do
1038 {
1039 Log(("hda: corb%02x: ", i));
1040 uint8_t j = 0;
1041 do
1042 {
1043 const char *prefix;
1044 if ((i + j) == HDA_REG(pThis, CORBRP);
1045 prefix = "[R]";
1046 else if ((i + j) == HDA_REG(pThis, CORBWP);
1047 prefix = "[W]";
1048 else
1049 prefix = " "; /* three spaces */
1050 Log(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
1051 j++;
1052 } while (j < 8);
1053 Log(("\n"));
1054 i += 8;
1055 } while(i != 0);
1056#endif
1057 }
1058 else
1059 {
1060 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1061 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1062 if (RT_FAILURE(rc))
1063 AssertRCReturn(rc, rc);
1064#ifdef DEBUG_CMD_BUFFER
1065 uint8_t i = 0;
1066 do {
1067 Log(("hda: rirb%02x: ", i));
1068 uint8_t j = 0;
1069 do {
1070 const char *prefix;
1071 if ((i + j) == HDA_REG(pThis, RIRBWP))
1072 prefix = "[W]";
1073 else
1074 prefix = " ";
1075 Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1076 } while (++j < 8);
1077 Log(("\n"));
1078 i += 8;
1079 } while (i != 0);
1080#endif
1081 }
1082 return rc;
1083}
1084
1085static int hdaCORBCmdProcess(PHDASTATE pThis)
1086{
1087 int rc;
1088 uint8_t corbRp;
1089 uint8_t corbWp;
1090 uint8_t rirbWp;
1091
1092 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1093
1094 rc = hdaCmdSync(pThis, true);
1095 if (RT_FAILURE(rc))
1096 AssertRCReturn(rc, rc);
1097 corbRp = HDA_REG(pThis, CORBRP);
1098 corbWp = HDA_REG(pThis, CORBWP);
1099 rirbWp = HDA_REG(pThis, RIRBWP);
1100 Assert((corbWp != corbRp));
1101 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1102 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1103 while (corbRp != corbWp)
1104 {
1105 uint32_t cmd;
1106 uint64_t resp;
1107 pfn = NULL;
1108 corbRp++;
1109 cmd = pThis->pu32CorbBuf[corbRp];
1110 rc = pThis->pCodec->pfnLookup(pThis->pCodec, cmd, &pfn);
1111 if (RT_FAILURE(rc))
1112 AssertRCReturn(rc, rc);
1113 Assert(pfn);
1114 (rirbWp)++;
1115
1116 if (RT_LIKELY(pfn))
1117 rc = pfn(pThis->pCodec, cmd, &resp);
1118 else
1119 rc = VERR_INVALID_FUNCTION;
1120
1121 if (RT_FAILURE(rc))
1122 AssertRCReturn(rc, rc);
1123 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
1124 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1125 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1126 {
1127 Log(("hda: unexpected unsolicited response.\n"));
1128 HDA_REG(pThis, CORBRP) = corbRp;
1129 return rc;
1130 }
1131 pThis->pu64RirbBuf[rirbWp] = resp;
1132 pThis->u8Counter++;
1133 if (pThis->u8Counter == RINTCNT_N(pThis))
1134 break;
1135 }
1136 HDA_REG(pThis, CORBRP) = corbRp;
1137 HDA_REG(pThis, RIRBWP) = rirbWp;
1138 rc = hdaCmdSync(pThis, false);
1139 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1140 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1141 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1142 {
1143 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1144 pThis->u8Counter = 0;
1145 rc = hdaProcessInterrupt(pThis);
1146 }
1147 if (RT_FAILURE(rc))
1148 AssertRCReturn(rc, rc);
1149 return rc;
1150}
1151#endif
1152
1153static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
1154{
1155 Log(("hda: reset of stream (%d) started\n", u8Strm));
1156 Assert(( pThis
1157 && pBdle
1158 && pStreamDesc
1159 && u8Strm <= 7));
1160 memset(pBdle, 0, sizeof(HDABDLEDESC));
1161 *pStreamDesc->pu32Lpib = 0;
1162 *pStreamDesc->pu32Sts = 0;
1163 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1164 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
1165 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1166
1167 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1168 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1169 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
1170 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1171 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1172 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1173 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1174 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1175 Log(("hda: reset of stream (%d) finished\n", u8Strm));
1176}
1177
1178/* Register access handlers. */
1179
1180static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1181{
1182 *pu32Value = 0;
1183 return VINF_SUCCESS;
1184}
1185
1186static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1187{
1188 return VINF_SUCCESS;
1189}
1190
1191/* U8 */
1192static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1193{
1194 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1195 return hdaRegReadU32(pThis, iReg, pu32Value);
1196}
1197
1198static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1199{
1200 Assert((u32Value & 0xffffff00) == 0);
1201 return hdaRegWriteU32(pThis, iReg, u32Value);
1202}
1203
1204/* U16 */
1205static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1206{
1207 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1208 return hdaRegReadU32(pThis, iReg, pu32Value);
1209}
1210
1211static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1212{
1213 Assert((u32Value & 0xffff0000) == 0);
1214 return hdaRegWriteU32(pThis, iReg, u32Value);
1215}
1216
1217/* U24 */
1218static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1219{
1220 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1221 return hdaRegReadU32(pThis, iReg, pu32Value);
1222}
1223
1224static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1225{
1226 Assert((u32Value & 0xff000000) == 0);
1227 return hdaRegWriteU32(pThis, iReg, u32Value);
1228}
1229
1230/* U32 */
1231static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1232{
1233 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1234
1235 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1236 return VINF_SUCCESS;
1237}
1238
1239static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1240{
1241 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1242
1243 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1244 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1245 return VINF_SUCCESS;
1246}
1247
1248static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1249{
1250 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1251 {
1252 /* exit reset state */
1253 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1254 pThis->fInReset = false;
1255 }
1256 else
1257 {
1258#ifdef IN_RING3
1259 /* enter reset state*/
1260 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1261 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1262 {
1263 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1264 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1265 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1266 }
1267 hdaReset(pThis->CTX_SUFF(pDevIns));
1268 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1269 pThis->fInReset = true;
1270#else
1271 return VINF_IOM_R3_MMIO_WRITE;
1272#endif
1273 }
1274 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1275 {
1276 /* Flush: GSTS:1 set, see 6.2.6*/
1277 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1278 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1279 }
1280 return VINF_SUCCESS;
1281}
1282
1283static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1284{
1285 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1286
1287 uint32_t v = pThis->au32Regs[iRegMem];
1288 uint32_t nv = u32Value & HDA_STATES_SCSF;
1289 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1290 return VINF_SUCCESS;
1291}
1292
1293static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1294{
1295 uint32_t v = 0;
1296 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1297 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1298 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1299 || HDA_REG(pThis, STATESTS))
1300 v |= RT_BIT(30);
1301#define HDA_IS_STREAM_EVENT(pThis, stream) \
1302 ( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1303 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1304 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1305#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
1306 MARK_STREAM(pThis, 0, v);
1307 MARK_STREAM(pThis, 1, v);
1308 MARK_STREAM(pThis, 2, v);
1309 MARK_STREAM(pThis, 3, v);
1310 MARK_STREAM(pThis, 4, v);
1311 MARK_STREAM(pThis, 5, v);
1312 MARK_STREAM(pThis, 6, v);
1313 MARK_STREAM(pThis, 7, v);
1314 v |= v ? RT_BIT(31) : 0;
1315 *pu32Value = v;
1316 return VINF_SUCCESS;
1317}
1318
1319static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1320{
1321 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1322 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1323 - pThis->u64BaseTS, 24, 1000);
1324 return VINF_SUCCESS;
1325}
1326
1327static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1328{
1329 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1330 HDA_REG(pThis, CORBRP) = 0;
1331#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1332 else
1333 return hdaRegWriteU8(pThis, iReg, u32Value);
1334#endif
1335 return VINF_SUCCESS;
1336}
1337
1338static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1339{
1340#ifdef IN_RING3
1341 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1342 AssertRC(rc);
1343 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1344 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1345 return hdaCORBCmdProcess(pThis);
1346 return rc;
1347#else
1348 return VINF_IOM_R3_MMIO_WRITE;
1349#endif
1350}
1351
1352static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1353{
1354 uint32_t v = HDA_REG(pThis, CORBSTS);
1355 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1356 return VINF_SUCCESS;
1357}
1358
1359static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1360{
1361#ifdef IN_RING3
1362 int rc;
1363 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1364 if (RT_FAILURE(rc))
1365 AssertRCReturn(rc, rc);
1366 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1367 return VINF_SUCCESS;
1368 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1369 return VINF_SUCCESS;
1370 rc = hdaCORBCmdProcess(pThis);
1371 return rc;
1372#else
1373 return VINF_IOM_R3_MMIO_WRITE;
1374#endif
1375}
1376
1377static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1378{
1379 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1380 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1381 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1382 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1383
1384 if (fInReset)
1385 {
1386 /*
1387 * Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1388 * from reset
1389 */
1390 Assert((!fReset));
1391 Log(("hda: guest initiated exit of stream reset.\n"));
1392 }
1393 else if (fReset)
1394 {
1395#ifdef IN_RING3
1396 /*
1397 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1398 */
1399 uint8_t u8Strm = 0;
1400 PHDABDLEDESC pBdle = NULL;
1401 HDASTREAMTRANSFERDESC StreamDesc;
1402 Assert((!fInRun && !fRun));
1403 switch (iReg)
1404 {
1405 case HDA_REG_SD0CTL:
1406 u8Strm = 0;
1407 pBdle = &pThis->StInBdle;
1408 break;
1409 case HDA_REG_SD4CTL:
1410 u8Strm = 4;
1411 pBdle = &pThis->StOutBdle;
1412 break;
1413 default:
1414 Log(("hda: changing SRST bit on non-attached stream\n"));
1415 return hdaRegWriteU24(pThis, iReg, u32Value);
1416 }
1417 Log(("hda: guest initiated enter to stream reset.\n"));
1418 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1419 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
1420#else
1421 return VINF_IOM_R3_MMIO_WRITE;
1422#endif
1423 }
1424 else
1425 {
1426#ifdef IN_RING3
1427 /* we enter here to change DMA states only */
1428 if ( (fInRun && !fRun)
1429 || (fRun && !fInRun))
1430 {
1431 Assert((!fReset && !fInReset));
1432 switch (iReg)
1433 {
1434 case HDA_REG_SD0CTL:
1435 AUD_set_active_in(pThis->pCodec->SwVoiceIn, fRun);
1436 break;
1437 case HDA_REG_SD4CTL:
1438 AUD_set_active_out(pThis->pCodec->SwVoiceOut, fRun);
1439 break;
1440 default:
1441 Log(("hda: changing RUN bit on non-attached stream\n"));
1442 break;
1443 }
1444 }
1445#else
1446 return VINF_IOM_R3_MMIO_WRITE;
1447#endif
1448 }
1449
1450 return hdaRegWriteU24(pThis, iReg, u32Value);
1451}
1452
1453static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1454{
1455 uint32_t v = HDA_REG_IND(pThis, iReg);
1456 v &= ~(u32Value & v);
1457 HDA_REG_IND(pThis, iReg) = v;
1458 hdaProcessInterrupt(pThis);
1459 return VINF_SUCCESS;
1460}
1461
1462static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1463{
1464 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1465 if (RT_FAILURE(rc))
1466 AssertRCReturn(rc, VINF_SUCCESS);
1467 return rc;
1468}
1469
1470static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1471{
1472 switch (u32Value)
1473 {
1474 case HDA_SDFIFOW_8B:
1475 case HDA_SDFIFOW_16B:
1476 case HDA_SDFIFOW_32B:
1477 return hdaRegWriteU16(pThis, iReg, u32Value);
1478 default:
1479 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1480 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1481 }
1482 return VINF_SUCCESS;
1483}
1484
1485/**
1486 * @note This method could be called for changing value on Output Streams
1487 * only (ICH6 datasheet 18.2.39)
1488 */
1489static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1490{
1491 switch (iReg)
1492 {
1493 /* SDInFIFOS is RO, n=0-3 */
1494 case HDA_REG_SD0FIFOS:
1495 case HDA_REG_SD1FIFOS:
1496 case HDA_REG_SD2FIFOS:
1497 case HDA_REG_SD3FIFOS:
1498 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1499 return VINF_SUCCESS;
1500 case HDA_REG_SD4FIFOS:
1501 case HDA_REG_SD5FIFOS:
1502 case HDA_REG_SD6FIFOS:
1503 case HDA_REG_SD7FIFOS:
1504 switch(u32Value)
1505 {
1506 case HDA_SDONFIFO_16B:
1507 case HDA_SDONFIFO_32B:
1508 case HDA_SDONFIFO_64B:
1509 case HDA_SDONFIFO_128B:
1510 case HDA_SDONFIFO_192B:
1511 return hdaRegWriteU16(pThis, iReg, u32Value);
1512
1513 case HDA_SDONFIFO_256B:
1514 Log(("hda: 256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1515 default:
1516 return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);
1517 }
1518 return VINF_SUCCESS;
1519 default:
1520 AssertMsgFailed(("Something weird happened with register lookup routine"));
1521 }
1522 return VINF_SUCCESS;
1523}
1524
1525#ifdef IN_RING3
1526static void hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1527{
1528 Assert((pAudSetting));
1529#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1530 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1531 uint32_t u32HzMult = 1;
1532 uint32_t u32HzDiv = 1;
1533 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
1534 {
1535 case 0: u32HzMult = 1; break;
1536 case 1: u32HzMult = 2; break;
1537 case 2: u32HzMult = 3; break;
1538 case 3: u32HzMult = 4; break;
1539 default:
1540 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1541 }
1542 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
1543 {
1544 case 0: u32HzDiv = 1; break;
1545 case 1: u32HzDiv = 2; break;
1546 case 2: u32HzDiv = 3; break;
1547 case 3: u32HzDiv = 4; break;
1548 case 4: u32HzDiv = 5; break;
1549 case 5: u32HzDiv = 6; break;
1550 case 6: u32HzDiv = 7; break;
1551 case 7: u32HzDiv = 8; break;
1552 }
1553 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1554
1555 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
1556 {
1557 case 0:
1558 Log(("hda: %s requested 8-bit\n", __FUNCTION__));
1559 pAudSetting->fmt = AUD_FMT_S8;
1560 break;
1561 case 1:
1562 Log(("hda: %s requested 16-bit\n", __FUNCTION__));
1563 pAudSetting->fmt = AUD_FMT_S16;
1564 break;
1565 case 2:
1566 Log(("hda: %s requested 20-bit\n", __FUNCTION__));
1567 break;
1568 case 3:
1569 Log(("hda: %s requested 24-bit\n", __FUNCTION__));
1570 break;
1571 case 4:
1572 Log(("hda: %s requested 32-bit\n", __FUNCTION__));
1573 pAudSetting->fmt = AUD_FMT_S32;
1574 break;
1575 default:
1576 AssertMsgFailed(("Unsupported"));
1577 }
1578 pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;
1579 pAudSetting->fmt = AUD_FMT_S16;
1580 pAudSetting->endianness = 0;
1581#undef EXTRACT_VALUE
1582}
1583#endif
1584
1585static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1586{
1587#ifdef IN_RING3
1588# ifdef VBOX_WITH_HDA_CODEC_EMU
1589 /** @todo a bit more investigation is required here. */
1590 int rc = 0;
1591 audsettings_t as;
1592 /* no reason to reopen voice with same settings */
1593 if (u32Value == HDA_REG_IND(pThis, iReg))
1594 return VINF_SUCCESS;
1595 hdaSdFmtToAudSettings(u32Value, &as);
1596 switch (iReg)
1597 {
1598 case HDA_REG_SD0FMT:
1599 rc = hdaCodecOpenVoice(pThis->pCodec, PI_INDEX, &as);
1600 break;
1601 case HDA_REG_SD4FMT:
1602 rc = hdaCodecOpenVoice(pThis->pCodec, PO_INDEX, &as);
1603 break;
1604 default:
1605 Log(("HDA: attempt to change format on %d\n", iReg));
1606 rc = 0;
1607 }
1608 return hdaRegWriteU16(pThis, iReg, u32Value);
1609# else
1610 return hdaRegWriteU16(pThis, iReg, u32Value);
1611# endif
1612#else
1613 return VINF_IOM_R3_MMIO_WRITE;
1614#endif
1615}
1616
1617static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1618{
1619 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1620 if (RT_FAILURE(rc))
1621 AssertRCReturn(rc, VINF_SUCCESS);
1622 return rc;
1623}
1624
1625static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1626{
1627 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1628 if (RT_FAILURE(rc))
1629 AssertRCReturn(rc, VINF_SUCCESS);
1630 return rc;
1631}
1632
1633static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1634{
1635 int rc = VINF_SUCCESS;
1636 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1637 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1638 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1639 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1640
1641 rc = hdaRegReadU32(pThis, iReg, pu32Value);
1642 return rc;
1643}
1644
1645static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1646{
1647 int rc = VINF_SUCCESS;
1648
1649 /*
1650 * if guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1651 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1652 */
1653 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1654 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
1655 {
1656#ifdef IN_RING3
1657 PFNHDACODECVERBPROCESSOR pfn = NULL;
1658 uint64_t resp;
1659 uint32_t cmd = HDA_REG(pThis, IC);
1660 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
1661 {
1662 /*
1663 * 3.4.3 defines behavior of immediate Command status register.
1664 */
1665 LogRel(("hda: guest attempted process immediate verb (%x) with active CORB\n", cmd));
1666 return rc;
1667 }
1668 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1669 Log(("hda: IC:%x\n", cmd));
1670 rc = pThis->pCodec->pfnLookup(pThis->pCodec, cmd, &pfn);
1671 if (RT_FAILURE(rc))
1672 AssertRCReturn(rc, rc);
1673 rc = pfn(pThis->pCodec, cmd, &resp);
1674 if (RT_FAILURE(rc))
1675 AssertRCReturn(rc, rc);
1676 HDA_REG(pThis, IR) = (uint32_t)resp;
1677 Log(("hda: IR:%x\n", HDA_REG(pThis, IR)));
1678 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1679 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1680#else
1681 rc = VINF_IOM_R3_MMIO_WRITE;
1682#endif
1683 return rc;
1684 }
1685 /*
1686 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1687 */
1688 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1689 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
1690 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1691 return rc;
1692}
1693
1694static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1695{
1696 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1697 {
1698 HDA_REG(pThis, RIRBWP) = 0;
1699 }
1700 /* The remaining bits are O, see 6.2.22 */
1701 return VINF_SUCCESS;
1702}
1703
1704static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1705{
1706 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1707 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1708 if (RT_FAILURE(rc))
1709 AssertRCReturn(rc, rc);
1710
1711 switch(iReg)
1712 {
1713 case HDA_REG_CORBLBASE:
1714 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
1715 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
1716 break;
1717 case HDA_REG_CORBUBASE:
1718 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
1719 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1720 break;
1721 case HDA_REG_RIRBLBASE:
1722 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
1723 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
1724 break;
1725 case HDA_REG_RIRBUBASE:
1726 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
1727 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1728 break;
1729 case HDA_REG_DPLBASE:
1730 /** @todo: first bit has special meaning */
1731 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
1732 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
1733 break;
1734 case HDA_REG_DPUBASE:
1735 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
1736 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1737 break;
1738 default:
1739 AssertMsgFailed(("Invalid index"));
1740 }
1741 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
1742 return rc;
1743}
1744
1745static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1746{
1747 uint8_t v = HDA_REG(pThis, RIRBSTS);
1748 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
1749
1750 return hdaProcessInterrupt(pThis);
1751}
1752
1753#ifdef IN_RING3
1754#ifdef LOG_ENABLED
1755static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1756{
1757#if 0
1758 uint64_t addr;
1759 uint32_t len;
1760 uint32_t ioc;
1761 uint8_t bdle[16];
1762 uint32_t counter;
1763 uint32_t i;
1764 uint32_t sum = 0;
1765 Assert(pBdle && pBdle->u32BdleMaxCvi);
1766 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1767 {
1768 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i*16, bdle, 16);
1769 addr = *(uint64_t *)bdle;
1770 len = *(uint32_t *)&bdle[8];
1771 ioc = *(uint32_t *)&bdle[12];
1772 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1773 sum += len;
1774 }
1775 Log(("hda: sum: %d\n", sum));
1776 for (i = 0; i < 8; ++i)
1777 {
1778 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1779 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
1780 i , counter));
1781 }
1782#endif
1783}
1784#endif
1785
1786static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1787{
1788 uint8_t bdle[16];
1789 Assert(( pStreamDesc->u64BaseDMA
1790 && pBdle
1791 && pBdle->u32BdleMaxCvi));
1792 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1793 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1794 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1795 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1796#ifdef LOG_ENABLED
1797 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
1798#endif
1799}
1800
1801DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1802 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1803{
1804 uint32_t cb2Copy;
1805 /*
1806 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
1807 */
1808 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1809 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1810 /*
1811 * we may increase the counter in range of [0, FIFOS + 1]
1812 */
1813 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1814 Assert((u32SoundBackendBufferBytesAvail > 0));
1815
1816 /* sanity check to avoid overriding the backend audio buffer */
1817 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1818 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1819
1820 if (cb2Copy <= pBdle->cbUnderFifoW)
1821 return 0;
1822 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
1823 return cb2Copy;
1824}
1825
1826DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1827 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1828{
1829 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1830 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1831 Assert((cbCopied));
1832 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1833 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
1834 * Probably we need to move the buffer, but it is rather hard to imagine a situation
1835 * where it might happen.
1836 */
1837 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write the entire buffer including unreported bytes */
1838 if ( pBdle->cbUnderFifoW
1839 && pBdle->cbUnderFifoW <= cbCopied)
1840 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1841
1842 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1843 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
1844
1845 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
1846 pBdle->u32BdleCviPos += cbArranged2Copy;
1847
1848 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1849 /* We report all bytes (including previously unreported bytes) */
1850 *pu32DMACursor += cbCopied;
1851 /* Decrease the backend counter by the number of bytes we copied to the backend */
1852 *pu32BackendBufferCapacity -= cbCopied;
1853 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1854 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1855}
1856
1857DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1858 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1859{
1860 Assert((cbCopied, cbArranged2Copy));
1861 *pu32BackendBufferCapacity -= cbCopied;
1862 pBdle->u32BdleCviPos += cbCopied;
1863 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1864 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1865 pBdle->cbUnderFifoW = 0;
1866 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1867 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1868}
1869
1870DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1871 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1872{
1873 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1874 pBdle->u32BdleCviPos += cbCopied;
1875 pBdle->cbUnderFifoW += cbCopied;
1876 /* In case of a read transaction we're always copying from the backend buffer */
1877 if (pu32BackendBufferCapacity)
1878 *pu32BackendBufferCapacity -= cbCopied;
1879 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1880 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
1881}
1882
1883DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1884{
1885 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1886 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1887
1888 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1889
1890 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1891 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1892 hdaUpdatePosBuf(pThis, pStreamDesc);
1893
1894 /* don't touch BdleCvi counter on uninitialized descriptor */
1895 if ( pBdle->u32BdleCviPos
1896 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1897 {
1898 pBdle->u32BdleCviPos = 0;
1899 pBdle->u32BdleCvi++;
1900 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1901 pBdle->u32BdleCvi = 0;
1902 }
1903 return fOnBufferEdge;
1904}
1905
1906DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1907 uint32_t cbInc)
1908{
1909 /*
1910 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
1911 * (ICH6 datasheet 18.2.38)
1912 */
1913 if (!pBdle->cbUnderFifoW)
1914 {
1915 *pStreamDesc->pu32Lpib += cbInc;
1916
1917 /*
1918 * Assert. The buffer counters should never overlap.
1919 */
1920 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1921
1922 hdaUpdatePosBuf(pThis, pStreamDesc);
1923
1924 }
1925}
1926
1927static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1928{
1929 bool fDoNextTransferLoop = true;
1930 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1931 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1932 {
1933 if ( !pBdle->cbUnderFifoW
1934 && pBdle->fBdleCviIoc)
1935 {
1936 /**
1937 * @todo - more carefully investigate BCIS flag.
1938 * Speech synthesis works fine on Mac Guest if this bit isn't set
1939 * but in general sound quality gets worse.
1940 */
1941 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1942
1943 /*
1944 * we should generate the interrupt if ICE bit of SDCTL register is set.
1945 */
1946 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1947 hdaProcessInterrupt(pThis);
1948 }
1949 fDoNextTransferLoop = false;
1950 }
1951 return fDoNextTransferLoop;
1952}
1953
1954/*
1955 * hdaReadAudio - copies samples from audio backend to DMA.
1956 * Note: this function writes to the DMA buffer immediately, but "reports bytes" when all conditions are met (FIFOW)
1957 */
1958static uint32_t hdaReadAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1959{
1960 PHDABDLEDESC pBdle = &pThis->StInBdle;
1961 uint32_t cbTransferred = 0;
1962 uint32_t cb2Copy = 0;
1963 uint32_t cbBackendCopy = 0;
1964
1965 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1966
1967 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1968 if (!cb2Copy)
1969 /* if we enter here we can't report "unreported bits" */
1970 *fStop = true;
1971 else
1972 {
1973 /*
1974 * read from backend input line to the last unreported position or at the begining.
1975 */
1976 cbBackendCopy = AUD_read(pThis->pCodec->SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1977 /*
1978 * write the HDA DMA buffer
1979 */
1980 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1981
1982 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
1983 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1984
1985 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pThis, 0))
1986 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1987 else
1988 {
1989 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1990 *fStop = true;
1991 }
1992 }
1993
1994 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
1995 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1996 return cbTransferred;
1997}
1998
1999static uint32_t hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
2000{
2001 PHDABDLEDESC pBdle = &pThis->StOutBdle;
2002 uint32_t cbTransferred = 0;
2003 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
2004 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
2005
2006 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2007
2008 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
2009
2010 /*
2011 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
2012 * previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
2013 */
2014 if (!cb2Copy)
2015 *fStop = true;
2016 else
2017 {
2018 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
2019 /*
2020 * Write to audio backend. we should ensure that we have enough bytes to copy to the backend.
2021 */
2022 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
2023 {
2024 /*
2025 * Feed the newly fetched samples, including unreported ones, to the backend.
2026 */
2027 cbBackendCopy = AUD_write (pThis->pCodec->SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
2028 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
2029 }
2030 else
2031 {
2032 /* Not enough bytes to be processed and reported, we'll try our luck next time around */
2033 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
2034 *fStop = true;
2035 }
2036 }
2037
2038 Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
2039 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransferred:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
2040 return cbTransferred;
2041}
2042
2043/**
2044 * @interface_method_impl{HDACODEC,pfnReset}
2045 */
2046DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2047{
2048 PHDASTATE pThis = (PHDASTATE)pCodec->pvHDAState;
2049 NOREF(pThis);
2050 return VINF_SUCCESS;
2051}
2052
2053DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
2054 PHDASTREAMTRANSFERDESC pStreamDesc)
2055{
2056 Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
2057
2058 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
2059 pStreamDesc->u8Strm = u8Strm;
2060 pStreamDesc->u32Ctl = HDA_STREAM_REG(pThis, CTL, u8Strm);
2061 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2062 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2063 pStreamDesc->pu32Lpib = &HDA_STREAM_REG(pThis, LPIB, u8Strm);
2064 pStreamDesc->pu32Sts = &HDA_STREAM_REG(pThis, STS, u8Strm);
2065 pStreamDesc->u32Cbl = HDA_STREAM_REG(pThis, CBL, u8Strm);
2066 pStreamDesc->u32Fifos = HDA_STREAM_REG(pThis, FIFOS, u8Strm);
2067
2068 pBdle->u32BdleMaxCvi = HDA_STREAM_REG(pThis, LVI, u8Strm);
2069
2070#ifdef LOG_ENABLED
2071 if ( pBdle
2072 && pBdle->u32BdleMaxCvi)
2073 {
2074 Log(("Initialization of transfer descriptor:\n"));
2075 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2076 }
2077#endif
2078}
2079
2080
2081/**
2082 * @interface_method_impl{HDACODEC,pfnTransfer}
2083 */
2084static DECLCALLBACK(void) hdaTransfer(PHDACODEC pCodec, ENMSOUNDSOURCE src, int avail)
2085{
2086 PHDASTATE pThis = (PHDASTATE)pCodec->pvHDAState;
2087 uint8_t u8Strm = 0;
2088 PHDABDLEDESC pBdle = NULL;
2089
2090 switch (src)
2091 {
2092 case PO_INDEX:
2093 {
2094 u8Strm = 4;
2095 pBdle = &pThis->StOutBdle;
2096 break;
2097 }
2098 case PI_INDEX:
2099 {
2100 u8Strm = 0;
2101 pBdle = &pThis->StInBdle;
2102 break;
2103 }
2104 default:
2105 return;
2106 }
2107
2108 HDASTREAMTRANSFERDESC StreamDesc;
2109 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2110
2111 bool fStop = false;
2112 while (avail && !fStop)
2113 {
2114 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
2115 && avail
2116 && StreamDesc.u64BaseDMA);
2117
2118 /* Fetch the Buffer Descriptor Entry (BDE). */
2119
2120 if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
2121 hdaFetchBdle(pThis, pBdle, &StreamDesc);
2122 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2123 Assert((avail >= 0 && (StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib)))); /* sanity */
2124 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
2125 Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
2126 Log(("hda: CBL=%d, LPIB=%d\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
2127 uint32_t cb;
2128 switch (src)
2129 {
2130 case PO_INDEX:
2131 cb = hdaWriteAudio(pThis, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
2132 break;
2133 case PI_INDEX:
2134 cb = hdaReadAudio(pThis, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
2135 break;
2136 default:
2137 cb = 0;
2138 fStop = true;
2139 AssertMsgFailed(("Unsupported"));
2140 }
2141 Assert(cb <= StreamDesc.u32Fifos + 1);
2142 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2143
2144 /* Process end of buffer condition. */
2145 hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cb);
2146 fStop = !fStop ? !hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc) : fStop;
2147 }
2148}
2149#endif
2150
2151/* MMIO callbacks */
2152
2153/**
2154 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
2155 *
2156 * @note During implementation, we discovered so-called "forgotten" or "hole"
2157 * registers whose description is not listed in the RPM, datasheet, or
2158 * spec.
2159 */
2160PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2161{
2162 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2163 int rc;
2164
2165 /*
2166 * Look up and log.
2167 */
2168 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2169 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
2170#ifdef LOG_ENABLED
2171 unsigned const cbLog = cb;
2172 uint32_t offRegLog = offReg;
2173#endif
2174
2175 Log(("hdaMMIORead: offReg=%#x cb=%#x\n", offReg, cb));
2176#define NEW_READ_CODE
2177#ifdef NEW_READ_CODE
2178 Assert(cb == 4); Assert((offReg & 3) == 0);
2179
2180 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2181 Log(("hda: access to registers except GCTL is blocked while reset\n"));
2182
2183 if (idxRegDsc == -1)
2184 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
2185
2186 if (idxRegDsc != -1)
2187 {
2188 /* ASSUMES gapless DWORD at end of map. */
2189 if (g_aHdaRegMap[idxRegDsc].size == 4)
2190 {
2191 /*
2192 * Straight forward DWORD access.
2193 */
2194 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
2195 Log(("hda: read %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
2196 }
2197 else
2198 {
2199 /*
2200 * Multi register read (unless there are trailing gaps).
2201 * ASSUMES that only DWORD reads have sideeffects.
2202 */
2203 uint32_t u32Value = 0;
2204 unsigned cbLeft = 4;
2205 do
2206 {
2207 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
2208 uint32_t u32Tmp = 0;
2209
2210 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
2211 Log(("hda: read %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
2212 if (rc != VINF_SUCCESS)
2213 break;
2214 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
2215
2216 cbLeft -= cbReg;
2217 offReg += cbReg;
2218 idxRegDsc++;
2219 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
2220
2221 if (rc == VINF_SUCCESS)
2222 *(uint32_t *)pv = u32Value;
2223 else
2224 Assert(!IOM_SUCCESS(rc));
2225 }
2226 }
2227 else
2228 {
2229 rc = VINF_IOM_MMIO_UNUSED_FF;
2230 Log(("hda: hole at %x is accessed for read\n", offReg));
2231 }
2232#else
2233 if (idxRegDsc != -1)
2234 {
2235 /** @todo r=bird: Accesses crossing register boundraries aren't handled
2236 * right from what I can tell? If they are, please explain
2237 * what the rules are. */
2238 uint32_t mask = 0;
2239 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2240 uint32_t u32Value = 0;
2241 switch(cb)
2242 {
2243 case 1: mask = 0x000000ff; break;
2244 case 2: mask = 0x0000ffff; break;
2245 case 4:
2246 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2247 case 8:
2248 mask = 0xffffffff;
2249 cb = 4;
2250 break;
2251 }
2252#if 0
2253 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
2254 */
2255 //Assert((cb <= g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset)));
2256 if (cb > g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset))
2257 {
2258 int off = cb - (g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset));
2259 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2260 if (RT_FAILURE(rc))
2261 AssertRCReturn (rc, rc);
2262 }
2263 //Assert(((offReg - g_aHdaRegMap[idxRegDsc].offset) == 0));
2264#endif
2265 mask <<= shift;
2266 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Value);
2267 *(uint32_t *)pv |= (u32Value & mask);
2268 Log(("hda: read %s[%x/%x]\n", g_aHdaRegMap[idxRegDsc].abbrev, u32Value, *(uint32_t *)pv));
2269 }
2270 else
2271 {
2272 *(uint32_t *)pv = 0xFF;
2273 Log(("hda: hole at %x is accessed for read\n", offReg));
2274 rc = VINF_SUCCESS;
2275 }
2276#endif
2277
2278 /*
2279 * Log the outcome.
2280 */
2281#ifdef LOG_ENABLED
2282 if (cbLog == 4)
2283 Log(("hdaMMIORead: @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
2284 else if (cbLog == 2)
2285 Log(("hdaMMIORead: @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
2286 else if (cbLog == 1)
2287 Log(("hdaMMIORead: @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
2288#endif
2289 return rc;
2290}
2291
2292
2293DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
2294{
2295 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2296 Log(("hda: access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
2297
2298 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2299#ifdef LOG_ENABLED
2300 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
2301#endif
2302 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
2303 Log(("hda: write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
2304 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
2305 return rc;
2306}
2307
2308
2309/**
2310 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
2311 */
2312PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2313{
2314 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2315 int rc;
2316
2317 /*
2318 * The behavior of accesses that aren't aligned on natural boundraries is
2319 * undefined. Just reject them outright.
2320 */
2321 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
2322 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
2323 if (GCPhysAddr & (cb - 1))
2324 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
2325
2326 /*
2327 * Look up and log the access.
2328 */
2329 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2330 int idxRegDsc = hdaRegLookup(pThis, offReg);
2331 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2332 uint64_t u64Value;
2333 if (cb == 4) u64Value = *(uint32_t const *)pv;
2334 else if (cb == 2) u64Value = *(uint16_t const *)pv;
2335 else if (cb == 1) u64Value = *(uint8_t const *)pv;
2336 else if (cb == 8) u64Value = *(uint64_t const *)pv;
2337 else
2338 {
2339 u64Value = 0; /* shut up gcc. */
2340 AssertReleaseMsgFailed(("%d\n", cb));
2341 }
2342
2343#ifdef LOG_ENABLED
2344 uint32_t const u32LogOldValue = idxRegDsc != -1 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
2345 uint32_t const offRegLog = offReg;
2346 int const idxRegLog = idxRegMem;
2347 if (idxRegDsc == -1)
2348 Log(("hdaMMIOWrite: @%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
2349 else if (cb == 4)
2350 Log(("hdaMMIOWrite: @%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2351 else if (cb == 2)
2352 Log(("hdaMMIOWrite: @%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2353 else if (cb == 1)
2354 Log(("hdaMMIOWrite: @%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2355 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size != cb)
2356 Log(("hdaMMIOWrite: size=%d != cb=%d!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
2357#endif
2358
2359#define NEW_WRITE_CODE
2360#ifdef NEW_WRITE_CODE
2361 /*
2362 * Try for a direct hit first.
2363 */
2364 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
2365 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
2366 /*
2367 * Partial or multiple register access, loop thru the requested memory.
2368 */
2369 else
2370 {
2371 /* If it's an access beyond the start of the register, shift the input
2372 value and fill in missing bits. Natural alignment rules means we
2373 will only see 1 or 2 byte accesses of this kind, so no risk of
2374 shifting out input values. */
2375 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
2376 {
2377 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
2378 offReg -= cbBefore;
2379 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2380 u64Value <<= cbBefore * 8;
2381 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
2382 Log(("hdaMMIOWrite: Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
2383 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
2384 }
2385
2386 /* Loop thru the write area, it may cover multiple registers. */
2387 rc = VINF_SUCCESS;
2388 for (;;)
2389 {
2390 uint32_t cbReg;
2391 if (idxRegDsc != -1)
2392 {
2393 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2394 cbReg = g_aHdaRegMap[idxRegDsc].size;
2395 if (cb < cbReg)
2396 {
2397 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
2398 Log(("hdaMMIOWrite: Supplying missing bits (%#x): %#llx -> %#llx ...\n",
2399 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
2400 }
2401 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
2402 }
2403 else
2404 {
2405 LogRel(("hda: Invalid write access @0x%x!\n", offReg));
2406 cbReg = 1;
2407 }
2408 if (rc != VINF_SUCCESS)
2409 break;
2410 if (cbReg >= cb)
2411 break;
2412
2413 /* advance */
2414 offReg += cbReg;
2415 cb -= cbReg;
2416 u64Value >>= cbReg * 8;
2417 if (idxRegDsc == -1)
2418 idxRegDsc = hdaRegLookup(pThis, offReg);
2419 else
2420 {
2421 idxRegDsc++;
2422 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
2423 || g_aHdaRegMap[idxRegDsc].offset != offReg)
2424 idxRegDsc = -1;
2425 }
2426 }
2427 }
2428#else
2429 if (idxRegDsc != -1)
2430 {
2431 /** @todo r=bird: This looks like code for handling unaligned register
2432 * accesses. If it isn't, then add a comment explaining what you're
2433 * trying to do here. OTOH, if it is then it has the following
2434 * issues:
2435 * -# You're calculating the wrong new value for the register.
2436 * -# You're not handling cross register accesses. Imagine a
2437 * 4-byte write starting at CORBCTL, or a 8-byte write.
2438 *
2439 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
2440 * nobody seems to be using it and it just adds complexity when reading
2441 * the code.
2442 *
2443 */
2444 uint32_t u32CurValue = pThis->au32Regs[idxRegMem];
2445 uint32_t u32NewValue;
2446 uint32_t mask;
2447 switch (cb)
2448 {
2449 case 1:
2450 u32NewValue = *(uint8_t const *)pv;
2451 mask = 0xff;
2452 break;
2453 case 2:
2454 u32NewValue = *(uint16_t const *)pv;
2455 mask = 0xffff;
2456 break;
2457 case 4:
2458 case 8:
2459 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2460 u32NewValue = *(uint32_t const *)pv;
2461 mask = 0xffffffff;
2462 cb = 4;
2463 break;
2464 default:
2465 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
2466 }
2467 /* cross-register access, see corresponding comment in hdaMMIORead */
2468 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2469 mask <<= shift;
2470 u32NewValue <<= shift;
2471 u32NewValue &= mask;
2472 u32NewValue |= (u32CurValue & ~mask);
2473
2474 rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32NewValue);
2475 Log(("hda: write %s:(%x) %x => %x\n", g_aHdaRegMap[idxRegDsc].abbrev, u32NewValue,
2476 u32CurValue, pThis->au32Regs[idxRegMem]));
2477 }
2478 else
2479 rc = VINF_SUCCESS;
2480#endif
2481 Log(("hdaMMIOWrite: @%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2482 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2483 return rc;
2484}
2485
2486
2487/* PCI callback. */
2488
2489#ifdef IN_RING3
2490/**
2491 * @callback_method_impl{FNPCIIOREGIONMAP}
2492 */
2493static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
2494 PCIADDRESSSPACE enmType)
2495{
2496 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2497 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
2498 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
2499 int rc;
2500
2501 /*
2502 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
2503 *
2504 * Let IOM talk DWORDs when reading, saves a lot of complications. On
2505 * writing though, we have to do it all ourselves because of sideeffects.
2506 */
2507 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2508 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2509#ifdef NEW_READ_CODE
2510 IOMMMIO_FLAGS_READ_DWORD |
2511#else
2512 IOMMMIO_FLAGS_READ_PASSTHRU |
2513#endif
2514 IOMMMIO_FLAGS_WRITE_PASSTHRU,
2515 hdaMMIOWrite, hdaMMIORead, "HDA");
2516
2517 if (RT_FAILURE(rc))
2518 return rc;
2519
2520 if (pThis->fR0Enabled)
2521 {
2522 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
2523 "hdaMMIOWrite", "hdaMMIORead");
2524 if (RT_FAILURE(rc))
2525 return rc;
2526 }
2527
2528 if (pThis->fRCEnabled)
2529 {
2530 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
2531 "hdaMMIOWrite", "hdaMMIORead");
2532 if (RT_FAILURE(rc))
2533 return rc;
2534 }
2535
2536 pThis->MMIOBaseAddr = GCPhysAddress;
2537 return VINF_SUCCESS;
2538}
2539
2540
2541/* Saved state callbacks. */
2542
2543/**
2544 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2545 */
2546static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2547{
2548 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2549 /* Save Codec nodes states */
2550 hdaCodecSaveState(pThis->pCodec, pSSM);
2551
2552 /* Save MMIO registers */
2553 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
2554 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
2555 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
2556
2557 /* Save HDA dma counters */
2558 SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2559 SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2560 SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2561 return VINF_SUCCESS;
2562}
2563
2564
2565/**
2566 * @callback_method_impl{FNSSMDEVLOADEXEC}
2567 */
2568static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2569{
2570 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2571
2572 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2573
2574 /*
2575 * Load Codec nodes states.
2576 */
2577 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
2578 if (RT_FAILURE(rc))
2579 return rc;
2580
2581 /*
2582 * Load MMIO registers.
2583 */
2584 uint32_t cRegs;
2585 switch (uVersion)
2586 {
2587 case HDA_SSM_VERSION_1:
2588 /* Starting with r71199, we would save 112 instead of 113
2589 registers due to some code cleanups. This only affected trunk
2590 builds in the 4.1 development period. */
2591 cRegs = 113;
2592 if (SSMR3HandleRevision(pSSM) >= 71199)
2593 {
2594 uint32_t uVer = SSMR3HandleVersion(pSSM);
2595 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
2596 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
2597 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
2598 cRegs = 112;
2599 }
2600 break;
2601
2602 case HDA_SSM_VERSION_2:
2603 case HDA_SSM_VERSION_3:
2604 cRegs = 112;
2605 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
2606 break;
2607
2608 case HDA_SSM_VERSION:
2609 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
2610 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
2611 LogRel(("hda: cRegs is %d, expected %d\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
2612 break;
2613
2614 default:
2615 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2616 }
2617
2618 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
2619 {
2620 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
2621 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
2622 }
2623 else
2624 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
2625
2626 /*
2627 * Load HDA dma counters.
2628 */
2629 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
2630 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
2631 SSMR3GetStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), fFlags, paFields, NULL);
2632 SSMR3GetStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), fFlags, paFields, NULL);
2633 rc = SSMR3GetStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), fFlags, paFields, NULL);
2634 AssertRCReturn(rc, rc);
2635
2636 /*
2637 * Update stuff after the state changes.
2638 */
2639 AUD_set_active_in(pThis->pCodec->SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2640 AUD_set_active_out(pThis->pCodec->SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2641
2642 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
2643 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
2644 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
2645 return VINF_SUCCESS;
2646}
2647
2648
2649/* Debug and log type formatters. */
2650
2651/**
2652 * @callback_method_impl{FNRTSTRFORMATTYPE}
2653 */
2654static DECLCALLBACK(size_t)
2655hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2656 const char *pszType, void const *pvValue,
2657 int cchWidth, int cchPrecision, unsigned fFlags,
2658 void *pvUser)
2659{
2660 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
2661 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2662 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
2663 sdCtl,
2664 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> HDA_SDCTL_NUM_SHIFT,
2665 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
2666 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
2667 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
2668 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
2669 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
2670 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
2671 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
2672}
2673
2674/**
2675 * @callback_method_impl{FNRTSTRFORMATTYPE}
2676 */
2677static DECLCALLBACK(size_t)
2678hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2679 const char *pszType, void const *pvValue,
2680 int cchWidth, int cchPrecision, unsigned fFlags,
2681 void *pvUser)
2682{
2683 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
2684 uint32_t cb;
2685 switch (uSdFifos)
2686 {
2687 case HDA_SDONFIFO_16B: cb = 16; break;
2688 case HDA_SDONFIFO_32B: cb = 32; break;
2689 case HDA_SDONFIFO_64B: cb = 64; break;
2690 case HDA_SDONFIFO_128B: cb = 128; break;
2691 case HDA_SDONFIFO_192B: cb = 192; break;
2692 case HDA_SDONFIFO_256B: cb = 256; break;
2693 case HDA_SDINFIFO_120B: cb = 120; break;
2694 case HDA_SDINFIFO_160B: cb = 160; break;
2695 default: cb = 0; break;
2696 }
2697 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
2698}
2699
2700/**
2701 * @callback_method_impl{FNRTSTRFORMATTYPE}
2702 */
2703static DECLCALLBACK(size_t)
2704hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2705 const char *pszType, void const *pvValue,
2706 int cchWidth, int cchPrecision, unsigned fFlags,
2707 void *pvUser)
2708{
2709 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
2710 uint32_t cb;
2711 switch (uSdFifos)
2712 {
2713 case HDA_SDFIFOW_8B: cb = 8; break;
2714 case HDA_SDFIFOW_16B: cb = 16; break;
2715 case HDA_SDFIFOW_32B: cb = 32; break;
2716 default: cb = 0; break;
2717 }
2718 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
2719}
2720
2721/**
2722 * @callback_method_impl{FNRTSTRFORMATTYPE}
2723 */
2724static DECLCALLBACK(size_t)
2725hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2726 const char *pszType, void const *pvValue,
2727 int cchWidth, int cchPrecision, unsigned fFlags,
2728 void *pvUser)
2729{
2730 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
2731 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2732 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
2733 uSdSts,
2734 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
2735 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
2736 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
2737 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
2738}
2739
2740
2741static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
2742{
2743 int iReg = 0;
2744 for (; iReg < HDA_NREGS; ++iReg)
2745 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
2746 return iReg;
2747 return -1;
2748}
2749
2750
2751static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
2752{
2753 Assert( pThis
2754 && iHdaIndex >= 0
2755 && iHdaIndex < HDA_NREGS);
2756 pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
2757}
2758
2759
2760/**
2761 * @callback_method_impl{FNDBGFHANDLERDEV}
2762 */
2763static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2764{
2765 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2766 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
2767 if (iHdaRegisterIndex != -1)
2768 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
2769 else
2770 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
2771 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
2772}
2773
2774
2775static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
2776{
2777 Assert( pThis
2778 && iHdaStrmIndex >= 0
2779 && iHdaStrmIndex < 7);
2780 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
2781 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
2782 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
2783 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
2784 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
2785}
2786
2787
2788static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
2789{
2790 /* todo: add args parsing */
2791 return -1;
2792}
2793
2794
2795/**
2796 * @callback_method_impl{FNDBGFHANDLERDEV}
2797 */
2798static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2799{
2800 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2801 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
2802 if (iHdaStrmIndex != -1)
2803 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
2804 else
2805 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
2806 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
2807}
2808
2809/**
2810 * @callback_method_impl{FNDBGFHANDLERDEV}
2811 */
2812static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2813{
2814 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2815 if (pThis->pCodec->pfnCodecDbgListNodes)
2816 pThis->pCodec->pfnCodecDbgListNodes(pThis->pCodec, pHlp, pszArgs);
2817 else
2818 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2819}
2820
2821
2822/**
2823 * @callback_method_impl{FNDBGFHANDLERDEV}
2824 */
2825static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2826{
2827 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2828 if (pThis->pCodec->pfnCodecDbgSelector)
2829 pThis->pCodec->pfnCodecDbgSelector(pThis->pCodec, pHlp, pszArgs);
2830 else
2831 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2832}
2833
2834
2835/* PDMIBASE */
2836
2837/**
2838 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2839 */
2840static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
2841{
2842 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
2843 Assert(&pThis->IBase == pInterface);
2844
2845 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2846 return NULL;
2847}
2848
2849
2850/* PDMDEVREG */
2851
2852/**
2853 * Reset notification.
2854 *
2855 * @returns VBox status.
2856 * @param pDevIns The device instance data.
2857 *
2858 * @remark The original sources didn't install a reset handler, but it seems to
2859 * make sense to me so we'll do it.
2860 */
2861static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
2862{
2863 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2864 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
2865 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
2866 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
2867 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
2868 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
2869 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
2870 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
2871 HDA_REG(pThis, CORBRP) = 0x0;
2872 HDA_REG(pThis, RIRBWP) = 0x0;
2873
2874 Log(("hda: inter HDA reset.\n"));
2875 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
2876
2877 if (pThis->pu32CorbBuf)
2878 memset(pThis->pu32CorbBuf, 0, pThis->cbCorbBuf);
2879 else
2880 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
2881
2882 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
2883 if (pThis->pu64RirbBuf)
2884 memset(pThis->pu64RirbBuf, 0, pThis->cbRirbBuf);
2885 else
2886 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
2887
2888 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2889
2890 HDABDLEDESC StEmptyBdle;
2891 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2892 {
2893 HDASTREAMTRANSFERDESC StreamDesc;
2894 PHDABDLEDESC pBdle = NULL;
2895 if (u8Strm == 0)
2896 pBdle = &pThis->StInBdle;
2897 else if(u8Strm == 4)
2898 pBdle = &pThis->StOutBdle;
2899 else
2900 {
2901 memset(&StEmptyBdle, 0, sizeof(HDABDLEDESC));
2902 pBdle = &StEmptyBdle;
2903 }
2904 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2905 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
2906 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
2907 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
2908 }
2909
2910 /* emulation of codec "wake up" (HDA spec 5.5.1 and 6.5)*/
2911 HDA_REG(pThis, STATESTS) = 0x1;
2912
2913 Log(("hda: reset finished\n"));
2914}
2915
2916
2917/**
2918 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2919 */
2920static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
2921{
2922 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2923
2924 if (pThis->pCodec)
2925 {
2926 int rc = hdaCodecDestruct(pThis->pCodec);
2927 AssertRC(rc);
2928
2929 RTMemFree(pThis->pCodec);
2930 pThis->pCodec = NULL;
2931 }
2932
2933 RTMemFree(pThis->pu32CorbBuf);
2934 pThis->pu32CorbBuf = NULL;
2935
2936 RTMemFree(pThis->pu64RirbBuf);
2937 pThis->pu64RirbBuf = NULL;
2938
2939 return VINF_SUCCESS;
2940}
2941
2942/**
2943 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2944 */
2945static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2946{
2947 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2948 int rc;
2949
2950 Assert(iInstance == 0);
2951 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2952
2953 /*
2954 * Validations.
2955 */
2956 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
2957 "RCEnabled\0"))
2958 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2959 N_ ("Invalid configuration for the Intel HDA device"));
2960
2961 rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
2962 if (RT_FAILURE(rc))
2963 return PDMDEV_SET_ERROR(pDevIns, rc,
2964 N_("HDA configuration error: failed to read RCEnabled as boolean"));
2965 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
2966 if (RT_FAILURE(rc))
2967 return PDMDEV_SET_ERROR(pDevIns, rc,
2968 N_("HDA configuration error: failed to read R0Enabled as boolean"));
2969
2970 /*
2971 * Initialize data (most of it anyway).
2972 */
2973 pThis->pDevInsR3 = pDevIns;
2974 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2975 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2976 /* IBase */
2977 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
2978
2979 /* PCI Device */
2980 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
2981 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
2982
2983 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
2984 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2985 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
2986 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
2987 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
2988 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2989 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
2990 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
2991 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2992 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
2993 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
2994
2995#if defined(HDA_AS_PCI_EXPRESS)
2996 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
2997#elif defined(VBOX_WITH_MSI_DEVICES)
2998 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
2999#else
3000 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
3001#endif
3002
3003 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
3004 /// of these values needs to be properly documented!
3005 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
3006 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
3007
3008 /* Power Management */
3009 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
3010 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
3011 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
3012
3013#ifdef HDA_AS_PCI_EXPRESS
3014 /* PCI Express */
3015 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
3016 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
3017 /* Device flags */
3018 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
3019 /* version */ 0x1 |
3020 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
3021 /* MSI */ (100) << 9 );
3022 /* Device capabilities */
3023 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
3024 /* Device control */
3025 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
3026 /* Device status */
3027 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
3028 /* Link caps */
3029 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
3030 /* Link control */
3031 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
3032 /* Link status */
3033 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
3034 /* Slot capabilities */
3035 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
3036 /* Slot control */
3037 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
3038 /* Slot status */
3039 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
3040 /* Root control */
3041 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
3042 /* Root capabilities */
3043 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
3044 /* Root status */
3045 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
3046 /* Device capabilities 2 */
3047 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
3048 /* Device control 2 */
3049 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
3050 /* Link control 2 */
3051 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
3052 /* Slot control 2 */
3053 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
3054#endif
3055
3056 /*
3057 * Register the PCI device.
3058 */
3059 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
3060 if (RT_FAILURE(rc))
3061 return rc;
3062
3063 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
3064 if (RT_FAILURE(rc))
3065 return rc;
3066
3067#ifdef VBOX_WITH_MSI_DEVICES
3068 PDMMSIREG MsiReg;
3069 RT_ZERO(MsiReg);
3070 MsiReg.cMsiVectors = 1;
3071 MsiReg.iMsiCapOffset = 0x60;
3072 MsiReg.iMsiNextOffset = 0x50;
3073 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3074 if (RT_FAILURE(rc))
3075 {
3076 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
3077 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
3078 }
3079#endif
3080
3081 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
3082 if (RT_FAILURE(rc))
3083 return rc;
3084
3085 /*
3086 * Attach driver.
3087 */
3088 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Audio Driver Port");
3089 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3090 Log(("hda: No attached driver!\n"));
3091 else if (RT_FAILURE(rc))
3092 {
3093 AssertMsgFailed(("Failed to attach Intel HDA LUN #0! rc=%Rrc\n", rc));
3094 return rc;
3095 }
3096
3097 /* Construct codec state. */
3098 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
3099 if (!pThis->pCodec)
3100 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("HDA: Out of memory allocating codec state"));
3101
3102 pThis->pCodec->pvHDAState = pThis;
3103 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, pCfgHandle);
3104 if (RT_FAILURE(rc))
3105 AssertRCReturn(rc, rc);
3106
3107 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
3108 verb F20 should provide device/codec recognition. */
3109 Assert(pThis->pCodec->u16VendorId);
3110 Assert(pThis->pCodec->u16DeviceId);
3111 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
3112 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
3113
3114 hdaReset(pDevIns);
3115 pThis->pCodec->id = 0;
3116 pThis->pCodec->pfnTransfer = hdaTransfer;
3117 pThis->pCodec->pfnReset = hdaCodecReset;
3118
3119 /*
3120 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
3121 * hdaReset shouldn't affects these registers.
3122 */
3123 HDA_REG(pThis, WAKEEN) = 0x0;
3124 HDA_REG(pThis, STATESTS) = 0x0;
3125
3126 /*
3127 * Debug and string formatter types.
3128 */
3129 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
3130 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
3131 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
3132 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
3133
3134 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
3135 AssertRC(rc);
3136 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
3137 AssertRC(rc);
3138 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
3139 AssertRC(rc);
3140 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
3141 AssertRC(rc);
3142#if 0
3143 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
3144 AssertRC(rc);
3145#endif
3146
3147 /*
3148 * Some debug assertions.
3149 */
3150 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
3151 {
3152 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
3153 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
3154
3155 /* binary search order. */
3156 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
3157 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3158 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3159
3160 /* alignment. */
3161 AssertReleaseMsg( pReg->size == 1
3162 || (pReg->size == 2 && (pReg->offset & 1) == 0)
3163 || (pReg->size == 3 && (pReg->offset & 3) == 0)
3164 || (pReg->size == 4 && (pReg->offset & 3) == 0),
3165 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3166
3167 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
3168 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
3169 if (pReg->offset & 3)
3170 {
3171 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
3172 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3173 if (pPrevReg)
3174 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
3175 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3176 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
3177 }
3178#if 0
3179 if ((pReg->offset + pReg->size) & 3)
3180 {
3181 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3182 if (pNextReg)
3183 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
3184 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3185 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3186 }
3187#endif
3188
3189 /* The final entry is a full dword, no gaps! Allows shortcuts. */
3190 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
3191 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3192 }
3193
3194 return VINF_SUCCESS;
3195}
3196
3197/**
3198 * The device registration structure.
3199 */
3200const PDMDEVREG g_DeviceICH6_HDA =
3201{
3202 /* u32Version */
3203 PDM_DEVREG_VERSION,
3204 /* szName */
3205 "hda",
3206 /* szRCMod */
3207 "VBoxDDGC.gc",
3208 /* szR0Mod */
3209 "VBoxDDR0.r0",
3210 /* pszDescription */
3211 "Intel HD Audio Controller",
3212 /* fFlags */
3213 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
3214 /* fClass */
3215 PDM_DEVREG_CLASS_AUDIO,
3216 /* cMaxInstances */
3217 1,
3218 /* cbInstance */
3219 sizeof(HDASTATE),
3220 /* pfnConstruct */
3221 hdaConstruct,
3222 /* pfnDestruct */
3223 hdaDestruct,
3224 /* pfnRelocate */
3225 NULL,
3226 /* pfnMemSetup */
3227 NULL,
3228 /* pfnPowerOn */
3229 NULL,
3230 /* pfnReset */
3231 hdaReset,
3232 /* pfnSuspend */
3233 NULL,
3234 /* pfnResume */
3235 NULL,
3236 /* pfnAttach */
3237 NULL,
3238 /* pfnDetach */
3239 NULL,
3240 /* pfnQueryInterface. */
3241 NULL,
3242 /* pfnInitComplete */
3243 NULL,
3244 /* pfnPowerOff */
3245 NULL,
3246 /* pfnSoftReset */
3247 NULL,
3248 /* u32VersionEnd */
3249 PDM_DEVREG_VERSION
3250};
3251
3252#endif /* IN_RING3 */
3253#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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