VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 54230

Last change on this file since 54230 was 54230, checked in by vboxsync, 10 years ago

PDM/Audio: Update.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 160.6 KB
Line 
1/* $Id: DevIchHda.cpp 54230 2015-02-17 13:13:02Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2015 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/vmm/pdmaudioifs.h>
27#include <VBox/version.h>
28
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#ifdef IN_RING3
33# include <iprt/uuid.h>
34# include <iprt/string.h>
35# include <iprt/mem.h>
36#endif
37#include <iprt/list.h>
38
39#if 0
40/* Warning: Enabling this causes a *lot* of output! */
41#ifdef LOG_GROUP
42# undef LOG_GROUP
43#endif
44#define LOG_GROUP LOG_GROUP_DEV_AUDIO
45#include <VBox/log.h>
46#endif
47
48#include "VBoxDD.h"
49
50#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
51# include "AudioMixer.h"
52#else
53 extern "C" {
54 #include "audio.h"
55 }
56#endif
57#include "DevIchHdaCodec.h"
58
59/*******************************************************************************
60* Defined Constants And Macros *
61*******************************************************************************/
62//#define HDA_AS_PCI_EXPRESS
63#define VBOX_WITH_INTEL_HDA
64
65#if (defined(DEBUG) && defined(DEBUG_andy))
66/* Enables experimental support for separate mic-in handling.
67 Do not enable this yet for regular builds, as this needs more testing first! */
68# define VBOX_WITH_HDA_MIC_IN
69#endif
70
71#if defined(VBOX_WITH_HP_HDA)
72/* HP Pavilion dv4t-1300 */
73# define HDA_PCI_VENDOR_ID 0x103c
74# define HDA_PCI_DEVICE_ID 0x30f7
75#elif defined(VBOX_WITH_INTEL_HDA)
76/* Intel HDA controller */
77# define HDA_PCI_VENDOR_ID 0x8086
78# define HDA_PCI_DEVICE_ID 0x2668
79#elif defined(VBOX_WITH_NVIDIA_HDA)
80/* nVidia HDA controller */
81# define HDA_PCI_VENDOR_ID 0x10de
82# define HDA_PCI_DEVICE_ID 0x0ac0
83#else
84# error "Please specify your HDA device vendor/device IDs"
85#endif
86
87/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
88 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
89 * is read only except for bit 15 like the HDA spec states.
90 *
91 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
92 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
93#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
94
95#define HDA_NREGS 114
96#define HDA_NREGS_SAVED 112
97
98/**
99 * NB: Register values stored in memory (au32Regs[]) are indexed through
100 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
101 * register descriptors in g_aHdaRegMap[] are indexed through the
102 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
103 *
104 * The au32Regs[] layout is kept unchanged for saved state
105 * compatibility. */
106
107/* Registers */
108#define HDA_REG_IND_NAME(x) HDA_REG_##x
109#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
110#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
111#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
112#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
113#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
114#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
115#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
116
117
118#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
119#define HDA_RMX_GCAP 0
120/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
121 * oss (15:12) - number of output streams supported
122 * iss (11:8) - number of input streams supported
123 * bss (7:3) - number of bidirectional streams supported
124 * bds (2:1) - number of serial data out signals supported
125 * b64sup (0) - 64 bit addressing supported.
126 */
127#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
128 ( (((oss) & 0xF) << 12) \
129 | (((iss) & 0xF) << 8) \
130 | (((bss) & 0x1F) << 3) \
131 | (((bds) & 0x3) << 2) \
132 | ((b64sup) & 1))
133
134#define HDA_REG_VMIN 1 /* 0x02 */
135#define HDA_RMX_VMIN 1
136
137#define HDA_REG_VMAJ 2 /* 0x03 */
138#define HDA_RMX_VMAJ 2
139
140#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
141#define HDA_RMX_OUTPAY 3
142
143#define HDA_REG_INPAY 4 /* 0x06-0x07 */
144#define HDA_RMX_INPAY 4
145
146#define HDA_REG_GCTL 5 /* 0x08-0x0B */
147#define HDA_RMX_GCTL 5
148#define HDA_GCTL_RST_SHIFT 0
149#define HDA_GCTL_FSH_SHIFT 1
150#define HDA_GCTL_UR_SHIFT 8
151
152#define HDA_REG_WAKEEN 6 /* 0x0C */
153#define HDA_RMX_WAKEEN 6
154
155#define HDA_REG_STATESTS 7 /* 0x0E */
156#define HDA_RMX_STATESTS 7
157#define HDA_STATES_SCSF 0x7
158
159#define HDA_REG_GSTS 8 /* 0x10-0x11*/
160#define HDA_RMX_GSTS 8
161#define HDA_GSTS_FSH_SHIFT 1
162
163#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
164#define HDA_RMX_OUTSTRMPAY 112
165
166#define HDA_REG_INSTRMPAY 10 /* 0x1a */
167#define HDA_RMX_INSTRMPAY 113
168
169#define HDA_REG_INTCTL 11 /* 0x20 */
170#define HDA_RMX_INTCTL 9
171#define HDA_INTCTL_GIE_SHIFT 31
172#define HDA_INTCTL_CIE_SHIFT 30
173#define HDA_INTCTL_S0_SHIFT 0
174#define HDA_INTCTL_S1_SHIFT 1
175#define HDA_INTCTL_S2_SHIFT 2
176#define HDA_INTCTL_S3_SHIFT 3
177#define HDA_INTCTL_S4_SHIFT 4
178#define HDA_INTCTL_S5_SHIFT 5
179#define HDA_INTCTL_S6_SHIFT 6
180#define HDA_INTCTL_S7_SHIFT 7
181#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
182
183#define HDA_REG_INTSTS 12 /* 0x24 */
184#define HDA_RMX_INTSTS 10
185#define HDA_INTSTS_GIS_SHIFT 31
186#define HDA_INTSTS_CIS_SHIFT 30
187#define HDA_INTSTS_S0_SHIFT 0
188#define HDA_INTSTS_S1_SHIFT 1
189#define HDA_INTSTS_S2_SHIFT 2
190#define HDA_INTSTS_S3_SHIFT 3
191#define HDA_INTSTS_S4_SHIFT 4
192#define HDA_INTSTS_S5_SHIFT 5
193#define HDA_INTSTS_S6_SHIFT 6
194#define HDA_INTSTS_S7_SHIFT 7
195#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
196
197#define HDA_REG_WALCLK 13 /* 0x24 */
198#define HDA_RMX_WALCLK /* Not defined! */
199
200/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
201 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
202 * the datasheet.
203 */
204#define HDA_REG_SSYNC 14 /* 0x34 */
205#define HDA_RMX_SSYNC 12
206
207#define HDA_REG_CORBLBASE 15 /* 0x40 */
208#define HDA_RMX_CORBLBASE 13
209
210#define HDA_REG_CORBUBASE 16 /* 0x44 */
211#define HDA_RMX_CORBUBASE 14
212
213#define HDA_REG_CORBWP 17 /* 0x48 */
214#define HDA_RMX_CORBWP 15
215
216#define HDA_REG_CORBRP 18 /* 0x4A */
217#define HDA_RMX_CORBRP 16
218#define HDA_CORBRP_RST_SHIFT 15
219#define HDA_CORBRP_WP_SHIFT 0
220#define HDA_CORBRP_WP_MASK 0xFF
221
222#define HDA_REG_CORBCTL 19 /* 0x4C */
223#define HDA_RMX_CORBCTL 17
224#define HDA_CORBCTL_DMA_SHIFT 1
225#define HDA_CORBCTL_CMEIE_SHIFT 0
226
227#define HDA_REG_CORBSTS 20 /* 0x4D */
228#define HDA_RMX_CORBSTS 18
229#define HDA_CORBSTS_CMEI_SHIFT 0
230
231#define HDA_REG_CORBSIZE 21 /* 0x4E */
232#define HDA_RMX_CORBSIZE 19
233#define HDA_CORBSIZE_SZ_CAP 0xF0
234#define HDA_CORBSIZE_SZ 0x3
235/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
236
237#define HDA_REG_RIRBLBASE 22 /* 0x50 */
238#define HDA_RMX_RIRBLBASE 20
239
240#define HDA_REG_RIRBUBASE 23 /* 0x54 */
241#define HDA_RMX_RIRBUBASE 21
242
243#define HDA_REG_RIRBWP 24 /* 0x58 */
244#define HDA_RMX_RIRBWP 22
245#define HDA_RIRBWP_RST_SHIFT 15
246#define HDA_RIRBWP_WP_MASK 0xFF
247
248#define HDA_REG_RINTCNT 25 /* 0x5A */
249#define HDA_RMX_RINTCNT 23
250#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
251
252#define HDA_REG_RIRBCTL 26 /* 0x5C */
253#define HDA_RMX_RIRBCTL 24
254#define HDA_RIRBCTL_RIC_SHIFT 0
255#define HDA_RIRBCTL_DMA_SHIFT 1
256#define HDA_ROI_DMA_SHIFT 2
257
258#define HDA_REG_RIRBSTS 27 /* 0x5D */
259#define HDA_RMX_RIRBSTS 25
260#define HDA_RIRBSTS_RINTFL_SHIFT 0
261#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
262
263#define HDA_REG_RIRBSIZE 28 /* 0x5E */
264#define HDA_RMX_RIRBSIZE 26
265#define HDA_RIRBSIZE_SZ_CAP 0xF0
266#define HDA_RIRBSIZE_SZ 0x3
267
268#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
269#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
270
271
272#define HDA_REG_IC 29 /* 0x60 */
273#define HDA_RMX_IC 27
274
275#define HDA_REG_IR 30 /* 0x64 */
276#define HDA_RMX_IR 28
277
278#define HDA_REG_IRS 31 /* 0x68 */
279#define HDA_RMX_IRS 29
280#define HDA_IRS_ICB_SHIFT 0
281#define HDA_IRS_IRV_SHIFT 1
282
283#define HDA_REG_DPLBASE 32 /* 0x70 */
284#define HDA_RMX_DPLBASE 30
285#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
286
287#define HDA_REG_DPUBASE 33 /* 0x74 */
288#define HDA_RMX_DPUBASE 31
289#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
290#define DPBASE_ENABLED 1
291#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
292
293#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
294#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
295/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
296#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
297
298#define HDA_REG_SD0CTL 34 /* 0x80 */
299#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
300#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
301#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
302#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
303#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
304#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
305#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
306#define HDA_RMX_SD0CTL 32
307#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
308#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
309#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
310#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
311#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
312#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
313#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
314
315#define SD(func, num) SD##num##func
316#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
317#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
318#define HDA_SDCTL_NUM_MASK 0xF
319#define HDA_SDCTL_NUM_SHIFT 20
320#define HDA_SDCTL_DIR_SHIFT 19
321#define HDA_SDCTL_TP_SHIFT 18
322#define HDA_SDCTL_STRIPE_MASK 0x3
323#define HDA_SDCTL_STRIPE_SHIFT 16
324#define HDA_SDCTL_DEIE_SHIFT 4
325#define HDA_SDCTL_FEIE_SHIFT 3
326#define HDA_SDCTL_ICE_SHIFT 2
327#define HDA_SDCTL_RUN_SHIFT 1
328#define HDA_SDCTL_SRST_SHIFT 0
329
330#define HDA_REG_SD0STS 35 /* 0x83 */
331#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
332#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
333#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
334#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
335#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
336#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
337#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
338#define HDA_RMX_SD0STS 33
339#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
340#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
341#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
342#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
343#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
344#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
345#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
346
347#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
348#define HDA_SDSTS_FIFORDY_SHIFT 5
349#define HDA_SDSTS_DE_SHIFT 4
350#define HDA_SDSTS_FE_SHIFT 3
351#define HDA_SDSTS_BCIS_SHIFT 2
352
353#define HDA_REG_SD0LPIB 36 /* 0x84 */
354#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
355#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
356#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
357#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
358#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
359#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
360#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
361#define HDA_RMX_SD0LPIB 34
362#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
363#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
364#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
365#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
366#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
367#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
368#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
369
370#define HDA_REG_SD0CBL 37 /* 0x88 */
371#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
372#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
373#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
374#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
375#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
376#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
377#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
378#define HDA_RMX_SD0CBL 35
379#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
380#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
381#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
382#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
383#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
384#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
385#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
386
387
388#define HDA_REG_SD0LVI 38 /* 0x8C */
389#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
390#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
391#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
392#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
393#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
394#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
395#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
396#define HDA_RMX_SD0LVI 36
397#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
398#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
399#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
400#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
401#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
402#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
403#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
404
405#define HDA_REG_SD0FIFOW 39 /* 0x8E */
406#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
407#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
408#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
409#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
410#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
411#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
412#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
413#define HDA_RMX_SD0FIFOW 37
414#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
415#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
416#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
417#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
418#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
419#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
420#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
421
422/*
423 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
424 */
425#define HDA_SDFIFOW_8B 0x2
426#define HDA_SDFIFOW_16B 0x3
427#define HDA_SDFIFOW_32B 0x4
428
429#define HDA_REG_SD0FIFOS 40 /* 0x90 */
430#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
431#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
432#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
433#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
434#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
435#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
436#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
437#define HDA_RMX_SD0FIFOS 38
438#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
439#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
440#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
441#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
442#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
443#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
444#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
445
446/*
447 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
448 * formula: size - 1
449 * Other values not listed are not supported.
450 */
451#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
452#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
453#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
454#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
455#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
456#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
457#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
458#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
459#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
460
461#define HDA_REG_SD0FMT 41 /* 0x92 */
462#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
463#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
464#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
465#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
466#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
467#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
468#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
469#define HDA_RMX_SD0FMT 39
470#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
471#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
472#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
473#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
474#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
475#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
476#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
477
478#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
479#define HDA_SDFMT_BASE_RATE_SHIFT 14
480#define HDA_SDFMT_MULT_SHIFT 11
481#define HDA_SDFMT_MULT_MASK 0x7
482#define HDA_SDFMT_DIV_SHIFT 8
483#define HDA_SDFMT_DIV_MASK 0x7
484#define HDA_SDFMT_BITS_SHIFT 4
485#define HDA_SDFMT_BITS_MASK 0x7
486#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
487#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
488#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
489
490#define HDA_REG_SD0BDPL 42 /* 0x98 */
491#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
492#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
493#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
494#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
495#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
496#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
497#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
498#define HDA_RMX_SD0BDPL 40
499#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
500#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
501#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
502#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
503#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
504#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
505#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
506
507#define HDA_REG_SD0BDPU 43 /* 0x9C */
508#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
509#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
510#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
511#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
512#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
513#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
514#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
515#define HDA_RMX_SD0BDPU 41
516#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
517#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
518#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
519#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
520#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
521#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
522#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
523
524#define HDA_CODEC_CAD_SHIFT 28
525/* Encodes the (required) LUN into a codec command. */
526#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
527
528
529
530/*******************************************************************************
531* Structures and Typedefs *
532*******************************************************************************/
533typedef struct HDABDLEDESC
534{
535 uint64_t u64BdleCviAddr;
536 uint32_t u32BdleMaxCvi;
537 uint32_t u32BdleCvi;
538 uint32_t u32BdleCviLen;
539 uint32_t u32BdleCviPos;
540 bool fBdleCviIoc;
541 uint32_t cbUnderFifoW;
542 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
543} HDABDLEDESC, *PHDABDLEDESC;
544
545typedef struct HDASTREAMTRANSFERDESC
546{
547 uint64_t u64BaseDMA;
548 uint32_t u32Ctl;
549 uint32_t *pu32Sts;
550 uint8_t u8Strm;
551 uint32_t *pu32Lpib;
552 uint32_t u32Cbl;
553 uint32_t u32Fifos;
554} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
555
556#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
557typedef struct HDAINPUTSTREAM
558{
559 /** PCM line input stream. */
560 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
561 /** Mixer handle for line input stream. */
562 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
563} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
564
565typedef struct HDAOUTPUTSTREAM
566{
567 /** PCM output stream. */
568 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
569} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
570
571/**
572 * Struct for maintaining a host backend driver.
573 * This driver must be associated to one, and only one,
574 * HDA codec. The HDA controller does the actual multiplexing
575 * of HDA codec data to various host backend drivers then.
576 *
577 * This HDA device uses a timer in order to synchronize all
578 * read/write accesses across all attached LUNs / backends.
579 */
580typedef struct HDADRIVER
581{
582 union
583 {
584 /** Node for storing this driver in our device driver
585 * list of HDASTATE. */
586 RTLISTNODE Node;
587 struct
588 {
589 R3PTRTYPE(void *) dummy1;
590 R3PTRTYPE(void *) dummy2;
591 } dummy;
592 };
593
594 /** Pointer to HDA controller (state). */
595 R3PTRTYPE(PHDASTATE) pHDAState;
596 /** Driver flags. */
597 PDMAUDIODRVFLAGS Flags;
598 uint8_t u32Padding0[3];
599 /** LUN to which this driver has been assigned. */
600 uint8_t uLUN;
601 /** Audio connector interface to the underlying
602 * host backend. */
603 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
604 /** Stream for line input. */
605 HDAINPUTSTREAM LineIn;
606 /** Stream for mic input. */
607 HDAINPUTSTREAM MicIn;
608 /** Stream for output. */
609 HDAOUTPUTSTREAM Out;
610 /** Number of samples to play (output), needed
611 * for the timer routine. */
612 uint32_t cSamplesLive;
613} HDADRIVER, *PHDADRIVER;
614#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
615
616/**
617 * ICH Intel HD Audio Controller state.
618 */
619typedef struct HDASTATE
620{
621 /** The PCI device structure. */
622 PCIDevice PciDev;
623 /** R3 Pointer to the device instance. */
624 PPDMDEVINSR3 pDevInsR3;
625 /** R0 Pointer to the device instance. */
626 PPDMDEVINSR0 pDevInsR0;
627 /** R0 Pointer to the device instance. */
628 PPDMDEVINSRC pDevInsRC;
629
630 uint32_t u32Padding;
631
632 /** Pointer to the attached audio driver. */
633 R3PTRTYPE(PPDMIBASE) pDrvBase;
634 /** The base interface for LUN\#0. */
635 PDMIBASE IBase;
636 RTGCPHYS MMIOBaseAddr;
637 uint32_t au32Regs[HDA_NREGS];
638 HDABDLEDESC StInBdle;
639 HDABDLEDESC StOutBdle;
640 HDABDLEDESC StMicBdle;
641 uint64_t u64CORBBase;
642 uint64_t u64RIRBBase;
643 uint64_t u64DPBase;
644 /** Pointer to CORB buffer. */
645 R3PTRTYPE(uint32_t *) pu32CorbBuf;
646 /** Size in bytes of CORB buffer. */
647 uint32_t cbCorbBuf;
648 uint32_t u32Padding2;
649 /** Pointer to RIRB buffer. */
650 R3PTRTYPE(uint64_t *) pu64RirbBuf;
651 /** Size in bytes of RIRB buffer. */
652 uint32_t cbRirbBuf;
653 /** Indicates if HDA is in reset. */
654 bool fInReset;
655 /** Interrupt on completion */
656 bool fCviIoc;
657 /** Flag whether the R0 part is enabled. */
658 bool fR0Enabled;
659 /** Flag whether the RC part is enabled. */
660 bool fRCEnabled;
661#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
662 /** The emulation timer for handling the attached
663 * LUN drivers. */
664 PTMTIMERR3 pTimer;
665 /** Timer ticks for handling the LUN drivers. */
666 uint64_t uTicks;
667# ifdef VBOX_WITH_STATISTICS
668 STAMPROFILE StatTimer;
669 STAMCOUNTER StatBytesRead;
670 STAMCOUNTER StatBytesWritten;
671# endif
672 /** Pointer to HDA codec to use. */
673 R3PTRTYPE(PHDACODEC) pCodec;
674 union
675 {
676 /** List of associated LUN drivers. */
677 RTLISTANCHOR lstDrv;
678 struct
679 {
680 R3PTRTYPE(void *) dummy1;
681 R3PTRTYPE(void *) dummy2;
682 } dummy;
683 };
684 /** The device' software mixer. */
685 R3PTRTYPE(PAUDIOMIXER) pMixer;
686 /** Audio mixer sink for line input. */
687 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
688 /** Audio mixer sink for microphone input. */
689 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
690#else /* !VBOX_WITH_PDM_AUDIO_DRIVER */
691 /** The HDA codec to use. */
692 R3PTRTYPE(PHDACODEC) pCodec;
693#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
694 uint64_t u64BaseTS;
695 /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
696 uint8_t u8Counter;
697#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
698 uint8_t au8Padding[7];
699#else
700 uint8_t au8Padding[7];
701#endif
702} HDASTATE;
703/** Pointer to the ICH Intel HD Audio Controller state. */
704typedef HDASTATE *PHDASTATE;
705
706#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
707 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
708#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
709 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
710
711
712/*******************************************************************************
713* Internal Functions *
714*******************************************************************************/
715#ifndef VBOX_DEVICE_STRUCT_TESTCASE
716static FNPDMDEVRESET hdaReset;
717
718static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
719static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
720static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
721static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
722static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
723static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
724static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
725static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
726static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
727static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
728static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
729static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
730static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
731static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
732static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
733static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
734static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
735
736static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
737static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
738static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
739static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
740static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
741static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
742static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
743static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
744static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
745static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
746static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
747static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
748static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
749static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
750static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
751static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
752
753#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
754static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
755static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail);
756#else
757static int hdaTransfer(PHDACODEC pCodec, ENMSOUNDSOURCE enmSource, int cbAvail);
758#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
759
760#ifdef IN_RING3
761DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
762 PHDASTREAMTRANSFERDESC pStreamDesc);
763static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
764#ifdef LOG_ENABLED
765static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
766#endif
767#endif
768
769
770/*******************************************************************************
771* Global Variables *
772*******************************************************************************/
773
774/* see 302349 p 6.2*/
775static const struct HDAREGDESC
776{
777 /** Register offset in the register space. */
778 uint32_t offset;
779 /** Size in bytes. Registers of size > 4 are in fact tables. */
780 uint32_t size;
781 /** Readable bits. */
782 uint32_t readable;
783 /** Writable bits. */
784 uint32_t writable;
785 /** Read callback. */
786 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
787 /** Write callback. */
788 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
789 /** Index into the register storage array. */
790 uint32_t mem_idx;
791 /** Abbreviated name. */
792 const char *abbrev;
793} g_aHdaRegMap[HDA_NREGS] =
794
795/* Turn a short register name into an memory index and a stringized name. */
796#define RA(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
797/* Same as above for an input stream ('I' prefixed). */
798#define IA(abbrev) HDA_MEM_IND_NAME(abbrev), "I"#abbrev
799/* Same as above for an output stream ('O' prefixed). */
800#define OA(abbrev) HDA_MEM_IND_NAME(abbrev), "O"#abbrev
801/* Same as above for a register *not* stored in memory. */
802#define UA(abbrev) 0, #abbrev
803
804{
805 /* offset size read mask write mask read callback write callback abbrev */
806 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- */
807 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(GCAP) }, /* Global Capabilities */
808 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMIN) }, /* Minor Version */
809 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMAJ) }, /* Major Version */
810 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTPAY) }, /* Output Payload Capabilities */
811 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INPAY) }, /* Input Payload Capabilities */
812 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , RA(GCTL) }, /* Global Control */
813 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , RA(WAKEEN) }, /* Wake Enable */
814 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , RA(STATESTS) }, /* State Change Status */
815 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , RA(GSTS) }, /* Global Status */
816 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTSTRMPAY)}, /* Output Stream Payload Capability */
817 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INSTRMPAY) }, /* Input Stream Payload Capability */
818 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(INTCTL) }, /* Interrupt Control */
819 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , RA(INTSTS) }, /* Interrupt Status */
820 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , UA(WALCLK) }, /* Wall Clock Counter */
821 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
822 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(SSYNC) }, /* Stream Synchronization */
823 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(CORBLBASE) }, /* CORB Lower Base Address */
824 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(CORBUBASE) }, /* CORB Upper Base Address */
825 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , RA(CORBWP) }, /* CORB Write Pointer */
826 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , RA(CORBRP) }, /* CORB Read Pointer */
827 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , RA(CORBCTL) }, /* CORB Control */
828 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , RA(CORBSTS) }, /* CORB Status */
829 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(CORBSIZE) }, /* CORB Size */
830 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBLBASE) }, /* RIRB Lower Base Address */
831 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBUBASE) }, /* RIRB Upper Base Address */
832 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , RA(RIRBWP) }, /* RIRB Write Pointer */
833 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , RA(RINTCNT) }, /* Response Interrupt Count */
834 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , RA(RIRBCTL) }, /* RIRB Control */
835 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , RA(RIRBSTS) }, /* RIRB Status */
836 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(RIRBSIZE) }, /* RIRB Size */
837 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , RA(IC) }, /* Immediate Command */
838 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , RA(IR) }, /* Immediate Response */
839 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , RA(IRS) }, /* Immediate Command Status */
840 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , RA(DPLBASE) }, /* MA Position Lower Base */
841 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(DPUBASE) }, /* DMA Position Upper Base */
842
843 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD0CTL) }, /* Input Stream Descriptor 0 (ICD0) Control */
844 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD0STS) }, /* ISD0 Status */
845 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0LPIB) }, /* ISD0 Link Position In Buffer */
846 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0CBL) }, /* ISD0 Cyclic Buffer Length */
847 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD0LVI) }, /* ISD0 Last Valid Index */
848 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD0FIFOW) }, /* ISD0 FIFO Watermark */
849 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD0FIFOS) }, /* ISD0 FIFO Size */
850 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD0FMT) }, /* ISD0 Format */
851 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD0BDPL) }, /* ISD0 Buffer Descriptor List Pointer-Lower Base Address */
852 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD0BDPU) }, /* ISD0 Buffer Descriptor List Pointer-Upper Base Address */
853
854 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD1CTL) }, /* Input Stream Descriptor 1 (ISD1) Control */
855 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD1STS) }, /* ISD1 Status */
856 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1LPIB) }, /* ISD1 Link Position In Buffer */
857 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1CBL) }, /* ISD1 Cyclic Buffer Length */
858 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD1LVI) }, /* ISD1 Last Valid Index */
859 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD1FIFOW) }, /* ISD1 FIFO Watermark */
860 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD1FIFOS) }, /* ISD1 FIFO Size */
861 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD1FMT) }, /* ISD1 Format */
862 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD1BDPL) }, /* ISD1 Buffer Descriptor List Pointer-Lower Base Address */
863 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD1BDPU) }, /* ISD1 Buffer Descriptor List Pointer-Upper Base Address */
864
865 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD2CTL) }, /* Input Stream Descriptor 2 (ISD2) Control */
866 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD2STS) }, /* ISD2 Status */
867 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2LPIB) }, /* ISD2 Link Position In Buffer */
868 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2CBL) }, /* ISD2 Cyclic Buffer Length */
869 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD2LVI) }, /* ISD2 Last Valid Index */
870 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD2FIFOW) }, /* ISD2 FIFO Watermark */
871 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD2FIFOS) }, /* ISD2 FIFO Size */
872 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD2FMT) }, /* ISD2 Format */
873 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD2BDPL) }, /* ISD2 Buffer Descriptor List Pointer-Lower Base Address */
874 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD2BDPU) }, /* ISD2 Buffer Descriptor List Pointer-Upper Base Address */
875
876 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD3CTL) }, /* Input Stream Descriptor 3 (ISD3) Control */
877 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD3STS) }, /* ISD3 Status */
878 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3LPIB) }, /* ISD3 Link Position In Buffer */
879 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3CBL) }, /* ISD3 Cyclic Buffer Length */
880 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD3LVI) }, /* ISD3 Last Valid Index */
881 { 0x000EE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD3FIFOW) }, /* ISD3 FIFO Watermark */
882 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD3FIFOS) }, /* ISD3 FIFO Size */
883 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD3FMT) }, /* ISD3 Format */
884 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD3BDPL) }, /* ISD3 Buffer Descriptor List Pointer-Lower Base Address */
885 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD3BDPU) }, /* ISD3 Buffer Descriptor List Pointer-Upper Base Address */
886
887 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD4CTL) }, /* Output Stream Descriptor 4 (OSD4) Control */
888 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD4STS) }, /* OSD4 Status */
889 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4LPIB) }, /* OSD4 Link Position In Buffer */
890 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4CBL) }, /* OSD4 Cyclic Buffer Length */
891 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD4LVI) }, /* OSD4 Last Valid Index */
892 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD4FIFOW) }, /* OSD4 FIFO Watermark */
893 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD4FIFOS) }, /* OSD4 FIFO Size */
894 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD4FMT) }, /* OSD4 Format */
895 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD4BDPL) }, /* OSD4 Buffer Descriptor List Pointer-Lower Base Address */
896 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD4BDPU) }, /* OSD4 Buffer Descriptor List Pointer-Upper Base Address */
897
898 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD5CTL) }, /* Output Stream Descriptor 5 (OSD5) Control */
899 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD5STS) }, /* OSD5 Status */
900 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5LPIB) }, /* OSD5 Link Position In Buffer */
901 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5CBL) }, /* OSD5 Cyclic Buffer Length */
902 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD5LVI) }, /* OSD5 Last Valid Index */
903 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD5FIFOW) }, /* OSD5 FIFO Watermark */
904 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD5FIFOS) }, /* OSD5 FIFO Size */
905 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD5FMT) }, /* OSD5 Format */
906 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD5BDPL) }, /* OSD5 Buffer Descriptor List Pointer-Lower Base Address */
907 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD5BDPU) }, /* OSD5 Buffer Descriptor List Pointer-Upper Base Address */
908
909 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD6CTL) }, /* Output Stream Descriptor 6 (OSD6) Control */
910 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD6STS) }, /* OSD6 Status */
911 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6LPIB) }, /* OSD6 Link Position In Buffer */
912 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6CBL) }, /* OSD6 Cyclic Buffer Length */
913 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD6LVI) }, /* OSD6 Last Valid Index */
914 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD6FIFOW) }, /* OSD6 FIFO Watermark */
915 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD6FIFOS) }, /* OSD6 FIFO Size */
916 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD6FMT) }, /* OSD6 Format */
917 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD6BDPL) }, /* OSD6 Buffer Descriptor List Pointer-Lower Base Address */
918 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD6BDPU) }, /* OSD6 Buffer Descriptor List Pointer-Upper Base Address */
919
920 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD7CTL) }, /* Output Stream Descriptor 7 (OSD7) Control */
921 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD7STS) }, /* OSD7 Status */
922 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7LPIB) }, /* OSD7 Link Position In Buffer */
923 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7CBL) }, /* OSD7 Cyclic Buffer Length */
924 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD7LVI) }, /* OSD7 Last Valid Index */
925 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD7FIFOW) }, /* OSD7 FIFO Watermark */
926 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD7FIFOS) }, /* OSD7 FIFO Size */
927 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD7FMT) }, /* OSD7 Format */
928 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD7BDPL) }, /* OSD7 Buffer Descriptor List Pointer-Lower Base Address */
929 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD7BDPU) }, /* OSD7 Buffer Descriptor List Pointer-Upper Base Address */
930};
931
932/**
933 * HDA register aliases (HDA spec 3.3.45).
934 * @remarks Sorted by offReg.
935 */
936static const struct
937{
938 /** The alias register offset. */
939 uint32_t offReg;
940 /** The register index. */
941 int idxAlias;
942} g_aHdaRegAliases[] =
943{
944 { 0x2084, HDA_REG_SD0LPIB },
945 { 0x20a4, HDA_REG_SD1LPIB },
946 { 0x20c4, HDA_REG_SD2LPIB },
947 { 0x20e4, HDA_REG_SD3LPIB },
948 { 0x2104, HDA_REG_SD4LPIB },
949 { 0x2124, HDA_REG_SD5LPIB },
950 { 0x2144, HDA_REG_SD6LPIB },
951 { 0x2164, HDA_REG_SD7LPIB },
952};
953
954#ifdef IN_RING3
955/** HDABDLEDESC field descriptors the v3+ saved state. */
956static SSMFIELD const g_aHdaBDLEDescFields[] =
957{
958 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
959 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
960 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
961 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
962 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
963 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
964 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
965 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
966 SSMFIELD_ENTRY_TERM()
967};
968
969/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
970static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
971{
972 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
973 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
974 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
975 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
976 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
977 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
978 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
979 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
980 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
981 SSMFIELD_ENTRY_TERM()
982};
983#endif
984
985/**
986 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
987 */
988static uint32_t const g_afMasks[5] =
989{
990 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
991};
992
993#ifdef IN_RING3
994DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
995{
996 if (pThis->u64DPBase & DPBASE_ENABLED)
997 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
998 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
999 pStreamDesc->pu32Lpib, sizeof(uint32_t));
1000}
1001#endif
1002
1003DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
1004{
1005#if 0
1006 switch(HDA_STREAM_REG(pThis, FIFOW, pStreamDesc->u8Strm))
1007 {
1008 case HDA_SDFIFOW_8B: return 8;
1009 case HDA_SDFIFOW_16B: return 16;
1010 case HDA_SDFIFOW_32B: return 32;
1011 default:
1012 AssertMsgFailed(("unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
1013 }
1014#endif
1015 return 0;
1016}
1017
1018static int hdaProcessInterrupt(PHDASTATE pThis)
1019{
1020#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1021 ( INTCTL_SX((pThis), num) \
1022 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1023 bool fIrq = false;
1024 if ( HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1025 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1026 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1027 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1028 fIrq = true;
1029
1030 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1031 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1032 fIrq = true;
1033
1034 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1035 {
1036 LogFunc(("irq %s\n", fIrq ? "asserted" : "deasserted"));
1037 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1038 }
1039 return VINF_SUCCESS;
1040}
1041
1042/**
1043 * Looks up a register at the exact offset given by @a offReg.
1044 *
1045 * @returns Register index on success, -1 if not found.
1046 * @param pThis The HDA device state.
1047 * @param offReg The register offset.
1048 */
1049static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1050{
1051 /*
1052 * Aliases.
1053 */
1054 if (offReg >= g_aHdaRegAliases[0].offReg)
1055 {
1056 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1057 if (offReg == g_aHdaRegAliases[i].offReg)
1058 return g_aHdaRegAliases[i].idxAlias;
1059 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1060 return -1;
1061 }
1062
1063 /*
1064 * Binary search the
1065 */
1066 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1067 int idxLow = 0;
1068 for (;;)
1069 {
1070 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1071 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1072 {
1073 if (idxLow == idxMiddle)
1074 break;
1075 idxEnd = idxMiddle;
1076 }
1077 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1078 {
1079 idxLow = idxMiddle + 1;
1080 if (idxLow >= idxEnd)
1081 break;
1082 }
1083 else
1084 return idxMiddle;
1085 }
1086
1087#ifdef RT_STRICT
1088 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1089 Assert(g_aHdaRegMap[i].offset != offReg);
1090#endif
1091 return -1;
1092}
1093
1094/**
1095 * Looks up a register covering the offset given by @a offReg.
1096 *
1097 * @returns Register index on success, -1 if not found.
1098 * @param pThis The HDA device state.
1099 * @param offReg The register offset.
1100 */
1101static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1102{
1103 /*
1104 * Aliases.
1105 */
1106 if (offReg >= g_aHdaRegAliases[0].offReg)
1107 {
1108 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1109 {
1110 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1111 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1112 return g_aHdaRegAliases[i].idxAlias;
1113 }
1114 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1115 return -1;
1116 }
1117
1118 /*
1119 * Binary search the
1120 */
1121 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1122 int idxLow = 0;
1123 for (;;)
1124 {
1125 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1126 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1127 {
1128 if (idxLow == idxMiddle)
1129 break;
1130 idxEnd = idxMiddle;
1131 }
1132 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1133 {
1134 idxLow = idxMiddle + 1;
1135 if (idxLow >= idxEnd)
1136 break;
1137 }
1138 else
1139 return idxMiddle;
1140 }
1141
1142#ifdef RT_STRICT
1143 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1144 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1145#endif
1146 return -1;
1147}
1148
1149#ifdef IN_RING3
1150static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1151{
1152 int rc = VINF_SUCCESS;
1153 if (fLocal)
1154 {
1155 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1156 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1157 if (RT_FAILURE(rc))
1158 AssertRCReturn(rc, rc);
1159#ifdef DEBUG_CMD_BUFFER
1160 uint8_t i = 0;
1161 do
1162 {
1163 LogFunc(("corb%02x: ", i));
1164 uint8_t j = 0;
1165 do
1166 {
1167 const char *prefix;
1168 if ((i + j) == HDA_REG(pThis, CORBRP);
1169 prefix = "[R]";
1170 else if ((i + j) == HDA_REG(pThis, CORBWP);
1171 prefix = "[W]";
1172 else
1173 prefix = " "; /* three spaces */
1174 LogFunc(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
1175 j++;
1176 } while (j < 8);
1177 LogFunc(("\n"));
1178 i += 8;
1179 } while(i != 0);
1180#endif
1181 }
1182 else
1183 {
1184 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1185 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1186 if (RT_FAILURE(rc))
1187 AssertRCReturn(rc, rc);
1188#ifdef DEBUG_CMD_BUFFER
1189 uint8_t i = 0;
1190 do {
1191 LogFunc(("rirb%02x: ", i));
1192 uint8_t j = 0;
1193 do {
1194 const char *prefix;
1195 if ((i + j) == HDA_REG(pThis, RIRBWP))
1196 prefix = "[W]";
1197 else
1198 prefix = " ";
1199 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1200 } while (++j < 8);
1201 LogFunc(("\n"));
1202 i += 8;
1203 } while (i != 0);
1204#endif
1205 }
1206 return rc;
1207}
1208
1209static int hdaCORBCmdProcess(PHDASTATE pThis)
1210{
1211 int rc;
1212 uint8_t corbRp;
1213 uint8_t corbWp;
1214 uint8_t rirbWp;
1215
1216 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1217
1218 rc = hdaCmdSync(pThis, true);
1219 if (RT_FAILURE(rc))
1220 AssertRCReturn(rc, rc);
1221 corbRp = HDA_REG(pThis, CORBRP);
1222 corbWp = HDA_REG(pThis, CORBWP);
1223 rirbWp = HDA_REG(pThis, RIRBWP);
1224 Assert((corbWp != corbRp));
1225 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1226 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1227 while (corbRp != corbWp)
1228 {
1229 uint32_t cmd;
1230 uint64_t resp;
1231 pfn = NULL;
1232 corbRp++;
1233 cmd = pThis->pu32CorbBuf[corbRp];
1234
1235 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1236 HDA_CODEC_CMD(cmd, 0 /* Codec index */),
1237 &pfn);
1238 if (RT_SUCCESS(rc))
1239 {
1240 rc = pfn(pThis->pCodec,
1241 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1242 }
1243
1244 if (RT_FAILURE(rc))
1245 AssertRCReturn(rc, rc);
1246 Assert(pfn);
1247 (rirbWp)++;
1248
1249 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1250 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1251 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1252 {
1253 LogFunc(("unexpected unsolicited response.\n"));
1254 HDA_REG(pThis, CORBRP) = corbRp;
1255 return rc;
1256 }
1257 pThis->pu64RirbBuf[rirbWp] = resp;
1258 pThis->u8Counter++;
1259 if (pThis->u8Counter == RINTCNT_N(pThis))
1260 break;
1261 }
1262 HDA_REG(pThis, CORBRP) = corbRp;
1263 HDA_REG(pThis, RIRBWP) = rirbWp;
1264 rc = hdaCmdSync(pThis, false);
1265 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1266 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1267 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1268 {
1269 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1270 pThis->u8Counter = 0;
1271 rc = hdaProcessInterrupt(pThis);
1272 }
1273 if (RT_FAILURE(rc))
1274 AssertRCReturn(rc, rc);
1275 return rc;
1276}
1277#endif
1278
1279static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
1280{
1281 LogFunc(("reset of stream (%d) started\n", u8Strm));
1282 Assert(( pThis
1283 && pBdle
1284 && pStreamDesc
1285 && u8Strm <= 7));
1286 RT_BZERO(pBdle, sizeof(HDABDLEDESC));
1287 *pStreamDesc->pu32Lpib = 0;
1288 *pStreamDesc->pu32Sts = 0;
1289 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1290 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
1291 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1292
1293 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1294 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1295 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
1296 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1297 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1298 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1299 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1300 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1301 LogFunc(("reset of stream (%d) finished\n", u8Strm));
1302}
1303
1304/* Register access handlers. */
1305
1306static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1307{
1308 *pu32Value = 0;
1309 return VINF_SUCCESS;
1310}
1311
1312static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1313{
1314 return VINF_SUCCESS;
1315}
1316
1317/* U8 */
1318static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1319{
1320 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1321 return hdaRegReadU32(pThis, iReg, pu32Value);
1322}
1323
1324static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1325{
1326 Assert((u32Value & 0xffffff00) == 0);
1327 return hdaRegWriteU32(pThis, iReg, u32Value);
1328}
1329
1330/* U16 */
1331static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1332{
1333 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1334 return hdaRegReadU32(pThis, iReg, pu32Value);
1335}
1336
1337static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1338{
1339 Assert((u32Value & 0xffff0000) == 0);
1340 return hdaRegWriteU32(pThis, iReg, u32Value);
1341}
1342
1343/* U24 */
1344static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1345{
1346 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1347 return hdaRegReadU32(pThis, iReg, pu32Value);
1348}
1349
1350static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1351{
1352 Assert((u32Value & 0xff000000) == 0);
1353 return hdaRegWriteU32(pThis, iReg, u32Value);
1354}
1355
1356/* U32 */
1357static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1358{
1359 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1360
1361 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1362 return VINF_SUCCESS;
1363}
1364
1365static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1366{
1367 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1368
1369 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1370 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1371 return VINF_SUCCESS;
1372}
1373
1374static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1375{
1376 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1377 {
1378 /* exit reset state */
1379 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1380 pThis->fInReset = false;
1381 }
1382 else
1383 {
1384#ifdef IN_RING3
1385 /* enter reset state*/
1386 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1387 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1388 {
1389 LogFunc(("HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1390 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1391 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1392 }
1393 hdaReset(pThis->CTX_SUFF(pDevIns));
1394 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1395 pThis->fInReset = true;
1396#else
1397 return VINF_IOM_R3_MMIO_WRITE;
1398#endif
1399 }
1400 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1401 {
1402 /* Flush: GSTS:1 set, see 6.2.6*/
1403 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1404 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1405 }
1406 return VINF_SUCCESS;
1407}
1408
1409static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1410{
1411 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1412
1413 uint32_t v = pThis->au32Regs[iRegMem];
1414 uint32_t nv = u32Value & HDA_STATES_SCSF;
1415 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1416 return VINF_SUCCESS;
1417}
1418
1419static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1420{
1421 uint32_t v = 0;
1422 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1423 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1424 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1425 || HDA_REG(pThis, STATESTS))
1426 v |= RT_BIT(30);
1427#define HDA_IS_STREAM_EVENT(pThis, stream) \
1428 ( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1429 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1430 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1431#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
1432 MARK_STREAM(pThis, 0, v);
1433 MARK_STREAM(pThis, 1, v);
1434 MARK_STREAM(pThis, 2, v);
1435 MARK_STREAM(pThis, 3, v);
1436 MARK_STREAM(pThis, 4, v);
1437 MARK_STREAM(pThis, 5, v);
1438 MARK_STREAM(pThis, 6, v);
1439 MARK_STREAM(pThis, 7, v);
1440 v |= v ? RT_BIT(31) : 0;
1441 *pu32Value = v;
1442 return VINF_SUCCESS;
1443}
1444
1445static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1446{
1447 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1448 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1449 - pThis->u64BaseTS, 24, 1000);
1450 return VINF_SUCCESS;
1451}
1452
1453static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1454{
1455 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1456 HDA_REG(pThis, CORBRP) = 0;
1457#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1458 else
1459 return hdaRegWriteU8(pThis, iReg, u32Value);
1460#endif
1461 return VINF_SUCCESS;
1462}
1463
1464static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1465{
1466#ifdef IN_RING3
1467 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1468 AssertRC(rc);
1469 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1470 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1471 return hdaCORBCmdProcess(pThis);
1472 return rc;
1473#else
1474 return VINF_IOM_R3_MMIO_WRITE;
1475#endif
1476}
1477
1478static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1479{
1480 uint32_t v = HDA_REG(pThis, CORBSTS);
1481 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1482 return VINF_SUCCESS;
1483}
1484
1485static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1486{
1487#ifdef IN_RING3
1488 int rc;
1489 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1490 if (RT_FAILURE(rc))
1491 AssertRCReturn(rc, rc);
1492 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1493 return VINF_SUCCESS;
1494 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1495 return VINF_SUCCESS;
1496 rc = hdaCORBCmdProcess(pThis);
1497 return rc;
1498#else
1499 return VINF_IOM_R3_MMIO_WRITE;
1500#endif
1501}
1502
1503static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1504{
1505 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1506 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1507 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1508 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1509
1510 if (fInReset)
1511 {
1512 /*
1513 * Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1514 * from reset
1515 */
1516 Assert((!fReset));
1517 LogFunc(("guest initiated exit of stream reset.\n"));
1518 }
1519 else if (fReset)
1520 {
1521#ifdef IN_RING3
1522 /*
1523 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1524 */
1525 uint8_t u8Strm = 0;
1526 PHDABDLEDESC pBdle = NULL;
1527 HDASTREAMTRANSFERDESC StreamDesc;
1528 Assert((!fInRun && !fRun));
1529 switch (iReg)
1530 {
1531 case HDA_REG_SD0CTL:
1532 u8Strm = 0;
1533 pBdle = &pThis->StInBdle;
1534 break;
1535#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1536# ifdef VBOX_WITH_HDA_MIC_IN
1537 case HDA_REG_SD2CTL:
1538 u8Strm = 2;
1539 pBdle = &pThis->StMicBdle;
1540 break;
1541# endif
1542#endif
1543 case HDA_REG_SD4CTL:
1544 u8Strm = 4;
1545 pBdle = &pThis->StOutBdle;
1546 break;
1547 default:
1548 LogFunc(("changing SRST bit on non-attached stream\n"));
1549 return hdaRegWriteU24(pThis, iReg, u32Value);
1550 }
1551 LogFunc(("guest initiated enter to stream reset.\n"));
1552 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1553 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
1554#else
1555 return VINF_IOM_R3_MMIO_WRITE;
1556#endif
1557 }
1558 else
1559 {
1560#ifdef IN_RING3
1561 /* we enter here to change DMA states only */
1562 if ( (fInRun && !fRun)
1563 || (fRun && !fInRun))
1564 {
1565 Assert((!fReset && !fInReset));
1566
1567# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1568 PHDADRIVER pDrv;
1569# endif
1570 switch (iReg)
1571 {
1572 case HDA_REG_SD0CTL:
1573# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1574 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1575 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1576 pDrv->LineIn.pStrmIn, fRun);
1577# else
1578 AUD_set_active_in(pThis->pCodec->SwVoiceIn, fRun);
1579# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1580 break;
1581# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1582# ifdef VBOX_WITH_HDA_MIC_IN
1583 case HDA_REG_SD2CTL:
1584 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1585 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1586 pDrv->MicIn.pStrmIn, fRun);
1587# endif
1588# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1589 break;
1590 case HDA_REG_SD4CTL:
1591# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1592 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1593 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1594 pDrv->Out.pStrmOut, fRun);
1595# else
1596 AUD_set_active_out(pThis->pCodec->SwVoiceOut, fRun);
1597# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1598 break;
1599 default:
1600 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1601 break;
1602 }
1603 }
1604#else /* !IN_RING3 */
1605 return VINF_IOM_R3_MMIO_WRITE;
1606#endif /* IN_RING3 */
1607 }
1608
1609 return hdaRegWriteU24(pThis, iReg, u32Value);
1610}
1611
1612static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1613{
1614 uint32_t v = HDA_REG_IND(pThis, iReg);
1615 v &= ~(u32Value & v);
1616 HDA_REG_IND(pThis, iReg) = v;
1617 hdaProcessInterrupt(pThis);
1618 return VINF_SUCCESS;
1619}
1620
1621static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1622{
1623 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1624 if (RT_FAILURE(rc))
1625 AssertRCReturn(rc, VINF_SUCCESS);
1626 return rc;
1627}
1628
1629static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1630{
1631 switch (u32Value)
1632 {
1633 case HDA_SDFIFOW_8B:
1634 case HDA_SDFIFOW_16B:
1635 case HDA_SDFIFOW_32B:
1636 return hdaRegWriteU16(pThis, iReg, u32Value);
1637 default:
1638 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1639 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1640 }
1641 return VINF_SUCCESS;
1642}
1643
1644/**
1645 * @note This method could be called for changing value on Output Streams
1646 * only (ICH6 datasheet 18.2.39)
1647 */
1648static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1649{
1650 switch (iReg)
1651 {
1652 /* SDInFIFOS is RO, n=0-3 */
1653 case HDA_REG_SD0FIFOS:
1654 case HDA_REG_SD1FIFOS:
1655 case HDA_REG_SD2FIFOS:
1656 case HDA_REG_SD3FIFOS:
1657 LogFunc(("Guest tries change value of FIFO size of input stream\n"));
1658 break;
1659 case HDA_REG_SD4FIFOS:
1660 case HDA_REG_SD5FIFOS:
1661 case HDA_REG_SD6FIFOS:
1662 case HDA_REG_SD7FIFOS:
1663 switch(u32Value)
1664 {
1665 case HDA_SDONFIFO_16B:
1666 case HDA_SDONFIFO_32B:
1667 case HDA_SDONFIFO_64B:
1668 case HDA_SDONFIFO_128B:
1669 case HDA_SDONFIFO_192B:
1670 return hdaRegWriteU16(pThis, iReg, u32Value);
1671
1672 case HDA_SDONFIFO_256B:
1673 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1674 default:
1675 return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);
1676 }
1677 break;
1678 default:
1679 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
1680 }
1681
1682 return VINF_SUCCESS;
1683}
1684
1685#ifdef IN_RING3
1686#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1687static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
1688#else
1689static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pCfg)
1690#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1691{
1692 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1693
1694# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1695
1696 int rc = VINF_SUCCESS;
1697
1698 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1699 uint32_t u32HzMult = 1;
1700 uint32_t u32HzDiv = 1;
1701
1702 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
1703 {
1704 case 0: u32HzMult = 1; break;
1705 case 1: u32HzMult = 2; break;
1706 case 2: u32HzMult = 3; break;
1707 case 3: u32HzMult = 4; break;
1708 default:
1709 LogFunc(("Unsupported multiplier %x\n",
1710 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
1711 rc = VERR_NOT_SUPPORTED;
1712 break;
1713 }
1714 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
1715 {
1716 case 0: u32HzDiv = 1; break;
1717 case 1: u32HzDiv = 2; break;
1718 case 2: u32HzDiv = 3; break;
1719 case 3: u32HzDiv = 4; break;
1720 case 4: u32HzDiv = 5; break;
1721 case 5: u32HzDiv = 6; break;
1722 case 6: u32HzDiv = 7; break;
1723 case 7: u32HzDiv = 8; break;
1724 default:
1725 LogFunc(("Unsupported divisor %x\n",
1726 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
1727 rc = VERR_NOT_SUPPORTED;
1728 break;
1729 }
1730
1731#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1732 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1733#else
1734 audfmt_e enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1735#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1736
1737 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
1738 {
1739 case 0:
1740 LogFunc(("%s requested 8-bit\n", __FUNCTION__));
1741#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1742 enmFmt = AUD_FMT_S8;
1743#else
1744 enmFmt = AUD_FMT_S8;
1745#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1746 break;
1747 case 1:
1748 LogFunc(("%s requested 16-bit\n", __FUNCTION__));
1749#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1750 enmFmt = AUD_FMT_S16;
1751#else
1752 enmFmt = AUD_FMT_S16;
1753#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1754 break;
1755 case 2:
1756 LogFunc(("%s requested 20-bit\n", __FUNCTION__));
1757 break;
1758 case 3:
1759 LogFunc(("%s requested 24-bit\n", __FUNCTION__));
1760 break;
1761 case 4:
1762 LogFunc(("%s requested 32-bit\n", __FUNCTION__));
1763#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1764 enmFmt = AUD_FMT_S32;
1765#else
1766 enmFmt = AUD_FMT_S32;
1767#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1768 break;
1769 default:
1770 AssertMsgFailed(("Unsupported bits shift %x\n",
1771 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
1772 rc = VERR_NOT_SUPPORTED;
1773 break;
1774 }
1775
1776 if (RT_SUCCESS(rc))
1777 {
1778#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1779 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
1780 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
1781 pCfg->enmFormat = enmFmt;
1782 pCfg->enmEndianness = PDMAUDIOHOSTENDIANESS;
1783#else
1784 pCfg->nchannels = (u32SdFmt & 0xf) + 1;
1785 pCfg->fmt = enmFmt;
1786 pCfg->endianness = 0;
1787#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1788 }
1789
1790# undef EXTRACT_VALUE
1791
1792 return rc;
1793}
1794#endif
1795
1796static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1797{
1798#ifdef IN_RING3
1799# ifdef VBOX_WITH_HDA_CODEC_EMU
1800 /* No reason to reopen voice with same settings. */
1801 if (u32Value == HDA_REG_IND(pThis, iReg))
1802 return VINF_SUCCESS;
1803
1804 PDMAUDIOSTREAMCFG as;
1805 int rc = hdaSdFmtToAudSettings(u32Value, &as);
1806 if (RT_FAILURE(rc))
1807 return rc;
1808
1809 PHDADRIVER pDrv;
1810 switch (iReg)
1811 {
1812 case HDA_REG_SD0FMT:
1813 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1814 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &as);
1815 break;
1816#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1817# ifdef VBOX_WITH_HDA_MIC_IN
1818 case HDA_REG_SD2FMT:
1819 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1820 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &as);
1821 break;
1822# endif
1823#endif
1824 default:
1825 LogFunc(("Warning: Attempt to change format on register %d\n", iReg));
1826 break;
1827 }
1828
1829 /** @todo r=andy rc gets lost; needs fixing. */
1830 return hdaRegWriteU16(pThis, iReg, u32Value);
1831# else
1832 return hdaRegWriteU16(pThis, iReg, u32Value);
1833# endif
1834#else
1835 return VINF_IOM_R3_MMIO_WRITE;
1836#endif
1837}
1838
1839static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1840{
1841 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1842 if (RT_FAILURE(rc))
1843 AssertRCReturn(rc, VINF_SUCCESS);
1844 return rc;
1845}
1846
1847static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1848{
1849 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1850 if (RT_FAILURE(rc))
1851 AssertRCReturn(rc, VINF_SUCCESS);
1852 return rc;
1853}
1854
1855static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1856{
1857 int rc = VINF_SUCCESS;
1858 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1859 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1860 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1861 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1862
1863 rc = hdaRegReadU32(pThis, iReg, pu32Value);
1864 return rc;
1865}
1866
1867static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1868{
1869 int rc = VINF_SUCCESS;
1870
1871 /*
1872 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1873 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1874 */
1875 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1876 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
1877 {
1878#ifdef IN_RING3
1879 PFNHDACODECVERBPROCESSOR pfn = NULL;
1880 uint64_t resp;
1881 uint32_t cmd = HDA_REG(pThis, IC);
1882 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
1883 {
1884 /*
1885 * 3.4.3 defines behavior of immediate Command status register.
1886 */
1887 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
1888 return rc;
1889 }
1890 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1891 LogFunc(("IC:%x\n", cmd));
1892
1893 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1894 HDA_CODEC_CMD(cmd, 0 /* LUN */),
1895 &pfn);
1896 if (RT_FAILURE(rc))
1897 AssertRCReturn(rc, rc);
1898 rc = pfn(pThis->pCodec,
1899 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1900 if (RT_FAILURE(rc))
1901 AssertRCReturn(rc, rc);
1902
1903 HDA_REG(pThis, IR) = (uint32_t)resp;
1904 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
1905 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1906 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1907#else /* !IN_RING3 */
1908 rc = VINF_IOM_R3_MMIO_WRITE;
1909#endif
1910 return rc;
1911 }
1912 /*
1913 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1914 */
1915 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1916 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
1917 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1918 return rc;
1919}
1920
1921static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1922{
1923 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1924 {
1925 HDA_REG(pThis, RIRBWP) = 0;
1926 }
1927 /* The remaining bits are O, see 6.2.22 */
1928 return VINF_SUCCESS;
1929}
1930
1931static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1932{
1933 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1934 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1935 if (RT_FAILURE(rc))
1936 AssertRCReturn(rc, rc);
1937
1938 switch(iReg)
1939 {
1940 case HDA_REG_CORBLBASE:
1941 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
1942 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
1943 break;
1944 case HDA_REG_CORBUBASE:
1945 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
1946 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1947 break;
1948 case HDA_REG_RIRBLBASE:
1949 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
1950 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
1951 break;
1952 case HDA_REG_RIRBUBASE:
1953 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
1954 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1955 break;
1956 case HDA_REG_DPLBASE:
1957 /** @todo: first bit has special meaning */
1958 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
1959 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
1960 break;
1961 case HDA_REG_DPUBASE:
1962 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
1963 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1964 break;
1965 default:
1966 AssertMsgFailed(("Invalid index"));
1967 break;
1968 }
1969
1970 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
1971 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
1972 return rc;
1973}
1974
1975static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1976{
1977 uint8_t v = HDA_REG(pThis, RIRBSTS);
1978 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
1979
1980 return hdaProcessInterrupt(pThis);
1981}
1982
1983#ifdef IN_RING3
1984#ifdef LOG_ENABLED
1985static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1986{
1987#if 0
1988 uint64_t addr;
1989 uint32_t len;
1990 uint32_t ioc;
1991 uint8_t bdle[16];
1992 uint32_t counter;
1993 uint32_t i;
1994 uint32_t sum = 0;
1995 Assert(pBdle && pBdle->u32BdleMaxCvi);
1996 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1997 {
1998 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i*16, bdle, 16);
1999 addr = *(uint64_t *)bdle;
2000 len = *(uint32_t *)&bdle[8];
2001 ioc = *(uint32_t *)&bdle[12];
2002 LogFunc(("%s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
2003 sum += len;
2004 }
2005 LogFunc(("sum: %d\n", sum));
2006 for (i = 0; i < 8; ++i)
2007 {
2008 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
2009 LogFunc(("%s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
2010 i , counter));
2011 }
2012#endif
2013}
2014#endif
2015
2016static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2017{
2018 uint8_t bdle[16];
2019 Assert(( pStreamDesc->u64BaseDMA
2020 && pBdle
2021 && pBdle->u32BdleMaxCvi));
2022 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
2023 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
2024 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
2025 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
2026#ifdef LOG_ENABLED
2027 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2028#endif
2029}
2030
2031DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2032 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
2033{
2034 /*
2035 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
2036 */
2037 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
2038 uint32_t cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
2039 /*
2040 * we may increase the counter in range of [0, FIFOS + 1]
2041 */
2042 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
2043 Assert((u32SoundBackendBufferBytesAvail > 0));
2044
2045 /* sanity check to avoid overriding the backend audio buffer */
2046 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
2047 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
2048
2049 if (cb2Copy <= pBdle->cbUnderFifoW)
2050 return 0;
2051 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
2052 return cb2Copy;
2053}
2054
2055DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2056 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2057{
2058 LogFunc(("cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2059 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2060 Assert((cbCopied));
2061 AssertPtr(pu32DMACursor);
2062 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
2063 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
2064 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2065 * where it might happen.
2066 */
2067 AssertMsg((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy), /* we assume that we write the entire buffer including unreported bytes */
2068 ("cbCopied=%RU32 != pBdle->cbUnderFifoW=%RU32 + cbArranged2Copy=%RU32\n",
2069 cbCopied, pBdle->cbUnderFifoW, cbArranged2Copy));
2070 if ( pBdle->cbUnderFifoW
2071 && pBdle->cbUnderFifoW <= cbCopied)
2072 {
2073 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n",
2074 pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2075 }
2076
2077 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
2078 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
2079
2080 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
2081 pBdle->u32BdleCviPos += cbArranged2Copy;
2082
2083 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
2084 /* We report all bytes (including previously unreported bytes) */
2085 *pu32DMACursor += cbCopied;
2086 /* Decrease the backend counter by the number of bytes we copied to the backend */
2087 *pu32BackendBufferCapacity -= cbCopied;
2088 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2089 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
2090}
2091
2092DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2093 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2094{
2095 Assert((cbCopied, cbArranged2Copy));
2096 *pu32BackendBufferCapacity -= cbCopied;
2097 pBdle->u32BdleCviPos += cbCopied;
2098 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2099 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
2100 pBdle->cbUnderFifoW = 0;
2101 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2102 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2103}
2104
2105DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2106 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
2107{
2108 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2109 pBdle->u32BdleCviPos += cbCopied;
2110 pBdle->cbUnderFifoW += cbCopied;
2111 /* In case of a read transaction we're always copying from the backend buffer */
2112 if (pu32BackendBufferCapacity)
2113 *pu32BackendBufferCapacity -= cbCopied;
2114 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2115 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
2116}
2117
2118DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2119{
2120 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
2121 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
2122
2123 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2124
2125 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2126 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
2127 hdaUpdatePosBuf(pThis, pStreamDesc);
2128
2129 /* don't touch BdleCvi counter on uninitialized descriptor */
2130 if ( pBdle->u32BdleCviPos
2131 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
2132 {
2133 pBdle->u32BdleCviPos = 0;
2134 pBdle->u32BdleCvi++;
2135 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
2136 pBdle->u32BdleCvi = 0;
2137 }
2138 return fOnBufferEdge;
2139}
2140
2141DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2142 uint32_t cbInc)
2143{
2144 /*
2145 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
2146 * (ICH6 datasheet 18.2.38)
2147 */
2148 if (!pBdle->cbUnderFifoW)
2149 {
2150 *pStreamDesc->pu32Lpib += cbInc;
2151
2152 /*
2153 * Assert. The buffer counters should never overlap.
2154 */
2155 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2156
2157 hdaUpdatePosBuf(pThis, pStreamDesc);
2158 }
2159}
2160
2161static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2162{
2163 bool fDoNextTransferLoop = true;
2164 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
2165 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2166 {
2167 if ( !pBdle->cbUnderFifoW
2168 && pBdle->fBdleCviIoc)
2169 {
2170 /**
2171 * @todo - more carefully investigate BCIS flag.
2172 * Speech synthesis works fine on Mac Guest if this bit isn't set
2173 * but in general sound quality gets worse.
2174 */
2175 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2176
2177 /*
2178 * we should generate the interrupt if ICE bit of SDCTL register is set.
2179 */
2180 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2181 hdaProcessInterrupt(pThis);
2182 }
2183 fDoNextTransferLoop = false;
2184 }
2185 return fDoNextTransferLoop;
2186}
2187
2188#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2189/**
2190 * hdaReadAudio - copies samples from audio backend to DMA.
2191 * Note: This function writes to the DMA buffer immediately,
2192 * but "reports bytes" when all conditions are met (FIFOW).
2193 */
2194static int hdaReadAudio(PHDASTATE pThis, PAUDMIXSINK pSink,
2195 PHDASTREAMTRANSFERDESC pStreamDesc,
2196 uint32_t u32CblLimit, uint32_t *pcbAvail, uint32_t *pcbRead)
2197{
2198 PHDABDLEDESC pBdle = &pThis->StInBdle; /** @todo Add support for mic in. */
2199
2200 int rc;
2201 uint32_t cbTransferred = 0;
2202
2203 LogFlowFunc(("CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2204
2205 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2206 if (!cb2Copy)
2207 {
2208 /* If we enter here we can't report "unreported bits". */
2209 rc = VERR_NO_DATA;
2210 }
2211 else
2212 {
2213 uint32_t cbRead = 0;
2214 rc = audioMixerProcessSinkIn(pSink, pBdle->au8HdaBuffer, cb2Copy, &cbRead);
2215 if (RT_SUCCESS(rc))
2216 {
2217 Assert(cbRead);
2218
2219 /*
2220 * Write the HDA DMA buffer.
2221 */
2222 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2223 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2224 pBdle->au8HdaBuffer, cbRead);
2225
2226 /* Don't see any reason why cb2Copy would differ from cbRead. */
2227 Assert((cbRead == cb2Copy && (*pcbAvail) >= cb2Copy)); /* sanity */
2228
2229 if (pBdle->cbUnderFifoW + cbRead > hdaFifoWToSz(pThis, 0))
2230 hdaBackendReadTransferReported(pBdle, cb2Copy, cbRead, &cbTransferred, pcbAvail);
2231 else
2232 {
2233 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbRead, pcbAvail);
2234 rc = VERR_NO_DATA;
2235 }
2236 }
2237 }
2238
2239 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2240 LogFunc(("CVI(pos:%RU32, len:%RU32), cbTransferred=%RU32, rc=%Rrc\n",
2241 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2242
2243 if (RT_SUCCESS(rc))
2244 *pcbRead = cbTransferred;
2245
2246 return rc;
2247}
2248#else
2249static int hdaReadAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc,
2250 uint32_t u32CblLimit, uint32_t *pu32Avail, uint32_t *pcbRead)
2251{
2252 PHDABDLEDESC pBdle = &pThis->StInBdle;
2253
2254 uint32_t cbTransferred = 0;
2255 uint32_t cb2Copy = 0;
2256 uint32_t cbBackendCopy = 0;
2257
2258 int rc;
2259
2260 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2261
2262 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
2263 if (!cb2Copy)
2264 {
2265 /* if we enter here we can't report "unreported bits" */
2266 rc = VERR_NO_DATA;
2267 }
2268 else
2269 {
2270 /*
2271 * read from backend input line to the last unreported position or at the begining.
2272 */
2273 cbBackendCopy = AUD_read(pThis->pCodec->SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
2274
2275 /*
2276 * write the HDA DMA buffer
2277 */
2278 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer,
2279 cbBackendCopy);
2280
2281 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
2282 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
2283
2284 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pThis, 0))
2285 {
2286 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
2287 rc = VINF_SUCCESS;
2288 }
2289 else
2290 {
2291 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
2292 rc = VERR_NO_DATA;
2293 }
2294 }
2295
2296 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2297 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
2298
2299 if (pcbRead)
2300 *pcbRead = cbTransferred;
2301
2302 return rc;
2303}
2304#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2305
2306static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32CblLimit,
2307 uint32_t *pcbAvail, uint32_t *pcbWritten)
2308{
2309 PHDABDLEDESC pBdle = &pThis->StOutBdle;
2310
2311 int rc = VINF_SUCCESS;
2312
2313 uint32_t cbTransferred = 0;
2314 uint32_t cbWrittenMin = 0; /* local byte counter, how many bytes copied to backend */
2315
2316 LogFunc(("CVI(cvi:%RU32, pos:%RU32, len:%RU32)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2317
2318 /* Local byte counter (on local buffer). */
2319 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2320
2321 /*
2322 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
2323 * previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
2324 */
2325 if (!cb2Copy)
2326 {
2327 rc = VERR_NO_DATA;
2328 }
2329 else
2330 {
2331 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2332 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2333 pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
2334#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2335 STAM_COUNTER_ADD(&pThis->StatBytesRead, cb2Copy);
2336#endif
2337
2338 /*
2339 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2340 */
2341 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
2342 {
2343#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2344 uint32_t cbWritten;
2345 cbWrittenMin = UINT32_MAX;
2346
2347 PHDADRIVER pDrv;
2348 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2349 {
2350 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2351 {
2352 rc = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2353 pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW,
2354 &cbWritten);
2355 if (RT_FAILURE(rc))
2356 continue;
2357 }
2358 else /* Stream disabled, just assume all was copied. */
2359 cbWritten = cb2Copy;
2360
2361 cbWrittenMin = RT_MIN(cbWrittenMin, cbWritten);
2362 LogFlowFunc(("\tLUN#%RU8: cbWritten=%RU32, cWrittenMin=%RU32\n", pDrv->uLUN, cbWritten, cbWrittenMin));
2363 }
2364
2365 if (cbWrittenMin == UINT32_MAX)
2366 cbWrittenMin = 0;
2367#else
2368 cbWrittenMin = AUD_write (pThis->pCodec->SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
2369#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2370
2371 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbWrittenMin, &cbTransferred, pcbAvail);
2372 }
2373 else
2374 {
2375 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2376 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
2377 rc = VERR_NO_DATA;
2378 }
2379 }
2380
2381 Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
2382 LogFunc(("CVI(pos:%RU32, len:%RU32, cbTransferred:%RU32), rc=%Rrc\n",
2383 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2384
2385 if (RT_SUCCESS(rc))
2386 *pcbWritten = cbTransferred;
2387
2388 return rc;
2389}
2390
2391/**
2392 * @interface_method_impl{HDACODEC,pfnReset}
2393 */
2394DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2395{
2396 PHDASTATE pThis = pCodec->pHDAState;
2397 NOREF(pThis);
2398 return VINF_SUCCESS;
2399}
2400
2401DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
2402 PHDASTREAMTRANSFERDESC pStreamDesc)
2403{
2404 Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
2405
2406 RT_BZERO(pStreamDesc, sizeof(HDASTREAMTRANSFERDESC));
2407 pStreamDesc->u8Strm = u8Strm;
2408 pStreamDesc->u32Ctl = HDA_STREAM_REG(pThis, CTL, u8Strm);
2409 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2410 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2411 pStreamDesc->pu32Lpib = &HDA_STREAM_REG(pThis, LPIB, u8Strm);
2412 pStreamDesc->pu32Sts = &HDA_STREAM_REG(pThis, STS, u8Strm);
2413 pStreamDesc->u32Cbl = HDA_STREAM_REG(pThis, CBL, u8Strm);
2414 pStreamDesc->u32Fifos = HDA_STREAM_REG(pThis, FIFOS, u8Strm);
2415
2416 pBdle->u32BdleMaxCvi = HDA_STREAM_REG(pThis, LVI, u8Strm);
2417
2418#ifdef LOG_ENABLED
2419 if ( pBdle
2420 && pBdle->u32BdleMaxCvi)
2421 {
2422 LogFunc(("Initialization of transfer descriptor:\n"));
2423 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2424 }
2425#endif
2426}
2427
2428static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2429{
2430 NOREF(pThis);
2431 NOREF(enmRecSource);
2432 LogFlowFuncEnter();
2433}
2434
2435static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2436{
2437 NOREF(pThis);
2438 LogFlowFuncEnter();
2439}
2440
2441#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2442static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2443 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2444 PPDMAUDIOSTREAMCFG pCfg)
2445{
2446 PAUDMIXSINK pSink;
2447
2448 switch (enmRecSource)
2449 {
2450# ifdef VBOX_WITH_HDA_MIC_IN
2451 case PDMAUDIORECSOURCE_MIC:
2452 pSink = pThis->pSinkMicIn;
2453 break;
2454# endif
2455 case PDMAUDIORECSOURCE_LINE_IN:
2456 pSink = pThis->pSinkLineIn;
2457 break;
2458 default:
2459 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2460 return VERR_NOT_SUPPORTED;
2461 }
2462
2463 int rc;
2464 char *pszDesc;
2465
2466 PHDADRIVER pDrv;
2467 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2468 {
2469 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2470 {
2471 rc = VERR_NO_MEMORY;
2472 break;
2473 }
2474
2475 rc = pDrv->pConnector->pfnOpenIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2476 LogFlowFunc(("LUN#%RU8: Opened input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2477 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2478 {
2479 audioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2480 rc = audioMixerAddStreamIn(pSink,
2481 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2482 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2483 }
2484
2485 RTStrFree(pszDesc);
2486 }
2487
2488 LogFlowFuncLeaveRC(rc);
2489 return rc;
2490}
2491
2492static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2493 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2494{
2495 int rc = VINF_SUCCESS;
2496
2497 PHDADRIVER pDrv;
2498 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2499 {
2500 int rc2 = pDrv->pConnector->pfnOpenOut(pDrv->pConnector, pszName, pCfg, &pDrv->Out.pStrmOut);
2501 if (RT_FAILURE(rc2))
2502 {
2503 LogFunc(("LUN#%RU8: Opening stream \"%s\" failed, rc=%Rrc\n", pDrv->uLUN, pszName, rc2));
2504 if (RT_SUCCESS(rc))
2505 rc = rc2;
2506 /* Keep going. */
2507 }
2508 }
2509
2510 LogFlowFuncLeaveRC(rc);
2511 return rc;
2512}
2513
2514static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis,
2515 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2516{
2517 int rc = VINF_SUCCESS;
2518
2519 PHDADRIVER pDrv;
2520 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2521 {
2522 int rc2 = pDrv->pConnector->pfnSetVolume(pDrv->pConnector,
2523 fMute, uVolLeft, uVolRight);
2524 if (RT_FAILURE(rc2))
2525 {
2526 LogFunc(("Failed for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
2527 if (RT_SUCCESS(rc))
2528 rc = rc2;
2529 /* Keep going. */
2530 }
2531 }
2532
2533 LogFlowFuncLeaveRC(rc);
2534 return rc;
2535}
2536#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2537
2538#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2539static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2540{
2541 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2542 AssertPtr(pThis);
2543
2544 STAM_PROFILE_START(&pThis->StatTimer, a);
2545
2546 int rc = VINF_SUCCESS;
2547
2548 uint32_t cbInMax = 0;
2549 uint32_t cbOutMin = UINT32_MAX;
2550
2551 PHDADRIVER pDrv;
2552 uint32_t cbIn, cbOut;
2553
2554 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2555 {
2556 if (!pDrv->pConnector->pfnIsOutputOK(pDrv->pConnector, pDrv->Out.pStrmOut))
2557 {
2558 pDrv->cSamplesLive = 0;
2559 continue;
2560 }
2561
2562 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2563 &cbIn, &cbOut, &pDrv->cSamplesLive);
2564 if (RT_SUCCESS(rc))
2565 {
2566 if (cbIn || cbOut)
2567 LogFlowFunc(("\tLUN#%RU8: cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2568
2569 cbInMax = RT_MAX(cbInMax, cbIn);
2570 cbOutMin = RT_MIN(cbOutMin, cbOut);
2571 }
2572 else
2573 pDrv->cSamplesLive = 0;
2574 }
2575
2576 /*
2577 * Playback.
2578 */
2579 if (cbOutMin)
2580 {
2581 Assert(cbOutMin != UINT32_MAX);
2582 hdaTransfer(pThis, PO_INDEX, cbOutMin); /** @todo Add rc! */
2583 }
2584 else
2585 {
2586 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2587 {
2588 /*if (pDrv->cSamplesLive)
2589 pDrv->pConnector->pfnPlayOut(pDrv->pConnector);*/
2590 }
2591 }
2592
2593 /*
2594 * Recording.
2595 */
2596 if (cbInMax)
2597 hdaTransfer(pThis, PI_INDEX, cbInMax); /** @todo Add rc! */
2598
2599 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
2600
2601 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2602}
2603
2604static DECLCALLBACK(int) hdaTransfer(PHDASTATE pThis,
2605 ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2606{
2607 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2608
2609 LogFlowFunc(("pThis=%p, cbAvail=%RU32\n", pThis, cbAvail));
2610#else
2611static DECLCALLBACK(int) hdaTransfer(PHDACODEC pCodec, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2612{
2613 AssertPtrReturn(pCodec, VERR_INVALID_POINTER);
2614 PHDASTATE pThis = pCodec->pHDAState;
2615 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2616#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2617 int rc;
2618
2619 uint8_t u8Strm;
2620 PHDABDLEDESC pBdle;
2621
2622 switch (enmSrc)
2623 {
2624 case PI_INDEX:
2625 {
2626 u8Strm = 0;
2627 pBdle = &pThis->StInBdle;
2628 break;
2629 }
2630
2631#ifdef VBOX_WITH_HDA_MIC_IN
2632 case MC_INDEX:
2633 {
2634 u8Strm = 2;
2635 pBdle = &pThis->StMicBdle;
2636 break;
2637 }
2638#endif
2639 case PO_INDEX:
2640 {
2641 u8Strm = 4;
2642 pBdle = &pThis->StOutBdle;
2643 break;
2644 }
2645
2646 default:
2647 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
2648 return VERR_NOT_SUPPORTED;
2649 }
2650
2651 HDASTREAMTRANSFERDESC StreamDesc;
2652 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2653
2654 while (cbAvail)
2655 {
2656 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
2657 && cbAvail
2658 && StreamDesc.u64BaseDMA);
2659
2660 /* Fetch the Buffer Descriptor Entry (BDE). */
2661 if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
2662 hdaFetchBdle(pThis, pBdle, &StreamDesc);
2663
2664 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2665 Assert((StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib))); /* sanity */
2666 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
2667 Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
2668
2669 LogFunc(("CBL=%RU32, LPIB=%RU32\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
2670
2671#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2672 PAUDMIXSINK pSink;
2673#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2674 uint32_t cbWritten;
2675 switch (enmSrc)
2676 {
2677 case PI_INDEX:
2678#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2679 pSink = pThis->pSinkLineIn;
2680 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2681#else
2682 rc = hdaReadAudio(pThis, &StreamDesc, u32CblLimit, (uint32_t *)&cbAvail, &cbWritten);
2683#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2684 break;
2685 case PO_INDEX:
2686 rc = hdaWriteAudio(pThis, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2687 break;
2688#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2689# ifdef VBOX_WITH_HDA_MIC_IN
2690 case MC_INDEX:
2691 pSink = pThis->pSinkMicIn;
2692 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2693 break;
2694# endif
2695#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2696 default:
2697 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
2698 rc = VERR_NOT_SUPPORTED;
2699 break;
2700 }
2701 Assert(cbWritten <= StreamDesc.u32Fifos + 1);
2702 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2703
2704 /* Process end of buffer condition. */
2705 hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cbWritten);
2706
2707 if ( !hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc)
2708 || RT_FAILURE(rc))
2709 {
2710 if (rc == VERR_NO_DATA) /* No more data to process. */
2711 rc = VINF_SUCCESS;
2712
2713 break;
2714 }
2715 }
2716
2717 return rc;
2718}
2719#endif /* IN_RING3 */
2720
2721/* MMIO callbacks */
2722
2723/**
2724 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
2725 *
2726 * @note During implementation, we discovered so-called "forgotten" or "hole"
2727 * registers whose description is not listed in the RPM, datasheet, or
2728 * spec.
2729 */
2730PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2731{
2732 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2733 int rc;
2734
2735 /*
2736 * Look up and log.
2737 */
2738 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2739 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
2740#ifdef LOG_ENABLED
2741 unsigned const cbLog = cb;
2742 uint32_t offRegLog = offReg;
2743#endif
2744
2745 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
2746#define NEW_READ_CODE
2747#ifdef NEW_READ_CODE
2748 Assert(cb == 4); Assert((offReg & 3) == 0);
2749
2750 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2751 LogFunc(("access to registers except GCTL is blocked while reset\n"));
2752
2753 if (idxRegDsc == -1)
2754 LogRel(("Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
2755
2756 if (idxRegDsc != -1)
2757 {
2758 /* ASSUMES gapless DWORD at end of map. */
2759 if (g_aHdaRegMap[idxRegDsc].size == 4)
2760 {
2761 /*
2762 * Straight forward DWORD access.
2763 */
2764 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
2765 LogFunc(("read %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
2766 }
2767 else
2768 {
2769 /*
2770 * Multi register read (unless there are trailing gaps).
2771 * ASSUMES that only DWORD reads have sideeffects.
2772 */
2773 uint32_t u32Value = 0;
2774 unsigned cbLeft = 4;
2775 do
2776 {
2777 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
2778 uint32_t u32Tmp = 0;
2779
2780 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
2781 LogFunc(("read %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
2782 if (rc != VINF_SUCCESS)
2783 break;
2784 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
2785
2786 cbLeft -= cbReg;
2787 offReg += cbReg;
2788 idxRegDsc++;
2789 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
2790
2791 if (rc == VINF_SUCCESS)
2792 *(uint32_t *)pv = u32Value;
2793 else
2794 Assert(!IOM_SUCCESS(rc));
2795 }
2796 }
2797 else
2798 {
2799 rc = VINF_IOM_MMIO_UNUSED_FF;
2800 LogFunc(("hole at %x is accessed for read\n", offReg));
2801 }
2802#else
2803 if (idxRegDsc != -1)
2804 {
2805 /** @todo r=bird: Accesses crossing register boundraries aren't handled
2806 * right from what I can tell? If they are, please explain
2807 * what the rules are. */
2808 uint32_t mask = 0;
2809 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2810 uint32_t u32Value = 0;
2811 switch(cb)
2812 {
2813 case 1: mask = 0x000000ff; break;
2814 case 2: mask = 0x0000ffff; break;
2815 case 4:
2816 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2817 case 8:
2818 mask = 0xffffffff;
2819 cb = 4;
2820 break;
2821 }
2822#if 0
2823 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
2824 */
2825 //Assert((cb <= g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset)));
2826 if (cb > g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset))
2827 {
2828 int off = cb - (g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset));
2829 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2830 if (RT_FAILURE(rc))
2831 AssertRCReturn (rc, rc);
2832 }
2833 //Assert(((offReg - g_aHdaRegMap[idxRegDsc].offset) == 0));
2834#endif
2835 mask <<= shift;
2836 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Value);
2837 *(uint32_t *)pv |= (u32Value & mask);
2838 LogFunc(("read %s[%x/%x]\n", g_aHdaRegMap[idxRegDsc].abbrev, u32Value, *(uint32_t *)pv));
2839 }
2840 else
2841 {
2842 *(uint32_t *)pv = 0xFF;
2843 LogFunc(("hole at %x is accessed for read\n", offReg));
2844 rc = VINF_SUCCESS;
2845 }
2846#endif
2847
2848 /*
2849 * Log the outcome.
2850 */
2851#ifdef LOG_ENABLED
2852 if (cbLog == 4)
2853 LogFunc(("@%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
2854 else if (cbLog == 2)
2855 LogFunc(("@%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
2856 else if (cbLog == 1)
2857 LogFunc(("@%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
2858#endif
2859 return rc;
2860}
2861
2862
2863DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
2864{
2865 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2866 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
2867
2868 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2869#ifdef LOG_ENABLED
2870 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
2871#endif
2872 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
2873 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
2874 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
2875 return rc;
2876}
2877
2878
2879/**
2880 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
2881 */
2882PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2883{
2884 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2885 int rc;
2886
2887 /*
2888 * The behavior of accesses that aren't aligned on natural boundraries is
2889 * undefined. Just reject them outright.
2890 */
2891 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
2892 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
2893 if (GCPhysAddr & (cb - 1))
2894 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
2895
2896 /*
2897 * Look up and log the access.
2898 */
2899 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2900 int idxRegDsc = hdaRegLookup(pThis, offReg);
2901 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
2902 uint64_t u64Value;
2903 if (cb == 4) u64Value = *(uint32_t const *)pv;
2904 else if (cb == 2) u64Value = *(uint16_t const *)pv;
2905 else if (cb == 1) u64Value = *(uint8_t const *)pv;
2906 else if (cb == 8) u64Value = *(uint64_t const *)pv;
2907 else
2908 {
2909 u64Value = 0; /* shut up gcc. */
2910 AssertReleaseMsgFailed(("%d\n", cb));
2911 }
2912
2913#ifdef LOG_ENABLED
2914 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
2915 uint32_t const offRegLog = offReg;
2916 int const idxRegLog = idxRegMem;
2917 if (idxRegDsc == -1)
2918 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
2919 else if (cb == 4)
2920 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2921 else if (cb == 2)
2922 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2923 else if (cb == 1)
2924 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2925 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
2926 LogFunc(("size=%d != cb=%d!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
2927#endif
2928
2929#define NEW_WRITE_CODE
2930#ifdef NEW_WRITE_CODE
2931 /*
2932 * Try for a direct hit first.
2933 */
2934 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
2935 {
2936 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
2937 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2938 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2939 }
2940 /*
2941 * Partial or multiple register access, loop thru the requested memory.
2942 */
2943 else
2944 {
2945 /* If it's an access beyond the start of the register, shift the input
2946 value and fill in missing bits. Natural alignment rules means we
2947 will only see 1 or 2 byte accesses of this kind, so no risk of
2948 shifting out input values. */
2949 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
2950 {
2951 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
2952 offReg -= cbBefore;
2953 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2954 u64Value <<= cbBefore * 8;
2955 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
2956 LogFunc(("Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
2957 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
2958 }
2959
2960 /* Loop thru the write area, it may cover multiple registers. */
2961 rc = VINF_SUCCESS;
2962 for (;;)
2963 {
2964 uint32_t cbReg;
2965 if (idxRegDsc != -1)
2966 {
2967 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2968 cbReg = g_aHdaRegMap[idxRegDsc].size;
2969 if (cb < cbReg)
2970 {
2971 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
2972 LogFunc(("Supplying missing bits (%#x): %#llx -> %#llx ...\n",
2973 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
2974 }
2975 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
2976 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
2977 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldVal,
2978 pThis->au32Regs[idxRegMem]));
2979 }
2980 else
2981 {
2982 LogRel(("HDA: Invalid write access @0x%x!\n", offReg));
2983 cbReg = 1;
2984 }
2985 if (rc != VINF_SUCCESS)
2986 break;
2987 if (cbReg >= cb)
2988 break;
2989
2990 /* advance */
2991 offReg += cbReg;
2992 cb -= cbReg;
2993 u64Value >>= cbReg * 8;
2994 if (idxRegDsc == -1)
2995 idxRegDsc = hdaRegLookup(pThis, offReg);
2996 else
2997 {
2998 idxRegDsc++;
2999 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3000 || g_aHdaRegMap[idxRegDsc].offset != offReg)
3001 idxRegDsc = -1;
3002 }
3003 }
3004 }
3005#else
3006 if (idxRegDsc != -1)
3007 {
3008 /** @todo r=bird: This looks like code for handling unaligned register
3009 * accesses. If it isn't, then add a comment explaining what you're
3010 * trying to do here. OTOH, if it is then it has the following
3011 * issues:
3012 * -# You're calculating the wrong new value for the register.
3013 * -# You're not handling cross register accesses. Imagine a
3014 * 4-byte write starting at CORBCTL, or a 8-byte write.
3015 *
3016 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
3017 * nobody seems to be using it and it just adds complexity when reading
3018 * the code.
3019 *
3020 */
3021 uint32_t u32CurValue = pThis->au32Regs[idxRegMem];
3022 uint32_t u32NewValue;
3023 uint32_t mask;
3024 switch (cb)
3025 {
3026 case 1:
3027 u32NewValue = *(uint8_t const *)pv;
3028 mask = 0xff;
3029 break;
3030 case 2:
3031 u32NewValue = *(uint16_t const *)pv;
3032 mask = 0xffff;
3033 break;
3034 case 4:
3035 case 8:
3036 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
3037 u32NewValue = *(uint32_t const *)pv;
3038 mask = 0xffffffff;
3039 cb = 4;
3040 break;
3041 default:
3042 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
3043 }
3044 /* cross-register access, see corresponding comment in hdaMMIORead */
3045 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
3046 mask <<= shift;
3047 u32NewValue <<= shift;
3048 u32NewValue &= mask;
3049 u32NewValue |= (u32CurValue & ~mask);
3050
3051 rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32NewValue);
3052 LogFunc(("write %s:(%x) %x => %x\n", g_aHdaRegMap[idxRegDsc].abbrev, u32NewValue,
3053 u32CurValue, pThis->au32Regs[idxRegMem]));
3054 }
3055 else
3056 rc = VINF_SUCCESS;
3057
3058 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
3059 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
3060#endif
3061 return rc;
3062}
3063
3064
3065/* PCI callback. */
3066
3067#ifdef IN_RING3
3068/**
3069 * @callback_method_impl{FNPCIIOREGIONMAP}
3070 */
3071static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
3072 PCIADDRESSSPACE enmType)
3073{
3074 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3075 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3076 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3077 int rc;
3078
3079 /*
3080 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3081 *
3082 * Let IOM talk DWORDs when reading, saves a lot of complications. On
3083 * writing though, we have to do it all ourselves because of sideeffects.
3084 */
3085 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3086 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
3087#ifdef NEW_READ_CODE
3088 IOMMMIO_FLAGS_READ_DWORD |
3089#else
3090 IOMMMIO_FLAGS_READ_PASSTHRU |
3091#endif
3092 IOMMMIO_FLAGS_WRITE_PASSTHRU,
3093 hdaMMIOWrite, hdaMMIORead, "HDA");
3094
3095 if (RT_FAILURE(rc))
3096 return rc;
3097
3098 if (pThis->fR0Enabled)
3099 {
3100 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
3101 "hdaMMIOWrite", "hdaMMIORead");
3102 if (RT_FAILURE(rc))
3103 return rc;
3104 }
3105
3106 if (pThis->fRCEnabled)
3107 {
3108 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
3109 "hdaMMIOWrite", "hdaMMIORead");
3110 if (RT_FAILURE(rc))
3111 return rc;
3112 }
3113
3114 pThis->MMIOBaseAddr = GCPhysAddress;
3115 return VINF_SUCCESS;
3116}
3117
3118
3119/* Saved state callbacks. */
3120
3121/**
3122 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3123 */
3124static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3125{
3126 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3127
3128 /* Save Codec nodes states */
3129 hdaCodecSaveState(pThis->pCodec, pSSM);
3130
3131 /* Save MMIO registers */
3132 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3133 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3134 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3135
3136 /* Save HDA dma counters */
3137 SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3138 SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3139 SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3140 return VINF_SUCCESS;
3141}
3142
3143
3144/**
3145 * @callback_method_impl{FNSSMDEVLOADEXEC}
3146 */
3147static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3148{
3149 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3150
3151 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3152
3153 /*
3154 * Load Codec nodes states.
3155 */
3156 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3157 if (RT_FAILURE(rc))
3158 return rc;
3159
3160 /*
3161 * Load MMIO registers.
3162 */
3163 uint32_t cRegs;
3164 switch (uVersion)
3165 {
3166 case HDA_SSM_VERSION_1:
3167 /* Starting with r71199, we would save 112 instead of 113
3168 registers due to some code cleanups. This only affected trunk
3169 builds in the 4.1 development period. */
3170 cRegs = 113;
3171 if (SSMR3HandleRevision(pSSM) >= 71199)
3172 {
3173 uint32_t uVer = SSMR3HandleVersion(pSSM);
3174 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3175 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3176 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3177 cRegs = 112;
3178 }
3179 break;
3180
3181 case HDA_SSM_VERSION_2:
3182 case HDA_SSM_VERSION_3:
3183 cRegs = 112;
3184 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3185 break;
3186
3187 case HDA_SSM_VERSION:
3188 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3189 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3190 LogRel(("cRegs is %d, expected %d\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3191 break;
3192
3193 default:
3194 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3195 }
3196
3197 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3198 {
3199 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3200 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3201 }
3202 else
3203 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3204
3205 /*
3206 * Load HDA DMA counters.
3207 */
3208 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
3209 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
3210 rc = SSMR3GetStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), fFlags, paFields, NULL);
3211 AssertRCReturn(rc, rc);
3212 rc = SSMR3GetStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), fFlags, paFields, NULL);
3213 AssertRCReturn(rc, rc);
3214 rc = SSMR3GetStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), fFlags, paFields, NULL);
3215 AssertRCReturn(rc, rc);
3216
3217 /*
3218 * Update stuff after the state changes.
3219 */
3220 bool fEnableIn = RT_BOOL(SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3221#ifdef VBOX_WITH_HDA_MIC_IN
3222 bool fEnableMicIn = RT_BOOL(SDCTL(pThis, 2) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3223#endif
3224 bool fEnableOut = RT_BOOL(SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3225
3226#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3227 PHDADRIVER pDrv;
3228 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3229 {
3230 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn,
3231 fEnableIn);
3232 if (RT_FAILURE(rc))
3233 break;
3234# ifdef VBOX_WITH_HDA_MIC_IN
3235 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn,
3236 fEnableMicIn);
3237 if (RT_FAILURE(rc))
3238 break;
3239# endif
3240 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut,
3241 fEnableOut);
3242 if (RT_FAILURE(rc))
3243 break;
3244 }
3245#else
3246 AUD_set_active_in(pThis->pCodec->SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3247 AUD_set_active_out(pThis->pCodec->SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3248#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3249
3250 if (RT_SUCCESS(rc))
3251 {
3252 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3253 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3254 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3255 }
3256
3257 LogFlowFuncLeaveRC(rc);
3258 return rc;
3259}
3260
3261
3262/* Debug and log type formatters. */
3263
3264/**
3265 * @callback_method_impl{FNRTSTRFORMATTYPE}
3266 */
3267static DECLCALLBACK(size_t)
3268hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3269 const char *pszType, void const *pvValue,
3270 int cchWidth, int cchPrecision, unsigned fFlags,
3271 void *pvUser)
3272{
3273 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
3274 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3275 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
3276 sdCtl,
3277 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> HDA_SDCTL_NUM_SHIFT,
3278 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
3279 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3280 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3281 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3282 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3283 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3284 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3285}
3286
3287/**
3288 * @callback_method_impl{FNRTSTRFORMATTYPE}
3289 */
3290static DECLCALLBACK(size_t)
3291hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3292 const char *pszType, void const *pvValue,
3293 int cchWidth, int cchPrecision, unsigned fFlags,
3294 void *pvUser)
3295{
3296 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3297 uint32_t cb;
3298 switch (uSdFifos)
3299 {
3300 case HDA_SDONFIFO_16B: cb = 16; break;
3301 case HDA_SDONFIFO_32B: cb = 32; break;
3302 case HDA_SDONFIFO_64B: cb = 64; break;
3303 case HDA_SDONFIFO_128B: cb = 128; break;
3304 case HDA_SDONFIFO_192B: cb = 192; break;
3305 case HDA_SDONFIFO_256B: cb = 256; break;
3306 case HDA_SDINFIFO_120B: cb = 120; break;
3307 case HDA_SDINFIFO_160B: cb = 160; break;
3308 default: cb = 0; break;
3309 }
3310 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
3311}
3312
3313/**
3314 * @callback_method_impl{FNRTSTRFORMATTYPE}
3315 */
3316static DECLCALLBACK(size_t)
3317hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3318 const char *pszType, void const *pvValue,
3319 int cchWidth, int cchPrecision, unsigned fFlags,
3320 void *pvUser)
3321{
3322 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3323 uint32_t cb;
3324 switch (uSdFifos)
3325 {
3326 case HDA_SDFIFOW_8B: cb = 8; break;
3327 case HDA_SDFIFOW_16B: cb = 16; break;
3328 case HDA_SDFIFOW_32B: cb = 32; break;
3329 default: cb = 0; break;
3330 }
3331 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
3332}
3333
3334/**
3335 * @callback_method_impl{FNRTSTRFORMATTYPE}
3336 */
3337static DECLCALLBACK(size_t)
3338hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3339 const char *pszType, void const *pvValue,
3340 int cchWidth, int cchPrecision, unsigned fFlags,
3341 void *pvUser)
3342{
3343 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3344 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3345 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3346 uSdSts,
3347 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3348 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3349 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3350 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3351}
3352
3353
3354static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3355{
3356 int iReg = 0;
3357 for (; iReg < HDA_NREGS; ++iReg)
3358 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3359 return iReg;
3360 return -1;
3361}
3362
3363
3364static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
3365{
3366 Assert( pThis
3367 && iHdaIndex >= 0
3368 && iHdaIndex < HDA_NREGS);
3369 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
3370}
3371
3372
3373/**
3374 * @callback_method_impl{FNDBGFHANDLERDEV}
3375 */
3376static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3377{
3378 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3379 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
3380 if (iHdaRegisterIndex != -1)
3381 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3382 else
3383 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
3384 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3385}
3386
3387
3388static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
3389{
3390 Assert( pThis
3391 && iHdaStrmIndex >= 0
3392 && iHdaStrmIndex < 7);
3393 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
3394 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
3395 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
3396 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
3397 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
3398}
3399
3400
3401static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
3402{
3403 /* todo: add args parsing */
3404 return -1;
3405}
3406
3407
3408/**
3409 * @callback_method_impl{FNDBGFHANDLERDEV}
3410 */
3411static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3412{
3413 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3414 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
3415 if (iHdaStrmIndex != -1)
3416 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3417 else
3418 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
3419 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3420}
3421
3422
3423/**
3424 * @callback_method_impl{FNDBGFHANDLERDEV}
3425 */
3426static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3427{
3428 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3429
3430 if (pThis->pCodec->pfnCodecDbgListNodes)
3431 pThis->pCodec->pfnCodecDbgListNodes(pThis->pCodec, pHlp, pszArgs);
3432 else
3433 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3434}
3435
3436
3437/**
3438 * @callback_method_impl{FNDBGFHANDLERDEV}
3439 */
3440static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3441{
3442 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3443
3444 if (pThis->pCodec->pfnCodecDbgSelector)
3445 pThis->pCodec->pfnCodecDbgSelector(pThis->pCodec, pHlp, pszArgs);
3446 else
3447 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3448}
3449
3450
3451/* PDMIBASE */
3452
3453/**
3454 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3455 */
3456static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3457{
3458 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
3459 Assert(&pThis->IBase == pInterface);
3460
3461 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3462 return NULL;
3463}
3464
3465
3466/* PDMDEVREG */
3467
3468/**
3469 * Reset notification.
3470 *
3471 * @returns VBox status.
3472 * @param pDevIns The device instance data.
3473 *
3474 * @remark The original sources didn't install a reset handler, but it seems to
3475 * make sense to me so we'll do it.
3476 */
3477static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
3478{
3479 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3480 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
3481 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3482 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3483 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3484 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3485 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
3486 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
3487 HDA_REG(pThis, CORBRP) = 0x0;
3488 HDA_REG(pThis, RIRBWP) = 0x0;
3489
3490 LogFunc(("Resetting ...\n"));
3491
3492#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3493 /* Stop any audio currently playing. */
3494 PHDADRIVER pDrv;
3495 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3496 {
3497 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
3498 /* Ignore rc. */
3499 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
3500 /* Ditto. */
3501 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
3502 /* Ditto. */
3503 }
3504#else
3505 AUD_set_active_in(pThis->pCodec->SwVoiceIn, false);
3506 AUD_set_active_out(pThis->pCodec->SwVoiceOut, false);
3507#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3508
3509 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
3510
3511 if (pThis->pu32CorbBuf)
3512 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3513 else
3514 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3515
3516 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
3517 if (pThis->pu64RirbBuf)
3518 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3519 else
3520 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3521
3522 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
3523
3524 HDABDLEDESC StEmptyBdle;
3525 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
3526 {
3527 HDASTREAMTRANSFERDESC StreamDesc;
3528 PHDABDLEDESC pBdle = NULL;
3529 if (u8Strm == 0)
3530 pBdle = &pThis->StInBdle;
3531# ifdef VBOX_WITH_HDA_MIC_IN
3532 else if (u8Strm == 2)
3533 pBdle = &pThis->StMicBdle;
3534# endif
3535 else if(u8Strm == 4)
3536 pBdle = &pThis->StOutBdle;
3537 else
3538 {
3539 RT_ZERO(StEmptyBdle);
3540 pBdle = &StEmptyBdle;
3541 }
3542 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
3543 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
3544 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
3545 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
3546 }
3547
3548 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3549 HDA_REG(pThis, STATESTS) = 0x1;
3550
3551 LogRel(("HDA: Reset\n"));
3552}
3553
3554/**
3555 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3556 */
3557static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
3558{
3559 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3560
3561#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3562 PHDADRIVER pDrv;
3563 while (!RTListIsEmpty(&pThis->lstDrv))
3564 {
3565 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
3566
3567 RTListNodeRemove(&pDrv->Node);
3568 RTMemFree(pDrv);
3569 }
3570
3571 if (pThis->pMixer)
3572 {
3573 audioMixerDestroy(pThis->pMixer);
3574 pThis->pMixer = NULL;
3575 }
3576#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3577
3578 if (pThis->pCodec)
3579 {
3580 int rc = hdaCodecDestruct(pThis->pCodec);
3581 AssertRC(rc);
3582
3583 RTMemFree(pThis->pCodec);
3584 pThis->pCodec = NULL;
3585 }
3586
3587 RTMemFree(pThis->pu32CorbBuf);
3588 pThis->pu32CorbBuf = NULL;
3589
3590 RTMemFree(pThis->pu64RirbBuf);
3591 pThis->pu64RirbBuf = NULL;
3592
3593 return VINF_SUCCESS;
3594}
3595
3596#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3597/**
3598 * Attach command.
3599 *
3600 * This is called to let the device attach to a driver for a specified LUN
3601 * during runtime. This is not called during VM construction, the device
3602 * constructor have to attach to all the available drivers.
3603 *
3604 * @returns VBox status code.
3605 * @param pDevIns The device instance.
3606 * @param uLUN The logical unit which is being detached.
3607 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3608 */
3609static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
3610{
3611 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3612
3613 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3614 ("HDA device does not support hotplugging\n"),
3615 VERR_INVALID_PARAMETER);
3616
3617 /*
3618 * Attach driver.
3619 */
3620 char *pszDesc = NULL;
3621 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
3622 AssertMsgReturn(pszDesc,
3623 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
3624 VERR_NO_MEMORY);
3625
3626 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
3627 &pThis->IBase, &pThis->pDrvBase, pszDesc);
3628 if (RT_SUCCESS(rc))
3629 {
3630 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
3631 if (pDrv)
3632 {
3633 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
3634 AssertMsg(pDrv->pConnector != NULL,
3635 ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n",
3636 uLUN, rc));
3637 pDrv->pHDAState = pThis;
3638 pDrv->uLUN = uLUN;
3639
3640 /*
3641 * For now we always set the driver at LUN 0 as our primary
3642 * host backend. This might change in the future.
3643 */
3644 if (pDrv->uLUN == 0)
3645 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
3646
3647 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
3648
3649 /* Attach to driver list. */
3650 RTListAppend(&pThis->lstDrv, &pDrv->Node);
3651 }
3652 else
3653 rc = VERR_NO_MEMORY;
3654 }
3655 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
3656 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
3657 {
3658 LogFunc(("No attached driver for LUN #%u\n", uLUN));
3659 }
3660 else if (RT_FAILURE(rc))
3661 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
3662 uLUN, pszDesc, rc));
3663
3664 RTStrFree(pszDesc);
3665
3666 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
3667 return rc;
3668}
3669
3670static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3671{
3672 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
3673
3674 LogFlowFuncEnter();
3675}
3676#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3677
3678/**
3679 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3680 */
3681static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
3682{
3683 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3684 Assert(iInstance == 0);
3685 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3686
3687 /*
3688 * Validations.
3689 */
3690 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
3691 "RCEnabled\0"))
3692 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3693 N_ ("Invalid configuration for the Intel HDA device"));
3694
3695 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
3696 if (RT_FAILURE(rc))
3697 return PDMDEV_SET_ERROR(pDevIns, rc,
3698 N_("HDA configuration error: failed to read RCEnabled as boolean"));
3699 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
3700 if (RT_FAILURE(rc))
3701 return PDMDEV_SET_ERROR(pDevIns, rc,
3702 N_("HDA configuration error: failed to read R0Enabled as boolean"));
3703
3704 /*
3705 * Initialize data (most of it anyway).
3706 */
3707 pThis->pDevInsR3 = pDevIns;
3708 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3709 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3710 /* IBase */
3711 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
3712
3713 /* PCI Device */
3714 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
3715 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
3716
3717 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
3718 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
3719 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
3720 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
3721 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
3722 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
3723 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
3724 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
3725 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
3726 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
3727 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
3728
3729#if defined(HDA_AS_PCI_EXPRESS)
3730 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
3731#elif defined(VBOX_WITH_MSI_DEVICES)
3732 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
3733#else
3734 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
3735#endif
3736
3737 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
3738 /// of these values needs to be properly documented!
3739 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
3740 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
3741
3742 /* Power Management */
3743 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
3744 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
3745 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
3746
3747#ifdef HDA_AS_PCI_EXPRESS
3748 /* PCI Express */
3749 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
3750 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
3751 /* Device flags */
3752 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
3753 /* version */ 0x1 |
3754 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
3755 /* MSI */ (100) << 9 );
3756 /* Device capabilities */
3757 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
3758 /* Device control */
3759 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
3760 /* Device status */
3761 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
3762 /* Link caps */
3763 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
3764 /* Link control */
3765 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
3766 /* Link status */
3767 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
3768 /* Slot capabilities */
3769 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
3770 /* Slot control */
3771 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
3772 /* Slot status */
3773 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
3774 /* Root control */
3775 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
3776 /* Root capabilities */
3777 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
3778 /* Root status */
3779 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
3780 /* Device capabilities 2 */
3781 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
3782 /* Device control 2 */
3783 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
3784 /* Link control 2 */
3785 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
3786 /* Slot control 2 */
3787 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
3788#endif
3789
3790 /*
3791 * Register the PCI device.
3792 */
3793 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
3794 if (RT_FAILURE(rc))
3795 return rc;
3796
3797 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
3798 if (RT_FAILURE(rc))
3799 return rc;
3800
3801#ifdef VBOX_WITH_MSI_DEVICES
3802 PDMMSIREG MsiReg;
3803 RT_ZERO(MsiReg);
3804 MsiReg.cMsiVectors = 1;
3805 MsiReg.iMsiCapOffset = 0x60;
3806 MsiReg.iMsiNextOffset = 0x50;
3807 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3808 if (RT_FAILURE(rc))
3809 {
3810 /* That's OK, we can work without MSI */
3811 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
3812 }
3813#endif
3814
3815 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
3816 if (RT_FAILURE(rc))
3817 return rc;
3818
3819#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3820 RTListInit(&pThis->lstDrv);
3821
3822 uint8_t uLUN;
3823 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
3824 {
3825 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
3826 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
3827 if (RT_FAILURE(rc))
3828 {
3829 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3830 rc = VINF_SUCCESS;
3831
3832 break;
3833 }
3834
3835 uLUN++;
3836 }
3837
3838 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3839
3840 if (RT_SUCCESS(rc))
3841 {
3842 rc = audioMixerCreate("HDA Mixer", 0 /* uFlags */,
3843 &pThis->pMixer);
3844 if (RT_SUCCESS(rc))
3845 {
3846 PDMAUDIOSTREAMCFG streamCfg;
3847 streamCfg.uHz = 48000;
3848 streamCfg.cChannels = 2;
3849 streamCfg.enmFormat = AUD_FMT_S16;
3850 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANESS;
3851
3852 rc = audioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
3853 AssertRC(rc);
3854
3855 /* Add all required audio sinks. */
3856 rc = audioMixerAddSink(pThis->pMixer, "[Recording] Line In",
3857 &pThis->pSinkLineIn);
3858 AssertRC(rc);
3859
3860 rc = audioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
3861 &pThis->pSinkMicIn);
3862 AssertRC(rc);
3863 }
3864 }
3865
3866 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3867#else
3868 /*
3869 * Attach driver.
3870 */
3871 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Audio Driver Port");
3872 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3873 Log(("hda: No attached driver!\n"));
3874 else if (RT_FAILURE(rc))
3875 {
3876 AssertMsgFailed(("Failed to attach Intel HDA LUN #0! rc=%Rrc\n", rc));
3877 return rc;
3878 }
3879#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3880
3881 if (RT_SUCCESS(rc))
3882 {
3883 /* Construct codec. */
3884 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
3885 if (!pThis->pCodec)
3886 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
3887
3888#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3889 /* Audio driver callbacks for multiplexing. */
3890 pThis->pCodec->pfnCloseIn = hdaCloseIn;
3891 pThis->pCodec->pfnCloseOut = hdaCloseOut;
3892 pThis->pCodec->pfnOpenIn = hdaOpenIn;
3893 pThis->pCodec->pfnOpenOut = hdaOpenOut;
3894 pThis->pCodec->pfnSetVolume = hdaSetVolume;
3895#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3896
3897 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
3898
3899 /* Construct the codec. */
3900 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
3901 if (RT_FAILURE(rc))
3902 AssertRCReturn(rc, rc);
3903
3904 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
3905 verb F20 should provide device/codec recognition. */
3906 Assert(pThis->pCodec->u16VendorId);
3907 Assert(pThis->pCodec->u16DeviceId);
3908 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
3909 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
3910
3911#ifndef VBOX_WITH_PDM_AUDIO_DRIVER
3912 pThis->pCodec->pfnTransfer = hdaTransfer;
3913#endif
3914 pThis->pCodec->pfnReset = hdaCodecReset;
3915 }
3916
3917 if (RT_SUCCESS(rc))
3918 {
3919 hdaReset(pDevIns);
3920
3921 /*
3922 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
3923 * hdaReset shouldn't affects these registers.
3924 */
3925 HDA_REG(pThis, WAKEEN) = 0x0;
3926 HDA_REG(pThis, STATESTS) = 0x0;
3927
3928 /*
3929 * Debug and string formatter types.
3930 */
3931 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
3932 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
3933 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
3934 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
3935
3936 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
3937 AssertRC(rc);
3938 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
3939 AssertRC(rc);
3940 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
3941 AssertRC(rc);
3942 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
3943 AssertRC(rc);
3944 #if 0
3945 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
3946 AssertRC(rc);
3947 #endif
3948
3949 /*
3950 * Some debug assertions.
3951 */
3952 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
3953 {
3954 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
3955 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
3956
3957 /* binary search order. */
3958 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
3959 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3960 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3961
3962 /* alignment. */
3963 AssertReleaseMsg( pReg->size == 1
3964 || (pReg->size == 2 && (pReg->offset & 1) == 0)
3965 || (pReg->size == 3 && (pReg->offset & 3) == 0)
3966 || (pReg->size == 4 && (pReg->offset & 3) == 0),
3967 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3968
3969 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
3970 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
3971 if (pReg->offset & 3)
3972 {
3973 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
3974 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3975 if (pPrevReg)
3976 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
3977 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3978 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
3979 }
3980 #if 0
3981 if ((pReg->offset + pReg->size) & 3)
3982 {
3983 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3984 if (pNextReg)
3985 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
3986 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3987 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3988 }
3989 #endif
3990
3991 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
3992 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
3993 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3994 }
3995 }
3996
3997#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3998 if (RT_SUCCESS(rc))
3999 {
4000 /* Start the emulation timer. */
4001 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
4002 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
4003 AssertRCReturn(rc, rc);
4004
4005 if (RT_SUCCESS(rc))
4006 {
4007 /** @todo Investigate why sounds is getting corrupted if the "ticks" value is too
4008 * low, e.g. "PDMDevHlpTMTimeVirtGetFreq / 200". */
4009 pThis->uTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 500; /** @todo Make this configurable! */
4010 if (pThis->uTicks < 100)
4011 pThis->uTicks = 100;
4012 LogFunc(("Timer ticks=%RU64\n", pThis->uTicks));
4013
4014 /* Fire off timer. */
4015 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
4016 }
4017 }
4018
4019# ifdef VBOX_WITH_STATISTICS
4020 if (RT_SUCCESS(rc))
4021 {
4022 /*
4023 * Register statistics.
4024 */
4025 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
4026 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
4027 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
4028 }
4029# endif
4030
4031#endif
4032
4033 LogFlowFuncLeaveRC(rc);
4034 return rc;
4035}
4036
4037/**
4038 * The device registration structure.
4039 */
4040const PDMDEVREG g_DeviceICH6_HDA =
4041{
4042 /* u32Version */
4043 PDM_DEVREG_VERSION,
4044 /* szName */
4045 "hda",
4046 /* szRCMod */
4047 "VBoxDDGC.gc",
4048 /* szR0Mod */
4049 "VBoxDDR0.r0",
4050 /* pszDescription */
4051 "Intel HD Audio Controller",
4052 /* fFlags */
4053 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
4054 /* fClass */
4055 PDM_DEVREG_CLASS_AUDIO,
4056 /* cMaxInstances */
4057 1,
4058 /* cbInstance */
4059 sizeof(HDASTATE),
4060 /* pfnConstruct */
4061 hdaConstruct,
4062 /* pfnDestruct */
4063 hdaDestruct,
4064 /* pfnRelocate */
4065 NULL,
4066 /* pfnMemSetup */
4067 NULL,
4068 /* pfnPowerOn */
4069 NULL,
4070 /* pfnReset */
4071 hdaReset,
4072 /* pfnSuspend */
4073 NULL,
4074 /* pfnResume */
4075 NULL,
4076 /* pfnAttach */
4077 NULL,
4078 /* pfnDetach */
4079 NULL,
4080 /* pfnQueryInterface. */
4081 NULL,
4082 /* pfnInitComplete */
4083 NULL,
4084 /* pfnPowerOff */
4085 NULL,
4086 /* pfnSoftReset */
4087 NULL,
4088 /* u32VersionEnd */
4089 PDM_DEVREG_VERSION
4090};
4091
4092#endif /* IN_RING3 */
4093#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette