VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 56284

Last change on this file since 56284 was 56284, checked in by vboxsync, 9 years ago

s/VMMGC.gc/VMMRC.rc/g s/VBoxDDGC.gc/VBoxDDRC.rc/g s/VBoxDD2GC.gc/VBoxDD2RC.rc/g
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1/* $Id: DevIchHda.cpp 56284 2015-06-09 10:46:34Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2015 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/vmm/pdmaudioifs.h>
27#include <VBox/version.h>
28
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#ifdef IN_RING3
33# include <iprt/uuid.h>
34# include <iprt/string.h>
35# include <iprt/mem.h>
36#endif
37#include <iprt/list.h>
38
39#ifdef LOG_GROUP
40# undef LOG_GROUP
41#endif
42#define LOG_GROUP LOG_GROUP_DEV_AUDIO
43#include <VBox/log.h>
44
45#include "VBoxDD.h"
46
47#include "AudioMixer.h"
48#include "DevIchHdaCodec.h"
49
50/*******************************************************************************
51* Defined Constants And Macros *
52*******************************************************************************/
53//#define HDA_AS_PCI_EXPRESS
54#define VBOX_WITH_INTEL_HDA
55
56#if (defined(DEBUG) && defined(DEBUG_andy))
57/* Enables experimental support for separate mic-in handling.
58 Do not enable this yet for regular builds, as this needs more testing first! */
59# define VBOX_WITH_HDA_MIC_IN
60#endif
61
62#if defined(VBOX_WITH_HP_HDA)
63/* HP Pavilion dv4t-1300 */
64# define HDA_PCI_VENDOR_ID 0x103c
65# define HDA_PCI_DEVICE_ID 0x30f7
66#elif defined(VBOX_WITH_INTEL_HDA)
67/* Intel HDA controller */
68# define HDA_PCI_VENDOR_ID 0x8086
69# define HDA_PCI_DEVICE_ID 0x2668
70#elif defined(VBOX_WITH_NVIDIA_HDA)
71/* nVidia HDA controller */
72# define HDA_PCI_VENDOR_ID 0x10de
73# define HDA_PCI_DEVICE_ID 0x0ac0
74#else
75# error "Please specify your HDA device vendor/device IDs"
76#endif
77
78/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
79 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
80 * is read only except for bit 15 like the HDA spec states.
81 *
82 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
83 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
84#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
85
86#define HDA_NREGS 114
87#define HDA_NREGS_SAVED 112
88
89/**
90 * NB: Register values stored in memory (au32Regs[]) are indexed through
91 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
92 * register descriptors in g_aHdaRegMap[] are indexed through the
93 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
94 *
95 * The au32Regs[] layout is kept unchanged for saved state
96 * compatibility. */
97
98/* Registers */
99#define HDA_REG_IND_NAME(x) HDA_REG_##x
100#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
101#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
102#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
103#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
104#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
105#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
106#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
107
108
109#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
110#define HDA_RMX_GCAP 0
111/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
112 * oss (15:12) - number of output streams supported
113 * iss (11:8) - number of input streams supported
114 * bss (7:3) - number of bidirectional streams supported
115 * bds (2:1) - number of serial data out signals supported
116 * b64sup (0) - 64 bit addressing supported.
117 */
118#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
119 ( (((oss) & 0xF) << 12) \
120 | (((iss) & 0xF) << 8) \
121 | (((bss) & 0x1F) << 3) \
122 | (((bds) & 0x3) << 2) \
123 | ((b64sup) & 1))
124
125#define HDA_REG_VMIN 1 /* 0x02 */
126#define HDA_RMX_VMIN 1
127
128#define HDA_REG_VMAJ 2 /* 0x03 */
129#define HDA_RMX_VMAJ 2
130
131#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
132#define HDA_RMX_OUTPAY 3
133
134#define HDA_REG_INPAY 4 /* 0x06-0x07 */
135#define HDA_RMX_INPAY 4
136
137#define HDA_REG_GCTL 5 /* 0x08-0x0B */
138#define HDA_RMX_GCTL 5
139#define HDA_GCTL_RST_SHIFT 0
140#define HDA_GCTL_FSH_SHIFT 1
141#define HDA_GCTL_UR_SHIFT 8
142
143#define HDA_REG_WAKEEN 6 /* 0x0C */
144#define HDA_RMX_WAKEEN 6
145
146#define HDA_REG_STATESTS 7 /* 0x0E */
147#define HDA_RMX_STATESTS 7
148#define HDA_STATES_SCSF 0x7
149
150#define HDA_REG_GSTS 8 /* 0x10-0x11*/
151#define HDA_RMX_GSTS 8
152#define HDA_GSTS_FSH_SHIFT 1
153
154#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
155#define HDA_RMX_OUTSTRMPAY 112
156
157#define HDA_REG_INSTRMPAY 10 /* 0x1a */
158#define HDA_RMX_INSTRMPAY 113
159
160#define HDA_REG_INTCTL 11 /* 0x20 */
161#define HDA_RMX_INTCTL 9
162#define HDA_INTCTL_GIE_SHIFT 31
163#define HDA_INTCTL_CIE_SHIFT 30
164#define HDA_INTCTL_S0_SHIFT 0
165#define HDA_INTCTL_S1_SHIFT 1
166#define HDA_INTCTL_S2_SHIFT 2
167#define HDA_INTCTL_S3_SHIFT 3
168#define HDA_INTCTL_S4_SHIFT 4
169#define HDA_INTCTL_S5_SHIFT 5
170#define HDA_INTCTL_S6_SHIFT 6
171#define HDA_INTCTL_S7_SHIFT 7
172#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
173
174#define HDA_REG_INTSTS 12 /* 0x24 */
175#define HDA_RMX_INTSTS 10
176#define HDA_INTSTS_GIS_SHIFT 31
177#define HDA_INTSTS_CIS_SHIFT 30
178#define HDA_INTSTS_S0_SHIFT 0
179#define HDA_INTSTS_S1_SHIFT 1
180#define HDA_INTSTS_S2_SHIFT 2
181#define HDA_INTSTS_S3_SHIFT 3
182#define HDA_INTSTS_S4_SHIFT 4
183#define HDA_INTSTS_S5_SHIFT 5
184#define HDA_INTSTS_S6_SHIFT 6
185#define HDA_INTSTS_S7_SHIFT 7
186#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
187
188#define HDA_REG_WALCLK 13 /* 0x24 */
189#define HDA_RMX_WALCLK /* Not defined! */
190
191/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
192 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
193 * the datasheet.
194 */
195#define HDA_REG_SSYNC 14 /* 0x34 */
196#define HDA_RMX_SSYNC 12
197
198#define HDA_REG_CORBLBASE 15 /* 0x40 */
199#define HDA_RMX_CORBLBASE 13
200
201#define HDA_REG_CORBUBASE 16 /* 0x44 */
202#define HDA_RMX_CORBUBASE 14
203
204#define HDA_REG_CORBWP 17 /* 0x48 */
205#define HDA_RMX_CORBWP 15
206
207#define HDA_REG_CORBRP 18 /* 0x4A */
208#define HDA_RMX_CORBRP 16
209#define HDA_CORBRP_RST_SHIFT 15
210#define HDA_CORBRP_WP_SHIFT 0
211#define HDA_CORBRP_WP_MASK 0xFF
212
213#define HDA_REG_CORBCTL 19 /* 0x4C */
214#define HDA_RMX_CORBCTL 17
215#define HDA_CORBCTL_DMA_SHIFT 1
216#define HDA_CORBCTL_CMEIE_SHIFT 0
217
218#define HDA_REG_CORBSTS 20 /* 0x4D */
219#define HDA_RMX_CORBSTS 18
220#define HDA_CORBSTS_CMEI_SHIFT 0
221
222#define HDA_REG_CORBSIZE 21 /* 0x4E */
223#define HDA_RMX_CORBSIZE 19
224#define HDA_CORBSIZE_SZ_CAP 0xF0
225#define HDA_CORBSIZE_SZ 0x3
226/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
227
228#define HDA_REG_RIRBLBASE 22 /* 0x50 */
229#define HDA_RMX_RIRBLBASE 20
230
231#define HDA_REG_RIRBUBASE 23 /* 0x54 */
232#define HDA_RMX_RIRBUBASE 21
233
234#define HDA_REG_RIRBWP 24 /* 0x58 */
235#define HDA_RMX_RIRBWP 22
236#define HDA_RIRBWP_RST_SHIFT 15
237#define HDA_RIRBWP_WP_MASK 0xFF
238
239#define HDA_REG_RINTCNT 25 /* 0x5A */
240#define HDA_RMX_RINTCNT 23
241#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
242
243#define HDA_REG_RIRBCTL 26 /* 0x5C */
244#define HDA_RMX_RIRBCTL 24
245#define HDA_RIRBCTL_RIC_SHIFT 0
246#define HDA_RIRBCTL_DMA_SHIFT 1
247#define HDA_ROI_DMA_SHIFT 2
248
249#define HDA_REG_RIRBSTS 27 /* 0x5D */
250#define HDA_RMX_RIRBSTS 25
251#define HDA_RIRBSTS_RINTFL_SHIFT 0
252#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
253
254#define HDA_REG_RIRBSIZE 28 /* 0x5E */
255#define HDA_RMX_RIRBSIZE 26
256#define HDA_RIRBSIZE_SZ_CAP 0xF0
257#define HDA_RIRBSIZE_SZ 0x3
258
259#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
260#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
261
262
263#define HDA_REG_IC 29 /* 0x60 */
264#define HDA_RMX_IC 27
265
266#define HDA_REG_IR 30 /* 0x64 */
267#define HDA_RMX_IR 28
268
269#define HDA_REG_IRS 31 /* 0x68 */
270#define HDA_RMX_IRS 29
271#define HDA_IRS_ICB_SHIFT 0
272#define HDA_IRS_IRV_SHIFT 1
273
274#define HDA_REG_DPLBASE 32 /* 0x70 */
275#define HDA_RMX_DPLBASE 30
276#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
277
278#define HDA_REG_DPUBASE 33 /* 0x74 */
279#define HDA_RMX_DPUBASE 31
280#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
281#define DPBASE_ENABLED 1
282#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
283
284#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
285#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
286/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
287#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
288
289#define HDA_REG_SD0CTL 34 /* 0x80 */
290#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
291#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
292#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
293#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
294#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
295#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
296#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
297#define HDA_RMX_SD0CTL 32
298#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
299#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
300#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
301#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
302#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
303#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
304#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
305
306#define SD(func, num) SD##num##func
307#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
308#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
309#define HDA_SDCTL_NUM_MASK 0xF
310#define HDA_SDCTL_NUM_SHIFT 20
311#define HDA_SDCTL_DIR_SHIFT 19
312#define HDA_SDCTL_TP_SHIFT 18
313#define HDA_SDCTL_STRIPE_MASK 0x3
314#define HDA_SDCTL_STRIPE_SHIFT 16
315#define HDA_SDCTL_DEIE_SHIFT 4
316#define HDA_SDCTL_FEIE_SHIFT 3
317#define HDA_SDCTL_ICE_SHIFT 2
318#define HDA_SDCTL_RUN_SHIFT 1
319#define HDA_SDCTL_SRST_SHIFT 0
320
321#define HDA_REG_SD0STS 35 /* 0x83 */
322#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
323#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
324#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
325#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
326#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
327#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
328#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
329#define HDA_RMX_SD0STS 33
330#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
331#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
332#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
333#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
334#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
335#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
336#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
337
338#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
339#define HDA_SDSTS_FIFORDY_SHIFT 5
340#define HDA_SDSTS_DE_SHIFT 4
341#define HDA_SDSTS_FE_SHIFT 3
342#define HDA_SDSTS_BCIS_SHIFT 2
343
344#define HDA_REG_SD0LPIB 36 /* 0x84 */
345#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
346#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
347#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
348#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
349#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
350#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
351#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
352#define HDA_RMX_SD0LPIB 34
353#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
354#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
355#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
356#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
357#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
358#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
359#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
360
361#define HDA_REG_SD0CBL 37 /* 0x88 */
362#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
363#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
364#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
365#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
366#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
367#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
368#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
369#define HDA_RMX_SD0CBL 35
370#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
371#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
372#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
373#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
374#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
375#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
376#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
377
378
379#define HDA_REG_SD0LVI 38 /* 0x8C */
380#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
381#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
382#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
383#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
384#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
385#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
386#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
387#define HDA_RMX_SD0LVI 36
388#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
389#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
390#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
391#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
392#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
393#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
394#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
395
396#define HDA_REG_SD0FIFOW 39 /* 0x8E */
397#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
398#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
399#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
400#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
401#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
402#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
403#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
404#define HDA_RMX_SD0FIFOW 37
405#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
406#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
407#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
408#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
409#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
410#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
411#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
412
413/*
414 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
415 */
416#define HDA_SDFIFOW_8B 0x2
417#define HDA_SDFIFOW_16B 0x3
418#define HDA_SDFIFOW_32B 0x4
419
420#define HDA_REG_SD0FIFOS 40 /* 0x90 */
421#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
422#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
423#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
424#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
425#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
426#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
427#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
428#define HDA_RMX_SD0FIFOS 38
429#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
430#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
431#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
432#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
433#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
434#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
435#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
436
437/*
438 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
439 * formula: size - 1
440 * Other values not listed are not supported.
441 */
442#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
443#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
444#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
445#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
446#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
447#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
448#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
449#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
450#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
451
452#define HDA_REG_SD0FMT 41 /* 0x92 */
453#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
454#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
455#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
456#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
457#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
458#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
459#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
460#define HDA_RMX_SD0FMT 39
461#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
462#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
463#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
464#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
465#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
466#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
467#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
468
469#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
470#define HDA_SDFMT_BASE_RATE_SHIFT 14
471#define HDA_SDFMT_MULT_SHIFT 11
472#define HDA_SDFMT_MULT_MASK 0x7
473#define HDA_SDFMT_DIV_SHIFT 8
474#define HDA_SDFMT_DIV_MASK 0x7
475#define HDA_SDFMT_BITS_SHIFT 4
476#define HDA_SDFMT_BITS_MASK 0x7
477#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
478#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
479#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
480
481#define HDA_REG_SD0BDPL 42 /* 0x98 */
482#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
483#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
484#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
485#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
486#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
487#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
488#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
489#define HDA_RMX_SD0BDPL 40
490#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
491#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
492#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
493#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
494#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
495#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
496#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
497
498#define HDA_REG_SD0BDPU 43 /* 0x9C */
499#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
500#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
501#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
502#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
503#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
504#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
505#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
506#define HDA_RMX_SD0BDPU 41
507#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
508#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
509#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
510#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
511#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
512#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
513#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
514
515#define HDA_CODEC_CAD_SHIFT 28
516/* Encodes the (required) LUN into a codec command. */
517#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
518
519
520
521/*******************************************************************************
522* Structures and Typedefs *
523*******************************************************************************/
524typedef struct HDABDLEDESC
525{
526 uint64_t u64BdleCviAddr;
527 uint32_t u32BdleMaxCvi;
528 uint32_t u32BdleCvi;
529 uint32_t u32BdleCviLen;
530 uint32_t u32BdleCviPos;
531 bool fBdleCviIoc;
532 uint32_t cbUnderFifoW;
533 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
534} HDABDLEDESC, *PHDABDLEDESC;
535
536typedef struct HDASTREAMTRANSFERDESC
537{
538 uint64_t u64BaseDMA;
539 uint32_t u32Ctl;
540 uint32_t *pu32Sts;
541 uint8_t u8Strm;
542 uint32_t *pu32Lpib;
543 uint32_t u32Cbl;
544 uint32_t u32Fifos;
545} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
546
547typedef struct HDAINPUTSTREAM
548{
549 /** PCM line input stream. */
550 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
551 /** Mixer handle for line input stream. */
552 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
553} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
554
555typedef struct HDAOUTPUTSTREAM
556{
557 /** PCM output stream. */
558 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
559 /** Mixer handle for line output stream. */
560 R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
561} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
562
563/**
564 * Struct for maintaining a host backend driver.
565 * This driver must be associated to one, and only one,
566 * HDA codec. The HDA controller does the actual multiplexing
567 * of HDA codec data to various host backend drivers then.
568 *
569 * This HDA device uses a timer in order to synchronize all
570 * read/write accesses across all attached LUNs / backends.
571 */
572typedef struct HDADRIVER
573{
574 union
575 {
576 /** Node for storing this driver in our device driver
577 * list of HDASTATE. */
578 RTLISTNODE Node;
579 struct
580 {
581 R3PTRTYPE(void *) dummy1;
582 R3PTRTYPE(void *) dummy2;
583 } dummy;
584 };
585
586 /** Pointer to HDA controller (state). */
587 R3PTRTYPE(PHDASTATE) pHDAState;
588 /** Driver flags. */
589 PDMAUDIODRVFLAGS Flags;
590 uint8_t u32Padding0[3];
591 /** LUN to which this driver has been assigned. */
592 uint8_t uLUN;
593 /** Audio connector interface to the underlying
594 * host backend. */
595 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
596 /** Stream for line input. */
597 HDAINPUTSTREAM LineIn;
598 /** Stream for mic input. */
599 HDAINPUTSTREAM MicIn;
600 /** Stream for output. */
601 HDAOUTPUTSTREAM Out;
602} HDADRIVER, *PHDADRIVER;
603
604/**
605 * ICH Intel HD Audio Controller state.
606 */
607typedef struct HDASTATE
608{
609 /** The PCI device structure. */
610 PCIDevice PciDev;
611 /** R3 Pointer to the device instance. */
612 PPDMDEVINSR3 pDevInsR3;
613 /** R0 Pointer to the device instance. */
614 PPDMDEVINSR0 pDevInsR0;
615 /** R0 Pointer to the device instance. */
616 PPDMDEVINSRC pDevInsRC;
617
618 uint32_t u32Padding;
619
620 /** Pointer to the attached audio driver. */
621 R3PTRTYPE(PPDMIBASE) pDrvBase;
622 /** The base interface for LUN\#0. */
623 PDMIBASE IBase;
624 RTGCPHYS MMIOBaseAddr;
625 uint32_t au32Regs[HDA_NREGS];
626 HDABDLEDESC StInBdle;
627 HDABDLEDESC StOutBdle;
628 HDABDLEDESC StMicBdle;
629 uint64_t u64CORBBase;
630 uint64_t u64RIRBBase;
631 uint64_t u64DPBase;
632 /** Pointer to CORB buffer. */
633 R3PTRTYPE(uint32_t *) pu32CorbBuf;
634 /** Size in bytes of CORB buffer. */
635 uint32_t cbCorbBuf;
636 uint32_t u32Padding2;
637 /** Pointer to RIRB buffer. */
638 R3PTRTYPE(uint64_t *) pu64RirbBuf;
639 /** Size in bytes of RIRB buffer. */
640 uint32_t cbRirbBuf;
641 /** Indicates if HDA is in reset. */
642 bool fInReset;
643 /** Interrupt on completion */
644 bool fCviIoc;
645 /** Flag whether the R0 part is enabled. */
646 bool fR0Enabled;
647 /** Flag whether the RC part is enabled. */
648 bool fRCEnabled;
649 /** The emulation timer for handling the attached
650 * LUN drivers. */
651 PTMTIMERR3 pTimer;
652 /** Timer ticks for handling the LUN drivers. */
653 uint64_t uTicks;
654# ifdef VBOX_WITH_STATISTICS
655 STAMPROFILE StatTimer;
656 STAMCOUNTER StatBytesRead;
657 STAMCOUNTER StatBytesWritten;
658# endif
659 /** Pointer to HDA codec to use. */
660 R3PTRTYPE(PHDACODEC) pCodec;
661 union
662 {
663 /** List of associated LUN drivers. */
664 RTLISTANCHOR lstDrv;
665 struct
666 {
667 R3PTRTYPE(void *) dummy1;
668 R3PTRTYPE(void *) dummy2;
669 } dummy;
670 };
671 /** The device' software mixer. */
672 R3PTRTYPE(PAUDIOMIXER) pMixer;
673 /** Audio sink for PCM output. */
674 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
675 /** Audio mixer sink for line input. */
676 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
677 /** Audio mixer sink for microphone input. */
678 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
679 uint64_t u64BaseTS;
680 /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
681 uint8_t u8Counter;
682 uint8_t au8Padding[7];
683} HDASTATE;
684/** Pointer to the ICH Intel HD Audio Controller state. */
685typedef HDASTATE *PHDASTATE;
686
687#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
688 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
689#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
690 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
691
692
693/*******************************************************************************
694* Internal Functions *
695*******************************************************************************/
696#ifndef VBOX_DEVICE_STRUCT_TESTCASE
697static FNPDMDEVRESET hdaReset;
698
699static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
700static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
701static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
702static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
703static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
704static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
705static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
706static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
707static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
708static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
709static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
710static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
711static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
712static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
713static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
714static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
715static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
716
717static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
718static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
719static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
720static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
721static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
722static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
723static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
724static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
725static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
726static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
727static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
728static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
729static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
730static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
731static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
732static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
733
734static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
735static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail);
736
737#ifdef IN_RING3
738DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
739 PHDASTREAMTRANSFERDESC pStreamDesc);
740static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
741#ifdef LOG_ENABLED
742static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
743#endif
744#endif
745
746
747/*******************************************************************************
748* Global Variables *
749*******************************************************************************/
750
751/* see 302349 p 6.2*/
752static const struct HDAREGDESC
753{
754 /** Register offset in the register space. */
755 uint32_t offset;
756 /** Size in bytes. Registers of size > 4 are in fact tables. */
757 uint32_t size;
758 /** Readable bits. */
759 uint32_t readable;
760 /** Writable bits. */
761 uint32_t writable;
762 /** Read callback. */
763 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
764 /** Write callback. */
765 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
766 /** Index into the register storage array. */
767 uint32_t mem_idx;
768 /** Abbreviated name. */
769 const char *abbrev;
770} g_aHdaRegMap[HDA_NREGS] =
771
772/* Turn a short register name into an memory index and a stringized name. */
773#define RA(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
774/* Same as above for an input stream ('I' prefixed). */
775#define IA(abbrev) HDA_MEM_IND_NAME(abbrev), "I"#abbrev
776/* Same as above for an output stream ('O' prefixed). */
777#define OA(abbrev) HDA_MEM_IND_NAME(abbrev), "O"#abbrev
778/* Same as above for a register *not* stored in memory. */
779#define UA(abbrev) 0, #abbrev
780
781{
782 /* offset size read mask write mask read callback write callback abbrev */
783 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- */
784 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(GCAP) }, /* Global Capabilities */
785 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMIN) }, /* Minor Version */
786 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMAJ) }, /* Major Version */
787 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTPAY) }, /* Output Payload Capabilities */
788 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INPAY) }, /* Input Payload Capabilities */
789 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , RA(GCTL) }, /* Global Control */
790 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , RA(WAKEEN) }, /* Wake Enable */
791 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , RA(STATESTS) }, /* State Change Status */
792 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , RA(GSTS) }, /* Global Status */
793 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTSTRMPAY)}, /* Output Stream Payload Capability */
794 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INSTRMPAY) }, /* Input Stream Payload Capability */
795 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(INTCTL) }, /* Interrupt Control */
796 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , RA(INTSTS) }, /* Interrupt Status */
797 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , UA(WALCLK) }, /* Wall Clock Counter */
798 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
799 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(SSYNC) }, /* Stream Synchronization */
800 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(CORBLBASE) }, /* CORB Lower Base Address */
801 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(CORBUBASE) }, /* CORB Upper Base Address */
802 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , RA(CORBWP) }, /* CORB Write Pointer */
803 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , RA(CORBRP) }, /* CORB Read Pointer */
804 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , RA(CORBCTL) }, /* CORB Control */
805 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , RA(CORBSTS) }, /* CORB Status */
806 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(CORBSIZE) }, /* CORB Size */
807 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBLBASE) }, /* RIRB Lower Base Address */
808 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBUBASE) }, /* RIRB Upper Base Address */
809 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , RA(RIRBWP) }, /* RIRB Write Pointer */
810 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , RA(RINTCNT) }, /* Response Interrupt Count */
811 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , RA(RIRBCTL) }, /* RIRB Control */
812 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , RA(RIRBSTS) }, /* RIRB Status */
813 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(RIRBSIZE) }, /* RIRB Size */
814 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , RA(IC) }, /* Immediate Command */
815 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , RA(IR) }, /* Immediate Response */
816 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , RA(IRS) }, /* Immediate Command Status */
817 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , RA(DPLBASE) }, /* MA Position Lower Base */
818 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(DPUBASE) }, /* DMA Position Upper Base */
819
820 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD0CTL) }, /* Input Stream Descriptor 0 (ICD0) Control */
821 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD0STS) }, /* ISD0 Status */
822 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0LPIB) }, /* ISD0 Link Position In Buffer */
823 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0CBL) }, /* ISD0 Cyclic Buffer Length */
824 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD0LVI) }, /* ISD0 Last Valid Index */
825 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD0FIFOW) }, /* ISD0 FIFO Watermark */
826 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD0FIFOS) }, /* ISD0 FIFO Size */
827 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD0FMT) }, /* ISD0 Format */
828 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD0BDPL) }, /* ISD0 Buffer Descriptor List Pointer-Lower Base Address */
829 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD0BDPU) }, /* ISD0 Buffer Descriptor List Pointer-Upper Base Address */
830
831 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD1CTL) }, /* Input Stream Descriptor 1 (ISD1) Control */
832 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD1STS) }, /* ISD1 Status */
833 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1LPIB) }, /* ISD1 Link Position In Buffer */
834 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1CBL) }, /* ISD1 Cyclic Buffer Length */
835 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD1LVI) }, /* ISD1 Last Valid Index */
836 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD1FIFOW) }, /* ISD1 FIFO Watermark */
837 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD1FIFOS) }, /* ISD1 FIFO Size */
838 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD1FMT) }, /* ISD1 Format */
839 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD1BDPL) }, /* ISD1 Buffer Descriptor List Pointer-Lower Base Address */
840 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD1BDPU) }, /* ISD1 Buffer Descriptor List Pointer-Upper Base Address */
841
842 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD2CTL) }, /* Input Stream Descriptor 2 (ISD2) Control */
843 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD2STS) }, /* ISD2 Status */
844 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2LPIB) }, /* ISD2 Link Position In Buffer */
845 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2CBL) }, /* ISD2 Cyclic Buffer Length */
846 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD2LVI) }, /* ISD2 Last Valid Index */
847 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD2FIFOW) }, /* ISD2 FIFO Watermark */
848 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD2FIFOS) }, /* ISD2 FIFO Size */
849 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD2FMT) }, /* ISD2 Format */
850 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD2BDPL) }, /* ISD2 Buffer Descriptor List Pointer-Lower Base Address */
851 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD2BDPU) }, /* ISD2 Buffer Descriptor List Pointer-Upper Base Address */
852
853 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD3CTL) }, /* Input Stream Descriptor 3 (ISD3) Control */
854 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD3STS) }, /* ISD3 Status */
855 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3LPIB) }, /* ISD3 Link Position In Buffer */
856 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3CBL) }, /* ISD3 Cyclic Buffer Length */
857 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD3LVI) }, /* ISD3 Last Valid Index */
858 { 0x000EE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD3FIFOW) }, /* ISD3 FIFO Watermark */
859 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD3FIFOS) }, /* ISD3 FIFO Size */
860 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD3FMT) }, /* ISD3 Format */
861 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD3BDPL) }, /* ISD3 Buffer Descriptor List Pointer-Lower Base Address */
862 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD3BDPU) }, /* ISD3 Buffer Descriptor List Pointer-Upper Base Address */
863
864 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD4CTL) }, /* Output Stream Descriptor 4 (OSD4) Control */
865 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD4STS) }, /* OSD4 Status */
866 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4LPIB) }, /* OSD4 Link Position In Buffer */
867 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4CBL) }, /* OSD4 Cyclic Buffer Length */
868 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD4LVI) }, /* OSD4 Last Valid Index */
869 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD4FIFOW) }, /* OSD4 FIFO Watermark */
870 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD4FIFOS) }, /* OSD4 FIFO Size */
871 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD4FMT) }, /* OSD4 Format */
872 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD4BDPL) }, /* OSD4 Buffer Descriptor List Pointer-Lower Base Address */
873 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD4BDPU) }, /* OSD4 Buffer Descriptor List Pointer-Upper Base Address */
874
875 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD5CTL) }, /* Output Stream Descriptor 5 (OSD5) Control */
876 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD5STS) }, /* OSD5 Status */
877 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5LPIB) }, /* OSD5 Link Position In Buffer */
878 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5CBL) }, /* OSD5 Cyclic Buffer Length */
879 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD5LVI) }, /* OSD5 Last Valid Index */
880 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD5FIFOW) }, /* OSD5 FIFO Watermark */
881 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD5FIFOS) }, /* OSD5 FIFO Size */
882 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD5FMT) }, /* OSD5 Format */
883 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD5BDPL) }, /* OSD5 Buffer Descriptor List Pointer-Lower Base Address */
884 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD5BDPU) }, /* OSD5 Buffer Descriptor List Pointer-Upper Base Address */
885
886 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD6CTL) }, /* Output Stream Descriptor 6 (OSD6) Control */
887 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD6STS) }, /* OSD6 Status */
888 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6LPIB) }, /* OSD6 Link Position In Buffer */
889 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6CBL) }, /* OSD6 Cyclic Buffer Length */
890 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD6LVI) }, /* OSD6 Last Valid Index */
891 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD6FIFOW) }, /* OSD6 FIFO Watermark */
892 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD6FIFOS) }, /* OSD6 FIFO Size */
893 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD6FMT) }, /* OSD6 Format */
894 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD6BDPL) }, /* OSD6 Buffer Descriptor List Pointer-Lower Base Address */
895 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD6BDPU) }, /* OSD6 Buffer Descriptor List Pointer-Upper Base Address */
896
897 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD7CTL) }, /* Output Stream Descriptor 7 (OSD7) Control */
898 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD7STS) }, /* OSD7 Status */
899 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7LPIB) }, /* OSD7 Link Position In Buffer */
900 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7CBL) }, /* OSD7 Cyclic Buffer Length */
901 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD7LVI) }, /* OSD7 Last Valid Index */
902 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD7FIFOW) }, /* OSD7 FIFO Watermark */
903 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD7FIFOS) }, /* OSD7 FIFO Size */
904 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD7FMT) }, /* OSD7 Format */
905 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD7BDPL) }, /* OSD7 Buffer Descriptor List Pointer-Lower Base Address */
906 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD7BDPU) }, /* OSD7 Buffer Descriptor List Pointer-Upper Base Address */
907};
908
909/**
910 * HDA register aliases (HDA spec 3.3.45).
911 * @remarks Sorted by offReg.
912 */
913static const struct
914{
915 /** The alias register offset. */
916 uint32_t offReg;
917 /** The register index. */
918 int idxAlias;
919} g_aHdaRegAliases[] =
920{
921 { 0x2084, HDA_REG_SD0LPIB },
922 { 0x20a4, HDA_REG_SD1LPIB },
923 { 0x20c4, HDA_REG_SD2LPIB },
924 { 0x20e4, HDA_REG_SD3LPIB },
925 { 0x2104, HDA_REG_SD4LPIB },
926 { 0x2124, HDA_REG_SD5LPIB },
927 { 0x2144, HDA_REG_SD6LPIB },
928 { 0x2164, HDA_REG_SD7LPIB },
929};
930
931#ifdef IN_RING3
932/** HDABDLEDESC field descriptors the v3+ saved state. */
933static SSMFIELD const g_aHdaBDLEDescFields[] =
934{
935 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
936 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
937 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
938 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
939 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
940 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
941 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
942 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
943 SSMFIELD_ENTRY_TERM()
944};
945
946/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
947static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
948{
949 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
950 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
951 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
952 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
953 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
954 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
955 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
956 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
957 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
958 SSMFIELD_ENTRY_TERM()
959};
960#endif
961
962/**
963 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
964 */
965static uint32_t const g_afMasks[5] =
966{
967 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
968};
969
970#ifdef IN_RING3
971DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
972{
973 if (pThis->u64DPBase & DPBASE_ENABLED)
974 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
975 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
976 pStreamDesc->pu32Lpib, sizeof(uint32_t));
977}
978#endif
979
980DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
981{
982#if 0
983 switch(HDA_STREAM_REG(pThis, FIFOW, pStreamDesc->u8Strm))
984 {
985 case HDA_SDFIFOW_8B: return 8;
986 case HDA_SDFIFOW_16B: return 16;
987 case HDA_SDFIFOW_32B: return 32;
988 default:
989 AssertMsgFailed(("unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
990 }
991#endif
992 return 0;
993}
994
995static int hdaProcessInterrupt(PHDASTATE pThis)
996{
997#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
998 ( INTCTL_SX((pThis), num) \
999 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1000 bool fIrq = false;
1001 if ( HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1002 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1003 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1004 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1005 fIrq = true;
1006
1007 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1008 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1009 fIrq = true;
1010
1011 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1012 {
1013 LogFunc(("irq %s\n", fIrq ? "asserted" : "deasserted"));
1014 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1015 }
1016 return VINF_SUCCESS;
1017}
1018
1019/**
1020 * Looks up a register at the exact offset given by @a offReg.
1021 *
1022 * @returns Register index on success, -1 if not found.
1023 * @param pThis The HDA device state.
1024 * @param offReg The register offset.
1025 */
1026static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1027{
1028 /*
1029 * Aliases.
1030 */
1031 if (offReg >= g_aHdaRegAliases[0].offReg)
1032 {
1033 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1034 if (offReg == g_aHdaRegAliases[i].offReg)
1035 return g_aHdaRegAliases[i].idxAlias;
1036 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1037 return -1;
1038 }
1039
1040 /*
1041 * Binary search the
1042 */
1043 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1044 int idxLow = 0;
1045 for (;;)
1046 {
1047 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1048 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1049 {
1050 if (idxLow == idxMiddle)
1051 break;
1052 idxEnd = idxMiddle;
1053 }
1054 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1055 {
1056 idxLow = idxMiddle + 1;
1057 if (idxLow >= idxEnd)
1058 break;
1059 }
1060 else
1061 return idxMiddle;
1062 }
1063
1064#ifdef RT_STRICT
1065 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1066 Assert(g_aHdaRegMap[i].offset != offReg);
1067#endif
1068 return -1;
1069}
1070
1071/**
1072 * Looks up a register covering the offset given by @a offReg.
1073 *
1074 * @returns Register index on success, -1 if not found.
1075 * @param pThis The HDA device state.
1076 * @param offReg The register offset.
1077 */
1078static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1079{
1080 /*
1081 * Aliases.
1082 */
1083 if (offReg >= g_aHdaRegAliases[0].offReg)
1084 {
1085 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1086 {
1087 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1088 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1089 return g_aHdaRegAliases[i].idxAlias;
1090 }
1091 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1092 return -1;
1093 }
1094
1095 /*
1096 * Binary search the
1097 */
1098 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1099 int idxLow = 0;
1100 for (;;)
1101 {
1102 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1103 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1104 {
1105 if (idxLow == idxMiddle)
1106 break;
1107 idxEnd = idxMiddle;
1108 }
1109 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1110 {
1111 idxLow = idxMiddle + 1;
1112 if (idxLow >= idxEnd)
1113 break;
1114 }
1115 else
1116 return idxMiddle;
1117 }
1118
1119#ifdef RT_STRICT
1120 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1121 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1122#endif
1123 return -1;
1124}
1125
1126#ifdef IN_RING3
1127static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1128{
1129 int rc = VINF_SUCCESS;
1130 if (fLocal)
1131 {
1132 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1133 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1134 if (RT_FAILURE(rc))
1135 AssertRCReturn(rc, rc);
1136#ifdef DEBUG_CMD_BUFFER
1137 uint8_t i = 0;
1138 do
1139 {
1140 LogFunc(("corb%02x: ", i));
1141 uint8_t j = 0;
1142 do
1143 {
1144 const char *prefix;
1145 if ((i + j) == HDA_REG(pThis, CORBRP));
1146 prefix = "[R]";
1147 else if ((i + j) == HDA_REG(pThis, CORBWP));
1148 prefix = "[W]";
1149 else
1150 prefix = " "; /* three spaces */
1151 LogFunc(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
1152 j++;
1153 } while (j < 8);
1154 LogFunc(("\n"));
1155 i += 8;
1156 } while(i != 0);
1157#endif
1158 }
1159 else
1160 {
1161 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1162 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1163 if (RT_FAILURE(rc))
1164 AssertRCReturn(rc, rc);
1165#ifdef DEBUG_CMD_BUFFER
1166 uint8_t i = 0;
1167 do {
1168 LogFunc(("rirb%02x: ", i));
1169 uint8_t j = 0;
1170 do {
1171 const char *prefix;
1172 if ((i + j) == HDA_REG(pThis, RIRBWP))
1173 prefix = "[W]";
1174 else
1175 prefix = " ";
1176 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1177 } while (++j < 8);
1178 LogFunc(("\n"));
1179 i += 8;
1180 } while (i != 0);
1181#endif
1182 }
1183 return rc;
1184}
1185
1186static int hdaCORBCmdProcess(PHDASTATE pThis)
1187{
1188 int rc;
1189 uint8_t corbRp;
1190 uint8_t corbWp;
1191 uint8_t rirbWp;
1192
1193 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1194
1195 rc = hdaCmdSync(pThis, true);
1196 if (RT_FAILURE(rc))
1197 AssertRCReturn(rc, rc);
1198 corbRp = HDA_REG(pThis, CORBRP);
1199 corbWp = HDA_REG(pThis, CORBWP);
1200 rirbWp = HDA_REG(pThis, RIRBWP);
1201 Assert((corbWp != corbRp));
1202 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1203 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1204 while (corbRp != corbWp)
1205 {
1206 uint32_t cmd;
1207 uint64_t resp;
1208 pfn = NULL;
1209 corbRp++;
1210 cmd = pThis->pu32CorbBuf[corbRp];
1211
1212 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1213 HDA_CODEC_CMD(cmd, 0 /* Codec index */),
1214 &pfn);
1215 if (RT_SUCCESS(rc))
1216 {
1217 rc = pfn(pThis->pCodec,
1218 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1219 }
1220
1221 if (RT_FAILURE(rc))
1222 AssertRCReturn(rc, rc);
1223 Assert(pfn);
1224 (rirbWp)++;
1225
1226 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1227 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1228 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1229 {
1230 LogFunc(("unexpected unsolicited response.\n"));
1231 HDA_REG(pThis, CORBRP) = corbRp;
1232 return rc;
1233 }
1234 pThis->pu64RirbBuf[rirbWp] = resp;
1235 pThis->u8Counter++;
1236 if (pThis->u8Counter == RINTCNT_N(pThis))
1237 break;
1238 }
1239 HDA_REG(pThis, CORBRP) = corbRp;
1240 HDA_REG(pThis, RIRBWP) = rirbWp;
1241 rc = hdaCmdSync(pThis, false);
1242 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1243 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1244 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1245 {
1246 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1247 pThis->u8Counter = 0;
1248 rc = hdaProcessInterrupt(pThis);
1249 }
1250 if (RT_FAILURE(rc))
1251 AssertRCReturn(rc, rc);
1252 return rc;
1253}
1254#endif
1255
1256static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
1257{
1258 LogFunc(("reset of stream (%d) started\n", u8Strm));
1259 Assert(( pThis
1260 && pBdle
1261 && pStreamDesc
1262 && u8Strm <= 7));
1263 RT_BZERO(pBdle, sizeof(HDABDLEDESC));
1264 *pStreamDesc->pu32Lpib = 0;
1265 *pStreamDesc->pu32Sts = 0;
1266 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1267 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
1268 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1269
1270 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1271 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1272 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
1273 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1274 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1275 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1276 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1277 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1278 LogFunc(("reset of stream (%d) finished\n", u8Strm));
1279}
1280
1281/* Register access handlers. */
1282
1283static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1284{
1285 *pu32Value = 0;
1286 return VINF_SUCCESS;
1287}
1288
1289static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1290{
1291 return VINF_SUCCESS;
1292}
1293
1294/* U8 */
1295static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1296{
1297 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1298 return hdaRegReadU32(pThis, iReg, pu32Value);
1299}
1300
1301static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1302{
1303 Assert((u32Value & 0xffffff00) == 0);
1304 return hdaRegWriteU32(pThis, iReg, u32Value);
1305}
1306
1307/* U16 */
1308static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1309{
1310 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1311 return hdaRegReadU32(pThis, iReg, pu32Value);
1312}
1313
1314static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1315{
1316 Assert((u32Value & 0xffff0000) == 0);
1317 return hdaRegWriteU32(pThis, iReg, u32Value);
1318}
1319
1320/* U24 */
1321static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1322{
1323 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1324 return hdaRegReadU32(pThis, iReg, pu32Value);
1325}
1326
1327static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1328{
1329 Assert((u32Value & 0xff000000) == 0);
1330 return hdaRegWriteU32(pThis, iReg, u32Value);
1331}
1332
1333/* U32 */
1334static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1335{
1336 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1337
1338 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1339 return VINF_SUCCESS;
1340}
1341
1342static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1343{
1344 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1345
1346 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1347 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1348 return VINF_SUCCESS;
1349}
1350
1351static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1352{
1353 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1354 {
1355 /* exit reset state */
1356 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1357 pThis->fInReset = false;
1358 }
1359 else
1360 {
1361#ifdef IN_RING3
1362 /* enter reset state*/
1363 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1364 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1365 {
1366 LogFunc(("HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1367 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1368 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1369 }
1370 hdaReset(pThis->CTX_SUFF(pDevIns));
1371 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1372 pThis->fInReset = true;
1373#else
1374 return VINF_IOM_R3_MMIO_WRITE;
1375#endif
1376 }
1377 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1378 {
1379 /* Flush: GSTS:1 set, see 6.2.6*/
1380 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1381 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1382 }
1383 return VINF_SUCCESS;
1384}
1385
1386static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1387{
1388 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1389
1390 uint32_t v = pThis->au32Regs[iRegMem];
1391 uint32_t nv = u32Value & HDA_STATES_SCSF;
1392 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1393 return VINF_SUCCESS;
1394}
1395
1396static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1397{
1398 uint32_t v = 0;
1399 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1400 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1401 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1402 || HDA_REG(pThis, STATESTS))
1403 v |= RT_BIT(30);
1404#define HDA_IS_STREAM_EVENT(pThis, stream) \
1405 ( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1406 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1407 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1408#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
1409 MARK_STREAM(pThis, 0, v);
1410 MARK_STREAM(pThis, 1, v);
1411 MARK_STREAM(pThis, 2, v);
1412 MARK_STREAM(pThis, 3, v);
1413 MARK_STREAM(pThis, 4, v);
1414 MARK_STREAM(pThis, 5, v);
1415 MARK_STREAM(pThis, 6, v);
1416 MARK_STREAM(pThis, 7, v);
1417 v |= v ? RT_BIT(31) : 0;
1418 *pu32Value = v;
1419 return VINF_SUCCESS;
1420}
1421
1422static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1423{
1424 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1425 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1426 - pThis->u64BaseTS, 24, 1000);
1427 return VINF_SUCCESS;
1428}
1429
1430static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1431{
1432 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1433 HDA_REG(pThis, CORBRP) = 0;
1434#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1435 else
1436 return hdaRegWriteU8(pThis, iReg, u32Value);
1437#endif
1438 return VINF_SUCCESS;
1439}
1440
1441static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1442{
1443#ifdef IN_RING3
1444 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1445 AssertRC(rc);
1446 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1447 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1448 return hdaCORBCmdProcess(pThis);
1449 return rc;
1450#else
1451 return VINF_IOM_R3_MMIO_WRITE;
1452#endif
1453}
1454
1455static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1456{
1457 uint32_t v = HDA_REG(pThis, CORBSTS);
1458 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1459 return VINF_SUCCESS;
1460}
1461
1462static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1463{
1464#ifdef IN_RING3
1465 int rc;
1466 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1467 if (RT_FAILURE(rc))
1468 AssertRCReturn(rc, rc);
1469 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1470 return VINF_SUCCESS;
1471 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1472 return VINF_SUCCESS;
1473 rc = hdaCORBCmdProcess(pThis);
1474 return rc;
1475#else
1476 return VINF_IOM_R3_MMIO_WRITE;
1477#endif
1478}
1479
1480static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1481{
1482 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1483 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1484 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1485 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1486
1487 if (fInReset)
1488 {
1489 /*
1490 * Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1491 * from reset
1492 */
1493 Assert((!fReset));
1494 LogFunc(("guest initiated exit of stream reset.\n"));
1495 }
1496 else if (fReset)
1497 {
1498#ifdef IN_RING3
1499 /*
1500 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1501 */
1502 uint8_t u8Strm = 0;
1503 PHDABDLEDESC pBdle = NULL;
1504 HDASTREAMTRANSFERDESC StreamDesc;
1505 Assert((!fInRun && !fRun));
1506 switch (iReg)
1507 {
1508 case HDA_REG_SD0CTL:
1509 u8Strm = 0;
1510 pBdle = &pThis->StInBdle;
1511 break;
1512#ifdef VBOX_WITH_HDA_MIC_IN
1513 case HDA_REG_SD2CTL:
1514 u8Strm = 2;
1515 pBdle = &pThis->StMicBdle;
1516 break;
1517#endif
1518 case HDA_REG_SD4CTL:
1519 u8Strm = 4;
1520 pBdle = &pThis->StOutBdle;
1521 break;
1522 default:
1523 LogFunc(("changing SRST bit on non-attached stream\n"));
1524 return hdaRegWriteU24(pThis, iReg, u32Value);
1525 }
1526 LogFunc(("guest initiated enter to stream reset.\n"));
1527 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1528 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
1529#else
1530 return VINF_IOM_R3_MMIO_WRITE;
1531#endif
1532 }
1533 else
1534 {
1535#ifdef IN_RING3
1536 /* we enter here to change DMA states only */
1537 if ( (fInRun && !fRun)
1538 || (fRun && !fInRun))
1539 {
1540 Assert((!fReset && !fInReset));
1541
1542 PHDADRIVER pDrv;
1543 switch (iReg)
1544 {
1545 case HDA_REG_SD0CTL:
1546 {
1547 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1548 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1549 pDrv->LineIn.pStrmIn, fRun);
1550 break;
1551 }
1552# ifdef VBOX_WITH_HDA_MIC_IN
1553 case HDA_REG_SD2CTL:
1554 {
1555 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1556 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1557 pDrv->MicIn.pStrmIn, fRun);
1558 break;
1559 }
1560# endif
1561 case HDA_REG_SD4CTL:
1562 {
1563 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1564 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1565 pDrv->Out.pStrmOut, fRun);
1566 break;
1567 }
1568 default:
1569 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1570 break;
1571 }
1572 }
1573#else /* !IN_RING3 */
1574 return VINF_IOM_R3_MMIO_WRITE;
1575#endif /* IN_RING3 */
1576 }
1577
1578 return hdaRegWriteU24(pThis, iReg, u32Value);
1579}
1580
1581static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1582{
1583 uint32_t v = HDA_REG_IND(pThis, iReg);
1584 v &= ~(u32Value & v);
1585 HDA_REG_IND(pThis, iReg) = v;
1586 hdaProcessInterrupt(pThis);
1587 return VINF_SUCCESS;
1588}
1589
1590static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1591{
1592 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1593 if (RT_FAILURE(rc))
1594 AssertRCReturn(rc, VINF_SUCCESS);
1595 return rc;
1596}
1597
1598static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1599{
1600 switch (u32Value)
1601 {
1602 case HDA_SDFIFOW_8B:
1603 case HDA_SDFIFOW_16B:
1604 case HDA_SDFIFOW_32B:
1605 return hdaRegWriteU16(pThis, iReg, u32Value);
1606 default:
1607 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1608 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1609 }
1610 return VINF_SUCCESS;
1611}
1612
1613/**
1614 * @note This method could be called for changing value on Output Streams
1615 * only (ICH6 datasheet 18.2.39)
1616 */
1617static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1618{
1619 switch (iReg)
1620 {
1621 /* SDInFIFOS is RO, n=0-3 */
1622 case HDA_REG_SD0FIFOS:
1623 case HDA_REG_SD1FIFOS:
1624 case HDA_REG_SD2FIFOS:
1625 case HDA_REG_SD3FIFOS:
1626 LogFunc(("Guest tries change value of FIFO size of input stream\n"));
1627 break;
1628 case HDA_REG_SD4FIFOS:
1629 case HDA_REG_SD5FIFOS:
1630 case HDA_REG_SD6FIFOS:
1631 case HDA_REG_SD7FIFOS:
1632 switch(u32Value)
1633 {
1634 case HDA_SDONFIFO_16B:
1635 case HDA_SDONFIFO_32B:
1636 case HDA_SDONFIFO_64B:
1637 case HDA_SDONFIFO_128B:
1638 case HDA_SDONFIFO_192B:
1639 return hdaRegWriteU16(pThis, iReg, u32Value);
1640
1641 case HDA_SDONFIFO_256B:
1642 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1643 default:
1644 return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);
1645 }
1646 break;
1647 default:
1648 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
1649 }
1650
1651 return VINF_SUCCESS;
1652}
1653
1654#ifdef IN_RING3
1655static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
1656{
1657 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1658
1659# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1660
1661 int rc = VINF_SUCCESS;
1662
1663 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1664 uint32_t u32HzMult = 1;
1665 uint32_t u32HzDiv = 1;
1666
1667 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
1668 {
1669 case 0: u32HzMult = 1; break;
1670 case 1: u32HzMult = 2; break;
1671 case 2: u32HzMult = 3; break;
1672 case 3: u32HzMult = 4; break;
1673 default:
1674 LogFunc(("Unsupported multiplier %x\n",
1675 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
1676 rc = VERR_NOT_SUPPORTED;
1677 break;
1678 }
1679 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
1680 {
1681 case 0: u32HzDiv = 1; break;
1682 case 1: u32HzDiv = 2; break;
1683 case 2: u32HzDiv = 3; break;
1684 case 3: u32HzDiv = 4; break;
1685 case 4: u32HzDiv = 5; break;
1686 case 5: u32HzDiv = 6; break;
1687 case 6: u32HzDiv = 7; break;
1688 case 7: u32HzDiv = 8; break;
1689 default:
1690 LogFunc(("Unsupported divisor %x\n",
1691 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
1692 rc = VERR_NOT_SUPPORTED;
1693 break;
1694 }
1695
1696 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1697 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
1698 {
1699 case 0:
1700 LogFunc(("Requested 8-bit\n"));
1701 enmFmt = AUD_FMT_S8;
1702 break;
1703 case 1:
1704 LogFunc(("Requested 16-bit\n"));
1705 enmFmt = AUD_FMT_S16;
1706 break;
1707 case 2:
1708 LogFunc(("Requested 20-bit\n"));
1709 break;
1710 case 3:
1711 LogFunc(("Requested 24-bit\n"));
1712 break;
1713 case 4:
1714 LogFunc(("Requested 32-bit\n"));
1715 enmFmt = AUD_FMT_S32;
1716 break;
1717 default:
1718 AssertMsgFailed(("Unsupported bits shift %x\n",
1719 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
1720 rc = VERR_NOT_SUPPORTED;
1721 break;
1722 }
1723
1724 if (RT_SUCCESS(rc))
1725 {
1726 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
1727 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
1728 pCfg->enmFormat = enmFmt;
1729 pCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
1730 }
1731
1732# undef EXTRACT_VALUE
1733
1734 return rc;
1735}
1736#endif
1737
1738static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1739{
1740#ifdef IN_RING3
1741# ifdef VBOX_WITH_HDA_CODEC_EMU
1742 /* No reason to reopen voice with same settings. */
1743 if (u32Value == HDA_REG_IND(pThis, iReg))
1744 return VINF_SUCCESS;
1745
1746 PDMAUDIOSTREAMCFG as;
1747 int rc = hdaSdFmtToAudSettings(u32Value, &as);
1748 if (RT_FAILURE(rc))
1749 return rc;
1750
1751 PHDADRIVER pDrv;
1752 switch (iReg)
1753 {
1754 case HDA_REG_SD0FMT:
1755 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1756 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &as);
1757 break;
1758# ifdef VBOX_WITH_HDA_MIC_IN
1759 case HDA_REG_SD2FMT:
1760 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1761 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &as);
1762 break;
1763# endif
1764 default:
1765 LogFunc(("Warning: Attempt to change format on register %d\n", iReg));
1766 break;
1767 }
1768
1769 /** @todo r=andy rc gets lost; needs fixing. */
1770 return hdaRegWriteU16(pThis, iReg, u32Value);
1771# else /* !VBOX_WITH_HDA_CODEC_EMU */
1772 return hdaRegWriteU16(pThis, iReg, u32Value);
1773# endif
1774#else /* !IN_RING3 */
1775 return VINF_IOM_R3_MMIO_WRITE;
1776#endif
1777}
1778
1779static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1780{
1781 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1782 if (RT_FAILURE(rc))
1783 AssertRCReturn(rc, VINF_SUCCESS);
1784 return rc;
1785}
1786
1787static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1788{
1789 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1790 if (RT_FAILURE(rc))
1791 AssertRCReturn(rc, VINF_SUCCESS);
1792 return rc;
1793}
1794
1795static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1796{
1797 int rc = VINF_SUCCESS;
1798 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1799 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1800 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1801 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1802
1803 rc = hdaRegReadU32(pThis, iReg, pu32Value);
1804 return rc;
1805}
1806
1807static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1808{
1809 int rc = VINF_SUCCESS;
1810
1811 /*
1812 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1813 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1814 */
1815 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1816 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
1817 {
1818#ifdef IN_RING3
1819 PFNHDACODECVERBPROCESSOR pfn = NULL;
1820 uint64_t resp;
1821 uint32_t cmd = HDA_REG(pThis, IC);
1822 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
1823 {
1824 /*
1825 * 3.4.3 defines behavior of immediate Command status register.
1826 */
1827 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
1828 return rc;
1829 }
1830 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1831 LogFunc(("IC:%x\n", cmd));
1832
1833 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1834 HDA_CODEC_CMD(cmd, 0 /* LUN */),
1835 &pfn);
1836 if (RT_FAILURE(rc))
1837 AssertRCReturn(rc, rc);
1838 rc = pfn(pThis->pCodec,
1839 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1840 if (RT_FAILURE(rc))
1841 AssertRCReturn(rc, rc);
1842
1843 HDA_REG(pThis, IR) = (uint32_t)resp;
1844 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
1845 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1846 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1847#else /* !IN_RING3 */
1848 rc = VINF_IOM_R3_MMIO_WRITE;
1849#endif
1850 return rc;
1851 }
1852 /*
1853 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1854 */
1855 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1856 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
1857 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1858 return rc;
1859}
1860
1861static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1862{
1863 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1864 {
1865 HDA_REG(pThis, RIRBWP) = 0;
1866 }
1867 /* The remaining bits are O, see 6.2.22 */
1868 return VINF_SUCCESS;
1869}
1870
1871static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1872{
1873 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1874 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1875 if (RT_FAILURE(rc))
1876 AssertRCReturn(rc, rc);
1877
1878 switch(iReg)
1879 {
1880 case HDA_REG_CORBLBASE:
1881 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
1882 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
1883 break;
1884 case HDA_REG_CORBUBASE:
1885 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
1886 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1887 break;
1888 case HDA_REG_RIRBLBASE:
1889 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
1890 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
1891 break;
1892 case HDA_REG_RIRBUBASE:
1893 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
1894 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1895 break;
1896 case HDA_REG_DPLBASE:
1897 /** @todo: first bit has special meaning */
1898 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
1899 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
1900 break;
1901 case HDA_REG_DPUBASE:
1902 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
1903 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1904 break;
1905 default:
1906 AssertMsgFailed(("Invalid index"));
1907 break;
1908 }
1909
1910 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
1911 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
1912 return rc;
1913}
1914
1915static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1916{
1917 uint8_t v = HDA_REG(pThis, RIRBSTS);
1918 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
1919
1920 return hdaProcessInterrupt(pThis);
1921}
1922
1923#ifdef IN_RING3
1924#ifdef LOG_ENABLED
1925static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1926{
1927#if 0
1928 uint64_t addr;
1929 uint32_t len;
1930 uint32_t ioc;
1931 uint8_t bdle[16];
1932 uint32_t counter;
1933 uint32_t i;
1934 uint32_t sum = 0;
1935 Assert(pBdle && pBdle->u32BdleMaxCvi);
1936 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1937 {
1938 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i*16, bdle, 16);
1939 addr = *(uint64_t *)bdle;
1940 len = *(uint32_t *)&bdle[8];
1941 ioc = *(uint32_t *)&bdle[12];
1942 LogFunc(("%s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1943 sum += len;
1944 }
1945 LogFunc(("sum: %d\n", sum));
1946 for (i = 0; i < 8; ++i)
1947 {
1948 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1949 LogFunc(("%s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
1950 i , counter));
1951 }
1952#endif
1953}
1954#endif
1955
1956static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1957{
1958 uint8_t bdle[16];
1959 Assert(( pStreamDesc->u64BaseDMA
1960 && pBdle
1961 && pBdle->u32BdleMaxCvi));
1962 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1963 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1964 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1965 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1966#ifdef LOG_ENABLED
1967 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
1968#endif
1969}
1970
1971DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1972 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1973{
1974 /*
1975 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
1976 */
1977 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1978 uint32_t cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1979 /*
1980 * we may increase the counter in range of [0, FIFOS + 1]
1981 */
1982 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1983 Assert((u32SoundBackendBufferBytesAvail > 0));
1984
1985 /* sanity check to avoid overriding the backend audio buffer */
1986 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1987 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1988
1989 if (cb2Copy <= pBdle->cbUnderFifoW)
1990 return 0;
1991 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
1992 return cb2Copy;
1993}
1994
1995DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1996 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1997{
1998 LogFunc(("cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1999 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2000 Assert((cbCopied));
2001 AssertPtr(pu32DMACursor);
2002 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
2003 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
2004 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2005 * where it might happen.
2006 */
2007 AssertMsg((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy), /* we assume that we write the entire buffer including unreported bytes */
2008 ("cbCopied=%RU32 != pBdle->cbUnderFifoW=%RU32 + cbArranged2Copy=%RU32\n",
2009 cbCopied, pBdle->cbUnderFifoW, cbArranged2Copy));
2010 if ( pBdle->cbUnderFifoW
2011 && pBdle->cbUnderFifoW <= cbCopied)
2012 {
2013 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n",
2014 pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2015 }
2016
2017 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
2018 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
2019
2020 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
2021 pBdle->u32BdleCviPos += cbArranged2Copy;
2022
2023 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
2024 /* We report all bytes (including previously unreported bytes) */
2025 *pu32DMACursor += cbCopied;
2026 /* Decrease the backend counter by the number of bytes we copied to the backend */
2027 *pu32BackendBufferCapacity -= cbCopied;
2028 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2029 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
2030}
2031
2032DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2033 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2034{
2035 Assert((cbCopied, cbArranged2Copy));
2036 *pu32BackendBufferCapacity -= cbCopied;
2037 pBdle->u32BdleCviPos += cbCopied;
2038 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2039 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
2040 pBdle->cbUnderFifoW = 0;
2041 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2042 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2043}
2044
2045DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2046 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
2047{
2048 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2049 pBdle->u32BdleCviPos += cbCopied;
2050 pBdle->cbUnderFifoW += cbCopied;
2051 /* In case of a read transaction we're always copying from the backend buffer */
2052 if (pu32BackendBufferCapacity)
2053 *pu32BackendBufferCapacity -= cbCopied;
2054 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2055 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
2056}
2057
2058DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2059{
2060 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
2061 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
2062
2063 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2064
2065 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2066 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
2067 hdaUpdatePosBuf(pThis, pStreamDesc);
2068
2069 /* don't touch BdleCvi counter on uninitialized descriptor */
2070 if ( pBdle->u32BdleCviPos
2071 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
2072 {
2073 pBdle->u32BdleCviPos = 0;
2074 pBdle->u32BdleCvi++;
2075 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
2076 pBdle->u32BdleCvi = 0;
2077 }
2078 return fOnBufferEdge;
2079}
2080
2081DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2082 uint32_t cbInc)
2083{
2084 /*
2085 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
2086 * (ICH6 datasheet 18.2.38)
2087 */
2088 if (!pBdle->cbUnderFifoW)
2089 {
2090 *pStreamDesc->pu32Lpib += cbInc;
2091
2092 /*
2093 * Assert. The buffer counters should never overlap.
2094 */
2095 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2096
2097 hdaUpdatePosBuf(pThis, pStreamDesc);
2098 }
2099}
2100
2101static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2102{
2103 bool fDoNextTransferLoop = true;
2104 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
2105 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2106 {
2107 if ( !pBdle->cbUnderFifoW
2108 && pBdle->fBdleCviIoc)
2109 {
2110 /**
2111 * @todo - more carefully investigate BCIS flag.
2112 * Speech synthesis works fine on Mac Guest if this bit isn't set
2113 * but in general sound quality gets worse.
2114 */
2115 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2116
2117 /*
2118 * we should generate the interrupt if ICE bit of SDCTL register is set.
2119 */
2120 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2121 hdaProcessInterrupt(pThis);
2122 }
2123 fDoNextTransferLoop = false;
2124 }
2125 return fDoNextTransferLoop;
2126}
2127
2128/**
2129 * hdaReadAudio - copies samples from audio backend to DMA.
2130 * Note: This function writes to the DMA buffer immediately,
2131 * but "reports bytes" when all conditions are met (FIFOW).
2132 */
2133static int hdaReadAudio(PHDASTATE pThis, PAUDMIXSINK pSink,
2134 PHDASTREAMTRANSFERDESC pStreamDesc,
2135 uint32_t u32CblLimit, uint32_t *pcbAvail, uint32_t *pcbRead)
2136{
2137 PHDABDLEDESC pBdle = &pThis->StInBdle; /** @todo Add support for mic in. */
2138
2139 int rc;
2140 uint32_t cbTransferred = 0;
2141
2142 LogFlowFunc(("CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2143
2144 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2145 if (!cb2Copy)
2146 {
2147 /* If we enter here we can't report "unreported bits". */
2148 rc = VERR_NO_DATA;
2149 }
2150 else
2151 {
2152 uint32_t cbRead = 0;
2153 rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pBdle->au8HdaBuffer, cb2Copy, &cbRead);
2154 if (RT_SUCCESS(rc))
2155 {
2156 Assert(cbRead);
2157
2158 /*
2159 * Write the HDA DMA buffer.
2160 */
2161 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2162 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2163 pBdle->au8HdaBuffer, cbRead);
2164
2165 /* Don't see any reason why cb2Copy would differ from cbRead. */
2166 Assert((cbRead == cb2Copy && (*pcbAvail) >= cb2Copy)); /* sanity */
2167
2168 if (pBdle->cbUnderFifoW + cbRead > hdaFifoWToSz(pThis, 0))
2169 hdaBackendReadTransferReported(pBdle, cb2Copy, cbRead, &cbTransferred, pcbAvail);
2170 else
2171 {
2172 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbRead, pcbAvail);
2173 rc = VERR_NO_DATA;
2174 }
2175 }
2176 }
2177
2178 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2179 LogFunc(("CVI(pos:%RU32, len:%RU32), cbTransferred=%RU32, rc=%Rrc\n",
2180 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2181
2182 if (RT_SUCCESS(rc))
2183 *pcbRead = cbTransferred;
2184
2185 return rc;
2186}
2187
2188static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32CblLimit,
2189 uint32_t *pcbAvail, uint32_t *pcbWritten)
2190{
2191 PHDABDLEDESC pBdle = &pThis->StOutBdle;
2192
2193 int rc = VINF_SUCCESS;
2194
2195 uint32_t cbTransferred = 0;
2196 uint32_t cbWrittenMin = 0; /* local byte counter, how many bytes copied to backend */
2197
2198 LogFunc(("CVI(cvi:%RU32, pos:%RU32, len:%RU32)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2199
2200 /* Local byte counter (on local buffer). */
2201 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2202
2203 /*
2204 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
2205 * previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
2206 */
2207 if (!cb2Copy)
2208 {
2209 rc = VINF_EOF;
2210 }
2211 else
2212 {
2213 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2214 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2215 pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
2216
2217#ifdef VBOX_WITH_STATISTICS
2218 STAM_COUNTER_ADD(&pThis->StatBytesRead, cb2Copy);
2219#endif
2220
2221 /*
2222 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2223 */
2224 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
2225 {
2226 uint32_t cbWritten;
2227 cbWrittenMin = UINT32_MAX;
2228
2229 PHDADRIVER pDrv;
2230 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2231 {
2232 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2233 {
2234 int rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2235 pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW,
2236 &cbWritten);
2237 if (RT_FAILURE(rc2))
2238 continue;
2239 }
2240 else /* Stream disabled, just assume all was copied. */
2241 cbWritten = cb2Copy;
2242
2243 cbWrittenMin = RT_MIN(cbWrittenMin, cbWritten);
2244 LogFlowFunc(("\tLUN#%RU8: cbWritten=%RU32, cWrittenMin=%RU32\n", pDrv->uLUN, cbWritten, cbWrittenMin));
2245 }
2246
2247 if (cbWrittenMin == UINT32_MAX)
2248 cbWrittenMin = 0;
2249
2250 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbWrittenMin, &cbTransferred, pcbAvail);
2251 }
2252 else
2253 {
2254 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2255 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
2256 rc = VINF_EOF;
2257 }
2258 }
2259
2260 Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
2261 LogFunc(("CVI(pos:%RU32, len:%RU32, cbTransferred:%RU32), rc=%Rrc\n",
2262 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2263
2264 if (RT_SUCCESS(rc))
2265 *pcbWritten = cbTransferred;
2266
2267 return rc;
2268}
2269
2270/**
2271 * @interface_method_impl{HDACODEC,pfnReset}
2272 */
2273DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2274{
2275 PHDASTATE pThis = pCodec->pHDAState;
2276 NOREF(pThis);
2277 return VINF_SUCCESS;
2278}
2279
2280DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
2281 PHDASTREAMTRANSFERDESC pStreamDesc)
2282{
2283 Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
2284
2285 RT_BZERO(pStreamDesc, sizeof(HDASTREAMTRANSFERDESC));
2286 pStreamDesc->u8Strm = u8Strm;
2287 pStreamDesc->u32Ctl = HDA_STREAM_REG(pThis, CTL, u8Strm);
2288 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2289 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2290 pStreamDesc->pu32Lpib = &HDA_STREAM_REG(pThis, LPIB, u8Strm);
2291 pStreamDesc->pu32Sts = &HDA_STREAM_REG(pThis, STS, u8Strm);
2292 pStreamDesc->u32Cbl = HDA_STREAM_REG(pThis, CBL, u8Strm);
2293 pStreamDesc->u32Fifos = HDA_STREAM_REG(pThis, FIFOS, u8Strm);
2294
2295 pBdle->u32BdleMaxCvi = HDA_STREAM_REG(pThis, LVI, u8Strm);
2296
2297#ifdef LOG_ENABLED
2298 if ( pBdle
2299 && pBdle->u32BdleMaxCvi)
2300 {
2301 LogFunc(("Initialization of transfer descriptor:\n"));
2302 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2303 }
2304#endif
2305}
2306
2307static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2308{
2309 NOREF(pThis);
2310 NOREF(enmRecSource);
2311 LogFlowFuncEnter();
2312}
2313
2314static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2315{
2316 NOREF(pThis);
2317 LogFlowFuncEnter();
2318}
2319
2320static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2321 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2322 PPDMAUDIOSTREAMCFG pCfg)
2323{
2324 PAUDMIXSINK pSink;
2325
2326 switch (enmRecSource)
2327 {
2328# ifdef VBOX_WITH_HDA_MIC_IN
2329 case PDMAUDIORECSOURCE_MIC:
2330 pSink = pThis->pSinkMicIn;
2331 break;
2332# endif
2333 case PDMAUDIORECSOURCE_LINE_IN:
2334 pSink = pThis->pSinkLineIn;
2335 break;
2336 default:
2337 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2338 return VERR_NOT_SUPPORTED;
2339 }
2340
2341 int rc = VINF_SUCCESS;
2342 char *pszDesc;
2343
2344 PHDADRIVER pDrv;
2345 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2346 {
2347 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2348 {
2349 rc = VERR_NO_MEMORY;
2350 break;
2351 }
2352
2353 rc = pDrv->pConnector->pfnOpenIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2354 LogFlowFunc(("LUN#%RU8: Opened input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2355 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2356 {
2357 AudioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2358 rc = AudioMixerAddStreamIn(pSink,
2359 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2360 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2361 }
2362
2363 RTStrFree(pszDesc);
2364 }
2365
2366 LogFlowFuncLeaveRC(rc);
2367 return rc;
2368}
2369
2370static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2371 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2372{
2373 int rc = VINF_SUCCESS;
2374 char *pszDesc;
2375
2376 PHDADRIVER pDrv;
2377 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2378 {
2379 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2380 {
2381 rc = VERR_NO_MEMORY;
2382 break;
2383 }
2384
2385 rc = pDrv->pConnector->pfnOpenOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
2386 LogFlowFunc(("LUN#%RU8: Opened output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2387 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2388 {
2389 AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
2390 rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
2391 pDrv->pConnector, pDrv->Out.pStrmOut,
2392 0 /* uFlags */, &pDrv->Out.phStrmOut);
2393 }
2394
2395 RTStrFree(pszDesc);
2396 }
2397
2398 LogFlowFuncLeaveRC(rc);
2399 return rc;
2400}
2401
2402static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis, ENMSOUNDSOURCE enmSource,
2403 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2404{
2405 int rc = VINF_SUCCESS;
2406 PDMAUDIOVOLUME vol = { fMute, uVolLeft, uVolRight };
2407 PAUDMIXSINK pSink;
2408
2409 /* Convert the audio source to corresponding sink. */
2410 switch (enmSource) {
2411 case PO_INDEX:
2412 pSink = pThis->pSinkOutput;
2413 break;
2414 case PI_INDEX:
2415 pSink = pThis->pSinkLineIn;
2416 break;
2417 case MC_INDEX:
2418 pSink = pThis->pSinkMicIn;
2419 break;
2420 default:
2421 AssertFailedReturn(VERR_INVALID_PARAMETER);
2422 }
2423
2424 /* Set the volume. Codec already converted it to the correct range. */
2425 AudioMixerSetSinkVolume(pSink, &vol);
2426
2427 LogFlowFuncLeaveRC(rc);
2428 return rc;
2429}
2430
2431static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2432{
2433 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2434 AssertPtr(pThis);
2435
2436 STAM_PROFILE_START(&pThis->StatTimer, a);
2437
2438 int rc = VINF_SUCCESS;
2439
2440 uint32_t cbInMax = 0;
2441 uint32_t cbOutMin = UINT32_MAX;
2442
2443 PHDADRIVER pDrv;
2444
2445 uint32_t cbIn, cbOut, cSamplesLive;
2446 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2447 {
2448 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2449 &cbIn, &cbOut, &cSamplesLive);
2450 if (RT_SUCCESS(rc))
2451 {
2452#ifdef DEBUG_TIMER
2453 LogFlowFunc(("\tLUN#%RU8: [1] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2454#endif
2455 if (cSamplesLive)
2456 {
2457 uint32_t cSamplesPlayed;
2458 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2459 if (RT_SUCCESS(rc2))
2460 LogFlowFunc(("LUN#%RU8: cSamplesLive=%RU32, cSamplesPlayed=%RU32\n",
2461 pDrv->uLUN, cSamplesLive, cSamplesPlayed));
2462
2463 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2464 &cbIn, &cbOut, &cSamplesLive);
2465#ifdef DEBUG_TIMER
2466 if (RT_SUCCESS(rc))
2467 LogFlowFunc(("\tLUN#%RU8: [2] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2468#endif
2469 }
2470
2471 cbInMax = RT_MAX(cbInMax, cbIn);
2472 cbOutMin = RT_MIN(cbOutMin, cbOut);
2473 }
2474 }
2475
2476#ifdef DEBUG_TIMER
2477 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
2478#endif
2479
2480 if (cbOutMin == UINT32_MAX)
2481 cbOutMin = 0;
2482
2483 /*
2484 * Playback.
2485 */
2486 if (cbOutMin)
2487 {
2488 Assert(cbOutMin != UINT32_MAX);
2489 hdaTransfer(pThis, PO_INDEX, cbOutMin); /** @todo Add rc! */
2490 }
2491
2492 /*
2493 * Recording.
2494 */
2495 if (cbInMax)
2496 hdaTransfer(pThis, PI_INDEX, cbInMax); /** @todo Add rc! */
2497
2498 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
2499
2500 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2501}
2502
2503static DECLCALLBACK(int) hdaTransfer(PHDASTATE pThis,
2504 ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2505{
2506 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2507
2508 LogFlowFunc(("pThis=%p, cbAvail=%RU32\n", pThis, cbAvail));
2509
2510 uint8_t u8Strm;
2511 PHDABDLEDESC pBdle;
2512
2513 switch (enmSrc)
2514 {
2515 case PI_INDEX:
2516 {
2517 u8Strm = 0;
2518 pBdle = &pThis->StInBdle;
2519 break;
2520 }
2521
2522#ifdef VBOX_WITH_HDA_MIC_IN
2523 case MC_INDEX:
2524 {
2525 u8Strm = 2;
2526 pBdle = &pThis->StMicBdle;
2527 break;
2528 }
2529#endif
2530 case PO_INDEX:
2531 {
2532 u8Strm = 4;
2533 pBdle = &pThis->StOutBdle;
2534 break;
2535 }
2536
2537 default:
2538 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
2539 return VERR_NOT_SUPPORTED;
2540 }
2541
2542 HDASTREAMTRANSFERDESC StreamDesc;
2543 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2544
2545 int rc = VINF_EOF;
2546 while (cbAvail)
2547 {
2548 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
2549 && cbAvail
2550 && StreamDesc.u64BaseDMA);
2551
2552 /* Fetch the Buffer Descriptor Entry (BDE). */
2553 if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
2554 hdaFetchBdle(pThis, pBdle, &StreamDesc);
2555
2556 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2557 Assert((StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib))); /* sanity */
2558 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
2559 Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
2560
2561 LogFunc(("CBL=%RU32, LPIB=%RU32\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
2562
2563 PAUDMIXSINK pSink;
2564 uint32_t cbWritten = 0;
2565 switch (enmSrc)
2566 {
2567 case PI_INDEX:
2568 pSink = pThis->pSinkLineIn;
2569 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2570 break;
2571 case PO_INDEX:
2572 rc = hdaWriteAudio(pThis, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2573 break;
2574#ifdef VBOX_WITH_HDA_MIC_IN
2575 case MC_INDEX:
2576 pSink = pThis->pSinkMicIn;
2577 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2578 break;
2579#endif
2580 default:
2581 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
2582 rc = VERR_NOT_SUPPORTED;
2583 break;
2584 }
2585 Assert(cbWritten <= StreamDesc.u32Fifos + 1);
2586 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2587
2588 /* Process end of buffer condition. */
2589 hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cbWritten);
2590
2591 if (!hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc))
2592 break;
2593
2594 if ( RT_FAILURE(rc)
2595 || rc == VINF_EOF) /* All data processed? */
2596 {
2597 break;
2598 }
2599 }
2600
2601 return rc;
2602}
2603#endif /* IN_RING3 */
2604
2605/* MMIO callbacks */
2606
2607/**
2608 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
2609 *
2610 * @note During implementation, we discovered so-called "forgotten" or "hole"
2611 * registers whose description is not listed in the RPM, datasheet, or
2612 * spec.
2613 */
2614PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2615{
2616 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2617 int rc;
2618
2619 /*
2620 * Look up and log.
2621 */
2622 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2623 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
2624#ifdef LOG_ENABLED
2625 unsigned const cbLog = cb;
2626 uint32_t offRegLog = offReg;
2627#endif
2628
2629 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
2630#define NEW_READ_CODE
2631#ifdef NEW_READ_CODE
2632 Assert(cb == 4); Assert((offReg & 3) == 0);
2633
2634 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2635 LogFunc(("access to registers except GCTL is blocked while reset\n"));
2636
2637 if (idxRegDsc == -1)
2638 LogRel(("Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
2639
2640 if (idxRegDsc != -1)
2641 {
2642 /* ASSUMES gapless DWORD at end of map. */
2643 if (g_aHdaRegMap[idxRegDsc].size == 4)
2644 {
2645 /*
2646 * Straight forward DWORD access.
2647 */
2648 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
2649 LogFunc(("read %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
2650 }
2651 else
2652 {
2653 /*
2654 * Multi register read (unless there are trailing gaps).
2655 * ASSUMES that only DWORD reads have sideeffects.
2656 */
2657 uint32_t u32Value = 0;
2658 unsigned cbLeft = 4;
2659 do
2660 {
2661 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
2662 uint32_t u32Tmp = 0;
2663
2664 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
2665 LogFunc(("read %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
2666 if (rc != VINF_SUCCESS)
2667 break;
2668 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
2669
2670 cbLeft -= cbReg;
2671 offReg += cbReg;
2672 idxRegDsc++;
2673 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
2674
2675 if (rc == VINF_SUCCESS)
2676 *(uint32_t *)pv = u32Value;
2677 else
2678 Assert(!IOM_SUCCESS(rc));
2679 }
2680 }
2681 else
2682 {
2683 rc = VINF_IOM_MMIO_UNUSED_FF;
2684 LogFunc(("hole at %x is accessed for read\n", offReg));
2685 }
2686#else
2687 if (idxRegDsc != -1)
2688 {
2689 /** @todo r=bird: Accesses crossing register boundraries aren't handled
2690 * right from what I can tell? If they are, please explain
2691 * what the rules are. */
2692 uint32_t mask = 0;
2693 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2694 uint32_t u32Value = 0;
2695 switch(cb)
2696 {
2697 case 1: mask = 0x000000ff; break;
2698 case 2: mask = 0x0000ffff; break;
2699 case 4:
2700 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2701 case 8:
2702 mask = 0xffffffff;
2703 cb = 4;
2704 break;
2705 }
2706#if 0
2707 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
2708 */
2709 //Assert((cb <= g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset)));
2710 if (cb > g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset))
2711 {
2712 int off = cb - (g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset));
2713 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2714 if (RT_FAILURE(rc))
2715 AssertRCReturn (rc, rc);
2716 }
2717 //Assert(((offReg - g_aHdaRegMap[idxRegDsc].offset) == 0));
2718#endif
2719 mask <<= shift;
2720 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Value);
2721 *(uint32_t *)pv |= (u32Value & mask);
2722 LogFunc(("read %s[%x/%x]\n", g_aHdaRegMap[idxRegDsc].abbrev, u32Value, *(uint32_t *)pv));
2723 }
2724 else
2725 {
2726 *(uint32_t *)pv = 0xFF;
2727 LogFunc(("hole at %x is accessed for read\n", offReg));
2728 rc = VINF_SUCCESS;
2729 }
2730#endif
2731
2732 /*
2733 * Log the outcome.
2734 */
2735#ifdef LOG_ENABLED
2736 if (cbLog == 4)
2737 LogFunc(("@%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
2738 else if (cbLog == 2)
2739 LogFunc(("@%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
2740 else if (cbLog == 1)
2741 LogFunc(("@%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
2742#endif
2743 return rc;
2744}
2745
2746
2747DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
2748{
2749 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2750 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
2751
2752 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2753#ifdef LOG_ENABLED
2754 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
2755#endif
2756 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
2757 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
2758 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
2759 return rc;
2760}
2761
2762
2763/**
2764 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
2765 */
2766PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2767{
2768 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2769 int rc;
2770
2771 /*
2772 * The behavior of accesses that aren't aligned on natural boundraries is
2773 * undefined. Just reject them outright.
2774 */
2775 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
2776 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
2777 if (GCPhysAddr & (cb - 1))
2778 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
2779
2780 /*
2781 * Look up and log the access.
2782 */
2783 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2784 int idxRegDsc = hdaRegLookup(pThis, offReg);
2785 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
2786 uint64_t u64Value;
2787 if (cb == 4) u64Value = *(uint32_t const *)pv;
2788 else if (cb == 2) u64Value = *(uint16_t const *)pv;
2789 else if (cb == 1) u64Value = *(uint8_t const *)pv;
2790 else if (cb == 8) u64Value = *(uint64_t const *)pv;
2791 else
2792 {
2793 u64Value = 0; /* shut up gcc. */
2794 AssertReleaseMsgFailed(("%d\n", cb));
2795 }
2796
2797#ifdef LOG_ENABLED
2798 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
2799 uint32_t const offRegLog = offReg;
2800 int const idxRegLog = idxRegMem;
2801 if (idxRegDsc == -1)
2802 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
2803 else if (cb == 4)
2804 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2805 else if (cb == 2)
2806 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2807 else if (cb == 1)
2808 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2809 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
2810 LogFunc(("size=%d != cb=%d!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
2811#endif
2812
2813#define NEW_WRITE_CODE
2814#ifdef NEW_WRITE_CODE
2815 /*
2816 * Try for a direct hit first.
2817 */
2818 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
2819 {
2820 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
2821 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2822 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2823 }
2824 /*
2825 * Partial or multiple register access, loop thru the requested memory.
2826 */
2827 else
2828 {
2829 /* If it's an access beyond the start of the register, shift the input
2830 value and fill in missing bits. Natural alignment rules means we
2831 will only see 1 or 2 byte accesses of this kind, so no risk of
2832 shifting out input values. */
2833 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
2834 {
2835 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
2836 offReg -= cbBefore;
2837 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2838 u64Value <<= cbBefore * 8;
2839 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
2840 LogFunc(("Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
2841 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
2842 }
2843
2844 /* Loop thru the write area, it may cover multiple registers. */
2845 rc = VINF_SUCCESS;
2846 for (;;)
2847 {
2848 uint32_t cbReg;
2849 if (idxRegDsc != -1)
2850 {
2851 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2852 cbReg = g_aHdaRegMap[idxRegDsc].size;
2853 if (cb < cbReg)
2854 {
2855 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
2856 LogFunc(("Supplying missing bits (%#x): %#llx -> %#llx ...\n",
2857 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
2858 }
2859 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
2860 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
2861 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldVal,
2862 pThis->au32Regs[idxRegMem]));
2863 }
2864 else
2865 {
2866 LogRel(("HDA: Invalid write access @0x%x!\n", offReg));
2867 cbReg = 1;
2868 }
2869 if (rc != VINF_SUCCESS)
2870 break;
2871 if (cbReg >= cb)
2872 break;
2873
2874 /* advance */
2875 offReg += cbReg;
2876 cb -= cbReg;
2877 u64Value >>= cbReg * 8;
2878 if (idxRegDsc == -1)
2879 idxRegDsc = hdaRegLookup(pThis, offReg);
2880 else
2881 {
2882 idxRegDsc++;
2883 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
2884 || g_aHdaRegMap[idxRegDsc].offset != offReg)
2885 idxRegDsc = -1;
2886 }
2887 }
2888 }
2889#else
2890 if (idxRegDsc != -1)
2891 {
2892 /** @todo r=bird: This looks like code for handling unaligned register
2893 * accesses. If it isn't, then add a comment explaining what you're
2894 * trying to do here. OTOH, if it is then it has the following
2895 * issues:
2896 * -# You're calculating the wrong new value for the register.
2897 * -# You're not handling cross register accesses. Imagine a
2898 * 4-byte write starting at CORBCTL, or a 8-byte write.
2899 *
2900 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
2901 * nobody seems to be using it and it just adds complexity when reading
2902 * the code.
2903 *
2904 */
2905 uint32_t u32CurValue = pThis->au32Regs[idxRegMem];
2906 uint32_t u32NewValue;
2907 uint32_t mask;
2908 switch (cb)
2909 {
2910 case 1:
2911 u32NewValue = *(uint8_t const *)pv;
2912 mask = 0xff;
2913 break;
2914 case 2:
2915 u32NewValue = *(uint16_t const *)pv;
2916 mask = 0xffff;
2917 break;
2918 case 4:
2919 case 8:
2920 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2921 u32NewValue = *(uint32_t const *)pv;
2922 mask = 0xffffffff;
2923 cb = 4;
2924 break;
2925 default:
2926 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
2927 }
2928 /* cross-register access, see corresponding comment in hdaMMIORead */
2929 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2930 mask <<= shift;
2931 u32NewValue <<= shift;
2932 u32NewValue &= mask;
2933 u32NewValue |= (u32CurValue & ~mask);
2934
2935 rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32NewValue);
2936 LogFunc(("write %s:(%x) %x => %x\n", g_aHdaRegMap[idxRegDsc].abbrev, u32NewValue,
2937 u32CurValue, pThis->au32Regs[idxRegMem]));
2938 }
2939 else
2940 rc = VINF_SUCCESS;
2941
2942 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2943 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2944#endif
2945 return rc;
2946}
2947
2948
2949/* PCI callback. */
2950
2951#ifdef IN_RING3
2952/**
2953 * @callback_method_impl{FNPCIIOREGIONMAP}
2954 */
2955static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
2956 PCIADDRESSSPACE enmType)
2957{
2958 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2959 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
2960 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
2961 int rc;
2962
2963 /*
2964 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
2965 *
2966 * Let IOM talk DWORDs when reading, saves a lot of complications. On
2967 * writing though, we have to do it all ourselves because of sideeffects.
2968 */
2969 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2970 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2971#ifdef NEW_READ_CODE
2972 IOMMMIO_FLAGS_READ_DWORD |
2973#else
2974 IOMMMIO_FLAGS_READ_PASSTHRU |
2975#endif
2976 IOMMMIO_FLAGS_WRITE_PASSTHRU,
2977 hdaMMIOWrite, hdaMMIORead, "HDA");
2978
2979 if (RT_FAILURE(rc))
2980 return rc;
2981
2982 if (pThis->fR0Enabled)
2983 {
2984 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
2985 "hdaMMIOWrite", "hdaMMIORead");
2986 if (RT_FAILURE(rc))
2987 return rc;
2988 }
2989
2990 if (pThis->fRCEnabled)
2991 {
2992 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
2993 "hdaMMIOWrite", "hdaMMIORead");
2994 if (RT_FAILURE(rc))
2995 return rc;
2996 }
2997
2998 pThis->MMIOBaseAddr = GCPhysAddress;
2999 return VINF_SUCCESS;
3000}
3001
3002
3003/* Saved state callbacks. */
3004
3005/**
3006 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3007 */
3008static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3009{
3010 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3011
3012 /* Save Codec nodes states */
3013 hdaCodecSaveState(pThis->pCodec, pSSM);
3014
3015 /* Save MMIO registers */
3016 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3017 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3018 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3019
3020 /* Save HDA dma counters */
3021 SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3022 SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3023 SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3024 return VINF_SUCCESS;
3025}
3026
3027
3028/**
3029 * @callback_method_impl{FNSSMDEVLOADEXEC}
3030 */
3031static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3032{
3033 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3034
3035 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3036
3037 /*
3038 * Load Codec nodes states.
3039 */
3040 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3041 if (RT_FAILURE(rc))
3042 return rc;
3043
3044 /*
3045 * Load MMIO registers.
3046 */
3047 uint32_t cRegs;
3048 switch (uVersion)
3049 {
3050 case HDA_SSM_VERSION_1:
3051 /* Starting with r71199, we would save 112 instead of 113
3052 registers due to some code cleanups. This only affected trunk
3053 builds in the 4.1 development period. */
3054 cRegs = 113;
3055 if (SSMR3HandleRevision(pSSM) >= 71199)
3056 {
3057 uint32_t uVer = SSMR3HandleVersion(pSSM);
3058 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3059 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3060 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3061 cRegs = 112;
3062 }
3063 break;
3064
3065 case HDA_SSM_VERSION_2:
3066 case HDA_SSM_VERSION_3:
3067 cRegs = 112;
3068 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3069 break;
3070
3071 case HDA_SSM_VERSION:
3072 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3073 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3074 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3075 break;
3076
3077 default:
3078 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3079 }
3080
3081 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3082 {
3083 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3084 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3085 }
3086 else
3087 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3088
3089 /*
3090 * Load HDA DMA counters.
3091 */
3092 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
3093 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
3094 rc = SSMR3GetStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), fFlags, paFields, NULL);
3095 AssertRCReturn(rc, rc);
3096 rc = SSMR3GetStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), fFlags, paFields, NULL);
3097 AssertRCReturn(rc, rc);
3098 rc = SSMR3GetStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), fFlags, paFields, NULL);
3099 AssertRCReturn(rc, rc);
3100
3101 /*
3102 * Update stuff after the state changes.
3103 */
3104 bool fEnableIn = RT_BOOL(SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3105#ifdef VBOX_WITH_HDA_MIC_IN
3106 bool fEnableMicIn = RT_BOOL(SDCTL(pThis, 2) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3107#else
3108 bool fEnableMicIn = fEnableIn; /* Mic In == Line In */
3109#endif
3110 bool fEnableOut = RT_BOOL(SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3111
3112 PHDADRIVER pDrv;
3113 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3114 {
3115 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, fEnableIn);
3116 if (RT_FAILURE(rc))
3117 break;
3118 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, fEnableMicIn);
3119 if (RT_FAILURE(rc))
3120 break;
3121 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, fEnableOut);
3122 if (RT_FAILURE(rc))
3123 break;
3124 }
3125
3126 if (RT_SUCCESS(rc))
3127 {
3128 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3129 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3130 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3131 }
3132
3133 LogFlowFuncLeaveRC(rc);
3134 return rc;
3135}
3136
3137
3138/* Debug and log type formatters. */
3139
3140/**
3141 * @callback_method_impl{FNRTSTRFORMATTYPE}
3142 */
3143static DECLCALLBACK(size_t)
3144hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3145 const char *pszType, void const *pvValue,
3146 int cchWidth, int cchPrecision, unsigned fFlags,
3147 void *pvUser)
3148{
3149 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
3150 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3151 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
3152 sdCtl,
3153 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> HDA_SDCTL_NUM_SHIFT,
3154 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
3155 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3156 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3157 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3158 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3159 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3160 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3161}
3162
3163/**
3164 * @callback_method_impl{FNRTSTRFORMATTYPE}
3165 */
3166static DECLCALLBACK(size_t)
3167hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3168 const char *pszType, void const *pvValue,
3169 int cchWidth, int cchPrecision, unsigned fFlags,
3170 void *pvUser)
3171{
3172 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3173 uint32_t cb;
3174 switch (uSdFifos)
3175 {
3176 case HDA_SDONFIFO_16B: cb = 16; break;
3177 case HDA_SDONFIFO_32B: cb = 32; break;
3178 case HDA_SDONFIFO_64B: cb = 64; break;
3179 case HDA_SDONFIFO_128B: cb = 128; break;
3180 case HDA_SDONFIFO_192B: cb = 192; break;
3181 case HDA_SDONFIFO_256B: cb = 256; break;
3182 case HDA_SDINFIFO_120B: cb = 120; break;
3183 case HDA_SDINFIFO_160B: cb = 160; break;
3184 default: cb = 0; break;
3185 }
3186 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
3187}
3188
3189/**
3190 * @callback_method_impl{FNRTSTRFORMATTYPE}
3191 */
3192static DECLCALLBACK(size_t)
3193hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3194 const char *pszType, void const *pvValue,
3195 int cchWidth, int cchPrecision, unsigned fFlags,
3196 void *pvUser)
3197{
3198 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3199 uint32_t cb;
3200 switch (uSdFifos)
3201 {
3202 case HDA_SDFIFOW_8B: cb = 8; break;
3203 case HDA_SDFIFOW_16B: cb = 16; break;
3204 case HDA_SDFIFOW_32B: cb = 32; break;
3205 default: cb = 0; break;
3206 }
3207 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
3208}
3209
3210/**
3211 * @callback_method_impl{FNRTSTRFORMATTYPE}
3212 */
3213static DECLCALLBACK(size_t)
3214hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3215 const char *pszType, void const *pvValue,
3216 int cchWidth, int cchPrecision, unsigned fFlags,
3217 void *pvUser)
3218{
3219 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3220 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3221 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3222 uSdSts,
3223 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3224 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3225 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3226 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3227}
3228
3229
3230static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3231{
3232 int iReg = 0;
3233 for (; iReg < HDA_NREGS; ++iReg)
3234 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3235 return iReg;
3236 return -1;
3237}
3238
3239
3240static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
3241{
3242 Assert( pThis
3243 && iHdaIndex >= 0
3244 && iHdaIndex < HDA_NREGS);
3245 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
3246}
3247
3248
3249/**
3250 * @callback_method_impl{FNDBGFHANDLERDEV}
3251 */
3252static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3253{
3254 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3255 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
3256 if (iHdaRegisterIndex != -1)
3257 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3258 else
3259 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
3260 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3261}
3262
3263
3264static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
3265{
3266 Assert( pThis
3267 && iHdaStrmIndex >= 0
3268 && iHdaStrmIndex < 7);
3269 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
3270 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
3271 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
3272 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
3273 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
3274}
3275
3276
3277static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
3278{
3279 /* todo: add args parsing */
3280 return -1;
3281}
3282
3283
3284/**
3285 * @callback_method_impl{FNDBGFHANDLERDEV}
3286 */
3287static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3288{
3289 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3290 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
3291 if (iHdaStrmIndex != -1)
3292 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3293 else
3294 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
3295 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3296}
3297
3298
3299/**
3300 * @callback_method_impl{FNDBGFHANDLERDEV}
3301 */
3302static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3303{
3304 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3305
3306 if (pThis->pCodec->pfnCodecDbgListNodes)
3307 pThis->pCodec->pfnCodecDbgListNodes(pThis->pCodec, pHlp, pszArgs);
3308 else
3309 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3310}
3311
3312
3313/**
3314 * @callback_method_impl{FNDBGFHANDLERDEV}
3315 */
3316static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3317{
3318 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3319
3320 if (pThis->pCodec->pfnCodecDbgSelector)
3321 pThis->pCodec->pfnCodecDbgSelector(pThis->pCodec, pHlp, pszArgs);
3322 else
3323 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3324}
3325
3326
3327/* PDMIBASE */
3328
3329/**
3330 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3331 */
3332static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3333{
3334 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
3335 Assert(&pThis->IBase == pInterface);
3336
3337 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3338 return NULL;
3339}
3340
3341
3342/* PDMDEVREG */
3343
3344/**
3345 * Reset notification.
3346 *
3347 * @returns VBox status.
3348 * @param pDevIns The device instance data.
3349 *
3350 * @remark The original sources didn't install a reset handler, but it seems to
3351 * make sense to me so we'll do it.
3352 */
3353static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
3354{
3355 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3356 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
3357 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3358 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3359 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3360 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3361 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
3362 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
3363 HDA_REG(pThis, CORBRP) = 0x0;
3364 HDA_REG(pThis, RIRBWP) = 0x0;
3365
3366 LogFunc(("Resetting ...\n"));
3367
3368 /* Stop any audio currently playing. */
3369 PHDADRIVER pDrv;
3370 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3371 {
3372 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
3373 /* Ignore rc. */
3374 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
3375 /* Ditto. */
3376 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
3377 /* Ditto. */
3378 }
3379
3380 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
3381
3382 if (pThis->pu32CorbBuf)
3383 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3384 else
3385 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3386
3387 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
3388 if (pThis->pu64RirbBuf)
3389 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3390 else
3391 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3392
3393 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
3394
3395 HDABDLEDESC StEmptyBdle;
3396 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
3397 {
3398 HDASTREAMTRANSFERDESC StreamDesc;
3399 PHDABDLEDESC pBdle = NULL;
3400 if (u8Strm == 0)
3401 pBdle = &pThis->StInBdle;
3402# ifdef VBOX_WITH_HDA_MIC_IN
3403 else if (u8Strm == 2)
3404 pBdle = &pThis->StMicBdle;
3405# endif
3406 else if(u8Strm == 4)
3407 pBdle = &pThis->StOutBdle;
3408 else
3409 {
3410 RT_ZERO(StEmptyBdle);
3411 pBdle = &StEmptyBdle;
3412 }
3413 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
3414 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
3415 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
3416 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
3417 }
3418
3419 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3420 HDA_REG(pThis, STATESTS) = 0x1;
3421
3422 LogRel(("HDA: Reset\n"));
3423}
3424
3425/**
3426 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3427 */
3428static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
3429{
3430 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3431
3432 PHDADRIVER pDrv;
3433 while (!RTListIsEmpty(&pThis->lstDrv))
3434 {
3435 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
3436
3437 RTListNodeRemove(&pDrv->Node);
3438 RTMemFree(pDrv);
3439 }
3440
3441 if (pThis->pMixer)
3442 {
3443 AudioMixerDestroy(pThis->pMixer);
3444 pThis->pMixer = NULL;
3445 }
3446
3447 if (pThis->pCodec)
3448 {
3449 int rc = hdaCodecDestruct(pThis->pCodec);
3450 AssertRC(rc);
3451
3452 RTMemFree(pThis->pCodec);
3453 pThis->pCodec = NULL;
3454 }
3455
3456 RTMemFree(pThis->pu32CorbBuf);
3457 pThis->pu32CorbBuf = NULL;
3458
3459 RTMemFree(pThis->pu64RirbBuf);
3460 pThis->pu64RirbBuf = NULL;
3461
3462 return VINF_SUCCESS;
3463}
3464
3465/**
3466 * Attach command.
3467 *
3468 * This is called to let the device attach to a driver for a specified LUN
3469 * during runtime. This is not called during VM construction, the device
3470 * constructor have to attach to all the available drivers.
3471 *
3472 * @returns VBox status code.
3473 * @param pDevIns The device instance.
3474 * @param uLUN The logical unit which is being detached.
3475 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3476 */
3477static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
3478{
3479 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3480
3481 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3482 ("HDA device does not support hotplugging\n"),
3483 VERR_INVALID_PARAMETER);
3484
3485 /*
3486 * Attach driver.
3487 */
3488 char *pszDesc = NULL;
3489 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
3490 AssertMsgReturn(pszDesc,
3491 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
3492 VERR_NO_MEMORY);
3493
3494 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
3495 &pThis->IBase, &pThis->pDrvBase, pszDesc);
3496 if (RT_SUCCESS(rc))
3497 {
3498 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
3499 if (pDrv)
3500 {
3501 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
3502 AssertMsg(pDrv->pConnector != NULL,
3503 ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n",
3504 uLUN, rc));
3505 pDrv->pHDAState = pThis;
3506 pDrv->uLUN = uLUN;
3507
3508 /*
3509 * For now we always set the driver at LUN 0 as our primary
3510 * host backend. This might change in the future.
3511 */
3512 if (pDrv->uLUN == 0)
3513 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
3514
3515 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
3516
3517 /* Attach to driver list. */
3518 RTListAppend(&pThis->lstDrv, &pDrv->Node);
3519 }
3520 else
3521 rc = VERR_NO_MEMORY;
3522 }
3523 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
3524 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
3525 {
3526 LogFunc(("No attached driver for LUN #%u\n", uLUN));
3527 }
3528 else if (RT_FAILURE(rc))
3529 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
3530 uLUN, pszDesc, rc));
3531
3532 RTStrFree(pszDesc);
3533
3534 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
3535 return rc;
3536}
3537
3538static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3539{
3540 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
3541
3542 LogFlowFuncEnter();
3543}
3544
3545/**
3546 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3547 */
3548static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
3549{
3550 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3551 Assert(iInstance == 0);
3552 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3553
3554 /*
3555 * Validations.
3556 */
3557 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
3558 "RCEnabled\0"))
3559 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3560 N_ ("Invalid configuration for the Intel HDA device"));
3561
3562 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
3563 if (RT_FAILURE(rc))
3564 return PDMDEV_SET_ERROR(pDevIns, rc,
3565 N_("HDA configuration error: failed to read RCEnabled as boolean"));
3566 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
3567 if (RT_FAILURE(rc))
3568 return PDMDEV_SET_ERROR(pDevIns, rc,
3569 N_("HDA configuration error: failed to read R0Enabled as boolean"));
3570
3571 /*
3572 * Initialize data (most of it anyway).
3573 */
3574 pThis->pDevInsR3 = pDevIns;
3575 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3576 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3577 /* IBase */
3578 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
3579
3580 /* PCI Device */
3581 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
3582 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
3583
3584 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
3585 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
3586 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
3587 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
3588 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
3589 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
3590 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
3591 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
3592 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
3593 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
3594 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
3595
3596#if defined(HDA_AS_PCI_EXPRESS)
3597 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
3598#elif defined(VBOX_WITH_MSI_DEVICES)
3599 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
3600#else
3601 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
3602#endif
3603
3604 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
3605 /// of these values needs to be properly documented!
3606 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
3607 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
3608
3609 /* Power Management */
3610 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
3611 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
3612 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
3613
3614#ifdef HDA_AS_PCI_EXPRESS
3615 /* PCI Express */
3616 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
3617 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
3618 /* Device flags */
3619 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
3620 /* version */ 0x1 |
3621 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
3622 /* MSI */ (100) << 9 );
3623 /* Device capabilities */
3624 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
3625 /* Device control */
3626 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
3627 /* Device status */
3628 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
3629 /* Link caps */
3630 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
3631 /* Link control */
3632 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
3633 /* Link status */
3634 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
3635 /* Slot capabilities */
3636 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
3637 /* Slot control */
3638 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
3639 /* Slot status */
3640 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
3641 /* Root control */
3642 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
3643 /* Root capabilities */
3644 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
3645 /* Root status */
3646 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
3647 /* Device capabilities 2 */
3648 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
3649 /* Device control 2 */
3650 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
3651 /* Link control 2 */
3652 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
3653 /* Slot control 2 */
3654 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
3655#endif
3656
3657 /*
3658 * Register the PCI device.
3659 */
3660 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
3661 if (RT_FAILURE(rc))
3662 return rc;
3663
3664 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
3665 if (RT_FAILURE(rc))
3666 return rc;
3667
3668#ifdef VBOX_WITH_MSI_DEVICES
3669 PDMMSIREG MsiReg;
3670 RT_ZERO(MsiReg);
3671 MsiReg.cMsiVectors = 1;
3672 MsiReg.iMsiCapOffset = 0x60;
3673 MsiReg.iMsiNextOffset = 0x50;
3674 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3675 if (RT_FAILURE(rc))
3676 {
3677 /* That's OK, we can work without MSI */
3678 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
3679 }
3680#endif
3681
3682 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
3683 if (RT_FAILURE(rc))
3684 return rc;
3685
3686 RTListInit(&pThis->lstDrv);
3687
3688 uint8_t uLUN;
3689 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
3690 {
3691 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
3692 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
3693 if (RT_FAILURE(rc))
3694 {
3695 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3696 rc = VINF_SUCCESS;
3697
3698 break;
3699 }
3700
3701 uLUN++;
3702 }
3703
3704 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3705
3706 if (RT_SUCCESS(rc))
3707 {
3708 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
3709 if (RT_SUCCESS(rc))
3710 {
3711 /* Set a default audio format for our mixer. */
3712 PDMAUDIOSTREAMCFG streamCfg;
3713 streamCfg.uHz = 41000;
3714 streamCfg.cChannels = 2;
3715 streamCfg.enmFormat = AUD_FMT_S16;
3716 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
3717
3718 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
3719 AssertRC(rc);
3720
3721 /* Add all required audio sinks. */
3722 rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output",
3723 AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
3724 AssertRC(rc);
3725
3726 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In",
3727 AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
3728 AssertRC(rc);
3729
3730 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
3731 AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
3732 AssertRC(rc);
3733
3734 /* There is no master volume control. Set the master to max. */
3735 PDMAUDIOVOLUME vol = { false, 255, 255 };
3736 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
3737 AssertRC(rc);
3738 }
3739 }
3740
3741 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3742
3743 if (RT_SUCCESS(rc))
3744 {
3745 /* Construct codec. */
3746 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
3747 if (!pThis->pCodec)
3748 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
3749
3750 /* Audio driver callbacks for multiplexing. */
3751 pThis->pCodec->pfnCloseIn = hdaCloseIn;
3752 pThis->pCodec->pfnCloseOut = hdaCloseOut;
3753 pThis->pCodec->pfnOpenIn = hdaOpenIn;
3754 pThis->pCodec->pfnOpenOut = hdaOpenOut;
3755 pThis->pCodec->pfnReset = hdaCodecReset;
3756 pThis->pCodec->pfnSetVolume = hdaSetVolume;
3757
3758 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
3759
3760 /* Construct the codec. */
3761 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
3762 if (RT_FAILURE(rc))
3763 AssertRCReturn(rc, rc);
3764
3765 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
3766 verb F20 should provide device/codec recognition. */
3767 Assert(pThis->pCodec->u16VendorId);
3768 Assert(pThis->pCodec->u16DeviceId);
3769 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
3770 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
3771 }
3772
3773 if (RT_SUCCESS(rc))
3774 {
3775 hdaReset(pDevIns);
3776
3777 /*
3778 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
3779 * hdaReset shouldn't affects these registers.
3780 */
3781 HDA_REG(pThis, WAKEEN) = 0x0;
3782 HDA_REG(pThis, STATESTS) = 0x0;
3783
3784 /*
3785 * Debug and string formatter types.
3786 */
3787 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
3788 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
3789 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
3790 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
3791
3792 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
3793 AssertRC(rc);
3794 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
3795 AssertRC(rc);
3796 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
3797 AssertRC(rc);
3798 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
3799 AssertRC(rc);
3800 #if 0
3801 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
3802 AssertRC(rc);
3803 #endif
3804
3805 /*
3806 * Some debug assertions.
3807 */
3808 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
3809 {
3810 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
3811 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
3812
3813 /* binary search order. */
3814 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
3815 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3816 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3817
3818 /* alignment. */
3819 AssertReleaseMsg( pReg->size == 1
3820 || (pReg->size == 2 && (pReg->offset & 1) == 0)
3821 || (pReg->size == 3 && (pReg->offset & 3) == 0)
3822 || (pReg->size == 4 && (pReg->offset & 3) == 0),
3823 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3824
3825 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
3826 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
3827 if (pReg->offset & 3)
3828 {
3829 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
3830 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3831 if (pPrevReg)
3832 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
3833 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3834 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
3835 }
3836 #if 0
3837 if ((pReg->offset + pReg->size) & 3)
3838 {
3839 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3840 if (pNextReg)
3841 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
3842 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3843 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3844 }
3845 #endif
3846
3847 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
3848 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
3849 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3850 }
3851 }
3852
3853 if (RT_SUCCESS(rc))
3854 {
3855 /* Start the emulation timer. */
3856 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
3857 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
3858 AssertRCReturn(rc, rc);
3859
3860 if (RT_SUCCESS(rc))
3861 {
3862 /** @todo Investigate why sounds is getting corrupted if the "ticks" value is too
3863 * low, e.g. "PDMDevHlpTMTimeVirtGetFreq / 200". */
3864 pThis->uTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 500; /** @todo Make this configurable! */
3865 if (pThis->uTicks < 100)
3866 pThis->uTicks = 100;
3867 LogFunc(("Timer ticks=%RU64\n", pThis->uTicks));
3868
3869 /* Fire off timer. */
3870 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
3871 }
3872 }
3873
3874# ifdef VBOX_WITH_STATISTICS
3875 if (RT_SUCCESS(rc))
3876 {
3877 /*
3878 * Register statistics.
3879 */
3880 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
3881 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
3882 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
3883 }
3884# endif
3885
3886 LogFlowFuncLeaveRC(rc);
3887 return rc;
3888}
3889
3890/**
3891 * The device registration structure.
3892 */
3893const PDMDEVREG g_DeviceICH6_HDA =
3894{
3895 /* u32Version */
3896 PDM_DEVREG_VERSION,
3897 /* szName */
3898 "hda",
3899 /* szRCMod */
3900 "VBoxDDRC.rc",
3901 /* szR0Mod */
3902 "VBoxDDR0.r0",
3903 /* pszDescription */
3904 "Intel HD Audio Controller",
3905 /* fFlags */
3906 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
3907 /* fClass */
3908 PDM_DEVREG_CLASS_AUDIO,
3909 /* cMaxInstances */
3910 1,
3911 /* cbInstance */
3912 sizeof(HDASTATE),
3913 /* pfnConstruct */
3914 hdaConstruct,
3915 /* pfnDestruct */
3916 hdaDestruct,
3917 /* pfnRelocate */
3918 NULL,
3919 /* pfnMemSetup */
3920 NULL,
3921 /* pfnPowerOn */
3922 NULL,
3923 /* pfnReset */
3924 hdaReset,
3925 /* pfnSuspend */
3926 NULL,
3927 /* pfnResume */
3928 NULL,
3929 /* pfnAttach */
3930 NULL,
3931 /* pfnDetach */
3932 NULL,
3933 /* pfnQueryInterface. */
3934 NULL,
3935 /* pfnInitComplete */
3936 NULL,
3937 /* pfnPowerOff */
3938 NULL,
3939 /* pfnSoftReset */
3940 NULL,
3941 /* u32VersionEnd */
3942 PDM_DEVREG_VERSION
3943};
3944
3945#endif /* IN_RING3 */
3946#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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