VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 56648

Last change on this file since 56648 was 56648, checked in by vboxsync, 9 years ago

Audio: Remove DEV_AUDIO logging group and split it up into per device and driver groups for finer grained logging
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1/* $Id: DevIchHda.cpp 56648 2015-06-25 21:57:41Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2015 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_DEV_HDA
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBox/vmm/pdmaudioifs.h>
29#include <VBox/version.h>
30
31#include <iprt/assert.h>
32#include <iprt/asm.h>
33#include <iprt/asm-math.h>
34#ifdef IN_RING3
35# include <iprt/uuid.h>
36# include <iprt/string.h>
37# include <iprt/mem.h>
38#endif
39#include <iprt/list.h>
40
41#include "VBoxDD.h"
42
43#include "AudioMixer.h"
44#include "DevIchHdaCodec.h"
45
46/*******************************************************************************
47* Defined Constants And Macros *
48*******************************************************************************/
49//#define HDA_AS_PCI_EXPRESS
50#define VBOX_WITH_INTEL_HDA
51
52#if (defined(DEBUG) && defined(DEBUG_andy))
53/* Enables experimental support for separate mic-in handling.
54 Do not enable this yet for regular builds, as this needs more testing first! */
55# define VBOX_WITH_HDA_MIC_IN
56#endif
57
58#if defined(VBOX_WITH_HP_HDA)
59/* HP Pavilion dv4t-1300 */
60# define HDA_PCI_VENDOR_ID 0x103c
61# define HDA_PCI_DEVICE_ID 0x30f7
62#elif defined(VBOX_WITH_INTEL_HDA)
63/* Intel HDA controller */
64# define HDA_PCI_VENDOR_ID 0x8086
65# define HDA_PCI_DEVICE_ID 0x2668
66#elif defined(VBOX_WITH_NVIDIA_HDA)
67/* nVidia HDA controller */
68# define HDA_PCI_VENDOR_ID 0x10de
69# define HDA_PCI_DEVICE_ID 0x0ac0
70#else
71# error "Please specify your HDA device vendor/device IDs"
72#endif
73
74/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
75 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
76 * is read only except for bit 15 like the HDA spec states.
77 *
78 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
79 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
80#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
81
82#define HDA_NREGS 114
83#define HDA_NREGS_SAVED 112
84
85/**
86 * NB: Register values stored in memory (au32Regs[]) are indexed through
87 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
88 * register descriptors in g_aHdaRegMap[] are indexed through the
89 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
90 *
91 * The au32Regs[] layout is kept unchanged for saved state
92 * compatibility. */
93
94/* Registers */
95#define HDA_REG_IND_NAME(x) HDA_REG_##x
96#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
97#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
98#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
99#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
100#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
101#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
102#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
103
104
105#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
106#define HDA_RMX_GCAP 0
107/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
108 * oss (15:12) - number of output streams supported
109 * iss (11:8) - number of input streams supported
110 * bss (7:3) - number of bidirectional streams supported
111 * bds (2:1) - number of serial data out signals supported
112 * b64sup (0) - 64 bit addressing supported.
113 */
114#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
115 ( (((oss) & 0xF) << 12) \
116 | (((iss) & 0xF) << 8) \
117 | (((bss) & 0x1F) << 3) \
118 | (((bds) & 0x3) << 2) \
119 | ((b64sup) & 1))
120
121#define HDA_REG_VMIN 1 /* 0x02 */
122#define HDA_RMX_VMIN 1
123
124#define HDA_REG_VMAJ 2 /* 0x03 */
125#define HDA_RMX_VMAJ 2
126
127#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
128#define HDA_RMX_OUTPAY 3
129
130#define HDA_REG_INPAY 4 /* 0x06-0x07 */
131#define HDA_RMX_INPAY 4
132
133#define HDA_REG_GCTL 5 /* 0x08-0x0B */
134#define HDA_RMX_GCTL 5
135#define HDA_GCTL_RST_SHIFT 0
136#define HDA_GCTL_FSH_SHIFT 1
137#define HDA_GCTL_UR_SHIFT 8
138
139#define HDA_REG_WAKEEN 6 /* 0x0C */
140#define HDA_RMX_WAKEEN 6
141
142#define HDA_REG_STATESTS 7 /* 0x0E */
143#define HDA_RMX_STATESTS 7
144#define HDA_STATES_SCSF 0x7
145
146#define HDA_REG_GSTS 8 /* 0x10-0x11*/
147#define HDA_RMX_GSTS 8
148#define HDA_GSTS_FSH_SHIFT 1
149
150#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
151#define HDA_RMX_OUTSTRMPAY 112
152
153#define HDA_REG_INSTRMPAY 10 /* 0x1a */
154#define HDA_RMX_INSTRMPAY 113
155
156#define HDA_REG_INTCTL 11 /* 0x20 */
157#define HDA_RMX_INTCTL 9
158#define HDA_INTCTL_GIE_SHIFT 31
159#define HDA_INTCTL_CIE_SHIFT 30
160#define HDA_INTCTL_S0_SHIFT 0
161#define HDA_INTCTL_S1_SHIFT 1
162#define HDA_INTCTL_S2_SHIFT 2
163#define HDA_INTCTL_S3_SHIFT 3
164#define HDA_INTCTL_S4_SHIFT 4
165#define HDA_INTCTL_S5_SHIFT 5
166#define HDA_INTCTL_S6_SHIFT 6
167#define HDA_INTCTL_S7_SHIFT 7
168#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
169
170#define HDA_REG_INTSTS 12 /* 0x24 */
171#define HDA_RMX_INTSTS 10
172#define HDA_INTSTS_GIS_SHIFT 31
173#define HDA_INTSTS_CIS_SHIFT 30
174#define HDA_INTSTS_S0_SHIFT 0
175#define HDA_INTSTS_S1_SHIFT 1
176#define HDA_INTSTS_S2_SHIFT 2
177#define HDA_INTSTS_S3_SHIFT 3
178#define HDA_INTSTS_S4_SHIFT 4
179#define HDA_INTSTS_S5_SHIFT 5
180#define HDA_INTSTS_S6_SHIFT 6
181#define HDA_INTSTS_S7_SHIFT 7
182#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
183
184#define HDA_REG_WALCLK 13 /* 0x24 */
185#define HDA_RMX_WALCLK /* Not defined! */
186
187/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
188 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
189 * the datasheet.
190 */
191#define HDA_REG_SSYNC 14 /* 0x34 */
192#define HDA_RMX_SSYNC 12
193
194#define HDA_REG_CORBLBASE 15 /* 0x40 */
195#define HDA_RMX_CORBLBASE 13
196
197#define HDA_REG_CORBUBASE 16 /* 0x44 */
198#define HDA_RMX_CORBUBASE 14
199
200#define HDA_REG_CORBWP 17 /* 0x48 */
201#define HDA_RMX_CORBWP 15
202
203#define HDA_REG_CORBRP 18 /* 0x4A */
204#define HDA_RMX_CORBRP 16
205#define HDA_CORBRP_RST_SHIFT 15
206#define HDA_CORBRP_WP_SHIFT 0
207#define HDA_CORBRP_WP_MASK 0xFF
208
209#define HDA_REG_CORBCTL 19 /* 0x4C */
210#define HDA_RMX_CORBCTL 17
211#define HDA_CORBCTL_DMA_SHIFT 1
212#define HDA_CORBCTL_CMEIE_SHIFT 0
213
214#define HDA_REG_CORBSTS 20 /* 0x4D */
215#define HDA_RMX_CORBSTS 18
216#define HDA_CORBSTS_CMEI_SHIFT 0
217
218#define HDA_REG_CORBSIZE 21 /* 0x4E */
219#define HDA_RMX_CORBSIZE 19
220#define HDA_CORBSIZE_SZ_CAP 0xF0
221#define HDA_CORBSIZE_SZ 0x3
222/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
223
224#define HDA_REG_RIRBLBASE 22 /* 0x50 */
225#define HDA_RMX_RIRBLBASE 20
226
227#define HDA_REG_RIRBUBASE 23 /* 0x54 */
228#define HDA_RMX_RIRBUBASE 21
229
230#define HDA_REG_RIRBWP 24 /* 0x58 */
231#define HDA_RMX_RIRBWP 22
232#define HDA_RIRBWP_RST_SHIFT 15
233#define HDA_RIRBWP_WP_MASK 0xFF
234
235#define HDA_REG_RINTCNT 25 /* 0x5A */
236#define HDA_RMX_RINTCNT 23
237#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
238
239#define HDA_REG_RIRBCTL 26 /* 0x5C */
240#define HDA_RMX_RIRBCTL 24
241#define HDA_RIRBCTL_RIC_SHIFT 0
242#define HDA_RIRBCTL_DMA_SHIFT 1
243#define HDA_ROI_DMA_SHIFT 2
244
245#define HDA_REG_RIRBSTS 27 /* 0x5D */
246#define HDA_RMX_RIRBSTS 25
247#define HDA_RIRBSTS_RINTFL_SHIFT 0
248#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
249
250#define HDA_REG_RIRBSIZE 28 /* 0x5E */
251#define HDA_RMX_RIRBSIZE 26
252#define HDA_RIRBSIZE_SZ_CAP 0xF0
253#define HDA_RIRBSIZE_SZ 0x3
254
255#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
256#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
257
258
259#define HDA_REG_IC 29 /* 0x60 */
260#define HDA_RMX_IC 27
261
262#define HDA_REG_IR 30 /* 0x64 */
263#define HDA_RMX_IR 28
264
265#define HDA_REG_IRS 31 /* 0x68 */
266#define HDA_RMX_IRS 29
267#define HDA_IRS_ICB_SHIFT 0
268#define HDA_IRS_IRV_SHIFT 1
269
270#define HDA_REG_DPLBASE 32 /* 0x70 */
271#define HDA_RMX_DPLBASE 30
272#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
273
274#define HDA_REG_DPUBASE 33 /* 0x74 */
275#define HDA_RMX_DPUBASE 31
276#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
277#define DPBASE_ENABLED 1
278#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
279
280#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
281#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
282/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
283#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
284
285#define HDA_REG_SD0CTL 34 /* 0x80 */
286#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
287#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
288#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
289#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
290#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
291#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
292#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
293#define HDA_RMX_SD0CTL 32
294#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
295#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
296#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
297#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
298#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
299#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
300#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
301
302#define SD(func, num) SD##num##func
303#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
304#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
305#define HDA_SDCTL_NUM_MASK 0xF
306#define HDA_SDCTL_NUM_SHIFT 20
307#define HDA_SDCTL_DIR_SHIFT 19
308#define HDA_SDCTL_TP_SHIFT 18
309#define HDA_SDCTL_STRIPE_MASK 0x3
310#define HDA_SDCTL_STRIPE_SHIFT 16
311#define HDA_SDCTL_DEIE_SHIFT 4
312#define HDA_SDCTL_FEIE_SHIFT 3
313#define HDA_SDCTL_ICE_SHIFT 2
314#define HDA_SDCTL_RUN_SHIFT 1
315#define HDA_SDCTL_SRST_SHIFT 0
316
317#define HDA_REG_SD0STS 35 /* 0x83 */
318#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
319#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
320#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
321#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
322#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
323#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
324#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
325#define HDA_RMX_SD0STS 33
326#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
327#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
328#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
329#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
330#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
331#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
332#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
333
334#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
335#define HDA_SDSTS_FIFORDY_SHIFT 5
336#define HDA_SDSTS_DE_SHIFT 4
337#define HDA_SDSTS_FE_SHIFT 3
338#define HDA_SDSTS_BCIS_SHIFT 2
339
340#define HDA_REG_SD0LPIB 36 /* 0x84 */
341#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
342#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
343#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
344#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
345#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
346#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
347#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
348#define HDA_RMX_SD0LPIB 34
349#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
350#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
351#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
352#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
353#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
354#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
355#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
356
357#define HDA_REG_SD0CBL 37 /* 0x88 */
358#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
359#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
360#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
361#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
362#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
363#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
364#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
365#define HDA_RMX_SD0CBL 35
366#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
367#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
368#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
369#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
370#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
371#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
372#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
373
374
375#define HDA_REG_SD0LVI 38 /* 0x8C */
376#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
377#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
378#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
379#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
380#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
381#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
382#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
383#define HDA_RMX_SD0LVI 36
384#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
385#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
386#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
387#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
388#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
389#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
390#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
391
392#define HDA_REG_SD0FIFOW 39 /* 0x8E */
393#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
394#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
395#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
396#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
397#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
398#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
399#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
400#define HDA_RMX_SD0FIFOW 37
401#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
402#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
403#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
404#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
405#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
406#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
407#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
408
409/*
410 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
411 */
412#define HDA_SDFIFOW_8B 0x2
413#define HDA_SDFIFOW_16B 0x3
414#define HDA_SDFIFOW_32B 0x4
415
416#define HDA_REG_SD0FIFOS 40 /* 0x90 */
417#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
418#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
419#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
420#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
421#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
422#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
423#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
424#define HDA_RMX_SD0FIFOS 38
425#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
426#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
427#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
428#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
429#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
430#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
431#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
432
433/*
434 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
435 * formula: size - 1
436 * Other values not listed are not supported.
437 */
438#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
439#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
440#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
441#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
442#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
443#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
444#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
445#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
446#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
447
448#define HDA_REG_SD0FMT 41 /* 0x92 */
449#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
450#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
451#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
452#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
453#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
454#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
455#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
456#define HDA_RMX_SD0FMT 39
457#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
458#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
459#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
460#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
461#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
462#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
463#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
464
465#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
466#define HDA_SDFMT_BASE_RATE_SHIFT 14
467#define HDA_SDFMT_MULT_SHIFT 11
468#define HDA_SDFMT_MULT_MASK 0x7
469#define HDA_SDFMT_DIV_SHIFT 8
470#define HDA_SDFMT_DIV_MASK 0x7
471#define HDA_SDFMT_BITS_SHIFT 4
472#define HDA_SDFMT_BITS_MASK 0x7
473#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
474#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
475#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
476
477#define HDA_REG_SD0BDPL 42 /* 0x98 */
478#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
479#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
480#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
481#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
482#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
483#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
484#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
485#define HDA_RMX_SD0BDPL 40
486#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
487#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
488#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
489#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
490#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
491#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
492#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
493
494#define HDA_REG_SD0BDPU 43 /* 0x9C */
495#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
496#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
497#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
498#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
499#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
500#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
501#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
502#define HDA_RMX_SD0BDPU 41
503#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
504#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
505#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
506#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
507#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
508#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
509#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
510
511#define HDA_CODEC_CAD_SHIFT 28
512/* Encodes the (required) LUN into a codec command. */
513#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
514
515
516
517/*******************************************************************************
518* Structures and Typedefs *
519*******************************************************************************/
520typedef struct HDABDLEDESC
521{
522 uint64_t u64BdleCviAddr;
523 uint32_t u32BdleMaxCvi;
524 uint32_t u32BdleCvi;
525 uint32_t u32BdleCviLen;
526 uint32_t u32BdleCviPos;
527 bool fBdleCviIoc;
528 uint32_t cbUnderFifoW;
529 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
530} HDABDLEDESC, *PHDABDLEDESC;
531
532typedef struct HDASTREAMTRANSFERDESC
533{
534 uint64_t u64BaseDMA;
535 uint32_t u32Ctl;
536 uint32_t *pu32Sts;
537 uint8_t u8Strm;
538 uint32_t *pu32Lpib;
539 uint32_t u32Cbl;
540 uint32_t u32Fifos;
541} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
542
543typedef struct HDAINPUTSTREAM
544{
545 /** PCM line input stream. */
546 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
547 /** Mixer handle for line input stream. */
548 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
549} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
550
551typedef struct HDAOUTPUTSTREAM
552{
553 /** PCM output stream. */
554 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
555 /** Mixer handle for line output stream. */
556 R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
557} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
558
559/**
560 * Struct for maintaining a host backend driver.
561 * This driver must be associated to one, and only one,
562 * HDA codec. The HDA controller does the actual multiplexing
563 * of HDA codec data to various host backend drivers then.
564 *
565 * This HDA device uses a timer in order to synchronize all
566 * read/write accesses across all attached LUNs / backends.
567 */
568typedef struct HDADRIVER
569{
570 union
571 {
572 /** Node for storing this driver in our device driver
573 * list of HDASTATE. */
574 RTLISTNODE Node;
575 struct
576 {
577 R3PTRTYPE(void *) dummy1;
578 R3PTRTYPE(void *) dummy2;
579 } dummy;
580 };
581
582 /** Pointer to HDA controller (state). */
583 R3PTRTYPE(PHDASTATE) pHDAState;
584 /** Driver flags. */
585 PDMAUDIODRVFLAGS Flags;
586 uint8_t u32Padding0[3];
587 /** LUN to which this driver has been assigned. */
588 uint8_t uLUN;
589 /** Audio connector interface to the underlying
590 * host backend. */
591 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
592 /** Stream for line input. */
593 HDAINPUTSTREAM LineIn;
594 /** Stream for mic input. */
595 HDAINPUTSTREAM MicIn;
596 /** Stream for output. */
597 HDAOUTPUTSTREAM Out;
598} HDADRIVER, *PHDADRIVER;
599
600/**
601 * ICH Intel HD Audio Controller state.
602 */
603typedef struct HDASTATE
604{
605 /** The PCI device structure. */
606 PCIDevice PciDev;
607 /** R3 Pointer to the device instance. */
608 PPDMDEVINSR3 pDevInsR3;
609 /** R0 Pointer to the device instance. */
610 PPDMDEVINSR0 pDevInsR0;
611 /** R0 Pointer to the device instance. */
612 PPDMDEVINSRC pDevInsRC;
613
614 uint32_t u32Padding;
615
616 /** Pointer to the attached audio driver. */
617 R3PTRTYPE(PPDMIBASE) pDrvBase;
618 /** The base interface for LUN\#0. */
619 PDMIBASE IBase;
620 RTGCPHYS MMIOBaseAddr;
621 uint32_t au32Regs[HDA_NREGS];
622 HDABDLEDESC StInBdle;
623 HDABDLEDESC StOutBdle;
624 HDABDLEDESC StMicBdle;
625 uint64_t u64CORBBase;
626 uint64_t u64RIRBBase;
627 uint64_t u64DPBase;
628 /** Pointer to CORB buffer. */
629 R3PTRTYPE(uint32_t *) pu32CorbBuf;
630 /** Size in bytes of CORB buffer. */
631 uint32_t cbCorbBuf;
632 uint32_t u32Padding2;
633 /** Pointer to RIRB buffer. */
634 R3PTRTYPE(uint64_t *) pu64RirbBuf;
635 /** Size in bytes of RIRB buffer. */
636 uint32_t cbRirbBuf;
637 /** Indicates if HDA is in reset. */
638 bool fInReset;
639 /** Interrupt on completion */
640 bool fCviIoc;
641 /** Flag whether the R0 part is enabled. */
642 bool fR0Enabled;
643 /** Flag whether the RC part is enabled. */
644 bool fRCEnabled;
645 /** The emulation timer for handling the attached
646 * LUN drivers. */
647 PTMTIMERR3 pTimer;
648 /** Timer ticks for handling the LUN drivers. */
649 uint64_t uTicks;
650# ifdef VBOX_WITH_STATISTICS
651 STAMPROFILE StatTimer;
652 STAMCOUNTER StatBytesRead;
653 STAMCOUNTER StatBytesWritten;
654# endif
655 /** Pointer to HDA codec to use. */
656 R3PTRTYPE(PHDACODEC) pCodec;
657 union
658 {
659 /** List of associated LUN drivers. */
660 RTLISTANCHOR lstDrv;
661 struct
662 {
663 R3PTRTYPE(void *) dummy1;
664 R3PTRTYPE(void *) dummy2;
665 } dummy;
666 };
667 /** The device' software mixer. */
668 R3PTRTYPE(PAUDIOMIXER) pMixer;
669 /** Audio sink for PCM output. */
670 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
671 /** Audio mixer sink for line input. */
672 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
673 /** Audio mixer sink for microphone input. */
674 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
675 uint64_t u64BaseTS;
676 /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
677 uint8_t u8Counter;
678 uint8_t au8Padding[7];
679} HDASTATE;
680/** Pointer to the ICH Intel HD Audio Controller state. */
681typedef HDASTATE *PHDASTATE;
682
683#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
684 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
685#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
686 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
687
688
689/*******************************************************************************
690* Internal Functions *
691*******************************************************************************/
692#ifndef VBOX_DEVICE_STRUCT_TESTCASE
693static FNPDMDEVRESET hdaReset;
694
695static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
696static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
697static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
698static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
699static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
700static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
701static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
702static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
703static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
704static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
705static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
706static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
707static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
708static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
709static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
710static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
711static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
712
713static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
714static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
715static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
716static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
717static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
718static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
719static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
720static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
721static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
722static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
723static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
724static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
725static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
726static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
727static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
728static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
729
730static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
731static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail);
732
733#ifdef IN_RING3
734DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
735 PHDASTREAMTRANSFERDESC pStreamDesc);
736static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
737#ifdef LOG_ENABLED
738static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
739#endif
740#endif
741
742
743/*******************************************************************************
744* Global Variables *
745*******************************************************************************/
746
747/* see 302349 p 6.2*/
748static const struct HDAREGDESC
749{
750 /** Register offset in the register space. */
751 uint32_t offset;
752 /** Size in bytes. Registers of size > 4 are in fact tables. */
753 uint32_t size;
754 /** Readable bits. */
755 uint32_t readable;
756 /** Writable bits. */
757 uint32_t writable;
758 /** Read callback. */
759 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
760 /** Write callback. */
761 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
762 /** Index into the register storage array. */
763 uint32_t mem_idx;
764 /** Abbreviated name. */
765 const char *abbrev;
766} g_aHdaRegMap[HDA_NREGS] =
767
768/* Turn a short register name into an memory index and a stringized name. */
769#define RA(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
770/* Same as above for an input stream ('I' prefixed). */
771#define IA(abbrev) HDA_MEM_IND_NAME(abbrev), "I"#abbrev
772/* Same as above for an output stream ('O' prefixed). */
773#define OA(abbrev) HDA_MEM_IND_NAME(abbrev), "O"#abbrev
774/* Same as above for a register *not* stored in memory. */
775#define UA(abbrev) 0, #abbrev
776
777{
778 /* offset size read mask write mask read callback write callback abbrev */
779 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- */
780 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(GCAP) }, /* Global Capabilities */
781 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMIN) }, /* Minor Version */
782 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMAJ) }, /* Major Version */
783 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTPAY) }, /* Output Payload Capabilities */
784 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INPAY) }, /* Input Payload Capabilities */
785 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , RA(GCTL) }, /* Global Control */
786 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , RA(WAKEEN) }, /* Wake Enable */
787 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , RA(STATESTS) }, /* State Change Status */
788 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , RA(GSTS) }, /* Global Status */
789 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTSTRMPAY)}, /* Output Stream Payload Capability */
790 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INSTRMPAY) }, /* Input Stream Payload Capability */
791 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(INTCTL) }, /* Interrupt Control */
792 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , RA(INTSTS) }, /* Interrupt Status */
793 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , UA(WALCLK) }, /* Wall Clock Counter */
794 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
795 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(SSYNC) }, /* Stream Synchronization */
796 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(CORBLBASE) }, /* CORB Lower Base Address */
797 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(CORBUBASE) }, /* CORB Upper Base Address */
798 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , RA(CORBWP) }, /* CORB Write Pointer */
799 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , RA(CORBRP) }, /* CORB Read Pointer */
800 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , RA(CORBCTL) }, /* CORB Control */
801 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , RA(CORBSTS) }, /* CORB Status */
802 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(CORBSIZE) }, /* CORB Size */
803 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBLBASE) }, /* RIRB Lower Base Address */
804 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBUBASE) }, /* RIRB Upper Base Address */
805 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , RA(RIRBWP) }, /* RIRB Write Pointer */
806 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , RA(RINTCNT) }, /* Response Interrupt Count */
807 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , RA(RIRBCTL) }, /* RIRB Control */
808 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , RA(RIRBSTS) }, /* RIRB Status */
809 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(RIRBSIZE) }, /* RIRB Size */
810 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , RA(IC) }, /* Immediate Command */
811 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , RA(IR) }, /* Immediate Response */
812 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , RA(IRS) }, /* Immediate Command Status */
813 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , RA(DPLBASE) }, /* MA Position Lower Base */
814 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(DPUBASE) }, /* DMA Position Upper Base */
815
816 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD0CTL) }, /* Input Stream Descriptor 0 (ICD0) Control */
817 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD0STS) }, /* ISD0 Status */
818 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0LPIB) }, /* ISD0 Link Position In Buffer */
819 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0CBL) }, /* ISD0 Cyclic Buffer Length */
820 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD0LVI) }, /* ISD0 Last Valid Index */
821 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD0FIFOW) }, /* ISD0 FIFO Watermark */
822 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD0FIFOS) }, /* ISD0 FIFO Size */
823 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD0FMT) }, /* ISD0 Format */
824 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD0BDPL) }, /* ISD0 Buffer Descriptor List Pointer-Lower Base Address */
825 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD0BDPU) }, /* ISD0 Buffer Descriptor List Pointer-Upper Base Address */
826
827 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD1CTL) }, /* Input Stream Descriptor 1 (ISD1) Control */
828 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD1STS) }, /* ISD1 Status */
829 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1LPIB) }, /* ISD1 Link Position In Buffer */
830 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1CBL) }, /* ISD1 Cyclic Buffer Length */
831 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD1LVI) }, /* ISD1 Last Valid Index */
832 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD1FIFOW) }, /* ISD1 FIFO Watermark */
833 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD1FIFOS) }, /* ISD1 FIFO Size */
834 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD1FMT) }, /* ISD1 Format */
835 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD1BDPL) }, /* ISD1 Buffer Descriptor List Pointer-Lower Base Address */
836 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD1BDPU) }, /* ISD1 Buffer Descriptor List Pointer-Upper Base Address */
837
838 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD2CTL) }, /* Input Stream Descriptor 2 (ISD2) Control */
839 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD2STS) }, /* ISD2 Status */
840 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2LPIB) }, /* ISD2 Link Position In Buffer */
841 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2CBL) }, /* ISD2 Cyclic Buffer Length */
842 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD2LVI) }, /* ISD2 Last Valid Index */
843 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD2FIFOW) }, /* ISD2 FIFO Watermark */
844 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD2FIFOS) }, /* ISD2 FIFO Size */
845 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD2FMT) }, /* ISD2 Format */
846 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD2BDPL) }, /* ISD2 Buffer Descriptor List Pointer-Lower Base Address */
847 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD2BDPU) }, /* ISD2 Buffer Descriptor List Pointer-Upper Base Address */
848
849 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD3CTL) }, /* Input Stream Descriptor 3 (ISD3) Control */
850 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD3STS) }, /* ISD3 Status */
851 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3LPIB) }, /* ISD3 Link Position In Buffer */
852 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3CBL) }, /* ISD3 Cyclic Buffer Length */
853 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD3LVI) }, /* ISD3 Last Valid Index */
854 { 0x000EE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD3FIFOW) }, /* ISD3 FIFO Watermark */
855 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD3FIFOS) }, /* ISD3 FIFO Size */
856 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD3FMT) }, /* ISD3 Format */
857 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD3BDPL) }, /* ISD3 Buffer Descriptor List Pointer-Lower Base Address */
858 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD3BDPU) }, /* ISD3 Buffer Descriptor List Pointer-Upper Base Address */
859
860 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD4CTL) }, /* Output Stream Descriptor 4 (OSD4) Control */
861 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD4STS) }, /* OSD4 Status */
862 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4LPIB) }, /* OSD4 Link Position In Buffer */
863 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4CBL) }, /* OSD4 Cyclic Buffer Length */
864 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD4LVI) }, /* OSD4 Last Valid Index */
865 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD4FIFOW) }, /* OSD4 FIFO Watermark */
866 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD4FIFOS) }, /* OSD4 FIFO Size */
867 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD4FMT) }, /* OSD4 Format */
868 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD4BDPL) }, /* OSD4 Buffer Descriptor List Pointer-Lower Base Address */
869 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD4BDPU) }, /* OSD4 Buffer Descriptor List Pointer-Upper Base Address */
870
871 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD5CTL) }, /* Output Stream Descriptor 5 (OSD5) Control */
872 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD5STS) }, /* OSD5 Status */
873 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5LPIB) }, /* OSD5 Link Position In Buffer */
874 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5CBL) }, /* OSD5 Cyclic Buffer Length */
875 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD5LVI) }, /* OSD5 Last Valid Index */
876 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD5FIFOW) }, /* OSD5 FIFO Watermark */
877 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD5FIFOS) }, /* OSD5 FIFO Size */
878 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD5FMT) }, /* OSD5 Format */
879 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD5BDPL) }, /* OSD5 Buffer Descriptor List Pointer-Lower Base Address */
880 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD5BDPU) }, /* OSD5 Buffer Descriptor List Pointer-Upper Base Address */
881
882 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD6CTL) }, /* Output Stream Descriptor 6 (OSD6) Control */
883 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD6STS) }, /* OSD6 Status */
884 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6LPIB) }, /* OSD6 Link Position In Buffer */
885 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6CBL) }, /* OSD6 Cyclic Buffer Length */
886 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD6LVI) }, /* OSD6 Last Valid Index */
887 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD6FIFOW) }, /* OSD6 FIFO Watermark */
888 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD6FIFOS) }, /* OSD6 FIFO Size */
889 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD6FMT) }, /* OSD6 Format */
890 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD6BDPL) }, /* OSD6 Buffer Descriptor List Pointer-Lower Base Address */
891 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD6BDPU) }, /* OSD6 Buffer Descriptor List Pointer-Upper Base Address */
892
893 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD7CTL) }, /* Output Stream Descriptor 7 (OSD7) Control */
894 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD7STS) }, /* OSD7 Status */
895 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7LPIB) }, /* OSD7 Link Position In Buffer */
896 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7CBL) }, /* OSD7 Cyclic Buffer Length */
897 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD7LVI) }, /* OSD7 Last Valid Index */
898 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD7FIFOW) }, /* OSD7 FIFO Watermark */
899 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD7FIFOS) }, /* OSD7 FIFO Size */
900 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD7FMT) }, /* OSD7 Format */
901 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD7BDPL) }, /* OSD7 Buffer Descriptor List Pointer-Lower Base Address */
902 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD7BDPU) }, /* OSD7 Buffer Descriptor List Pointer-Upper Base Address */
903};
904
905/**
906 * HDA register aliases (HDA spec 3.3.45).
907 * @remarks Sorted by offReg.
908 */
909static const struct
910{
911 /** The alias register offset. */
912 uint32_t offReg;
913 /** The register index. */
914 int idxAlias;
915} g_aHdaRegAliases[] =
916{
917 { 0x2084, HDA_REG_SD0LPIB },
918 { 0x20a4, HDA_REG_SD1LPIB },
919 { 0x20c4, HDA_REG_SD2LPIB },
920 { 0x20e4, HDA_REG_SD3LPIB },
921 { 0x2104, HDA_REG_SD4LPIB },
922 { 0x2124, HDA_REG_SD5LPIB },
923 { 0x2144, HDA_REG_SD6LPIB },
924 { 0x2164, HDA_REG_SD7LPIB },
925};
926
927#ifdef IN_RING3
928/** HDABDLEDESC field descriptors the v3+ saved state. */
929static SSMFIELD const g_aHdaBDLEDescFields[] =
930{
931 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
932 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
933 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
934 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
935 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
936 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
937 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
938 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
939 SSMFIELD_ENTRY_TERM()
940};
941
942/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
943static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
944{
945 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
946 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
947 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
948 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
949 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
950 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
951 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
952 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
953 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
954 SSMFIELD_ENTRY_TERM()
955};
956#endif
957
958/**
959 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
960 */
961static uint32_t const g_afMasks[5] =
962{
963 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
964};
965
966#ifdef IN_RING3
967DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
968{
969 if (pThis->u64DPBase & DPBASE_ENABLED)
970 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
971 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
972 pStreamDesc->pu32Lpib, sizeof(uint32_t));
973}
974#endif
975
976DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
977{
978#if 0
979 switch(HDA_STREAM_REG(pThis, FIFOW, pStreamDesc->u8Strm))
980 {
981 case HDA_SDFIFOW_8B: return 8;
982 case HDA_SDFIFOW_16B: return 16;
983 case HDA_SDFIFOW_32B: return 32;
984 default:
985 AssertMsgFailed(("unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
986 }
987#endif
988 return 0;
989}
990
991static int hdaProcessInterrupt(PHDASTATE pThis)
992{
993#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
994 ( INTCTL_SX((pThis), num) \
995 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
996 bool fIrq = false;
997 if ( HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
998 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
999 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1000 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1001 fIrq = true;
1002
1003 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1004 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1005 fIrq = true;
1006
1007 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1008 {
1009 LogFunc(("irq %s\n", fIrq ? "asserted" : "deasserted"));
1010 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1011 }
1012 return VINF_SUCCESS;
1013}
1014
1015/**
1016 * Looks up a register at the exact offset given by @a offReg.
1017 *
1018 * @returns Register index on success, -1 if not found.
1019 * @param pThis The HDA device state.
1020 * @param offReg The register offset.
1021 */
1022static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1023{
1024 /*
1025 * Aliases.
1026 */
1027 if (offReg >= g_aHdaRegAliases[0].offReg)
1028 {
1029 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1030 if (offReg == g_aHdaRegAliases[i].offReg)
1031 return g_aHdaRegAliases[i].idxAlias;
1032 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1033 return -1;
1034 }
1035
1036 /*
1037 * Binary search the
1038 */
1039 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1040 int idxLow = 0;
1041 for (;;)
1042 {
1043 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1044 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1045 {
1046 if (idxLow == idxMiddle)
1047 break;
1048 idxEnd = idxMiddle;
1049 }
1050 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1051 {
1052 idxLow = idxMiddle + 1;
1053 if (idxLow >= idxEnd)
1054 break;
1055 }
1056 else
1057 return idxMiddle;
1058 }
1059
1060#ifdef RT_STRICT
1061 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1062 Assert(g_aHdaRegMap[i].offset != offReg);
1063#endif
1064 return -1;
1065}
1066
1067/**
1068 * Looks up a register covering the offset given by @a offReg.
1069 *
1070 * @returns Register index on success, -1 if not found.
1071 * @param pThis The HDA device state.
1072 * @param offReg The register offset.
1073 */
1074static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1075{
1076 /*
1077 * Aliases.
1078 */
1079 if (offReg >= g_aHdaRegAliases[0].offReg)
1080 {
1081 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1082 {
1083 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1084 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1085 return g_aHdaRegAliases[i].idxAlias;
1086 }
1087 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1088 return -1;
1089 }
1090
1091 /*
1092 * Binary search the
1093 */
1094 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1095 int idxLow = 0;
1096 for (;;)
1097 {
1098 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1099 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1100 {
1101 if (idxLow == idxMiddle)
1102 break;
1103 idxEnd = idxMiddle;
1104 }
1105 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1106 {
1107 idxLow = idxMiddle + 1;
1108 if (idxLow >= idxEnd)
1109 break;
1110 }
1111 else
1112 return idxMiddle;
1113 }
1114
1115#ifdef RT_STRICT
1116 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1117 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1118#endif
1119 return -1;
1120}
1121
1122#ifdef IN_RING3
1123static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1124{
1125 int rc = VINF_SUCCESS;
1126 if (fLocal)
1127 {
1128 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1129 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1130 if (RT_FAILURE(rc))
1131 AssertRCReturn(rc, rc);
1132#ifdef DEBUG_CMD_BUFFER
1133 uint8_t i = 0;
1134 do
1135 {
1136 LogFunc(("corb%02x: ", i));
1137 uint8_t j = 0;
1138 do
1139 {
1140 const char *prefix;
1141 if ((i + j) == HDA_REG(pThis, CORBRP));
1142 prefix = "[R]";
1143 else if ((i + j) == HDA_REG(pThis, CORBWP));
1144 prefix = "[W]";
1145 else
1146 prefix = " "; /* three spaces */
1147 LogFunc(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
1148 j++;
1149 } while (j < 8);
1150 LogFunc(("\n"));
1151 i += 8;
1152 } while(i != 0);
1153#endif
1154 }
1155 else
1156 {
1157 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1158 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1159 if (RT_FAILURE(rc))
1160 AssertRCReturn(rc, rc);
1161#ifdef DEBUG_CMD_BUFFER
1162 uint8_t i = 0;
1163 do {
1164 LogFunc(("rirb%02x: ", i));
1165 uint8_t j = 0;
1166 do {
1167 const char *prefix;
1168 if ((i + j) == HDA_REG(pThis, RIRBWP))
1169 prefix = "[W]";
1170 else
1171 prefix = " ";
1172 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1173 } while (++j < 8);
1174 LogFunc(("\n"));
1175 i += 8;
1176 } while (i != 0);
1177#endif
1178 }
1179 return rc;
1180}
1181
1182static int hdaCORBCmdProcess(PHDASTATE pThis)
1183{
1184 int rc;
1185 uint8_t corbRp;
1186 uint8_t corbWp;
1187 uint8_t rirbWp;
1188
1189 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1190
1191 rc = hdaCmdSync(pThis, true);
1192 if (RT_FAILURE(rc))
1193 AssertRCReturn(rc, rc);
1194 corbRp = HDA_REG(pThis, CORBRP);
1195 corbWp = HDA_REG(pThis, CORBWP);
1196 rirbWp = HDA_REG(pThis, RIRBWP);
1197 Assert((corbWp != corbRp));
1198 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1199 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1200 while (corbRp != corbWp)
1201 {
1202 uint32_t cmd;
1203 uint64_t resp;
1204 pfn = NULL;
1205 corbRp++;
1206 cmd = pThis->pu32CorbBuf[corbRp];
1207
1208 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1209 HDA_CODEC_CMD(cmd, 0 /* Codec index */),
1210 &pfn);
1211 if (RT_SUCCESS(rc))
1212 {
1213 rc = pfn(pThis->pCodec,
1214 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1215 }
1216
1217 if (RT_FAILURE(rc))
1218 AssertRCReturn(rc, rc);
1219 Assert(pfn);
1220 (rirbWp)++;
1221
1222 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1223 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1224 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1225 {
1226 LogFunc(("unexpected unsolicited response.\n"));
1227 HDA_REG(pThis, CORBRP) = corbRp;
1228 return rc;
1229 }
1230 pThis->pu64RirbBuf[rirbWp] = resp;
1231 pThis->u8Counter++;
1232 if (pThis->u8Counter == RINTCNT_N(pThis))
1233 break;
1234 }
1235 HDA_REG(pThis, CORBRP) = corbRp;
1236 HDA_REG(pThis, RIRBWP) = rirbWp;
1237 rc = hdaCmdSync(pThis, false);
1238 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1239 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1240 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1241 {
1242 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1243 pThis->u8Counter = 0;
1244 rc = hdaProcessInterrupt(pThis);
1245 }
1246 if (RT_FAILURE(rc))
1247 AssertRCReturn(rc, rc);
1248 return rc;
1249}
1250#endif
1251
1252static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
1253{
1254 LogFunc(("reset of stream (%d) started\n", u8Strm));
1255 Assert(( pThis
1256 && pBdle
1257 && pStreamDesc
1258 && u8Strm <= 7));
1259 RT_BZERO(pBdle, sizeof(HDABDLEDESC));
1260 *pStreamDesc->pu32Lpib = 0;
1261 *pStreamDesc->pu32Sts = 0;
1262 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1263 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
1264 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1265
1266 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1267 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1268 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
1269 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1270 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1271 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1272 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1273 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1274 LogFunc(("reset of stream (%d) finished\n", u8Strm));
1275}
1276
1277/* Register access handlers. */
1278
1279static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1280{
1281 *pu32Value = 0;
1282 return VINF_SUCCESS;
1283}
1284
1285static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1286{
1287 return VINF_SUCCESS;
1288}
1289
1290/* U8 */
1291static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1292{
1293 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1294 return hdaRegReadU32(pThis, iReg, pu32Value);
1295}
1296
1297static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1298{
1299 Assert((u32Value & 0xffffff00) == 0);
1300 return hdaRegWriteU32(pThis, iReg, u32Value);
1301}
1302
1303/* U16 */
1304static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1305{
1306 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1307 return hdaRegReadU32(pThis, iReg, pu32Value);
1308}
1309
1310static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1311{
1312 Assert((u32Value & 0xffff0000) == 0);
1313 return hdaRegWriteU32(pThis, iReg, u32Value);
1314}
1315
1316/* U24 */
1317static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1318{
1319 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1320 return hdaRegReadU32(pThis, iReg, pu32Value);
1321}
1322
1323static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1324{
1325 Assert((u32Value & 0xff000000) == 0);
1326 return hdaRegWriteU32(pThis, iReg, u32Value);
1327}
1328
1329/* U32 */
1330static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1331{
1332 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1333
1334 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1335 return VINF_SUCCESS;
1336}
1337
1338static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1339{
1340 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1341
1342 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1343 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1344 return VINF_SUCCESS;
1345}
1346
1347static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1348{
1349 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1350 {
1351 /* exit reset state */
1352 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1353 pThis->fInReset = false;
1354 }
1355 else
1356 {
1357#ifdef IN_RING3
1358 /* enter reset state*/
1359 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1360 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1361 {
1362 LogFunc(("HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1363 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1364 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1365 }
1366 hdaReset(pThis->CTX_SUFF(pDevIns));
1367 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1368 pThis->fInReset = true;
1369#else
1370 return VINF_IOM_R3_MMIO_WRITE;
1371#endif
1372 }
1373 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1374 {
1375 /* Flush: GSTS:1 set, see 6.2.6*/
1376 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1377 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1378 }
1379 return VINF_SUCCESS;
1380}
1381
1382static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1383{
1384 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1385
1386 uint32_t v = pThis->au32Regs[iRegMem];
1387 uint32_t nv = u32Value & HDA_STATES_SCSF;
1388 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1389 return VINF_SUCCESS;
1390}
1391
1392static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1393{
1394 uint32_t v = 0;
1395 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1396 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1397 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1398 || HDA_REG(pThis, STATESTS))
1399 v |= RT_BIT(30);
1400#define HDA_IS_STREAM_EVENT(pThis, stream) \
1401 ( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1402 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1403 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1404#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
1405 MARK_STREAM(pThis, 0, v);
1406 MARK_STREAM(pThis, 1, v);
1407 MARK_STREAM(pThis, 2, v);
1408 MARK_STREAM(pThis, 3, v);
1409 MARK_STREAM(pThis, 4, v);
1410 MARK_STREAM(pThis, 5, v);
1411 MARK_STREAM(pThis, 6, v);
1412 MARK_STREAM(pThis, 7, v);
1413 v |= v ? RT_BIT(31) : 0;
1414 *pu32Value = v;
1415 return VINF_SUCCESS;
1416}
1417
1418static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1419{
1420 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1421 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1422 - pThis->u64BaseTS, 24, 1000);
1423 return VINF_SUCCESS;
1424}
1425
1426static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1427{
1428 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1429 HDA_REG(pThis, CORBRP) = 0;
1430#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1431 else
1432 return hdaRegWriteU8(pThis, iReg, u32Value);
1433#endif
1434 return VINF_SUCCESS;
1435}
1436
1437static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1438{
1439#ifdef IN_RING3
1440 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1441 AssertRC(rc);
1442 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1443 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1444 return hdaCORBCmdProcess(pThis);
1445 return rc;
1446#else
1447 return VINF_IOM_R3_MMIO_WRITE;
1448#endif
1449}
1450
1451static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1452{
1453 uint32_t v = HDA_REG(pThis, CORBSTS);
1454 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1455 return VINF_SUCCESS;
1456}
1457
1458static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1459{
1460#ifdef IN_RING3
1461 int rc;
1462 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1463 if (RT_FAILURE(rc))
1464 AssertRCReturn(rc, rc);
1465 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1466 return VINF_SUCCESS;
1467 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1468 return VINF_SUCCESS;
1469 rc = hdaCORBCmdProcess(pThis);
1470 return rc;
1471#else
1472 return VINF_IOM_R3_MMIO_WRITE;
1473#endif
1474}
1475
1476static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1477{
1478 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1479 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1480 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1481 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1482
1483 if (fInReset)
1484 {
1485 /*
1486 * Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1487 * from reset
1488 */
1489 Assert((!fReset));
1490 LogFunc(("guest initiated exit of stream reset.\n"));
1491 }
1492 else if (fReset)
1493 {
1494#ifdef IN_RING3
1495 /*
1496 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1497 */
1498 uint8_t u8Strm = 0;
1499 PHDABDLEDESC pBdle = NULL;
1500 HDASTREAMTRANSFERDESC StreamDesc;
1501 Assert((!fInRun && !fRun));
1502 switch (iReg)
1503 {
1504 case HDA_REG_SD0CTL:
1505 u8Strm = 0;
1506 pBdle = &pThis->StInBdle;
1507 break;
1508#ifdef VBOX_WITH_HDA_MIC_IN
1509 case HDA_REG_SD2CTL:
1510 u8Strm = 2;
1511 pBdle = &pThis->StMicBdle;
1512 break;
1513#endif
1514 case HDA_REG_SD4CTL:
1515 u8Strm = 4;
1516 pBdle = &pThis->StOutBdle;
1517 break;
1518 default:
1519 LogFunc(("changing SRST bit on non-attached stream\n"));
1520 return hdaRegWriteU24(pThis, iReg, u32Value);
1521 }
1522 LogFunc(("guest initiated enter to stream reset.\n"));
1523 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1524 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
1525#else
1526 return VINF_IOM_R3_MMIO_WRITE;
1527#endif
1528 }
1529 else
1530 {
1531#ifdef IN_RING3
1532 /* we enter here to change DMA states only */
1533 if ( (fInRun && !fRun)
1534 || (fRun && !fInRun))
1535 {
1536 Assert((!fReset && !fInReset));
1537
1538 PHDADRIVER pDrv;
1539 switch (iReg)
1540 {
1541 case HDA_REG_SD0CTL:
1542 {
1543 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1544 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1545 pDrv->LineIn.pStrmIn, fRun);
1546 break;
1547 }
1548# ifdef VBOX_WITH_HDA_MIC_IN
1549 case HDA_REG_SD2CTL:
1550 {
1551 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1552 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1553 pDrv->MicIn.pStrmIn, fRun);
1554 break;
1555 }
1556# endif
1557 case HDA_REG_SD4CTL:
1558 {
1559 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1560 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1561 pDrv->Out.pStrmOut, fRun);
1562 break;
1563 }
1564 default:
1565 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1566 break;
1567 }
1568 }
1569#else /* !IN_RING3 */
1570 return VINF_IOM_R3_MMIO_WRITE;
1571#endif /* IN_RING3 */
1572 }
1573
1574 return hdaRegWriteU24(pThis, iReg, u32Value);
1575}
1576
1577static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1578{
1579 uint32_t v = HDA_REG_IND(pThis, iReg);
1580 v &= ~(u32Value & v);
1581 HDA_REG_IND(pThis, iReg) = v;
1582 hdaProcessInterrupt(pThis);
1583 return VINF_SUCCESS;
1584}
1585
1586static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1587{
1588 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1589 if (RT_FAILURE(rc))
1590 AssertRCReturn(rc, VINF_SUCCESS);
1591 return rc;
1592}
1593
1594static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1595{
1596 switch (u32Value)
1597 {
1598 case HDA_SDFIFOW_8B:
1599 case HDA_SDFIFOW_16B:
1600 case HDA_SDFIFOW_32B:
1601 return hdaRegWriteU16(pThis, iReg, u32Value);
1602 default:
1603 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1604 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1605 }
1606 return VINF_SUCCESS;
1607}
1608
1609/**
1610 * @note This method could be called for changing value on Output Streams
1611 * only (ICH6 datasheet 18.2.39)
1612 */
1613static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1614{
1615 switch (iReg)
1616 {
1617 /* SDInFIFOS is RO, n=0-3 */
1618 case HDA_REG_SD0FIFOS:
1619 case HDA_REG_SD1FIFOS:
1620 case HDA_REG_SD2FIFOS:
1621 case HDA_REG_SD3FIFOS:
1622 LogFunc(("Guest tries change value of FIFO size of input stream\n"));
1623 break;
1624 case HDA_REG_SD4FIFOS:
1625 case HDA_REG_SD5FIFOS:
1626 case HDA_REG_SD6FIFOS:
1627 case HDA_REG_SD7FIFOS:
1628 switch(u32Value)
1629 {
1630 case HDA_SDONFIFO_16B:
1631 case HDA_SDONFIFO_32B:
1632 case HDA_SDONFIFO_64B:
1633 case HDA_SDONFIFO_128B:
1634 case HDA_SDONFIFO_192B:
1635 return hdaRegWriteU16(pThis, iReg, u32Value);
1636
1637 case HDA_SDONFIFO_256B:
1638 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1639 default:
1640 return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);
1641 }
1642 break;
1643 default:
1644 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
1645 }
1646
1647 return VINF_SUCCESS;
1648}
1649
1650#ifdef IN_RING3
1651static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
1652{
1653 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1654
1655# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1656
1657 int rc = VINF_SUCCESS;
1658
1659 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1660 uint32_t u32HzMult = 1;
1661 uint32_t u32HzDiv = 1;
1662
1663 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
1664 {
1665 case 0: u32HzMult = 1; break;
1666 case 1: u32HzMult = 2; break;
1667 case 2: u32HzMult = 3; break;
1668 case 3: u32HzMult = 4; break;
1669 default:
1670 LogFunc(("Unsupported multiplier %x\n",
1671 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
1672 rc = VERR_NOT_SUPPORTED;
1673 break;
1674 }
1675 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
1676 {
1677 case 0: u32HzDiv = 1; break;
1678 case 1: u32HzDiv = 2; break;
1679 case 2: u32HzDiv = 3; break;
1680 case 3: u32HzDiv = 4; break;
1681 case 4: u32HzDiv = 5; break;
1682 case 5: u32HzDiv = 6; break;
1683 case 6: u32HzDiv = 7; break;
1684 case 7: u32HzDiv = 8; break;
1685 default:
1686 LogFunc(("Unsupported divisor %x\n",
1687 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
1688 rc = VERR_NOT_SUPPORTED;
1689 break;
1690 }
1691
1692 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1693 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
1694 {
1695 case 0:
1696 LogFunc(("Requested 8-bit\n"));
1697 enmFmt = AUD_FMT_S8;
1698 break;
1699 case 1:
1700 LogFunc(("Requested 16-bit\n"));
1701 enmFmt = AUD_FMT_S16;
1702 break;
1703 case 2:
1704 LogFunc(("Requested 20-bit\n"));
1705 break;
1706 case 3:
1707 LogFunc(("Requested 24-bit\n"));
1708 break;
1709 case 4:
1710 LogFunc(("Requested 32-bit\n"));
1711 enmFmt = AUD_FMT_S32;
1712 break;
1713 default:
1714 AssertMsgFailed(("Unsupported bits shift %x\n",
1715 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
1716 rc = VERR_NOT_SUPPORTED;
1717 break;
1718 }
1719
1720 if (RT_SUCCESS(rc))
1721 {
1722 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
1723 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
1724 pCfg->enmFormat = enmFmt;
1725 pCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
1726 }
1727
1728# undef EXTRACT_VALUE
1729
1730 return rc;
1731}
1732#endif
1733
1734static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1735{
1736#ifdef IN_RING3
1737# ifdef VBOX_WITH_HDA_CODEC_EMU
1738 /* No reason to reopen voice with same settings. */
1739 if (u32Value == HDA_REG_IND(pThis, iReg))
1740 return VINF_SUCCESS;
1741
1742 PDMAUDIOSTREAMCFG as;
1743 int rc = hdaSdFmtToAudSettings(u32Value, &as);
1744 if (RT_FAILURE(rc))
1745 return rc;
1746
1747 PHDADRIVER pDrv;
1748 switch (iReg)
1749 {
1750 case HDA_REG_SD0FMT:
1751 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1752 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &as);
1753 break;
1754# ifdef VBOX_WITH_HDA_MIC_IN
1755 case HDA_REG_SD2FMT:
1756 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1757 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &as);
1758 break;
1759# endif
1760 default:
1761 LogFunc(("Warning: Attempt to change format on register %d\n", iReg));
1762 break;
1763 }
1764
1765 /** @todo r=andy rc gets lost; needs fixing. */
1766 return hdaRegWriteU16(pThis, iReg, u32Value);
1767# else /* !VBOX_WITH_HDA_CODEC_EMU */
1768 return hdaRegWriteU16(pThis, iReg, u32Value);
1769# endif
1770#else /* !IN_RING3 */
1771 return VINF_IOM_R3_MMIO_WRITE;
1772#endif
1773}
1774
1775static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1776{
1777 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1778 if (RT_FAILURE(rc))
1779 AssertRCReturn(rc, VINF_SUCCESS);
1780 return rc;
1781}
1782
1783static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1784{
1785 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1786 if (RT_FAILURE(rc))
1787 AssertRCReturn(rc, VINF_SUCCESS);
1788 return rc;
1789}
1790
1791static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1792{
1793 int rc = VINF_SUCCESS;
1794 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1795 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1796 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1797 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1798
1799 rc = hdaRegReadU32(pThis, iReg, pu32Value);
1800 return rc;
1801}
1802
1803static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1804{
1805 int rc = VINF_SUCCESS;
1806
1807 /*
1808 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1809 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1810 */
1811 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1812 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
1813 {
1814#ifdef IN_RING3
1815 PFNHDACODECVERBPROCESSOR pfn = NULL;
1816 uint64_t resp;
1817 uint32_t cmd = HDA_REG(pThis, IC);
1818 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
1819 {
1820 /*
1821 * 3.4.3 defines behavior of immediate Command status register.
1822 */
1823 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
1824 return rc;
1825 }
1826 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1827 LogFunc(("IC:%x\n", cmd));
1828
1829 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1830 HDA_CODEC_CMD(cmd, 0 /* LUN */),
1831 &pfn);
1832 if (RT_FAILURE(rc))
1833 AssertRCReturn(rc, rc);
1834 rc = pfn(pThis->pCodec,
1835 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1836 if (RT_FAILURE(rc))
1837 AssertRCReturn(rc, rc);
1838
1839 HDA_REG(pThis, IR) = (uint32_t)resp;
1840 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
1841 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1842 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1843#else /* !IN_RING3 */
1844 rc = VINF_IOM_R3_MMIO_WRITE;
1845#endif
1846 return rc;
1847 }
1848 /*
1849 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1850 */
1851 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1852 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
1853 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1854 return rc;
1855}
1856
1857static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1858{
1859 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1860 {
1861 HDA_REG(pThis, RIRBWP) = 0;
1862 }
1863 /* The remaining bits are O, see 6.2.22 */
1864 return VINF_SUCCESS;
1865}
1866
1867static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1868{
1869 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1870 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1871 if (RT_FAILURE(rc))
1872 AssertRCReturn(rc, rc);
1873
1874 switch(iReg)
1875 {
1876 case HDA_REG_CORBLBASE:
1877 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
1878 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
1879 break;
1880 case HDA_REG_CORBUBASE:
1881 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
1882 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1883 break;
1884 case HDA_REG_RIRBLBASE:
1885 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
1886 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
1887 break;
1888 case HDA_REG_RIRBUBASE:
1889 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
1890 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1891 break;
1892 case HDA_REG_DPLBASE:
1893 /** @todo: first bit has special meaning */
1894 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
1895 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
1896 break;
1897 case HDA_REG_DPUBASE:
1898 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
1899 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1900 break;
1901 default:
1902 AssertMsgFailed(("Invalid index"));
1903 break;
1904 }
1905
1906 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
1907 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
1908 return rc;
1909}
1910
1911static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1912{
1913 uint8_t v = HDA_REG(pThis, RIRBSTS);
1914 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
1915
1916 return hdaProcessInterrupt(pThis);
1917}
1918
1919#ifdef IN_RING3
1920#ifdef LOG_ENABLED
1921static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1922{
1923#if 0
1924 uint64_t addr;
1925 uint32_t len;
1926 uint32_t ioc;
1927 uint8_t bdle[16];
1928 uint32_t counter;
1929 uint32_t i;
1930 uint32_t sum = 0;
1931 Assert(pBdle && pBdle->u32BdleMaxCvi);
1932 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1933 {
1934 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i*16, bdle, 16);
1935 addr = *(uint64_t *)bdle;
1936 len = *(uint32_t *)&bdle[8];
1937 ioc = *(uint32_t *)&bdle[12];
1938 LogFunc(("%s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1939 sum += len;
1940 }
1941 LogFunc(("sum: %d\n", sum));
1942 for (i = 0; i < 8; ++i)
1943 {
1944 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1945 LogFunc(("%s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
1946 i , counter));
1947 }
1948#endif
1949}
1950#endif
1951
1952static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1953{
1954 uint8_t bdle[16];
1955 Assert(( pStreamDesc->u64BaseDMA
1956 && pBdle
1957 && pBdle->u32BdleMaxCvi));
1958 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1959 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1960 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1961 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1962#ifdef LOG_ENABLED
1963 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
1964#endif
1965}
1966
1967DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1968 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1969{
1970 /*
1971 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
1972 */
1973 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1974 uint32_t cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1975 /*
1976 * we may increase the counter in range of [0, FIFOS + 1]
1977 */
1978 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1979 Assert((u32SoundBackendBufferBytesAvail > 0));
1980
1981 /* sanity check to avoid overriding the backend audio buffer */
1982 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1983 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1984
1985 if (cb2Copy <= pBdle->cbUnderFifoW)
1986 return 0;
1987 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
1988 return cb2Copy;
1989}
1990
1991DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1992 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1993{
1994 LogFunc(("cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1995 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1996 Assert((cbCopied));
1997 AssertPtr(pu32DMACursor);
1998 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1999 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
2000 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2001 * where it might happen.
2002 */
2003 AssertMsg((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy), /* we assume that we write the entire buffer including unreported bytes */
2004 ("cbCopied=%RU32 != pBdle->cbUnderFifoW=%RU32 + cbArranged2Copy=%RU32\n",
2005 cbCopied, pBdle->cbUnderFifoW, cbArranged2Copy));
2006 if ( pBdle->cbUnderFifoW
2007 && pBdle->cbUnderFifoW <= cbCopied)
2008 {
2009 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n",
2010 pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2011 }
2012
2013 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
2014 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
2015
2016 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
2017 pBdle->u32BdleCviPos += cbArranged2Copy;
2018
2019 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
2020 /* We report all bytes (including previously unreported bytes) */
2021 *pu32DMACursor += cbCopied;
2022 /* Decrease the backend counter by the number of bytes we copied to the backend */
2023 *pu32BackendBufferCapacity -= cbCopied;
2024 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2025 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
2026}
2027
2028DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2029 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2030{
2031 Assert((cbCopied, cbArranged2Copy));
2032 *pu32BackendBufferCapacity -= cbCopied;
2033 pBdle->u32BdleCviPos += cbCopied;
2034 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2035 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
2036 pBdle->cbUnderFifoW = 0;
2037 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2038 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2039}
2040
2041DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2042 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
2043{
2044 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2045 pBdle->u32BdleCviPos += cbCopied;
2046 pBdle->cbUnderFifoW += cbCopied;
2047 /* In case of a read transaction we're always copying from the backend buffer */
2048 if (pu32BackendBufferCapacity)
2049 *pu32BackendBufferCapacity -= cbCopied;
2050 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2051 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
2052}
2053
2054DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2055{
2056 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
2057 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
2058
2059 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2060
2061 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2062 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
2063 hdaUpdatePosBuf(pThis, pStreamDesc);
2064
2065 /* don't touch BdleCvi counter on uninitialized descriptor */
2066 if ( pBdle->u32BdleCviPos
2067 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
2068 {
2069 pBdle->u32BdleCviPos = 0;
2070 pBdle->u32BdleCvi++;
2071 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
2072 pBdle->u32BdleCvi = 0;
2073 }
2074 return fOnBufferEdge;
2075}
2076
2077DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2078 uint32_t cbInc)
2079{
2080 /*
2081 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
2082 * (ICH6 datasheet 18.2.38)
2083 */
2084 if (!pBdle->cbUnderFifoW)
2085 {
2086 *pStreamDesc->pu32Lpib += cbInc;
2087
2088 /*
2089 * Assert. The buffer counters should never overlap.
2090 */
2091 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2092
2093 hdaUpdatePosBuf(pThis, pStreamDesc);
2094 }
2095}
2096
2097static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2098{
2099 bool fDoNextTransferLoop = true;
2100 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
2101 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2102 {
2103 if ( !pBdle->cbUnderFifoW
2104 && pBdle->fBdleCviIoc)
2105 {
2106 /**
2107 * @todo - more carefully investigate BCIS flag.
2108 * Speech synthesis works fine on Mac Guest if this bit isn't set
2109 * but in general sound quality gets worse.
2110 */
2111 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2112
2113 /*
2114 * we should generate the interrupt if ICE bit of SDCTL register is set.
2115 */
2116 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2117 hdaProcessInterrupt(pThis);
2118 }
2119 fDoNextTransferLoop = false;
2120 }
2121 return fDoNextTransferLoop;
2122}
2123
2124/**
2125 * hdaReadAudio - copies samples from audio backend to DMA.
2126 * Note: This function writes to the DMA buffer immediately,
2127 * but "reports bytes" when all conditions are met (FIFOW).
2128 */
2129static int hdaReadAudio(PHDASTATE pThis, PAUDMIXSINK pSink,
2130 PHDASTREAMTRANSFERDESC pStreamDesc,
2131 uint32_t u32CblLimit, uint32_t *pcbAvail, uint32_t *pcbRead)
2132{
2133 PHDABDLEDESC pBdle = &pThis->StInBdle; /** @todo Add support for mic in. */
2134
2135 int rc;
2136 uint32_t cbTransferred = 0;
2137
2138 LogFlowFunc(("CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2139
2140 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2141 if (!cb2Copy)
2142 {
2143 /* If we enter here we can't report "unreported bits". */
2144 rc = VERR_NO_DATA;
2145 }
2146 else
2147 {
2148 uint32_t cbRead = 0;
2149 rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pBdle->au8HdaBuffer, cb2Copy, &cbRead);
2150 if (RT_SUCCESS(rc))
2151 {
2152 Assert(cbRead);
2153
2154 /*
2155 * Write the HDA DMA buffer.
2156 */
2157 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2158 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2159 pBdle->au8HdaBuffer, cbRead);
2160
2161 /* Don't see any reason why cb2Copy would differ from cbRead. */
2162 Assert((cbRead == cb2Copy && (*pcbAvail) >= cb2Copy)); /* sanity */
2163
2164 if (pBdle->cbUnderFifoW + cbRead > hdaFifoWToSz(pThis, 0))
2165 hdaBackendReadTransferReported(pBdle, cb2Copy, cbRead, &cbTransferred, pcbAvail);
2166 else
2167 {
2168 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbRead, pcbAvail);
2169 rc = VERR_NO_DATA;
2170 }
2171 }
2172 }
2173
2174 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2175 LogFunc(("CVI(pos:%RU32, len:%RU32), cbTransferred=%RU32, rc=%Rrc\n",
2176 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2177
2178 if (RT_SUCCESS(rc))
2179 *pcbRead = cbTransferred;
2180
2181 return rc;
2182}
2183
2184static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32CblLimit,
2185 uint32_t *pcbAvail, uint32_t *pcbWritten)
2186{
2187 PHDABDLEDESC pBdle = &pThis->StOutBdle;
2188
2189 int rc = VINF_SUCCESS;
2190
2191 uint32_t cbTransferred = 0;
2192 uint32_t cbWrittenMin = 0; /* local byte counter, how many bytes copied to backend */
2193
2194 LogFunc(("CVI(cvi:%RU32, pos:%RU32, len:%RU32)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2195
2196 /* Local byte counter (on local buffer). */
2197 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2198
2199 /*
2200 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
2201 * previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
2202 */
2203 if (!cb2Copy)
2204 {
2205 rc = VINF_EOF;
2206 }
2207 else
2208 {
2209 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2210 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2211 pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
2212
2213#ifdef VBOX_WITH_STATISTICS
2214 STAM_COUNTER_ADD(&pThis->StatBytesRead, cb2Copy);
2215#endif
2216
2217 /*
2218 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2219 */
2220 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
2221 {
2222 uint32_t cbWritten;
2223 cbWrittenMin = UINT32_MAX;
2224
2225 PHDADRIVER pDrv;
2226 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2227 {
2228 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2229 {
2230 int rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2231 pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW,
2232 &cbWritten);
2233 if (RT_FAILURE(rc2))
2234 continue;
2235 }
2236 else /* Stream disabled, just assume all was copied. */
2237 cbWritten = cb2Copy;
2238
2239 cbWrittenMin = RT_MIN(cbWrittenMin, cbWritten);
2240 LogFlowFunc(("\tLUN#%RU8: cbWritten=%RU32, cWrittenMin=%RU32\n", pDrv->uLUN, cbWritten, cbWrittenMin));
2241 }
2242
2243 if (cbWrittenMin == UINT32_MAX)
2244 cbWrittenMin = 0;
2245
2246 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbWrittenMin, &cbTransferred, pcbAvail);
2247 }
2248 else
2249 {
2250 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2251 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
2252 rc = VINF_EOF;
2253 }
2254 }
2255
2256 Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
2257 LogFunc(("CVI(pos:%RU32, len:%RU32, cbTransferred:%RU32), rc=%Rrc\n",
2258 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2259
2260 if (RT_SUCCESS(rc))
2261 *pcbWritten = cbTransferred;
2262
2263 return rc;
2264}
2265
2266/**
2267 * @interface_method_impl{HDACODEC,pfnReset}
2268 */
2269DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2270{
2271 PHDASTATE pThis = pCodec->pHDAState;
2272 NOREF(pThis);
2273 return VINF_SUCCESS;
2274}
2275
2276DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
2277 PHDASTREAMTRANSFERDESC pStreamDesc)
2278{
2279 Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
2280
2281 RT_BZERO(pStreamDesc, sizeof(HDASTREAMTRANSFERDESC));
2282 pStreamDesc->u8Strm = u8Strm;
2283 pStreamDesc->u32Ctl = HDA_STREAM_REG(pThis, CTL, u8Strm);
2284 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2285 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2286 pStreamDesc->pu32Lpib = &HDA_STREAM_REG(pThis, LPIB, u8Strm);
2287 pStreamDesc->pu32Sts = &HDA_STREAM_REG(pThis, STS, u8Strm);
2288 pStreamDesc->u32Cbl = HDA_STREAM_REG(pThis, CBL, u8Strm);
2289 pStreamDesc->u32Fifos = HDA_STREAM_REG(pThis, FIFOS, u8Strm);
2290
2291 pBdle->u32BdleMaxCvi = HDA_STREAM_REG(pThis, LVI, u8Strm);
2292
2293#ifdef LOG_ENABLED
2294 if ( pBdle
2295 && pBdle->u32BdleMaxCvi)
2296 {
2297 LogFunc(("Initialization of transfer descriptor:\n"));
2298 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2299 }
2300#endif
2301}
2302
2303static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2304{
2305 NOREF(pThis);
2306 NOREF(enmRecSource);
2307 LogFlowFuncEnter();
2308}
2309
2310static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2311{
2312 NOREF(pThis);
2313 LogFlowFuncEnter();
2314}
2315
2316static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2317 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2318 PPDMAUDIOSTREAMCFG pCfg)
2319{
2320 PAUDMIXSINK pSink;
2321
2322 switch (enmRecSource)
2323 {
2324# ifdef VBOX_WITH_HDA_MIC_IN
2325 case PDMAUDIORECSOURCE_MIC:
2326 pSink = pThis->pSinkMicIn;
2327 break;
2328# endif
2329 case PDMAUDIORECSOURCE_LINE_IN:
2330 pSink = pThis->pSinkLineIn;
2331 break;
2332 default:
2333 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2334 return VERR_NOT_SUPPORTED;
2335 }
2336
2337 int rc = VINF_SUCCESS;
2338 char *pszDesc;
2339
2340 PHDADRIVER pDrv;
2341 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2342 {
2343 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2344 {
2345 rc = VERR_NO_MEMORY;
2346 break;
2347 }
2348
2349 rc = pDrv->pConnector->pfnOpenIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2350 LogFlowFunc(("LUN#%RU8: Opened input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2351 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2352 {
2353 AudioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2354 rc = AudioMixerAddStreamIn(pSink,
2355 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2356 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2357 }
2358
2359 RTStrFree(pszDesc);
2360 }
2361
2362 LogFlowFuncLeaveRC(rc);
2363 return rc;
2364}
2365
2366static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2367 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2368{
2369 int rc = VINF_SUCCESS;
2370 char *pszDesc;
2371
2372 PHDADRIVER pDrv;
2373 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2374 {
2375 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2376 {
2377 rc = VERR_NO_MEMORY;
2378 break;
2379 }
2380
2381 rc = pDrv->pConnector->pfnOpenOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
2382 LogFlowFunc(("LUN#%RU8: Opened output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2383 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2384 {
2385 AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
2386 rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
2387 pDrv->pConnector, pDrv->Out.pStrmOut,
2388 0 /* uFlags */, &pDrv->Out.phStrmOut);
2389 }
2390
2391 RTStrFree(pszDesc);
2392 }
2393
2394 LogFlowFuncLeaveRC(rc);
2395 return rc;
2396}
2397
2398static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis, ENMSOUNDSOURCE enmSource,
2399 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2400{
2401 int rc = VINF_SUCCESS;
2402 PDMAUDIOVOLUME vol = { fMute, uVolLeft, uVolRight };
2403 PAUDMIXSINK pSink;
2404
2405 /* Convert the audio source to corresponding sink. */
2406 switch (enmSource) {
2407 case PO_INDEX:
2408 pSink = pThis->pSinkOutput;
2409 break;
2410 case PI_INDEX:
2411 pSink = pThis->pSinkLineIn;
2412 break;
2413 case MC_INDEX:
2414 pSink = pThis->pSinkMicIn;
2415 break;
2416 default:
2417 AssertFailedReturn(VERR_INVALID_PARAMETER);
2418 }
2419
2420 /* Set the volume. Codec already converted it to the correct range. */
2421 AudioMixerSetSinkVolume(pSink, &vol);
2422
2423 LogFlowFuncLeaveRC(rc);
2424 return rc;
2425}
2426
2427static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2428{
2429 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2430 AssertPtr(pThis);
2431
2432 STAM_PROFILE_START(&pThis->StatTimer, a);
2433
2434 int rc = VINF_SUCCESS;
2435
2436 uint32_t cbInMax = 0;
2437 uint32_t cbOutMin = UINT32_MAX;
2438
2439 PHDADRIVER pDrv;
2440
2441 uint32_t cbIn, cbOut, cSamplesLive;
2442 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2443 {
2444 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2445 &cbIn, &cbOut, &cSamplesLive);
2446 if (RT_SUCCESS(rc))
2447 {
2448#ifdef DEBUG_TIMER
2449 LogFlowFunc(("\tLUN#%RU8: [1] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2450#endif
2451 if (cSamplesLive)
2452 {
2453 uint32_t cSamplesPlayed;
2454 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2455 if (RT_SUCCESS(rc2))
2456 LogFlowFunc(("LUN#%RU8: cSamplesLive=%RU32, cSamplesPlayed=%RU32\n",
2457 pDrv->uLUN, cSamplesLive, cSamplesPlayed));
2458
2459 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2460 &cbIn, &cbOut, &cSamplesLive);
2461#ifdef DEBUG_TIMER
2462 if (RT_SUCCESS(rc))
2463 LogFlowFunc(("\tLUN#%RU8: [2] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2464#endif
2465 }
2466
2467 cbInMax = RT_MAX(cbInMax, cbIn);
2468 cbOutMin = RT_MIN(cbOutMin, cbOut);
2469 }
2470 }
2471
2472#ifdef DEBUG_TIMER
2473 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
2474#endif
2475
2476 if (cbOutMin == UINT32_MAX)
2477 cbOutMin = 0;
2478
2479 /*
2480 * Playback.
2481 */
2482 if (cbOutMin)
2483 {
2484 Assert(cbOutMin != UINT32_MAX);
2485 hdaTransfer(pThis, PO_INDEX, cbOutMin); /** @todo Add rc! */
2486 }
2487
2488 /*
2489 * Recording.
2490 */
2491 if (cbInMax)
2492 hdaTransfer(pThis, PI_INDEX, cbInMax); /** @todo Add rc! */
2493
2494 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
2495
2496 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2497}
2498
2499static DECLCALLBACK(int) hdaTransfer(PHDASTATE pThis,
2500 ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2501{
2502 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2503
2504 LogFlowFunc(("pThis=%p, cbAvail=%RU32\n", pThis, cbAvail));
2505
2506 uint8_t u8Strm;
2507 PHDABDLEDESC pBdle;
2508
2509 switch (enmSrc)
2510 {
2511 case PI_INDEX:
2512 {
2513 u8Strm = 0;
2514 pBdle = &pThis->StInBdle;
2515 break;
2516 }
2517
2518#ifdef VBOX_WITH_HDA_MIC_IN
2519 case MC_INDEX:
2520 {
2521 u8Strm = 2;
2522 pBdle = &pThis->StMicBdle;
2523 break;
2524 }
2525#endif
2526 case PO_INDEX:
2527 {
2528 u8Strm = 4;
2529 pBdle = &pThis->StOutBdle;
2530 break;
2531 }
2532
2533 default:
2534 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
2535 return VERR_NOT_SUPPORTED;
2536 }
2537
2538 HDASTREAMTRANSFERDESC StreamDesc;
2539 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2540
2541 int rc = VINF_EOF;
2542 while (cbAvail)
2543 {
2544 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
2545 && cbAvail
2546 && StreamDesc.u64BaseDMA);
2547
2548 /* Fetch the Buffer Descriptor Entry (BDE). */
2549 if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
2550 hdaFetchBdle(pThis, pBdle, &StreamDesc);
2551
2552 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2553 Assert((StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib))); /* sanity */
2554 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
2555 Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
2556
2557 LogFunc(("CBL=%RU32, LPIB=%RU32\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
2558
2559 PAUDMIXSINK pSink;
2560 uint32_t cbWritten = 0;
2561 switch (enmSrc)
2562 {
2563 case PI_INDEX:
2564 pSink = pThis->pSinkLineIn;
2565 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2566 break;
2567 case PO_INDEX:
2568 rc = hdaWriteAudio(pThis, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2569 break;
2570#ifdef VBOX_WITH_HDA_MIC_IN
2571 case MC_INDEX:
2572 pSink = pThis->pSinkMicIn;
2573 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2574 break;
2575#endif
2576 default:
2577 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
2578 rc = VERR_NOT_SUPPORTED;
2579 break;
2580 }
2581 Assert(cbWritten <= StreamDesc.u32Fifos + 1);
2582 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2583
2584 /* Process end of buffer condition. */
2585 hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cbWritten);
2586
2587 if (!hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc))
2588 break;
2589
2590 if ( RT_FAILURE(rc)
2591 || rc == VINF_EOF) /* All data processed? */
2592 {
2593 break;
2594 }
2595 }
2596
2597 return rc;
2598}
2599#endif /* IN_RING3 */
2600
2601/* MMIO callbacks */
2602
2603/**
2604 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
2605 *
2606 * @note During implementation, we discovered so-called "forgotten" or "hole"
2607 * registers whose description is not listed in the RPM, datasheet, or
2608 * spec.
2609 */
2610PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2611{
2612 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2613 int rc;
2614
2615 /*
2616 * Look up and log.
2617 */
2618 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2619 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
2620#ifdef LOG_ENABLED
2621 unsigned const cbLog = cb;
2622 uint32_t offRegLog = offReg;
2623#endif
2624
2625 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
2626#define NEW_READ_CODE
2627#ifdef NEW_READ_CODE
2628 Assert(cb == 4); Assert((offReg & 3) == 0);
2629
2630 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2631 LogFunc(("access to registers except GCTL is blocked while reset\n"));
2632
2633 if (idxRegDsc == -1)
2634 LogRel(("Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
2635
2636 if (idxRegDsc != -1)
2637 {
2638 /* ASSUMES gapless DWORD at end of map. */
2639 if (g_aHdaRegMap[idxRegDsc].size == 4)
2640 {
2641 /*
2642 * Straight forward DWORD access.
2643 */
2644 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
2645 LogFunc(("read %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
2646 }
2647 else
2648 {
2649 /*
2650 * Multi register read (unless there are trailing gaps).
2651 * ASSUMES that only DWORD reads have sideeffects.
2652 */
2653 uint32_t u32Value = 0;
2654 unsigned cbLeft = 4;
2655 do
2656 {
2657 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
2658 uint32_t u32Tmp = 0;
2659
2660 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
2661 LogFunc(("read %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
2662 if (rc != VINF_SUCCESS)
2663 break;
2664 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
2665
2666 cbLeft -= cbReg;
2667 offReg += cbReg;
2668 idxRegDsc++;
2669 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
2670
2671 if (rc == VINF_SUCCESS)
2672 *(uint32_t *)pv = u32Value;
2673 else
2674 Assert(!IOM_SUCCESS(rc));
2675 }
2676 }
2677 else
2678 {
2679 rc = VINF_IOM_MMIO_UNUSED_FF;
2680 LogFunc(("hole at %x is accessed for read\n", offReg));
2681 }
2682#else
2683 if (idxRegDsc != -1)
2684 {
2685 /** @todo r=bird: Accesses crossing register boundraries aren't handled
2686 * right from what I can tell? If they are, please explain
2687 * what the rules are. */
2688 uint32_t mask = 0;
2689 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2690 uint32_t u32Value = 0;
2691 switch(cb)
2692 {
2693 case 1: mask = 0x000000ff; break;
2694 case 2: mask = 0x0000ffff; break;
2695 case 4:
2696 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2697 case 8:
2698 mask = 0xffffffff;
2699 cb = 4;
2700 break;
2701 }
2702#if 0
2703 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
2704 */
2705 //Assert((cb <= g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset)));
2706 if (cb > g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset))
2707 {
2708 int off = cb - (g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset));
2709 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2710 if (RT_FAILURE(rc))
2711 AssertRCReturn (rc, rc);
2712 }
2713 //Assert(((offReg - g_aHdaRegMap[idxRegDsc].offset) == 0));
2714#endif
2715 mask <<= shift;
2716 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Value);
2717 *(uint32_t *)pv |= (u32Value & mask);
2718 LogFunc(("read %s[%x/%x]\n", g_aHdaRegMap[idxRegDsc].abbrev, u32Value, *(uint32_t *)pv));
2719 }
2720 else
2721 {
2722 *(uint32_t *)pv = 0xFF;
2723 LogFunc(("hole at %x is accessed for read\n", offReg));
2724 rc = VINF_SUCCESS;
2725 }
2726#endif
2727
2728 /*
2729 * Log the outcome.
2730 */
2731#ifdef LOG_ENABLED
2732 if (cbLog == 4)
2733 LogFunc(("@%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
2734 else if (cbLog == 2)
2735 LogFunc(("@%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
2736 else if (cbLog == 1)
2737 LogFunc(("@%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
2738#endif
2739 return rc;
2740}
2741
2742
2743DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
2744{
2745 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2746 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
2747
2748 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2749#ifdef LOG_ENABLED
2750 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
2751#endif
2752 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
2753 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
2754 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
2755 return rc;
2756}
2757
2758
2759/**
2760 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
2761 */
2762PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2763{
2764 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2765 int rc;
2766
2767 /*
2768 * The behavior of accesses that aren't aligned on natural boundraries is
2769 * undefined. Just reject them outright.
2770 */
2771 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
2772 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
2773 if (GCPhysAddr & (cb - 1))
2774 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
2775
2776 /*
2777 * Look up and log the access.
2778 */
2779 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2780 int idxRegDsc = hdaRegLookup(pThis, offReg);
2781 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
2782 uint64_t u64Value;
2783 if (cb == 4) u64Value = *(uint32_t const *)pv;
2784 else if (cb == 2) u64Value = *(uint16_t const *)pv;
2785 else if (cb == 1) u64Value = *(uint8_t const *)pv;
2786 else if (cb == 8) u64Value = *(uint64_t const *)pv;
2787 else
2788 {
2789 u64Value = 0; /* shut up gcc. */
2790 AssertReleaseMsgFailed(("%d\n", cb));
2791 }
2792
2793#ifdef LOG_ENABLED
2794 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
2795 uint32_t const offRegLog = offReg;
2796 int const idxRegLog = idxRegMem;
2797 if (idxRegDsc == -1)
2798 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
2799 else if (cb == 4)
2800 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2801 else if (cb == 2)
2802 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2803 else if (cb == 1)
2804 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2805 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
2806 LogFunc(("size=%d != cb=%d!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
2807#endif
2808
2809#define NEW_WRITE_CODE
2810#ifdef NEW_WRITE_CODE
2811 /*
2812 * Try for a direct hit first.
2813 */
2814 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
2815 {
2816 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
2817 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2818 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2819 }
2820 /*
2821 * Partial or multiple register access, loop thru the requested memory.
2822 */
2823 else
2824 {
2825 /* If it's an access beyond the start of the register, shift the input
2826 value and fill in missing bits. Natural alignment rules means we
2827 will only see 1 or 2 byte accesses of this kind, so no risk of
2828 shifting out input values. */
2829 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
2830 {
2831 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
2832 offReg -= cbBefore;
2833 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2834 u64Value <<= cbBefore * 8;
2835 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
2836 LogFunc(("Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
2837 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
2838 }
2839
2840 /* Loop thru the write area, it may cover multiple registers. */
2841 rc = VINF_SUCCESS;
2842 for (;;)
2843 {
2844 uint32_t cbReg;
2845 if (idxRegDsc != -1)
2846 {
2847 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2848 cbReg = g_aHdaRegMap[idxRegDsc].size;
2849 if (cb < cbReg)
2850 {
2851 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
2852 LogFunc(("Supplying missing bits (%#x): %#llx -> %#llx ...\n",
2853 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
2854 }
2855 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
2856 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
2857 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldVal,
2858 pThis->au32Regs[idxRegMem]));
2859 }
2860 else
2861 {
2862 LogRel(("HDA: Invalid write access @0x%x!\n", offReg));
2863 cbReg = 1;
2864 }
2865 if (rc != VINF_SUCCESS)
2866 break;
2867 if (cbReg >= cb)
2868 break;
2869
2870 /* advance */
2871 offReg += cbReg;
2872 cb -= cbReg;
2873 u64Value >>= cbReg * 8;
2874 if (idxRegDsc == -1)
2875 idxRegDsc = hdaRegLookup(pThis, offReg);
2876 else
2877 {
2878 idxRegDsc++;
2879 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
2880 || g_aHdaRegMap[idxRegDsc].offset != offReg)
2881 idxRegDsc = -1;
2882 }
2883 }
2884 }
2885#else
2886 if (idxRegDsc != -1)
2887 {
2888 /** @todo r=bird: This looks like code for handling unaligned register
2889 * accesses. If it isn't, then add a comment explaining what you're
2890 * trying to do here. OTOH, if it is then it has the following
2891 * issues:
2892 * -# You're calculating the wrong new value for the register.
2893 * -# You're not handling cross register accesses. Imagine a
2894 * 4-byte write starting at CORBCTL, or a 8-byte write.
2895 *
2896 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
2897 * nobody seems to be using it and it just adds complexity when reading
2898 * the code.
2899 *
2900 */
2901 uint32_t u32CurValue = pThis->au32Regs[idxRegMem];
2902 uint32_t u32NewValue;
2903 uint32_t mask;
2904 switch (cb)
2905 {
2906 case 1:
2907 u32NewValue = *(uint8_t const *)pv;
2908 mask = 0xff;
2909 break;
2910 case 2:
2911 u32NewValue = *(uint16_t const *)pv;
2912 mask = 0xffff;
2913 break;
2914 case 4:
2915 case 8:
2916 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2917 u32NewValue = *(uint32_t const *)pv;
2918 mask = 0xffffffff;
2919 cb = 4;
2920 break;
2921 default:
2922 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
2923 }
2924 /* cross-register access, see corresponding comment in hdaMMIORead */
2925 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2926 mask <<= shift;
2927 u32NewValue <<= shift;
2928 u32NewValue &= mask;
2929 u32NewValue |= (u32CurValue & ~mask);
2930
2931 rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32NewValue);
2932 LogFunc(("write %s:(%x) %x => %x\n", g_aHdaRegMap[idxRegDsc].abbrev, u32NewValue,
2933 u32CurValue, pThis->au32Regs[idxRegMem]));
2934 }
2935 else
2936 rc = VINF_SUCCESS;
2937
2938 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2939 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2940#endif
2941 return rc;
2942}
2943
2944
2945/* PCI callback. */
2946
2947#ifdef IN_RING3
2948/**
2949 * @callback_method_impl{FNPCIIOREGIONMAP}
2950 */
2951static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
2952 PCIADDRESSSPACE enmType)
2953{
2954 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2955 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
2956 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
2957 int rc;
2958
2959 /*
2960 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
2961 *
2962 * Let IOM talk DWORDs when reading, saves a lot of complications. On
2963 * writing though, we have to do it all ourselves because of sideeffects.
2964 */
2965 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2966 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2967#ifdef NEW_READ_CODE
2968 IOMMMIO_FLAGS_READ_DWORD |
2969#else
2970 IOMMMIO_FLAGS_READ_PASSTHRU |
2971#endif
2972 IOMMMIO_FLAGS_WRITE_PASSTHRU,
2973 hdaMMIOWrite, hdaMMIORead, "HDA");
2974
2975 if (RT_FAILURE(rc))
2976 return rc;
2977
2978 if (pThis->fR0Enabled)
2979 {
2980 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
2981 "hdaMMIOWrite", "hdaMMIORead");
2982 if (RT_FAILURE(rc))
2983 return rc;
2984 }
2985
2986 if (pThis->fRCEnabled)
2987 {
2988 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
2989 "hdaMMIOWrite", "hdaMMIORead");
2990 if (RT_FAILURE(rc))
2991 return rc;
2992 }
2993
2994 pThis->MMIOBaseAddr = GCPhysAddress;
2995 return VINF_SUCCESS;
2996}
2997
2998
2999/* Saved state callbacks. */
3000
3001/**
3002 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3003 */
3004static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3005{
3006 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3007
3008 /* Save Codec nodes states */
3009 hdaCodecSaveState(pThis->pCodec, pSSM);
3010
3011 /* Save MMIO registers */
3012 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3013 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3014 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3015
3016 /* Save HDA dma counters */
3017 SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3018 SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3019 SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3020 return VINF_SUCCESS;
3021}
3022
3023
3024/**
3025 * @callback_method_impl{FNSSMDEVLOADEXEC}
3026 */
3027static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3028{
3029 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3030
3031 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3032
3033 /*
3034 * Load Codec nodes states.
3035 */
3036 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3037 if (RT_FAILURE(rc))
3038 return rc;
3039
3040 /*
3041 * Load MMIO registers.
3042 */
3043 uint32_t cRegs;
3044 switch (uVersion)
3045 {
3046 case HDA_SSM_VERSION_1:
3047 /* Starting with r71199, we would save 112 instead of 113
3048 registers due to some code cleanups. This only affected trunk
3049 builds in the 4.1 development period. */
3050 cRegs = 113;
3051 if (SSMR3HandleRevision(pSSM) >= 71199)
3052 {
3053 uint32_t uVer = SSMR3HandleVersion(pSSM);
3054 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3055 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3056 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3057 cRegs = 112;
3058 }
3059 break;
3060
3061 case HDA_SSM_VERSION_2:
3062 case HDA_SSM_VERSION_3:
3063 cRegs = 112;
3064 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3065 break;
3066
3067 case HDA_SSM_VERSION:
3068 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3069 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3070 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3071 break;
3072
3073 default:
3074 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3075 }
3076
3077 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3078 {
3079 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3080 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3081 }
3082 else
3083 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3084
3085 /*
3086 * Load HDA DMA counters.
3087 */
3088 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
3089 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
3090 rc = SSMR3GetStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), fFlags, paFields, NULL);
3091 AssertRCReturn(rc, rc);
3092 rc = SSMR3GetStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), fFlags, paFields, NULL);
3093 AssertRCReturn(rc, rc);
3094 rc = SSMR3GetStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), fFlags, paFields, NULL);
3095 AssertRCReturn(rc, rc);
3096
3097 /*
3098 * Update stuff after the state changes.
3099 */
3100 bool fEnableIn = RT_BOOL(SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3101#ifdef VBOX_WITH_HDA_MIC_IN
3102 bool fEnableMicIn = RT_BOOL(SDCTL(pThis, 2) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3103#else
3104 bool fEnableMicIn = fEnableIn; /* Mic In == Line In */
3105#endif
3106 bool fEnableOut = RT_BOOL(SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3107
3108 PHDADRIVER pDrv;
3109 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3110 {
3111 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, fEnableIn);
3112 if (RT_FAILURE(rc))
3113 break;
3114 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, fEnableMicIn);
3115 if (RT_FAILURE(rc))
3116 break;
3117 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, fEnableOut);
3118 if (RT_FAILURE(rc))
3119 break;
3120 }
3121
3122 if (RT_SUCCESS(rc))
3123 {
3124 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3125 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3126 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3127 }
3128
3129 LogFlowFuncLeaveRC(rc);
3130 return rc;
3131}
3132
3133
3134/* Debug and log type formatters. */
3135
3136/**
3137 * @callback_method_impl{FNRTSTRFORMATTYPE}
3138 */
3139static DECLCALLBACK(size_t)
3140hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3141 const char *pszType, void const *pvValue,
3142 int cchWidth, int cchPrecision, unsigned fFlags,
3143 void *pvUser)
3144{
3145 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
3146 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3147 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
3148 sdCtl,
3149 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> HDA_SDCTL_NUM_SHIFT,
3150 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
3151 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3152 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3153 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3154 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3155 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3156 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3157}
3158
3159/**
3160 * @callback_method_impl{FNRTSTRFORMATTYPE}
3161 */
3162static DECLCALLBACK(size_t)
3163hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3164 const char *pszType, void const *pvValue,
3165 int cchWidth, int cchPrecision, unsigned fFlags,
3166 void *pvUser)
3167{
3168 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3169 uint32_t cb;
3170 switch (uSdFifos)
3171 {
3172 case HDA_SDONFIFO_16B: cb = 16; break;
3173 case HDA_SDONFIFO_32B: cb = 32; break;
3174 case HDA_SDONFIFO_64B: cb = 64; break;
3175 case HDA_SDONFIFO_128B: cb = 128; break;
3176 case HDA_SDONFIFO_192B: cb = 192; break;
3177 case HDA_SDONFIFO_256B: cb = 256; break;
3178 case HDA_SDINFIFO_120B: cb = 120; break;
3179 case HDA_SDINFIFO_160B: cb = 160; break;
3180 default: cb = 0; break;
3181 }
3182 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
3183}
3184
3185/**
3186 * @callback_method_impl{FNRTSTRFORMATTYPE}
3187 */
3188static DECLCALLBACK(size_t)
3189hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3190 const char *pszType, void const *pvValue,
3191 int cchWidth, int cchPrecision, unsigned fFlags,
3192 void *pvUser)
3193{
3194 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3195 uint32_t cb;
3196 switch (uSdFifos)
3197 {
3198 case HDA_SDFIFOW_8B: cb = 8; break;
3199 case HDA_SDFIFOW_16B: cb = 16; break;
3200 case HDA_SDFIFOW_32B: cb = 32; break;
3201 default: cb = 0; break;
3202 }
3203 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
3204}
3205
3206/**
3207 * @callback_method_impl{FNRTSTRFORMATTYPE}
3208 */
3209static DECLCALLBACK(size_t)
3210hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3211 const char *pszType, void const *pvValue,
3212 int cchWidth, int cchPrecision, unsigned fFlags,
3213 void *pvUser)
3214{
3215 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3216 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3217 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3218 uSdSts,
3219 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3220 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3221 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3222 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3223}
3224
3225
3226static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3227{
3228 int iReg = 0;
3229 for (; iReg < HDA_NREGS; ++iReg)
3230 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3231 return iReg;
3232 return -1;
3233}
3234
3235
3236static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
3237{
3238 Assert( pThis
3239 && iHdaIndex >= 0
3240 && iHdaIndex < HDA_NREGS);
3241 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
3242}
3243
3244
3245/**
3246 * @callback_method_impl{FNDBGFHANDLERDEV}
3247 */
3248static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3249{
3250 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3251 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
3252 if (iHdaRegisterIndex != -1)
3253 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3254 else
3255 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
3256 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3257}
3258
3259
3260static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
3261{
3262 Assert( pThis
3263 && iHdaStrmIndex >= 0
3264 && iHdaStrmIndex < 7);
3265 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
3266 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
3267 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
3268 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
3269 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
3270}
3271
3272
3273static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
3274{
3275 /* todo: add args parsing */
3276 return -1;
3277}
3278
3279
3280/**
3281 * @callback_method_impl{FNDBGFHANDLERDEV}
3282 */
3283static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3284{
3285 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3286 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
3287 if (iHdaStrmIndex != -1)
3288 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3289 else
3290 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
3291 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3292}
3293
3294
3295/**
3296 * @callback_method_impl{FNDBGFHANDLERDEV}
3297 */
3298static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3299{
3300 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3301
3302 if (pThis->pCodec->pfnCodecDbgListNodes)
3303 pThis->pCodec->pfnCodecDbgListNodes(pThis->pCodec, pHlp, pszArgs);
3304 else
3305 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3306}
3307
3308
3309/**
3310 * @callback_method_impl{FNDBGFHANDLERDEV}
3311 */
3312static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3313{
3314 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3315
3316 if (pThis->pCodec->pfnCodecDbgSelector)
3317 pThis->pCodec->pfnCodecDbgSelector(pThis->pCodec, pHlp, pszArgs);
3318 else
3319 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3320}
3321
3322
3323/* PDMIBASE */
3324
3325/**
3326 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3327 */
3328static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3329{
3330 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
3331 Assert(&pThis->IBase == pInterface);
3332
3333 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3334 return NULL;
3335}
3336
3337
3338/* PDMDEVREG */
3339
3340/**
3341 * Reset notification.
3342 *
3343 * @returns VBox status.
3344 * @param pDevIns The device instance data.
3345 *
3346 * @remark The original sources didn't install a reset handler, but it seems to
3347 * make sense to me so we'll do it.
3348 */
3349static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
3350{
3351 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3352 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
3353 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3354 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3355 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3356 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3357 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
3358 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
3359 HDA_REG(pThis, CORBRP) = 0x0;
3360 HDA_REG(pThis, RIRBWP) = 0x0;
3361
3362 LogFunc(("Resetting ...\n"));
3363
3364 /* Stop any audio currently playing. */
3365 PHDADRIVER pDrv;
3366 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3367 {
3368 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
3369 /* Ignore rc. */
3370 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
3371 /* Ditto. */
3372 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
3373 /* Ditto. */
3374 }
3375
3376 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
3377
3378 if (pThis->pu32CorbBuf)
3379 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3380 else
3381 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3382
3383 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
3384 if (pThis->pu64RirbBuf)
3385 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3386 else
3387 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3388
3389 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
3390
3391 HDABDLEDESC StEmptyBdle;
3392 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
3393 {
3394 HDASTREAMTRANSFERDESC StreamDesc;
3395 PHDABDLEDESC pBdle = NULL;
3396 if (u8Strm == 0)
3397 pBdle = &pThis->StInBdle;
3398# ifdef VBOX_WITH_HDA_MIC_IN
3399 else if (u8Strm == 2)
3400 pBdle = &pThis->StMicBdle;
3401# endif
3402 else if(u8Strm == 4)
3403 pBdle = &pThis->StOutBdle;
3404 else
3405 {
3406 RT_ZERO(StEmptyBdle);
3407 pBdle = &StEmptyBdle;
3408 }
3409 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
3410 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
3411 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
3412 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
3413 }
3414
3415 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3416 HDA_REG(pThis, STATESTS) = 0x1;
3417
3418 LogRel(("HDA: Reset\n"));
3419}
3420
3421/**
3422 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3423 */
3424static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
3425{
3426 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3427
3428 PHDADRIVER pDrv;
3429 while (!RTListIsEmpty(&pThis->lstDrv))
3430 {
3431 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
3432
3433 RTListNodeRemove(&pDrv->Node);
3434 RTMemFree(pDrv);
3435 }
3436
3437 if (pThis->pMixer)
3438 {
3439 AudioMixerDestroy(pThis->pMixer);
3440 pThis->pMixer = NULL;
3441 }
3442
3443 if (pThis->pCodec)
3444 {
3445 int rc = hdaCodecDestruct(pThis->pCodec);
3446 AssertRC(rc);
3447
3448 RTMemFree(pThis->pCodec);
3449 pThis->pCodec = NULL;
3450 }
3451
3452 RTMemFree(pThis->pu32CorbBuf);
3453 pThis->pu32CorbBuf = NULL;
3454
3455 RTMemFree(pThis->pu64RirbBuf);
3456 pThis->pu64RirbBuf = NULL;
3457
3458 return VINF_SUCCESS;
3459}
3460
3461/**
3462 * Attach command.
3463 *
3464 * This is called to let the device attach to a driver for a specified LUN
3465 * during runtime. This is not called during VM construction, the device
3466 * constructor have to attach to all the available drivers.
3467 *
3468 * @returns VBox status code.
3469 * @param pDevIns The device instance.
3470 * @param uLUN The logical unit which is being detached.
3471 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3472 */
3473static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
3474{
3475 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3476
3477 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3478 ("HDA device does not support hotplugging\n"),
3479 VERR_INVALID_PARAMETER);
3480
3481 /*
3482 * Attach driver.
3483 */
3484 char *pszDesc = NULL;
3485 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
3486 AssertMsgReturn(pszDesc,
3487 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
3488 VERR_NO_MEMORY);
3489
3490 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
3491 &pThis->IBase, &pThis->pDrvBase, pszDesc);
3492 if (RT_SUCCESS(rc))
3493 {
3494 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
3495 if (pDrv)
3496 {
3497 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
3498 AssertMsg(pDrv->pConnector != NULL,
3499 ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n",
3500 uLUN, rc));
3501 pDrv->pHDAState = pThis;
3502 pDrv->uLUN = uLUN;
3503
3504 /*
3505 * For now we always set the driver at LUN 0 as our primary
3506 * host backend. This might change in the future.
3507 */
3508 if (pDrv->uLUN == 0)
3509 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
3510
3511 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
3512
3513 /* Attach to driver list. */
3514 RTListAppend(&pThis->lstDrv, &pDrv->Node);
3515 }
3516 else
3517 rc = VERR_NO_MEMORY;
3518 }
3519 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
3520 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
3521 {
3522 LogFunc(("No attached driver for LUN #%u\n", uLUN));
3523 }
3524 else if (RT_FAILURE(rc))
3525 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
3526 uLUN, pszDesc, rc));
3527
3528 RTStrFree(pszDesc);
3529
3530 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
3531 return rc;
3532}
3533
3534static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3535{
3536 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
3537
3538 LogFlowFuncEnter();
3539}
3540
3541/**
3542 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3543 */
3544static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
3545{
3546 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3547 Assert(iInstance == 0);
3548 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3549
3550 /*
3551 * Validations.
3552 */
3553 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
3554 "RCEnabled\0"))
3555 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3556 N_ ("Invalid configuration for the Intel HDA device"));
3557
3558 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
3559 if (RT_FAILURE(rc))
3560 return PDMDEV_SET_ERROR(pDevIns, rc,
3561 N_("HDA configuration error: failed to read RCEnabled as boolean"));
3562 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
3563 if (RT_FAILURE(rc))
3564 return PDMDEV_SET_ERROR(pDevIns, rc,
3565 N_("HDA configuration error: failed to read R0Enabled as boolean"));
3566
3567 /*
3568 * Initialize data (most of it anyway).
3569 */
3570 pThis->pDevInsR3 = pDevIns;
3571 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3572 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3573 /* IBase */
3574 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
3575
3576 /* PCI Device */
3577 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
3578 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
3579
3580 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
3581 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
3582 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
3583 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
3584 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
3585 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
3586 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
3587 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
3588 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
3589 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
3590 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
3591
3592#if defined(HDA_AS_PCI_EXPRESS)
3593 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
3594#elif defined(VBOX_WITH_MSI_DEVICES)
3595 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
3596#else
3597 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
3598#endif
3599
3600 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
3601 /// of these values needs to be properly documented!
3602 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
3603 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
3604
3605 /* Power Management */
3606 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
3607 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
3608 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
3609
3610#ifdef HDA_AS_PCI_EXPRESS
3611 /* PCI Express */
3612 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
3613 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
3614 /* Device flags */
3615 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
3616 /* version */ 0x1 |
3617 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
3618 /* MSI */ (100) << 9 );
3619 /* Device capabilities */
3620 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
3621 /* Device control */
3622 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
3623 /* Device status */
3624 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
3625 /* Link caps */
3626 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
3627 /* Link control */
3628 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
3629 /* Link status */
3630 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
3631 /* Slot capabilities */
3632 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
3633 /* Slot control */
3634 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
3635 /* Slot status */
3636 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
3637 /* Root control */
3638 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
3639 /* Root capabilities */
3640 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
3641 /* Root status */
3642 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
3643 /* Device capabilities 2 */
3644 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
3645 /* Device control 2 */
3646 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
3647 /* Link control 2 */
3648 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
3649 /* Slot control 2 */
3650 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
3651#endif
3652
3653 /*
3654 * Register the PCI device.
3655 */
3656 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
3657 if (RT_FAILURE(rc))
3658 return rc;
3659
3660 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
3661 if (RT_FAILURE(rc))
3662 return rc;
3663
3664#ifdef VBOX_WITH_MSI_DEVICES
3665 PDMMSIREG MsiReg;
3666 RT_ZERO(MsiReg);
3667 MsiReg.cMsiVectors = 1;
3668 MsiReg.iMsiCapOffset = 0x60;
3669 MsiReg.iMsiNextOffset = 0x50;
3670 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3671 if (RT_FAILURE(rc))
3672 {
3673 /* That's OK, we can work without MSI */
3674 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
3675 }
3676#endif
3677
3678 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
3679 if (RT_FAILURE(rc))
3680 return rc;
3681
3682 RTListInit(&pThis->lstDrv);
3683
3684 uint8_t uLUN;
3685 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
3686 {
3687 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
3688 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
3689 if (RT_FAILURE(rc))
3690 {
3691 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3692 rc = VINF_SUCCESS;
3693
3694 break;
3695 }
3696
3697 uLUN++;
3698 }
3699
3700 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3701
3702 if (RT_SUCCESS(rc))
3703 {
3704 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
3705 if (RT_SUCCESS(rc))
3706 {
3707 /* Set a default audio format for our mixer. */
3708 PDMAUDIOSTREAMCFG streamCfg;
3709 streamCfg.uHz = 41000;
3710 streamCfg.cChannels = 2;
3711 streamCfg.enmFormat = AUD_FMT_S16;
3712 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
3713
3714 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
3715 AssertRC(rc);
3716
3717 /* Add all required audio sinks. */
3718 rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output",
3719 AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
3720 AssertRC(rc);
3721
3722 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In",
3723 AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
3724 AssertRC(rc);
3725
3726 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
3727 AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
3728 AssertRC(rc);
3729
3730 /* There is no master volume control. Set the master to max. */
3731 PDMAUDIOVOLUME vol = { false, 255, 255 };
3732 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
3733 AssertRC(rc);
3734 }
3735 }
3736
3737 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3738
3739 if (RT_SUCCESS(rc))
3740 {
3741 /* Construct codec. */
3742 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
3743 if (!pThis->pCodec)
3744 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
3745
3746 /* Audio driver callbacks for multiplexing. */
3747 pThis->pCodec->pfnCloseIn = hdaCloseIn;
3748 pThis->pCodec->pfnCloseOut = hdaCloseOut;
3749 pThis->pCodec->pfnOpenIn = hdaOpenIn;
3750 pThis->pCodec->pfnOpenOut = hdaOpenOut;
3751 pThis->pCodec->pfnReset = hdaCodecReset;
3752 pThis->pCodec->pfnSetVolume = hdaSetVolume;
3753
3754 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
3755
3756 /* Construct the codec. */
3757 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
3758 if (RT_FAILURE(rc))
3759 AssertRCReturn(rc, rc);
3760
3761 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
3762 verb F20 should provide device/codec recognition. */
3763 Assert(pThis->pCodec->u16VendorId);
3764 Assert(pThis->pCodec->u16DeviceId);
3765 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
3766 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
3767 }
3768
3769 if (RT_SUCCESS(rc))
3770 {
3771 hdaReset(pDevIns);
3772
3773 /*
3774 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
3775 * hdaReset shouldn't affects these registers.
3776 */
3777 HDA_REG(pThis, WAKEEN) = 0x0;
3778 HDA_REG(pThis, STATESTS) = 0x0;
3779
3780 /*
3781 * Debug and string formatter types.
3782 */
3783 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
3784 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
3785 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
3786 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
3787
3788 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
3789 AssertRC(rc);
3790 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
3791 AssertRC(rc);
3792 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
3793 AssertRC(rc);
3794 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
3795 AssertRC(rc);
3796 #if 0
3797 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
3798 AssertRC(rc);
3799 #endif
3800
3801 /*
3802 * Some debug assertions.
3803 */
3804 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
3805 {
3806 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
3807 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
3808
3809 /* binary search order. */
3810 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
3811 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3812 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3813
3814 /* alignment. */
3815 AssertReleaseMsg( pReg->size == 1
3816 || (pReg->size == 2 && (pReg->offset & 1) == 0)
3817 || (pReg->size == 3 && (pReg->offset & 3) == 0)
3818 || (pReg->size == 4 && (pReg->offset & 3) == 0),
3819 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3820
3821 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
3822 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
3823 if (pReg->offset & 3)
3824 {
3825 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
3826 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3827 if (pPrevReg)
3828 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
3829 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3830 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
3831 }
3832 #if 0
3833 if ((pReg->offset + pReg->size) & 3)
3834 {
3835 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3836 if (pNextReg)
3837 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
3838 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3839 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3840 }
3841 #endif
3842
3843 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
3844 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
3845 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3846 }
3847 }
3848
3849 if (RT_SUCCESS(rc))
3850 {
3851 /* Start the emulation timer. */
3852 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
3853 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
3854 AssertRCReturn(rc, rc);
3855
3856 if (RT_SUCCESS(rc))
3857 {
3858 /** @todo Investigate why sounds is getting corrupted if the "ticks" value is too
3859 * low, e.g. "PDMDevHlpTMTimeVirtGetFreq / 200". */
3860 pThis->uTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 500; /** @todo Make this configurable! */
3861 if (pThis->uTicks < 100)
3862 pThis->uTicks = 100;
3863 LogFunc(("Timer ticks=%RU64\n", pThis->uTicks));
3864
3865 /* Fire off timer. */
3866 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
3867 }
3868 }
3869
3870# ifdef VBOX_WITH_STATISTICS
3871 if (RT_SUCCESS(rc))
3872 {
3873 /*
3874 * Register statistics.
3875 */
3876 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
3877 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
3878 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
3879 }
3880# endif
3881
3882 LogFlowFuncLeaveRC(rc);
3883 return rc;
3884}
3885
3886/**
3887 * The device registration structure.
3888 */
3889const PDMDEVREG g_DeviceICH6_HDA =
3890{
3891 /* u32Version */
3892 PDM_DEVREG_VERSION,
3893 /* szName */
3894 "hda",
3895 /* szRCMod */
3896 "VBoxDDRC.rc",
3897 /* szR0Mod */
3898 "VBoxDDR0.r0",
3899 /* pszDescription */
3900 "Intel HD Audio Controller",
3901 /* fFlags */
3902 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
3903 /* fClass */
3904 PDM_DEVREG_CLASS_AUDIO,
3905 /* cMaxInstances */
3906 1,
3907 /* cbInstance */
3908 sizeof(HDASTATE),
3909 /* pfnConstruct */
3910 hdaConstruct,
3911 /* pfnDestruct */
3912 hdaDestruct,
3913 /* pfnRelocate */
3914 NULL,
3915 /* pfnMemSetup */
3916 NULL,
3917 /* pfnPowerOn */
3918 NULL,
3919 /* pfnReset */
3920 hdaReset,
3921 /* pfnSuspend */
3922 NULL,
3923 /* pfnResume */
3924 NULL,
3925 /* pfnAttach */
3926 NULL,
3927 /* pfnDetach */
3928 NULL,
3929 /* pfnQueryInterface. */
3930 NULL,
3931 /* pfnInitComplete */
3932 NULL,
3933 /* pfnPowerOff */
3934 NULL,
3935 /* pfnSoftReset */
3936 NULL,
3937 /* u32VersionEnd */
3938 PDM_DEVREG_VERSION
3939};
3940
3941#endif /* IN_RING3 */
3942#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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