VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 57358

Last change on this file since 57358 was 57358, checked in by vboxsync, 9 years ago

*: scm cleanup run.
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1/* $Id: DevIchHda.cpp 57358 2015-08-14 15:16:38Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2015 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#ifdef IN_RING3
36# include <iprt/uuid.h>
37# include <iprt/string.h>
38# include <iprt/mem.h>
39#endif
40#include <iprt/list.h>
41
42#include "VBoxDD.h"
43
44#include "AudioMixer.h"
45#include "DevIchHdaCodec.h"
46
47
48/*********************************************************************************************************************************
49* Defined Constants And Macros *
50*********************************************************************************************************************************/
51//#define HDA_AS_PCI_EXPRESS
52#define VBOX_WITH_INTEL_HDA
53
54#if (defined(DEBUG) && defined(DEBUG_andy))
55/* Enables experimental support for separate mic-in handling.
56 Do not enable this yet for regular builds, as this needs more testing first! */
57# define VBOX_WITH_HDA_MIC_IN
58#endif
59
60#if defined(VBOX_WITH_HP_HDA)
61/* HP Pavilion dv4t-1300 */
62# define HDA_PCI_VENDOR_ID 0x103c
63# define HDA_PCI_DEVICE_ID 0x30f7
64#elif defined(VBOX_WITH_INTEL_HDA)
65/* Intel HDA controller */
66# define HDA_PCI_VENDOR_ID 0x8086
67# define HDA_PCI_DEVICE_ID 0x2668
68#elif defined(VBOX_WITH_NVIDIA_HDA)
69/* nVidia HDA controller */
70# define HDA_PCI_VENDOR_ID 0x10de
71# define HDA_PCI_DEVICE_ID 0x0ac0
72#else
73# error "Please specify your HDA device vendor/device IDs"
74#endif
75
76/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
77 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
78 * is read only except for bit 15 like the HDA spec states.
79 *
80 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
81 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
82#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
83
84#define HDA_NREGS 114
85#define HDA_NREGS_SAVED 112
86
87/**
88 * NB: Register values stored in memory (au32Regs[]) are indexed through
89 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
90 * register descriptors in g_aHdaRegMap[] are indexed through the
91 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
92 *
93 * The au32Regs[] layout is kept unchanged for saved state
94 * compatibility. */
95
96/* Registers */
97#define HDA_REG_IND_NAME(x) HDA_REG_##x
98#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
99#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
100#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
101#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
102#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
103#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
104#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
105
106
107#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
108#define HDA_RMX_GCAP 0
109/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
110 * oss (15:12) - number of output streams supported
111 * iss (11:8) - number of input streams supported
112 * bss (7:3) - number of bidirectional streams supported
113 * bds (2:1) - number of serial data out signals supported
114 * b64sup (0) - 64 bit addressing supported.
115 */
116#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
117 ( (((oss) & 0xF) << 12) \
118 | (((iss) & 0xF) << 8) \
119 | (((bss) & 0x1F) << 3) \
120 | (((bds) & 0x3) << 2) \
121 | ((b64sup) & 1))
122
123#define HDA_REG_VMIN 1 /* 0x02 */
124#define HDA_RMX_VMIN 1
125
126#define HDA_REG_VMAJ 2 /* 0x03 */
127#define HDA_RMX_VMAJ 2
128
129#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
130#define HDA_RMX_OUTPAY 3
131
132#define HDA_REG_INPAY 4 /* 0x06-0x07 */
133#define HDA_RMX_INPAY 4
134
135#define HDA_REG_GCTL 5 /* 0x08-0x0B */
136#define HDA_RMX_GCTL 5
137#define HDA_GCTL_RST_SHIFT 0
138#define HDA_GCTL_FSH_SHIFT 1
139#define HDA_GCTL_UR_SHIFT 8
140
141#define HDA_REG_WAKEEN 6 /* 0x0C */
142#define HDA_RMX_WAKEEN 6
143
144#define HDA_REG_STATESTS 7 /* 0x0E */
145#define HDA_RMX_STATESTS 7
146#define HDA_STATES_SCSF 0x7
147
148#define HDA_REG_GSTS 8 /* 0x10-0x11*/
149#define HDA_RMX_GSTS 8
150#define HDA_GSTS_FSH_SHIFT 1
151
152#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
153#define HDA_RMX_OUTSTRMPAY 112
154
155#define HDA_REG_INSTRMPAY 10 /* 0x1a */
156#define HDA_RMX_INSTRMPAY 113
157
158#define HDA_REG_INTCTL 11 /* 0x20 */
159#define HDA_RMX_INTCTL 9
160#define HDA_INTCTL_GIE_SHIFT 31
161#define HDA_INTCTL_CIE_SHIFT 30
162#define HDA_INTCTL_S0_SHIFT 0
163#define HDA_INTCTL_S1_SHIFT 1
164#define HDA_INTCTL_S2_SHIFT 2
165#define HDA_INTCTL_S3_SHIFT 3
166#define HDA_INTCTL_S4_SHIFT 4
167#define HDA_INTCTL_S5_SHIFT 5
168#define HDA_INTCTL_S6_SHIFT 6
169#define HDA_INTCTL_S7_SHIFT 7
170#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
171
172#define HDA_REG_INTSTS 12 /* 0x24 */
173#define HDA_RMX_INTSTS 10
174#define HDA_INTSTS_GIS_SHIFT 31
175#define HDA_INTSTS_CIS_SHIFT 30
176#define HDA_INTSTS_S0_SHIFT 0
177#define HDA_INTSTS_S1_SHIFT 1
178#define HDA_INTSTS_S2_SHIFT 2
179#define HDA_INTSTS_S3_SHIFT 3
180#define HDA_INTSTS_S4_SHIFT 4
181#define HDA_INTSTS_S5_SHIFT 5
182#define HDA_INTSTS_S6_SHIFT 6
183#define HDA_INTSTS_S7_SHIFT 7
184#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
185
186#define HDA_REG_WALCLK 13 /* 0x24 */
187#define HDA_RMX_WALCLK /* Not defined! */
188
189/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
190 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
191 * the datasheet.
192 */
193#define HDA_REG_SSYNC 14 /* 0x34 */
194#define HDA_RMX_SSYNC 12
195
196#define HDA_REG_CORBLBASE 15 /* 0x40 */
197#define HDA_RMX_CORBLBASE 13
198
199#define HDA_REG_CORBUBASE 16 /* 0x44 */
200#define HDA_RMX_CORBUBASE 14
201
202#define HDA_REG_CORBWP 17 /* 0x48 */
203#define HDA_RMX_CORBWP 15
204
205#define HDA_REG_CORBRP 18 /* 0x4A */
206#define HDA_RMX_CORBRP 16
207#define HDA_CORBRP_RST_SHIFT 15
208#define HDA_CORBRP_WP_SHIFT 0
209#define HDA_CORBRP_WP_MASK 0xFF
210
211#define HDA_REG_CORBCTL 19 /* 0x4C */
212#define HDA_RMX_CORBCTL 17
213#define HDA_CORBCTL_DMA_SHIFT 1
214#define HDA_CORBCTL_CMEIE_SHIFT 0
215
216#define HDA_REG_CORBSTS 20 /* 0x4D */
217#define HDA_RMX_CORBSTS 18
218#define HDA_CORBSTS_CMEI_SHIFT 0
219
220#define HDA_REG_CORBSIZE 21 /* 0x4E */
221#define HDA_RMX_CORBSIZE 19
222#define HDA_CORBSIZE_SZ_CAP 0xF0
223#define HDA_CORBSIZE_SZ 0x3
224/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
225
226#define HDA_REG_RIRBLBASE 22 /* 0x50 */
227#define HDA_RMX_RIRBLBASE 20
228
229#define HDA_REG_RIRBUBASE 23 /* 0x54 */
230#define HDA_RMX_RIRBUBASE 21
231
232#define HDA_REG_RIRBWP 24 /* 0x58 */
233#define HDA_RMX_RIRBWP 22
234#define HDA_RIRBWP_RST_SHIFT 15
235#define HDA_RIRBWP_WP_MASK 0xFF
236
237#define HDA_REG_RINTCNT 25 /* 0x5A */
238#define HDA_RMX_RINTCNT 23
239#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
240
241#define HDA_REG_RIRBCTL 26 /* 0x5C */
242#define HDA_RMX_RIRBCTL 24
243#define HDA_RIRBCTL_RIC_SHIFT 0
244#define HDA_RIRBCTL_DMA_SHIFT 1
245#define HDA_ROI_DMA_SHIFT 2
246
247#define HDA_REG_RIRBSTS 27 /* 0x5D */
248#define HDA_RMX_RIRBSTS 25
249#define HDA_RIRBSTS_RINTFL_SHIFT 0
250#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
251
252#define HDA_REG_RIRBSIZE 28 /* 0x5E */
253#define HDA_RMX_RIRBSIZE 26
254#define HDA_RIRBSIZE_SZ_CAP 0xF0
255#define HDA_RIRBSIZE_SZ 0x3
256
257#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
258#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
259
260
261#define HDA_REG_IC 29 /* 0x60 */
262#define HDA_RMX_IC 27
263
264#define HDA_REG_IR 30 /* 0x64 */
265#define HDA_RMX_IR 28
266
267#define HDA_REG_IRS 31 /* 0x68 */
268#define HDA_RMX_IRS 29
269#define HDA_IRS_ICB_SHIFT 0
270#define HDA_IRS_IRV_SHIFT 1
271
272#define HDA_REG_DPLBASE 32 /* 0x70 */
273#define HDA_RMX_DPLBASE 30
274#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
275
276#define HDA_REG_DPUBASE 33 /* 0x74 */
277#define HDA_RMX_DPUBASE 31
278#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
279#define DPBASE_ENABLED 1
280#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
281
282#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
283#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
284/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
285#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
286
287#define HDA_REG_SD0CTL 34 /* 0x80 */
288#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
289#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
290#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
291#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
292#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
293#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
294#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
295#define HDA_RMX_SD0CTL 32
296#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
297#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
298#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
299#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
300#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
301#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
302#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
303
304#define SD(func, num) SD##num##func
305#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
306#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
307#define HDA_SDCTL_NUM_MASK 0xF
308#define HDA_SDCTL_NUM_SHIFT 20
309#define HDA_SDCTL_DIR_SHIFT 19
310#define HDA_SDCTL_TP_SHIFT 18
311#define HDA_SDCTL_STRIPE_MASK 0x3
312#define HDA_SDCTL_STRIPE_SHIFT 16
313#define HDA_SDCTL_DEIE_SHIFT 4
314#define HDA_SDCTL_FEIE_SHIFT 3
315#define HDA_SDCTL_ICE_SHIFT 2
316#define HDA_SDCTL_RUN_SHIFT 1
317#define HDA_SDCTL_SRST_SHIFT 0
318
319#define HDA_REG_SD0STS 35 /* 0x83 */
320#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
321#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
322#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
323#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
324#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
325#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
326#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
327#define HDA_RMX_SD0STS 33
328#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
329#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
330#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
331#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
332#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
333#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
334#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
335
336#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
337#define HDA_SDSTS_FIFORDY_SHIFT 5
338#define HDA_SDSTS_DE_SHIFT 4
339#define HDA_SDSTS_FE_SHIFT 3
340#define HDA_SDSTS_BCIS_SHIFT 2
341
342#define HDA_REG_SD0LPIB 36 /* 0x84 */
343#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
344#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
345#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
346#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
347#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
348#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
349#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
350#define HDA_RMX_SD0LPIB 34
351#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
352#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
353#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
354#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
355#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
356#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
357#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
358
359#define HDA_REG_SD0CBL 37 /* 0x88 */
360#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
361#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
362#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
363#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
364#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
365#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
366#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
367#define HDA_RMX_SD0CBL 35
368#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
369#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
370#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
371#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
372#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
373#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
374#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
375
376
377#define HDA_REG_SD0LVI 38 /* 0x8C */
378#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
379#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
380#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
381#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
382#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
383#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
384#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
385#define HDA_RMX_SD0LVI 36
386#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
387#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
388#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
389#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
390#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
391#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
392#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
393
394#define HDA_REG_SD0FIFOW 39 /* 0x8E */
395#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
396#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
397#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
398#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
399#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
400#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
401#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
402#define HDA_RMX_SD0FIFOW 37
403#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
404#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
405#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
406#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
407#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
408#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
409#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
410
411/*
412 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
413 */
414#define HDA_SDFIFOW_8B 0x2
415#define HDA_SDFIFOW_16B 0x3
416#define HDA_SDFIFOW_32B 0x4
417
418#define HDA_REG_SD0FIFOS 40 /* 0x90 */
419#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
420#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
421#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
422#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
423#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
424#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
425#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
426#define HDA_RMX_SD0FIFOS 38
427#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
428#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
429#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
430#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
431#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
432#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
433#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
434
435/*
436 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
437 * formula: size - 1
438 * Other values not listed are not supported.
439 */
440#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
441#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
442#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
443#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
444#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
445#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
446#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
447#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
448#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
449
450#define HDA_REG_SD0FMT 41 /* 0x92 */
451#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
452#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
453#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
454#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
455#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
456#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
457#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
458#define HDA_RMX_SD0FMT 39
459#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
460#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
461#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
462#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
463#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
464#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
465#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
466
467#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
468#define HDA_SDFMT_BASE_RATE_SHIFT 14
469#define HDA_SDFMT_MULT_SHIFT 11
470#define HDA_SDFMT_MULT_MASK 0x7
471#define HDA_SDFMT_DIV_SHIFT 8
472#define HDA_SDFMT_DIV_MASK 0x7
473#define HDA_SDFMT_BITS_SHIFT 4
474#define HDA_SDFMT_BITS_MASK 0x7
475#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
476#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
477#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
478
479#define HDA_REG_SD0BDPL 42 /* 0x98 */
480#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
481#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
482#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
483#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
484#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
485#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
486#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
487#define HDA_RMX_SD0BDPL 40
488#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
489#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
490#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
491#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
492#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
493#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
494#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
495
496#define HDA_REG_SD0BDPU 43 /* 0x9C */
497#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
498#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
499#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
500#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
501#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
502#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
503#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
504#define HDA_RMX_SD0BDPU 41
505#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
506#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
507#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
508#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
509#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
510#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
511#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
512
513#define HDA_CODEC_CAD_SHIFT 28
514/* Encodes the (required) LUN into a codec command. */
515#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
516
517
518
519/*********************************************************************************************************************************
520* Structures and Typedefs *
521*********************************************************************************************************************************/
522typedef struct HDABDLEDESC
523{
524 uint64_t u64BdleCviAddr;
525 uint32_t u32BdleMaxCvi;
526 uint32_t u32BdleCvi;
527 uint32_t u32BdleCviLen;
528 uint32_t u32BdleCviPos;
529 bool fBdleCviIoc;
530 uint32_t cbUnderFifoW;
531 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
532} HDABDLEDESC, *PHDABDLEDESC;
533
534typedef struct HDASTREAMTRANSFERDESC
535{
536 uint64_t u64BaseDMA;
537 uint32_t u32Ctl;
538 uint32_t *pu32Sts;
539 uint8_t u8Strm;
540 uint32_t *pu32Lpib;
541 uint32_t u32Cbl;
542 uint32_t u32Fifos;
543} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
544
545typedef struct HDAINPUTSTREAM
546{
547 /** PCM line input stream. */
548 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
549 /** Mixer handle for line input stream. */
550 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
551} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
552
553typedef struct HDAOUTPUTSTREAM
554{
555 /** PCM output stream. */
556 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
557 /** Mixer handle for line output stream. */
558 R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
559} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
560
561/**
562 * Struct for maintaining a host backend driver.
563 * This driver must be associated to one, and only one,
564 * HDA codec. The HDA controller does the actual multiplexing
565 * of HDA codec data to various host backend drivers then.
566 *
567 * This HDA device uses a timer in order to synchronize all
568 * read/write accesses across all attached LUNs / backends.
569 */
570typedef struct HDADRIVER
571{
572 union
573 {
574 /** Node for storing this driver in our device driver
575 * list of HDASTATE. */
576 RTLISTNODE Node;
577 struct
578 {
579 R3PTRTYPE(void *) dummy1;
580 R3PTRTYPE(void *) dummy2;
581 } dummy;
582 };
583
584 /** Pointer to HDA controller (state). */
585 R3PTRTYPE(PHDASTATE) pHDAState;
586 /** Driver flags. */
587 PDMAUDIODRVFLAGS Flags;
588 uint8_t u32Padding0[3];
589 /** LUN to which this driver has been assigned. */
590 uint8_t uLUN;
591 /** Audio connector interface to the underlying
592 * host backend. */
593 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
594 /** Stream for line input. */
595 HDAINPUTSTREAM LineIn;
596 /** Stream for mic input. */
597 HDAINPUTSTREAM MicIn;
598 /** Stream for output. */
599 HDAOUTPUTSTREAM Out;
600} HDADRIVER, *PHDADRIVER;
601
602/**
603 * ICH Intel HD Audio Controller state.
604 */
605typedef struct HDASTATE
606{
607 /** The PCI device structure. */
608 PCIDevice PciDev;
609 /** R3 Pointer to the device instance. */
610 PPDMDEVINSR3 pDevInsR3;
611 /** R0 Pointer to the device instance. */
612 PPDMDEVINSR0 pDevInsR0;
613 /** R0 Pointer to the device instance. */
614 PPDMDEVINSRC pDevInsRC;
615
616 uint32_t u32Padding;
617
618 /** Pointer to the attached audio driver. */
619 R3PTRTYPE(PPDMIBASE) pDrvBase;
620 /** The base interface for LUN\#0. */
621 PDMIBASE IBase;
622 RTGCPHYS MMIOBaseAddr;
623 uint32_t au32Regs[HDA_NREGS];
624 HDABDLEDESC StInBdle;
625 HDABDLEDESC StOutBdle;
626 HDABDLEDESC StMicBdle;
627 uint64_t u64CORBBase;
628 uint64_t u64RIRBBase;
629 uint64_t u64DPBase;
630 /** Pointer to CORB buffer. */
631 R3PTRTYPE(uint32_t *) pu32CorbBuf;
632 /** Size in bytes of CORB buffer. */
633 uint32_t cbCorbBuf;
634 uint32_t u32Padding2;
635 /** Pointer to RIRB buffer. */
636 R3PTRTYPE(uint64_t *) pu64RirbBuf;
637 /** Size in bytes of RIRB buffer. */
638 uint32_t cbRirbBuf;
639 /** Indicates if HDA is in reset. */
640 bool fInReset;
641 /** Interrupt on completion */
642 bool fCviIoc;
643 /** Flag whether the R0 part is enabled. */
644 bool fR0Enabled;
645 /** Flag whether the RC part is enabled. */
646 bool fRCEnabled;
647 /** The emulation timer for handling the attached
648 * LUN drivers. */
649 PTMTIMERR3 pTimer;
650 /** Timer ticks for handling the LUN drivers. */
651 uint64_t uTicks;
652# ifdef VBOX_WITH_STATISTICS
653 STAMPROFILE StatTimer;
654 STAMCOUNTER StatBytesRead;
655 STAMCOUNTER StatBytesWritten;
656# endif
657 /** Pointer to HDA codec to use. */
658 R3PTRTYPE(PHDACODEC) pCodec;
659 union
660 {
661 /** List of associated LUN drivers. */
662 RTLISTANCHOR lstDrv;
663 struct
664 {
665 R3PTRTYPE(void *) dummy1;
666 R3PTRTYPE(void *) dummy2;
667 } dummy;
668 };
669 /** The device' software mixer. */
670 R3PTRTYPE(PAUDIOMIXER) pMixer;
671 /** Audio sink for PCM output. */
672 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
673 /** Audio mixer sink for line input. */
674 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
675 /** Audio mixer sink for microphone input. */
676 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
677 uint64_t u64BaseTS;
678 /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
679 uint8_t u8Counter;
680 uint8_t au8Padding[7];
681} HDASTATE;
682/** Pointer to the ICH Intel HD Audio Controller state. */
683typedef HDASTATE *PHDASTATE;
684
685#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
686 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
687#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
688 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
689
690
691/*********************************************************************************************************************************
692* Internal Functions *
693*********************************************************************************************************************************/
694#ifndef VBOX_DEVICE_STRUCT_TESTCASE
695static FNPDMDEVRESET hdaReset;
696
697static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
698static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
699static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
700static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
701static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
702static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
703static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
704static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
705static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
706static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
707static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
708static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
709static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
710static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
711static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
712static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
713static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
714
715static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
716static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
717static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
718static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
719static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
720static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
721static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
722static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
723static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
724static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
725static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
726static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
727static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
728static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
729static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
730static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
731
732static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
733static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail);
734
735#ifdef IN_RING3
736DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
737 PHDASTREAMTRANSFERDESC pStreamDesc);
738static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
739#ifdef LOG_ENABLED
740static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
741#endif
742#endif
743
744
745/*********************************************************************************************************************************
746* Global Variables *
747*********************************************************************************************************************************/
748
749/* see 302349 p 6.2*/
750static const struct HDAREGDESC
751{
752 /** Register offset in the register space. */
753 uint32_t offset;
754 /** Size in bytes. Registers of size > 4 are in fact tables. */
755 uint32_t size;
756 /** Readable bits. */
757 uint32_t readable;
758 /** Writable bits. */
759 uint32_t writable;
760 /** Read callback. */
761 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
762 /** Write callback. */
763 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
764 /** Index into the register storage array. */
765 uint32_t mem_idx;
766 /** Abbreviated name. */
767 const char *abbrev;
768} g_aHdaRegMap[HDA_NREGS] =
769
770/* Turn a short register name into an memory index and a stringized name. */
771#define RA(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
772/* Same as above for an input stream ('I' prefixed). */
773#define IA(abbrev) HDA_MEM_IND_NAME(abbrev), "I"#abbrev
774/* Same as above for an output stream ('O' prefixed). */
775#define OA(abbrev) HDA_MEM_IND_NAME(abbrev), "O"#abbrev
776/* Same as above for a register *not* stored in memory. */
777#define UA(abbrev) 0, #abbrev
778
779{
780 /* offset size read mask write mask read callback write callback abbrev */
781 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- */
782 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(GCAP) }, /* Global Capabilities */
783 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMIN) }, /* Minor Version */
784 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMAJ) }, /* Major Version */
785 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTPAY) }, /* Output Payload Capabilities */
786 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INPAY) }, /* Input Payload Capabilities */
787 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , RA(GCTL) }, /* Global Control */
788 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , RA(WAKEEN) }, /* Wake Enable */
789 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , RA(STATESTS) }, /* State Change Status */
790 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , RA(GSTS) }, /* Global Status */
791 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTSTRMPAY)}, /* Output Stream Payload Capability */
792 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INSTRMPAY) }, /* Input Stream Payload Capability */
793 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(INTCTL) }, /* Interrupt Control */
794 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , RA(INTSTS) }, /* Interrupt Status */
795 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , UA(WALCLK) }, /* Wall Clock Counter */
796 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
797 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(SSYNC) }, /* Stream Synchronization */
798 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(CORBLBASE) }, /* CORB Lower Base Address */
799 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(CORBUBASE) }, /* CORB Upper Base Address */
800 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , RA(CORBWP) }, /* CORB Write Pointer */
801 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , RA(CORBRP) }, /* CORB Read Pointer */
802 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , RA(CORBCTL) }, /* CORB Control */
803 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , RA(CORBSTS) }, /* CORB Status */
804 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(CORBSIZE) }, /* CORB Size */
805 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBLBASE) }, /* RIRB Lower Base Address */
806 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBUBASE) }, /* RIRB Upper Base Address */
807 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , RA(RIRBWP) }, /* RIRB Write Pointer */
808 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , RA(RINTCNT) }, /* Response Interrupt Count */
809 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , RA(RIRBCTL) }, /* RIRB Control */
810 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , RA(RIRBSTS) }, /* RIRB Status */
811 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(RIRBSIZE) }, /* RIRB Size */
812 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , RA(IC) }, /* Immediate Command */
813 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , RA(IR) }, /* Immediate Response */
814 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , RA(IRS) }, /* Immediate Command Status */
815 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , RA(DPLBASE) }, /* MA Position Lower Base */
816 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(DPUBASE) }, /* DMA Position Upper Base */
817
818 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD0CTL) }, /* Input Stream Descriptor 0 (ICD0) Control */
819 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD0STS) }, /* ISD0 Status */
820 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0LPIB) }, /* ISD0 Link Position In Buffer */
821 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0CBL) }, /* ISD0 Cyclic Buffer Length */
822 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD0LVI) }, /* ISD0 Last Valid Index */
823 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD0FIFOW) }, /* ISD0 FIFO Watermark */
824 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD0FIFOS) }, /* ISD0 FIFO Size */
825 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD0FMT) }, /* ISD0 Format */
826 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD0BDPL) }, /* ISD0 Buffer Descriptor List Pointer-Lower Base Address */
827 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD0BDPU) }, /* ISD0 Buffer Descriptor List Pointer-Upper Base Address */
828
829 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD1CTL) }, /* Input Stream Descriptor 1 (ISD1) Control */
830 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD1STS) }, /* ISD1 Status */
831 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1LPIB) }, /* ISD1 Link Position In Buffer */
832 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1CBL) }, /* ISD1 Cyclic Buffer Length */
833 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD1LVI) }, /* ISD1 Last Valid Index */
834 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD1FIFOW) }, /* ISD1 FIFO Watermark */
835 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD1FIFOS) }, /* ISD1 FIFO Size */
836 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD1FMT) }, /* ISD1 Format */
837 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD1BDPL) }, /* ISD1 Buffer Descriptor List Pointer-Lower Base Address */
838 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD1BDPU) }, /* ISD1 Buffer Descriptor List Pointer-Upper Base Address */
839
840 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD2CTL) }, /* Input Stream Descriptor 2 (ISD2) Control */
841 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD2STS) }, /* ISD2 Status */
842 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2LPIB) }, /* ISD2 Link Position In Buffer */
843 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2CBL) }, /* ISD2 Cyclic Buffer Length */
844 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD2LVI) }, /* ISD2 Last Valid Index */
845 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD2FIFOW) }, /* ISD2 FIFO Watermark */
846 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD2FIFOS) }, /* ISD2 FIFO Size */
847 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD2FMT) }, /* ISD2 Format */
848 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD2BDPL) }, /* ISD2 Buffer Descriptor List Pointer-Lower Base Address */
849 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD2BDPU) }, /* ISD2 Buffer Descriptor List Pointer-Upper Base Address */
850
851 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD3CTL) }, /* Input Stream Descriptor 3 (ISD3) Control */
852 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD3STS) }, /* ISD3 Status */
853 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3LPIB) }, /* ISD3 Link Position In Buffer */
854 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3CBL) }, /* ISD3 Cyclic Buffer Length */
855 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD3LVI) }, /* ISD3 Last Valid Index */
856 { 0x000EE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD3FIFOW) }, /* ISD3 FIFO Watermark */
857 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD3FIFOS) }, /* ISD3 FIFO Size */
858 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD3FMT) }, /* ISD3 Format */
859 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD3BDPL) }, /* ISD3 Buffer Descriptor List Pointer-Lower Base Address */
860 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD3BDPU) }, /* ISD3 Buffer Descriptor List Pointer-Upper Base Address */
861
862 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD4CTL) }, /* Output Stream Descriptor 4 (OSD4) Control */
863 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD4STS) }, /* OSD4 Status */
864 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4LPIB) }, /* OSD4 Link Position In Buffer */
865 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4CBL) }, /* OSD4 Cyclic Buffer Length */
866 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD4LVI) }, /* OSD4 Last Valid Index */
867 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD4FIFOW) }, /* OSD4 FIFO Watermark */
868 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD4FIFOS) }, /* OSD4 FIFO Size */
869 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD4FMT) }, /* OSD4 Format */
870 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD4BDPL) }, /* OSD4 Buffer Descriptor List Pointer-Lower Base Address */
871 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD4BDPU) }, /* OSD4 Buffer Descriptor List Pointer-Upper Base Address */
872
873 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD5CTL) }, /* Output Stream Descriptor 5 (OSD5) Control */
874 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD5STS) }, /* OSD5 Status */
875 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5LPIB) }, /* OSD5 Link Position In Buffer */
876 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5CBL) }, /* OSD5 Cyclic Buffer Length */
877 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD5LVI) }, /* OSD5 Last Valid Index */
878 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD5FIFOW) }, /* OSD5 FIFO Watermark */
879 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD5FIFOS) }, /* OSD5 FIFO Size */
880 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD5FMT) }, /* OSD5 Format */
881 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD5BDPL) }, /* OSD5 Buffer Descriptor List Pointer-Lower Base Address */
882 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD5BDPU) }, /* OSD5 Buffer Descriptor List Pointer-Upper Base Address */
883
884 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD6CTL) }, /* Output Stream Descriptor 6 (OSD6) Control */
885 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD6STS) }, /* OSD6 Status */
886 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6LPIB) }, /* OSD6 Link Position In Buffer */
887 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6CBL) }, /* OSD6 Cyclic Buffer Length */
888 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD6LVI) }, /* OSD6 Last Valid Index */
889 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD6FIFOW) }, /* OSD6 FIFO Watermark */
890 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD6FIFOS) }, /* OSD6 FIFO Size */
891 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD6FMT) }, /* OSD6 Format */
892 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD6BDPL) }, /* OSD6 Buffer Descriptor List Pointer-Lower Base Address */
893 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD6BDPU) }, /* OSD6 Buffer Descriptor List Pointer-Upper Base Address */
894
895 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD7CTL) }, /* Output Stream Descriptor 7 (OSD7) Control */
896 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD7STS) }, /* OSD7 Status */
897 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7LPIB) }, /* OSD7 Link Position In Buffer */
898 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7CBL) }, /* OSD7 Cyclic Buffer Length */
899 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD7LVI) }, /* OSD7 Last Valid Index */
900 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD7FIFOW) }, /* OSD7 FIFO Watermark */
901 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD7FIFOS) }, /* OSD7 FIFO Size */
902 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD7FMT) }, /* OSD7 Format */
903 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD7BDPL) }, /* OSD7 Buffer Descriptor List Pointer-Lower Base Address */
904 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD7BDPU) }, /* OSD7 Buffer Descriptor List Pointer-Upper Base Address */
905};
906
907/**
908 * HDA register aliases (HDA spec 3.3.45).
909 * @remarks Sorted by offReg.
910 */
911static const struct
912{
913 /** The alias register offset. */
914 uint32_t offReg;
915 /** The register index. */
916 int idxAlias;
917} g_aHdaRegAliases[] =
918{
919 { 0x2084, HDA_REG_SD0LPIB },
920 { 0x20a4, HDA_REG_SD1LPIB },
921 { 0x20c4, HDA_REG_SD2LPIB },
922 { 0x20e4, HDA_REG_SD3LPIB },
923 { 0x2104, HDA_REG_SD4LPIB },
924 { 0x2124, HDA_REG_SD5LPIB },
925 { 0x2144, HDA_REG_SD6LPIB },
926 { 0x2164, HDA_REG_SD7LPIB },
927};
928
929#ifdef IN_RING3
930/** HDABDLEDESC field descriptors the v3+ saved state. */
931static SSMFIELD const g_aHdaBDLEDescFields[] =
932{
933 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
934 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
935 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
936 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
937 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
938 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
939 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
940 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
941 SSMFIELD_ENTRY_TERM()
942};
943
944/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
945static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
946{
947 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
948 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
949 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
950 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
951 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
952 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
953 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
954 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
955 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
956 SSMFIELD_ENTRY_TERM()
957};
958#endif
959
960/**
961 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
962 */
963static uint32_t const g_afMasks[5] =
964{
965 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
966};
967
968#ifdef IN_RING3
969DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
970{
971 if (pThis->u64DPBase & DPBASE_ENABLED)
972 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
973 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
974 pStreamDesc->pu32Lpib, sizeof(uint32_t));
975}
976#endif
977
978DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
979{
980#if 0
981 switch(HDA_STREAM_REG(pThis, FIFOW, pStreamDesc->u8Strm))
982 {
983 case HDA_SDFIFOW_8B: return 8;
984 case HDA_SDFIFOW_16B: return 16;
985 case HDA_SDFIFOW_32B: return 32;
986 default:
987 AssertMsgFailed(("unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
988 }
989#endif
990 return 0;
991}
992
993static int hdaProcessInterrupt(PHDASTATE pThis)
994{
995#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
996 ( INTCTL_SX((pThis), num) \
997 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
998 bool fIrq = false;
999 if ( HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1000 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1001 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1002 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1003 fIrq = true;
1004
1005 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1006 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1007 fIrq = true;
1008
1009 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1010 {
1011 LogFunc(("irq %s\n", fIrq ? "asserted" : "deasserted"));
1012 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1013 }
1014 return VINF_SUCCESS;
1015}
1016
1017/**
1018 * Looks up a register at the exact offset given by @a offReg.
1019 *
1020 * @returns Register index on success, -1 if not found.
1021 * @param pThis The HDA device state.
1022 * @param offReg The register offset.
1023 */
1024static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1025{
1026 /*
1027 * Aliases.
1028 */
1029 if (offReg >= g_aHdaRegAliases[0].offReg)
1030 {
1031 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1032 if (offReg == g_aHdaRegAliases[i].offReg)
1033 return g_aHdaRegAliases[i].idxAlias;
1034 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1035 return -1;
1036 }
1037
1038 /*
1039 * Binary search the
1040 */
1041 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1042 int idxLow = 0;
1043 for (;;)
1044 {
1045 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1046 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1047 {
1048 if (idxLow == idxMiddle)
1049 break;
1050 idxEnd = idxMiddle;
1051 }
1052 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1053 {
1054 idxLow = idxMiddle + 1;
1055 if (idxLow >= idxEnd)
1056 break;
1057 }
1058 else
1059 return idxMiddle;
1060 }
1061
1062#ifdef RT_STRICT
1063 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1064 Assert(g_aHdaRegMap[i].offset != offReg);
1065#endif
1066 return -1;
1067}
1068
1069/**
1070 * Looks up a register covering the offset given by @a offReg.
1071 *
1072 * @returns Register index on success, -1 if not found.
1073 * @param pThis The HDA device state.
1074 * @param offReg The register offset.
1075 */
1076static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1077{
1078 /*
1079 * Aliases.
1080 */
1081 if (offReg >= g_aHdaRegAliases[0].offReg)
1082 {
1083 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1084 {
1085 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1086 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1087 return g_aHdaRegAliases[i].idxAlias;
1088 }
1089 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1090 return -1;
1091 }
1092
1093 /*
1094 * Binary search the
1095 */
1096 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1097 int idxLow = 0;
1098 for (;;)
1099 {
1100 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1101 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1102 {
1103 if (idxLow == idxMiddle)
1104 break;
1105 idxEnd = idxMiddle;
1106 }
1107 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1108 {
1109 idxLow = idxMiddle + 1;
1110 if (idxLow >= idxEnd)
1111 break;
1112 }
1113 else
1114 return idxMiddle;
1115 }
1116
1117#ifdef RT_STRICT
1118 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1119 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1120#endif
1121 return -1;
1122}
1123
1124#ifdef IN_RING3
1125static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1126{
1127 int rc = VINF_SUCCESS;
1128 if (fLocal)
1129 {
1130 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1131 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1132 if (RT_FAILURE(rc))
1133 AssertRCReturn(rc, rc);
1134#ifdef DEBUG_CMD_BUFFER
1135 uint8_t i = 0;
1136 do
1137 {
1138 LogFunc(("corb%02x: ", i));
1139 uint8_t j = 0;
1140 do
1141 {
1142 const char *prefix;
1143 if ((i + j) == HDA_REG(pThis, CORBRP));
1144 prefix = "[R]";
1145 else if ((i + j) == HDA_REG(pThis, CORBWP));
1146 prefix = "[W]";
1147 else
1148 prefix = " "; /* three spaces */
1149 LogFunc(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
1150 j++;
1151 } while (j < 8);
1152 LogFunc(("\n"));
1153 i += 8;
1154 } while(i != 0);
1155#endif
1156 }
1157 else
1158 {
1159 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1160 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1161 if (RT_FAILURE(rc))
1162 AssertRCReturn(rc, rc);
1163#ifdef DEBUG_CMD_BUFFER
1164 uint8_t i = 0;
1165 do {
1166 LogFunc(("rirb%02x: ", i));
1167 uint8_t j = 0;
1168 do {
1169 const char *prefix;
1170 if ((i + j) == HDA_REG(pThis, RIRBWP))
1171 prefix = "[W]";
1172 else
1173 prefix = " ";
1174 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1175 } while (++j < 8);
1176 LogFunc(("\n"));
1177 i += 8;
1178 } while (i != 0);
1179#endif
1180 }
1181 return rc;
1182}
1183
1184static int hdaCORBCmdProcess(PHDASTATE pThis)
1185{
1186 int rc;
1187 uint8_t corbRp;
1188 uint8_t corbWp;
1189 uint8_t rirbWp;
1190
1191 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1192
1193 rc = hdaCmdSync(pThis, true);
1194 if (RT_FAILURE(rc))
1195 AssertRCReturn(rc, rc);
1196 corbRp = HDA_REG(pThis, CORBRP);
1197 corbWp = HDA_REG(pThis, CORBWP);
1198 rirbWp = HDA_REG(pThis, RIRBWP);
1199 Assert((corbWp != corbRp));
1200 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1201 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1202 while (corbRp != corbWp)
1203 {
1204 uint32_t cmd;
1205 uint64_t resp;
1206 pfn = NULL;
1207 corbRp++;
1208 cmd = pThis->pu32CorbBuf[corbRp];
1209
1210 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1211 HDA_CODEC_CMD(cmd, 0 /* Codec index */),
1212 &pfn);
1213 if (RT_SUCCESS(rc))
1214 {
1215 rc = pfn(pThis->pCodec,
1216 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1217 }
1218
1219 if (RT_FAILURE(rc))
1220 AssertRCReturn(rc, rc);
1221 Assert(pfn);
1222 (rirbWp)++;
1223
1224 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1225 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1226 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1227 {
1228 LogFunc(("unexpected unsolicited response.\n"));
1229 HDA_REG(pThis, CORBRP) = corbRp;
1230 return rc;
1231 }
1232 pThis->pu64RirbBuf[rirbWp] = resp;
1233 pThis->u8Counter++;
1234 if (pThis->u8Counter == RINTCNT_N(pThis))
1235 break;
1236 }
1237 HDA_REG(pThis, CORBRP) = corbRp;
1238 HDA_REG(pThis, RIRBWP) = rirbWp;
1239 rc = hdaCmdSync(pThis, false);
1240 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1241 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1242 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1243 {
1244 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1245 pThis->u8Counter = 0;
1246 rc = hdaProcessInterrupt(pThis);
1247 }
1248 if (RT_FAILURE(rc))
1249 AssertRCReturn(rc, rc);
1250 return rc;
1251}
1252#endif
1253
1254static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
1255{
1256 LogFunc(("reset of stream (%d) started\n", u8Strm));
1257 Assert(( pThis
1258 && pBdle
1259 && pStreamDesc
1260 && u8Strm <= 7));
1261 RT_BZERO(pBdle, sizeof(HDABDLEDESC));
1262 *pStreamDesc->pu32Lpib = 0;
1263 *pStreamDesc->pu32Sts = 0;
1264 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1265 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
1266 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1267
1268 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1269 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1270 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
1271 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1272 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1273 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1274 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1275 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1276 LogFunc(("reset of stream (%d) finished\n", u8Strm));
1277}
1278
1279/* Register access handlers. */
1280
1281static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1282{
1283 *pu32Value = 0;
1284 return VINF_SUCCESS;
1285}
1286
1287static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1288{
1289 return VINF_SUCCESS;
1290}
1291
1292/* U8 */
1293static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1294{
1295 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1296 return hdaRegReadU32(pThis, iReg, pu32Value);
1297}
1298
1299static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1300{
1301 Assert((u32Value & 0xffffff00) == 0);
1302 return hdaRegWriteU32(pThis, iReg, u32Value);
1303}
1304
1305/* U16 */
1306static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1307{
1308 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1309 return hdaRegReadU32(pThis, iReg, pu32Value);
1310}
1311
1312static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1313{
1314 Assert((u32Value & 0xffff0000) == 0);
1315 return hdaRegWriteU32(pThis, iReg, u32Value);
1316}
1317
1318/* U24 */
1319static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1320{
1321 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1322 return hdaRegReadU32(pThis, iReg, pu32Value);
1323}
1324
1325static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1326{
1327 Assert((u32Value & 0xff000000) == 0);
1328 return hdaRegWriteU32(pThis, iReg, u32Value);
1329}
1330
1331/* U32 */
1332static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1333{
1334 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1335
1336 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1337 return VINF_SUCCESS;
1338}
1339
1340static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1341{
1342 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1343
1344 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1345 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1346 return VINF_SUCCESS;
1347}
1348
1349static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1350{
1351 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1352 {
1353 /* exit reset state */
1354 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1355 pThis->fInReset = false;
1356 }
1357 else
1358 {
1359#ifdef IN_RING3
1360 /* enter reset state*/
1361 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1362 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1363 {
1364 LogFunc(("HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1365 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1366 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1367 }
1368 hdaReset(pThis->CTX_SUFF(pDevIns));
1369 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1370 pThis->fInReset = true;
1371#else
1372 return VINF_IOM_R3_MMIO_WRITE;
1373#endif
1374 }
1375 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1376 {
1377 /* Flush: GSTS:1 set, see 6.2.6*/
1378 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1379 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1380 }
1381 return VINF_SUCCESS;
1382}
1383
1384static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1385{
1386 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1387
1388 uint32_t v = pThis->au32Regs[iRegMem];
1389 uint32_t nv = u32Value & HDA_STATES_SCSF;
1390 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1391 return VINF_SUCCESS;
1392}
1393
1394static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1395{
1396 uint32_t v = 0;
1397 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1398 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1399 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1400 || HDA_REG(pThis, STATESTS))
1401 v |= RT_BIT(30);
1402#define HDA_IS_STREAM_EVENT(pThis, stream) \
1403 ( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1404 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1405 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1406#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
1407 MARK_STREAM(pThis, 0, v);
1408 MARK_STREAM(pThis, 1, v);
1409 MARK_STREAM(pThis, 2, v);
1410 MARK_STREAM(pThis, 3, v);
1411 MARK_STREAM(pThis, 4, v);
1412 MARK_STREAM(pThis, 5, v);
1413 MARK_STREAM(pThis, 6, v);
1414 MARK_STREAM(pThis, 7, v);
1415 v |= v ? RT_BIT(31) : 0;
1416 *pu32Value = v;
1417 return VINF_SUCCESS;
1418}
1419
1420static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1421{
1422 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1423 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1424 - pThis->u64BaseTS, 24, 1000);
1425 return VINF_SUCCESS;
1426}
1427
1428static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1429{
1430 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1431 HDA_REG(pThis, CORBRP) = 0;
1432#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1433 else
1434 return hdaRegWriteU8(pThis, iReg, u32Value);
1435#endif
1436 return VINF_SUCCESS;
1437}
1438
1439static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1440{
1441#ifdef IN_RING3
1442 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1443 AssertRC(rc);
1444 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1445 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1446 return hdaCORBCmdProcess(pThis);
1447 return rc;
1448#else
1449 return VINF_IOM_R3_MMIO_WRITE;
1450#endif
1451}
1452
1453static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1454{
1455 uint32_t v = HDA_REG(pThis, CORBSTS);
1456 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1457 return VINF_SUCCESS;
1458}
1459
1460static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1461{
1462#ifdef IN_RING3
1463 int rc;
1464 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1465 if (RT_FAILURE(rc))
1466 AssertRCReturn(rc, rc);
1467 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1468 return VINF_SUCCESS;
1469 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1470 return VINF_SUCCESS;
1471 rc = hdaCORBCmdProcess(pThis);
1472 return rc;
1473#else
1474 return VINF_IOM_R3_MMIO_WRITE;
1475#endif
1476}
1477
1478static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1479{
1480 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1481 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1482 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1483 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1484
1485 if (fInReset)
1486 {
1487 /*
1488 * Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1489 * from reset
1490 */
1491 Assert((!fReset));
1492 LogFunc(("guest initiated exit of stream reset.\n"));
1493 }
1494 else if (fReset)
1495 {
1496#ifdef IN_RING3
1497 /*
1498 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1499 */
1500 uint8_t u8Strm = 0;
1501 PHDABDLEDESC pBdle = NULL;
1502 HDASTREAMTRANSFERDESC StreamDesc;
1503 Assert((!fInRun && !fRun));
1504 switch (iReg)
1505 {
1506 case HDA_REG_SD0CTL:
1507 u8Strm = 0;
1508 pBdle = &pThis->StInBdle;
1509 break;
1510#ifdef VBOX_WITH_HDA_MIC_IN
1511 case HDA_REG_SD2CTL:
1512 u8Strm = 2;
1513 pBdle = &pThis->StMicBdle;
1514 break;
1515#endif
1516 case HDA_REG_SD4CTL:
1517 u8Strm = 4;
1518 pBdle = &pThis->StOutBdle;
1519 break;
1520 default:
1521 LogFunc(("changing SRST bit on non-attached stream\n"));
1522 return hdaRegWriteU24(pThis, iReg, u32Value);
1523 }
1524 LogFunc(("guest initiated enter to stream reset.\n"));
1525 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1526 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
1527#else
1528 return VINF_IOM_R3_MMIO_WRITE;
1529#endif
1530 }
1531 else
1532 {
1533#ifdef IN_RING3
1534 /* we enter here to change DMA states only */
1535 if ( (fInRun && !fRun)
1536 || (fRun && !fInRun))
1537 {
1538 Assert((!fReset && !fInReset));
1539
1540 PHDADRIVER pDrv;
1541 switch (iReg)
1542 {
1543 case HDA_REG_SD0CTL:
1544 {
1545 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1546 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1547 pDrv->LineIn.pStrmIn, fRun);
1548 break;
1549 }
1550# ifdef VBOX_WITH_HDA_MIC_IN
1551 case HDA_REG_SD2CTL:
1552 {
1553 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1554 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1555 pDrv->MicIn.pStrmIn, fRun);
1556 break;
1557 }
1558# endif
1559 case HDA_REG_SD4CTL:
1560 {
1561 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1562 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1563 pDrv->Out.pStrmOut, fRun);
1564 break;
1565 }
1566 default:
1567 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1568 break;
1569 }
1570 }
1571#else /* !IN_RING3 */
1572 return VINF_IOM_R3_MMIO_WRITE;
1573#endif /* IN_RING3 */
1574 }
1575
1576 return hdaRegWriteU24(pThis, iReg, u32Value);
1577}
1578
1579static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1580{
1581 uint32_t v = HDA_REG_IND(pThis, iReg);
1582 v &= ~(u32Value & v);
1583 HDA_REG_IND(pThis, iReg) = v;
1584 hdaProcessInterrupt(pThis);
1585 return VINF_SUCCESS;
1586}
1587
1588static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1589{
1590 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1591 if (RT_FAILURE(rc))
1592 AssertRCReturn(rc, VINF_SUCCESS);
1593 return rc;
1594}
1595
1596static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1597{
1598 switch (u32Value)
1599 {
1600 case HDA_SDFIFOW_8B:
1601 case HDA_SDFIFOW_16B:
1602 case HDA_SDFIFOW_32B:
1603 return hdaRegWriteU16(pThis, iReg, u32Value);
1604 default:
1605 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1606 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1607 }
1608 return VINF_SUCCESS;
1609}
1610
1611/**
1612 * @note This method could be called for changing value on Output Streams
1613 * only (ICH6 datasheet 18.2.39)
1614 */
1615static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1616{
1617 switch (iReg)
1618 {
1619 /* SDInFIFOS is RO, n=0-3 */
1620 case HDA_REG_SD0FIFOS:
1621 case HDA_REG_SD1FIFOS:
1622 case HDA_REG_SD2FIFOS:
1623 case HDA_REG_SD3FIFOS:
1624 LogFunc(("Guest tries change value of FIFO size of input stream\n"));
1625 break;
1626 case HDA_REG_SD4FIFOS:
1627 case HDA_REG_SD5FIFOS:
1628 case HDA_REG_SD6FIFOS:
1629 case HDA_REG_SD7FIFOS:
1630 switch(u32Value)
1631 {
1632 case HDA_SDONFIFO_16B:
1633 case HDA_SDONFIFO_32B:
1634 case HDA_SDONFIFO_64B:
1635 case HDA_SDONFIFO_128B:
1636 case HDA_SDONFIFO_192B:
1637 return hdaRegWriteU16(pThis, iReg, u32Value);
1638
1639 case HDA_SDONFIFO_256B:
1640 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1641 default:
1642 return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);
1643 }
1644 break;
1645 default:
1646 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
1647 }
1648
1649 return VINF_SUCCESS;
1650}
1651
1652#ifdef IN_RING3
1653static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
1654{
1655 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1656
1657# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1658
1659 int rc = VINF_SUCCESS;
1660
1661 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1662 uint32_t u32HzMult = 1;
1663 uint32_t u32HzDiv = 1;
1664
1665 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
1666 {
1667 case 0: u32HzMult = 1; break;
1668 case 1: u32HzMult = 2; break;
1669 case 2: u32HzMult = 3; break;
1670 case 3: u32HzMult = 4; break;
1671 default:
1672 LogFunc(("Unsupported multiplier %x\n",
1673 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
1674 rc = VERR_NOT_SUPPORTED;
1675 break;
1676 }
1677 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
1678 {
1679 case 0: u32HzDiv = 1; break;
1680 case 1: u32HzDiv = 2; break;
1681 case 2: u32HzDiv = 3; break;
1682 case 3: u32HzDiv = 4; break;
1683 case 4: u32HzDiv = 5; break;
1684 case 5: u32HzDiv = 6; break;
1685 case 6: u32HzDiv = 7; break;
1686 case 7: u32HzDiv = 8; break;
1687 default:
1688 LogFunc(("Unsupported divisor %x\n",
1689 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
1690 rc = VERR_NOT_SUPPORTED;
1691 break;
1692 }
1693
1694 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1695 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
1696 {
1697 case 0:
1698 LogFunc(("Requested 8-bit\n"));
1699 enmFmt = AUD_FMT_S8;
1700 break;
1701 case 1:
1702 LogFunc(("Requested 16-bit\n"));
1703 enmFmt = AUD_FMT_S16;
1704 break;
1705 case 2:
1706 LogFunc(("Requested 20-bit\n"));
1707 break;
1708 case 3:
1709 LogFunc(("Requested 24-bit\n"));
1710 break;
1711 case 4:
1712 LogFunc(("Requested 32-bit\n"));
1713 enmFmt = AUD_FMT_S32;
1714 break;
1715 default:
1716 AssertMsgFailed(("Unsupported bits shift %x\n",
1717 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
1718 rc = VERR_NOT_SUPPORTED;
1719 break;
1720 }
1721
1722 if (RT_SUCCESS(rc))
1723 {
1724 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
1725 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
1726 pCfg->enmFormat = enmFmt;
1727 pCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
1728 }
1729
1730# undef EXTRACT_VALUE
1731
1732 return rc;
1733}
1734#endif
1735
1736static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1737{
1738#ifdef IN_RING3
1739# ifdef VBOX_WITH_HDA_CODEC_EMU
1740 /* No reason to reopen voice with same settings. */
1741 if (u32Value == HDA_REG_IND(pThis, iReg))
1742 return VINF_SUCCESS;
1743
1744 PDMAUDIOSTREAMCFG as;
1745 int rc = hdaSdFmtToAudSettings(u32Value, &as);
1746 if (RT_FAILURE(rc))
1747 return rc;
1748
1749 PHDADRIVER pDrv;
1750 switch (iReg)
1751 {
1752 case HDA_REG_SD0FMT:
1753 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1754 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &as);
1755 break;
1756# ifdef VBOX_WITH_HDA_MIC_IN
1757 case HDA_REG_SD2FMT:
1758 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1759 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &as);
1760 break;
1761# endif
1762 default:
1763 LogFunc(("Warning: Attempt to change format on register %d\n", iReg));
1764 break;
1765 }
1766
1767 /** @todo r=andy rc gets lost; needs fixing. */
1768 return hdaRegWriteU16(pThis, iReg, u32Value);
1769# else /* !VBOX_WITH_HDA_CODEC_EMU */
1770 return hdaRegWriteU16(pThis, iReg, u32Value);
1771# endif
1772#else /* !IN_RING3 */
1773 return VINF_IOM_R3_MMIO_WRITE;
1774#endif
1775}
1776
1777static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1778{
1779 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1780 if (RT_FAILURE(rc))
1781 AssertRCReturn(rc, VINF_SUCCESS);
1782 return rc;
1783}
1784
1785static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1786{
1787 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1788 if (RT_FAILURE(rc))
1789 AssertRCReturn(rc, VINF_SUCCESS);
1790 return rc;
1791}
1792
1793static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1794{
1795 int rc = VINF_SUCCESS;
1796 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1797 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1798 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1799 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1800
1801 rc = hdaRegReadU32(pThis, iReg, pu32Value);
1802 return rc;
1803}
1804
1805static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1806{
1807 int rc = VINF_SUCCESS;
1808
1809 /*
1810 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1811 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1812 */
1813 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1814 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
1815 {
1816#ifdef IN_RING3
1817 PFNHDACODECVERBPROCESSOR pfn = NULL;
1818 uint64_t resp;
1819 uint32_t cmd = HDA_REG(pThis, IC);
1820 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
1821 {
1822 /*
1823 * 3.4.3 defines behavior of immediate Command status register.
1824 */
1825 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
1826 return rc;
1827 }
1828 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1829 LogFunc(("IC:%x\n", cmd));
1830
1831 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1832 HDA_CODEC_CMD(cmd, 0 /* LUN */),
1833 &pfn);
1834 if (RT_FAILURE(rc))
1835 AssertRCReturn(rc, rc);
1836 rc = pfn(pThis->pCodec,
1837 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1838 if (RT_FAILURE(rc))
1839 AssertRCReturn(rc, rc);
1840
1841 HDA_REG(pThis, IR) = (uint32_t)resp;
1842 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
1843 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1844 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1845#else /* !IN_RING3 */
1846 rc = VINF_IOM_R3_MMIO_WRITE;
1847#endif
1848 return rc;
1849 }
1850 /*
1851 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1852 */
1853 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1854 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
1855 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1856 return rc;
1857}
1858
1859static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1860{
1861 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1862 {
1863 HDA_REG(pThis, RIRBWP) = 0;
1864 }
1865 /* The remaining bits are O, see 6.2.22 */
1866 return VINF_SUCCESS;
1867}
1868
1869static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1870{
1871 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1872 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1873 if (RT_FAILURE(rc))
1874 AssertRCReturn(rc, rc);
1875
1876 switch(iReg)
1877 {
1878 case HDA_REG_CORBLBASE:
1879 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
1880 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
1881 break;
1882 case HDA_REG_CORBUBASE:
1883 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
1884 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1885 break;
1886 case HDA_REG_RIRBLBASE:
1887 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
1888 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
1889 break;
1890 case HDA_REG_RIRBUBASE:
1891 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
1892 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1893 break;
1894 case HDA_REG_DPLBASE:
1895 /** @todo: first bit has special meaning */
1896 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
1897 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
1898 break;
1899 case HDA_REG_DPUBASE:
1900 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
1901 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1902 break;
1903 default:
1904 AssertMsgFailed(("Invalid index"));
1905 break;
1906 }
1907
1908 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
1909 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
1910 return rc;
1911}
1912
1913static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1914{
1915 uint8_t v = HDA_REG(pThis, RIRBSTS);
1916 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
1917
1918 return hdaProcessInterrupt(pThis);
1919}
1920
1921#ifdef IN_RING3
1922#ifdef LOG_ENABLED
1923static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1924{
1925#if 0
1926 uint64_t addr;
1927 uint32_t len;
1928 uint32_t ioc;
1929 uint8_t bdle[16];
1930 uint32_t counter;
1931 uint32_t i;
1932 uint32_t sum = 0;
1933 Assert(pBdle && pBdle->u32BdleMaxCvi);
1934 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1935 {
1936 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i*16, bdle, 16);
1937 addr = *(uint64_t *)bdle;
1938 len = *(uint32_t *)&bdle[8];
1939 ioc = *(uint32_t *)&bdle[12];
1940 LogFunc(("%s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1941 sum += len;
1942 }
1943 LogFunc(("sum: %d\n", sum));
1944 for (i = 0; i < 8; ++i)
1945 {
1946 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1947 LogFunc(("%s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
1948 i , counter));
1949 }
1950#endif
1951}
1952#endif
1953
1954static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1955{
1956 uint8_t bdle[16];
1957 Assert(( pStreamDesc->u64BaseDMA
1958 && pBdle
1959 && pBdle->u32BdleMaxCvi));
1960 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1961 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1962 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1963 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1964#ifdef LOG_ENABLED
1965 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
1966#endif
1967}
1968
1969DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1970 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1971{
1972 /*
1973 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
1974 */
1975 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1976 uint32_t cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1977 /*
1978 * we may increase the counter in range of [0, FIFOS + 1]
1979 */
1980 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1981 Assert((u32SoundBackendBufferBytesAvail > 0));
1982
1983 /* sanity check to avoid overriding the backend audio buffer */
1984 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1985 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1986
1987 if (cb2Copy <= pBdle->cbUnderFifoW)
1988 return 0;
1989 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
1990 return cb2Copy;
1991}
1992
1993DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1994 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1995{
1996 LogFunc(("cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1997 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1998 Assert((cbCopied));
1999 AssertPtr(pu32DMACursor);
2000 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
2001 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
2002 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2003 * where it might happen.
2004 */
2005 AssertMsg((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy), /* we assume that we write the entire buffer including unreported bytes */
2006 ("cbCopied=%RU32 != pBdle->cbUnderFifoW=%RU32 + cbArranged2Copy=%RU32\n",
2007 cbCopied, pBdle->cbUnderFifoW, cbArranged2Copy));
2008 if ( pBdle->cbUnderFifoW
2009 && pBdle->cbUnderFifoW <= cbCopied)
2010 {
2011 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n",
2012 pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2013 }
2014
2015 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
2016 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
2017
2018 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
2019 pBdle->u32BdleCviPos += cbArranged2Copy;
2020
2021 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
2022 /* We report all bytes (including previously unreported bytes) */
2023 *pu32DMACursor += cbCopied;
2024 /* Decrease the backend counter by the number of bytes we copied to the backend */
2025 *pu32BackendBufferCapacity -= cbCopied;
2026 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2027 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
2028}
2029
2030DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2031 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2032{
2033 Assert((cbCopied, cbArranged2Copy));
2034 *pu32BackendBufferCapacity -= cbCopied;
2035 pBdle->u32BdleCviPos += cbCopied;
2036 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2037 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
2038 pBdle->cbUnderFifoW = 0;
2039 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2040 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2041}
2042
2043DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2044 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
2045{
2046 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2047 pBdle->u32BdleCviPos += cbCopied;
2048 pBdle->cbUnderFifoW += cbCopied;
2049 /* In case of a read transaction we're always copying from the backend buffer */
2050 if (pu32BackendBufferCapacity)
2051 *pu32BackendBufferCapacity -= cbCopied;
2052 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2053 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
2054}
2055
2056DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2057{
2058 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
2059 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
2060
2061 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2062
2063 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2064 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
2065 hdaUpdatePosBuf(pThis, pStreamDesc);
2066
2067 /* don't touch BdleCvi counter on uninitialized descriptor */
2068 if ( pBdle->u32BdleCviPos
2069 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
2070 {
2071 pBdle->u32BdleCviPos = 0;
2072 pBdle->u32BdleCvi++;
2073 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
2074 pBdle->u32BdleCvi = 0;
2075 }
2076 return fOnBufferEdge;
2077}
2078
2079DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2080 uint32_t cbInc)
2081{
2082 /*
2083 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
2084 * (ICH6 datasheet 18.2.38)
2085 */
2086 if (!pBdle->cbUnderFifoW)
2087 {
2088 *pStreamDesc->pu32Lpib += cbInc;
2089
2090 /*
2091 * Assert. The buffer counters should never overlap.
2092 */
2093 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2094
2095 hdaUpdatePosBuf(pThis, pStreamDesc);
2096 }
2097}
2098
2099static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2100{
2101 bool fDoNextTransferLoop = true;
2102 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
2103 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2104 {
2105 if ( !pBdle->cbUnderFifoW
2106 && pBdle->fBdleCviIoc)
2107 {
2108 /**
2109 * @todo - more carefully investigate BCIS flag.
2110 * Speech synthesis works fine on Mac Guest if this bit isn't set
2111 * but in general sound quality gets worse.
2112 */
2113 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2114
2115 /*
2116 * we should generate the interrupt if ICE bit of SDCTL register is set.
2117 */
2118 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2119 hdaProcessInterrupt(pThis);
2120 }
2121 fDoNextTransferLoop = false;
2122 }
2123 return fDoNextTransferLoop;
2124}
2125
2126/**
2127 * hdaReadAudio - copies samples from audio backend to DMA.
2128 * Note: This function writes to the DMA buffer immediately,
2129 * but "reports bytes" when all conditions are met (FIFOW).
2130 */
2131static int hdaReadAudio(PHDASTATE pThis, PAUDMIXSINK pSink,
2132 PHDASTREAMTRANSFERDESC pStreamDesc,
2133 uint32_t u32CblLimit, uint32_t *pcbAvail, uint32_t *pcbRead)
2134{
2135 PHDABDLEDESC pBdle = &pThis->StInBdle; /** @todo Add support for mic in. */
2136
2137 int rc;
2138 uint32_t cbTransferred = 0;
2139
2140 LogFlowFunc(("CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2141
2142 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2143 if (!cb2Copy)
2144 {
2145 /* If we enter here we can't report "unreported bits". */
2146 rc = VERR_NO_DATA;
2147 }
2148 else
2149 {
2150 uint32_t cbRead = 0;
2151 rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pBdle->au8HdaBuffer, cb2Copy, &cbRead);
2152 if (RT_SUCCESS(rc))
2153 {
2154 Assert(cbRead);
2155
2156 /*
2157 * Write the HDA DMA buffer.
2158 */
2159 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2160 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2161 pBdle->au8HdaBuffer, cbRead);
2162
2163 /* Don't see any reason why cb2Copy would differ from cbRead. */
2164 Assert((cbRead == cb2Copy && (*pcbAvail) >= cb2Copy)); /* sanity */
2165
2166 if (pBdle->cbUnderFifoW + cbRead > hdaFifoWToSz(pThis, 0))
2167 hdaBackendReadTransferReported(pBdle, cb2Copy, cbRead, &cbTransferred, pcbAvail);
2168 else
2169 {
2170 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbRead, pcbAvail);
2171 rc = VERR_NO_DATA;
2172 }
2173 }
2174 }
2175
2176 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2177 LogFunc(("CVI(pos:%RU32, len:%RU32), cbTransferred=%RU32, rc=%Rrc\n",
2178 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2179
2180 if (RT_SUCCESS(rc))
2181 *pcbRead = cbTransferred;
2182
2183 return rc;
2184}
2185
2186static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32CblLimit,
2187 uint32_t *pcbAvail, uint32_t *pcbWritten)
2188{
2189 PHDABDLEDESC pBdle = &pThis->StOutBdle;
2190
2191 int rc = VINF_SUCCESS;
2192
2193 uint32_t cbTransferred = 0;
2194 uint32_t cbWrittenMin = 0; /* local byte counter, how many bytes copied to backend */
2195
2196 LogFunc(("CVI(cvi:%RU32, pos:%RU32, len:%RU32)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2197
2198 /* Local byte counter (on local buffer). */
2199 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2200
2201 /*
2202 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
2203 * previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
2204 */
2205 if (!cb2Copy)
2206 {
2207 rc = VINF_EOF;
2208 }
2209 else
2210 {
2211 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2212 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2213 pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
2214
2215#ifdef VBOX_WITH_STATISTICS
2216 STAM_COUNTER_ADD(&pThis->StatBytesRead, cb2Copy);
2217#endif
2218
2219 /*
2220 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2221 */
2222 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
2223 {
2224 uint32_t cbWritten;
2225 cbWrittenMin = UINT32_MAX;
2226
2227 PHDADRIVER pDrv;
2228 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2229 {
2230 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2231 {
2232 int rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2233 pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW,
2234 &cbWritten);
2235 if (RT_FAILURE(rc2))
2236 continue;
2237 }
2238 else /* Stream disabled, just assume all was copied. */
2239 cbWritten = cb2Copy;
2240
2241 cbWrittenMin = RT_MIN(cbWrittenMin, cbWritten);
2242 LogFlowFunc(("\tLUN#%RU8: cbWritten=%RU32, cWrittenMin=%RU32\n", pDrv->uLUN, cbWritten, cbWrittenMin));
2243 }
2244
2245 if (cbWrittenMin == UINT32_MAX)
2246 cbWrittenMin = 0;
2247
2248 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbWrittenMin, &cbTransferred, pcbAvail);
2249 }
2250 else
2251 {
2252 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2253 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
2254 rc = VINF_EOF;
2255 }
2256 }
2257
2258 Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
2259 LogFunc(("CVI(pos:%RU32, len:%RU32, cbTransferred:%RU32), rc=%Rrc\n",
2260 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2261
2262 if (RT_SUCCESS(rc))
2263 *pcbWritten = cbTransferred;
2264
2265 return rc;
2266}
2267
2268/**
2269 * @interface_method_impl{HDACODEC,pfnReset}
2270 */
2271DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2272{
2273 PHDASTATE pThis = pCodec->pHDAState;
2274 NOREF(pThis);
2275 return VINF_SUCCESS;
2276}
2277
2278DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
2279 PHDASTREAMTRANSFERDESC pStreamDesc)
2280{
2281 Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
2282
2283 RT_BZERO(pStreamDesc, sizeof(HDASTREAMTRANSFERDESC));
2284 pStreamDesc->u8Strm = u8Strm;
2285 pStreamDesc->u32Ctl = HDA_STREAM_REG(pThis, CTL, u8Strm);
2286 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2287 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2288 pStreamDesc->pu32Lpib = &HDA_STREAM_REG(pThis, LPIB, u8Strm);
2289 pStreamDesc->pu32Sts = &HDA_STREAM_REG(pThis, STS, u8Strm);
2290 pStreamDesc->u32Cbl = HDA_STREAM_REG(pThis, CBL, u8Strm);
2291 pStreamDesc->u32Fifos = HDA_STREAM_REG(pThis, FIFOS, u8Strm);
2292
2293 pBdle->u32BdleMaxCvi = HDA_STREAM_REG(pThis, LVI, u8Strm);
2294
2295#ifdef LOG_ENABLED
2296 if ( pBdle
2297 && pBdle->u32BdleMaxCvi)
2298 {
2299 LogFunc(("Initialization of transfer descriptor:\n"));
2300 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2301 }
2302#endif
2303}
2304
2305static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2306{
2307 NOREF(pThis);
2308 NOREF(enmRecSource);
2309 LogFlowFuncEnter();
2310}
2311
2312static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2313{
2314 NOREF(pThis);
2315 LogFlowFuncEnter();
2316}
2317
2318static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2319 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2320 PPDMAUDIOSTREAMCFG pCfg)
2321{
2322 PAUDMIXSINK pSink;
2323
2324 switch (enmRecSource)
2325 {
2326# ifdef VBOX_WITH_HDA_MIC_IN
2327 case PDMAUDIORECSOURCE_MIC:
2328 pSink = pThis->pSinkMicIn;
2329 break;
2330# endif
2331 case PDMAUDIORECSOURCE_LINE_IN:
2332 pSink = pThis->pSinkLineIn;
2333 break;
2334 default:
2335 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2336 return VERR_NOT_SUPPORTED;
2337 }
2338
2339 int rc = VINF_SUCCESS;
2340 char *pszDesc;
2341
2342 PHDADRIVER pDrv;
2343 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2344 {
2345 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2346 {
2347 rc = VERR_NO_MEMORY;
2348 break;
2349 }
2350
2351 rc = pDrv->pConnector->pfnOpenIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2352 LogFlowFunc(("LUN#%RU8: Opened input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2353 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2354 {
2355 AudioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2356 rc = AudioMixerAddStreamIn(pSink,
2357 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2358 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2359 }
2360
2361 RTStrFree(pszDesc);
2362 }
2363
2364 LogFlowFuncLeaveRC(rc);
2365 return rc;
2366}
2367
2368static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2369 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2370{
2371 int rc = VINF_SUCCESS;
2372 char *pszDesc;
2373
2374 PHDADRIVER pDrv;
2375 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2376 {
2377 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2378 {
2379 rc = VERR_NO_MEMORY;
2380 break;
2381 }
2382
2383 rc = pDrv->pConnector->pfnOpenOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
2384 LogFlowFunc(("LUN#%RU8: Opened output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2385 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2386 {
2387 AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
2388 rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
2389 pDrv->pConnector, pDrv->Out.pStrmOut,
2390 0 /* uFlags */, &pDrv->Out.phStrmOut);
2391 }
2392
2393 RTStrFree(pszDesc);
2394 }
2395
2396 LogFlowFuncLeaveRC(rc);
2397 return rc;
2398}
2399
2400static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis, ENMSOUNDSOURCE enmSource,
2401 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2402{
2403 int rc = VINF_SUCCESS;
2404 PDMAUDIOVOLUME vol = { fMute, uVolLeft, uVolRight };
2405 PAUDMIXSINK pSink;
2406
2407 /* Convert the audio source to corresponding sink. */
2408 switch (enmSource) {
2409 case PO_INDEX:
2410 pSink = pThis->pSinkOutput;
2411 break;
2412 case PI_INDEX:
2413 pSink = pThis->pSinkLineIn;
2414 break;
2415 case MC_INDEX:
2416 pSink = pThis->pSinkMicIn;
2417 break;
2418 default:
2419 AssertFailedReturn(VERR_INVALID_PARAMETER);
2420 }
2421
2422 /* Set the volume. Codec already converted it to the correct range. */
2423 AudioMixerSetSinkVolume(pSink, &vol);
2424
2425 LogFlowFuncLeaveRC(rc);
2426 return rc;
2427}
2428
2429static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2430{
2431 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2432 AssertPtr(pThis);
2433
2434 STAM_PROFILE_START(&pThis->StatTimer, a);
2435
2436 int rc = VINF_SUCCESS;
2437
2438 uint32_t cbInMax = 0;
2439 uint32_t cbOutMin = UINT32_MAX;
2440
2441 PHDADRIVER pDrv;
2442
2443 uint32_t cbIn, cbOut, cSamplesLive;
2444 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2445 {
2446 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2447 &cbIn, &cbOut, &cSamplesLive);
2448 if (RT_SUCCESS(rc))
2449 {
2450#ifdef DEBUG_TIMER
2451 LogFlowFunc(("\tLUN#%RU8: [1] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2452#endif
2453 if (cSamplesLive)
2454 {
2455 uint32_t cSamplesPlayed;
2456 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2457 if (RT_SUCCESS(rc2))
2458 LogFlowFunc(("LUN#%RU8: cSamplesLive=%RU32, cSamplesPlayed=%RU32\n",
2459 pDrv->uLUN, cSamplesLive, cSamplesPlayed));
2460
2461 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2462 &cbIn, &cbOut, &cSamplesLive);
2463#ifdef DEBUG_TIMER
2464 if (RT_SUCCESS(rc))
2465 LogFlowFunc(("\tLUN#%RU8: [2] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2466#endif
2467 }
2468
2469 cbInMax = RT_MAX(cbInMax, cbIn);
2470 cbOutMin = RT_MIN(cbOutMin, cbOut);
2471 }
2472 }
2473
2474#ifdef DEBUG_TIMER
2475 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
2476#endif
2477
2478 if (cbOutMin == UINT32_MAX)
2479 cbOutMin = 0;
2480
2481 /*
2482 * Playback.
2483 */
2484 if (cbOutMin)
2485 {
2486 Assert(cbOutMin != UINT32_MAX);
2487 hdaTransfer(pThis, PO_INDEX, cbOutMin); /** @todo Add rc! */
2488 }
2489
2490 /*
2491 * Recording.
2492 */
2493 if (cbInMax)
2494 hdaTransfer(pThis, PI_INDEX, cbInMax); /** @todo Add rc! */
2495
2496 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
2497
2498 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2499}
2500
2501static DECLCALLBACK(int) hdaTransfer(PHDASTATE pThis,
2502 ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2503{
2504 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2505
2506 LogFlowFunc(("pThis=%p, cbAvail=%RU32\n", pThis, cbAvail));
2507
2508 uint8_t u8Strm;
2509 PHDABDLEDESC pBdle;
2510
2511 switch (enmSrc)
2512 {
2513 case PI_INDEX:
2514 {
2515 u8Strm = 0;
2516 pBdle = &pThis->StInBdle;
2517 break;
2518 }
2519
2520#ifdef VBOX_WITH_HDA_MIC_IN
2521 case MC_INDEX:
2522 {
2523 u8Strm = 2;
2524 pBdle = &pThis->StMicBdle;
2525 break;
2526 }
2527#endif
2528 case PO_INDEX:
2529 {
2530 u8Strm = 4;
2531 pBdle = &pThis->StOutBdle;
2532 break;
2533 }
2534
2535 default:
2536 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
2537 return VERR_NOT_SUPPORTED;
2538 }
2539
2540 HDASTREAMTRANSFERDESC StreamDesc;
2541 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2542
2543 int rc = VINF_EOF;
2544 while (cbAvail)
2545 {
2546 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
2547 && cbAvail
2548 && StreamDesc.u64BaseDMA);
2549
2550 /* Fetch the Buffer Descriptor Entry (BDE). */
2551 if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
2552 hdaFetchBdle(pThis, pBdle, &StreamDesc);
2553
2554 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2555 Assert((StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib))); /* sanity */
2556 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
2557 Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
2558
2559 LogFunc(("CBL=%RU32, LPIB=%RU32\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
2560
2561 PAUDMIXSINK pSink;
2562 uint32_t cbWritten = 0;
2563 switch (enmSrc)
2564 {
2565 case PI_INDEX:
2566 pSink = pThis->pSinkLineIn;
2567 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2568 break;
2569 case PO_INDEX:
2570 rc = hdaWriteAudio(pThis, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2571 break;
2572#ifdef VBOX_WITH_HDA_MIC_IN
2573 case MC_INDEX:
2574 pSink = pThis->pSinkMicIn;
2575 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2576 break;
2577#endif
2578 default:
2579 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
2580 rc = VERR_NOT_SUPPORTED;
2581 break;
2582 }
2583 Assert(cbWritten <= StreamDesc.u32Fifos + 1);
2584 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2585
2586 /* Process end of buffer condition. */
2587 hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cbWritten);
2588
2589 if (!hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc))
2590 break;
2591
2592 if ( RT_FAILURE(rc)
2593 || rc == VINF_EOF) /* All data processed? */
2594 {
2595 break;
2596 }
2597 }
2598
2599 return rc;
2600}
2601#endif /* IN_RING3 */
2602
2603/* MMIO callbacks */
2604
2605/**
2606 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
2607 *
2608 * @note During implementation, we discovered so-called "forgotten" or "hole"
2609 * registers whose description is not listed in the RPM, datasheet, or
2610 * spec.
2611 */
2612PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2613{
2614 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2615 int rc;
2616
2617 /*
2618 * Look up and log.
2619 */
2620 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2621 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
2622#ifdef LOG_ENABLED
2623 unsigned const cbLog = cb;
2624 uint32_t offRegLog = offReg;
2625#endif
2626
2627 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
2628#define NEW_READ_CODE
2629#ifdef NEW_READ_CODE
2630 Assert(cb == 4); Assert((offReg & 3) == 0);
2631
2632 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2633 LogFunc(("access to registers except GCTL is blocked while reset\n"));
2634
2635 if (idxRegDsc == -1)
2636 LogRel(("Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
2637
2638 if (idxRegDsc != -1)
2639 {
2640 /* ASSUMES gapless DWORD at end of map. */
2641 if (g_aHdaRegMap[idxRegDsc].size == 4)
2642 {
2643 /*
2644 * Straight forward DWORD access.
2645 */
2646 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
2647 LogFunc(("read %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
2648 }
2649 else
2650 {
2651 /*
2652 * Multi register read (unless there are trailing gaps).
2653 * ASSUMES that only DWORD reads have sideeffects.
2654 */
2655 uint32_t u32Value = 0;
2656 unsigned cbLeft = 4;
2657 do
2658 {
2659 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
2660 uint32_t u32Tmp = 0;
2661
2662 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
2663 LogFunc(("read %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
2664 if (rc != VINF_SUCCESS)
2665 break;
2666 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
2667
2668 cbLeft -= cbReg;
2669 offReg += cbReg;
2670 idxRegDsc++;
2671 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
2672
2673 if (rc == VINF_SUCCESS)
2674 *(uint32_t *)pv = u32Value;
2675 else
2676 Assert(!IOM_SUCCESS(rc));
2677 }
2678 }
2679 else
2680 {
2681 rc = VINF_IOM_MMIO_UNUSED_FF;
2682 LogFunc(("hole at %x is accessed for read\n", offReg));
2683 }
2684#else
2685 if (idxRegDsc != -1)
2686 {
2687 /** @todo r=bird: Accesses crossing register boundraries aren't handled
2688 * right from what I can tell? If they are, please explain
2689 * what the rules are. */
2690 uint32_t mask = 0;
2691 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2692 uint32_t u32Value = 0;
2693 switch(cb)
2694 {
2695 case 1: mask = 0x000000ff; break;
2696 case 2: mask = 0x0000ffff; break;
2697 case 4:
2698 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2699 case 8:
2700 mask = 0xffffffff;
2701 cb = 4;
2702 break;
2703 }
2704#if 0
2705 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
2706 */
2707 //Assert((cb <= g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset)));
2708 if (cb > g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset))
2709 {
2710 int off = cb - (g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset));
2711 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2712 if (RT_FAILURE(rc))
2713 AssertRCReturn (rc, rc);
2714 }
2715 //Assert(((offReg - g_aHdaRegMap[idxRegDsc].offset) == 0));
2716#endif
2717 mask <<= shift;
2718 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Value);
2719 *(uint32_t *)pv |= (u32Value & mask);
2720 LogFunc(("read %s[%x/%x]\n", g_aHdaRegMap[idxRegDsc].abbrev, u32Value, *(uint32_t *)pv));
2721 }
2722 else
2723 {
2724 *(uint32_t *)pv = 0xFF;
2725 LogFunc(("hole at %x is accessed for read\n", offReg));
2726 rc = VINF_SUCCESS;
2727 }
2728#endif
2729
2730 /*
2731 * Log the outcome.
2732 */
2733#ifdef LOG_ENABLED
2734 if (cbLog == 4)
2735 LogFunc(("@%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
2736 else if (cbLog == 2)
2737 LogFunc(("@%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
2738 else if (cbLog == 1)
2739 LogFunc(("@%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
2740#endif
2741 return rc;
2742}
2743
2744
2745DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
2746{
2747 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2748 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
2749
2750 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2751#ifdef LOG_ENABLED
2752 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
2753#endif
2754 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
2755 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
2756 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
2757 return rc;
2758}
2759
2760
2761/**
2762 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
2763 */
2764PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2765{
2766 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2767 int rc;
2768
2769 /*
2770 * The behavior of accesses that aren't aligned on natural boundraries is
2771 * undefined. Just reject them outright.
2772 */
2773 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
2774 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
2775 if (GCPhysAddr & (cb - 1))
2776 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
2777
2778 /*
2779 * Look up and log the access.
2780 */
2781 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2782 int idxRegDsc = hdaRegLookup(pThis, offReg);
2783 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
2784 uint64_t u64Value;
2785 if (cb == 4) u64Value = *(uint32_t const *)pv;
2786 else if (cb == 2) u64Value = *(uint16_t const *)pv;
2787 else if (cb == 1) u64Value = *(uint8_t const *)pv;
2788 else if (cb == 8) u64Value = *(uint64_t const *)pv;
2789 else
2790 {
2791 u64Value = 0; /* shut up gcc. */
2792 AssertReleaseMsgFailed(("%d\n", cb));
2793 }
2794
2795#ifdef LOG_ENABLED
2796 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
2797 uint32_t const offRegLog = offReg;
2798 int const idxRegLog = idxRegMem;
2799 if (idxRegDsc == -1)
2800 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
2801 else if (cb == 4)
2802 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2803 else if (cb == 2)
2804 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2805 else if (cb == 1)
2806 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2807 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
2808 LogFunc(("size=%d != cb=%d!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
2809#endif
2810
2811#define NEW_WRITE_CODE
2812#ifdef NEW_WRITE_CODE
2813 /*
2814 * Try for a direct hit first.
2815 */
2816 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
2817 {
2818 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
2819 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2820 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2821 }
2822 /*
2823 * Partial or multiple register access, loop thru the requested memory.
2824 */
2825 else
2826 {
2827 /* If it's an access beyond the start of the register, shift the input
2828 value and fill in missing bits. Natural alignment rules means we
2829 will only see 1 or 2 byte accesses of this kind, so no risk of
2830 shifting out input values. */
2831 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
2832 {
2833 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
2834 offReg -= cbBefore;
2835 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2836 u64Value <<= cbBefore * 8;
2837 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
2838 LogFunc(("Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
2839 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
2840 }
2841
2842 /* Loop thru the write area, it may cover multiple registers. */
2843 rc = VINF_SUCCESS;
2844 for (;;)
2845 {
2846 uint32_t cbReg;
2847 if (idxRegDsc != -1)
2848 {
2849 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2850 cbReg = g_aHdaRegMap[idxRegDsc].size;
2851 if (cb < cbReg)
2852 {
2853 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
2854 LogFunc(("Supplying missing bits (%#x): %#llx -> %#llx ...\n",
2855 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
2856 }
2857 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
2858 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
2859 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldVal,
2860 pThis->au32Regs[idxRegMem]));
2861 }
2862 else
2863 {
2864 LogRel(("HDA: Invalid write access @0x%x!\n", offReg));
2865 cbReg = 1;
2866 }
2867 if (rc != VINF_SUCCESS)
2868 break;
2869 if (cbReg >= cb)
2870 break;
2871
2872 /* advance */
2873 offReg += cbReg;
2874 cb -= cbReg;
2875 u64Value >>= cbReg * 8;
2876 if (idxRegDsc == -1)
2877 idxRegDsc = hdaRegLookup(pThis, offReg);
2878 else
2879 {
2880 idxRegDsc++;
2881 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
2882 || g_aHdaRegMap[idxRegDsc].offset != offReg)
2883 idxRegDsc = -1;
2884 }
2885 }
2886 }
2887#else
2888 if (idxRegDsc != -1)
2889 {
2890 /** @todo r=bird: This looks like code for handling unaligned register
2891 * accesses. If it isn't, then add a comment explaining what you're
2892 * trying to do here. OTOH, if it is then it has the following
2893 * issues:
2894 * -# You're calculating the wrong new value for the register.
2895 * -# You're not handling cross register accesses. Imagine a
2896 * 4-byte write starting at CORBCTL, or a 8-byte write.
2897 *
2898 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
2899 * nobody seems to be using it and it just adds complexity when reading
2900 * the code.
2901 *
2902 */
2903 uint32_t u32CurValue = pThis->au32Regs[idxRegMem];
2904 uint32_t u32NewValue;
2905 uint32_t mask;
2906 switch (cb)
2907 {
2908 case 1:
2909 u32NewValue = *(uint8_t const *)pv;
2910 mask = 0xff;
2911 break;
2912 case 2:
2913 u32NewValue = *(uint16_t const *)pv;
2914 mask = 0xffff;
2915 break;
2916 case 4:
2917 case 8:
2918 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2919 u32NewValue = *(uint32_t const *)pv;
2920 mask = 0xffffffff;
2921 cb = 4;
2922 break;
2923 default:
2924 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
2925 }
2926 /* cross-register access, see corresponding comment in hdaMMIORead */
2927 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2928 mask <<= shift;
2929 u32NewValue <<= shift;
2930 u32NewValue &= mask;
2931 u32NewValue |= (u32CurValue & ~mask);
2932
2933 rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32NewValue);
2934 LogFunc(("write %s:(%x) %x => %x\n", g_aHdaRegMap[idxRegDsc].abbrev, u32NewValue,
2935 u32CurValue, pThis->au32Regs[idxRegMem]));
2936 }
2937 else
2938 rc = VINF_SUCCESS;
2939
2940 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2941 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2942#endif
2943 return rc;
2944}
2945
2946
2947/* PCI callback. */
2948
2949#ifdef IN_RING3
2950/**
2951 * @callback_method_impl{FNPCIIOREGIONMAP}
2952 */
2953static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
2954 PCIADDRESSSPACE enmType)
2955{
2956 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2957 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
2958 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
2959 int rc;
2960
2961 /*
2962 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
2963 *
2964 * Let IOM talk DWORDs when reading, saves a lot of complications. On
2965 * writing though, we have to do it all ourselves because of sideeffects.
2966 */
2967 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2968 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2969#ifdef NEW_READ_CODE
2970 IOMMMIO_FLAGS_READ_DWORD |
2971#else
2972 IOMMMIO_FLAGS_READ_PASSTHRU |
2973#endif
2974 IOMMMIO_FLAGS_WRITE_PASSTHRU,
2975 hdaMMIOWrite, hdaMMIORead, "HDA");
2976
2977 if (RT_FAILURE(rc))
2978 return rc;
2979
2980 if (pThis->fR0Enabled)
2981 {
2982 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
2983 "hdaMMIOWrite", "hdaMMIORead");
2984 if (RT_FAILURE(rc))
2985 return rc;
2986 }
2987
2988 if (pThis->fRCEnabled)
2989 {
2990 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
2991 "hdaMMIOWrite", "hdaMMIORead");
2992 if (RT_FAILURE(rc))
2993 return rc;
2994 }
2995
2996 pThis->MMIOBaseAddr = GCPhysAddress;
2997 return VINF_SUCCESS;
2998}
2999
3000
3001/* Saved state callbacks. */
3002
3003/**
3004 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3005 */
3006static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3007{
3008 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3009
3010 /* Save Codec nodes states */
3011 hdaCodecSaveState(pThis->pCodec, pSSM);
3012
3013 /* Save MMIO registers */
3014 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3015 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3016 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3017
3018 /* Save HDA dma counters */
3019 SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3020 SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3021 SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3022 return VINF_SUCCESS;
3023}
3024
3025
3026/**
3027 * @callback_method_impl{FNSSMDEVLOADEXEC}
3028 */
3029static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3030{
3031 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3032
3033 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3034
3035 /*
3036 * Load Codec nodes states.
3037 */
3038 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3039 if (RT_FAILURE(rc))
3040 return rc;
3041
3042 /*
3043 * Load MMIO registers.
3044 */
3045 uint32_t cRegs;
3046 switch (uVersion)
3047 {
3048 case HDA_SSM_VERSION_1:
3049 /* Starting with r71199, we would save 112 instead of 113
3050 registers due to some code cleanups. This only affected trunk
3051 builds in the 4.1 development period. */
3052 cRegs = 113;
3053 if (SSMR3HandleRevision(pSSM) >= 71199)
3054 {
3055 uint32_t uVer = SSMR3HandleVersion(pSSM);
3056 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3057 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3058 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3059 cRegs = 112;
3060 }
3061 break;
3062
3063 case HDA_SSM_VERSION_2:
3064 case HDA_SSM_VERSION_3:
3065 cRegs = 112;
3066 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3067 break;
3068
3069 case HDA_SSM_VERSION:
3070 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3071 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3072 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3073 break;
3074
3075 default:
3076 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3077 }
3078
3079 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3080 {
3081 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3082 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3083 }
3084 else
3085 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3086
3087 /*
3088 * Load HDA DMA counters.
3089 */
3090 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
3091 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
3092 rc = SSMR3GetStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), fFlags, paFields, NULL);
3093 AssertRCReturn(rc, rc);
3094 rc = SSMR3GetStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), fFlags, paFields, NULL);
3095 AssertRCReturn(rc, rc);
3096 rc = SSMR3GetStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), fFlags, paFields, NULL);
3097 AssertRCReturn(rc, rc);
3098
3099 /*
3100 * Update stuff after the state changes.
3101 */
3102 bool fEnableIn = RT_BOOL(SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3103#ifdef VBOX_WITH_HDA_MIC_IN
3104 bool fEnableMicIn = RT_BOOL(SDCTL(pThis, 2) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3105#else
3106 bool fEnableMicIn = fEnableIn; /* Mic In == Line In */
3107#endif
3108 bool fEnableOut = RT_BOOL(SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3109
3110 PHDADRIVER pDrv;
3111 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3112 {
3113 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, fEnableIn);
3114 if (RT_FAILURE(rc))
3115 break;
3116 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, fEnableMicIn);
3117 if (RT_FAILURE(rc))
3118 break;
3119 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, fEnableOut);
3120 if (RT_FAILURE(rc))
3121 break;
3122 }
3123
3124 if (RT_SUCCESS(rc))
3125 {
3126 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3127 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3128 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3129 }
3130
3131 LogFlowFuncLeaveRC(rc);
3132 return rc;
3133}
3134
3135
3136/* Debug and log type formatters. */
3137
3138/**
3139 * @callback_method_impl{FNRTSTRFORMATTYPE}
3140 */
3141static DECLCALLBACK(size_t)
3142hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3143 const char *pszType, void const *pvValue,
3144 int cchWidth, int cchPrecision, unsigned fFlags,
3145 void *pvUser)
3146{
3147 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
3148 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3149 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
3150 sdCtl,
3151 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> HDA_SDCTL_NUM_SHIFT,
3152 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
3153 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3154 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3155 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3156 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3157 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3158 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3159}
3160
3161/**
3162 * @callback_method_impl{FNRTSTRFORMATTYPE}
3163 */
3164static DECLCALLBACK(size_t)
3165hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3166 const char *pszType, void const *pvValue,
3167 int cchWidth, int cchPrecision, unsigned fFlags,
3168 void *pvUser)
3169{
3170 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3171 uint32_t cb;
3172 switch (uSdFifos)
3173 {
3174 case HDA_SDONFIFO_16B: cb = 16; break;
3175 case HDA_SDONFIFO_32B: cb = 32; break;
3176 case HDA_SDONFIFO_64B: cb = 64; break;
3177 case HDA_SDONFIFO_128B: cb = 128; break;
3178 case HDA_SDONFIFO_192B: cb = 192; break;
3179 case HDA_SDONFIFO_256B: cb = 256; break;
3180 case HDA_SDINFIFO_120B: cb = 120; break;
3181 case HDA_SDINFIFO_160B: cb = 160; break;
3182 default: cb = 0; break;
3183 }
3184 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
3185}
3186
3187/**
3188 * @callback_method_impl{FNRTSTRFORMATTYPE}
3189 */
3190static DECLCALLBACK(size_t)
3191hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3192 const char *pszType, void const *pvValue,
3193 int cchWidth, int cchPrecision, unsigned fFlags,
3194 void *pvUser)
3195{
3196 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3197 uint32_t cb;
3198 switch (uSdFifos)
3199 {
3200 case HDA_SDFIFOW_8B: cb = 8; break;
3201 case HDA_SDFIFOW_16B: cb = 16; break;
3202 case HDA_SDFIFOW_32B: cb = 32; break;
3203 default: cb = 0; break;
3204 }
3205 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
3206}
3207
3208/**
3209 * @callback_method_impl{FNRTSTRFORMATTYPE}
3210 */
3211static DECLCALLBACK(size_t)
3212hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3213 const char *pszType, void const *pvValue,
3214 int cchWidth, int cchPrecision, unsigned fFlags,
3215 void *pvUser)
3216{
3217 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3218 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3219 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3220 uSdSts,
3221 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3222 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3223 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3224 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3225}
3226
3227
3228static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3229{
3230 int iReg = 0;
3231 for (; iReg < HDA_NREGS; ++iReg)
3232 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3233 return iReg;
3234 return -1;
3235}
3236
3237
3238static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
3239{
3240 Assert( pThis
3241 && iHdaIndex >= 0
3242 && iHdaIndex < HDA_NREGS);
3243 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
3244}
3245
3246
3247/**
3248 * @callback_method_impl{FNDBGFHANDLERDEV}
3249 */
3250static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3251{
3252 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3253 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
3254 if (iHdaRegisterIndex != -1)
3255 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3256 else
3257 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
3258 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3259}
3260
3261
3262static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
3263{
3264 Assert( pThis
3265 && iHdaStrmIndex >= 0
3266 && iHdaStrmIndex < 7);
3267 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
3268 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
3269 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
3270 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
3271 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
3272}
3273
3274
3275static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
3276{
3277 /* todo: add args parsing */
3278 return -1;
3279}
3280
3281
3282/**
3283 * @callback_method_impl{FNDBGFHANDLERDEV}
3284 */
3285static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3286{
3287 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3288 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
3289 if (iHdaStrmIndex != -1)
3290 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3291 else
3292 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
3293 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3294}
3295
3296
3297/**
3298 * @callback_method_impl{FNDBGFHANDLERDEV}
3299 */
3300static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3301{
3302 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3303
3304 if (pThis->pCodec->pfnDbgListNodes)
3305 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
3306 else
3307 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3308}
3309
3310
3311/**
3312 * @callback_method_impl{FNDBGFHANDLERDEV}
3313 */
3314static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3315{
3316 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3317
3318 if (pThis->pCodec->pfnDbgSelector)
3319 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
3320 else
3321 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3322}
3323
3324
3325/**
3326 * @callback_method_impl{FNDBGFHANDLERDEV}
3327 */
3328static DECLCALLBACK(void) hdaInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3329{
3330 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3331
3332 if (pThis->pMixer)
3333 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
3334 else
3335 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
3336}
3337
3338
3339/* PDMIBASE */
3340
3341/**
3342 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3343 */
3344static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3345{
3346 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
3347 Assert(&pThis->IBase == pInterface);
3348
3349 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3350 return NULL;
3351}
3352
3353
3354/* PDMDEVREG */
3355
3356/**
3357 * Reset notification.
3358 *
3359 * @returns VBox status.
3360 * @param pDevIns The device instance data.
3361 *
3362 * @remark The original sources didn't install a reset handler, but it seems to
3363 * make sense to me so we'll do it.
3364 */
3365static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
3366{
3367 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3368 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
3369 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3370 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3371 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3372 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3373 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
3374 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
3375 HDA_REG(pThis, CORBRP) = 0x0;
3376 HDA_REG(pThis, RIRBWP) = 0x0;
3377
3378 LogFunc(("Resetting ...\n"));
3379
3380 /* Stop any audio currently playing. */
3381 PHDADRIVER pDrv;
3382 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3383 {
3384 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
3385 /* Ignore rc. */
3386 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
3387 /* Ditto. */
3388 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
3389 /* Ditto. */
3390 }
3391
3392 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
3393
3394 if (pThis->pu32CorbBuf)
3395 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3396 else
3397 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3398
3399 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
3400 if (pThis->pu64RirbBuf)
3401 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3402 else
3403 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3404
3405 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
3406
3407 HDABDLEDESC StEmptyBdle;
3408 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
3409 {
3410 HDASTREAMTRANSFERDESC StreamDesc;
3411 PHDABDLEDESC pBdle = NULL;
3412 if (u8Strm == 0)
3413 pBdle = &pThis->StInBdle;
3414# ifdef VBOX_WITH_HDA_MIC_IN
3415 else if (u8Strm == 2)
3416 pBdle = &pThis->StMicBdle;
3417# endif
3418 else if(u8Strm == 4)
3419 pBdle = &pThis->StOutBdle;
3420 else
3421 {
3422 RT_ZERO(StEmptyBdle);
3423 pBdle = &StEmptyBdle;
3424 }
3425 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
3426 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
3427 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
3428 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
3429 }
3430
3431 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3432 HDA_REG(pThis, STATESTS) = 0x1;
3433
3434 LogRel(("HDA: Reset\n"));
3435}
3436
3437/**
3438 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3439 */
3440static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
3441{
3442 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3443
3444 PHDADRIVER pDrv;
3445 while (!RTListIsEmpty(&pThis->lstDrv))
3446 {
3447 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
3448
3449 RTListNodeRemove(&pDrv->Node);
3450 RTMemFree(pDrv);
3451 }
3452
3453 if (pThis->pMixer)
3454 {
3455 AudioMixerDestroy(pThis->pMixer);
3456 pThis->pMixer = NULL;
3457 }
3458
3459 if (pThis->pCodec)
3460 {
3461 int rc = hdaCodecDestruct(pThis->pCodec);
3462 AssertRC(rc);
3463
3464 RTMemFree(pThis->pCodec);
3465 pThis->pCodec = NULL;
3466 }
3467
3468 RTMemFree(pThis->pu32CorbBuf);
3469 pThis->pu32CorbBuf = NULL;
3470
3471 RTMemFree(pThis->pu64RirbBuf);
3472 pThis->pu64RirbBuf = NULL;
3473
3474 return VINF_SUCCESS;
3475}
3476
3477/**
3478 * Attach command.
3479 *
3480 * This is called to let the device attach to a driver for a specified LUN
3481 * during runtime. This is not called during VM construction, the device
3482 * constructor have to attach to all the available drivers.
3483 *
3484 * @returns VBox status code.
3485 * @param pDevIns The device instance.
3486 * @param uLUN The logical unit which is being detached.
3487 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3488 */
3489static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
3490{
3491 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3492
3493 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3494 ("HDA device does not support hotplugging\n"),
3495 VERR_INVALID_PARAMETER);
3496
3497 /*
3498 * Attach driver.
3499 */
3500 char *pszDesc = NULL;
3501 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
3502 AssertMsgReturn(pszDesc,
3503 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
3504 VERR_NO_MEMORY);
3505
3506 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
3507 &pThis->IBase, &pThis->pDrvBase, pszDesc);
3508 if (RT_SUCCESS(rc))
3509 {
3510 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
3511 if (pDrv)
3512 {
3513 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
3514 AssertMsg(pDrv->pConnector != NULL,
3515 ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n",
3516 uLUN, rc));
3517 pDrv->pHDAState = pThis;
3518 pDrv->uLUN = uLUN;
3519
3520 /*
3521 * For now we always set the driver at LUN 0 as our primary
3522 * host backend. This might change in the future.
3523 */
3524 if (pDrv->uLUN == 0)
3525 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
3526
3527 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
3528
3529 /* Attach to driver list. */
3530 RTListAppend(&pThis->lstDrv, &pDrv->Node);
3531 }
3532 else
3533 rc = VERR_NO_MEMORY;
3534 }
3535 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
3536 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
3537 {
3538 LogFunc(("No attached driver for LUN #%u\n", uLUN));
3539 }
3540 else if (RT_FAILURE(rc))
3541 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
3542 uLUN, pszDesc, rc));
3543
3544 RTStrFree(pszDesc);
3545
3546 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
3547 return rc;
3548}
3549
3550static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3551{
3552 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
3553
3554 LogFlowFuncEnter();
3555}
3556
3557/**
3558 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3559 */
3560static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
3561{
3562 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3563 Assert(iInstance == 0);
3564 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3565
3566 /*
3567 * Validations.
3568 */
3569 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
3570 "RCEnabled\0"))
3571 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3572 N_ ("Invalid configuration for the Intel HDA device"));
3573
3574 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
3575 if (RT_FAILURE(rc))
3576 return PDMDEV_SET_ERROR(pDevIns, rc,
3577 N_("HDA configuration error: failed to read RCEnabled as boolean"));
3578 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
3579 if (RT_FAILURE(rc))
3580 return PDMDEV_SET_ERROR(pDevIns, rc,
3581 N_("HDA configuration error: failed to read R0Enabled as boolean"));
3582
3583 /*
3584 * Initialize data (most of it anyway).
3585 */
3586 pThis->pDevInsR3 = pDevIns;
3587 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3588 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3589 /* IBase */
3590 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
3591
3592 /* PCI Device */
3593 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
3594 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
3595
3596 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
3597 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
3598 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
3599 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
3600 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
3601 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
3602 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
3603 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
3604 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
3605 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
3606 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
3607
3608#if defined(HDA_AS_PCI_EXPRESS)
3609 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
3610#elif defined(VBOX_WITH_MSI_DEVICES)
3611 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
3612#else
3613 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
3614#endif
3615
3616 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
3617 /// of these values needs to be properly documented!
3618 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
3619 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
3620
3621 /* Power Management */
3622 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
3623 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
3624 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
3625
3626#ifdef HDA_AS_PCI_EXPRESS
3627 /* PCI Express */
3628 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
3629 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
3630 /* Device flags */
3631 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
3632 /* version */ 0x1 |
3633 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
3634 /* MSI */ (100) << 9 );
3635 /* Device capabilities */
3636 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
3637 /* Device control */
3638 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
3639 /* Device status */
3640 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
3641 /* Link caps */
3642 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
3643 /* Link control */
3644 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
3645 /* Link status */
3646 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
3647 /* Slot capabilities */
3648 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
3649 /* Slot control */
3650 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
3651 /* Slot status */
3652 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
3653 /* Root control */
3654 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
3655 /* Root capabilities */
3656 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
3657 /* Root status */
3658 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
3659 /* Device capabilities 2 */
3660 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
3661 /* Device control 2 */
3662 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
3663 /* Link control 2 */
3664 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
3665 /* Slot control 2 */
3666 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
3667#endif
3668
3669 /*
3670 * Register the PCI device.
3671 */
3672 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
3673 if (RT_FAILURE(rc))
3674 return rc;
3675
3676 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
3677 if (RT_FAILURE(rc))
3678 return rc;
3679
3680#ifdef VBOX_WITH_MSI_DEVICES
3681 PDMMSIREG MsiReg;
3682 RT_ZERO(MsiReg);
3683 MsiReg.cMsiVectors = 1;
3684 MsiReg.iMsiCapOffset = 0x60;
3685 MsiReg.iMsiNextOffset = 0x50;
3686 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3687 if (RT_FAILURE(rc))
3688 {
3689 /* That's OK, we can work without MSI */
3690 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
3691 }
3692#endif
3693
3694 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
3695 if (RT_FAILURE(rc))
3696 return rc;
3697
3698 RTListInit(&pThis->lstDrv);
3699
3700 uint8_t uLUN;
3701 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
3702 {
3703 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
3704 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
3705 if (RT_FAILURE(rc))
3706 {
3707 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3708 rc = VINF_SUCCESS;
3709
3710 break;
3711 }
3712
3713 uLUN++;
3714 }
3715
3716 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3717
3718 if (RT_SUCCESS(rc))
3719 {
3720 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
3721 if (RT_SUCCESS(rc))
3722 {
3723 /* Set a default audio format for our mixer. */
3724 PDMAUDIOSTREAMCFG streamCfg;
3725 streamCfg.uHz = 44100;
3726 streamCfg.cChannels = 2;
3727 streamCfg.enmFormat = AUD_FMT_S16;
3728 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
3729
3730 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
3731 AssertRC(rc);
3732
3733 /* Add all required audio sinks. */
3734 rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output",
3735 AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
3736 AssertRC(rc);
3737
3738 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In",
3739 AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
3740 AssertRC(rc);
3741
3742 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
3743 AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
3744 AssertRC(rc);
3745
3746 /* There is no master volume control. Set the master to max. */
3747 PDMAUDIOVOLUME vol = { false, 255, 255 };
3748 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
3749 AssertRC(rc);
3750 }
3751 }
3752
3753 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3754
3755 if (RT_SUCCESS(rc))
3756 {
3757 /* Construct codec. */
3758 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
3759 if (!pThis->pCodec)
3760 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
3761
3762 /* Audio driver callbacks for multiplexing. */
3763 pThis->pCodec->pfnCloseIn = hdaCloseIn;
3764 pThis->pCodec->pfnCloseOut = hdaCloseOut;
3765 pThis->pCodec->pfnOpenIn = hdaOpenIn;
3766 pThis->pCodec->pfnOpenOut = hdaOpenOut;
3767 pThis->pCodec->pfnReset = hdaCodecReset;
3768 pThis->pCodec->pfnSetVolume = hdaSetVolume;
3769
3770 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
3771
3772 /* Construct the codec. */
3773 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
3774 if (RT_FAILURE(rc))
3775 AssertRCReturn(rc, rc);
3776
3777 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
3778 verb F20 should provide device/codec recognition. */
3779 Assert(pThis->pCodec->u16VendorId);
3780 Assert(pThis->pCodec->u16DeviceId);
3781 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
3782 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
3783 }
3784
3785 if (RT_SUCCESS(rc))
3786 {
3787 hdaReset(pDevIns);
3788
3789 /*
3790 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
3791 * hdaReset shouldn't affects these registers.
3792 */
3793 HDA_REG(pThis, WAKEEN) = 0x0;
3794 HDA_REG(pThis, STATESTS) = 0x0;
3795
3796 /*
3797 * Debug and string formatter types.
3798 */
3799 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
3800 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
3801 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
3802 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
3803 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaInfoMixer);
3804
3805 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
3806 AssertRC(rc);
3807 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
3808 AssertRC(rc);
3809 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
3810 AssertRC(rc);
3811 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
3812 AssertRC(rc);
3813 #if 0
3814 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
3815 AssertRC(rc);
3816 #endif
3817
3818 /*
3819 * Some debug assertions.
3820 */
3821 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
3822 {
3823 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
3824 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
3825
3826 /* binary search order. */
3827 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
3828 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3829 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3830
3831 /* alignment. */
3832 AssertReleaseMsg( pReg->size == 1
3833 || (pReg->size == 2 && (pReg->offset & 1) == 0)
3834 || (pReg->size == 3 && (pReg->offset & 3) == 0)
3835 || (pReg->size == 4 && (pReg->offset & 3) == 0),
3836 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3837
3838 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
3839 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
3840 if (pReg->offset & 3)
3841 {
3842 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
3843 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3844 if (pPrevReg)
3845 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
3846 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3847 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
3848 }
3849 #if 0
3850 if ((pReg->offset + pReg->size) & 3)
3851 {
3852 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3853 if (pNextReg)
3854 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
3855 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3856 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3857 }
3858 #endif
3859
3860 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
3861 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
3862 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3863 }
3864 }
3865
3866 if (RT_SUCCESS(rc))
3867 {
3868 /* Start the emulation timer. */
3869 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
3870 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
3871 AssertRCReturn(rc, rc);
3872
3873 if (RT_SUCCESS(rc))
3874 {
3875 /** @todo Investigate why sounds is getting corrupted if the "ticks" value is too
3876 * low, e.g. "PDMDevHlpTMTimeVirtGetFreq / 200". */
3877 pThis->uTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 500; /** @todo Make this configurable! */
3878 if (pThis->uTicks < 100)
3879 pThis->uTicks = 100;
3880 LogFunc(("Timer ticks=%RU64\n", pThis->uTicks));
3881
3882 /* Fire off timer. */
3883 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
3884 }
3885 }
3886
3887# ifdef VBOX_WITH_STATISTICS
3888 if (RT_SUCCESS(rc))
3889 {
3890 /*
3891 * Register statistics.
3892 */
3893 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
3894 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
3895 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
3896 }
3897# endif
3898
3899 LogFlowFuncLeaveRC(rc);
3900 return rc;
3901}
3902
3903/**
3904 * The device registration structure.
3905 */
3906const PDMDEVREG g_DeviceICH6_HDA =
3907{
3908 /* u32Version */
3909 PDM_DEVREG_VERSION,
3910 /* szName */
3911 "hda",
3912 /* szRCMod */
3913 "VBoxDDRC.rc",
3914 /* szR0Mod */
3915 "VBoxDDR0.r0",
3916 /* pszDescription */
3917 "Intel HD Audio Controller",
3918 /* fFlags */
3919 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
3920 /* fClass */
3921 PDM_DEVREG_CLASS_AUDIO,
3922 /* cMaxInstances */
3923 1,
3924 /* cbInstance */
3925 sizeof(HDASTATE),
3926 /* pfnConstruct */
3927 hdaConstruct,
3928 /* pfnDestruct */
3929 hdaDestruct,
3930 /* pfnRelocate */
3931 NULL,
3932 /* pfnMemSetup */
3933 NULL,
3934 /* pfnPowerOn */
3935 NULL,
3936 /* pfnReset */
3937 hdaReset,
3938 /* pfnSuspend */
3939 NULL,
3940 /* pfnResume */
3941 NULL,
3942 /* pfnAttach */
3943 NULL,
3944 /* pfnDetach */
3945 NULL,
3946 /* pfnQueryInterface. */
3947 NULL,
3948 /* pfnInitComplete */
3949 NULL,
3950 /* pfnPowerOff */
3951 NULL,
3952 /* pfnSoftReset */
3953 NULL,
3954 /* u32VersionEnd */
3955 PDM_DEVREG_VERSION
3956};
3957
3958#endif /* IN_RING3 */
3959#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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