VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 58901

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1/* $Id: DevIchHda.cpp 58901 2015-11-27 13:11:20Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2015 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/list.h>
36#ifdef IN_RING3
37# include <iprt/mem.h>
38# include <iprt/string.h>
39# include <iprt/uuid.h>
40#endif
41
42#include "VBoxDD.h"
43
44#include "AudioMixer.h"
45#include "DevIchHdaCodec.h"
46
47
48/*********************************************************************************************************************************
49* Defined Constants And Macros *
50*********************************************************************************************************************************/
51//#define HDA_AS_PCI_EXPRESS
52#define VBOX_WITH_INTEL_HDA
53
54#if (defined(DEBUG) && defined(DEBUG_andy))
55/* Enables experimental support for separate mic-in handling.
56 Do not enable this yet for regular builds, as this needs more testing first! */
57# define VBOX_WITH_HDA_MIC_IN
58#endif
59
60#if defined(VBOX_WITH_HP_HDA)
61/* HP Pavilion dv4t-1300 */
62# define HDA_PCI_VENDOR_ID 0x103c
63# define HDA_PCI_DEVICE_ID 0x30f7
64#elif defined(VBOX_WITH_INTEL_HDA)
65/* Intel HDA controller */
66# define HDA_PCI_VENDOR_ID 0x8086
67# define HDA_PCI_DEVICE_ID 0x2668
68#elif defined(VBOX_WITH_NVIDIA_HDA)
69/* nVidia HDA controller */
70# define HDA_PCI_VENDOR_ID 0x10de
71# define HDA_PCI_DEVICE_ID 0x0ac0
72#else
73# error "Please specify your HDA device vendor/device IDs"
74#endif
75
76/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
77 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
78 * is read only except for bit 15 like the HDA spec states.
79 *
80 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
81 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
82#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
83
84#define HDA_NREGS 114
85#define HDA_NREGS_SAVED 112
86
87/**
88 * NB: Register values stored in memory (au32Regs[]) are indexed through
89 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
90 * register descriptors in g_aHdaRegMap[] are indexed through the
91 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
92 *
93 * The au32Regs[] layout is kept unchanged for saved state
94 * compatibility. */
95
96/* Registers */
97#define HDA_REG_IND_NAME(x) HDA_REG_##x
98#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
99#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
100#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
101#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
102#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
103#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
104#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
105
106
107#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
108#define HDA_RMX_GCAP 0
109/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
110 * oss (15:12) - number of output streams supported
111 * iss (11:8) - number of input streams supported
112 * bss (7:3) - number of bidirectional streams supported
113 * bds (2:1) - number of serial data out signals supported
114 * b64sup (0) - 64 bit addressing supported.
115 */
116#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
117 ( (((oss) & 0xF) << 12) \
118 | (((iss) & 0xF) << 8) \
119 | (((bss) & 0x1F) << 3) \
120 | (((bds) & 0x3) << 2) \
121 | ((b64sup) & 1))
122
123#define HDA_REG_VMIN 1 /* 0x02 */
124#define HDA_RMX_VMIN 1
125
126#define HDA_REG_VMAJ 2 /* 0x03 */
127#define HDA_RMX_VMAJ 2
128
129#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
130#define HDA_RMX_OUTPAY 3
131
132#define HDA_REG_INPAY 4 /* 0x06-0x07 */
133#define HDA_RMX_INPAY 4
134
135#define HDA_REG_GCTL 5 /* 0x08-0x0B */
136#define HDA_RMX_GCTL 5
137#define HDA_GCTL_RST_SHIFT 0
138#define HDA_GCTL_FSH_SHIFT 1
139#define HDA_GCTL_UR_SHIFT 8
140
141#define HDA_REG_WAKEEN 6 /* 0x0C */
142#define HDA_RMX_WAKEEN 6
143
144#define HDA_REG_STATESTS 7 /* 0x0E */
145#define HDA_RMX_STATESTS 7
146#define HDA_STATES_SCSF 0x7
147
148#define HDA_REG_GSTS 8 /* 0x10-0x11*/
149#define HDA_RMX_GSTS 8
150#define HDA_GSTS_FSH_SHIFT 1
151
152#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
153#define HDA_RMX_OUTSTRMPAY 112
154
155#define HDA_REG_INSTRMPAY 10 /* 0x1a */
156#define HDA_RMX_INSTRMPAY 113
157
158#define HDA_REG_INTCTL 11 /* 0x20 */
159#define HDA_RMX_INTCTL 9
160#define HDA_INTCTL_GIE_SHIFT 31
161#define HDA_INTCTL_CIE_SHIFT 30
162#define HDA_INTCTL_S0_SHIFT 0
163#define HDA_INTCTL_S1_SHIFT 1
164#define HDA_INTCTL_S2_SHIFT 2
165#define HDA_INTCTL_S3_SHIFT 3
166#define HDA_INTCTL_S4_SHIFT 4
167#define HDA_INTCTL_S5_SHIFT 5
168#define HDA_INTCTL_S6_SHIFT 6
169#define HDA_INTCTL_S7_SHIFT 7
170#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
171
172#define HDA_REG_INTSTS 12 /* 0x24 */
173#define HDA_RMX_INTSTS 10
174#define HDA_INTSTS_GIS_SHIFT 31
175#define HDA_INTSTS_CIS_SHIFT 30
176#define HDA_INTSTS_S0_SHIFT 0
177#define HDA_INTSTS_S1_SHIFT 1
178#define HDA_INTSTS_S2_SHIFT 2
179#define HDA_INTSTS_S3_SHIFT 3
180#define HDA_INTSTS_S4_SHIFT 4
181#define HDA_INTSTS_S5_SHIFT 5
182#define HDA_INTSTS_S6_SHIFT 6
183#define HDA_INTSTS_S7_SHIFT 7
184#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
185
186#define HDA_REG_WALCLK 13 /* 0x24 */
187#define HDA_RMX_WALCLK /* Not defined! */
188
189/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
190 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
191 * the datasheet.
192 */
193#define HDA_REG_SSYNC 14 /* 0x34 */
194#define HDA_RMX_SSYNC 12
195
196#define HDA_REG_CORBLBASE 15 /* 0x40 */
197#define HDA_RMX_CORBLBASE 13
198
199#define HDA_REG_CORBUBASE 16 /* 0x44 */
200#define HDA_RMX_CORBUBASE 14
201
202#define HDA_REG_CORBWP 17 /* 0x48 */
203#define HDA_RMX_CORBWP 15
204
205#define HDA_REG_CORBRP 18 /* 0x4A */
206#define HDA_RMX_CORBRP 16
207#define HDA_CORBRP_RST_SHIFT 15
208#define HDA_CORBRP_WP_SHIFT 0
209#define HDA_CORBRP_WP_MASK 0xFF
210
211#define HDA_REG_CORBCTL 19 /* 0x4C */
212#define HDA_RMX_CORBCTL 17
213#define HDA_CORBCTL_DMA_SHIFT 1
214#define HDA_CORBCTL_CMEIE_SHIFT 0
215
216#define HDA_REG_CORBSTS 20 /* 0x4D */
217#define HDA_RMX_CORBSTS 18
218#define HDA_CORBSTS_CMEI_SHIFT 0
219
220#define HDA_REG_CORBSIZE 21 /* 0x4E */
221#define HDA_RMX_CORBSIZE 19
222#define HDA_CORBSIZE_SZ_CAP 0xF0
223#define HDA_CORBSIZE_SZ 0x3
224/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
225
226#define HDA_REG_RIRBLBASE 22 /* 0x50 */
227#define HDA_RMX_RIRBLBASE 20
228
229#define HDA_REG_RIRBUBASE 23 /* 0x54 */
230#define HDA_RMX_RIRBUBASE 21
231
232#define HDA_REG_RIRBWP 24 /* 0x58 */
233#define HDA_RMX_RIRBWP 22
234#define HDA_RIRBWP_RST_SHIFT 15
235#define HDA_RIRBWP_WP_MASK 0xFF
236
237#define HDA_REG_RINTCNT 25 /* 0x5A */
238#define HDA_RMX_RINTCNT 23
239#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
240
241#define HDA_REG_RIRBCTL 26 /* 0x5C */
242#define HDA_RMX_RIRBCTL 24
243#define HDA_RIRBCTL_RIC_SHIFT 0
244#define HDA_RIRBCTL_DMA_SHIFT 1
245#define HDA_ROI_DMA_SHIFT 2
246
247#define HDA_REG_RIRBSTS 27 /* 0x5D */
248#define HDA_RMX_RIRBSTS 25
249#define HDA_RIRBSTS_RINTFL_SHIFT 0
250#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
251
252#define HDA_REG_RIRBSIZE 28 /* 0x5E */
253#define HDA_RMX_RIRBSIZE 26
254#define HDA_RIRBSIZE_SZ_CAP 0xF0
255#define HDA_RIRBSIZE_SZ 0x3
256
257#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
258#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
259
260
261#define HDA_REG_IC 29 /* 0x60 */
262#define HDA_RMX_IC 27
263
264#define HDA_REG_IR 30 /* 0x64 */
265#define HDA_RMX_IR 28
266
267#define HDA_REG_IRS 31 /* 0x68 */
268#define HDA_RMX_IRS 29
269#define HDA_IRS_ICB_SHIFT 0
270#define HDA_IRS_IRV_SHIFT 1
271
272#define HDA_REG_DPLBASE 32 /* 0x70 */
273#define HDA_RMX_DPLBASE 30
274#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
275
276#define HDA_REG_DPUBASE 33 /* 0x74 */
277#define HDA_RMX_DPUBASE 31
278#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
279/** DMA Position Buffer Enable (3.3.32). */
280#define DPBASE_ENABLED RT_BIT(0)
281#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
282
283#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
284#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
285/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
286#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
287
288#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
289
290#define HDA_REG_SD0CTL 34 /* 0x80 */
291#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
292#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
293#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
294#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
295#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
296#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
297#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
298#define HDA_RMX_SD0CTL 32
299#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
300#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
301#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
302#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
303#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
304#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
305#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
306
307#define SD(func, num) SD##num##func
308
309#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
310#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
311#define HDA_SDCTL_NUM_MASK 0xF
312#define HDA_SDCTL_NUM_SHIFT 20
313#define HDA_SDCTL_DIR_SHIFT 19
314#define HDA_SDCTL_TP_SHIFT 18
315#define HDA_SDCTL_STRIPE_MASK 0x3
316#define HDA_SDCTL_STRIPE_SHIFT 16
317#define HDA_SDCTL_DEIE_SHIFT 4
318#define HDA_SDCTL_FEIE_SHIFT 3
319#define HDA_SDCTL_ICE_SHIFT 2
320#define HDA_SDCTL_RUN_SHIFT 1
321#define HDA_SDCTL_SRST_SHIFT 0
322
323#define HDA_REG_SD0STS 35 /* 0x83 */
324#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
325#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
326#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
327#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
328#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
329#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
330#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
331#define HDA_RMX_SD0STS 33
332#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
333#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
334#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
335#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
336#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
337#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
338#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
339
340#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
341#define HDA_SDSTS_FIFORDY_SHIFT 5
342#define HDA_SDSTS_DE_SHIFT 4
343#define HDA_SDSTS_FE_SHIFT 3
344#define HDA_SDSTS_BCIS_SHIFT 2
345
346#define HDA_REG_SD0LPIB 36 /* 0x84 */
347#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
348#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
349#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
350#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
351#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
352#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
353#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
354#define HDA_RMX_SD0LPIB 34
355#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
356#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
357#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
358#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
359#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
360#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
361#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
362
363#define HDA_REG_SD0CBL 37 /* 0x88 */
364#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
365#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
366#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
367#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
368#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
369#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
370#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
371#define HDA_RMX_SD0CBL 35
372#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
373#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
374#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
375#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
376#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
377#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
378#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
379
380#define HDA_REG_SD0LVI 38 /* 0x8C */
381#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
382#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
383#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
384#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
385#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
386#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
387#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
388#define HDA_RMX_SD0LVI 36
389#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
390#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
391#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
392#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
393#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
394#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
395#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
396
397#define HDA_REG_SD0FIFOW 39 /* 0x8E */
398#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
399#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
400#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
401#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
402#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
403#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
404#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
405#define HDA_RMX_SD0FIFOW 37
406#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
407#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
408#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
409#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
410#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
411#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
412#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
413
414/*
415 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
416 */
417#define HDA_SDFIFOW_8B 0x2
418#define HDA_SDFIFOW_16B 0x3
419#define HDA_SDFIFOW_32B 0x4
420
421#define HDA_REG_SD0FIFOS 40 /* 0x90 */
422#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
423#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
424#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
425#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
426#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
427#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
428#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
429#define HDA_RMX_SD0FIFOS 38
430#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
431#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
432#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
433#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
434#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
435#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
436#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
437
438/*
439 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
440 * formula: size - 1
441 * Other values not listed are not supported.
442 */
443#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
444#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
445
446#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
447#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
448#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
449#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
450#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
451#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
452#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
453
454#define HDA_REG_SD0FMT 41 /* 0x92 */
455#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
456#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
457#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
458#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
459#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
460#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
461#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
462#define HDA_RMX_SD0FMT 39
463#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
464#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
465#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
466#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
467#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
468#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
469#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
470
471#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
472#define HDA_SDFMT_BASE_RATE_SHIFT 14
473#define HDA_SDFMT_MULT_SHIFT 11
474#define HDA_SDFMT_MULT_MASK 0x7
475#define HDA_SDFMT_DIV_SHIFT 8
476#define HDA_SDFMT_DIV_MASK 0x7
477#define HDA_SDFMT_BITS_SHIFT 4
478#define HDA_SDFMT_BITS_MASK 0x7
479#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
480#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
481#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
482
483#define HDA_REG_SD0BDPL 42 /* 0x98 */
484#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
485#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
486#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
487#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
488#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
489#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
490#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
491#define HDA_RMX_SD0BDPL 40
492#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
493#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
494#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
495#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
496#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
497#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
498#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
499
500#define HDA_REG_SD0BDPU 43 /* 0x9C */
501#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
502#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
503#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
504#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
505#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
506#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
507#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
508#define HDA_RMX_SD0BDPU 41
509#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
510#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
511#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
512#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
513#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
514#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
515#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
516
517#define HDA_CODEC_CAD_SHIFT 28
518/* Encodes the (required) LUN into a codec command. */
519#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
520
521
522
523/*********************************************************************************************************************************
524* Structures and Typedefs *
525*********************************************************************************************************************************/
526
527/**
528 * Internal state of a Buffer Descriptor List Entry (BDLE),
529 * needed to keep track of the data needed for the actual device
530 * emulation.
531 */
532typedef struct HDABDLESTATE
533{
534 /** Own index within the BDL (Buffer Descriptor List). */
535 uint32_t u32BDLIndex;
536 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
537 * Used to check if we need fill up the FIFO again. */
538 uint32_t cbBelowFIFOW;
539 /** The buffer descriptor's internal DMA buffer. */
540 uint8_t au8FIFO[HDA_SDONFIFO_256B + 1];
541 /** Current offset in DMA buffer (in bytes).*/
542 uint32_t u32BufOff;
543 uint8_t Padding;
544} HDABDLESTATE, *PHDABDLESTATE;
545
546/**
547 * Buffer Descriptor List Entry (BDLE) (3.6.3).
548 *
549 * Contains only register values which do *not* change until a
550 * stream reset occurs.
551 */
552typedef struct HDABDLE
553{
554 /** Starting address of the actual buffer. Must be 128-bit aligned. */
555 uint64_t u64BufAdr;
556 /** Size of the actual buffer (in bytes). */
557 uint32_t u32BufSize;
558 /** Interrupt on completion; the controller will generate
559 * an interrupt when the last byte of the buffer has been
560 * fetched by the DMA engine. */
561 bool fIntOnCompletion;
562 /** Internal state of this BDLE.
563 * Not part of the actual BDLE registers. */
564 HDABDLESTATE State;
565} HDABDLE, *PHDABDLE;
566
567/**
568 * Internal state of a HDA stream.
569 */
570typedef struct HDASTREAMSTATE
571{
572 /** Number of BDLEs (Buffer Descriptor List Entry).
573 * Should be SDnLVI + 1 usually. */
574 uint16_t cBDLE;
575 /** Current BDLE to use. Wraps around to 0 if
576 * maximum (cBDLE) is reached. */
577 uint16_t uCurBDLE;
578 uint8_t Padding0;
579 /** Array of BDLEs. */
580 R3PTRTYPE(PHDABDLE) paBDLE;
581 uint8_t Padding1[7];
582} HDASTREAMSTATE, *PHDASTREAMSTATE;
583
584/**
585 * Structure for keeping a HDA stream state.
586 *
587 * Contains only register values which do *not* change until a
588 * stream reset occurs.
589 */
590typedef struct HDASTREAM
591{
592 /** Stream number (SDn). */
593 uint8_t u8Strm;
594 uint8_t Padding0[4];
595 /** DMA base address (SDnBDPU - SDnBDPL). */
596 uint64_t u64BaseDMA;
597 /** Cyclic Buffer Length (SDnCBL).
598 * Represents the size of the ring buffer. */
599 uint32_t u32CBL;
600 /** Format (SDnFMT). */
601 uint16_t u16FMT;
602 /** FIFO Size (FIFOS).
603 * Maximum number of bytes that may have been DMA'd into
604 * memory but not yet transmitted on the link.
605 *
606 * Must be a power of two. */
607 uint16_t u16FIFOS;
608 /** Last Valid Index (SDnLVI). */
609 uint16_t u16LVI;
610 uint8_t Padding1[4];
611 /** Internal state of this stream. */
612 HDASTREAMSTATE State;
613} HDASTREAM, *PHDASTREAM;
614
615typedef struct HDAINPUTSTREAM
616{
617 /** PCM line input stream. */
618 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
619 /** Mixer handle for line input stream. */
620 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
621} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
622
623typedef struct HDAOUTPUTSTREAM
624{
625 /** PCM output stream. */
626 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
627 /** Mixer handle for line output stream. */
628 R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
629} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
630
631/**
632 * Struct for maintaining a host backend driver.
633 * This driver must be associated to one, and only one,
634 * HDA codec. The HDA controller does the actual multiplexing
635 * of HDA codec data to various host backend drivers then.
636 *
637 * This HDA device uses a timer in order to synchronize all
638 * read/write accesses across all attached LUNs / backends.
639 */
640typedef struct HDADRIVER
641{
642 union
643 {
644 /** Node for storing this driver in our device driver
645 * list of HDASTATE. */
646 RTLISTNODE Node;
647 struct
648 {
649 R3PTRTYPE(void *) dummy1;
650 R3PTRTYPE(void *) dummy2;
651 } dummy;
652 };
653
654 /** Pointer to HDA controller (state). */
655 R3PTRTYPE(PHDASTATE) pHDAState;
656 /** Driver flags. */
657 PDMAUDIODRVFLAGS Flags;
658 uint8_t u32Padding0[3];
659 /** LUN to which this driver has been assigned. */
660 uint8_t uLUN;
661 /** Audio connector interface to the underlying
662 * host backend. */
663 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
664 /** Stream for line input. */
665 HDAINPUTSTREAM LineIn;
666 /** Stream for mic input. */
667 HDAINPUTSTREAM MicIn;
668 /** Stream for output. */
669 HDAOUTPUTSTREAM Out;
670} HDADRIVER;
671
672/**
673 * ICH Intel HD Audio Controller state.
674 */
675typedef struct HDASTATE
676{
677 /** The PCI device structure. */
678 PCIDevice PciDev;
679 /** R3 Pointer to the device instance. */
680 PPDMDEVINSR3 pDevInsR3;
681 /** R0 Pointer to the device instance. */
682 PPDMDEVINSR0 pDevInsR0;
683 /** R0 Pointer to the device instance. */
684 PPDMDEVINSRC pDevInsRC;
685 /** Padding for alignment. */
686 uint32_t u32Padding;
687 /** Pointer to the attached audio driver. */
688 R3PTRTYPE(PPDMIBASE) pDrvBase;
689 /** The base interface for LUN\#0. */
690 PDMIBASE IBase;
691 RTGCPHYS MMIOBaseAddr;
692 /** The HDA's register set. */
693 uint32_t au32Regs[HDA_NREGS];
694 /** Stream state for line-in. */
695 HDASTREAM StrmStLineIn;
696 /** Stream state for microphone-in. */
697 HDASTREAM StrmStMicIn;
698 /** Stream state for output. */
699 HDASTREAM StrmStOut;
700 /** CORB buffer base address. */
701 uint64_t u64CORBBase;
702 /** RIRB buffer base address. */
703 uint64_t u64RIRBBase;
704 /** DMA base address.
705 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
706 uint64_t u64DPBase;
707 /** Pointer to CORB buffer. */
708 R3PTRTYPE(uint32_t *) pu32CorbBuf;
709 /** Size in bytes of CORB buffer. */
710 uint32_t cbCorbBuf;
711 /** Padding for alignment. */
712 uint32_t u32Padding2;
713 /** Pointer to RIRB buffer. */
714 R3PTRTYPE(uint64_t *) pu64RirbBuf;
715 /** Size in bytes of RIRB buffer. */
716 uint32_t cbRirbBuf;
717 /** Indicates if HDA is in reset. */
718 bool fInReset;
719 /** Flag whether the R0 part is enabled. */
720 bool fR0Enabled;
721 /** Flag whether the RC part is enabled. */
722 bool fRCEnabled;
723 /** The emulation timer for handling the attached
724 * LUN drivers. */
725 PTMTIMERR3 pTimer;
726 /** Timer ticks for handling the LUN drivers. */
727 uint64_t uTicks;
728#ifdef VBOX_WITH_STATISTICS
729# ifndef VBOX_WITH_AUDIO_CALLBACKS
730 STAMPROFILE StatTimer;
731# endif
732 STAMCOUNTER StatBytesRead;
733 STAMCOUNTER StatBytesWritten;
734#endif
735 /** Pointer to HDA codec to use. */
736 R3PTRTYPE(PHDACODEC) pCodec;
737 union
738 {
739 /** List of associated LUN drivers. */
740 RTLISTANCHOR lstDrv;
741 /** Padding for alignment. */
742 struct
743 {
744 R3PTRTYPE(void *) dummy1;
745 R3PTRTYPE(void *) dummy2;
746 } dummy;
747 };
748 /** The device' software mixer. */
749 R3PTRTYPE(PAUDIOMIXER) pMixer;
750 /** Audio sink for PCM output. */
751 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
752 /** Audio mixer sink for line input. */
753 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
754 /** Audio mixer sink for microphone input. */
755 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
756 uint64_t u64BaseTS;
757 /** Response Interrupt Count (RINTCNT). */
758 uint8_t u8RespIntCnt;
759 /** Padding for alignment. */
760 uint8_t au8Padding[7];
761} HDASTATE;
762/** Pointer to the ICH Intel HD Audio Controller state. */
763typedef HDASTATE *PHDASTATE;
764
765#ifdef VBOX_WITH_AUDIO_CALLBACKS
766typedef struct HDACALLBACKCTX
767{
768 PHDASTATE pThis;
769 PHDADRIVER pDriver;
770} HDACALLBACKCTX, *PHDACALLBACKCTX;
771#endif
772
773#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
774 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
775#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
776 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
777
778
779/*********************************************************************************************************************************
780* Internal Functions *
781*********************************************************************************************************************************/
782#ifndef VBOX_DEVICE_STRUCT_TESTCASE
783static FNPDMDEVRESET hdaReset;
784
785/*
786 * Stubs.
787 */
788static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
789static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
790
791/*
792 * Global register set read/write functions.
793 */
794static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
795static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
796static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
797static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
798static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
799static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
800static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
801static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
802static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
803static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
804static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
805static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
806static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
807static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
808static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
809
810/*
811 * {IOB}SDn read/write functions.
812 */
813static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
814static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
815static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
816static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
817static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
818static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
819static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
820static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
821static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
822
823/*
824 * Generic register read/write functions.
825 */
826static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
827static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
828static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
829static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
830static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
831static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
832static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
833static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
834
835static void hdaStreamDestroy(PHDASTREAM pStrmSt);
836
837static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t *pcbProcessed);
838
839#ifdef IN_RING3
840static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
841# ifdef LOG_ENABLED
842static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t u16LVI);
843# endif
844static void hdaBDLEReset(PHDABDLE pBDLE);
845#endif
846
847
848/*********************************************************************************************************************************
849* Global Variables *
850*********************************************************************************************************************************/
851
852/* see 302349 p 6.2. */
853static const struct HDAREGDESC
854{
855 /** Register offset in the register space. */
856 uint32_t offset;
857 /** Size in bytes. Registers of size > 4 are in fact tables. */
858 uint32_t size;
859 /** Readable bits. */
860 uint32_t readable;
861 /** Writable bits. */
862 uint32_t writable;
863 /** Read callback. */
864 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
865 /** Write callback. */
866 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
867 /** Index into the register storage array. */
868 uint32_t mem_idx;
869 /** Abbreviated name. */
870 const char *abbrev;
871} g_aHdaRegMap[HDA_NREGS] =
872
873/* Turn a short register name into an memory index and a stringized name. */
874#define RA(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
875/* Same as above for an input stream ('I' prefixed). */
876#define IA(abbrev) HDA_MEM_IND_NAME(abbrev), "I"#abbrev
877/* Same as above for an output stream ('O' prefixed). */
878#define OA(abbrev) HDA_MEM_IND_NAME(abbrev), "O"#abbrev
879/* Same as above for a register *not* stored in memory. */
880#define UA(abbrev) 0, #abbrev
881
882{
883 /* offset size read mask write mask read callback write callback abbrev */
884 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- */
885 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(GCAP) }, /* Global Capabilities */
886 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMIN) }, /* Minor Version */
887 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMAJ) }, /* Major Version */
888 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTPAY) }, /* Output Payload Capabilities */
889 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INPAY) }, /* Input Payload Capabilities */
890 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , RA(GCTL) }, /* Global Control */
891 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , RA(WAKEEN) }, /* Wake Enable */
892 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , RA(STATESTS) }, /* State Change Status */
893 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , RA(GSTS) }, /* Global Status */
894 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTSTRMPAY)}, /* Output Stream Payload Capability */
895 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INSTRMPAY) }, /* Input Stream Payload Capability */
896 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(INTCTL) }, /* Interrupt Control */
897 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , RA(INTSTS) }, /* Interrupt Status */
898 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , UA(WALCLK) }, /* Wall Clock Counter */
899 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
900 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(SSYNC) }, /* Stream Synchronization */
901 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(CORBLBASE) }, /* CORB Lower Base Address */
902 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(CORBUBASE) }, /* CORB Upper Base Address */
903 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , RA(CORBWP) }, /* CORB Write Pointer */
904 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , RA(CORBRP) }, /* CORB Read Pointer */
905 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , RA(CORBCTL) }, /* CORB Control */
906 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , RA(CORBSTS) }, /* CORB Status */
907 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(CORBSIZE) }, /* CORB Size */
908 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBLBASE) }, /* RIRB Lower Base Address */
909 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBUBASE) }, /* RIRB Upper Base Address */
910 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , RA(RIRBWP) }, /* RIRB Write Pointer */
911 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , RA(RINTCNT) }, /* Response Interrupt Count */
912 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , RA(RIRBCTL) }, /* RIRB Control */
913 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , RA(RIRBSTS) }, /* RIRB Status */
914 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(RIRBSIZE) }, /* RIRB Size */
915 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , RA(IC) }, /* Immediate Command */
916 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , RA(IR) }, /* Immediate Response */
917 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , RA(IRS) }, /* Immediate Command Status */
918 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , RA(DPLBASE) }, /* MA Position Lower Base */
919 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(DPUBASE) }, /* DMA Position Upper Base */
920
921 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD0CTL) }, /* Input Stream Descriptor 0 (ICD0) Control */
922 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD0STS) }, /* ISD0 Status */
923 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB , hdaRegWriteUnimpl , IA(SD0LPIB) }, /* ISD0 Link Position In Buffer (RO) */
924 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDCBL , IA(SD0CBL) }, /* ISD0 Cyclic Buffer Length */
925 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD0LVI) }, /* ISD0 Last Valid Index */
926 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD0FIFOW) }, /* ISD0 FIFO Watermark */
927 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD0FIFOS) }, /* ISD0 FIFO Size */
928 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD0FMT) }, /* ISD0 Format */
929 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD0BDPL) }, /* ISD0 Buffer Descriptor List Pointer-Lower Base Address */
930 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD0BDPU) }, /* ISD0 Buffer Descriptor List Pointer-Upper Base Address */
931
932 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD1CTL) }, /* Input Stream Descriptor 1 (ISD1) Control */
933 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD1STS) }, /* ISD1 Status */
934 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB , hdaRegWriteUnimpl , IA(SD1LPIB) }, /* ISD1 Link Position In Buffer (RO). */
935 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDCBL , IA(SD1CBL) }, /* ISD1 Cyclic Buffer Length */
936 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD1LVI) }, /* ISD1 Last Valid Index */
937 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD1FIFOW) }, /* ISD1 FIFO Watermark */
938 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD1FIFOS) }, /* ISD1 FIFO Size */
939 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD1FMT) }, /* ISD1 Format */
940 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD1BDPL) }, /* ISD1 Buffer Descriptor List Pointer-Lower Base Address */
941 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD1BDPU) }, /* ISD1 Buffer Descriptor List Pointer-Upper Base Address */
942
943 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD2CTL) }, /* Input Stream Descriptor 2 (ISD2) Control */
944 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD2STS) }, /* ISD2 Status */
945 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB , hdaRegWriteUnimpl , IA(SD2LPIB) }, /* ISD2 Link Position In Buffer (RO) */
946 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDCBL , IA(SD2CBL) }, /* ISD2 Cyclic Buffer Length */
947 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD2LVI) }, /* ISD2 Last Valid Index */
948 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD2FIFOW) }, /* ISD2 FIFO Watermark */
949 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD2FIFOS) }, /* ISD2 FIFO Size */
950 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD2FMT) }, /* ISD2 Format */
951 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD2BDPL) }, /* ISD2 Buffer Descriptor List Pointer-Lower Base Address */
952 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD2BDPU) }, /* ISD2 Buffer Descriptor List Pointer-Upper Base Address */
953
954 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD3CTL) }, /* Input Stream Descriptor 3 (ISD3) Control */
955 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD3STS) }, /* ISD3 Status */
956 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB , hdaRegWriteUnimpl , IA(SD3LPIB) }, /* ISD3 Link Position In Buffer (RO) */
957 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDCBL , IA(SD3CBL) }, /* ISD3 Cyclic Buffer Length */
958 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD3LVI) }, /* ISD3 Last Valid Index */
959 { 0x000EE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD3FIFOW) }, /* ISD3 FIFO Watermark */
960 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD3FIFOS) }, /* ISD3 FIFO Size */
961 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD3FMT) }, /* ISD3 Format */
962 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD3BDPL) }, /* ISD3 Buffer Descriptor List Pointer-Lower Base Address */
963 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD3BDPU) }, /* ISD3 Buffer Descriptor List Pointer-Upper Base Address */
964
965 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD4CTL) }, /* Output Stream Descriptor 4 (OSD4) Control */
966 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD4STS) }, /* OSD4 Status */
967 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB , hdaRegWriteUnimpl , OA(SD4LPIB) }, /* OSD4 Link Position In Buffer (RO) */
968 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDCBL , OA(SD4CBL) }, /* OSD4 Cyclic Buffer Length */
969 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD4LVI) }, /* OSD4 Last Valid Index */
970 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD4FIFOW) }, /* OSD4 FIFO Watermark */
971 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD4FIFOS) }, /* OSD4 FIFO Size */
972 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD4FMT) }, /* OSD4 Format */
973 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD4BDPL) }, /* OSD4 Buffer Descriptor List Pointer-Lower Base Address */
974 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD4BDPU) }, /* OSD4 Buffer Descriptor List Pointer-Upper Base Address */
975
976 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD5CTL) }, /* Output Stream Descriptor 5 (OSD5) Control */
977 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD5STS) }, /* OSD5 Status */
978 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB , hdaRegWriteUnimpl , OA(SD5LPIB) }, /* OSD5 Link Position In Buffer (RO) */
979 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDCBL , OA(SD5CBL) }, /* OSD5 Cyclic Buffer Length */
980 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD5LVI) }, /* OSD5 Last Valid Index */
981 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD5FIFOW) }, /* OSD5 FIFO Watermark */
982 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD5FIFOS) }, /* OSD5 FIFO Size */
983 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD5FMT) }, /* OSD5 Format */
984 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD5BDPL) }, /* OSD5 Buffer Descriptor List Pointer-Lower Base Address */
985 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD5BDPU) }, /* OSD5 Buffer Descriptor List Pointer-Upper Base Address */
986
987 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD6CTL) }, /* Output Stream Descriptor 6 (OSD6) Control */
988 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD6STS) }, /* OSD6 Status */
989 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB , hdaRegWriteUnimpl , OA(SD6LPIB) }, /* OSD6 Link Position In Buffer (RO) */
990 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDCBL , OA(SD6CBL) }, /* OSD6 Cyclic Buffer Length */
991 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD6LVI) }, /* OSD6 Last Valid Index */
992 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD6FIFOW) }, /* OSD6 FIFO Watermark */
993 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD6FIFOS) }, /* OSD6 FIFO Size */
994 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD6FMT) }, /* OSD6 Format */
995 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD6BDPL) }, /* OSD6 Buffer Descriptor List Pointer-Lower Base Address */
996 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD6BDPU) }, /* OSD6 Buffer Descriptor List Pointer-Upper Base Address */
997
998 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD7CTL) }, /* Output Stream Descriptor 7 (OSD7) Control */
999 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD7STS) }, /* OSD7 Status */
1000 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB , hdaRegWriteUnimpl , OA(SD7LPIB) }, /* OSD7 Link Position In Buffer (RO) */
1001 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDCBL , OA(SD7CBL) }, /* OSD7 Cyclic Buffer Length */
1002 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD7LVI) }, /* OSD7 Last Valid Index */
1003 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD7FIFOW) }, /* OSD7 FIFO Watermark */
1004 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD7FIFOS) }, /* OSD7 FIFO Size */
1005 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD7FMT) }, /* OSD7 Format */
1006 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD7BDPL) }, /* OSD7 Buffer Descriptor List Pointer-Lower Base Address */
1007 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD7BDPU) }, /* OSD7 Buffer Descriptor List Pointer-Upper Base Address */
1008};
1009
1010/**
1011 * HDA register aliases (HDA spec 3.3.45).
1012 * @remarks Sorted by offReg.
1013 */
1014static const struct
1015{
1016 /** The alias register offset. */
1017 uint32_t offReg;
1018 /** The register index. */
1019 int idxAlias;
1020} g_aHdaRegAliases[] =
1021{
1022 { 0x2084, HDA_REG_SD0LPIB },
1023 { 0x20a4, HDA_REG_SD1LPIB },
1024 { 0x20c4, HDA_REG_SD2LPIB },
1025 { 0x20e4, HDA_REG_SD3LPIB },
1026 { 0x2104, HDA_REG_SD4LPIB },
1027 { 0x2124, HDA_REG_SD5LPIB },
1028 { 0x2144, HDA_REG_SD6LPIB },
1029 { 0x2164, HDA_REG_SD7LPIB },
1030};
1031
1032#ifdef IN_RING3
1033/** HDABDLESTATE field descriptors for the v5+ saved state. */
1034static SSMFIELD const g_aSSMBDLEStateFields5[] =
1035{
1036 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
1037 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
1038 SSMFIELD_ENTRY(HDABDLESTATE, au8FIFO),
1039 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
1040 SSMFIELD_ENTRY_TERM()
1041};
1042
1043/** HDASTREAMSTATE field descriptors for the v5+ saved state. */
1044static SSMFIELD const g_aSSMStreamStateFields5[] =
1045{
1046 SSMFIELD_ENTRY (HDASTREAMSTATE, cBDLE),
1047 SSMFIELD_ENTRY (HDASTREAMSTATE, uCurBDLE),
1048 SSMFIELD_ENTRY_IGNORE(HDASTREAMSTATE, paBDLE),
1049 SSMFIELD_ENTRY_TERM()
1050};
1051#endif
1052
1053/**
1054 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1055 */
1056static uint32_t const g_afMasks[5] =
1057{
1058 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1059};
1060
1061#ifdef IN_RING3
1062DECLINLINE(void) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t u32LPIB)
1063{
1064 AssertPtrReturnVoid(pThis);
1065 AssertPtrReturnVoid(pStrmSt);
1066
1067 Assert(u32LPIB <= pStrmSt->u32CBL);
1068
1069 LogFlowFunc(("uStrm=%RU8, LPIB=%RU32 (DMA Position: %RTbool)\n",
1070 pStrmSt->u8Strm, u32LPIB, RT_BOOL(pThis->u64DPBase & DPBASE_ENABLED)));
1071
1072 /* Update LPIB in any case. */
1073 HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) = u32LPIB;
1074
1075 /* Do we need to tell the current DMA position? */
1076 if (pThis->u64DPBase & DPBASE_ENABLED)
1077 {
1078 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1079 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStrmSt->u8Strm * 8),
1080 (void *)&u32LPIB, sizeof(uint32_t));
1081 AssertRC(rc2);
1082 }
1083}
1084#endif
1085
1086/**
1087 * Retrieves the number of bytes of a FIFOS register.
1088 *
1089 * @return Number of bytes of a given FIFOS register.
1090 */
1091DECLINLINE(uint16_t) hdaSDFIFOSToBytes(uint32_t u32RegFIFOS)
1092{
1093 uint16_t cb;
1094 switch (u32RegFIFOS)
1095 {
1096 /* Input */
1097 case HDA_SDINFIFO_120B: cb = 120; break;
1098 case HDA_SDINFIFO_160B: cb = 160; break;
1099
1100 /* Output */
1101 case HDA_SDONFIFO_16B: cb = 16; break;
1102 case HDA_SDONFIFO_32B: cb = 32; break;
1103 case HDA_SDONFIFO_64B: cb = 64; break;
1104 case HDA_SDONFIFO_128B: cb = 128; break;
1105 case HDA_SDONFIFO_192B: cb = 192; break;
1106 case HDA_SDONFIFO_256B: cb = 256; break;
1107 default:
1108 {
1109 cb = 0;
1110 AssertMsgFailed(("Wrong FIFO value\n"));
1111 break;
1112 }
1113 }
1114
1115 return cb;
1116}
1117
1118/**
1119 * Retrieves the number of bytes of a FIFOW register.
1120 *
1121 * @return Number of bytes of a given FIFOW register.
1122 */
1123DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1124{
1125 uint32_t cb;
1126 switch (u32RegFIFOW)
1127 {
1128 case HDA_SDFIFOW_8B: cb = 8; break;
1129 case HDA_SDFIFOW_16B: cb = 16; break;
1130 case HDA_SDFIFOW_32B: cb = 32; break;
1131 default: cb = 0; break;
1132 }
1133
1134#ifdef RT_STRICT
1135 Assert(RT_IS_POWER_OF_TWO(cb));
1136#endif
1137 return cb;
1138}
1139
1140#ifdef IN_RING3
1141/**
1142 * Returns the current BDLE to use for a stream.
1143 *
1144 * @return BDLE to use, NULL if none found.
1145 */
1146DECLINLINE(PHDABDLE) hdaStreamGetCurrentBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
1147{
1148 AssertPtrReturn(pThis, NULL);
1149 AssertPtrReturn(pStrmSt, NULL);
1150
1151 Assert(pStrmSt->State.paBDLE);
1152 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1153
1154 PHDABDLE pBDLE = &pStrmSt->State.paBDLE[pStrmSt->State.uCurBDLE];
1155 return pBDLE;
1156}
1157
1158/**
1159 * Returns the next BDLE to use for a stream.
1160 *
1161 * @return BDLE to use next, NULL if none found.
1162 */
1163DECLINLINE(PHDABDLE) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
1164{
1165 AssertPtrReturn(pThis, NULL);
1166 AssertPtrReturn(pStrmSt, NULL);
1167
1168 NOREF(pThis);
1169
1170 Assert(pStrmSt->State.paBDLE);
1171 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1172
1173#ifdef DEBUG
1174 uint32_t uOldBDLE = pStrmSt->State.uCurBDLE;
1175#endif
1176
1177 pStrmSt->State.uCurBDLE++;
1178 if (pStrmSt->State.uCurBDLE == pStrmSt->State.cBDLE)
1179 {
1180 pStrmSt->State.uCurBDLE = 0;
1181
1182 hdaStreamUpdateLPIB(pThis, pStrmSt, 0);
1183 }
1184
1185 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1186
1187 PHDABDLE pBDLE = &pStrmSt->State.paBDLE[pStrmSt->State.uCurBDLE];
1188 AssertPtr(pBDLE);
1189
1190 hdaBDLEReset(pBDLE);
1191
1192#ifdef DEBUG
1193 LogFlowFunc(("uOldBDLE=%RU16, uCurBDLE=%RU16 %R[bdle]\n", uOldBDLE, pStrmSt->State.uCurBDLE, pBDLE));
1194#endif
1195 return pBDLE;
1196}
1197#endif
1198
1199/**
1200 * Retrieves the minimum number of bytes accumulated/free in the
1201 * FIFO before the controller will start a fetch/eviction of data.
1202 *
1203 * Uses SDFIFOW (FIFO Watermark Register).
1204 *
1205 * @return Number of bytes accumulated/free in the FIFO.
1206 */
1207DECLINLINE(uint8_t) hdaStreamGetFIFOW(PHDASTATE pThis, PHDASTREAM pStrmSt)
1208{
1209 AssertPtrReturn(pThis, 0);
1210 AssertPtrReturn(pStrmSt, 0);
1211
1212#ifdef VBOX_HDA_WITH_FIFO
1213 return hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, pStrmSt->u8Strm));
1214#else
1215 return 0;
1216#endif
1217}
1218
1219static int hdaProcessInterrupt(PHDASTATE pThis)
1220{
1221#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1222 ( INTCTL_SX((pThis), num) \
1223 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1224
1225 bool fIrq = false;
1226
1227 if (/* Controller Interrupt Enable (CIE). */
1228 HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1229 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1230 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1231 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1232 fIrq = true;
1233
1234 /** @todo Don't hardcode stream numbers here. */
1235 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1236 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1237 {
1238#ifdef IN_RING3
1239 LogFunc(("BCIS\n"));
1240#endif
1241 fIrq = true;
1242 }
1243
1244 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1245 {
1246 LogFunc(("%s\n", fIrq ? "Asserted" : "Deasserted"));
1247 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1248 }
1249
1250#undef IS_INTERRUPT_OCCURED_AND_ENABLED
1251
1252 return VINF_SUCCESS;
1253}
1254
1255/**
1256 * Looks up a register at the exact offset given by @a offReg.
1257 *
1258 * @returns Register index on success, -1 if not found.
1259 * @param pThis The HDA device state.
1260 * @param offReg The register offset.
1261 */
1262static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1263{
1264 /*
1265 * Aliases.
1266 */
1267 if (offReg >= g_aHdaRegAliases[0].offReg)
1268 {
1269 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1270 if (offReg == g_aHdaRegAliases[i].offReg)
1271 return g_aHdaRegAliases[i].idxAlias;
1272 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1273 return -1;
1274 }
1275
1276 /*
1277 * Binary search the
1278 */
1279 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1280 int idxLow = 0;
1281 for (;;)
1282 {
1283 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1284 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1285 {
1286 if (idxLow == idxMiddle)
1287 break;
1288 idxEnd = idxMiddle;
1289 }
1290 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1291 {
1292 idxLow = idxMiddle + 1;
1293 if (idxLow >= idxEnd)
1294 break;
1295 }
1296 else
1297 return idxMiddle;
1298 }
1299
1300#ifdef RT_STRICT
1301 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1302 Assert(g_aHdaRegMap[i].offset != offReg);
1303#endif
1304 return -1;
1305}
1306
1307/**
1308 * Looks up a register covering the offset given by @a offReg.
1309 *
1310 * @returns Register index on success, -1 if not found.
1311 * @param pThis The HDA device state.
1312 * @param offReg The register offset.
1313 */
1314static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1315{
1316 /*
1317 * Aliases.
1318 */
1319 if (offReg >= g_aHdaRegAliases[0].offReg)
1320 {
1321 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1322 {
1323 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1324 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1325 return g_aHdaRegAliases[i].idxAlias;
1326 }
1327 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1328 return -1;
1329 }
1330
1331 /*
1332 * Binary search the register map.
1333 */
1334 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1335 int idxLow = 0;
1336 for (;;)
1337 {
1338 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1339 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1340 {
1341 if (idxLow == idxMiddle)
1342 break;
1343 idxEnd = idxMiddle;
1344 }
1345 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1346 {
1347 idxLow = idxMiddle + 1;
1348 if (idxLow >= idxEnd)
1349 break;
1350 }
1351 else
1352 return idxMiddle;
1353 }
1354
1355#ifdef RT_STRICT
1356 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1357 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1358#endif
1359 return -1;
1360}
1361
1362#ifdef IN_RING3
1363static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1364{
1365 int rc = VINF_SUCCESS;
1366 if (fLocal)
1367 {
1368 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1369 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1370 if (RT_FAILURE(rc))
1371 AssertRCReturn(rc, rc);
1372#ifdef DEBUG_CMD_BUFFER
1373 uint8_t i = 0;
1374 do
1375 {
1376 LogFunc(("CORB%02x: ", i));
1377 uint8_t j = 0;
1378 do
1379 {
1380 const char *pszPrefix;
1381 if ((i + j) == HDA_REG(pThis, CORBRP));
1382 pszPrefix = "[R]";
1383 else if ((i + j) == HDA_REG(pThis, CORBWP));
1384 pszPrefix = "[W]";
1385 else
1386 pszPrefix = " "; /* three spaces */
1387 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1388 j++;
1389 } while (j < 8);
1390 LogFunc(("\n"));
1391 i += 8;
1392 } while(i != 0);
1393#endif
1394 }
1395 else
1396 {
1397 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1398 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1399 if (RT_FAILURE(rc))
1400 AssertRCReturn(rc, rc);
1401#ifdef DEBUG_CMD_BUFFER
1402 uint8_t i = 0;
1403 do {
1404 LogFunc(("RIRB%02x: ", i));
1405 uint8_t j = 0;
1406 do {
1407 const char *prefix;
1408 if ((i + j) == HDA_REG(pThis, RIRBWP))
1409 prefix = "[W]";
1410 else
1411 prefix = " ";
1412 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1413 } while (++j < 8);
1414 LogFunc(("\n"));
1415 i += 8;
1416 } while (i != 0);
1417#endif
1418 }
1419 return rc;
1420}
1421
1422static int hdaCORBCmdProcess(PHDASTATE pThis)
1423{
1424 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1425
1426 int rc = hdaCmdSync(pThis, true);
1427 if (RT_FAILURE(rc))
1428 AssertRCReturn(rc, rc);
1429
1430 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1431 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1432 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1433
1434 Assert((corbWp != corbRp));
1435 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1436
1437 while (corbRp != corbWp)
1438 {
1439 uint32_t cmd;
1440 uint64_t resp;
1441 pfn = NULL;
1442 corbRp++;
1443 cmd = pThis->pu32CorbBuf[corbRp];
1444
1445 rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* Codec index */), &pfn);
1446 if (RT_SUCCESS(rc))
1447 {
1448 AssertPtr(pfn);
1449 rc = pfn(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1450 }
1451
1452 if (RT_FAILURE(rc))
1453 AssertRCReturn(rc, rc);
1454 (rirbWp)++;
1455
1456 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1457 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1458 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1459 {
1460 LogFunc(("unexpected unsolicited response.\n"));
1461 HDA_REG(pThis, CORBRP) = corbRp;
1462 return rc;
1463 }
1464
1465 pThis->pu64RirbBuf[rirbWp] = resp;
1466
1467 pThis->u8RespIntCnt++;
1468 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1469 break;
1470 }
1471 HDA_REG(pThis, CORBRP) = corbRp;
1472 HDA_REG(pThis, RIRBWP) = rirbWp;
1473 rc = hdaCmdSync(pThis, false);
1474 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1475 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1476 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1477 {
1478 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1479
1480 pThis->u8RespIntCnt = 0;
1481 rc = hdaProcessInterrupt(pThis);
1482 }
1483 if (RT_FAILURE(rc))
1484 AssertRCReturn(rc, rc);
1485 return rc;
1486}
1487
1488static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1489{
1490 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1491 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1492
1493 pStrmSt->u8Strm = u8Strm;
1494 pStrmSt->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
1495 HDA_STREAM_REG(pThis, BDPU, u8Strm));
1496 pStrmSt->u16LVI = HDA_STREAM_REG(pThis, LVI, u8Strm);
1497 pStrmSt->u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1498 pStrmSt->u16FIFOS = hdaSDFIFOSToBytes(HDA_STREAM_REG(pThis, FIFOS, u8Strm));
1499
1500 hdaStreamDestroy(pStrmSt);
1501
1502 int rc = VINF_SUCCESS;
1503
1504 if (pStrmSt->u16LVI) /* Any BDLEs to fetch? */
1505 {
1506 uint32_t cbBDLE = 0;
1507
1508 pStrmSt->State.cBDLE = pStrmSt->u16LVI + 1; /* See 18.2.37: If LVI is n, then there are n + 1 entries. */
1509 pStrmSt->State.paBDLE = (PHDABDLE)RTMemAllocZ(sizeof(HDABDLE) * pStrmSt->State.cBDLE);
1510 if (pStrmSt->State.paBDLE)
1511 {
1512 for (uint16_t i = 0; i < pStrmSt->State.cBDLE; i++)
1513 {
1514 rc = hdaBDLEFetch(pThis, &pStrmSt->State.paBDLE[i], pStrmSt->u64BaseDMA, i);
1515 if (RT_FAILURE(rc))
1516 break;
1517
1518 cbBDLE += pStrmSt->State.paBDLE[i].u32BufSize;
1519 }
1520
1521#ifdef DEBUG
1522 hdaBDLEDumpAll(pThis, pStrmSt->u64BaseDMA, pStrmSt->State.cBDLE);
1523#endif
1524 if (RT_SUCCESS(rc))
1525 {
1526 if (pStrmSt->u32CBL != cbBDLE)
1527 LogRel(("HDA: Warning: CBL (%RU32) does not match BDL entries (%RU32); expect sound hickups\n",
1528 pStrmSt->u32CBL, cbBDLE));
1529
1530 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1531 }
1532 }
1533 else
1534 rc = VERR_NO_MEMORY;
1535 }
1536
1537 LogFunc(("[SD%RU8]: DMA=0x%x, LVI=%RU16, CBL=%RU32, FIFOS=%RU16\n",
1538 u8Strm, pStrmSt->u64BaseDMA, pStrmSt->u16LVI, pStrmSt->u32CBL, pStrmSt->u16FIFOS));
1539
1540 return rc;
1541}
1542
1543static void hdaStreamDestroy(PHDASTREAM pStrmSt)
1544{
1545 AssertPtrReturnVoid(pStrmSt);
1546
1547 if (pStrmSt->State.paBDLE)
1548 {
1549 Assert(pStrmSt->State.cBDLE);
1550 RTMemFree(pStrmSt->State.paBDLE);
1551 pStrmSt->State.paBDLE = NULL;
1552 }
1553
1554 pStrmSt->State.cBDLE = 0;
1555}
1556#endif
1557
1558static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1559{
1560 AssertPtrReturnVoid(pThis);
1561 AssertPtrReturnVoid(pStrmSt);
1562 AssertReturnVoid(u8Strm <= 7); /** @todo Use a define for MAX_STRAEMS! */
1563
1564 /*
1565 * Initialize stream state.
1566 */
1567 RT_BZERO(pStrmSt, sizeof(HDASTREAM));
1568
1569 /*
1570 * Initialize registers.
1571 */
1572 HDA_STREAM_REG(pThis, STS, u8Strm) = 0;
1573 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1574 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1575 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1576
1577 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39. */
1578 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1579 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1580 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = HDA_SDFIFOW_32B;
1581 HDA_STREAM_REG(pThis, LPIB, u8Strm) = 0;
1582 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1583 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1584 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1585 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1586 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1587
1588 LogFunc(("[SD%RU8] Reset\n", u8Strm));
1589}
1590
1591/* Register access handlers. */
1592
1593static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1594{
1595 *pu32Value = 0;
1596 return VINF_SUCCESS;
1597}
1598
1599static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1600{
1601 return VINF_SUCCESS;
1602}
1603
1604/* U8 */
1605static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1606{
1607 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1608 return hdaRegReadU32(pThis, iReg, pu32Value);
1609}
1610
1611static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1612{
1613 Assert((u32Value & 0xffffff00) == 0);
1614 return hdaRegWriteU32(pThis, iReg, u32Value);
1615}
1616
1617/* U16 */
1618static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1619{
1620 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1621 return hdaRegReadU32(pThis, iReg, pu32Value);
1622}
1623
1624static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1625{
1626 Assert((u32Value & 0xffff0000) == 0);
1627 return hdaRegWriteU32(pThis, iReg, u32Value);
1628}
1629
1630/* U24 */
1631static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1632{
1633 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1634 return hdaRegReadU32(pThis, iReg, pu32Value);
1635}
1636
1637static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1638{
1639 Assert((u32Value & 0xff000000) == 0);
1640 return hdaRegWriteU32(pThis, iReg, u32Value);
1641}
1642
1643/* U32 */
1644static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1645{
1646 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1647
1648 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1649 return VINF_SUCCESS;
1650}
1651
1652static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1653{
1654 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1655
1656 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1657 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1658 return VINF_SUCCESS;
1659}
1660
1661static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1662{
1663 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1664 {
1665 /* Exit reset state. */
1666 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1667 pThis->fInReset = false;
1668 }
1669 else
1670 {
1671#ifdef IN_RING3
1672 /* Enter reset state. */
1673 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1674 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1675 {
1676 LogFunc(("HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1677 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1678 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1679 }
1680 hdaReset(pThis->CTX_SUFF(pDevIns));
1681 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1682 pThis->fInReset = true;
1683#else
1684 return VINF_IOM_R3_MMIO_WRITE;
1685#endif
1686 }
1687 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1688 {
1689 /* Flush: GSTS:1 set, see 6.2.6. */
1690 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
1691 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1692 }
1693 return VINF_SUCCESS;
1694}
1695
1696static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1697{
1698 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1699
1700 uint32_t v = pThis->au32Regs[iRegMem];
1701 uint32_t nv = u32Value & HDA_STATES_SCSF;
1702 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1703 return VINF_SUCCESS;
1704}
1705
1706static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1707{
1708 uint32_t v = 0;
1709 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1710 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1711 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1712 || HDA_REG(pThis, STATESTS))
1713 {
1714 v |= RT_BIT(30); /* Touch CIS. */
1715 }
1716
1717#define HDA_IS_STREAM_EVENT(pThis, num) \
1718 ( (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1719 || (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1720 || (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1721
1722#define HDA_MARK_STREAM(pThis, num, v) \
1723 do { (v) |= HDA_IS_STREAM_EVENT((pThis), num) ? RT_BIT((num)) : 0; } while(0)
1724
1725 HDA_MARK_STREAM(pThis, 0, v);
1726 HDA_MARK_STREAM(pThis, 1, v);
1727 HDA_MARK_STREAM(pThis, 2, v);
1728 HDA_MARK_STREAM(pThis, 3, v);
1729 HDA_MARK_STREAM(pThis, 4, v);
1730 HDA_MARK_STREAM(pThis, 5, v);
1731 HDA_MARK_STREAM(pThis, 6, v);
1732 HDA_MARK_STREAM(pThis, 7, v);
1733
1734#undef HDA_IS_STREAM_EVENT
1735#undef HDA_MARK_STREAM
1736
1737 v |= v ? RT_BIT(31) : 0;
1738
1739 *pu32Value = v;
1740 return VINF_SUCCESS;
1741}
1742
1743static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1744{
1745 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1746 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1747 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1748
1749 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
1750
1751 *pu32Value = u32LPIB;
1752 return VINF_SUCCESS;
1753}
1754
1755static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1756{
1757 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1758 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1759 - pThis->u64BaseTS, 24, 1000);
1760 return VINF_SUCCESS;
1761}
1762
1763static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1764{
1765 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1766 {
1767 HDA_REG(pThis, CORBRP) = 0;
1768 }
1769#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1770 else
1771 return hdaRegWriteU8(pThis, iReg, u32Value);
1772#endif
1773 return VINF_SUCCESS;
1774}
1775
1776static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1777{
1778#ifdef IN_RING3
1779 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1780 AssertRC(rc);
1781 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1782 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1783 {
1784 return hdaCORBCmdProcess(pThis);
1785 }
1786 return rc;
1787#else
1788 return VINF_IOM_R3_MMIO_WRITE;
1789#endif
1790}
1791
1792static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1793{
1794 uint32_t v = HDA_REG(pThis, CORBSTS);
1795 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1796 return VINF_SUCCESS;
1797}
1798
1799static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1800{
1801#ifdef IN_RING3
1802 int rc;
1803 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1804 if (RT_FAILURE(rc))
1805 AssertRCReturn(rc, rc);
1806 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1807 return VINF_SUCCESS;
1808 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1809 return VINF_SUCCESS;
1810 rc = hdaCORBCmdProcess(pThis);
1811 return rc;
1812#else
1813 return VINF_IOM_R3_MMIO_WRITE;
1814#endif
1815}
1816
1817static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1818{
1819 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CBL, iReg);
1820 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1821
1822 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32Value));
1823
1824 return hdaRegWriteU32(pThis, iReg, u32Value);
1825}
1826
1827static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1828{
1829 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1830 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1831 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1832 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1833
1834 uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1835
1836 PHDASTREAM pStrmSt;
1837 switch (u8Strm)
1838 {
1839 case 0: /** @todo Use dynamic indices, based on stream assignment. */
1840 {
1841 pStrmSt = &pThis->StrmStLineIn;
1842 break;
1843 }
1844# ifdef VBOX_WITH_HDA_MIC_IN
1845 case 2: /** @todo Use dynamic indices, based on stream assignment. */
1846 {
1847 pStrmSt = &pThis->StrmStMicIn;
1848 break;
1849 }
1850# endif
1851 case 4: /** @todo Use dynamic indices, based on stream assignment. */
1852 {
1853 pStrmSt = &pThis->StrmStOut;
1854 break;
1855 }
1856
1857 default:
1858 {
1859 LogFunc(("Warning: Changing SDCTL on non-attached stream (iReg=0x%x)\n", iReg));
1860 return hdaRegWriteU24(pThis, iReg, u32Value); /* Write 3 bytes. */
1861 }
1862 }
1863
1864 LogFunc(("[SD%RU8]: %R[sdctl]\n", u8Strm, u32Value));
1865
1866 if (fInReset)
1867 {
1868 /* Guest is resetting HDA's stream, we're expecting guest will mark stream as exit. */
1869 Assert(!fReset);
1870 LogFunc(("Guest initiated exit of stream reset\n"));
1871 }
1872 else if (fReset)
1873 {
1874#ifdef IN_RING3
1875 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1876 Assert(!fInRun && !fRun);
1877
1878 LogFunc(("Guest initiated enter to stream reset\n"));
1879 hdaStreamReset(pThis, pStrmSt, u8Strm);
1880#else
1881 return VINF_IOM_R3_MMIO_WRITE;
1882#endif
1883 }
1884 else
1885 {
1886#ifdef IN_RING3
1887 /*
1888 * We enter here to change DMA states only.
1889 */
1890 if (fInRun != fRun)
1891 {
1892 Assert(!fReset && !fInReset);
1893
1894 PHDADRIVER pDrv;
1895 switch (u8Strm)
1896 {
1897 case 0: /** @todo Use a variable here. Later. */
1898 {
1899 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1900 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1901 pDrv->LineIn.pStrmIn, fRun);
1902 break;
1903 }
1904# ifdef VBOX_WITH_HDA_MIC_IN
1905 case 2: /** @todo Use a variable here. Later. */
1906 {
1907 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1908 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1909 pDrv->MicIn.pStrmIn, fRun);
1910 break;
1911 }
1912# endif
1913 case 4: /** @todo Use a variable here. Later. */
1914 {
1915 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1916 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1917 pDrv->Out.pStrmOut, fRun);
1918 break;
1919 }
1920 default:
1921 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1922 break;
1923 }
1924 }
1925
1926 if (pStrmSt)
1927 {
1928 int rc2 = hdaStreamInit(pThis, pStrmSt, u8Strm);
1929 AssertRC(rc2);
1930 }
1931
1932#else /* !IN_RING3 */
1933 return VINF_IOM_R3_MMIO_WRITE;
1934#endif /* IN_RING3 */
1935 }
1936
1937 return hdaRegWriteU24(pThis, iReg, u32Value);
1938}
1939
1940static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1941{
1942 uint32_t v = HDA_REG_IND(pThis, iReg);
1943 v &= ~(u32Value & v);
1944 HDA_REG_IND(pThis, iReg) = v;
1945 hdaProcessInterrupt(pThis);
1946 return VINF_SUCCESS;
1947}
1948
1949static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1950{
1951 /* Only can be modified if RUN bit is 0. */
1952 bool fIsRunning = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1953 if (fIsRunning)
1954 {
1955 AssertMsgFailed(("Cannot write to register when RUN bit is set\n"));
1956 return VINF_SUCCESS;
1957 }
1958
1959 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1960 if (RT_FAILURE(rc))
1961 AssertRCReturn(rc, VINF_SUCCESS);
1962 return rc;
1963}
1964
1965static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1966{
1967 switch (u32Value)
1968 {
1969 case HDA_SDFIFOW_8B:
1970 case HDA_SDFIFOW_16B:
1971 case HDA_SDFIFOW_32B:
1972 return hdaRegWriteU16(pThis, iReg, u32Value);
1973 default:
1974 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1975 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1976 }
1977 return VINF_SUCCESS; /* Never reached. */
1978}
1979
1980/**
1981 * @note This method could be called for changing value on Output Streams
1982 * only (ICH6 datasheet 18.2.39).
1983 */
1984static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1985{
1986 /** @todo Only allow updating FIFOS if RUN bit is 0? */
1987 uint32_t u32FIFOS = 0;
1988
1989 switch (iReg)
1990 {
1991 /* SDInFIFOS is RO, n=0-3. */
1992 case HDA_REG_SD0FIFOS:
1993 case HDA_REG_SD1FIFOS:
1994 case HDA_REG_SD2FIFOS:
1995 case HDA_REG_SD3FIFOS:
1996 {
1997 LogFunc(("Guest tries to change R/O value of FIFO size of input stream, ignoring\n"));
1998 break;
1999 }
2000 case HDA_REG_SD4FIFOS:
2001 case HDA_REG_SD5FIFOS:
2002 case HDA_REG_SD6FIFOS:
2003 case HDA_REG_SD7FIFOS:
2004 {
2005 switch(u32Value)
2006 {
2007 case HDA_SDONFIFO_16B:
2008 case HDA_SDONFIFO_32B:
2009 case HDA_SDONFIFO_64B:
2010 case HDA_SDONFIFO_128B:
2011 case HDA_SDONFIFO_192B:
2012 u32FIFOS = u32Value;
2013 break;
2014
2015 case HDA_SDONFIFO_256B: /** @todo r=andy Investigate this. */
2016 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
2017 /* Fall through is intentional. */
2018 default:
2019 u32FIFOS = HDA_SDONFIFO_192B;
2020 break;
2021 }
2022
2023 break;
2024 }
2025 default:
2026 {
2027 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
2028 break;
2029 }
2030 }
2031
2032 if (u32FIFOS)
2033 {
2034 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", 0, hdaSDFIFOSToBytes(u32FIFOS)));
2035 /** @todo Update internal stream state with new FIFOS. */
2036
2037 return hdaRegWriteU16(pThis, iReg, u32FIFOS);
2038 }
2039
2040 return VINF_SUCCESS;
2041}
2042
2043#ifdef IN_RING3
2044static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
2045{
2046 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2047
2048# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2049
2050 int rc = VINF_SUCCESS;
2051
2052 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
2053 uint32_t u32HzMult = 1;
2054 uint32_t u32HzDiv = 1;
2055
2056 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2057 {
2058 case 0: u32HzMult = 1; break;
2059 case 1: u32HzMult = 2; break;
2060 case 2: u32HzMult = 3; break;
2061 case 3: u32HzMult = 4; break;
2062 default:
2063 LogFunc(("Unsupported multiplier %x\n",
2064 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2065 rc = VERR_NOT_SUPPORTED;
2066 break;
2067 }
2068 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2069 {
2070 case 0: u32HzDiv = 1; break;
2071 case 1: u32HzDiv = 2; break;
2072 case 2: u32HzDiv = 3; break;
2073 case 3: u32HzDiv = 4; break;
2074 case 4: u32HzDiv = 5; break;
2075 case 5: u32HzDiv = 6; break;
2076 case 6: u32HzDiv = 7; break;
2077 case 7: u32HzDiv = 8; break;
2078 default:
2079 LogFunc(("Unsupported divisor %x\n",
2080 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2081 rc = VERR_NOT_SUPPORTED;
2082 break;
2083 }
2084
2085 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
2086 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2087 {
2088 case 0:
2089 LogFunc(("Requested 8-bit\n"));
2090 enmFmt = AUD_FMT_S8;
2091 break;
2092 case 1:
2093 LogFunc(("Requested 16-bit\n"));
2094 enmFmt = AUD_FMT_S16;
2095 break;
2096 case 2:
2097 LogFunc(("Requested 20-bit\n"));
2098 break;
2099 case 3:
2100 LogFunc(("Requested 24-bit\n"));
2101 break;
2102 case 4:
2103 LogFunc(("Requested 32-bit\n"));
2104 enmFmt = AUD_FMT_S32;
2105 break;
2106 default:
2107 AssertMsgFailed(("Unsupported bits shift %x\n",
2108 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2109 rc = VERR_NOT_SUPPORTED;
2110 break;
2111 }
2112
2113 if (RT_SUCCESS(rc))
2114 {
2115 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2116 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
2117 pCfg->enmFormat = enmFmt;
2118 pCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2119 }
2120
2121# undef EXTRACT_VALUE
2122
2123 LogFlowFuncLeaveRC(rc);
2124 return rc;
2125}
2126#endif
2127
2128static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2129{
2130#ifdef IN_RING3
2131# ifdef VBOX_WITH_HDA_CODEC_EMU
2132 /* No reason to reopen voice with same settings. */
2133 if (u32Value == HDA_REG_IND(pThis, iReg))
2134 return VINF_SUCCESS;
2135
2136 PDMAUDIOSTREAMCFG as;
2137 int rc = hdaSdFmtToAudSettings(u32Value, &as);
2138 if (RT_FAILURE(rc))
2139 return rc;
2140
2141 PHDADRIVER pDrv;
2142 switch (iReg)
2143 {
2144 case HDA_REG_SD0FMT:
2145 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2146 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &as);
2147 break;
2148# ifdef VBOX_WITH_HDA_MIC_IN
2149 case HDA_REG_SD2FMT:
2150 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2151 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &as);
2152 break;
2153# endif
2154 default:
2155 LogFunc(("Warning: Attempt to change format on register %d\n", iReg));
2156 break;
2157 }
2158
2159 /** @todo r=andy rc gets lost; needs fixing. */
2160 return hdaRegWriteU16(pThis, iReg, u32Value);
2161# else /* !VBOX_WITH_HDA_CODEC_EMU */
2162 return hdaRegWriteU16(pThis, iReg, u32Value);
2163# endif
2164#else /* !IN_RING3 */
2165 return VINF_IOM_R3_MMIO_WRITE;
2166#endif
2167}
2168
2169static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2170{
2171 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2172 if (RT_FAILURE(rc))
2173 AssertRCReturn(rc, VINF_SUCCESS);
2174 return rc;
2175}
2176
2177static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2178{
2179 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2180 if (RT_FAILURE(rc))
2181 AssertRCReturn(rc, VINF_SUCCESS);
2182 return rc;
2183}
2184
2185static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2186{
2187 int rc = VINF_SUCCESS;
2188 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2189 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2190 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2191 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2192
2193 rc = hdaRegReadU32(pThis, iReg, pu32Value);
2194 return rc;
2195}
2196
2197static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2198{
2199 int rc = VINF_SUCCESS;
2200
2201 /*
2202 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2203 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2204 */
2205 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
2206 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
2207 {
2208#ifdef IN_RING3
2209 PFNHDACODECVERBPROCESSOR pfn = NULL;
2210 uint64_t resp;
2211 uint32_t cmd = HDA_REG(pThis, IC);
2212 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2213 {
2214 /*
2215 * 3.4.3 defines behavior of immediate Command status register.
2216 */
2217 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
2218 return rc;
2219 }
2220 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2221 LogFunc(("IC:%x\n", cmd));
2222
2223 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
2224 HDA_CODEC_CMD(cmd, 0 /* LUN */),
2225 &pfn);
2226 if (RT_FAILURE(rc))
2227 AssertRCReturn(rc, rc);
2228 rc = pfn(pThis->pCodec,
2229 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
2230 if (RT_FAILURE(rc))
2231 AssertRCReturn(rc, rc);
2232
2233 HDA_REG(pThis, IR) = (uint32_t)resp;
2234 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
2235 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
2236 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
2237#else /* !IN_RING3 */
2238 rc = VINF_IOM_R3_MMIO_WRITE;
2239#endif
2240 return rc;
2241 }
2242 /*
2243 * Once the guest read the response, it should clean the IRV bit of the IRS register.
2244 */
2245 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
2246 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
2247 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
2248 return rc;
2249}
2250
2251static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2252{
2253 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
2254 {
2255 HDA_REG(pThis, RIRBWP) = 0;
2256 }
2257 /* The remaining bits are O, see 6.2.22 */
2258 return VINF_SUCCESS;
2259}
2260
2261static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2262{
2263 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2264 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2265 if (RT_FAILURE(rc))
2266 AssertRCReturn(rc, rc);
2267
2268 switch(iReg)
2269 {
2270 case HDA_REG_CORBLBASE:
2271 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2272 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
2273 break;
2274 case HDA_REG_CORBUBASE:
2275 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2276 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2277 break;
2278 case HDA_REG_RIRBLBASE:
2279 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2280 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
2281 break;
2282 case HDA_REG_RIRBUBASE:
2283 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2284 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2285 break;
2286 case HDA_REG_DPLBASE:
2287 /** @todo: first bit has special meaning */
2288 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
2289 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
2290 break;
2291 case HDA_REG_DPUBASE:
2292 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
2293 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2294 break;
2295 default:
2296 AssertMsgFailed(("Invalid index"));
2297 break;
2298 }
2299
2300 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2301 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2302 return rc;
2303}
2304
2305static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2306{
2307 uint8_t v = HDA_REG(pThis, RIRBSTS);
2308 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2309
2310 return hdaProcessInterrupt(pThis);
2311}
2312
2313#ifdef IN_RING3
2314#ifdef LOG_ENABLED
2315static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE)
2316{
2317 uint32_t cbBDLE = 0;
2318
2319 for (uint16_t i = 0; i < cBDLE; i++)
2320 {
2321 uint8_t bdle[16]; /** @todo Use a define. */
2322 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * 16, bdle, 16); /** @todo Use a define. */
2323
2324 uint64_t addr = *(uint64_t *)bdle;
2325 uint32_t len = *(uint32_t *)&bdle[8];
2326 uint32_t ioc = *(uint32_t *)&bdle[12];
2327
2328 LogFlowFunc(("#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
2329 i, addr, len, RT_BOOL(ioc & 0x1)));
2330
2331 cbBDLE += len;
2332 }
2333
2334 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
2335
2336 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
2337 return;
2338
2339 for (int i = 0; i < 8; i++) /** @todo Use a define. */
2340 {
2341 uint32_t uDMACnt;
2342 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i * 8, /** @todo Use a define. */
2343 &uDMACnt, sizeof(&uDMACnt));
2344
2345 LogFlowFunc(("%s #%02d STREAM(0x%x)\n",
2346 i == HDA_SDCTL_NUM(pThis, 4) || i == HDA_SDCTL_NUM(pThis, 0) ? "*" : " ", i , uDMACnt));
2347 }
2348}
2349#endif
2350
2351/**
2352 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
2353 *
2354 * @param pThis Pointer to HDA state.
2355 * @param pBDLE Where to store the fetched result.
2356 * @param u64BaseDMA Address base of DMA engine to use.
2357 * @param u16Entry BDLE entry to fetch.
2358 */
2359static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
2360{
2361 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2362 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
2363 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
2364 /** @todo Compare u16Entry with LVI. */
2365
2366 uint8_t uBundleEntry[16]; /** @todo Define a BDLE length. */
2367 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * 16, /** @todo Define a BDLE length. */
2368 uBundleEntry, RT_ELEMENTS(uBundleEntry));
2369 if (RT_FAILURE(rc))
2370 return rc;
2371
2372 pBDLE->State.u32BDLIndex = u16Entry;
2373 pBDLE->u64BufAdr = *(uint64_t *) uBundleEntry;
2374 pBDLE->u32BufSize = *(uint32_t *)&uBundleEntry[8];
2375 if (pBDLE->u32BufSize < sizeof(uint16_t)) /* Must be at least one word. */
2376 return VERR_INVALID_STATE;
2377
2378 pBDLE->fIntOnCompletion = (*(uint32_t *)&uBundleEntry[12]) & 0x1;
2379
2380 return VINF_SUCCESS;
2381}
2382
2383static void hdaBDLEReset(PHDABDLE pBDLE)
2384{
2385 AssertPtrReturnVoid(pBDLE);
2386
2387 pBDLE->State.u32BufOff = 0;
2388 pBDLE->State.cbBelowFIFOW = 0;
2389}
2390
2391/**
2392 * Returns the number of outstanding stream data bytes which need to be processed
2393 * by the DMA engine assigned to this stream.
2394 *
2395 * @return Number of bytes for the DMA engine to process.
2396 */
2397DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStrmSt)
2398{
2399 AssertPtrReturn(pThis, 0);
2400 AssertPtrReturn(pStrmSt, 0);
2401
2402 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2403
2404 uint32_t cbFree = pStrmSt->u32CBL - HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2405 if (cbFree)
2406 {
2407 /* Limit to the available free space of the current BDLE. */
2408 cbFree = RT_MIN(cbFree, pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2409
2410 /* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
2411 cbFree = RT_MIN(cbFree, pStrmSt->u16FIFOS);
2412
2413 if (pBDLE->State.cbBelowFIFOW)
2414 {
2415 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
2416 * No need to read data from DMA then. */
2417 if (cbFree > pBDLE->State.cbBelowFIFOW)
2418 {
2419 /* Subtract the amount of bytes that still would fit in the stream's FIFO
2420 * and therefore do not need to be processed by DMA. */
2421 cbFree -= pBDLE->State.cbBelowFIFOW;
2422 }
2423 }
2424
2425 Log(("HDADEBUG: cb2Copy=%RU32, CVI(len:%RU32, pos:%RU32), CBLL=%RU32, FIFOS=%RU32, Avail=%RU32\n",
2426 cbFree, pBDLE->u32BufSize, pBDLE->State.u32BufOff, pStrmSt->u32CBL - HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), pStrmSt->u16FIFOS, 0));
2427 }
2428
2429 LogFlowFunc(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, cbFree=%RU32, %R[bdle]\n", pStrmSt->u8Strm,
2430 pStrmSt->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), cbFree, pBDLE));
2431 return cbFree;
2432}
2433
2434DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
2435{
2436 AssertPtrReturnVoid(pBDLE);
2437
2438 if (!cbData || !cbProcessed)
2439 return;
2440
2441 /* Fewer than cbBelowFIFOW bytes were copied.
2442 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2443 * where it might happen. */
2444 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
2445 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
2446 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
2447
2448#if 0
2449 if ( pBDLE->State.cbBelowFIFOW
2450 && pBDLE->State.cbBelowFIFOW <= cbWritten)
2451 {
2452 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
2453 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->u32BufSize));
2454 }
2455#endif
2456
2457 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
2458 Assert(pBDLE->State.cbBelowFIFOW == 0);
2459
2460 /* We always increment the position of DMA buffer counter because we're always reading
2461 * into an intermediate buffer. */
2462 pBDLE->State.u32BufOff += cbData;
2463 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2464
2465 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
2466}
2467
2468DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
2469{
2470 AssertPtrReturn(pThis, false);
2471 AssertPtrReturn(pStrmSt, false);
2472
2473 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2474 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2475
2476 /* Did we reach the CBL (Cyclic Buffer List) limit? */
2477 bool fCBLLimitReached = u32LPIB >= pStrmSt->u32CBL;
2478
2479 /* Do we need to use the next BDLE entry? Either because we reached
2480 * the CBL limit or our internal DMA buffer is full. */
2481 bool fNeedsNextBDLE = ( fCBLLimitReached
2482 || pBDLE->State.u32BufOff >= pBDLE->u32BufSize);
2483
2484 Assert(u32LPIB <= pStrmSt->u32CBL);
2485 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2486
2487 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
2488 pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
2489
2490 if (fCBLLimitReached)
2491 {
2492 /* Reset LPIB register. */
2493 u32LPIB -= RT_MIN(u32LPIB, pStrmSt->u32CBL);
2494 hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2495 }
2496
2497 if (fNeedsNextBDLE)
2498 {
2499 /* Reset current BDLE. */
2500 hdaBDLEReset(pBDLE);
2501 }
2502
2503 return fNeedsNextBDLE;
2504}
2505
2506DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbInc)
2507{
2508 AssertPtrReturnVoid(pThis);
2509 AssertPtrReturnVoid(pStrmSt);
2510
2511 LogFlowFunc(("[SD%RU8]: cbInc=%RU32\n", pStrmSt->u8Strm, cbInc));
2512
2513 Assert(cbInc <= pStrmSt->u16FIFOS);
2514
2515 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2516
2517 /*
2518 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
2519 * doesn't fetch anything via DMA, so just update LPIB.
2520 * (ICH6 datasheet 18.2.38).
2521 */
2522 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
2523 {
2524 const uint32_t u32LPIB = RT_MIN(HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2525 pStrmSt->u32CBL);
2526
2527 LogFlowFunc(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
2528 pStrmSt->u8Strm,
2529 HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2530 pStrmSt->u32CBL));
2531
2532 hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2533 }
2534}
2535
2536static bool hdaStreamTransferIsComplete(PHDASTATE pThis, PHDASTREAM pStrmSt)
2537{
2538 AssertPtrReturn(pThis, true);
2539 AssertPtrReturn(pStrmSt, true);
2540
2541 bool fIsComplete = false;
2542
2543 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2544 const uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2545
2546 if ( pBDLE->State.u32BufOff >= pBDLE->u32BufSize
2547 || u32LPIB >= pStrmSt->u32CBL)
2548 {
2549 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2550 Assert(u32LPIB <= pStrmSt->u32CBL);
2551
2552 if (/* IOC (Interrupt On Completion) bit set? */
2553 pBDLE->fIntOnCompletion
2554 /* All data put into the DMA FIFO? */
2555 && pBDLE->State.cbBelowFIFOW == 0
2556 )
2557 {
2558 /**
2559 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
2560 * last byte of data for the current descriptor has been fetched
2561 * from memory and put into the DMA FIFO.
2562 *
2563 ** @todo More carefully investigate BCIS flag.
2564 *
2565 * Speech synthesis works fine on Mac Guest if this bit isn't set
2566 * but in general sound quality gets worse.
2567 */
2568 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2569
2570 /*
2571 * If the ICE (IOCE, "Interrupt On Completion Enable") bit of the SDCTL register is set
2572 * we need to generate an interrupt.
2573 */
2574 if (HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2575 hdaProcessInterrupt(pThis);
2576 }
2577
2578 fIsComplete = true;
2579 }
2580
2581 LogFlowFunc(("[SD%RU8]: u32LPIB=%RU32, CBL=%RU32, %R[bdle] => %s\n",
2582 pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, pBDLE, fIsComplete ? "COMPLETE" : "INCOMPLETE"));
2583
2584 return fIsComplete;
2585}
2586
2587/**
2588 * hdaReadAudio - copies samples from audio backend to DMA.
2589 * Note: This function writes to the DMA buffer immediately,
2590 * but "reports bytes" when all conditions are met (FIFOW).
2591 */
2592static int hdaReadAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, PAUDMIXSINK pSink, uint32_t *pcbRead)
2593{
2594 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2595 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2596 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
2597 /* pcbRead is optional. */
2598
2599 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2600
2601 int rc;
2602 uint32_t cbRead = 0;
2603 uint32_t cbBuf = hdaStreamGetTransferSize(pThis, pStrmSt);
2604
2605 LogFlowFunc(("cbBuf=%RU32, %R[bdle]\n", cbBuf, pBDLE));
2606
2607 if (!cbBuf)
2608 {
2609 /* Nothing to write, bail out. */
2610 rc = VERR_NO_DATA;
2611 }
2612 else
2613 {
2614 uint32_t cbReadFromSink = 0;
2615 rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pBDLE->State.au8FIFO, cbBuf, &cbReadFromSink);
2616 if (RT_SUCCESS(rc))
2617 {
2618 Assert(cbReadFromSink);
2619 Assert(cbReadFromSink == cbBuf);
2620 Assert(cbReadFromSink <= pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2621
2622 /*
2623 * Write to the BDLE's DMA buffer.
2624 */
2625 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2626 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2627 pBDLE->State.au8FIFO, cbReadFromSink);
2628 AssertRC(rc);
2629
2630 if (pBDLE->State.cbBelowFIFOW + cbReadFromSink > hdaStreamGetFIFOW(pThis, pStrmSt))
2631 {
2632 pBDLE->State.u32BufOff += cbReadFromSink;
2633 pBDLE->State.cbBelowFIFOW = 0;
2634 //hdaBackendReadTransferReported(pBDLE, cbDMAData, cbRead, &cbRead, pcbAvail);
2635 }
2636 else
2637 {
2638 pBDLE->State.u32BufOff += cbReadFromSink;
2639 pBDLE->State.cbBelowFIFOW += cbReadFromSink;
2640 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2641 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbRead, pcbAvail);
2642
2643 rc = VERR_NO_DATA;
2644 }
2645 }
2646 }
2647
2648 //Assert(cbRead <= (SDFIFOS(pThis, pStrmSt->u8Strm) + 1));
2649
2650 LogFunc(("BDLE(off:%RU32, size:%RU32), cbTransferred=%RU32, rc=%Rrc\n",
2651 pBDLE->State.u32BufOff, pBDLE->u32BufSize, cbRead, rc));
2652
2653 if (RT_SUCCESS(rc))
2654 {
2655 if (pcbRead)
2656 *pcbRead = cbRead;
2657 }
2658
2659 return rc;
2660}
2661
2662static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t *pcbWritten)
2663{
2664 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2665 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2666 AssertPtrReturn(pcbWritten, VERR_INVALID_POINTER);
2667 /* pcbWritten is optional. */
2668
2669 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2670 int rc;
2671
2672 uint32_t cbWritten = 0;
2673 uint32_t cbData = hdaStreamGetTransferSize(pThis, pStrmSt);
2674
2675 LogFlowFunc(("cbData=%RU32, %R[bdle]\n", cbData, pBDLE));
2676
2677 /*
2678 * Copy from DMA to the corresponding stream buffer (if there are any bytes from the
2679 * previous unreported transfer we write at offset 'pBDLE->State.cbUnderFifoW').
2680 */
2681 if (!cbData)
2682 {
2683 rc = VINF_EOF;
2684 }
2685 else
2686 {
2687 /*
2688 * Read from the current BDLE's DMA buffer.
2689 */
2690 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2691 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2692 pBDLE->State.au8FIFO + pBDLE->State.cbBelowFIFOW, cbData);
2693 AssertRC(rc);
2694
2695#ifdef VBOX_WITH_STATISTICS
2696 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbData);
2697#endif
2698 /*
2699 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2700 */
2701 uint32_t cbToWrite = cbData + pBDLE->State.cbBelowFIFOW;
2702 if (cbToWrite >= hdaStreamGetFIFOW(pThis, pStrmSt))
2703 {
2704 uint32_t cbWrittenToStream;
2705 int rc2;
2706
2707 PHDADRIVER pDrv;
2708 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2709 {
2710 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2711 {
2712 rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2713 pBDLE->State.au8FIFO, cbToWrite, &cbWrittenToStream);
2714 if (RT_SUCCESS(rc2))
2715 {
2716 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2717 LogFlowFunc(("\tLUN#%RU8: Warning: Only written %RU32 / %RU32 bytes, expect lags\n",
2718 pDrv->uLUN, cbWrittenToStream, cbToWrite));
2719 }
2720 }
2721 else /* Stream disabled, not fatal. */
2722 {
2723 cbWrittenToStream = 0;
2724 rc2 = VERR_NOT_AVAILABLE;
2725 /* Keep going. */
2726 }
2727
2728 LogFlowFunc(("\tLUN#%RU8: cbToWrite=%RU32, cbWrittenToStream=%RU32, rc=%Rrc\n",
2729 pDrv->uLUN, cbToWrite, cbWrittenToStream, rc2));
2730 }
2731
2732 /* Always report all data as being written;
2733 * backends who were not able to catch up have to deal with it themselves. */
2734 cbWritten = cbToWrite;
2735
2736 hdaBDLEUpdate(pBDLE, cbData, cbWritten);
2737 }
2738 else
2739 {
2740 pBDLE->State.u32BufOff += cbWritten;
2741 pBDLE->State.cbBelowFIFOW += cbWritten;
2742 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2743
2744 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2745 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbAvail, NULL);
2746 rc = VINF_EOF;
2747 }
2748 }
2749
2750 Assert(cbWritten <= pStrmSt->u16FIFOS);
2751
2752 if (RT_SUCCESS(rc))
2753 {
2754 if (pcbWritten)
2755 *pcbWritten = cbWritten;
2756 }
2757
2758 LogFunc(("Returning cbWritten=%RU32, rc=%Rrc\n", cbWritten, rc));
2759 return rc;
2760}
2761
2762/**
2763 * @interface_method_impl{HDACODEC,pfnReset}
2764 */
2765static DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2766{
2767 PHDASTATE pThis = pCodec->pHDAState;
2768 NOREF(pThis);
2769 return VINF_SUCCESS;
2770}
2771
2772
2773static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2774{
2775 NOREF(pThis);
2776 NOREF(enmRecSource);
2777 LogFlowFuncEnter();
2778}
2779
2780static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2781{
2782 NOREF(pThis);
2783 LogFlowFuncEnter();
2784}
2785
2786static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2787 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2788 PPDMAUDIOSTREAMCFG pCfg)
2789{
2790 PAUDMIXSINK pSink;
2791
2792 switch (enmRecSource)
2793 {
2794# ifdef VBOX_WITH_HDA_MIC_IN
2795 case PDMAUDIORECSOURCE_MIC:
2796 pSink = pThis->pSinkMicIn;
2797 break;
2798# endif
2799 case PDMAUDIORECSOURCE_LINE_IN:
2800 pSink = pThis->pSinkLineIn;
2801 break;
2802 default:
2803 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2804 return VERR_NOT_SUPPORTED;
2805 }
2806
2807 int rc = VINF_SUCCESS;
2808 char *pszDesc;
2809
2810 PHDADRIVER pDrv;
2811 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2812 {
2813 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2814 {
2815 rc = VERR_NO_MEMORY;
2816 break;
2817 }
2818
2819 rc = pDrv->pConnector->pfnCreateIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2820 LogFlowFunc(("LUN#%RU8: Created input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2821 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2822 {
2823 AudioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2824 rc = AudioMixerAddStreamIn(pSink,
2825 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2826 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2827 }
2828
2829 RTStrFree(pszDesc);
2830 }
2831
2832 LogFlowFuncLeaveRC(rc);
2833 return rc;
2834}
2835
2836static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2837 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2838{
2839 int rc = VINF_SUCCESS;
2840 char *pszDesc;
2841
2842 PHDADRIVER pDrv;
2843 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2844 {
2845 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2846 {
2847 rc = VERR_NO_MEMORY;
2848 break;
2849 }
2850
2851 rc = pDrv->pConnector->pfnCreateOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
2852 LogFlowFunc(("LUN#%RU8: Created output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2853 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2854 {
2855 AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
2856 rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
2857 pDrv->pConnector, pDrv->Out.pStrmOut,
2858 0 /* uFlags */, &pDrv->Out.phStrmOut);
2859 }
2860
2861 RTStrFree(pszDesc);
2862 }
2863
2864 LogFlowFuncLeaveRC(rc);
2865 return rc;
2866}
2867
2868static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis, ENMSOUNDSOURCE enmSource,
2869 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2870{
2871 int rc = VINF_SUCCESS;
2872 PDMAUDIOVOLUME vol = { fMute, uVolLeft, uVolRight };
2873 PAUDMIXSINK pSink;
2874
2875 /* Convert the audio source to corresponding sink. */
2876 switch (enmSource)
2877 {
2878 case PO_INDEX:
2879 pSink = pThis->pSinkOutput;
2880 break;
2881 case PI_INDEX:
2882 pSink = pThis->pSinkLineIn;
2883 break;
2884 case MC_INDEX:
2885 pSink = pThis->pSinkMicIn;
2886 break;
2887 default:
2888 AssertFailedReturn(VERR_INVALID_PARAMETER);
2889 break;
2890 }
2891
2892 /* Set the volume. Codec already converted it to the correct range. */
2893 AudioMixerSetSinkVolume(pSink, &vol);
2894
2895 LogFlowFuncLeaveRC(rc);
2896 return rc;
2897}
2898
2899#ifndef VBOX_WITH_AUDIO_CALLBACKS
2900
2901static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2902{
2903 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2904 AssertPtr(pThis);
2905
2906 STAM_PROFILE_START(&pThis->StatTimer, a);
2907
2908 int rc = VINF_SUCCESS;
2909
2910 uint32_t cbInMax = 0;
2911 uint32_t cbOutMin = UINT32_MAX;
2912
2913 PHDADRIVER pDrv;
2914
2915 uint32_t cbIn, cbOut, cSamplesLive;
2916 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2917 {
2918 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2919 &cbIn, &cbOut, &cSamplesLive);
2920 if (RT_SUCCESS(rc))
2921 {
2922#ifdef DEBUG_TIMER
2923 LogFlowFunc(("\tLUN#%RU8: [1] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2924#endif
2925 if (cSamplesLive)
2926 {
2927 uint32_t cSamplesPlayed;
2928 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2929 if (RT_SUCCESS(rc2))
2930 LogFlowFunc(("LUN#%RU8: cSamplesLive=%RU32, cSamplesPlayed=%RU32\n",
2931 pDrv->uLUN, cSamplesLive, cSamplesPlayed));
2932
2933 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2934 &cbIn, &cbOut, &cSamplesLive);
2935#ifdef DEBUG_TIMER
2936 if (RT_SUCCESS(rc))
2937 LogFlowFunc(("\tLUN#%RU8: [2] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2938#endif
2939 }
2940
2941 cbInMax = RT_MAX(cbInMax, cbIn);
2942 cbOutMin = RT_MIN(cbOutMin, cbOut);
2943 }
2944 }
2945
2946#ifdef DEBUG_TIMER
2947 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
2948#endif
2949
2950 if (cbOutMin == UINT32_MAX)
2951 cbOutMin = 0;
2952
2953 /*
2954 * Playback.
2955 */
2956 if (cbOutMin)
2957 {
2958 Assert(cbOutMin != UINT32_MAX);
2959 hdaTransfer(pThis, PO_INDEX, NULL /* pcbProcessed */); /** @todo Add rc! */
2960 }
2961
2962 /*
2963 * Recording.
2964 */
2965 if (cbInMax)
2966 hdaTransfer(pThis, PI_INDEX, NULL /* pcbProcessed */); /** @todo Add rc! */
2967
2968 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
2969
2970 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2971}
2972
2973#else /* VBOX_WITH_AUDIO_CALLBACKS */
2974
2975static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
2976{
2977 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
2978 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
2979 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
2980 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
2981 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
2982
2983 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
2984 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
2985
2986 PPDMAUDIOCALLBACKDATAIN pData = (PPDMAUDIOCALLBACKDATAIN)pvUser;
2987 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAIN), VERR_INVALID_PARAMETER);
2988
2989 return hdaTransfer(pCtx->pThis, PI_INDEX, &pData->cbOutRead);
2990}
2991
2992static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
2993{
2994 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
2995 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
2996 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
2997 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
2998 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
2999
3000 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
3001 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
3002
3003 PPDMAUDIOCALLBACKDATAOUT pData = (PPDMAUDIOCALLBACKDATAOUT)pvUser;
3004 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAOUT), VERR_INVALID_PARAMETER);
3005
3006 PHDASTATE pThis = pCtx->pThis;
3007
3008 int rc = hdaTransfer(pCtx->pThis, PO_INDEX, &pData->cbOutWritten);
3009 if ( RT_SUCCESS(rc)
3010 && pData->cbOutWritten)
3011 {
3012 PHDADRIVER pDrv;
3013 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3014 {
3015 uint32_t cSamplesPlayed;
3016 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
3017 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
3018 }
3019 }
3020}
3021#endif /* VBOX_WITH_AUDIO_CALLBACKS */
3022
3023static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t *pcbProcessed)
3024{
3025 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3026 /* pcbProcessed is optional. */
3027
3028 LogFlowFunc(("enmSrc=%RU32\n", enmSrc));
3029
3030 PHDASTREAM pStrmSt;
3031 switch (enmSrc)
3032 {
3033 case PI_INDEX:
3034 {
3035 pStrmSt = &pThis->StrmStLineIn;
3036 break;
3037 }
3038
3039#ifdef VBOX_WITH_HDA_MIC_IN
3040 case MC_INDEX:
3041 {
3042 pStrmSt = &pThis->StrmStMicIn;
3043 break;
3044 }
3045#endif
3046 case PO_INDEX:
3047 {
3048 pStrmSt = &pThis->StrmStOut;
3049 break;
3050 }
3051
3052 default:
3053 {
3054 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
3055 return VERR_NOT_SUPPORTED;
3056 }
3057 }
3058
3059 if (pStrmSt->State.cBDLE == 0) /* No buffers available? */
3060 {
3061 LogFlowFunc(("[SD%RU8] No buffers available\n", pStrmSt->u8Strm));
3062
3063 if (pcbProcessed)
3064 *pcbProcessed = 0;
3065 return VINF_SUCCESS;
3066 }
3067 AssertPtr(pStrmSt->State.paBDLE);
3068
3069 /* Is this stream running? */
3070 const bool fIsRunning = RT_BOOL(HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3071 if (!fIsRunning)
3072 {
3073 LogFlowFunc(("[SD%RU8]: Stream not running\n", pStrmSt->u8Strm));
3074
3075 if (pcbProcessed)
3076 *pcbProcessed = 0;
3077 return VINF_SUCCESS;
3078 }
3079
3080 Assert(pStrmSt->u8Strm <= 7); /** @todo Use a define for MAX_STRAEMS! */
3081 Assert(pStrmSt->u64BaseDMA);
3082 Assert(pStrmSt->u32CBL);
3083
3084 int rc;
3085 uint32_t cbProcessedTotal = 0;
3086 bool fIsComplete = false;
3087
3088 do
3089 {
3090 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
3091 if (hdaStreamNeedsNextBDLE(pThis, pStrmSt))
3092 hdaStreamGetNextBDLE(pThis, pStrmSt);
3093
3094 /* Set the FIFORDY bit on the stream while doing the transfer. */
3095 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3096
3097 uint32_t cbProcessed;
3098 switch (enmSrc)
3099 {
3100 case PI_INDEX:
3101 rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkLineIn, &cbProcessed);
3102 break;
3103 case PO_INDEX:
3104 rc = hdaWriteAudio(pThis, pStrmSt, &cbProcessed);
3105 break;
3106#ifdef VBOX_WITH_HDA_MIC_IN
3107 case MC_INDEX:
3108 rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkMicIn, &cbProcessed);
3109 break;
3110#endif
3111 default:
3112 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
3113 rc = VERR_NOT_SUPPORTED;
3114 break;
3115 }
3116
3117 /* Remove the FIFORDY bit again. */
3118 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3119
3120 if (RT_FAILURE(rc))
3121 break;
3122
3123 hdaStreamTransferUpdate(pThis, pStrmSt, cbProcessed);
3124
3125 cbProcessedTotal += cbProcessed;
3126
3127 LogFlowFunc(("cbProcessed=%RU32, cbProcessedTotal=%RU32, rc=%Rrc\n", cbProcessed, cbProcessedTotal, rc));
3128
3129 if (rc == VINF_EOF)
3130 fIsComplete = true;
3131
3132 if (!fIsComplete)
3133 fIsComplete = hdaStreamTransferIsComplete(pThis, pStrmSt);
3134
3135 } while (!fIsComplete);
3136
3137 if (RT_SUCCESS(rc))
3138 {
3139 if (pcbProcessed)
3140 *pcbProcessed = cbProcessedTotal;
3141 }
3142
3143 LogFlowFuncLeaveRC(rc);
3144 return rc;
3145}
3146#endif /* IN_RING3 */
3147
3148/* MMIO callbacks */
3149
3150/**
3151 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3152 *
3153 * @note During implementation, we discovered so-called "forgotten" or "hole"
3154 * registers whose description is not listed in the RPM, datasheet, or
3155 * spec.
3156 */
3157PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3158{
3159 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3160 int rc;
3161
3162 /*
3163 * Look up and log.
3164 */
3165 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3166 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
3167#ifdef LOG_ENABLED
3168 unsigned const cbLog = cb;
3169 uint32_t offRegLog = offReg;
3170#endif
3171
3172 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
3173 Assert(cb == 4); Assert((offReg & 3) == 0);
3174
3175 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3176 LogFunc(("\tAccess to registers except GCTL is blocked while reset\n"));
3177
3178 if (idxRegDsc == -1)
3179 LogRel(("HDA: Invalid read access @0x%x (bytes=%d)\n", offReg, cb));
3180
3181 if (idxRegDsc != -1)
3182 {
3183 /* ASSUMES gapless DWORD at end of map. */
3184 if (g_aHdaRegMap[idxRegDsc].size == 4)
3185 {
3186 /*
3187 * Straight forward DWORD access.
3188 */
3189 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3190 LogFunc(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
3191 }
3192 else
3193 {
3194 /*
3195 * Multi register read (unless there are trailing gaps).
3196 * ASSUMES that only DWORD reads have sideeffects.
3197 */
3198 uint32_t u32Value = 0;
3199 unsigned cbLeft = 4;
3200 do
3201 {
3202 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3203 uint32_t u32Tmp = 0;
3204
3205 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3206 LogFunc(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3207 if (rc != VINF_SUCCESS)
3208 break;
3209 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3210
3211 cbLeft -= cbReg;
3212 offReg += cbReg;
3213 idxRegDsc++;
3214 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3215
3216 if (rc == VINF_SUCCESS)
3217 *(uint32_t *)pv = u32Value;
3218 else
3219 Assert(!IOM_SUCCESS(rc));
3220 }
3221 }
3222 else
3223 {
3224 rc = VINF_IOM_MMIO_UNUSED_FF;
3225 LogFunc(("\tHole at %x is accessed for read\n", offReg));
3226 }
3227
3228 /*
3229 * Log the outcome.
3230 */
3231#ifdef LOG_ENABLED
3232 if (cbLog == 4)
3233 LogFunc(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
3234 else if (cbLog == 2)
3235 LogFunc(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
3236 else if (cbLog == 1)
3237 LogFunc(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
3238#endif
3239 return rc;
3240}
3241
3242
3243DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3244{
3245 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3246 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
3247
3248 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3249#ifdef LOG_ENABLED
3250 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
3251#endif
3252 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3253 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3254 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
3255 return rc;
3256}
3257
3258
3259/**
3260 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3261 */
3262PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
3263{
3264 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3265 int rc;
3266
3267 /*
3268 * The behavior of accesses that aren't aligned on natural boundraries is
3269 * undefined. Just reject them outright.
3270 */
3271 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3272 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
3273 if (GCPhysAddr & (cb - 1))
3274 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3275
3276 /*
3277 * Look up and log the access.
3278 */
3279 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3280 int idxRegDsc = hdaRegLookup(pThis, offReg);
3281 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3282 uint64_t u64Value;
3283 if (cb == 4) u64Value = *(uint32_t const *)pv;
3284 else if (cb == 2) u64Value = *(uint16_t const *)pv;
3285 else if (cb == 1) u64Value = *(uint8_t const *)pv;
3286 else if (cb == 8) u64Value = *(uint64_t const *)pv;
3287 else
3288 {
3289 u64Value = 0; /* shut up gcc. */
3290 AssertReleaseMsgFailed(("%u\n", cb));
3291 }
3292
3293#ifdef LOG_ENABLED
3294 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3295 if (idxRegDsc == -1)
3296 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
3297 else if (cb == 4)
3298 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3299 else if (cb == 2)
3300 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3301 else if (cb == 1)
3302 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3303
3304 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3305 LogFunc(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3306#endif
3307
3308 /*
3309 * Try for a direct hit first.
3310 */
3311 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3312 {
3313 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3314#ifdef LOG_ENABLED
3315 LogFunc(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3316#endif
3317 }
3318 /*
3319 * Partial or multiple register access, loop thru the requested memory.
3320 */
3321 else
3322 {
3323 /*
3324 * If it's an access beyond the start of the register, shift the input
3325 * value and fill in missing bits. Natural alignment rules means we
3326 * will only see 1 or 2 byte accesses of this kind, so no risk of
3327 * shifting out input values.
3328 */
3329 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
3330 {
3331 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3332 offReg -= cbBefore;
3333 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3334 u64Value <<= cbBefore * 8;
3335 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3336 LogFunc(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3337 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3338 }
3339
3340 /* Loop thru the write area, it may cover multiple registers. */
3341 rc = VINF_SUCCESS;
3342 for (;;)
3343 {
3344 uint32_t cbReg;
3345 if (idxRegDsc != -1)
3346 {
3347 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3348 cbReg = g_aHdaRegMap[idxRegDsc].size;
3349 if (cb < cbReg)
3350 {
3351 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3352 LogFunc(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3353 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3354 }
3355 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
3356 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3357 LogFunc(("\t%#x -> %#x\n", u32LogOldVal, pThis->au32Regs[idxRegMem]));
3358 }
3359 else
3360 {
3361 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3362 cbReg = 1;
3363 }
3364 if (rc != VINF_SUCCESS)
3365 break;
3366 if (cbReg >= cb)
3367 break;
3368
3369 /* Advance. */
3370 offReg += cbReg;
3371 cb -= cbReg;
3372 u64Value >>= cbReg * 8;
3373 if (idxRegDsc == -1)
3374 idxRegDsc = hdaRegLookup(pThis, offReg);
3375 else
3376 {
3377 idxRegDsc++;
3378 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3379 || g_aHdaRegMap[idxRegDsc].offset != offReg)
3380 {
3381 idxRegDsc = -1;
3382 }
3383 }
3384 }
3385 }
3386
3387 return rc;
3388}
3389
3390
3391/* PCI callback. */
3392
3393#ifdef IN_RING3
3394/**
3395 * @callback_method_impl{FNPCIIOREGIONMAP}
3396 */
3397static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
3398 PCIADDRESSSPACE enmType)
3399{
3400 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3401 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3402 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3403 int rc;
3404
3405 /*
3406 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3407 *
3408 * Let IOM talk DWORDs when reading, saves a lot of complications. On
3409 * writing though, we have to do it all ourselves because of sideeffects.
3410 */
3411 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3412 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
3413 IOMMMIO_FLAGS_READ_DWORD
3414 | IOMMMIO_FLAGS_WRITE_PASSTHRU,
3415 hdaMMIOWrite, hdaMMIORead, "HDA");
3416
3417 if (RT_FAILURE(rc))
3418 return rc;
3419
3420 if (pThis->fR0Enabled)
3421 {
3422 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
3423 "hdaMMIOWrite", "hdaMMIORead");
3424 if (RT_FAILURE(rc))
3425 return rc;
3426 }
3427
3428 if (pThis->fRCEnabled)
3429 {
3430 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
3431 "hdaMMIOWrite", "hdaMMIORead");
3432 if (RT_FAILURE(rc))
3433 return rc;
3434 }
3435
3436 pThis->MMIOBaseAddr = GCPhysAddress;
3437 return VINF_SUCCESS;
3438}
3439
3440
3441/* Saved state callbacks. */
3442
3443static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
3444{
3445 /* Save stream ID. */
3446 int rc = SSMR3PutU8(pSSM, pStrm->u8Strm);
3447 AssertRCReturn(rc, rc);
3448 Assert(pStrm->u8Strm <= 7); /** @todo Use a define. */
3449
3450 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields5, NULL);
3451 AssertRCReturn(rc, rc);
3452
3453 for (uint32_t i = 0; i < pStrm->State.cBDLE; i++)
3454 {
3455 rc = SSMR3PutStructEx(pSSM, &pStrm->State.paBDLE[i], sizeof(HDABDLE), 0 /*fFlags*/, g_aSSMBDLEStateFields5, NULL);
3456 AssertRCReturn(rc, rc);
3457 }
3458
3459 return rc;
3460}
3461
3462/**
3463 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3464 */
3465static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3466{
3467 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3468
3469 /* Save Codec nodes states. */
3470 hdaCodecSaveState(pThis->pCodec, pSSM);
3471
3472 /* Save MMIO registers. */
3473 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3474 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3475 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3476
3477 /* Save number of streams. */
3478 SSMR3PutU32(pSSM, 3);
3479
3480 /* Save stream states. */
3481 int rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStOut);
3482 AssertRCReturn(rc, rc);
3483 rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStMicIn);
3484 AssertRCReturn(rc, rc);
3485 rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStLineIn);
3486 AssertRCReturn(rc, rc);
3487
3488 return rc;
3489}
3490
3491
3492/**
3493 * @callback_method_impl{FNSSMDEVLOADEXEC}
3494 */
3495static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3496{
3497 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3498
3499 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3500
3501 LogFlowFunc(("uVersion=%RU32, uPass=%RU32\n", uVersion, uPass));
3502
3503 /*
3504 * Load Codec nodes states.
3505 */
3506 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3507 if (RT_FAILURE(rc))
3508 return rc;
3509
3510 /*
3511 * Load MMIO registers.
3512 */
3513 uint32_t cRegs;
3514 switch (uVersion)
3515 {
3516 case HDA_SSM_VERSION_1:
3517 /* Starting with r71199, we would save 112 instead of 113
3518 registers due to some code cleanups. This only affected trunk
3519 builds in the 4.1 development period. */
3520 cRegs = 113;
3521 if (SSMR3HandleRevision(pSSM) >= 71199)
3522 {
3523 uint32_t uVer = SSMR3HandleVersion(pSSM);
3524 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3525 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3526 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3527 cRegs = 112;
3528 }
3529 break;
3530
3531 case HDA_SSM_VERSION_2:
3532 case HDA_SSM_VERSION_3:
3533 cRegs = 112;
3534 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3535 break;
3536
3537 /* Since version 4 we store the register count to stay flexible. */
3538 case HDA_SSM_VERSION_4:
3539 case HDA_SSM_VERSION:
3540 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3541 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3542 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3543 break;
3544
3545 default:
3546 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3547 }
3548
3549 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3550 {
3551 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3552 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3553 }
3554 else
3555 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3556
3557 /*
3558 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3559 * *every* BDLE state, whereas it only needs to be stored
3560 * *once* for every stream. Most of the BDLE state we can
3561 * get out of the registers anyway, so just ignore those values.
3562 *
3563 * Also, only the current BDLE was saved, regardless whether
3564 * there were more than one (and there are at least two entries,
3565 * according to the spec).
3566 */
3567#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3568 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3569 AssertRCReturn(rc, rc); \
3570 rc = SSMR3Skip(pSSM, sizeof(uint64_t)); /* u64BdleCviAddr */ \
3571 AssertRCReturn(rc, rc); \
3572 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3573 AssertRCReturn(rc, rc); \
3574 rc = SSMR3GetU32(pSSM, &x->u32BDLIndex); /* u32BdleCvi */ \
3575 AssertRCReturn(rc, rc); \
3576 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleCviLen */ \
3577 AssertRCReturn(rc, rc); \
3578 rc = SSMR3GetU32(pSSM, &x->u32BufOff); /* u32BdleCviPos */ \
3579 AssertRCReturn(rc, rc); \
3580 rc = SSMR3Skip(pSSM, sizeof(uint8_t)); /* fBdleCviIoc */ \
3581 AssertRCReturn(rc, rc); \
3582 rc = SSMR3GetU32(pSSM, &x->cbBelowFIFOW); /* cbUnderFifoW */ \
3583 AssertRCReturn(rc, rc); \
3584 rc = SSMR3GetMem(pSSM, &x->au8FIFO, sizeof(x->au8FIFO)); \
3585 AssertRCReturn(rc, rc); \
3586 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3587 AssertRCReturn(rc, rc); \
3588
3589 /*
3590 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3591 */
3592 HDABDLESTATE StateBDLEDummy;
3593
3594 switch (uVersion)
3595 {
3596 case HDA_SSM_VERSION_1:
3597 case HDA_SSM_VERSION_2:
3598 case HDA_SSM_VERSION_3:
3599 case HDA_SSM_VERSION_4:
3600 {
3601 /* Only load the internal states.
3602 * The rest will be initialized from the saved registers later. */
3603
3604 /* Note: Only the *current* BDLE for a stream was saved! */
3605
3606 /* Output */
3607 rc = hdaStreamInit(pThis, &pThis->StrmStOut, 4 /* Stream number, hardcoded */);
3608 AssertRCBreak(rc);
3609 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStOut.State.cBDLE
3610 ? &pThis->StrmStOut.State.paBDLE[0].State : &StateBDLEDummy));
3611 /* Microphone-In */
3612 rc = hdaStreamInit(pThis, &pThis->StrmStMicIn, 2 /* Stream number, hardcoded */);
3613 AssertRCBreak(rc);
3614 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStMicIn.State.cBDLE
3615 ? &pThis->StrmStMicIn.State.paBDLE[0].State : &StateBDLEDummy));
3616 /* Line-In */
3617 rc = hdaStreamInit(pThis, &pThis->StrmStLineIn, 0 /* Stream number, hardcoded */);
3618 AssertRCBreak(rc);
3619 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStLineIn.State.cBDLE
3620 ? &pThis->StrmStLineIn.State.paBDLE[0].State : &StateBDLEDummy));
3621 break;
3622 }
3623
3624 /* Since v5 we support flexible stream and BDLE counts. */
3625 case HDA_SSM_VERSION:
3626 {
3627 uint32_t cStreams;
3628 rc = SSMR3GetU32(pSSM, &cStreams);
3629 AssertRCBreak(rc);
3630
3631 /* Load stream states. */
3632 for (uint32_t i = 0; i < cStreams; i++)
3633 {
3634 uint8_t uStreamID;
3635 rc = SSMR3GetU8(pSSM, &uStreamID);
3636 AssertRCBreak(rc);
3637
3638 PHDASTREAM pStrm;
3639 HDASTREAM StreamDummy;
3640
3641 switch (uStreamID)
3642 {
3643 case 0: /** @todo Use a define. */
3644 pStrm = &pThis->StrmStLineIn;
3645 break;
3646
3647 case 2: /** @todo Use a define. */
3648 pStrm = &pThis->StrmStMicIn;
3649 break;
3650
3651 case 4: /** @todo Use a define. */
3652 pStrm = &pThis->StrmStOut;
3653 break;
3654
3655 default:
3656 pStrm = &StreamDummy;
3657 break;
3658 }
3659
3660 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /* fFlags */, g_aSSMStreamStateFields5, NULL);
3661 AssertRCBreak(rc);
3662
3663 rc = hdaStreamInit(pThis, pStrm, uStreamID);
3664 AssertRCBreak(rc);
3665
3666 /* Load BDLE states. */
3667 for (uint32_t a = 0; a < pStrm->State.cBDLE; a++)
3668 {
3669 rc = SSMR3GetStructEx(pSSM, &pStrm->State.paBDLE[a].State, sizeof(HDABDLESTATE),
3670 0 /* fFlags */, g_aSSMBDLEStateFields5, NULL);
3671 AssertRCBreak(rc);
3672 }
3673
3674 /* Destroy dummy again. */
3675 if (pStrm == &StreamDummy)
3676 hdaStreamDestroy(pStrm);
3677 }
3678 break;
3679 }
3680
3681 default:
3682 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3683 }
3684
3685#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3686
3687 if (RT_SUCCESS(rc))
3688 {
3689 /*
3690 * Update stuff after the state changes.
3691 */
3692 bool fEnableIn = RT_BOOL(HDA_SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3693#ifdef VBOX_WITH_HDA_MIC_IN
3694 bool fEnableMicIn = RT_BOOL(HDA_SDCTL(pThis, 2) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3695#else
3696 bool fEnableMicIn = fEnableIn; /* Mic In == Line In */
3697#endif
3698 bool fEnableOut = RT_BOOL(HDA_SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3699
3700 PHDADRIVER pDrv;
3701 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3702 {
3703 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, fEnableIn);
3704 if (RT_FAILURE(rc))
3705 break;
3706 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, fEnableMicIn);
3707 if (RT_FAILURE(rc))
3708 break;
3709 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, fEnableOut);
3710 if (RT_FAILURE(rc))
3711 break;
3712 }
3713 }
3714
3715 if (RT_SUCCESS(rc))
3716 {
3717 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3718 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3719 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3720 }
3721
3722 LogFlowFuncLeaveRC(rc);
3723 return rc;
3724}
3725
3726#ifdef DEBUG
3727/* Debug and log type formatters. */
3728
3729/**
3730 * @callback_method_impl{FNRTSTRFORMATTYPE}
3731 */
3732static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3733 const char *pszType, void const *pvValue,
3734 int cchWidth, int cchPrecision, unsigned fFlags,
3735 void *pvUser)
3736{
3737 PHDABDLE pBDLE = (PHDABDLE)pvValue;
3738 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3739 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, DMA[%RU32 bytes @ 0x%x])",
3740 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW, pBDLE->u32BufSize, pBDLE->u64BufAdr);
3741}
3742
3743/**
3744 * @callback_method_impl{FNRTSTRFORMATTYPE}
3745 */
3746static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3747 const char *pszType, void const *pvValue,
3748 int cchWidth, int cchPrecision, unsigned fFlags,
3749 void *pvUser)
3750{
3751 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
3752 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3753 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
3754 uSDCTL,
3755 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
3756 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3757 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3758 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3759 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
3760 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3761 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3762 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3763}
3764
3765/**
3766 * @callback_method_impl{FNRTSTRFORMATTYPE}
3767 */
3768static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3769 const char *pszType, void const *pvValue,
3770 int cchWidth, int cchPrecision, unsigned fFlags,
3771 void *pvUser)
3772{
3773 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
3774 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, hdaSDFIFOSToBytes(uSDFIFOS));
3775}
3776
3777/**
3778 * @callback_method_impl{FNRTSTRFORMATTYPE}
3779 */
3780static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3781 const char *pszType, void const *pvValue,
3782 int cchWidth, int cchPrecision, unsigned fFlags,
3783 void *pvUser)
3784{
3785 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
3786 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
3787}
3788
3789/**
3790 * @callback_method_impl{FNRTSTRFORMATTYPE}
3791 */
3792static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3793 const char *pszType, void const *pvValue,
3794 int cchWidth, int cchPrecision, unsigned fFlags,
3795 void *pvUser)
3796{
3797 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3798 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3799 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3800 uSdSts,
3801 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3802 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3803 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3804 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3805}
3806
3807static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3808{
3809 int iReg = 0;
3810 for (; iReg < HDA_NREGS; ++iReg)
3811 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3812 return iReg;
3813 return -1;
3814}
3815
3816
3817static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
3818{
3819 Assert( pThis
3820 && iHdaIndex >= 0
3821 && iHdaIndex < HDA_NREGS);
3822 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
3823}
3824
3825/**
3826 * @callback_method_impl{FNDBGFHANDLERDEV}
3827 */
3828static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3829{
3830 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3831 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
3832 if (iHdaRegisterIndex != -1)
3833 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3834 else
3835 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
3836 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3837}
3838
3839static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
3840{
3841 Assert( pThis
3842 && iHdaStrmIndex >= 0
3843 && iHdaStrmIndex < 7);
3844 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
3845 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
3846 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
3847 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
3848 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
3849}
3850
3851static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
3852{
3853 /* todo: add args parsing */
3854 return -1;
3855}
3856
3857/**
3858 * @callback_method_impl{FNDBGFHANDLERDEV}
3859 */
3860static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3861{
3862 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3863 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
3864 if (iHdaStrmIndex != -1)
3865 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3866 else
3867 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
3868 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3869}
3870
3871/**
3872 * @callback_method_impl{FNDBGFHANDLERDEV}
3873 */
3874static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3875{
3876 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3877
3878 if (pThis->pCodec->pfnDbgListNodes)
3879 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
3880 else
3881 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3882}
3883
3884/**
3885 * @callback_method_impl{FNDBGFHANDLERDEV}
3886 */
3887static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3888{
3889 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3890
3891 if (pThis->pCodec->pfnDbgSelector)
3892 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
3893 else
3894 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3895}
3896
3897/**
3898 * @callback_method_impl{FNDBGFHANDLERDEV}
3899 */
3900static DECLCALLBACK(void) hdaInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3901{
3902 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3903
3904 if (pThis->pMixer)
3905 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
3906 else
3907 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
3908}
3909#endif /* DEBUG */
3910
3911/* PDMIBASE */
3912
3913/**
3914 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3915 */
3916static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3917{
3918 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
3919 Assert(&pThis->IBase == pInterface);
3920
3921 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3922 return NULL;
3923}
3924
3925
3926/* PDMDEVREG */
3927
3928/**
3929 * Reset notification.
3930 *
3931 * @returns VBox status code.
3932 * @param pDevIns The device instance data.
3933 *
3934 * @remark The original sources didn't install a reset handler, but it seems to
3935 * make sense to me so we'll do it.
3936 */
3937static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
3938{
3939 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3940
3941 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
3942 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3943 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3944 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3945 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3946 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
3947 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
3948 HDA_REG(pThis, CORBRP) = 0x0;
3949 HDA_REG(pThis, RIRBWP) = 0x0;
3950
3951 LogFunc(("Resetting ...\n"));
3952
3953 /* Stop any audio currently playing. */
3954 PHDADRIVER pDrv;
3955 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3956 {
3957 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
3958 /* Ignore rc. */
3959 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
3960 /* Ditto. */
3961 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
3962 /* Ditto. */
3963 }
3964
3965 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
3966
3967 if (pThis->pu32CorbBuf)
3968 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3969 else
3970 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3971
3972 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
3973 if (pThis->pu64RirbBuf)
3974 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3975 else
3976 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3977
3978 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
3979
3980 for (uint8_t u8Strm = 0; u8Strm < 8; u8Strm++) /** @todo Use a define here. */
3981 {
3982 PHDASTREAM pStrmSt = NULL;
3983 if (u8Strm == 0)
3984 pStrmSt = &pThis->StrmStOut;
3985# ifdef VBOX_WITH_HDA_MIC_IN
3986 else if (u8Strm == 2)
3987 pStrmSt = &pThis->StrmStMicIn;
3988# endif
3989 else if (u8Strm == 4)
3990 pStrmSt = &pThis->StrmStLineIn;
3991
3992 if (pStrmSt)
3993 {
3994 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
3995 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
3996
3997 hdaStreamReset(pThis, pStrmSt, u8Strm);
3998 }
3999 }
4000
4001 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
4002 HDA_REG(pThis, STATESTS) = 0x1;
4003
4004 LogRel(("HDA: Reset\n"));
4005}
4006
4007/**
4008 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4009 */
4010static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
4011{
4012 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4013
4014 PHDADRIVER pDrv;
4015 while (!RTListIsEmpty(&pThis->lstDrv))
4016 {
4017 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
4018
4019 RTListNodeRemove(&pDrv->Node);
4020 RTMemFree(pDrv);
4021 }
4022
4023 if (pThis->pMixer)
4024 {
4025 AudioMixerDestroy(pThis->pMixer);
4026 pThis->pMixer = NULL;
4027 }
4028
4029 if (pThis->pCodec)
4030 {
4031 int rc = hdaCodecDestruct(pThis->pCodec);
4032 AssertRC(rc);
4033
4034 RTMemFree(pThis->pCodec);
4035 pThis->pCodec = NULL;
4036 }
4037
4038 RTMemFree(pThis->pu32CorbBuf);
4039 pThis->pu32CorbBuf = NULL;
4040
4041 RTMemFree(pThis->pu64RirbBuf);
4042 pThis->pu64RirbBuf = NULL;
4043
4044 hdaStreamDestroy(&pThis->StrmStLineIn);
4045 hdaStreamDestroy(&pThis->StrmStMicIn);
4046 hdaStreamDestroy(&pThis->StrmStOut);
4047
4048 return VINF_SUCCESS;
4049}
4050
4051/**
4052 * Attach command.
4053 *
4054 * This is called to let the device attach to a driver for a specified LUN
4055 * during runtime. This is not called during VM construction, the device
4056 * constructor have to attach to all the available drivers.
4057 *
4058 * @returns VBox status code.
4059 * @param pDevIns The device instance.
4060 * @param uLUN The logical unit which is being detached.
4061 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4062 */
4063static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4064{
4065 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4066
4067 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
4068 ("HDA device does not support hotplugging\n"),
4069 VERR_INVALID_PARAMETER);
4070
4071 /*
4072 * Attach driver.
4073 */
4074 char *pszDesc = NULL;
4075 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4076 AssertMsgReturn(pszDesc,
4077 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
4078 VERR_NO_MEMORY);
4079
4080 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
4081 &pThis->IBase, &pThis->pDrvBase, pszDesc);
4082 if (RT_SUCCESS(rc))
4083 {
4084 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4085 if (pDrv)
4086 {
4087 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
4088 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4089 pDrv->pHDAState = pThis;
4090 pDrv->uLUN = uLUN;
4091
4092 /*
4093 * For now we always set the driver at LUN 0 as our primary
4094 * host backend. This might change in the future.
4095 */
4096 if (pDrv->uLUN == 0)
4097 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
4098
4099 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
4100
4101 /* Attach to driver list. */
4102 RTListAppend(&pThis->lstDrv, &pDrv->Node);
4103 }
4104 else
4105 rc = VERR_NO_MEMORY;
4106 }
4107 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
4108 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
4109 {
4110 LogFunc(("No attached driver for LUN #%u\n", uLUN));
4111 }
4112 else if (RT_FAILURE(rc))
4113 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
4114 uLUN, pszDesc, rc));
4115
4116 RTStrFree(pszDesc);
4117
4118 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4119 return rc;
4120}
4121
4122static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4123{
4124 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
4125
4126 LogFlowFuncEnter();
4127}
4128
4129/**
4130 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4131 */
4132static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
4133{
4134 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4135 Assert(iInstance == 0);
4136 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4137
4138 /*
4139 * Validations.
4140 */
4141 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
4142 "RCEnabled\0"))
4143 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4144 N_ ("Invalid configuration for the Intel HDA device"));
4145
4146 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
4147 if (RT_FAILURE(rc))
4148 return PDMDEV_SET_ERROR(pDevIns, rc,
4149 N_("HDA configuration error: failed to read RCEnabled as boolean"));
4150 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
4151 if (RT_FAILURE(rc))
4152 return PDMDEV_SET_ERROR(pDevIns, rc,
4153 N_("HDA configuration error: failed to read R0Enabled as boolean"));
4154
4155 /*
4156 * Initialize data (most of it anyway).
4157 */
4158 pThis->pDevInsR3 = pDevIns;
4159 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4160 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4161 /* IBase */
4162 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
4163
4164 /* PCI Device */
4165 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
4166 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
4167
4168 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
4169 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
4170 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
4171 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
4172 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
4173 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
4174 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
4175 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
4176 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
4177 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
4178 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
4179
4180#if defined(HDA_AS_PCI_EXPRESS)
4181 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
4182#elif defined(VBOX_WITH_MSI_DEVICES)
4183 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
4184#else
4185 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
4186#endif
4187
4188 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
4189 /// of these values needs to be properly documented!
4190 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
4191 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
4192
4193 /* Power Management */
4194 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
4195 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
4196 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
4197
4198#ifdef HDA_AS_PCI_EXPRESS
4199 /* PCI Express */
4200 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
4201 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
4202 /* Device flags */
4203 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
4204 /* version */ 0x1 |
4205 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
4206 /* MSI */ (100) << 9 );
4207 /* Device capabilities */
4208 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
4209 /* Device control */
4210 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
4211 /* Device status */
4212 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
4213 /* Link caps */
4214 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
4215 /* Link control */
4216 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
4217 /* Link status */
4218 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
4219 /* Slot capabilities */
4220 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
4221 /* Slot control */
4222 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
4223 /* Slot status */
4224 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
4225 /* Root control */
4226 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
4227 /* Root capabilities */
4228 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
4229 /* Root status */
4230 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
4231 /* Device capabilities 2 */
4232 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
4233 /* Device control 2 */
4234 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
4235 /* Link control 2 */
4236 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
4237 /* Slot control 2 */
4238 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
4239#endif
4240
4241 /*
4242 * Register the PCI device.
4243 */
4244 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
4245 if (RT_FAILURE(rc))
4246 return rc;
4247
4248 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
4249 if (RT_FAILURE(rc))
4250 return rc;
4251
4252#ifdef VBOX_WITH_MSI_DEVICES
4253 PDMMSIREG MsiReg;
4254 RT_ZERO(MsiReg);
4255 MsiReg.cMsiVectors = 1;
4256 MsiReg.iMsiCapOffset = 0x60;
4257 MsiReg.iMsiNextOffset = 0x50;
4258 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4259 if (RT_FAILURE(rc))
4260 {
4261 /* That's OK, we can work without MSI */
4262 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
4263 }
4264#endif
4265
4266 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
4267 if (RT_FAILURE(rc))
4268 return rc;
4269
4270 RTListInit(&pThis->lstDrv);
4271
4272 uint8_t uLUN;
4273 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
4274 {
4275 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
4276 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
4277 if (RT_FAILURE(rc))
4278 {
4279 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4280 rc = VINF_SUCCESS;
4281
4282 break;
4283 }
4284
4285 uLUN++;
4286 }
4287
4288 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
4289
4290 if (RT_SUCCESS(rc))
4291 {
4292 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
4293 if (RT_SUCCESS(rc))
4294 {
4295 /* Set a default audio format for our mixer. */
4296 PDMAUDIOSTREAMCFG streamCfg;
4297 streamCfg.uHz = 44100;
4298 streamCfg.cChannels = 2;
4299 streamCfg.enmFormat = AUD_FMT_S16;
4300 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
4301
4302 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
4303 AssertRC(rc);
4304
4305 /* Add all required audio sinks. */
4306 rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output",
4307 AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
4308 AssertRC(rc);
4309
4310 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In",
4311 AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
4312 AssertRC(rc);
4313
4314 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
4315 AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
4316 AssertRC(rc);
4317
4318 /* There is no master volume control. Set the master to max. */
4319 PDMAUDIOVOLUME vol = { false, 255, 255 };
4320 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
4321 AssertRC(rc);
4322 }
4323 }
4324
4325 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
4326
4327 if (RT_SUCCESS(rc))
4328 {
4329 /* Construct codec. */
4330 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
4331 if (!pThis->pCodec)
4332 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
4333
4334 /* Audio driver callbacks for multiplexing. */
4335 pThis->pCodec->pfnCloseIn = hdaCloseIn;
4336 pThis->pCodec->pfnCloseOut = hdaCloseOut;
4337 pThis->pCodec->pfnOpenIn = hdaOpenIn;
4338 pThis->pCodec->pfnOpenOut = hdaOpenOut;
4339 pThis->pCodec->pfnReset = hdaCodecReset;
4340 pThis->pCodec->pfnSetVolume = hdaSetVolume;
4341
4342 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
4343
4344 /* Construct the codec. */
4345 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
4346 if (RT_FAILURE(rc))
4347 AssertRCReturn(rc, rc);
4348
4349 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
4350 verb F20 should provide device/codec recognition. */
4351 Assert(pThis->pCodec->u16VendorId);
4352 Assert(pThis->pCodec->u16DeviceId);
4353 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
4354 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
4355 }
4356
4357 if (RT_SUCCESS(rc))
4358 {
4359 hdaReset(pDevIns);
4360
4361 /*
4362 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4363 * hdaReset shouldn't affects these registers.
4364 */
4365 HDA_REG(pThis, WAKEEN) = 0x0;
4366 HDA_REG(pThis, STATESTS) = 0x0;
4367
4368#ifdef DEBUG
4369 /*
4370 * Debug and string formatter types.
4371 */
4372 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
4373 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
4374 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
4375 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
4376 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaInfoMixer);
4377
4378 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
4379 AssertRC(rc);
4380 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
4381 AssertRC(rc);
4382 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
4383 AssertRC(rc);
4384 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
4385 AssertRC(rc);
4386 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
4387 AssertRC(rc);
4388#endif /* DEBUG */
4389
4390 /*
4391 * Some debug assertions.
4392 */
4393 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
4394 {
4395 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
4396 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
4397
4398 /* binary search order. */
4399 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
4400 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4401 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4402
4403 /* alignment. */
4404 AssertReleaseMsg( pReg->size == 1
4405 || (pReg->size == 2 && (pReg->offset & 1) == 0)
4406 || (pReg->size == 3 && (pReg->offset & 3) == 0)
4407 || (pReg->size == 4 && (pReg->offset & 3) == 0),
4408 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4409
4410 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
4411 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
4412 if (pReg->offset & 3)
4413 {
4414 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
4415 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4416 if (pPrevReg)
4417 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
4418 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4419 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
4420 }
4421#if 0
4422 if ((pReg->offset + pReg->size) & 3)
4423 {
4424 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4425 if (pNextReg)
4426 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
4427 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4428 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4429 }
4430#endif
4431 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
4432 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
4433 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4434 }
4435 }
4436
4437# ifndef VBOX_WITH_AUDIO_CALLBACKS
4438 if (RT_SUCCESS(rc))
4439 {
4440 /* Start the emulation timer. */
4441 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
4442 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
4443 AssertRCReturn(rc, rc);
4444
4445 if (RT_SUCCESS(rc))
4446 {
4447 /** @todo Investigate why sounds is getting corrupted if the "ticks" value is too
4448 * low, e.g. "PDMDevHlpTMTimeVirtGetFreq / 200". */
4449 pThis->uTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 500; /** @todo Make this configurable! */
4450 if (pThis->uTicks < 100)
4451 pThis->uTicks = 100;
4452 LogFunc(("Timer ticks=%RU64\n", pThis->uTicks));
4453
4454 /* Fire off timer. */
4455 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
4456 }
4457 }
4458# else
4459 if (RT_SUCCESS(rc))
4460 {
4461 PHDADRIVER pDrv;
4462 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4463 {
4464 /* Only register primary driver.
4465 * The device emulation does the output multiplexing then. */
4466 if (pDrv->Flags != PDMAUDIODRVFLAG_PRIMARY)
4467 continue;
4468
4469 PDMAUDIOCALLBACK AudioCallbacks[2];
4470
4471 HDACALLBACKCTX Ctx = { pThis, pDrv };
4472
4473 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
4474 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
4475 AudioCallbacks[0].pvCtx = &Ctx;
4476 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
4477
4478 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
4479 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
4480 AudioCallbacks[1].pvCtx = &Ctx;
4481 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
4482
4483 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
4484 if (RT_FAILURE(rc))
4485 break;
4486 }
4487 }
4488# endif
4489
4490# ifdef VBOX_WITH_STATISTICS
4491 if (RT_SUCCESS(rc))
4492 {
4493 /*
4494 * Register statistics.
4495 */
4496# ifndef VBOX_WITH_AUDIO_CALLBACKS
4497 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
4498# endif
4499 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
4500 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
4501 }
4502# endif
4503
4504 LogFlowFuncLeaveRC(rc);
4505 return rc;
4506}
4507
4508/**
4509 * The device registration structure.
4510 */
4511const PDMDEVREG g_DeviceICH6_HDA =
4512{
4513 /* u32Version */
4514 PDM_DEVREG_VERSION,
4515 /* szName */
4516 "hda",
4517 /* szRCMod */
4518 "VBoxDDRC.rc",
4519 /* szR0Mod */
4520 "VBoxDDR0.r0",
4521 /* pszDescription */
4522 "Intel HD Audio Controller",
4523 /* fFlags */
4524 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
4525 /* fClass */
4526 PDM_DEVREG_CLASS_AUDIO,
4527 /* cMaxInstances */
4528 1,
4529 /* cbInstance */
4530 sizeof(HDASTATE),
4531 /* pfnConstruct */
4532 hdaConstruct,
4533 /* pfnDestruct */
4534 hdaDestruct,
4535 /* pfnRelocate */
4536 NULL,
4537 /* pfnMemSetup */
4538 NULL,
4539 /* pfnPowerOn */
4540 NULL,
4541 /* pfnReset */
4542 hdaReset,
4543 /* pfnSuspend */
4544 NULL,
4545 /* pfnResume */
4546 NULL,
4547 /* pfnAttach */
4548 NULL,
4549 /* pfnDetach */
4550 NULL,
4551 /* pfnQueryInterface. */
4552 NULL,
4553 /* pfnInitComplete */
4554 NULL,
4555 /* pfnPowerOff */
4556 NULL,
4557 /* pfnSoftReset */
4558 NULL,
4559 /* u32VersionEnd */
4560 PDM_DEVREG_VERSION
4561};
4562
4563#endif /* IN_RING3 */
4564#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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