VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 58925

Last change on this file since 58925 was 58925, checked in by vboxsync, 9 years ago

Build fix.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 165.8 KB
Line 
1/* $Id: DevIchHda.cpp 58925 2015-11-30 21:32:50Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2015 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/list.h>
36#ifdef IN_RING3
37# include <iprt/mem.h>
38# include <iprt/string.h>
39# include <iprt/uuid.h>
40#endif
41
42#include "VBoxDD.h"
43
44#include "AudioMixer.h"
45#include "DevIchHdaCodec.h"
46
47
48/*********************************************************************************************************************************
49* Defined Constants And Macros *
50*********************************************************************************************************************************/
51//#define HDA_AS_PCI_EXPRESS
52#define VBOX_WITH_INTEL_HDA
53
54#if (defined(DEBUG) && defined(DEBUG_andy))
55/* Enables experimental support for separate mic-in handling.
56 Do not enable this yet for regular builds, as this needs more testing first! */
57# define VBOX_WITH_HDA_MIC_IN
58#endif
59
60#if defined(VBOX_WITH_HP_HDA)
61/* HP Pavilion dv4t-1300 */
62# define HDA_PCI_VENDOR_ID 0x103c
63# define HDA_PCI_DEVICE_ID 0x30f7
64#elif defined(VBOX_WITH_INTEL_HDA)
65/* Intel HDA controller */
66# define HDA_PCI_VENDOR_ID 0x8086
67# define HDA_PCI_DEVICE_ID 0x2668
68#elif defined(VBOX_WITH_NVIDIA_HDA)
69/* nVidia HDA controller */
70# define HDA_PCI_VENDOR_ID 0x10de
71# define HDA_PCI_DEVICE_ID 0x0ac0
72#else
73# error "Please specify your HDA device vendor/device IDs"
74#endif
75
76/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
77 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
78 * is read only except for bit 15 like the HDA spec states.
79 *
80 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
81 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
82#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
83
84#define HDA_NREGS 114
85#define HDA_NREGS_SAVED 112
86
87/**
88 * NB: Register values stored in memory (au32Regs[]) are indexed through
89 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
90 * register descriptors in g_aHdaRegMap[] are indexed through the
91 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
92 *
93 * The au32Regs[] layout is kept unchanged for saved state
94 * compatibility. */
95
96/* Registers */
97#define HDA_REG_IND_NAME(x) HDA_REG_##x
98#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
99#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
100#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
101#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
102#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
103#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
104#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
105
106
107#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
108#define HDA_RMX_GCAP 0
109/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
110 * oss (15:12) - number of output streams supported
111 * iss (11:8) - number of input streams supported
112 * bss (7:3) - number of bidirectional streams supported
113 * bds (2:1) - number of serial data out signals supported
114 * b64sup (0) - 64 bit addressing supported.
115 */
116#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
117 ( (((oss) & 0xF) << 12) \
118 | (((iss) & 0xF) << 8) \
119 | (((bss) & 0x1F) << 3) \
120 | (((bds) & 0x3) << 2) \
121 | ((b64sup) & 1))
122
123#define HDA_REG_VMIN 1 /* 0x02 */
124#define HDA_RMX_VMIN 1
125
126#define HDA_REG_VMAJ 2 /* 0x03 */
127#define HDA_RMX_VMAJ 2
128
129#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
130#define HDA_RMX_OUTPAY 3
131
132#define HDA_REG_INPAY 4 /* 0x06-0x07 */
133#define HDA_RMX_INPAY 4
134
135#define HDA_REG_GCTL 5 /* 0x08-0x0B */
136#define HDA_RMX_GCTL 5
137#define HDA_GCTL_RST_SHIFT 0
138#define HDA_GCTL_FSH_SHIFT 1
139#define HDA_GCTL_UR_SHIFT 8
140
141#define HDA_REG_WAKEEN 6 /* 0x0C */
142#define HDA_RMX_WAKEEN 6
143
144#define HDA_REG_STATESTS 7 /* 0x0E */
145#define HDA_RMX_STATESTS 7
146#define HDA_STATES_SCSF 0x7
147
148#define HDA_REG_GSTS 8 /* 0x10-0x11*/
149#define HDA_RMX_GSTS 8
150#define HDA_GSTS_FSH_SHIFT 1
151
152#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
153#define HDA_RMX_OUTSTRMPAY 112
154
155#define HDA_REG_INSTRMPAY 10 /* 0x1a */
156#define HDA_RMX_INSTRMPAY 113
157
158#define HDA_REG_INTCTL 11 /* 0x20 */
159#define HDA_RMX_INTCTL 9
160#define HDA_INTCTL_GIE_SHIFT 31
161#define HDA_INTCTL_CIE_SHIFT 30
162#define HDA_INTCTL_S0_SHIFT 0
163#define HDA_INTCTL_S1_SHIFT 1
164#define HDA_INTCTL_S2_SHIFT 2
165#define HDA_INTCTL_S3_SHIFT 3
166#define HDA_INTCTL_S4_SHIFT 4
167#define HDA_INTCTL_S5_SHIFT 5
168#define HDA_INTCTL_S6_SHIFT 6
169#define HDA_INTCTL_S7_SHIFT 7
170#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
171
172#define HDA_REG_INTSTS 12 /* 0x24 */
173#define HDA_RMX_INTSTS 10
174#define HDA_INTSTS_GIS_SHIFT 31
175#define HDA_INTSTS_CIS_SHIFT 30
176#define HDA_INTSTS_S0_SHIFT 0
177#define HDA_INTSTS_S1_SHIFT 1
178#define HDA_INTSTS_S2_SHIFT 2
179#define HDA_INTSTS_S3_SHIFT 3
180#define HDA_INTSTS_S4_SHIFT 4
181#define HDA_INTSTS_S5_SHIFT 5
182#define HDA_INTSTS_S6_SHIFT 6
183#define HDA_INTSTS_S7_SHIFT 7
184#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
185
186#define HDA_REG_WALCLK 13 /* 0x24 */
187#define HDA_RMX_WALCLK /* Not defined! */
188
189/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
190 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
191 * the datasheet.
192 */
193#define HDA_REG_SSYNC 14 /* 0x34 */
194#define HDA_RMX_SSYNC 12
195
196#define HDA_REG_CORBLBASE 15 /* 0x40 */
197#define HDA_RMX_CORBLBASE 13
198
199#define HDA_REG_CORBUBASE 16 /* 0x44 */
200#define HDA_RMX_CORBUBASE 14
201
202#define HDA_REG_CORBWP 17 /* 0x48 */
203#define HDA_RMX_CORBWP 15
204
205#define HDA_REG_CORBRP 18 /* 0x4A */
206#define HDA_RMX_CORBRP 16
207#define HDA_CORBRP_RST_SHIFT 15
208#define HDA_CORBRP_WP_SHIFT 0
209#define HDA_CORBRP_WP_MASK 0xFF
210
211#define HDA_REG_CORBCTL 19 /* 0x4C */
212#define HDA_RMX_CORBCTL 17
213#define HDA_CORBCTL_DMA_SHIFT 1
214#define HDA_CORBCTL_CMEIE_SHIFT 0
215
216#define HDA_REG_CORBSTS 20 /* 0x4D */
217#define HDA_RMX_CORBSTS 18
218#define HDA_CORBSTS_CMEI_SHIFT 0
219
220#define HDA_REG_CORBSIZE 21 /* 0x4E */
221#define HDA_RMX_CORBSIZE 19
222#define HDA_CORBSIZE_SZ_CAP 0xF0
223#define HDA_CORBSIZE_SZ 0x3
224/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
225
226#define HDA_REG_RIRBLBASE 22 /* 0x50 */
227#define HDA_RMX_RIRBLBASE 20
228
229#define HDA_REG_RIRBUBASE 23 /* 0x54 */
230#define HDA_RMX_RIRBUBASE 21
231
232#define HDA_REG_RIRBWP 24 /* 0x58 */
233#define HDA_RMX_RIRBWP 22
234#define HDA_RIRBWP_RST_SHIFT 15
235#define HDA_RIRBWP_WP_MASK 0xFF
236
237#define HDA_REG_RINTCNT 25 /* 0x5A */
238#define HDA_RMX_RINTCNT 23
239#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
240
241#define HDA_REG_RIRBCTL 26 /* 0x5C */
242#define HDA_RMX_RIRBCTL 24
243#define HDA_RIRBCTL_RIC_SHIFT 0
244#define HDA_RIRBCTL_DMA_SHIFT 1
245#define HDA_ROI_DMA_SHIFT 2
246
247#define HDA_REG_RIRBSTS 27 /* 0x5D */
248#define HDA_RMX_RIRBSTS 25
249#define HDA_RIRBSTS_RINTFL_SHIFT 0
250#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
251
252#define HDA_REG_RIRBSIZE 28 /* 0x5E */
253#define HDA_RMX_RIRBSIZE 26
254#define HDA_RIRBSIZE_SZ_CAP 0xF0
255#define HDA_RIRBSIZE_SZ 0x3
256
257#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
258#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
259
260
261#define HDA_REG_IC 29 /* 0x60 */
262#define HDA_RMX_IC 27
263
264#define HDA_REG_IR 30 /* 0x64 */
265#define HDA_RMX_IR 28
266
267#define HDA_REG_IRS 31 /* 0x68 */
268#define HDA_RMX_IRS 29
269#define HDA_IRS_ICB_SHIFT 0
270#define HDA_IRS_IRV_SHIFT 1
271
272#define HDA_REG_DPLBASE 32 /* 0x70 */
273#define HDA_RMX_DPLBASE 30
274#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
275
276#define HDA_REG_DPUBASE 33 /* 0x74 */
277#define HDA_RMX_DPUBASE 31
278#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
279/** DMA Position Buffer Enable (3.3.32). */
280#define DPBASE_ENABLED RT_BIT(0)
281#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
282
283#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
284#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
285/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
286#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
287
288#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
289
290#define HDA_REG_SD0CTL 34 /* 0x80 */
291#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
292#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
293#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
294#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
295#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
296#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
297#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
298#define HDA_RMX_SD0CTL 32
299#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
300#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
301#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
302#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
303#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
304#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
305#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
306
307#define SD(func, num) SD##num##func
308
309#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
310#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
311#define HDA_SDCTL_NUM_MASK 0xF
312#define HDA_SDCTL_NUM_SHIFT 20
313#define HDA_SDCTL_DIR_SHIFT 19
314#define HDA_SDCTL_TP_SHIFT 18
315#define HDA_SDCTL_STRIPE_MASK 0x3
316#define HDA_SDCTL_STRIPE_SHIFT 16
317#define HDA_SDCTL_DEIE_SHIFT 4
318#define HDA_SDCTL_FEIE_SHIFT 3
319#define HDA_SDCTL_ICE_SHIFT 2
320#define HDA_SDCTL_RUN_SHIFT 1
321#define HDA_SDCTL_SRST_SHIFT 0
322
323#define HDA_REG_SD0STS 35 /* 0x83 */
324#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
325#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
326#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
327#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
328#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
329#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
330#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
331#define HDA_RMX_SD0STS 33
332#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
333#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
334#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
335#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
336#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
337#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
338#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
339
340#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
341#define HDA_SDSTS_FIFORDY_SHIFT 5
342#define HDA_SDSTS_DE_SHIFT 4
343#define HDA_SDSTS_FE_SHIFT 3
344#define HDA_SDSTS_BCIS_SHIFT 2
345
346#define HDA_REG_SD0LPIB 36 /* 0x84 */
347#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
348#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
349#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
350#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
351#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
352#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
353#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
354#define HDA_RMX_SD0LPIB 34
355#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
356#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
357#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
358#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
359#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
360#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
361#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
362
363#define HDA_REG_SD0CBL 37 /* 0x88 */
364#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
365#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
366#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
367#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
368#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
369#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
370#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
371#define HDA_RMX_SD0CBL 35
372#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
373#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
374#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
375#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
376#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
377#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
378#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
379
380#define HDA_REG_SD0LVI 38 /* 0x8C */
381#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
382#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
383#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
384#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
385#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
386#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
387#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
388#define HDA_RMX_SD0LVI 36
389#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
390#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
391#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
392#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
393#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
394#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
395#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
396
397#define HDA_REG_SD0FIFOW 39 /* 0x8E */
398#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
399#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
400#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
401#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
402#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
403#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
404#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
405#define HDA_RMX_SD0FIFOW 37
406#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
407#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
408#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
409#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
410#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
411#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
412#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
413
414/*
415 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
416 */
417#define HDA_SDFIFOW_8B 0x2
418#define HDA_SDFIFOW_16B 0x3
419#define HDA_SDFIFOW_32B 0x4
420
421#define HDA_REG_SD0FIFOS 40 /* 0x90 */
422#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
423#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
424#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
425#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
426#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
427#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
428#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
429#define HDA_RMX_SD0FIFOS 38
430#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
431#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
432#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
433#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
434#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
435#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
436#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
437
438/*
439 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
440 * formula: size - 1
441 * Other values not listed are not supported.
442 */
443#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
444#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
445
446#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
447#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
448#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
449#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
450#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
451#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
452#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
453
454#define HDA_REG_SD0FMT 41 /* 0x92 */
455#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
456#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
457#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
458#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
459#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
460#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
461#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
462#define HDA_RMX_SD0FMT 39
463#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
464#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
465#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
466#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
467#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
468#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
469#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
470
471#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
472#define HDA_SDFMT_BASE_RATE_SHIFT 14
473#define HDA_SDFMT_MULT_SHIFT 11
474#define HDA_SDFMT_MULT_MASK 0x7
475#define HDA_SDFMT_DIV_SHIFT 8
476#define HDA_SDFMT_DIV_MASK 0x7
477#define HDA_SDFMT_BITS_SHIFT 4
478#define HDA_SDFMT_BITS_MASK 0x7
479#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
480#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
481#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
482
483#define HDA_REG_SD0BDPL 42 /* 0x98 */
484#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
485#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
486#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
487#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
488#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
489#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
490#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
491#define HDA_RMX_SD0BDPL 40
492#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
493#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
494#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
495#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
496#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
497#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
498#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
499
500#define HDA_REG_SD0BDPU 43 /* 0x9C */
501#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
502#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
503#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
504#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
505#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
506#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
507#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
508#define HDA_RMX_SD0BDPU 41
509#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
510#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
511#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
512#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
513#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
514#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
515#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
516
517#define HDA_CODEC_CAD_SHIFT 28
518/* Encodes the (required) LUN into a codec command. */
519#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
520
521
522
523/*********************************************************************************************************************************
524* Structures and Typedefs *
525*********************************************************************************************************************************/
526
527/**
528 * Internal state of a Buffer Descriptor List Entry (BDLE),
529 * needed to keep track of the data needed for the actual device
530 * emulation.
531 */
532typedef struct HDABDLESTATE
533{
534 /** Own index within the BDL (Buffer Descriptor List). */
535 uint32_t u32BDLIndex;
536 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
537 * Used to check if we need fill up the FIFO again. */
538 uint32_t cbBelowFIFOW;
539 /** The buffer descriptor's internal DMA buffer. */
540 uint8_t au8FIFO[HDA_SDONFIFO_256B + 1];
541 /** Current offset in DMA buffer (in bytes).*/
542 uint32_t u32BufOff;
543 uint32_t Padding;
544} HDABDLESTATE, *PHDABDLESTATE;
545
546/**
547 * Buffer Descriptor List Entry (BDLE) (3.6.3).
548 *
549 * Contains only register values which do *not* change until a
550 * stream reset occurs.
551 */
552typedef struct HDABDLE
553{
554 /** Starting address of the actual buffer. Must be 128-bit aligned. */
555 uint64_t u64BufAdr;
556 /** Size of the actual buffer (in bytes). */
557 uint32_t u32BufSize;
558 /** Interrupt on completion; the controller will generate
559 * an interrupt when the last byte of the buffer has been
560 * fetched by the DMA engine. */
561 bool fIntOnCompletion;
562 /** Internal state of this BDLE.
563 * Not part of the actual BDLE registers. */
564 HDABDLESTATE State;
565} HDABDLE, *PHDABDLE;
566
567/**
568 * Internal state of a HDA stream.
569 */
570typedef struct HDASTREAMSTATE
571{
572 /** Number of BDLEs (Buffer Descriptor List Entry).
573 * Should be SDnLVI + 1 usually. */
574 uint16_t cBDLE;
575 /** Current BDLE to use. Wraps around to 0 if
576 * maximum (cBDLE) is reached. */
577 uint16_t uCurBDLE;
578 uint32_t Padding;
579 /** Array of BDLEs. */
580 R3PTRTYPE(PHDABDLE) paBDLE;
581} HDASTREAMSTATE, *PHDASTREAMSTATE;
582
583/**
584 * Structure for keeping a HDA stream state.
585 *
586 * Contains only register values which do *not* change until a
587 * stream reset occurs.
588 */
589typedef struct HDASTREAM
590{
591 /** Stream number (SDn). */
592 uint8_t u8Strm;
593 uint8_t Padding0[7];
594 /** DMA base address (SDnBDPU - SDnBDPL). */
595 uint64_t u64BaseDMA;
596 /** Cyclic Buffer Length (SDnCBL).
597 * Represents the size of the ring buffer. */
598 uint32_t u32CBL;
599 /** Format (SDnFMT). */
600 uint16_t u16FMT;
601 /** FIFO Size (FIFOS).
602 * Maximum number of bytes that may have been DMA'd into
603 * memory but not yet transmitted on the link.
604 *
605 * Must be a power of two. */
606 uint16_t u16FIFOS;
607 /** Last Valid Index (SDnLVI). */
608 uint16_t u16LVI;
609 uint16_t Padding1[3];
610 /** Internal state of this stream. */
611 HDASTREAMSTATE State;
612} HDASTREAM, *PHDASTREAM;
613
614typedef struct HDAINPUTSTREAM
615{
616 /** PCM line input stream. */
617 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
618 /** Mixer handle for line input stream. */
619 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
620} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
621
622typedef struct HDAOUTPUTSTREAM
623{
624 /** PCM output stream. */
625 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
626 /** Mixer handle for line output stream. */
627 R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
628} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
629
630/**
631 * Struct for maintaining a host backend driver.
632 * This driver must be associated to one, and only one,
633 * HDA codec. The HDA controller does the actual multiplexing
634 * of HDA codec data to various host backend drivers then.
635 *
636 * This HDA device uses a timer in order to synchronize all
637 * read/write accesses across all attached LUNs / backends.
638 */
639typedef struct HDADRIVER
640{
641 union
642 {
643 /** Node for storing this driver in our device driver
644 * list of HDASTATE. */
645 RTLISTNODE Node;
646 struct
647 {
648 R3PTRTYPE(void *) dummy1;
649 R3PTRTYPE(void *) dummy2;
650 } dummy;
651 };
652
653 /** Pointer to HDA controller (state). */
654 R3PTRTYPE(PHDASTATE) pHDAState;
655 /** Driver flags. */
656 PDMAUDIODRVFLAGS Flags;
657 uint8_t u32Padding0[3];
658 /** LUN to which this driver has been assigned. */
659 uint8_t uLUN;
660 /** Audio connector interface to the underlying
661 * host backend. */
662 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
663 /** Stream for line input. */
664 HDAINPUTSTREAM LineIn;
665 /** Stream for mic input. */
666 HDAINPUTSTREAM MicIn;
667 /** Stream for output. */
668 HDAOUTPUTSTREAM Out;
669} HDADRIVER;
670
671/**
672 * ICH Intel HD Audio Controller state.
673 */
674typedef struct HDASTATE
675{
676 /** The PCI device structure. */
677 PCIDevice PciDev;
678 /** R3 Pointer to the device instance. */
679 PPDMDEVINSR3 pDevInsR3;
680 /** R0 Pointer to the device instance. */
681 PPDMDEVINSR0 pDevInsR0;
682 /** R0 Pointer to the device instance. */
683 PPDMDEVINSRC pDevInsRC;
684 /** Padding for alignment. */
685 uint32_t u32Padding;
686 /** Pointer to the attached audio driver. */
687 R3PTRTYPE(PPDMIBASE) pDrvBase;
688 /** The base interface for LUN\#0. */
689 PDMIBASE IBase;
690 RTGCPHYS MMIOBaseAddr;
691 /** The HDA's register set. */
692 uint32_t au32Regs[HDA_NREGS];
693 /** Stream state for line-in. */
694 HDASTREAM StrmStLineIn;
695 /** Stream state for microphone-in. */
696 HDASTREAM StrmStMicIn;
697 /** Stream state for output. */
698 HDASTREAM StrmStOut;
699 /** CORB buffer base address. */
700 uint64_t u64CORBBase;
701 /** RIRB buffer base address. */
702 uint64_t u64RIRBBase;
703 /** DMA base address.
704 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
705 uint64_t u64DPBase;
706 /** Pointer to CORB buffer. */
707 R3PTRTYPE(uint32_t *) pu32CorbBuf;
708 /** Size in bytes of CORB buffer. */
709 uint32_t cbCorbBuf;
710 /** Padding for alignment. */
711 uint32_t u32Padding2;
712 /** Pointer to RIRB buffer. */
713 R3PTRTYPE(uint64_t *) pu64RirbBuf;
714 /** Size in bytes of RIRB buffer. */
715 uint32_t cbRirbBuf;
716 /** Indicates if HDA is in reset. */
717 bool fInReset;
718 /** Flag whether the R0 part is enabled. */
719 bool fR0Enabled;
720 /** Flag whether the RC part is enabled. */
721 bool fRCEnabled;
722 /** The emulation timer for handling the attached
723 * LUN drivers. */
724 PTMTIMERR3 pTimer;
725 /** Timer ticks for handling the LUN drivers. */
726 uint64_t uTicks;
727#ifdef VBOX_WITH_STATISTICS
728# ifndef VBOX_WITH_AUDIO_CALLBACKS
729 STAMPROFILE StatTimer;
730# endif
731 STAMCOUNTER StatBytesRead;
732 STAMCOUNTER StatBytesWritten;
733#endif
734 /** Pointer to HDA codec to use. */
735 R3PTRTYPE(PHDACODEC) pCodec;
736 union
737 {
738 /** List of associated LUN drivers. */
739 RTLISTANCHOR lstDrv;
740 /** Padding for alignment. */
741 struct
742 {
743 R3PTRTYPE(void *) dummy1;
744 R3PTRTYPE(void *) dummy2;
745 } dummy;
746 };
747 /** The device' software mixer. */
748 R3PTRTYPE(PAUDIOMIXER) pMixer;
749 /** Audio sink for PCM output. */
750 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
751 /** Audio mixer sink for line input. */
752 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
753 /** Audio mixer sink for microphone input. */
754 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
755 uint64_t u64BaseTS;
756 /** Response Interrupt Count (RINTCNT). */
757 uint8_t u8RespIntCnt;
758 /** Padding for alignment. */
759 uint8_t au8Padding[7];
760} HDASTATE;
761/** Pointer to the ICH Intel HD Audio Controller state. */
762typedef HDASTATE *PHDASTATE;
763
764#ifdef VBOX_WITH_AUDIO_CALLBACKS
765typedef struct HDACALLBACKCTX
766{
767 PHDASTATE pThis;
768 PHDADRIVER pDriver;
769} HDACALLBACKCTX, *PHDACALLBACKCTX;
770#endif
771
772#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
773 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
774#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
775 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
776
777
778/*********************************************************************************************************************************
779* Internal Functions *
780*********************************************************************************************************************************/
781#ifndef VBOX_DEVICE_STRUCT_TESTCASE
782static FNPDMDEVRESET hdaReset;
783
784/*
785 * Stubs.
786 */
787static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
788static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
789
790/*
791 * Global register set read/write functions.
792 */
793static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
794static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
795static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
796static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
797static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
798static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
799static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
800static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
801static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
802static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
803static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
804static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
805static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
806static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
807static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
808
809/*
810 * {IOB}SDn read/write functions.
811 */
812static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
813static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
814static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
815static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
816static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
817static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
818static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
819static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
820static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
821
822/*
823 * Generic register read/write functions.
824 */
825static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
826static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
827static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
828static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
829static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
830static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
831static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
832static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
833
834static void hdaStreamDestroy(PHDASTREAM pStrmSt);
835
836static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t *pcbProcessed);
837
838#ifdef IN_RING3
839static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
840# ifdef LOG_ENABLED
841static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t u16LVI);
842# endif
843static void hdaBDLEReset(PHDABDLE pBDLE);
844#endif
845
846
847/*********************************************************************************************************************************
848* Global Variables *
849*********************************************************************************************************************************/
850
851/** Offset of the SD0 register map. */
852#define HDA_REG_DESC_SD0_BASE 0x80
853
854/** Turn a short global register name into an memory index and a stringized name. */
855#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
856
857/** Turns a short stream register name into an memory index and a stringized name. */
858#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
859
860/** Same as above for a register *not* stored in memory. */
861#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
862
863/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
864#define HDA_REG_MAP_STRM(offset, name) \
865 /* offset size read mask write mask read callback write callback index + abbrev description */ \
866 /* ------- ------- ---------- ---------- -------------- ----------------- ------------------------------ ----------- */ \
867 /* Offset 0x80 (SD0) */ \
868 { offset, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
869 /* Offset 0x83 (SD0) */ \
870 { offset + 0x3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
871 /* Offset 0x84 (SD0) */ \
872 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
873 /* Offset 0x88 (SD0) */ \
874 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
875 /* Offset 0x8C (SD0) */ \
876 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
877 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
878 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
879 /* Offset 0x90 (SD0) */ \
880 { offset + 0x10, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16, hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
881 /* Offset 0x92 (SD0) */ \
882 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Format" }, \
883 /* Reserved: 0x94 - 0x98. */ \
884 /* Offset 0x98 (SD0) */ \
885 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
886 /* Offset 0x9C (SD0) */ \
887 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
888
889/** Defines a single audio stream register set (e.g. OSD0). */
890#define HDA_REG_MAP_DEF_STREAM(index, name) \
891 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
892
893/* See 302349 p 6.2. */
894static const struct HDAREGDESC
895{
896 /** Register offset in the register space. */
897 uint32_t offset;
898 /** Size in bytes. Registers of size > 4 are in fact tables. */
899 uint32_t size;
900 /** Readable bits. */
901 uint32_t readable;
902 /** Writable bits. */
903 uint32_t writable;
904 /** Read callback. */
905 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
906 /** Write callback. */
907 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
908 /** Index into the register storage array. */
909 uint32_t mem_idx;
910 /** Abbreviated name. */
911 const char *abbrev;
912 /** Descripton. */
913 const char *desc;
914} g_aHdaRegMap[HDA_NREGS] =
915
916{
917 /* offset size read mask write mask read callback write callback index + abbrev */
918 /*------- ------- ---------- ---------- ----------------------- ---------------------- ---------------- */
919 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
920 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
921 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
922 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
923 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
924 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
925 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
926 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , HDA_REG_IDX(STATESTS) }, /* State Change Status */
927 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
928 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
929 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
930 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
931 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
932 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
933 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
934 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
935 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
936 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
937 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
938 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
939 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
940 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
941 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
942 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
943 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
944 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
945 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
946 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
947 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
948 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
949 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
950 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
951 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* MA Position Lower Base */
952 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
953 /* 4 Input Stream Descriptors (ISD). */
954 HDA_REG_MAP_DEF_STREAM(0, SD0),
955 HDA_REG_MAP_DEF_STREAM(1, SD1),
956 HDA_REG_MAP_DEF_STREAM(2, SD2),
957 HDA_REG_MAP_DEF_STREAM(3, SD3),
958 /* 4 Output Stream Descriptors (OSD). */
959 HDA_REG_MAP_DEF_STREAM(4, SD4),
960 HDA_REG_MAP_DEF_STREAM(5, SD5),
961 HDA_REG_MAP_DEF_STREAM(6, SD6),
962 HDA_REG_MAP_DEF_STREAM(7, SD7)
963};
964
965/**
966 * HDA register aliases (HDA spec 3.3.45).
967 * @remarks Sorted by offReg.
968 */
969static const struct
970{
971 /** The alias register offset. */
972 uint32_t offReg;
973 /** The register index. */
974 int idxAlias;
975} g_aHdaRegAliases[] =
976{
977 { 0x2084, HDA_REG_SD0LPIB },
978 { 0x20a4, HDA_REG_SD1LPIB },
979 { 0x20c4, HDA_REG_SD2LPIB },
980 { 0x20e4, HDA_REG_SD3LPIB },
981 { 0x2104, HDA_REG_SD4LPIB },
982 { 0x2124, HDA_REG_SD5LPIB },
983 { 0x2144, HDA_REG_SD6LPIB },
984 { 0x2164, HDA_REG_SD7LPIB },
985};
986
987#ifdef IN_RING3
988/** HDABDLESTATE field descriptors for the v5+ saved state. */
989static SSMFIELD const g_aSSMBDLEStateFields5[] =
990{
991 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
992 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
993 SSMFIELD_ENTRY(HDABDLESTATE, au8FIFO),
994 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
995 SSMFIELD_ENTRY_TERM()
996};
997
998/** HDASTREAMSTATE field descriptors for the v5+ saved state. */
999static SSMFIELD const g_aSSMStreamStateFields5[] =
1000{
1001 SSMFIELD_ENTRY (HDASTREAMSTATE, cBDLE),
1002 SSMFIELD_ENTRY (HDASTREAMSTATE, uCurBDLE),
1003 SSMFIELD_ENTRY_IGNORE(HDASTREAMSTATE, paBDLE),
1004 SSMFIELD_ENTRY_TERM()
1005};
1006#endif
1007
1008/**
1009 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1010 */
1011static uint32_t const g_afMasks[5] =
1012{
1013 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1014};
1015
1016#ifdef IN_RING3
1017DECLINLINE(void) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t u32LPIB)
1018{
1019 AssertPtrReturnVoid(pThis);
1020 AssertPtrReturnVoid(pStrmSt);
1021
1022 Assert(u32LPIB <= pStrmSt->u32CBL);
1023
1024 LogFlowFunc(("uStrm=%RU8, LPIB=%RU32 (DMA Position: %RTbool)\n",
1025 pStrmSt->u8Strm, u32LPIB, RT_BOOL(pThis->u64DPBase & DPBASE_ENABLED)));
1026
1027 /* Update LPIB in any case. */
1028 HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) = u32LPIB;
1029
1030 /* Do we need to tell the current DMA position? */
1031 if (pThis->u64DPBase & DPBASE_ENABLED)
1032 {
1033 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1034 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStrmSt->u8Strm * 8),
1035 (void *)&u32LPIB, sizeof(uint32_t));
1036 AssertRC(rc2);
1037 }
1038}
1039#endif
1040
1041/**
1042 * Retrieves the number of bytes of a FIFOS register.
1043 *
1044 * @return Number of bytes of a given FIFOS register.
1045 */
1046DECLINLINE(uint16_t) hdaSDFIFOSToBytes(uint32_t u32RegFIFOS)
1047{
1048 uint16_t cb;
1049 switch (u32RegFIFOS)
1050 {
1051 /* Input */
1052 case HDA_SDINFIFO_120B: cb = 120; break;
1053 case HDA_SDINFIFO_160B: cb = 160; break;
1054
1055 /* Output */
1056 case HDA_SDONFIFO_16B: cb = 16; break;
1057 case HDA_SDONFIFO_32B: cb = 32; break;
1058 case HDA_SDONFIFO_64B: cb = 64; break;
1059 case HDA_SDONFIFO_128B: cb = 128; break;
1060 case HDA_SDONFIFO_192B: cb = 192; break;
1061 case HDA_SDONFIFO_256B: cb = 256; break;
1062 default:
1063 {
1064 cb = 0;
1065 AssertMsgFailed(("Wrong FIFO value\n"));
1066 break;
1067 }
1068 }
1069
1070 return cb;
1071}
1072
1073/**
1074 * Retrieves the number of bytes of a FIFOW register.
1075 *
1076 * @return Number of bytes of a given FIFOW register.
1077 */
1078DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1079{
1080 uint32_t cb;
1081 switch (u32RegFIFOW)
1082 {
1083 case HDA_SDFIFOW_8B: cb = 8; break;
1084 case HDA_SDFIFOW_16B: cb = 16; break;
1085 case HDA_SDFIFOW_32B: cb = 32; break;
1086 default: cb = 0; break;
1087 }
1088
1089#ifdef RT_STRICT
1090 Assert(RT_IS_POWER_OF_TWO(cb));
1091#endif
1092 return cb;
1093}
1094
1095#ifdef IN_RING3
1096/**
1097 * Returns the current BDLE to use for a stream.
1098 *
1099 * @return BDLE to use, NULL if none found.
1100 */
1101DECLINLINE(PHDABDLE) hdaStreamGetCurrentBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
1102{
1103 AssertPtrReturn(pThis, NULL);
1104 AssertPtrReturn(pStrmSt, NULL);
1105
1106 Assert(pStrmSt->State.paBDLE);
1107 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1108
1109 PHDABDLE pBDLE = &pStrmSt->State.paBDLE[pStrmSt->State.uCurBDLE];
1110 return pBDLE;
1111}
1112
1113/**
1114 * Returns the next BDLE to use for a stream.
1115 *
1116 * @return BDLE to use next, NULL if none found.
1117 */
1118DECLINLINE(PHDABDLE) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
1119{
1120 AssertPtrReturn(pThis, NULL);
1121 AssertPtrReturn(pStrmSt, NULL);
1122
1123 NOREF(pThis);
1124
1125 Assert(pStrmSt->State.paBDLE);
1126 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1127
1128#ifdef DEBUG
1129 uint32_t uOldBDLE = pStrmSt->State.uCurBDLE;
1130#endif
1131
1132 pStrmSt->State.uCurBDLE++;
1133 if (pStrmSt->State.uCurBDLE == pStrmSt->State.cBDLE)
1134 {
1135 pStrmSt->State.uCurBDLE = 0;
1136
1137 hdaStreamUpdateLPIB(pThis, pStrmSt, 0);
1138 }
1139
1140 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1141
1142 PHDABDLE pBDLE = &pStrmSt->State.paBDLE[pStrmSt->State.uCurBDLE];
1143 AssertPtr(pBDLE);
1144
1145 hdaBDLEReset(pBDLE);
1146
1147#ifdef DEBUG
1148 LogFlowFunc(("uOldBDLE=%RU16, uCurBDLE=%RU16 %R[bdle]\n", uOldBDLE, pStrmSt->State.uCurBDLE, pBDLE));
1149#endif
1150 return pBDLE;
1151}
1152#endif
1153
1154/**
1155 * Retrieves the minimum number of bytes accumulated/free in the
1156 * FIFO before the controller will start a fetch/eviction of data.
1157 *
1158 * Uses SDFIFOW (FIFO Watermark Register).
1159 *
1160 * @return Number of bytes accumulated/free in the FIFO.
1161 */
1162DECLINLINE(uint8_t) hdaStreamGetFIFOW(PHDASTATE pThis, PHDASTREAM pStrmSt)
1163{
1164 AssertPtrReturn(pThis, 0);
1165 AssertPtrReturn(pStrmSt, 0);
1166
1167#ifdef VBOX_HDA_WITH_FIFO
1168 return hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, pStrmSt->u8Strm));
1169#else
1170 return 0;
1171#endif
1172}
1173
1174static int hdaProcessInterrupt(PHDASTATE pThis)
1175{
1176#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1177 ( INTCTL_SX((pThis), num) \
1178 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1179
1180 bool fIrq = false;
1181
1182 if (/* Controller Interrupt Enable (CIE). */
1183 HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1184 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1185 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1186 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1187 fIrq = true;
1188
1189 /** @todo Don't hardcode stream numbers here. */
1190 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1191 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1192 {
1193#ifdef IN_RING3
1194 LogFunc(("BCIS\n"));
1195#endif
1196 fIrq = true;
1197 }
1198
1199 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1200 {
1201 LogFunc(("%s\n", fIrq ? "Asserted" : "Deasserted"));
1202 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1203 }
1204
1205#undef IS_INTERRUPT_OCCURED_AND_ENABLED
1206
1207 return VINF_SUCCESS;
1208}
1209
1210/**
1211 * Looks up a register at the exact offset given by @a offReg.
1212 *
1213 * @returns Register index on success, -1 if not found.
1214 * @param pThis The HDA device state.
1215 * @param offReg The register offset.
1216 */
1217static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1218{
1219 /*
1220 * Aliases.
1221 */
1222 if (offReg >= g_aHdaRegAliases[0].offReg)
1223 {
1224 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1225 if (offReg == g_aHdaRegAliases[i].offReg)
1226 return g_aHdaRegAliases[i].idxAlias;
1227 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1228 return -1;
1229 }
1230
1231 /*
1232 * Binary search the
1233 */
1234 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1235 int idxLow = 0;
1236 for (;;)
1237 {
1238 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1239 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1240 {
1241 if (idxLow == idxMiddle)
1242 break;
1243 idxEnd = idxMiddle;
1244 }
1245 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1246 {
1247 idxLow = idxMiddle + 1;
1248 if (idxLow >= idxEnd)
1249 break;
1250 }
1251 else
1252 return idxMiddle;
1253 }
1254
1255#ifdef RT_STRICT
1256 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1257 Assert(g_aHdaRegMap[i].offset != offReg);
1258#endif
1259 return -1;
1260}
1261
1262/**
1263 * Looks up a register covering the offset given by @a offReg.
1264 *
1265 * @returns Register index on success, -1 if not found.
1266 * @param pThis The HDA device state.
1267 * @param offReg The register offset.
1268 */
1269static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1270{
1271 /*
1272 * Aliases.
1273 */
1274 if (offReg >= g_aHdaRegAliases[0].offReg)
1275 {
1276 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1277 {
1278 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1279 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1280 return g_aHdaRegAliases[i].idxAlias;
1281 }
1282 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1283 return -1;
1284 }
1285
1286 /*
1287 * Binary search the register map.
1288 */
1289 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1290 int idxLow = 0;
1291 for (;;)
1292 {
1293 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1294 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1295 {
1296 if (idxLow == idxMiddle)
1297 break;
1298 idxEnd = idxMiddle;
1299 }
1300 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1301 {
1302 idxLow = idxMiddle + 1;
1303 if (idxLow >= idxEnd)
1304 break;
1305 }
1306 else
1307 return idxMiddle;
1308 }
1309
1310#ifdef RT_STRICT
1311 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1312 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1313#endif
1314 return -1;
1315}
1316
1317#ifdef IN_RING3
1318static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1319{
1320 int rc = VINF_SUCCESS;
1321 if (fLocal)
1322 {
1323 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1324 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1325 if (RT_FAILURE(rc))
1326 AssertRCReturn(rc, rc);
1327#ifdef DEBUG_CMD_BUFFER
1328 uint8_t i = 0;
1329 do
1330 {
1331 LogFunc(("CORB%02x: ", i));
1332 uint8_t j = 0;
1333 do
1334 {
1335 const char *pszPrefix;
1336 if ((i + j) == HDA_REG(pThis, CORBRP));
1337 pszPrefix = "[R]";
1338 else if ((i + j) == HDA_REG(pThis, CORBWP));
1339 pszPrefix = "[W]";
1340 else
1341 pszPrefix = " "; /* three spaces */
1342 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1343 j++;
1344 } while (j < 8);
1345 LogFunc(("\n"));
1346 i += 8;
1347 } while(i != 0);
1348#endif
1349 }
1350 else
1351 {
1352 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1353 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1354 if (RT_FAILURE(rc))
1355 AssertRCReturn(rc, rc);
1356#ifdef DEBUG_CMD_BUFFER
1357 uint8_t i = 0;
1358 do {
1359 LogFunc(("RIRB%02x: ", i));
1360 uint8_t j = 0;
1361 do {
1362 const char *prefix;
1363 if ((i + j) == HDA_REG(pThis, RIRBWP))
1364 prefix = "[W]";
1365 else
1366 prefix = " ";
1367 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1368 } while (++j < 8);
1369 LogFunc(("\n"));
1370 i += 8;
1371 } while (i != 0);
1372#endif
1373 }
1374 return rc;
1375}
1376
1377static int hdaCORBCmdProcess(PHDASTATE pThis)
1378{
1379 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1380
1381 int rc = hdaCmdSync(pThis, true);
1382 if (RT_FAILURE(rc))
1383 AssertRCReturn(rc, rc);
1384
1385 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1386 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1387 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1388
1389 Assert((corbWp != corbRp));
1390 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1391
1392 while (corbRp != corbWp)
1393 {
1394 uint32_t cmd;
1395 uint64_t resp;
1396 pfn = NULL;
1397 corbRp++;
1398 cmd = pThis->pu32CorbBuf[corbRp];
1399
1400 rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* Codec index */), &pfn);
1401 if (RT_SUCCESS(rc))
1402 {
1403 AssertPtr(pfn);
1404 rc = pfn(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1405 }
1406
1407 if (RT_FAILURE(rc))
1408 AssertRCReturn(rc, rc);
1409 (rirbWp)++;
1410
1411 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1412 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1413 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1414 {
1415 LogFunc(("unexpected unsolicited response.\n"));
1416 HDA_REG(pThis, CORBRP) = corbRp;
1417 return rc;
1418 }
1419
1420 pThis->pu64RirbBuf[rirbWp] = resp;
1421
1422 pThis->u8RespIntCnt++;
1423 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1424 break;
1425 }
1426 HDA_REG(pThis, CORBRP) = corbRp;
1427 HDA_REG(pThis, RIRBWP) = rirbWp;
1428 rc = hdaCmdSync(pThis, false);
1429 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1430 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1431 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1432 {
1433 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1434
1435 pThis->u8RespIntCnt = 0;
1436 rc = hdaProcessInterrupt(pThis);
1437 }
1438 if (RT_FAILURE(rc))
1439 AssertRCReturn(rc, rc);
1440 return rc;
1441}
1442
1443static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1444{
1445 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1446 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1447
1448 pStrmSt->u8Strm = u8Strm;
1449 pStrmSt->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
1450 HDA_STREAM_REG(pThis, BDPU, u8Strm));
1451 pStrmSt->u16LVI = HDA_STREAM_REG(pThis, LVI, u8Strm);
1452 pStrmSt->u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1453 pStrmSt->u16FIFOS = hdaSDFIFOSToBytes(HDA_STREAM_REG(pThis, FIFOS, u8Strm));
1454
1455 hdaStreamDestroy(pStrmSt);
1456
1457 int rc = VINF_SUCCESS;
1458
1459 if (pStrmSt->u16LVI) /* Any BDLEs to fetch? */
1460 {
1461 uint32_t cbBDLE = 0;
1462
1463 pStrmSt->State.cBDLE = pStrmSt->u16LVI + 1; /* See 18.2.37: If LVI is n, then there are n + 1 entries. */
1464 pStrmSt->State.paBDLE = (PHDABDLE)RTMemAllocZ(sizeof(HDABDLE) * pStrmSt->State.cBDLE);
1465 if (pStrmSt->State.paBDLE)
1466 {
1467 for (uint16_t i = 0; i < pStrmSt->State.cBDLE; i++)
1468 {
1469 rc = hdaBDLEFetch(pThis, &pStrmSt->State.paBDLE[i], pStrmSt->u64BaseDMA, i);
1470 if (RT_FAILURE(rc))
1471 break;
1472
1473 cbBDLE += pStrmSt->State.paBDLE[i].u32BufSize;
1474 }
1475
1476#ifdef DEBUG
1477 hdaBDLEDumpAll(pThis, pStrmSt->u64BaseDMA, pStrmSt->State.cBDLE);
1478#endif
1479 if (RT_SUCCESS(rc))
1480 {
1481 if (pStrmSt->u32CBL != cbBDLE)
1482 LogRel(("HDA: Warning: CBL (%RU32) does not match BDL entries (%RU32); expect sound hickups\n",
1483 pStrmSt->u32CBL, cbBDLE));
1484
1485 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1486 }
1487 }
1488 else
1489 rc = VERR_NO_MEMORY;
1490 }
1491
1492 LogFunc(("[SD%RU8]: DMA=0x%x, LVI=%RU16, CBL=%RU32, FIFOS=%RU16\n",
1493 u8Strm, pStrmSt->u64BaseDMA, pStrmSt->u16LVI, pStrmSt->u32CBL, pStrmSt->u16FIFOS));
1494
1495 return rc;
1496}
1497
1498static void hdaStreamDestroy(PHDASTREAM pStrmSt)
1499{
1500 AssertPtrReturnVoid(pStrmSt);
1501
1502 if (pStrmSt->State.paBDLE)
1503 {
1504 Assert(pStrmSt->State.cBDLE);
1505 RTMemFree(pStrmSt->State.paBDLE);
1506 pStrmSt->State.paBDLE = NULL;
1507 }
1508
1509 pStrmSt->State.cBDLE = 0;
1510}
1511#endif
1512
1513static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1514{
1515 AssertPtrReturnVoid(pThis);
1516 AssertPtrReturnVoid(pStrmSt);
1517 AssertReturnVoid(u8Strm <= 7); /** @todo Use a define for MAX_STRAEMS! */
1518
1519 /*
1520 * Initialize stream state.
1521 */
1522 RT_BZERO(pStrmSt, sizeof(HDASTREAM));
1523
1524 /*
1525 * Initialize registers.
1526 */
1527 HDA_STREAM_REG(pThis, STS, u8Strm) = 0;
1528 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1529 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1530 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1531
1532 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39. */
1533 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1534 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1535 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = HDA_SDFIFOW_32B;
1536 HDA_STREAM_REG(pThis, LPIB, u8Strm) = 0;
1537 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1538 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1539 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1540 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1541 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1542
1543 LogFunc(("[SD%RU8] Reset\n", u8Strm));
1544}
1545
1546/* Register access handlers. */
1547
1548static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1549{
1550 *pu32Value = 0;
1551 return VINF_SUCCESS;
1552}
1553
1554static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1555{
1556 return VINF_SUCCESS;
1557}
1558
1559/* U8 */
1560static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1561{
1562 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1563 return hdaRegReadU32(pThis, iReg, pu32Value);
1564}
1565
1566static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1567{
1568 Assert((u32Value & 0xffffff00) == 0);
1569 return hdaRegWriteU32(pThis, iReg, u32Value);
1570}
1571
1572/* U16 */
1573static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1574{
1575 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1576 return hdaRegReadU32(pThis, iReg, pu32Value);
1577}
1578
1579static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1580{
1581 Assert((u32Value & 0xffff0000) == 0);
1582 return hdaRegWriteU32(pThis, iReg, u32Value);
1583}
1584
1585/* U24 */
1586static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1587{
1588 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1589 return hdaRegReadU32(pThis, iReg, pu32Value);
1590}
1591
1592static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1593{
1594 Assert((u32Value & 0xff000000) == 0);
1595 return hdaRegWriteU32(pThis, iReg, u32Value);
1596}
1597
1598/* U32 */
1599static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1600{
1601 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1602
1603 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1604 return VINF_SUCCESS;
1605}
1606
1607static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1608{
1609 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1610
1611 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1612 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1613 return VINF_SUCCESS;
1614}
1615
1616static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1617{
1618 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1619 {
1620 /* Exit reset state. */
1621 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1622 pThis->fInReset = false;
1623 }
1624 else
1625 {
1626#ifdef IN_RING3
1627 /* Enter reset state. */
1628 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1629 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1630 {
1631 LogFunc(("HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1632 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1633 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1634 }
1635 hdaReset(pThis->CTX_SUFF(pDevIns));
1636 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1637 pThis->fInReset = true;
1638#else
1639 return VINF_IOM_R3_MMIO_WRITE;
1640#endif
1641 }
1642 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1643 {
1644 /* Flush: GSTS:1 set, see 6.2.6. */
1645 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
1646 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1647 }
1648 return VINF_SUCCESS;
1649}
1650
1651static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1652{
1653 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1654
1655 uint32_t v = pThis->au32Regs[iRegMem];
1656 uint32_t nv = u32Value & HDA_STATES_SCSF;
1657 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1658 return VINF_SUCCESS;
1659}
1660
1661static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1662{
1663 uint32_t v = 0;
1664 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1665 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1666 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1667 || HDA_REG(pThis, STATESTS))
1668 {
1669 v |= RT_BIT(30); /* Touch CIS. */
1670 }
1671
1672#define HDA_IS_STREAM_EVENT(pThis, num) \
1673 ( (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1674 || (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1675 || (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1676
1677#define HDA_MARK_STREAM(pThis, num, v) \
1678 do { (v) |= HDA_IS_STREAM_EVENT((pThis), num) ? RT_BIT((num)) : 0; } while(0)
1679
1680 HDA_MARK_STREAM(pThis, 0, v);
1681 HDA_MARK_STREAM(pThis, 1, v);
1682 HDA_MARK_STREAM(pThis, 2, v);
1683 HDA_MARK_STREAM(pThis, 3, v);
1684 HDA_MARK_STREAM(pThis, 4, v);
1685 HDA_MARK_STREAM(pThis, 5, v);
1686 HDA_MARK_STREAM(pThis, 6, v);
1687 HDA_MARK_STREAM(pThis, 7, v);
1688
1689#undef HDA_IS_STREAM_EVENT
1690#undef HDA_MARK_STREAM
1691
1692 v |= v ? RT_BIT(31) : 0;
1693
1694 *pu32Value = v;
1695 return VINF_SUCCESS;
1696}
1697
1698static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1699{
1700 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1701 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1702 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1703
1704 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
1705
1706 *pu32Value = u32LPIB;
1707 return VINF_SUCCESS;
1708}
1709
1710static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1711{
1712 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1713 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1714 - pThis->u64BaseTS, 24, 1000);
1715 return VINF_SUCCESS;
1716}
1717
1718static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1719{
1720 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1721 {
1722 HDA_REG(pThis, CORBRP) = 0;
1723 }
1724#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1725 else
1726 return hdaRegWriteU8(pThis, iReg, u32Value);
1727#endif
1728 return VINF_SUCCESS;
1729}
1730
1731static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1732{
1733#ifdef IN_RING3
1734 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1735 AssertRC(rc);
1736 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1737 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1738 {
1739 return hdaCORBCmdProcess(pThis);
1740 }
1741 return rc;
1742#else
1743 return VINF_IOM_R3_MMIO_WRITE;
1744#endif
1745}
1746
1747static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1748{
1749 uint32_t v = HDA_REG(pThis, CORBSTS);
1750 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1751 return VINF_SUCCESS;
1752}
1753
1754static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1755{
1756#ifdef IN_RING3
1757 int rc;
1758 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1759 if (RT_FAILURE(rc))
1760 AssertRCReturn(rc, rc);
1761 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1762 return VINF_SUCCESS;
1763 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1764 return VINF_SUCCESS;
1765 rc = hdaCORBCmdProcess(pThis);
1766 return rc;
1767#else
1768 return VINF_IOM_R3_MMIO_WRITE;
1769#endif
1770}
1771
1772static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1773{
1774 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CBL, iReg);
1775 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1776
1777 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32Value));
1778
1779 return hdaRegWriteU32(pThis, iReg, u32Value);
1780}
1781
1782static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1783{
1784 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1785 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1786 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1787 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1788
1789 uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1790
1791 PHDASTREAM pStrmSt;
1792 switch (u8Strm)
1793 {
1794 case 0: /** @todo Use dynamic indices, based on stream assignment. */
1795 {
1796 pStrmSt = &pThis->StrmStLineIn;
1797 break;
1798 }
1799# ifdef VBOX_WITH_HDA_MIC_IN
1800 case 2: /** @todo Use dynamic indices, based on stream assignment. */
1801 {
1802 pStrmSt = &pThis->StrmStMicIn;
1803 break;
1804 }
1805# endif
1806 case 4: /** @todo Use dynamic indices, based on stream assignment. */
1807 {
1808 pStrmSt = &pThis->StrmStOut;
1809 break;
1810 }
1811
1812 default:
1813 {
1814 LogFunc(("Warning: Changing SDCTL on non-attached stream (iReg=0x%x)\n", iReg));
1815 return hdaRegWriteU24(pThis, iReg, u32Value); /* Write 3 bytes. */
1816 }
1817 }
1818
1819 LogFunc(("[SD%RU8]: %R[sdctl]\n", u8Strm, u32Value));
1820
1821 if (fInReset)
1822 {
1823 /* Guest is resetting HDA's stream, we're expecting guest will mark stream as exit. */
1824 Assert(!fReset);
1825 LogFunc(("Guest initiated exit of stream reset\n"));
1826 }
1827 else if (fReset)
1828 {
1829#ifdef IN_RING3
1830 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1831 Assert(!fInRun && !fRun);
1832
1833 LogFunc(("Guest initiated enter to stream reset\n"));
1834 hdaStreamReset(pThis, pStrmSt, u8Strm);
1835#else
1836 return VINF_IOM_R3_MMIO_WRITE;
1837#endif
1838 }
1839 else
1840 {
1841#ifdef IN_RING3
1842 /*
1843 * We enter here to change DMA states only.
1844 */
1845 if (fInRun != fRun)
1846 {
1847 Assert(!fReset && !fInReset);
1848
1849 PHDADRIVER pDrv;
1850 switch (u8Strm)
1851 {
1852 case 0: /** @todo Use a variable here. Later. */
1853 {
1854 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1855 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1856 pDrv->LineIn.pStrmIn, fRun);
1857 break;
1858 }
1859# ifdef VBOX_WITH_HDA_MIC_IN
1860 case 2: /** @todo Use a variable here. Later. */
1861 {
1862 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1863 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1864 pDrv->MicIn.pStrmIn, fRun);
1865 break;
1866 }
1867# endif
1868 case 4: /** @todo Use a variable here. Later. */
1869 {
1870 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1871 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1872 pDrv->Out.pStrmOut, fRun);
1873 break;
1874 }
1875 default:
1876 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1877 break;
1878 }
1879 }
1880
1881 if (pStrmSt)
1882 {
1883 int rc2 = hdaStreamInit(pThis, pStrmSt, u8Strm);
1884 AssertRC(rc2);
1885 }
1886
1887#else /* !IN_RING3 */
1888 return VINF_IOM_R3_MMIO_WRITE;
1889#endif /* IN_RING3 */
1890 }
1891
1892 return hdaRegWriteU24(pThis, iReg, u32Value);
1893}
1894
1895static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1896{
1897 uint32_t v = HDA_REG_IND(pThis, iReg);
1898 v &= ~(u32Value & v);
1899 HDA_REG_IND(pThis, iReg) = v;
1900 hdaProcessInterrupt(pThis);
1901 return VINF_SUCCESS;
1902}
1903
1904static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1905{
1906 /* Only can be modified if RUN bit is 0. */
1907 bool fIsRunning = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1908 if (fIsRunning)
1909 {
1910 AssertMsgFailed(("Cannot write to register when RUN bit is set\n"));
1911 return VINF_SUCCESS;
1912 }
1913
1914 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1915 if (RT_FAILURE(rc))
1916 AssertRCReturn(rc, VINF_SUCCESS);
1917 return rc;
1918}
1919
1920static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1921{
1922 switch (u32Value)
1923 {
1924 case HDA_SDFIFOW_8B:
1925 case HDA_SDFIFOW_16B:
1926 case HDA_SDFIFOW_32B:
1927 return hdaRegWriteU16(pThis, iReg, u32Value);
1928 default:
1929 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1930 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1931 }
1932 return VINF_SUCCESS; /* Never reached. */
1933}
1934
1935/**
1936 * @note This method could be called for changing value on Output Streams
1937 * only (ICH6 datasheet 18.2.39).
1938 */
1939static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1940{
1941 /** @todo Only allow updating FIFOS if RUN bit is 0? */
1942 uint32_t u32FIFOS = 0;
1943
1944 switch (iReg)
1945 {
1946 /* SDInFIFOS is RO, n=0-3. */
1947 case HDA_REG_SD0FIFOS:
1948 case HDA_REG_SD1FIFOS:
1949 case HDA_REG_SD2FIFOS:
1950 case HDA_REG_SD3FIFOS:
1951 {
1952 LogFunc(("Guest tries to change R/O value of FIFO size of input stream, ignoring\n"));
1953 break;
1954 }
1955 case HDA_REG_SD4FIFOS:
1956 case HDA_REG_SD5FIFOS:
1957 case HDA_REG_SD6FIFOS:
1958 case HDA_REG_SD7FIFOS:
1959 {
1960 switch(u32Value)
1961 {
1962 case HDA_SDONFIFO_16B:
1963 case HDA_SDONFIFO_32B:
1964 case HDA_SDONFIFO_64B:
1965 case HDA_SDONFIFO_128B:
1966 case HDA_SDONFIFO_192B:
1967 u32FIFOS = u32Value;
1968 break;
1969
1970 case HDA_SDONFIFO_256B: /** @todo r=andy Investigate this. */
1971 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1972 /* Fall through is intentional. */
1973 default:
1974 u32FIFOS = HDA_SDONFIFO_192B;
1975 break;
1976 }
1977
1978 break;
1979 }
1980 default:
1981 {
1982 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
1983 break;
1984 }
1985 }
1986
1987 if (u32FIFOS)
1988 {
1989 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", 0, hdaSDFIFOSToBytes(u32FIFOS)));
1990 /** @todo Update internal stream state with new FIFOS. */
1991
1992 return hdaRegWriteU16(pThis, iReg, u32FIFOS);
1993 }
1994
1995 return VINF_SUCCESS;
1996}
1997
1998#ifdef IN_RING3
1999static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
2000{
2001 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2002
2003# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2004
2005 int rc = VINF_SUCCESS;
2006
2007 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
2008 uint32_t u32HzMult = 1;
2009 uint32_t u32HzDiv = 1;
2010
2011 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2012 {
2013 case 0: u32HzMult = 1; break;
2014 case 1: u32HzMult = 2; break;
2015 case 2: u32HzMult = 3; break;
2016 case 3: u32HzMult = 4; break;
2017 default:
2018 LogFunc(("Unsupported multiplier %x\n",
2019 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2020 rc = VERR_NOT_SUPPORTED;
2021 break;
2022 }
2023 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2024 {
2025 case 0: u32HzDiv = 1; break;
2026 case 1: u32HzDiv = 2; break;
2027 case 2: u32HzDiv = 3; break;
2028 case 3: u32HzDiv = 4; break;
2029 case 4: u32HzDiv = 5; break;
2030 case 5: u32HzDiv = 6; break;
2031 case 6: u32HzDiv = 7; break;
2032 case 7: u32HzDiv = 8; break;
2033 default:
2034 LogFunc(("Unsupported divisor %x\n",
2035 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2036 rc = VERR_NOT_SUPPORTED;
2037 break;
2038 }
2039
2040 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
2041 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2042 {
2043 case 0:
2044 LogFunc(("Requested 8-bit\n"));
2045 enmFmt = AUD_FMT_S8;
2046 break;
2047 case 1:
2048 LogFunc(("Requested 16-bit\n"));
2049 enmFmt = AUD_FMT_S16;
2050 break;
2051 case 2:
2052 LogFunc(("Requested 20-bit\n"));
2053 break;
2054 case 3:
2055 LogFunc(("Requested 24-bit\n"));
2056 break;
2057 case 4:
2058 LogFunc(("Requested 32-bit\n"));
2059 enmFmt = AUD_FMT_S32;
2060 break;
2061 default:
2062 AssertMsgFailed(("Unsupported bits shift %x\n",
2063 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2064 rc = VERR_NOT_SUPPORTED;
2065 break;
2066 }
2067
2068 if (RT_SUCCESS(rc))
2069 {
2070 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2071 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
2072 pCfg->enmFormat = enmFmt;
2073 pCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2074 }
2075
2076# undef EXTRACT_VALUE
2077
2078 LogFlowFuncLeaveRC(rc);
2079 return rc;
2080}
2081#endif
2082
2083static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2084{
2085#ifdef IN_RING3
2086# ifdef VBOX_WITH_HDA_CODEC_EMU
2087 /* No reason to reopen voice with same settings. */
2088 if (u32Value == HDA_REG_IND(pThis, iReg))
2089 return VINF_SUCCESS;
2090
2091 PDMAUDIOSTREAMCFG as;
2092 int rc = hdaSdFmtToAudSettings(u32Value, &as);
2093 if (RT_FAILURE(rc))
2094 return rc;
2095
2096 PHDADRIVER pDrv;
2097 switch (iReg)
2098 {
2099 case HDA_REG_SD0FMT:
2100 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2101 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &as);
2102 break;
2103# ifdef VBOX_WITH_HDA_MIC_IN
2104 case HDA_REG_SD2FMT:
2105 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2106 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &as);
2107 break;
2108# endif
2109 default:
2110 LogFunc(("Warning: Attempt to change format on register %d\n", iReg));
2111 break;
2112 }
2113
2114 /** @todo r=andy rc gets lost; needs fixing. */
2115 return hdaRegWriteU16(pThis, iReg, u32Value);
2116# else /* !VBOX_WITH_HDA_CODEC_EMU */
2117 return hdaRegWriteU16(pThis, iReg, u32Value);
2118# endif
2119#else /* !IN_RING3 */
2120 return VINF_IOM_R3_MMIO_WRITE;
2121#endif
2122}
2123
2124static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2125{
2126 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2127 if (RT_FAILURE(rc))
2128 AssertRCReturn(rc, VINF_SUCCESS);
2129 return rc;
2130}
2131
2132static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2133{
2134 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2135 if (RT_FAILURE(rc))
2136 AssertRCReturn(rc, VINF_SUCCESS);
2137 return rc;
2138}
2139
2140static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2141{
2142 int rc = VINF_SUCCESS;
2143 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2144 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2145 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2146 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2147
2148 rc = hdaRegReadU32(pThis, iReg, pu32Value);
2149 return rc;
2150}
2151
2152static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2153{
2154 int rc = VINF_SUCCESS;
2155
2156 /*
2157 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2158 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2159 */
2160 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
2161 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
2162 {
2163#ifdef IN_RING3
2164 PFNHDACODECVERBPROCESSOR pfn = NULL;
2165 uint64_t resp;
2166 uint32_t cmd = HDA_REG(pThis, IC);
2167 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2168 {
2169 /*
2170 * 3.4.3 defines behavior of immediate Command status register.
2171 */
2172 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
2173 return rc;
2174 }
2175 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2176 LogFunc(("IC:%x\n", cmd));
2177
2178 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
2179 HDA_CODEC_CMD(cmd, 0 /* LUN */),
2180 &pfn);
2181 if (RT_FAILURE(rc))
2182 AssertRCReturn(rc, rc);
2183 rc = pfn(pThis->pCodec,
2184 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
2185 if (RT_FAILURE(rc))
2186 AssertRCReturn(rc, rc);
2187
2188 HDA_REG(pThis, IR) = (uint32_t)resp;
2189 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
2190 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
2191 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
2192#else /* !IN_RING3 */
2193 rc = VINF_IOM_R3_MMIO_WRITE;
2194#endif
2195 return rc;
2196 }
2197 /*
2198 * Once the guest read the response, it should clean the IRV bit of the IRS register.
2199 */
2200 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
2201 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
2202 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
2203 return rc;
2204}
2205
2206static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2207{
2208 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
2209 {
2210 HDA_REG(pThis, RIRBWP) = 0;
2211 }
2212 /* The remaining bits are O, see 6.2.22 */
2213 return VINF_SUCCESS;
2214}
2215
2216static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2217{
2218 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2219 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2220 if (RT_FAILURE(rc))
2221 AssertRCReturn(rc, rc);
2222
2223 switch(iReg)
2224 {
2225 case HDA_REG_CORBLBASE:
2226 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2227 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
2228 break;
2229 case HDA_REG_CORBUBASE:
2230 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2231 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2232 break;
2233 case HDA_REG_RIRBLBASE:
2234 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2235 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
2236 break;
2237 case HDA_REG_RIRBUBASE:
2238 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2239 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2240 break;
2241 case HDA_REG_DPLBASE:
2242 /** @todo: first bit has special meaning */
2243 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
2244 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
2245 break;
2246 case HDA_REG_DPUBASE:
2247 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
2248 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2249 break;
2250 default:
2251 AssertMsgFailed(("Invalid index"));
2252 break;
2253 }
2254
2255 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2256 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2257 return rc;
2258}
2259
2260static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2261{
2262 uint8_t v = HDA_REG(pThis, RIRBSTS);
2263 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2264
2265 return hdaProcessInterrupt(pThis);
2266}
2267
2268#ifdef IN_RING3
2269#ifdef LOG_ENABLED
2270static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE)
2271{
2272 uint32_t cbBDLE = 0;
2273
2274 for (uint16_t i = 0; i < cBDLE; i++)
2275 {
2276 uint8_t bdle[16]; /** @todo Use a define. */
2277 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * 16, bdle, 16); /** @todo Use a define. */
2278
2279 uint64_t addr = *(uint64_t *)bdle;
2280 uint32_t len = *(uint32_t *)&bdle[8];
2281 uint32_t ioc = *(uint32_t *)&bdle[12];
2282
2283 LogFlowFunc(("#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
2284 i, addr, len, RT_BOOL(ioc & 0x1)));
2285
2286 cbBDLE += len;
2287 }
2288
2289 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
2290
2291 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
2292 return;
2293
2294 for (int i = 0; i < 8; i++) /** @todo Use a define. */
2295 {
2296 uint32_t uDMACnt;
2297 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i * 8, /** @todo Use a define. */
2298 &uDMACnt, sizeof(&uDMACnt));
2299
2300 LogFlowFunc(("%s #%02d STREAM(0x%x)\n",
2301 i == HDA_SDCTL_NUM(pThis, 4) || i == HDA_SDCTL_NUM(pThis, 0) ? "*" : " ", i , uDMACnt));
2302 }
2303}
2304#endif
2305
2306/**
2307 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
2308 *
2309 * @param pThis Pointer to HDA state.
2310 * @param pBDLE Where to store the fetched result.
2311 * @param u64BaseDMA Address base of DMA engine to use.
2312 * @param u16Entry BDLE entry to fetch.
2313 */
2314static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
2315{
2316 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2317 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
2318 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
2319 /** @todo Compare u16Entry with LVI. */
2320
2321 uint8_t uBundleEntry[16]; /** @todo Define a BDLE length. */
2322 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * 16, /** @todo Define a BDLE length. */
2323 uBundleEntry, RT_ELEMENTS(uBundleEntry));
2324 if (RT_FAILURE(rc))
2325 return rc;
2326
2327 pBDLE->State.u32BDLIndex = u16Entry;
2328 pBDLE->u64BufAdr = *(uint64_t *) uBundleEntry;
2329 pBDLE->u32BufSize = *(uint32_t *)&uBundleEntry[8];
2330 if (pBDLE->u32BufSize < sizeof(uint16_t)) /* Must be at least one word. */
2331 return VERR_INVALID_STATE;
2332
2333 pBDLE->fIntOnCompletion = (*(uint32_t *)&uBundleEntry[12]) & 0x1;
2334
2335 return VINF_SUCCESS;
2336}
2337
2338static void hdaBDLEReset(PHDABDLE pBDLE)
2339{
2340 AssertPtrReturnVoid(pBDLE);
2341
2342 pBDLE->State.u32BufOff = 0;
2343 pBDLE->State.cbBelowFIFOW = 0;
2344}
2345
2346/**
2347 * Returns the number of outstanding stream data bytes which need to be processed
2348 * by the DMA engine assigned to this stream.
2349 *
2350 * @return Number of bytes for the DMA engine to process.
2351 */
2352DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStrmSt)
2353{
2354 AssertPtrReturn(pThis, 0);
2355 AssertPtrReturn(pStrmSt, 0);
2356
2357 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2358
2359 uint32_t cbFree = pStrmSt->u32CBL - HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2360 if (cbFree)
2361 {
2362 /* Limit to the available free space of the current BDLE. */
2363 cbFree = RT_MIN(cbFree, pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2364
2365 /* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
2366 cbFree = RT_MIN(cbFree, pStrmSt->u16FIFOS);
2367
2368 if (pBDLE->State.cbBelowFIFOW)
2369 {
2370 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
2371 * No need to read data from DMA then. */
2372 if (cbFree > pBDLE->State.cbBelowFIFOW)
2373 {
2374 /* Subtract the amount of bytes that still would fit in the stream's FIFO
2375 * and therefore do not need to be processed by DMA. */
2376 cbFree -= pBDLE->State.cbBelowFIFOW;
2377 }
2378 }
2379
2380 Log(("HDADEBUG: cb2Copy=%RU32, CVI(len:%RU32, pos:%RU32), CBLL=%RU32, FIFOS=%RU32, Avail=%RU32\n",
2381 cbFree, pBDLE->u32BufSize, pBDLE->State.u32BufOff, pStrmSt->u32CBL - HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), pStrmSt->u16FIFOS, 0));
2382 }
2383
2384 LogFlowFunc(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, cbFree=%RU32, %R[bdle]\n", pStrmSt->u8Strm,
2385 pStrmSt->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), cbFree, pBDLE));
2386 return cbFree;
2387}
2388
2389DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
2390{
2391 AssertPtrReturnVoid(pBDLE);
2392
2393 if (!cbData || !cbProcessed)
2394 return;
2395
2396 /* Fewer than cbBelowFIFOW bytes were copied.
2397 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2398 * where it might happen. */
2399 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
2400 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
2401 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
2402
2403#if 0
2404 if ( pBDLE->State.cbBelowFIFOW
2405 && pBDLE->State.cbBelowFIFOW <= cbWritten)
2406 {
2407 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
2408 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->u32BufSize));
2409 }
2410#endif
2411
2412 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
2413 Assert(pBDLE->State.cbBelowFIFOW == 0);
2414
2415 /* We always increment the position of DMA buffer counter because we're always reading
2416 * into an intermediate buffer. */
2417 pBDLE->State.u32BufOff += cbData;
2418 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2419
2420 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
2421}
2422
2423DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
2424{
2425 AssertPtrReturn(pThis, false);
2426 AssertPtrReturn(pStrmSt, false);
2427
2428 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2429 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2430
2431 /* Did we reach the CBL (Cyclic Buffer List) limit? */
2432 bool fCBLLimitReached = u32LPIB >= pStrmSt->u32CBL;
2433
2434 /* Do we need to use the next BDLE entry? Either because we reached
2435 * the CBL limit or our internal DMA buffer is full. */
2436 bool fNeedsNextBDLE = ( fCBLLimitReached
2437 || pBDLE->State.u32BufOff >= pBDLE->u32BufSize);
2438
2439 Assert(u32LPIB <= pStrmSt->u32CBL);
2440 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2441
2442 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
2443 pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
2444
2445 if (fCBLLimitReached)
2446 {
2447 /* Reset LPIB register. */
2448 u32LPIB -= RT_MIN(u32LPIB, pStrmSt->u32CBL);
2449 hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2450 }
2451
2452 if (fNeedsNextBDLE)
2453 {
2454 /* Reset current BDLE. */
2455 hdaBDLEReset(pBDLE);
2456 }
2457
2458 return fNeedsNextBDLE;
2459}
2460
2461DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbInc)
2462{
2463 AssertPtrReturnVoid(pThis);
2464 AssertPtrReturnVoid(pStrmSt);
2465
2466 LogFlowFunc(("[SD%RU8]: cbInc=%RU32\n", pStrmSt->u8Strm, cbInc));
2467
2468 Assert(cbInc <= pStrmSt->u16FIFOS);
2469
2470 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2471
2472 /*
2473 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
2474 * doesn't fetch anything via DMA, so just update LPIB.
2475 * (ICH6 datasheet 18.2.38).
2476 */
2477 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
2478 {
2479 const uint32_t u32LPIB = RT_MIN(HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2480 pStrmSt->u32CBL);
2481
2482 LogFlowFunc(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
2483 pStrmSt->u8Strm,
2484 HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2485 pStrmSt->u32CBL));
2486
2487 hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2488 }
2489}
2490
2491static bool hdaStreamTransferIsComplete(PHDASTATE pThis, PHDASTREAM pStrmSt)
2492{
2493 AssertPtrReturn(pThis, true);
2494 AssertPtrReturn(pStrmSt, true);
2495
2496 bool fIsComplete = false;
2497
2498 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2499 const uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2500
2501 if ( pBDLE->State.u32BufOff >= pBDLE->u32BufSize
2502 || u32LPIB >= pStrmSt->u32CBL)
2503 {
2504 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2505 Assert(u32LPIB <= pStrmSt->u32CBL);
2506
2507 if (/* IOC (Interrupt On Completion) bit set? */
2508 pBDLE->fIntOnCompletion
2509 /* All data put into the DMA FIFO? */
2510 && pBDLE->State.cbBelowFIFOW == 0
2511 )
2512 {
2513 /**
2514 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
2515 * last byte of data for the current descriptor has been fetched
2516 * from memory and put into the DMA FIFO.
2517 *
2518 ** @todo More carefully investigate BCIS flag.
2519 *
2520 * Speech synthesis works fine on Mac Guest if this bit isn't set
2521 * but in general sound quality gets worse.
2522 */
2523 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2524
2525 /*
2526 * If the ICE (IOCE, "Interrupt On Completion Enable") bit of the SDCTL register is set
2527 * we need to generate an interrupt.
2528 */
2529 if (HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2530 hdaProcessInterrupt(pThis);
2531 }
2532
2533 fIsComplete = true;
2534 }
2535
2536 LogFlowFunc(("[SD%RU8]: u32LPIB=%RU32, CBL=%RU32, %R[bdle] => %s\n",
2537 pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, pBDLE, fIsComplete ? "COMPLETE" : "INCOMPLETE"));
2538
2539 return fIsComplete;
2540}
2541
2542/**
2543 * hdaReadAudio - copies samples from audio backend to DMA.
2544 * Note: This function writes to the DMA buffer immediately,
2545 * but "reports bytes" when all conditions are met (FIFOW).
2546 */
2547static int hdaReadAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, PAUDMIXSINK pSink, uint32_t *pcbRead)
2548{
2549 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2550 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2551 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
2552 /* pcbRead is optional. */
2553
2554 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2555
2556 int rc;
2557 uint32_t cbRead = 0;
2558 uint32_t cbBuf = hdaStreamGetTransferSize(pThis, pStrmSt);
2559
2560 LogFlowFunc(("cbBuf=%RU32, %R[bdle]\n", cbBuf, pBDLE));
2561
2562 if (!cbBuf)
2563 {
2564 /* Nothing to write, bail out. */
2565 rc = VERR_NO_DATA;
2566 }
2567 else
2568 {
2569 uint32_t cbReadFromSink = 0;
2570 rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pBDLE->State.au8FIFO, cbBuf, &cbReadFromSink);
2571 if (RT_SUCCESS(rc))
2572 {
2573 Assert(cbReadFromSink);
2574 Assert(cbReadFromSink == cbBuf);
2575 Assert(cbReadFromSink <= pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2576
2577 /*
2578 * Write to the BDLE's DMA buffer.
2579 */
2580 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2581 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2582 pBDLE->State.au8FIFO, cbReadFromSink);
2583 AssertRC(rc);
2584
2585 if (pBDLE->State.cbBelowFIFOW + cbReadFromSink > hdaStreamGetFIFOW(pThis, pStrmSt))
2586 {
2587 pBDLE->State.u32BufOff += cbReadFromSink;
2588 pBDLE->State.cbBelowFIFOW = 0;
2589 //hdaBackendReadTransferReported(pBDLE, cbDMAData, cbRead, &cbRead, pcbAvail);
2590 }
2591 else
2592 {
2593 pBDLE->State.u32BufOff += cbReadFromSink;
2594 pBDLE->State.cbBelowFIFOW += cbReadFromSink;
2595 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2596 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbRead, pcbAvail);
2597
2598 rc = VERR_NO_DATA;
2599 }
2600 }
2601 }
2602
2603 //Assert(cbRead <= (SDFIFOS(pThis, pStrmSt->u8Strm) + 1));
2604
2605 LogFunc(("BDLE(off:%RU32, size:%RU32), cbTransferred=%RU32, rc=%Rrc\n",
2606 pBDLE->State.u32BufOff, pBDLE->u32BufSize, cbRead, rc));
2607
2608 if (RT_SUCCESS(rc))
2609 {
2610 if (pcbRead)
2611 *pcbRead = cbRead;
2612 }
2613
2614 return rc;
2615}
2616
2617static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t *pcbWritten)
2618{
2619 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2620 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2621 AssertPtrReturn(pcbWritten, VERR_INVALID_POINTER);
2622 /* pcbWritten is optional. */
2623
2624 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2625 int rc;
2626
2627 uint32_t cbWritten = 0;
2628 uint32_t cbData = hdaStreamGetTransferSize(pThis, pStrmSt);
2629
2630 LogFlowFunc(("cbData=%RU32, %R[bdle]\n", cbData, pBDLE));
2631
2632 /*
2633 * Copy from DMA to the corresponding stream buffer (if there are any bytes from the
2634 * previous unreported transfer we write at offset 'pBDLE->State.cbUnderFifoW').
2635 */
2636 if (!cbData)
2637 {
2638 rc = VINF_EOF;
2639 }
2640 else
2641 {
2642 /*
2643 * Read from the current BDLE's DMA buffer.
2644 */
2645 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2646 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2647 pBDLE->State.au8FIFO + pBDLE->State.cbBelowFIFOW, cbData);
2648 AssertRC(rc);
2649
2650#ifdef VBOX_WITH_STATISTICS
2651 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbData);
2652#endif
2653 /*
2654 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2655 */
2656 uint32_t cbToWrite = cbData + pBDLE->State.cbBelowFIFOW;
2657 if (cbToWrite >= hdaStreamGetFIFOW(pThis, pStrmSt))
2658 {
2659 uint32_t cbWrittenToStream;
2660 int rc2;
2661
2662 PHDADRIVER pDrv;
2663 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2664 {
2665 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2666 {
2667 rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2668 pBDLE->State.au8FIFO, cbToWrite, &cbWrittenToStream);
2669 if (RT_SUCCESS(rc2))
2670 {
2671 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2672 LogFlowFunc(("\tLUN#%RU8: Warning: Only written %RU32 / %RU32 bytes, expect lags\n",
2673 pDrv->uLUN, cbWrittenToStream, cbToWrite));
2674 }
2675 }
2676 else /* Stream disabled, not fatal. */
2677 {
2678 cbWrittenToStream = 0;
2679 rc2 = VERR_NOT_AVAILABLE;
2680 /* Keep going. */
2681 }
2682
2683 LogFlowFunc(("\tLUN#%RU8: cbToWrite=%RU32, cbWrittenToStream=%RU32, rc=%Rrc\n",
2684 pDrv->uLUN, cbToWrite, cbWrittenToStream, rc2));
2685 }
2686
2687 /* Always report all data as being written;
2688 * backends who were not able to catch up have to deal with it themselves. */
2689 cbWritten = cbToWrite;
2690
2691 hdaBDLEUpdate(pBDLE, cbData, cbWritten);
2692 }
2693 else
2694 {
2695 pBDLE->State.u32BufOff += cbWritten;
2696 pBDLE->State.cbBelowFIFOW += cbWritten;
2697 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2698
2699 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2700 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbAvail, NULL);
2701 rc = VINF_EOF;
2702 }
2703 }
2704
2705 Assert(cbWritten <= pStrmSt->u16FIFOS);
2706
2707 if (RT_SUCCESS(rc))
2708 {
2709 if (pcbWritten)
2710 *pcbWritten = cbWritten;
2711 }
2712
2713 LogFunc(("Returning cbWritten=%RU32, rc=%Rrc\n", cbWritten, rc));
2714 return rc;
2715}
2716
2717/**
2718 * @interface_method_impl{HDACODEC,pfnReset}
2719 */
2720static DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2721{
2722 PHDASTATE pThis = pCodec->pHDAState;
2723 NOREF(pThis);
2724 return VINF_SUCCESS;
2725}
2726
2727
2728static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2729{
2730 NOREF(pThis);
2731 NOREF(enmRecSource);
2732 LogFlowFuncEnter();
2733}
2734
2735static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2736{
2737 NOREF(pThis);
2738 LogFlowFuncEnter();
2739}
2740
2741static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2742 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2743 PPDMAUDIOSTREAMCFG pCfg)
2744{
2745 PAUDMIXSINK pSink;
2746
2747 switch (enmRecSource)
2748 {
2749# ifdef VBOX_WITH_HDA_MIC_IN
2750 case PDMAUDIORECSOURCE_MIC:
2751 pSink = pThis->pSinkMicIn;
2752 break;
2753# endif
2754 case PDMAUDIORECSOURCE_LINE_IN:
2755 pSink = pThis->pSinkLineIn;
2756 break;
2757 default:
2758 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2759 return VERR_NOT_SUPPORTED;
2760 }
2761
2762 int rc = VINF_SUCCESS;
2763 char *pszDesc;
2764
2765 PHDADRIVER pDrv;
2766 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2767 {
2768 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2769 {
2770 rc = VERR_NO_MEMORY;
2771 break;
2772 }
2773
2774 rc = pDrv->pConnector->pfnCreateIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2775 LogFlowFunc(("LUN#%RU8: Created input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2776 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2777 {
2778 AudioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2779 rc = AudioMixerAddStreamIn(pSink,
2780 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2781 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2782 }
2783
2784 RTStrFree(pszDesc);
2785 }
2786
2787 LogFlowFuncLeaveRC(rc);
2788 return rc;
2789}
2790
2791static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2792 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2793{
2794 int rc = VINF_SUCCESS;
2795 char *pszDesc;
2796
2797 PHDADRIVER pDrv;
2798 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2799 {
2800 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2801 {
2802 rc = VERR_NO_MEMORY;
2803 break;
2804 }
2805
2806 rc = pDrv->pConnector->pfnCreateOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
2807 LogFlowFunc(("LUN#%RU8: Created output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2808 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2809 {
2810 AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
2811 rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
2812 pDrv->pConnector, pDrv->Out.pStrmOut,
2813 0 /* uFlags */, &pDrv->Out.phStrmOut);
2814 }
2815
2816 RTStrFree(pszDesc);
2817 }
2818
2819 LogFlowFuncLeaveRC(rc);
2820 return rc;
2821}
2822
2823static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis, ENMSOUNDSOURCE enmSource,
2824 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2825{
2826 int rc = VINF_SUCCESS;
2827 PDMAUDIOVOLUME vol = { fMute, uVolLeft, uVolRight };
2828 PAUDMIXSINK pSink;
2829
2830 /* Convert the audio source to corresponding sink. */
2831 switch (enmSource)
2832 {
2833 case PO_INDEX:
2834 pSink = pThis->pSinkOutput;
2835 break;
2836 case PI_INDEX:
2837 pSink = pThis->pSinkLineIn;
2838 break;
2839 case MC_INDEX:
2840 pSink = pThis->pSinkMicIn;
2841 break;
2842 default:
2843 AssertFailedReturn(VERR_INVALID_PARAMETER);
2844 break;
2845 }
2846
2847 /* Set the volume. Codec already converted it to the correct range. */
2848 AudioMixerSetSinkVolume(pSink, &vol);
2849
2850 LogFlowFuncLeaveRC(rc);
2851 return rc;
2852}
2853
2854#ifndef VBOX_WITH_AUDIO_CALLBACKS
2855
2856static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2857{
2858 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2859 AssertPtr(pThis);
2860
2861 STAM_PROFILE_START(&pThis->StatTimer, a);
2862
2863 int rc = VINF_SUCCESS;
2864
2865 uint32_t cbInMax = 0;
2866 uint32_t cbOutMin = UINT32_MAX;
2867
2868 PHDADRIVER pDrv;
2869
2870 uint32_t cbIn, cbOut, cSamplesLive;
2871 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2872 {
2873 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2874 &cbIn, &cbOut, &cSamplesLive);
2875 if (RT_SUCCESS(rc))
2876 {
2877#ifdef DEBUG_TIMER
2878 LogFlowFunc(("\tLUN#%RU8: [1] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2879#endif
2880 if (cSamplesLive)
2881 {
2882 uint32_t cSamplesPlayed;
2883 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2884 if (RT_SUCCESS(rc2))
2885 LogFlowFunc(("LUN#%RU8: cSamplesLive=%RU32, cSamplesPlayed=%RU32\n",
2886 pDrv->uLUN, cSamplesLive, cSamplesPlayed));
2887
2888 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2889 &cbIn, &cbOut, &cSamplesLive);
2890#ifdef DEBUG_TIMER
2891 if (RT_SUCCESS(rc))
2892 LogFlowFunc(("\tLUN#%RU8: [2] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2893#endif
2894 }
2895
2896 cbInMax = RT_MAX(cbInMax, cbIn);
2897 cbOutMin = RT_MIN(cbOutMin, cbOut);
2898 }
2899 }
2900
2901#ifdef DEBUG_TIMER
2902 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
2903#endif
2904
2905 if (cbOutMin == UINT32_MAX)
2906 cbOutMin = 0;
2907
2908 /*
2909 * Playback.
2910 */
2911 if (cbOutMin)
2912 {
2913 Assert(cbOutMin != UINT32_MAX);
2914 hdaTransfer(pThis, PO_INDEX, NULL /* pcbProcessed */); /** @todo Add rc! */
2915 }
2916
2917 /*
2918 * Recording.
2919 */
2920 if (cbInMax)
2921 hdaTransfer(pThis, PI_INDEX, NULL /* pcbProcessed */); /** @todo Add rc! */
2922
2923 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
2924
2925 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2926}
2927
2928#else /* VBOX_WITH_AUDIO_CALLBACKS */
2929
2930static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
2931{
2932 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
2933 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
2934 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
2935 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
2936 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
2937
2938 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
2939 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
2940
2941 PPDMAUDIOCALLBACKDATAIN pData = (PPDMAUDIOCALLBACKDATAIN)pvUser;
2942 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAIN), VERR_INVALID_PARAMETER);
2943
2944 return hdaTransfer(pCtx->pThis, PI_INDEX, &pData->cbOutRead);
2945}
2946
2947static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
2948{
2949 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
2950 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
2951 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
2952 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
2953 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
2954
2955 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
2956 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
2957
2958 PPDMAUDIOCALLBACKDATAOUT pData = (PPDMAUDIOCALLBACKDATAOUT)pvUser;
2959 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAOUT), VERR_INVALID_PARAMETER);
2960
2961 PHDASTATE pThis = pCtx->pThis;
2962
2963 int rc = hdaTransfer(pCtx->pThis, PO_INDEX, &pData->cbOutWritten);
2964 if ( RT_SUCCESS(rc)
2965 && pData->cbOutWritten)
2966 {
2967 PHDADRIVER pDrv;
2968 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2969 {
2970 uint32_t cSamplesPlayed;
2971 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2972 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
2973 }
2974 }
2975}
2976#endif /* VBOX_WITH_AUDIO_CALLBACKS */
2977
2978static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t *pcbProcessed)
2979{
2980 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2981 /* pcbProcessed is optional. */
2982
2983 LogFlowFunc(("enmSrc=%RU32\n", enmSrc));
2984
2985 PHDASTREAM pStrmSt;
2986 switch (enmSrc)
2987 {
2988 case PI_INDEX:
2989 {
2990 pStrmSt = &pThis->StrmStLineIn;
2991 break;
2992 }
2993
2994#ifdef VBOX_WITH_HDA_MIC_IN
2995 case MC_INDEX:
2996 {
2997 pStrmSt = &pThis->StrmStMicIn;
2998 break;
2999 }
3000#endif
3001 case PO_INDEX:
3002 {
3003 pStrmSt = &pThis->StrmStOut;
3004 break;
3005 }
3006
3007 default:
3008 {
3009 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
3010 return VERR_NOT_SUPPORTED;
3011 }
3012 }
3013
3014 if (pStrmSt->State.cBDLE == 0) /* No buffers available? */
3015 {
3016 LogFlowFunc(("[SD%RU8] No buffers available\n", pStrmSt->u8Strm));
3017
3018 if (pcbProcessed)
3019 *pcbProcessed = 0;
3020 return VINF_SUCCESS;
3021 }
3022 AssertPtr(pStrmSt->State.paBDLE);
3023
3024 /* Is this stream running? */
3025 const bool fIsRunning = RT_BOOL(HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3026 if (!fIsRunning)
3027 {
3028 LogFlowFunc(("[SD%RU8]: Stream not running\n", pStrmSt->u8Strm));
3029
3030 if (pcbProcessed)
3031 *pcbProcessed = 0;
3032 return VINF_SUCCESS;
3033 }
3034
3035 Assert(pStrmSt->u8Strm <= 7); /** @todo Use a define for MAX_STRAEMS! */
3036 Assert(pStrmSt->u64BaseDMA);
3037 Assert(pStrmSt->u32CBL);
3038
3039 int rc;
3040 uint32_t cbProcessedTotal = 0;
3041 bool fIsComplete = false;
3042
3043 do
3044 {
3045 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
3046 if (hdaStreamNeedsNextBDLE(pThis, pStrmSt))
3047 hdaStreamGetNextBDLE(pThis, pStrmSt);
3048
3049 /* Set the FIFORDY bit on the stream while doing the transfer. */
3050 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3051
3052 uint32_t cbProcessed;
3053 switch (enmSrc)
3054 {
3055 case PI_INDEX:
3056 rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkLineIn, &cbProcessed);
3057 break;
3058 case PO_INDEX:
3059 rc = hdaWriteAudio(pThis, pStrmSt, &cbProcessed);
3060 break;
3061#ifdef VBOX_WITH_HDA_MIC_IN
3062 case MC_INDEX:
3063 rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkMicIn, &cbProcessed);
3064 break;
3065#endif
3066 default:
3067 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
3068 rc = VERR_NOT_SUPPORTED;
3069 break;
3070 }
3071
3072 /* Remove the FIFORDY bit again. */
3073 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3074
3075 if (RT_FAILURE(rc))
3076 break;
3077
3078 hdaStreamTransferUpdate(pThis, pStrmSt, cbProcessed);
3079
3080 cbProcessedTotal += cbProcessed;
3081
3082 LogFlowFunc(("cbProcessed=%RU32, cbProcessedTotal=%RU32, rc=%Rrc\n", cbProcessed, cbProcessedTotal, rc));
3083
3084 if (rc == VINF_EOF)
3085 fIsComplete = true;
3086
3087 if (!fIsComplete)
3088 fIsComplete = hdaStreamTransferIsComplete(pThis, pStrmSt);
3089
3090 } while (!fIsComplete);
3091
3092 if (RT_SUCCESS(rc))
3093 {
3094 if (pcbProcessed)
3095 *pcbProcessed = cbProcessedTotal;
3096 }
3097
3098 LogFlowFuncLeaveRC(rc);
3099 return rc;
3100}
3101#endif /* IN_RING3 */
3102
3103/* MMIO callbacks */
3104
3105/**
3106 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3107 *
3108 * @note During implementation, we discovered so-called "forgotten" or "hole"
3109 * registers whose description is not listed in the RPM, datasheet, or
3110 * spec.
3111 */
3112PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3113{
3114 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3115 int rc;
3116
3117 /*
3118 * Look up and log.
3119 */
3120 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3121 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
3122#ifdef LOG_ENABLED
3123 unsigned const cbLog = cb;
3124 uint32_t offRegLog = offReg;
3125#endif
3126
3127 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
3128 Assert(cb == 4); Assert((offReg & 3) == 0);
3129
3130 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3131 LogFunc(("\tAccess to registers except GCTL is blocked while reset\n"));
3132
3133 if (idxRegDsc == -1)
3134 LogRel(("HDA: Invalid read access @0x%x (bytes=%d)\n", offReg, cb));
3135
3136 if (idxRegDsc != -1)
3137 {
3138 /* ASSUMES gapless DWORD at end of map. */
3139 if (g_aHdaRegMap[idxRegDsc].size == 4)
3140 {
3141 /*
3142 * Straight forward DWORD access.
3143 */
3144 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3145 LogFunc(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
3146 }
3147 else
3148 {
3149 /*
3150 * Multi register read (unless there are trailing gaps).
3151 * ASSUMES that only DWORD reads have sideeffects.
3152 */
3153 uint32_t u32Value = 0;
3154 unsigned cbLeft = 4;
3155 do
3156 {
3157 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3158 uint32_t u32Tmp = 0;
3159
3160 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3161 LogFunc(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3162 if (rc != VINF_SUCCESS)
3163 break;
3164 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3165
3166 cbLeft -= cbReg;
3167 offReg += cbReg;
3168 idxRegDsc++;
3169 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3170
3171 if (rc == VINF_SUCCESS)
3172 *(uint32_t *)pv = u32Value;
3173 else
3174 Assert(!IOM_SUCCESS(rc));
3175 }
3176 }
3177 else
3178 {
3179 rc = VINF_IOM_MMIO_UNUSED_FF;
3180 LogFunc(("\tHole at %x is accessed for read\n", offReg));
3181 }
3182
3183 /*
3184 * Log the outcome.
3185 */
3186#ifdef LOG_ENABLED
3187 if (cbLog == 4)
3188 LogFunc(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
3189 else if (cbLog == 2)
3190 LogFunc(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
3191 else if (cbLog == 1)
3192 LogFunc(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
3193#endif
3194 return rc;
3195}
3196
3197
3198DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3199{
3200 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3201 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
3202
3203 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3204#ifdef LOG_ENABLED
3205 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
3206#endif
3207 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3208 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3209 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
3210 return rc;
3211}
3212
3213
3214/**
3215 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3216 */
3217PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
3218{
3219 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3220 int rc;
3221
3222 /*
3223 * The behavior of accesses that aren't aligned on natural boundraries is
3224 * undefined. Just reject them outright.
3225 */
3226 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3227 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
3228 if (GCPhysAddr & (cb - 1))
3229 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3230
3231 /*
3232 * Look up and log the access.
3233 */
3234 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3235 int idxRegDsc = hdaRegLookup(pThis, offReg);
3236 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3237 uint64_t u64Value;
3238 if (cb == 4) u64Value = *(uint32_t const *)pv;
3239 else if (cb == 2) u64Value = *(uint16_t const *)pv;
3240 else if (cb == 1) u64Value = *(uint8_t const *)pv;
3241 else if (cb == 8) u64Value = *(uint64_t const *)pv;
3242 else
3243 {
3244 u64Value = 0; /* shut up gcc. */
3245 AssertReleaseMsgFailed(("%u\n", cb));
3246 }
3247
3248#ifdef LOG_ENABLED
3249 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3250 if (idxRegDsc == -1)
3251 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
3252 else if (cb == 4)
3253 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3254 else if (cb == 2)
3255 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3256 else if (cb == 1)
3257 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3258
3259 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3260 LogFunc(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3261#endif
3262
3263 /*
3264 * Try for a direct hit first.
3265 */
3266 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3267 {
3268 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3269#ifdef LOG_ENABLED
3270 LogFunc(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3271#endif
3272 }
3273 /*
3274 * Partial or multiple register access, loop thru the requested memory.
3275 */
3276 else
3277 {
3278 /*
3279 * If it's an access beyond the start of the register, shift the input
3280 * value and fill in missing bits. Natural alignment rules means we
3281 * will only see 1 or 2 byte accesses of this kind, so no risk of
3282 * shifting out input values.
3283 */
3284 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
3285 {
3286 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3287 offReg -= cbBefore;
3288 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3289 u64Value <<= cbBefore * 8;
3290 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3291 LogFunc(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3292 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3293 }
3294
3295 /* Loop thru the write area, it may cover multiple registers. */
3296 rc = VINF_SUCCESS;
3297 for (;;)
3298 {
3299 uint32_t cbReg;
3300 if (idxRegDsc != -1)
3301 {
3302 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3303 cbReg = g_aHdaRegMap[idxRegDsc].size;
3304 if (cb < cbReg)
3305 {
3306 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3307 LogFunc(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3308 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3309 }
3310 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
3311 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3312 LogFunc(("\t%#x -> %#x\n", u32LogOldVal, pThis->au32Regs[idxRegMem]));
3313 }
3314 else
3315 {
3316 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3317 cbReg = 1;
3318 }
3319 if (rc != VINF_SUCCESS)
3320 break;
3321 if (cbReg >= cb)
3322 break;
3323
3324 /* Advance. */
3325 offReg += cbReg;
3326 cb -= cbReg;
3327 u64Value >>= cbReg * 8;
3328 if (idxRegDsc == -1)
3329 idxRegDsc = hdaRegLookup(pThis, offReg);
3330 else
3331 {
3332 idxRegDsc++;
3333 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3334 || g_aHdaRegMap[idxRegDsc].offset != offReg)
3335 {
3336 idxRegDsc = -1;
3337 }
3338 }
3339 }
3340 }
3341
3342 return rc;
3343}
3344
3345
3346/* PCI callback. */
3347
3348#ifdef IN_RING3
3349/**
3350 * @callback_method_impl{FNPCIIOREGIONMAP}
3351 */
3352static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
3353 PCIADDRESSSPACE enmType)
3354{
3355 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3356 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3357 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3358 int rc;
3359
3360 /*
3361 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3362 *
3363 * Let IOM talk DWORDs when reading, saves a lot of complications. On
3364 * writing though, we have to do it all ourselves because of sideeffects.
3365 */
3366 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3367 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
3368 IOMMMIO_FLAGS_READ_DWORD
3369 | IOMMMIO_FLAGS_WRITE_PASSTHRU,
3370 hdaMMIOWrite, hdaMMIORead, "HDA");
3371
3372 if (RT_FAILURE(rc))
3373 return rc;
3374
3375 if (pThis->fR0Enabled)
3376 {
3377 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
3378 "hdaMMIOWrite", "hdaMMIORead");
3379 if (RT_FAILURE(rc))
3380 return rc;
3381 }
3382
3383 if (pThis->fRCEnabled)
3384 {
3385 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
3386 "hdaMMIOWrite", "hdaMMIORead");
3387 if (RT_FAILURE(rc))
3388 return rc;
3389 }
3390
3391 pThis->MMIOBaseAddr = GCPhysAddress;
3392 return VINF_SUCCESS;
3393}
3394
3395
3396/* Saved state callbacks. */
3397
3398static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
3399{
3400 /* Save stream ID. */
3401 int rc = SSMR3PutU8(pSSM, pStrm->u8Strm);
3402 AssertRCReturn(rc, rc);
3403 Assert(pStrm->u8Strm <= 7); /** @todo Use a define. */
3404
3405 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields5, NULL);
3406 AssertRCReturn(rc, rc);
3407
3408 for (uint32_t i = 0; i < pStrm->State.cBDLE; i++)
3409 {
3410 rc = SSMR3PutStructEx(pSSM, &pStrm->State.paBDLE[i], sizeof(HDABDLE), 0 /*fFlags*/, g_aSSMBDLEStateFields5, NULL);
3411 AssertRCReturn(rc, rc);
3412 }
3413
3414 return rc;
3415}
3416
3417/**
3418 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3419 */
3420static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3421{
3422 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3423
3424 /* Save Codec nodes states. */
3425 hdaCodecSaveState(pThis->pCodec, pSSM);
3426
3427 /* Save MMIO registers. */
3428 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3429 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3430 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3431
3432 /* Save number of streams. */
3433 SSMR3PutU32(pSSM, 3);
3434
3435 /* Save stream states. */
3436 int rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStOut);
3437 AssertRCReturn(rc, rc);
3438 rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStMicIn);
3439 AssertRCReturn(rc, rc);
3440 rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStLineIn);
3441 AssertRCReturn(rc, rc);
3442
3443 return rc;
3444}
3445
3446
3447/**
3448 * @callback_method_impl{FNSSMDEVLOADEXEC}
3449 */
3450static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3451{
3452 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3453
3454 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3455
3456 LogFlowFunc(("uVersion=%RU32, uPass=%RU32\n", uVersion, uPass));
3457
3458 /*
3459 * Load Codec nodes states.
3460 */
3461 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3462 if (RT_FAILURE(rc))
3463 return rc;
3464
3465 /*
3466 * Load MMIO registers.
3467 */
3468 uint32_t cRegs;
3469 switch (uVersion)
3470 {
3471 case HDA_SSM_VERSION_1:
3472 /* Starting with r71199, we would save 112 instead of 113
3473 registers due to some code cleanups. This only affected trunk
3474 builds in the 4.1 development period. */
3475 cRegs = 113;
3476 if (SSMR3HandleRevision(pSSM) >= 71199)
3477 {
3478 uint32_t uVer = SSMR3HandleVersion(pSSM);
3479 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3480 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3481 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3482 cRegs = 112;
3483 }
3484 break;
3485
3486 case HDA_SSM_VERSION_2:
3487 case HDA_SSM_VERSION_3:
3488 cRegs = 112;
3489 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3490 break;
3491
3492 /* Since version 4 we store the register count to stay flexible. */
3493 case HDA_SSM_VERSION_4:
3494 case HDA_SSM_VERSION:
3495 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3496 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3497 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3498 break;
3499
3500 default:
3501 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3502 }
3503
3504 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3505 {
3506 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3507 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3508 }
3509 else
3510 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3511
3512 /*
3513 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3514 * *every* BDLE state, whereas it only needs to be stored
3515 * *once* for every stream. Most of the BDLE state we can
3516 * get out of the registers anyway, so just ignore those values.
3517 *
3518 * Also, only the current BDLE was saved, regardless whether
3519 * there were more than one (and there are at least two entries,
3520 * according to the spec).
3521 */
3522#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3523 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3524 AssertRCReturn(rc, rc); \
3525 rc = SSMR3Skip(pSSM, sizeof(uint64_t)); /* u64BdleCviAddr */ \
3526 AssertRCReturn(rc, rc); \
3527 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3528 AssertRCReturn(rc, rc); \
3529 rc = SSMR3GetU32(pSSM, &x->u32BDLIndex); /* u32BdleCvi */ \
3530 AssertRCReturn(rc, rc); \
3531 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleCviLen */ \
3532 AssertRCReturn(rc, rc); \
3533 rc = SSMR3GetU32(pSSM, &x->u32BufOff); /* u32BdleCviPos */ \
3534 AssertRCReturn(rc, rc); \
3535 rc = SSMR3Skip(pSSM, sizeof(uint8_t)); /* fBdleCviIoc */ \
3536 AssertRCReturn(rc, rc); \
3537 rc = SSMR3GetU32(pSSM, &x->cbBelowFIFOW); /* cbUnderFifoW */ \
3538 AssertRCReturn(rc, rc); \
3539 rc = SSMR3GetMem(pSSM, &x->au8FIFO, sizeof(x->au8FIFO)); \
3540 AssertRCReturn(rc, rc); \
3541 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3542 AssertRCReturn(rc, rc); \
3543
3544 /*
3545 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3546 */
3547 HDABDLESTATE StateBDLEDummy;
3548
3549 switch (uVersion)
3550 {
3551 case HDA_SSM_VERSION_1:
3552 case HDA_SSM_VERSION_2:
3553 case HDA_SSM_VERSION_3:
3554 case HDA_SSM_VERSION_4:
3555 {
3556 /* Only load the internal states.
3557 * The rest will be initialized from the saved registers later. */
3558
3559 /* Note: Only the *current* BDLE for a stream was saved! */
3560
3561 /* Output */
3562 rc = hdaStreamInit(pThis, &pThis->StrmStOut, 4 /* Stream number, hardcoded */);
3563 AssertRCBreak(rc);
3564 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStOut.State.cBDLE
3565 ? &pThis->StrmStOut.State.paBDLE[0].State : &StateBDLEDummy));
3566 /* Microphone-In */
3567 rc = hdaStreamInit(pThis, &pThis->StrmStMicIn, 2 /* Stream number, hardcoded */);
3568 AssertRCBreak(rc);
3569 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStMicIn.State.cBDLE
3570 ? &pThis->StrmStMicIn.State.paBDLE[0].State : &StateBDLEDummy));
3571 /* Line-In */
3572 rc = hdaStreamInit(pThis, &pThis->StrmStLineIn, 0 /* Stream number, hardcoded */);
3573 AssertRCBreak(rc);
3574 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStLineIn.State.cBDLE
3575 ? &pThis->StrmStLineIn.State.paBDLE[0].State : &StateBDLEDummy));
3576 break;
3577 }
3578
3579 /* Since v5 we support flexible stream and BDLE counts. */
3580 case HDA_SSM_VERSION:
3581 {
3582 uint32_t cStreams;
3583 rc = SSMR3GetU32(pSSM, &cStreams);
3584 AssertRCBreak(rc);
3585
3586 /* Load stream states. */
3587 for (uint32_t i = 0; i < cStreams; i++)
3588 {
3589 uint8_t uStreamID;
3590 rc = SSMR3GetU8(pSSM, &uStreamID);
3591 AssertRCBreak(rc);
3592
3593 PHDASTREAM pStrm;
3594 HDASTREAM StreamDummy;
3595
3596 switch (uStreamID)
3597 {
3598 case 0: /** @todo Use a define. */
3599 pStrm = &pThis->StrmStLineIn;
3600 break;
3601
3602 case 2: /** @todo Use a define. */
3603 pStrm = &pThis->StrmStMicIn;
3604 break;
3605
3606 case 4: /** @todo Use a define. */
3607 pStrm = &pThis->StrmStOut;
3608 break;
3609
3610 default:
3611 pStrm = &StreamDummy;
3612 break;
3613 }
3614
3615 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /* fFlags */, g_aSSMStreamStateFields5, NULL);
3616 AssertRCBreak(rc);
3617
3618 rc = hdaStreamInit(pThis, pStrm, uStreamID);
3619 AssertRCBreak(rc);
3620
3621 /* Load BDLE states. */
3622 for (uint32_t a = 0; a < pStrm->State.cBDLE; a++)
3623 {
3624 rc = SSMR3GetStructEx(pSSM, &pStrm->State.paBDLE[a].State, sizeof(HDABDLESTATE),
3625 0 /* fFlags */, g_aSSMBDLEStateFields5, NULL);
3626 AssertRCBreak(rc);
3627 }
3628
3629 /* Destroy dummy again. */
3630 if (pStrm == &StreamDummy)
3631 hdaStreamDestroy(pStrm);
3632 }
3633 break;
3634 }
3635
3636 default:
3637 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3638 }
3639
3640#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3641
3642 if (RT_SUCCESS(rc))
3643 {
3644 /*
3645 * Update stuff after the state changes.
3646 */
3647 bool fEnableIn = RT_BOOL(HDA_SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3648#ifdef VBOX_WITH_HDA_MIC_IN
3649 bool fEnableMicIn = RT_BOOL(HDA_SDCTL(pThis, 2) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3650#else
3651 bool fEnableMicIn = fEnableIn; /* Mic In == Line In */
3652#endif
3653 bool fEnableOut = RT_BOOL(HDA_SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3654
3655 PHDADRIVER pDrv;
3656 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3657 {
3658 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, fEnableIn);
3659 if (RT_FAILURE(rc))
3660 break;
3661 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, fEnableMicIn);
3662 if (RT_FAILURE(rc))
3663 break;
3664 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, fEnableOut);
3665 if (RT_FAILURE(rc))
3666 break;
3667 }
3668 }
3669
3670 if (RT_SUCCESS(rc))
3671 {
3672 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3673 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3674 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3675 }
3676
3677 LogFlowFuncLeaveRC(rc);
3678 return rc;
3679}
3680
3681#ifdef DEBUG
3682/* Debug and log type formatters. */
3683
3684/**
3685 * @callback_method_impl{FNRTSTRFORMATTYPE}
3686 */
3687static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3688 const char *pszType, void const *pvValue,
3689 int cchWidth, int cchPrecision, unsigned fFlags,
3690 void *pvUser)
3691{
3692 PHDABDLE pBDLE = (PHDABDLE)pvValue;
3693 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3694 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, DMA[%RU32 bytes @ 0x%x])",
3695 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW, pBDLE->u32BufSize, pBDLE->u64BufAdr);
3696}
3697
3698/**
3699 * @callback_method_impl{FNRTSTRFORMATTYPE}
3700 */
3701static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3702 const char *pszType, void const *pvValue,
3703 int cchWidth, int cchPrecision, unsigned fFlags,
3704 void *pvUser)
3705{
3706 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
3707 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3708 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
3709 uSDCTL,
3710 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
3711 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3712 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3713 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3714 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
3715 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3716 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3717 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3718}
3719
3720/**
3721 * @callback_method_impl{FNRTSTRFORMATTYPE}
3722 */
3723static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3724 const char *pszType, void const *pvValue,
3725 int cchWidth, int cchPrecision, unsigned fFlags,
3726 void *pvUser)
3727{
3728 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
3729 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, hdaSDFIFOSToBytes(uSDFIFOS));
3730}
3731
3732/**
3733 * @callback_method_impl{FNRTSTRFORMATTYPE}
3734 */
3735static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3736 const char *pszType, void const *pvValue,
3737 int cchWidth, int cchPrecision, unsigned fFlags,
3738 void *pvUser)
3739{
3740 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
3741 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
3742}
3743
3744/**
3745 * @callback_method_impl{FNRTSTRFORMATTYPE}
3746 */
3747static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3748 const char *pszType, void const *pvValue,
3749 int cchWidth, int cchPrecision, unsigned fFlags,
3750 void *pvUser)
3751{
3752 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3753 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3754 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3755 uSdSts,
3756 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3757 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3758 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3759 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3760}
3761
3762static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3763{
3764 int iReg = 0;
3765 for (; iReg < HDA_NREGS; ++iReg)
3766 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3767 return iReg;
3768 return -1;
3769}
3770
3771
3772static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
3773{
3774 Assert( pThis
3775 && iHdaIndex >= 0
3776 && iHdaIndex < HDA_NREGS);
3777 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
3778}
3779
3780/**
3781 * @callback_method_impl{FNDBGFHANDLERDEV}
3782 */
3783static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3784{
3785 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3786 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
3787 if (iHdaRegisterIndex != -1)
3788 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3789 else
3790 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
3791 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3792}
3793
3794static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
3795{
3796 Assert( pThis
3797 && iHdaStrmIndex >= 0
3798 && iHdaStrmIndex < 7);
3799 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
3800 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
3801 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
3802 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
3803 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
3804}
3805
3806static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
3807{
3808 /* todo: add args parsing */
3809 return -1;
3810}
3811
3812/**
3813 * @callback_method_impl{FNDBGFHANDLERDEV}
3814 */
3815static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3816{
3817 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3818 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
3819 if (iHdaStrmIndex != -1)
3820 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3821 else
3822 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
3823 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3824}
3825
3826/**
3827 * @callback_method_impl{FNDBGFHANDLERDEV}
3828 */
3829static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3830{
3831 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3832
3833 if (pThis->pCodec->pfnDbgListNodes)
3834 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
3835 else
3836 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3837}
3838
3839/**
3840 * @callback_method_impl{FNDBGFHANDLERDEV}
3841 */
3842static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3843{
3844 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3845
3846 if (pThis->pCodec->pfnDbgSelector)
3847 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
3848 else
3849 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3850}
3851
3852/**
3853 * @callback_method_impl{FNDBGFHANDLERDEV}
3854 */
3855static DECLCALLBACK(void) hdaInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3856{
3857 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3858
3859 if (pThis->pMixer)
3860 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
3861 else
3862 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
3863}
3864#endif /* DEBUG */
3865
3866/* PDMIBASE */
3867
3868/**
3869 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3870 */
3871static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3872{
3873 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
3874 Assert(&pThis->IBase == pInterface);
3875
3876 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3877 return NULL;
3878}
3879
3880
3881/* PDMDEVREG */
3882
3883/**
3884 * Reset notification.
3885 *
3886 * @returns VBox status code.
3887 * @param pDevIns The device instance data.
3888 *
3889 * @remark The original sources didn't install a reset handler, but it seems to
3890 * make sense to me so we'll do it.
3891 */
3892static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
3893{
3894 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3895
3896 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
3897 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3898 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3899 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3900 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3901 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
3902 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
3903 HDA_REG(pThis, CORBRP) = 0x0;
3904 HDA_REG(pThis, RIRBWP) = 0x0;
3905
3906 LogFunc(("Resetting ...\n"));
3907
3908 /* Stop any audio currently playing. */
3909 PHDADRIVER pDrv;
3910 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3911 {
3912 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
3913 /* Ignore rc. */
3914 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
3915 /* Ditto. */
3916 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
3917 /* Ditto. */
3918 }
3919
3920 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
3921
3922 if (pThis->pu32CorbBuf)
3923 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3924 else
3925 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3926
3927 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
3928 if (pThis->pu64RirbBuf)
3929 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3930 else
3931 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3932
3933 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
3934
3935 for (uint8_t u8Strm = 0; u8Strm < 8; u8Strm++) /** @todo Use a define here. */
3936 {
3937 PHDASTREAM pStrmSt = NULL;
3938 if (u8Strm == 0)
3939 pStrmSt = &pThis->StrmStOut;
3940# ifdef VBOX_WITH_HDA_MIC_IN
3941 else if (u8Strm == 2)
3942 pStrmSt = &pThis->StrmStMicIn;
3943# endif
3944 else if (u8Strm == 4)
3945 pStrmSt = &pThis->StrmStLineIn;
3946
3947 if (pStrmSt)
3948 {
3949 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
3950 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
3951
3952 hdaStreamReset(pThis, pStrmSt, u8Strm);
3953 }
3954 }
3955
3956 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3957 HDA_REG(pThis, STATESTS) = 0x1;
3958
3959 LogRel(("HDA: Reset\n"));
3960}
3961
3962/**
3963 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3964 */
3965static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
3966{
3967 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3968
3969 PHDADRIVER pDrv;
3970 while (!RTListIsEmpty(&pThis->lstDrv))
3971 {
3972 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
3973
3974 RTListNodeRemove(&pDrv->Node);
3975 RTMemFree(pDrv);
3976 }
3977
3978 if (pThis->pMixer)
3979 {
3980 AudioMixerDestroy(pThis->pMixer);
3981 pThis->pMixer = NULL;
3982 }
3983
3984 if (pThis->pCodec)
3985 {
3986 int rc = hdaCodecDestruct(pThis->pCodec);
3987 AssertRC(rc);
3988
3989 RTMemFree(pThis->pCodec);
3990 pThis->pCodec = NULL;
3991 }
3992
3993 RTMemFree(pThis->pu32CorbBuf);
3994 pThis->pu32CorbBuf = NULL;
3995
3996 RTMemFree(pThis->pu64RirbBuf);
3997 pThis->pu64RirbBuf = NULL;
3998
3999 hdaStreamDestroy(&pThis->StrmStLineIn);
4000 hdaStreamDestroy(&pThis->StrmStMicIn);
4001 hdaStreamDestroy(&pThis->StrmStOut);
4002
4003 return VINF_SUCCESS;
4004}
4005
4006/**
4007 * Attach command.
4008 *
4009 * This is called to let the device attach to a driver for a specified LUN
4010 * during runtime. This is not called during VM construction, the device
4011 * constructor have to attach to all the available drivers.
4012 *
4013 * @returns VBox status code.
4014 * @param pDevIns The device instance.
4015 * @param uLUN The logical unit which is being detached.
4016 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4017 */
4018static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4019{
4020 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4021
4022 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
4023 ("HDA device does not support hotplugging\n"),
4024 VERR_INVALID_PARAMETER);
4025
4026 /*
4027 * Attach driver.
4028 */
4029 char *pszDesc = NULL;
4030 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4031 AssertMsgReturn(pszDesc,
4032 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
4033 VERR_NO_MEMORY);
4034
4035 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
4036 &pThis->IBase, &pThis->pDrvBase, pszDesc);
4037 if (RT_SUCCESS(rc))
4038 {
4039 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4040 if (pDrv)
4041 {
4042 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
4043 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4044 pDrv->pHDAState = pThis;
4045 pDrv->uLUN = uLUN;
4046
4047 /*
4048 * For now we always set the driver at LUN 0 as our primary
4049 * host backend. This might change in the future.
4050 */
4051 if (pDrv->uLUN == 0)
4052 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
4053
4054 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
4055
4056 /* Attach to driver list. */
4057 RTListAppend(&pThis->lstDrv, &pDrv->Node);
4058 }
4059 else
4060 rc = VERR_NO_MEMORY;
4061 }
4062 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
4063 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
4064 {
4065 LogFunc(("No attached driver for LUN #%u\n", uLUN));
4066 }
4067 else if (RT_FAILURE(rc))
4068 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
4069 uLUN, pszDesc, rc));
4070
4071 RTStrFree(pszDesc);
4072
4073 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4074 return rc;
4075}
4076
4077static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4078{
4079 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
4080
4081 LogFlowFuncEnter();
4082}
4083
4084/**
4085 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4086 */
4087static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
4088{
4089 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4090 Assert(iInstance == 0);
4091 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4092
4093 /*
4094 * Validations.
4095 */
4096 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
4097 "RCEnabled\0"))
4098 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4099 N_ ("Invalid configuration for the Intel HDA device"));
4100
4101 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
4102 if (RT_FAILURE(rc))
4103 return PDMDEV_SET_ERROR(pDevIns, rc,
4104 N_("HDA configuration error: failed to read RCEnabled as boolean"));
4105 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
4106 if (RT_FAILURE(rc))
4107 return PDMDEV_SET_ERROR(pDevIns, rc,
4108 N_("HDA configuration error: failed to read R0Enabled as boolean"));
4109
4110 /*
4111 * Initialize data (most of it anyway).
4112 */
4113 pThis->pDevInsR3 = pDevIns;
4114 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4115 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4116 /* IBase */
4117 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
4118
4119 /* PCI Device */
4120 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
4121 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
4122
4123 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
4124 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
4125 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
4126 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
4127 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
4128 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
4129 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
4130 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
4131 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
4132 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
4133 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
4134
4135#if defined(HDA_AS_PCI_EXPRESS)
4136 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
4137#elif defined(VBOX_WITH_MSI_DEVICES)
4138 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
4139#else
4140 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
4141#endif
4142
4143 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
4144 /// of these values needs to be properly documented!
4145 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
4146 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
4147
4148 /* Power Management */
4149 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
4150 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
4151 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
4152
4153#ifdef HDA_AS_PCI_EXPRESS
4154 /* PCI Express */
4155 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
4156 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
4157 /* Device flags */
4158 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
4159 /* version */ 0x1 |
4160 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
4161 /* MSI */ (100) << 9 );
4162 /* Device capabilities */
4163 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
4164 /* Device control */
4165 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
4166 /* Device status */
4167 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
4168 /* Link caps */
4169 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
4170 /* Link control */
4171 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
4172 /* Link status */
4173 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
4174 /* Slot capabilities */
4175 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
4176 /* Slot control */
4177 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
4178 /* Slot status */
4179 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
4180 /* Root control */
4181 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
4182 /* Root capabilities */
4183 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
4184 /* Root status */
4185 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
4186 /* Device capabilities 2 */
4187 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
4188 /* Device control 2 */
4189 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
4190 /* Link control 2 */
4191 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
4192 /* Slot control 2 */
4193 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
4194#endif
4195
4196 /*
4197 * Register the PCI device.
4198 */
4199 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
4200 if (RT_FAILURE(rc))
4201 return rc;
4202
4203 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
4204 if (RT_FAILURE(rc))
4205 return rc;
4206
4207#ifdef VBOX_WITH_MSI_DEVICES
4208 PDMMSIREG MsiReg;
4209 RT_ZERO(MsiReg);
4210 MsiReg.cMsiVectors = 1;
4211 MsiReg.iMsiCapOffset = 0x60;
4212 MsiReg.iMsiNextOffset = 0x50;
4213 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4214 if (RT_FAILURE(rc))
4215 {
4216 /* That's OK, we can work without MSI */
4217 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
4218 }
4219#endif
4220
4221 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
4222 if (RT_FAILURE(rc))
4223 return rc;
4224
4225 RTListInit(&pThis->lstDrv);
4226
4227 uint8_t uLUN;
4228 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
4229 {
4230 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
4231 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
4232 if (RT_FAILURE(rc))
4233 {
4234 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4235 rc = VINF_SUCCESS;
4236
4237 break;
4238 }
4239
4240 uLUN++;
4241 }
4242
4243 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
4244
4245 if (RT_SUCCESS(rc))
4246 {
4247 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
4248 if (RT_SUCCESS(rc))
4249 {
4250 /* Set a default audio format for our mixer. */
4251 PDMAUDIOSTREAMCFG streamCfg;
4252 streamCfg.uHz = 44100;
4253 streamCfg.cChannels = 2;
4254 streamCfg.enmFormat = AUD_FMT_S16;
4255 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
4256
4257 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
4258 AssertRC(rc);
4259
4260 /* Add all required audio sinks. */
4261 rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output",
4262 AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
4263 AssertRC(rc);
4264
4265 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In",
4266 AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
4267 AssertRC(rc);
4268
4269 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
4270 AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
4271 AssertRC(rc);
4272
4273 /* There is no master volume control. Set the master to max. */
4274 PDMAUDIOVOLUME vol = { false, 255, 255 };
4275 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
4276 AssertRC(rc);
4277 }
4278 }
4279
4280 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
4281
4282 if (RT_SUCCESS(rc))
4283 {
4284 /* Construct codec. */
4285 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
4286 if (!pThis->pCodec)
4287 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
4288
4289 /* Audio driver callbacks for multiplexing. */
4290 pThis->pCodec->pfnCloseIn = hdaCloseIn;
4291 pThis->pCodec->pfnCloseOut = hdaCloseOut;
4292 pThis->pCodec->pfnOpenIn = hdaOpenIn;
4293 pThis->pCodec->pfnOpenOut = hdaOpenOut;
4294 pThis->pCodec->pfnReset = hdaCodecReset;
4295 pThis->pCodec->pfnSetVolume = hdaSetVolume;
4296
4297 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
4298
4299 /* Construct the codec. */
4300 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
4301 if (RT_FAILURE(rc))
4302 AssertRCReturn(rc, rc);
4303
4304 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
4305 verb F20 should provide device/codec recognition. */
4306 Assert(pThis->pCodec->u16VendorId);
4307 Assert(pThis->pCodec->u16DeviceId);
4308 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
4309 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
4310 }
4311
4312 if (RT_SUCCESS(rc))
4313 {
4314 hdaReset(pDevIns);
4315
4316 /*
4317 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4318 * hdaReset shouldn't affects these registers.
4319 */
4320 HDA_REG(pThis, WAKEEN) = 0x0;
4321 HDA_REG(pThis, STATESTS) = 0x0;
4322
4323#ifdef DEBUG
4324 /*
4325 * Debug and string formatter types.
4326 */
4327 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
4328 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
4329 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
4330 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
4331 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaInfoMixer);
4332
4333 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
4334 AssertRC(rc);
4335 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
4336 AssertRC(rc);
4337 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
4338 AssertRC(rc);
4339 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
4340 AssertRC(rc);
4341 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
4342 AssertRC(rc);
4343#endif /* DEBUG */
4344
4345 /*
4346 * Some debug assertions.
4347 */
4348 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
4349 {
4350 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
4351 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
4352
4353 /* binary search order. */
4354 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
4355 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4356 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4357
4358 /* alignment. */
4359 AssertReleaseMsg( pReg->size == 1
4360 || (pReg->size == 2 && (pReg->offset & 1) == 0)
4361 || (pReg->size == 3 && (pReg->offset & 3) == 0)
4362 || (pReg->size == 4 && (pReg->offset & 3) == 0),
4363 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4364
4365 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
4366 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
4367 if (pReg->offset & 3)
4368 {
4369 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
4370 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4371 if (pPrevReg)
4372 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
4373 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4374 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
4375 }
4376#if 0
4377 if ((pReg->offset + pReg->size) & 3)
4378 {
4379 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4380 if (pNextReg)
4381 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
4382 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4383 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4384 }
4385#endif
4386 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
4387 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
4388 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4389 }
4390 }
4391
4392# ifndef VBOX_WITH_AUDIO_CALLBACKS
4393 if (RT_SUCCESS(rc))
4394 {
4395 /* Start the emulation timer. */
4396 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
4397 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
4398 AssertRCReturn(rc, rc);
4399
4400 if (RT_SUCCESS(rc))
4401 {
4402 /** @todo Investigate why sounds is getting corrupted if the "ticks" value is too
4403 * low, e.g. "PDMDevHlpTMTimeVirtGetFreq / 200". */
4404 pThis->uTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 500; /** @todo Make this configurable! */
4405 if (pThis->uTicks < 100)
4406 pThis->uTicks = 100;
4407 LogFunc(("Timer ticks=%RU64\n", pThis->uTicks));
4408
4409 /* Fire off timer. */
4410 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
4411 }
4412 }
4413# else
4414 if (RT_SUCCESS(rc))
4415 {
4416 PHDADRIVER pDrv;
4417 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4418 {
4419 /* Only register primary driver.
4420 * The device emulation does the output multiplexing then. */
4421 if (pDrv->Flags != PDMAUDIODRVFLAG_PRIMARY)
4422 continue;
4423
4424 PDMAUDIOCALLBACK AudioCallbacks[2];
4425
4426 HDACALLBACKCTX Ctx = { pThis, pDrv };
4427
4428 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
4429 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
4430 AudioCallbacks[0].pvCtx = &Ctx;
4431 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
4432
4433 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
4434 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
4435 AudioCallbacks[1].pvCtx = &Ctx;
4436 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
4437
4438 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
4439 if (RT_FAILURE(rc))
4440 break;
4441 }
4442 }
4443# endif
4444
4445# ifdef VBOX_WITH_STATISTICS
4446 if (RT_SUCCESS(rc))
4447 {
4448 /*
4449 * Register statistics.
4450 */
4451# ifndef VBOX_WITH_AUDIO_CALLBACKS
4452 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
4453# endif
4454 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
4455 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
4456 }
4457# endif
4458
4459 LogFlowFuncLeaveRC(rc);
4460 return rc;
4461}
4462
4463/**
4464 * The device registration structure.
4465 */
4466const PDMDEVREG g_DeviceICH6_HDA =
4467{
4468 /* u32Version */
4469 PDM_DEVREG_VERSION,
4470 /* szName */
4471 "hda",
4472 /* szRCMod */
4473 "VBoxDDRC.rc",
4474 /* szR0Mod */
4475 "VBoxDDR0.r0",
4476 /* pszDescription */
4477 "Intel HD Audio Controller",
4478 /* fFlags */
4479 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
4480 /* fClass */
4481 PDM_DEVREG_CLASS_AUDIO,
4482 /* cMaxInstances */
4483 1,
4484 /* cbInstance */
4485 sizeof(HDASTATE),
4486 /* pfnConstruct */
4487 hdaConstruct,
4488 /* pfnDestruct */
4489 hdaDestruct,
4490 /* pfnRelocate */
4491 NULL,
4492 /* pfnMemSetup */
4493 NULL,
4494 /* pfnPowerOn */
4495 NULL,
4496 /* pfnReset */
4497 hdaReset,
4498 /* pfnSuspend */
4499 NULL,
4500 /* pfnResume */
4501 NULL,
4502 /* pfnAttach */
4503 NULL,
4504 /* pfnDetach */
4505 NULL,
4506 /* pfnQueryInterface. */
4507 NULL,
4508 /* pfnInitComplete */
4509 NULL,
4510 /* pfnPowerOff */
4511 NULL,
4512 /* pfnSoftReset */
4513 NULL,
4514 /* u32VersionEnd */
4515 PDM_DEVREG_VERSION
4516};
4517
4518#endif /* IN_RING3 */
4519#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette