VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 58926

Last change on this file since 58926 was 58926, checked in by vboxsync, 9 years ago

HDA: Handle the DMA buffer position bit, comments.
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1/* $Id: DevIchHda.cpp 58926 2015-11-30 22:11:22Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2015 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/list.h>
36#ifdef IN_RING3
37# include <iprt/mem.h>
38# include <iprt/string.h>
39# include <iprt/uuid.h>
40#endif
41
42#include "VBoxDD.h"
43
44#include "AudioMixer.h"
45#include "DevIchHdaCodec.h"
46
47
48/*********************************************************************************************************************************
49* Defined Constants And Macros *
50*********************************************************************************************************************************/
51//#define HDA_AS_PCI_EXPRESS
52#define VBOX_WITH_INTEL_HDA
53
54#if (defined(DEBUG) && defined(DEBUG_andy))
55/* Enables experimental support for separate mic-in handling.
56 Do not enable this yet for regular builds, as this needs more testing first! */
57# define VBOX_WITH_HDA_MIC_IN
58#endif
59
60#if defined(VBOX_WITH_HP_HDA)
61/* HP Pavilion dv4t-1300 */
62# define HDA_PCI_VENDOR_ID 0x103c
63# define HDA_PCI_DEVICE_ID 0x30f7
64#elif defined(VBOX_WITH_INTEL_HDA)
65/* Intel HDA controller */
66# define HDA_PCI_VENDOR_ID 0x8086
67# define HDA_PCI_DEVICE_ID 0x2668
68#elif defined(VBOX_WITH_NVIDIA_HDA)
69/* nVidia HDA controller */
70# define HDA_PCI_VENDOR_ID 0x10de
71# define HDA_PCI_DEVICE_ID 0x0ac0
72#else
73# error "Please specify your HDA device vendor/device IDs"
74#endif
75
76/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
77 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
78 * is read only except for bit 15 like the HDA spec states.
79 *
80 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
81 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
82#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
83
84#define HDA_NREGS 114
85#define HDA_NREGS_SAVED 112
86
87/**
88 * NB: Register values stored in memory (au32Regs[]) are indexed through
89 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
90 * register descriptors in g_aHdaRegMap[] are indexed through the
91 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
92 *
93 * The au32Regs[] layout is kept unchanged for saved state
94 * compatibility. */
95
96/* Registers */
97#define HDA_REG_IND_NAME(x) HDA_REG_##x
98#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
99#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
100#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
101#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
102#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
103#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
104#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
105
106
107#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
108#define HDA_RMX_GCAP 0
109/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
110 * oss (15:12) - number of output streams supported
111 * iss (11:8) - number of input streams supported
112 * bss (7:3) - number of bidirectional streams supported
113 * bds (2:1) - number of serial data out signals supported
114 * b64sup (0) - 64 bit addressing supported.
115 */
116#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
117 ( (((oss) & 0xF) << 12) \
118 | (((iss) & 0xF) << 8) \
119 | (((bss) & 0x1F) << 3) \
120 | (((bds) & 0x3) << 2) \
121 | ((b64sup) & 1))
122
123#define HDA_REG_VMIN 1 /* 0x02 */
124#define HDA_RMX_VMIN 1
125
126#define HDA_REG_VMAJ 2 /* 0x03 */
127#define HDA_RMX_VMAJ 2
128
129#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
130#define HDA_RMX_OUTPAY 3
131
132#define HDA_REG_INPAY 4 /* 0x06-0x07 */
133#define HDA_RMX_INPAY 4
134
135#define HDA_REG_GCTL 5 /* 0x08-0x0B */
136#define HDA_RMX_GCTL 5
137#define HDA_GCTL_RST_SHIFT 0
138#define HDA_GCTL_FSH_SHIFT 1
139#define HDA_GCTL_UR_SHIFT 8
140
141#define HDA_REG_WAKEEN 6 /* 0x0C */
142#define HDA_RMX_WAKEEN 6
143
144#define HDA_REG_STATESTS 7 /* 0x0E */
145#define HDA_RMX_STATESTS 7
146#define HDA_STATES_SCSF 0x7
147
148#define HDA_REG_GSTS 8 /* 0x10-0x11*/
149#define HDA_RMX_GSTS 8
150#define HDA_GSTS_FSH_SHIFT 1
151
152#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
153#define HDA_RMX_OUTSTRMPAY 112
154
155#define HDA_REG_INSTRMPAY 10 /* 0x1a */
156#define HDA_RMX_INSTRMPAY 113
157
158#define HDA_REG_INTCTL 11 /* 0x20 */
159#define HDA_RMX_INTCTL 9
160#define HDA_INTCTL_GIE_SHIFT 31
161#define HDA_INTCTL_CIE_SHIFT 30
162#define HDA_INTCTL_S0_SHIFT 0
163#define HDA_INTCTL_S1_SHIFT 1
164#define HDA_INTCTL_S2_SHIFT 2
165#define HDA_INTCTL_S3_SHIFT 3
166#define HDA_INTCTL_S4_SHIFT 4
167#define HDA_INTCTL_S5_SHIFT 5
168#define HDA_INTCTL_S6_SHIFT 6
169#define HDA_INTCTL_S7_SHIFT 7
170#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
171
172#define HDA_REG_INTSTS 12 /* 0x24 */
173#define HDA_RMX_INTSTS 10
174#define HDA_INTSTS_GIS_SHIFT 31
175#define HDA_INTSTS_CIS_SHIFT 30
176#define HDA_INTSTS_S0_SHIFT 0
177#define HDA_INTSTS_S1_SHIFT 1
178#define HDA_INTSTS_S2_SHIFT 2
179#define HDA_INTSTS_S3_SHIFT 3
180#define HDA_INTSTS_S4_SHIFT 4
181#define HDA_INTSTS_S5_SHIFT 5
182#define HDA_INTSTS_S6_SHIFT 6
183#define HDA_INTSTS_S7_SHIFT 7
184#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
185
186#define HDA_REG_WALCLK 13 /* 0x24 */
187#define HDA_RMX_WALCLK /* Not defined! */
188
189/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
190 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
191 * the datasheet.
192 */
193#define HDA_REG_SSYNC 14 /* 0x34 */
194#define HDA_RMX_SSYNC 12
195
196#define HDA_REG_CORBLBASE 15 /* 0x40 */
197#define HDA_RMX_CORBLBASE 13
198
199#define HDA_REG_CORBUBASE 16 /* 0x44 */
200#define HDA_RMX_CORBUBASE 14
201
202#define HDA_REG_CORBWP 17 /* 0x48 */
203#define HDA_RMX_CORBWP 15
204
205#define HDA_REG_CORBRP 18 /* 0x4A */
206#define HDA_RMX_CORBRP 16
207#define HDA_CORBRP_RST_SHIFT 15
208#define HDA_CORBRP_WP_SHIFT 0
209#define HDA_CORBRP_WP_MASK 0xFF
210
211#define HDA_REG_CORBCTL 19 /* 0x4C */
212#define HDA_RMX_CORBCTL 17
213#define HDA_CORBCTL_DMA_SHIFT 1
214#define HDA_CORBCTL_CMEIE_SHIFT 0
215
216#define HDA_REG_CORBSTS 20 /* 0x4D */
217#define HDA_RMX_CORBSTS 18
218#define HDA_CORBSTS_CMEI_SHIFT 0
219
220#define HDA_REG_CORBSIZE 21 /* 0x4E */
221#define HDA_RMX_CORBSIZE 19
222#define HDA_CORBSIZE_SZ_CAP 0xF0
223#define HDA_CORBSIZE_SZ 0x3
224/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
225
226#define HDA_REG_RIRBLBASE 22 /* 0x50 */
227#define HDA_RMX_RIRBLBASE 20
228
229#define HDA_REG_RIRBUBASE 23 /* 0x54 */
230#define HDA_RMX_RIRBUBASE 21
231
232#define HDA_REG_RIRBWP 24 /* 0x58 */
233#define HDA_RMX_RIRBWP 22
234#define HDA_RIRBWP_RST_SHIFT 15
235#define HDA_RIRBWP_WP_MASK 0xFF
236
237#define HDA_REG_RINTCNT 25 /* 0x5A */
238#define HDA_RMX_RINTCNT 23
239#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
240
241#define HDA_REG_RIRBCTL 26 /* 0x5C */
242#define HDA_RMX_RIRBCTL 24
243#define HDA_RIRBCTL_RIC_SHIFT 0
244#define HDA_RIRBCTL_DMA_SHIFT 1
245#define HDA_ROI_DMA_SHIFT 2
246
247#define HDA_REG_RIRBSTS 27 /* 0x5D */
248#define HDA_RMX_RIRBSTS 25
249#define HDA_RIRBSTS_RINTFL_SHIFT 0
250#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
251
252#define HDA_REG_RIRBSIZE 28 /* 0x5E */
253#define HDA_RMX_RIRBSIZE 26
254#define HDA_RIRBSIZE_SZ_CAP 0xF0
255#define HDA_RIRBSIZE_SZ 0x3
256
257#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
258#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
259
260
261#define HDA_REG_IC 29 /* 0x60 */
262#define HDA_RMX_IC 27
263
264#define HDA_REG_IR 30 /* 0x64 */
265#define HDA_RMX_IR 28
266
267#define HDA_REG_IRS 31 /* 0x68 */
268#define HDA_RMX_IRS 29
269#define HDA_IRS_ICB_SHIFT 0
270#define HDA_IRS_IRV_SHIFT 1
271
272#define HDA_REG_DPLBASE 32 /* 0x70 */
273#define HDA_RMX_DPLBASE 30
274#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
275
276#define HDA_REG_DPUBASE 33 /* 0x74 */
277#define HDA_RMX_DPUBASE 31
278#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
279
280#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
281
282#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
283#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
284/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
285#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
286
287#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
288
289#define HDA_REG_SD0CTL 34 /* 0x80 */
290#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
291#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
292#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
293#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
294#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
295#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
296#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
297#define HDA_RMX_SD0CTL 32
298#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
299#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
300#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
301#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
302#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
303#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
304#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
305
306#define SD(func, num) SD##num##func
307
308#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
309#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
310#define HDA_SDCTL_NUM_MASK 0xF
311#define HDA_SDCTL_NUM_SHIFT 20
312#define HDA_SDCTL_DIR_SHIFT 19
313#define HDA_SDCTL_TP_SHIFT 18
314#define HDA_SDCTL_STRIPE_MASK 0x3
315#define HDA_SDCTL_STRIPE_SHIFT 16
316#define HDA_SDCTL_DEIE_SHIFT 4
317#define HDA_SDCTL_FEIE_SHIFT 3
318#define HDA_SDCTL_ICE_SHIFT 2
319#define HDA_SDCTL_RUN_SHIFT 1
320#define HDA_SDCTL_SRST_SHIFT 0
321
322#define HDA_REG_SD0STS 35 /* 0x83 */
323#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
324#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
325#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
326#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
327#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
328#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
329#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
330#define HDA_RMX_SD0STS 33
331#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
332#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
333#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
334#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
335#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
336#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
337#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
338
339#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
340#define HDA_SDSTS_FIFORDY_SHIFT 5
341#define HDA_SDSTS_DE_SHIFT 4
342#define HDA_SDSTS_FE_SHIFT 3
343#define HDA_SDSTS_BCIS_SHIFT 2
344
345#define HDA_REG_SD0LPIB 36 /* 0x84 */
346#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
347#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
348#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
349#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
350#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
351#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
352#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
353#define HDA_RMX_SD0LPIB 34
354#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
355#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
356#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
357#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
358#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
359#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
360#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
361
362#define HDA_REG_SD0CBL 37 /* 0x88 */
363#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
364#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
365#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
366#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
367#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
368#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
369#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
370#define HDA_RMX_SD0CBL 35
371#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
372#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
373#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
374#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
375#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
376#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
377#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
378
379#define HDA_REG_SD0LVI 38 /* 0x8C */
380#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
381#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
382#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
383#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
384#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
385#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
386#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
387#define HDA_RMX_SD0LVI 36
388#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
389#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
390#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
391#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
392#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
393#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
394#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
395
396#define HDA_REG_SD0FIFOW 39 /* 0x8E */
397#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
398#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
399#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
400#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
401#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
402#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
403#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
404#define HDA_RMX_SD0FIFOW 37
405#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
406#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
407#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
408#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
409#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
410#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
411#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
412
413/*
414 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
415 */
416#define HDA_SDFIFOW_8B 0x2
417#define HDA_SDFIFOW_16B 0x3
418#define HDA_SDFIFOW_32B 0x4
419
420#define HDA_REG_SD0FIFOS 40 /* 0x90 */
421#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
422#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
423#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
424#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
425#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
426#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
427#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
428#define HDA_RMX_SD0FIFOS 38
429#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
430#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
431#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
432#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
433#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
434#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
435#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
436
437/*
438 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
439 * formula: size - 1
440 * Other values not listed are not supported.
441 */
442#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
443#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
444
445#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
446#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
447#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
448#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
449#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
450#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
451#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
452
453#define HDA_REG_SD0FMT 41 /* 0x92 */
454#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
455#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
456#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
457#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
458#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
459#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
460#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
461#define HDA_RMX_SD0FMT 39
462#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
463#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
464#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
465#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
466#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
467#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
468#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
469
470#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
471#define HDA_SDFMT_BASE_RATE_SHIFT 14
472#define HDA_SDFMT_MULT_SHIFT 11
473#define HDA_SDFMT_MULT_MASK 0x7
474#define HDA_SDFMT_DIV_SHIFT 8
475#define HDA_SDFMT_DIV_MASK 0x7
476#define HDA_SDFMT_BITS_SHIFT 4
477#define HDA_SDFMT_BITS_MASK 0x7
478#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
479#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
480#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
481
482#define HDA_REG_SD0BDPL 42 /* 0x98 */
483#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
484#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
485#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
486#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
487#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
488#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
489#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
490#define HDA_RMX_SD0BDPL 40
491#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
492#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
493#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
494#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
495#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
496#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
497#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
498
499#define HDA_REG_SD0BDPU 43 /* 0x9C */
500#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
501#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
502#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
503#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
504#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
505#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
506#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
507#define HDA_RMX_SD0BDPU 41
508#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
509#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
510#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
511#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
512#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
513#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
514#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
515
516#define HDA_CODEC_CAD_SHIFT 28
517/* Encodes the (required) LUN into a codec command. */
518#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
519
520
521
522/*********************************************************************************************************************************
523* Structures and Typedefs *
524*********************************************************************************************************************************/
525
526/**
527 * Internal state of a Buffer Descriptor List Entry (BDLE),
528 * needed to keep track of the data needed for the actual device
529 * emulation.
530 */
531typedef struct HDABDLESTATE
532{
533 /** Own index within the BDL (Buffer Descriptor List). */
534 uint32_t u32BDLIndex;
535 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
536 * Used to check if we need fill up the FIFO again. */
537 uint32_t cbBelowFIFOW;
538 /** The buffer descriptor's internal DMA buffer. */
539 uint8_t au8FIFO[HDA_SDONFIFO_256B + 1];
540 /** Current offset in DMA buffer (in bytes).*/
541 uint32_t u32BufOff;
542 uint32_t Padding;
543} HDABDLESTATE, *PHDABDLESTATE;
544
545/**
546 * Buffer Descriptor List Entry (BDLE) (3.6.3).
547 *
548 * Contains only register values which do *not* change until a
549 * stream reset occurs.
550 */
551typedef struct HDABDLE
552{
553 /** Starting address of the actual buffer. Must be 128-bit aligned. */
554 uint64_t u64BufAdr;
555 /** Size of the actual buffer (in bytes). */
556 uint32_t u32BufSize;
557 /** Interrupt on completion; the controller will generate
558 * an interrupt when the last byte of the buffer has been
559 * fetched by the DMA engine. */
560 bool fIntOnCompletion;
561 /** Internal state of this BDLE.
562 * Not part of the actual BDLE registers. */
563 HDABDLESTATE State;
564} HDABDLE, *PHDABDLE;
565
566/**
567 * Internal state of a HDA stream.
568 */
569typedef struct HDASTREAMSTATE
570{
571 /** Number of BDLEs (Buffer Descriptor List Entry).
572 * Should be SDnLVI + 1 usually. */
573 uint16_t cBDLE;
574 /** Current BDLE to use. Wraps around to 0 if
575 * maximum (cBDLE) is reached. */
576 uint16_t uCurBDLE;
577 uint32_t Padding;
578 /** Array of BDLEs. */
579 R3PTRTYPE(PHDABDLE) paBDLE;
580} HDASTREAMSTATE, *PHDASTREAMSTATE;
581
582/**
583 * Structure for keeping a HDA stream state.
584 *
585 * Contains only register values which do *not* change until a
586 * stream reset occurs.
587 */
588typedef struct HDASTREAM
589{
590 /** Stream number (SDn). */
591 uint8_t u8Strm;
592 uint8_t Padding0[7];
593 /** DMA base address (SDnBDPU - SDnBDPL). */
594 uint64_t u64BaseDMA;
595 /** Cyclic Buffer Length (SDnCBL).
596 * Represents the size of the ring buffer. */
597 uint32_t u32CBL;
598 /** Format (SDnFMT). */
599 uint16_t u16FMT;
600 /** FIFO Size (FIFOS).
601 * Maximum number of bytes that may have been DMA'd into
602 * memory but not yet transmitted on the link.
603 *
604 * Must be a power of two. */
605 uint16_t u16FIFOS;
606 /** Last Valid Index (SDnLVI). */
607 uint16_t u16LVI;
608 uint16_t Padding1[3];
609 /** Internal state of this stream. */
610 HDASTREAMSTATE State;
611} HDASTREAM, *PHDASTREAM;
612
613typedef struct HDAINPUTSTREAM
614{
615 /** PCM line input stream. */
616 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
617 /** Mixer handle for line input stream. */
618 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
619} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
620
621typedef struct HDAOUTPUTSTREAM
622{
623 /** PCM output stream. */
624 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
625 /** Mixer handle for line output stream. */
626 R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
627} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
628
629/**
630 * Struct for maintaining a host backend driver.
631 * This driver must be associated to one, and only one,
632 * HDA codec. The HDA controller does the actual multiplexing
633 * of HDA codec data to various host backend drivers then.
634 *
635 * This HDA device uses a timer in order to synchronize all
636 * read/write accesses across all attached LUNs / backends.
637 */
638typedef struct HDADRIVER
639{
640 union
641 {
642 /** Node for storing this driver in our device driver
643 * list of HDASTATE. */
644 RTLISTNODE Node;
645 struct
646 {
647 R3PTRTYPE(void *) dummy1;
648 R3PTRTYPE(void *) dummy2;
649 } dummy;
650 };
651
652 /** Pointer to HDA controller (state). */
653 R3PTRTYPE(PHDASTATE) pHDAState;
654 /** Driver flags. */
655 PDMAUDIODRVFLAGS Flags;
656 uint8_t u32Padding0[3];
657 /** LUN to which this driver has been assigned. */
658 uint8_t uLUN;
659 /** Audio connector interface to the underlying
660 * host backend. */
661 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
662 /** Stream for line input. */
663 HDAINPUTSTREAM LineIn;
664 /** Stream for mic input. */
665 HDAINPUTSTREAM MicIn;
666 /** Stream for output. */
667 HDAOUTPUTSTREAM Out;
668} HDADRIVER;
669
670/**
671 * ICH Intel HD Audio Controller state.
672 */
673typedef struct HDASTATE
674{
675 /** The PCI device structure. */
676 PCIDevice PciDev;
677 /** R3 Pointer to the device instance. */
678 PPDMDEVINSR3 pDevInsR3;
679 /** R0 Pointer to the device instance. */
680 PPDMDEVINSR0 pDevInsR0;
681 /** R0 Pointer to the device instance. */
682 PPDMDEVINSRC pDevInsRC;
683 /** Padding for alignment. */
684 uint32_t u32Padding;
685 /** Pointer to the attached audio driver. */
686 R3PTRTYPE(PPDMIBASE) pDrvBase;
687 /** The base interface for LUN\#0. */
688 PDMIBASE IBase;
689 RTGCPHYS MMIOBaseAddr;
690 /** The HDA's register set. */
691 uint32_t au32Regs[HDA_NREGS];
692 /** Stream state for line-in. */
693 HDASTREAM StrmStLineIn;
694 /** Stream state for microphone-in. */
695 HDASTREAM StrmStMicIn;
696 /** Stream state for output. */
697 HDASTREAM StrmStOut;
698 /** CORB buffer base address. */
699 uint64_t u64CORBBase;
700 /** RIRB buffer base address. */
701 uint64_t u64RIRBBase;
702 /** DMA base address.
703 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
704 uint64_t u64DPBase;
705 /** DMA position buffer enable bit. */
706 bool fDMAPosition;
707 /** Pointer to CORB buffer. */
708 R3PTRTYPE(uint32_t *) pu32CorbBuf;
709 /** Size in bytes of CORB buffer. */
710 uint32_t cbCorbBuf;
711 /** Padding for alignment. */
712 uint32_t u32Padding2;
713 /** Pointer to RIRB buffer. */
714 R3PTRTYPE(uint64_t *) pu64RirbBuf;
715 /** Size in bytes of RIRB buffer. */
716 uint32_t cbRirbBuf;
717 /** Indicates if HDA is in reset. */
718 bool fInReset;
719 /** Flag whether the R0 part is enabled. */
720 bool fR0Enabled;
721 /** Flag whether the RC part is enabled. */
722 bool fRCEnabled;
723 /** The emulation timer for handling the attached
724 * LUN drivers. */
725 PTMTIMERR3 pTimer;
726 /** Timer ticks for handling the LUN drivers. */
727 uint64_t uTicks;
728#ifdef VBOX_WITH_STATISTICS
729# ifndef VBOX_WITH_AUDIO_CALLBACKS
730 STAMPROFILE StatTimer;
731# endif
732 STAMCOUNTER StatBytesRead;
733 STAMCOUNTER StatBytesWritten;
734#endif
735 /** Pointer to HDA codec to use. */
736 R3PTRTYPE(PHDACODEC) pCodec;
737 union
738 {
739 /** List of associated LUN drivers. */
740 RTLISTANCHOR lstDrv;
741 /** Padding for alignment. */
742 struct
743 {
744 R3PTRTYPE(void *) dummy1;
745 R3PTRTYPE(void *) dummy2;
746 } dummy;
747 };
748 /** The device' software mixer. */
749 R3PTRTYPE(PAUDIOMIXER) pMixer;
750 /** Audio sink for PCM output. */
751 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
752 /** Audio mixer sink for line input. */
753 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
754 /** Audio mixer sink for microphone input. */
755 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
756 uint64_t u64BaseTS;
757 /** Response Interrupt Count (RINTCNT). */
758 uint8_t u8RespIntCnt;
759 /** Padding for alignment. */
760 uint8_t au8Padding[7];
761} HDASTATE;
762/** Pointer to the ICH Intel HD Audio Controller state. */
763typedef HDASTATE *PHDASTATE;
764
765#ifdef VBOX_WITH_AUDIO_CALLBACKS
766typedef struct HDACALLBACKCTX
767{
768 PHDASTATE pThis;
769 PHDADRIVER pDriver;
770} HDACALLBACKCTX, *PHDACALLBACKCTX;
771#endif
772
773/*********************************************************************************************************************************
774* Internal Functions *
775*********************************************************************************************************************************/
776#ifndef VBOX_DEVICE_STRUCT_TESTCASE
777static FNPDMDEVRESET hdaReset;
778
779/*
780 * Stubs.
781 */
782static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
783static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
784
785/*
786 * Global register set read/write functions.
787 */
788static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
789static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
790static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
791static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
792static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
793static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
794static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
795static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
796static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
797static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
798static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
799static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
800static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
801static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
802static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
803
804/*
805 * {IOB}SDn read/write functions.
806 */
807static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
808static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
809static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
810static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
811static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
812static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
813static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
814static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
815static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
816
817/*
818 * Generic register read/write functions.
819 */
820static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
821static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
822static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
823static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
824static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
825static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
826static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
827static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
828
829static void hdaStreamDestroy(PHDASTREAM pStrmSt);
830
831static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t *pcbProcessed);
832
833#ifdef IN_RING3
834static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
835# ifdef LOG_ENABLED
836static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t u16LVI);
837# endif
838static void hdaBDLEReset(PHDABDLE pBDLE);
839#endif
840
841
842/*********************************************************************************************************************************
843* Global Variables *
844*********************************************************************************************************************************/
845
846/** Offset of the SD0 register map. */
847#define HDA_REG_DESC_SD0_BASE 0x80
848
849/** Turn a short global register name into an memory index and a stringized name. */
850#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
851
852/** Turns a short stream register name into an memory index and a stringized name. */
853#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
854
855/** Same as above for a register *not* stored in memory. */
856#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
857
858/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
859#define HDA_REG_MAP_STRM(offset, name) \
860 /* offset size read mask write mask read callback write callback index + abbrev description */ \
861 /* ------- ------- ---------- ---------- -------------- ----------------- ------------------------------ ----------- */ \
862 /* Offset 0x80 (SD0) */ \
863 { offset, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
864 /* Offset 0x83 (SD0) */ \
865 { offset + 0x3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
866 /* Offset 0x84 (SD0) */ \
867 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
868 /* Offset 0x88 (SD0) */ \
869 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
870 /* Offset 0x8C (SD0) */ \
871 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
872 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
873 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
874 /* Offset 0x90 (SD0) */ \
875 { offset + 0x10, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16, hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
876 /* Offset 0x92 (SD0) */ \
877 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Format" }, \
878 /* Reserved: 0x94 - 0x98. */ \
879 /* Offset 0x98 (SD0) */ \
880 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
881 /* Offset 0x9C (SD0) */ \
882 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
883
884/** Defines a single audio stream register set (e.g. OSD0). */
885#define HDA_REG_MAP_DEF_STREAM(index, name) \
886 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
887
888/* See 302349 p 6.2. */
889static const struct HDAREGDESC
890{
891 /** Register offset in the register space. */
892 uint32_t offset;
893 /** Size in bytes. Registers of size > 4 are in fact tables. */
894 uint32_t size;
895 /** Readable bits. */
896 uint32_t readable;
897 /** Writable bits. */
898 uint32_t writable;
899 /** Read callback. */
900 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
901 /** Write callback. */
902 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
903 /** Index into the register storage array. */
904 uint32_t mem_idx;
905 /** Abbreviated name. */
906 const char *abbrev;
907 /** Descripton. */
908 const char *desc;
909} g_aHdaRegMap[HDA_NREGS] =
910
911{
912 /* offset size read mask write mask read callback write callback index + abbrev */
913 /*------- ------- ---------- ---------- ----------------------- ---------------------- ---------------- */
914 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
915 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
916 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
917 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
918 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
919 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
920 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
921 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , HDA_REG_IDX(STATESTS) }, /* State Change Status */
922 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
923 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
924 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
925 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
926 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
927 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
928 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
929 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
930 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
931 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
932 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
933 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
934 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
935 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
936 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
937 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
938 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
939 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
940 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
941 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
942 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
943 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
944 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
945 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
946 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
947 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
948 /* 4 Input Stream Descriptors (ISD). */
949 HDA_REG_MAP_DEF_STREAM(0, SD0),
950 HDA_REG_MAP_DEF_STREAM(1, SD1),
951 HDA_REG_MAP_DEF_STREAM(2, SD2),
952 HDA_REG_MAP_DEF_STREAM(3, SD3),
953 /* 4 Output Stream Descriptors (OSD). */
954 HDA_REG_MAP_DEF_STREAM(4, SD4),
955 HDA_REG_MAP_DEF_STREAM(5, SD5),
956 HDA_REG_MAP_DEF_STREAM(6, SD6),
957 HDA_REG_MAP_DEF_STREAM(7, SD7)
958};
959
960/**
961 * HDA register aliases (HDA spec 3.3.45).
962 * @remarks Sorted by offReg.
963 */
964static const struct
965{
966 /** The alias register offset. */
967 uint32_t offReg;
968 /** The register index. */
969 int idxAlias;
970} g_aHdaRegAliases[] =
971{
972 { 0x2084, HDA_REG_SD0LPIB },
973 { 0x20a4, HDA_REG_SD1LPIB },
974 { 0x20c4, HDA_REG_SD2LPIB },
975 { 0x20e4, HDA_REG_SD3LPIB },
976 { 0x2104, HDA_REG_SD4LPIB },
977 { 0x2124, HDA_REG_SD5LPIB },
978 { 0x2144, HDA_REG_SD6LPIB },
979 { 0x2164, HDA_REG_SD7LPIB },
980};
981
982#ifdef IN_RING3
983/** HDABDLESTATE field descriptors for the v5+ saved state. */
984static SSMFIELD const g_aSSMBDLEStateFields5[] =
985{
986 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
987 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
988 SSMFIELD_ENTRY(HDABDLESTATE, au8FIFO),
989 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
990 SSMFIELD_ENTRY_TERM()
991};
992
993/** HDASTREAMSTATE field descriptors for the v5+ saved state. */
994static SSMFIELD const g_aSSMStreamStateFields5[] =
995{
996 SSMFIELD_ENTRY (HDASTREAMSTATE, cBDLE),
997 SSMFIELD_ENTRY (HDASTREAMSTATE, uCurBDLE),
998 SSMFIELD_ENTRY_IGNORE(HDASTREAMSTATE, paBDLE),
999 SSMFIELD_ENTRY_TERM()
1000};
1001#endif
1002
1003/**
1004 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1005 */
1006static uint32_t const g_afMasks[5] =
1007{
1008 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1009};
1010
1011#ifdef IN_RING3
1012DECLINLINE(void) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t u32LPIB)
1013{
1014 AssertPtrReturnVoid(pThis);
1015 AssertPtrReturnVoid(pStrmSt);
1016
1017 Assert(u32LPIB <= pStrmSt->u32CBL);
1018
1019 LogFlowFunc(("uStrm=%RU8, LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1020 pStrmSt->u8Strm, u32LPIB, pThis->fDMAPosition));
1021
1022 /* Update LPIB in any case. */
1023 HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) = u32LPIB;
1024
1025 /* Do we need to tell the current DMA position? */
1026 if (pThis->fDMAPosition)
1027 {
1028 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1029 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStrmSt->u8Strm * 8),
1030 (void *)&u32LPIB, sizeof(uint32_t));
1031 AssertRC(rc2);
1032 }
1033}
1034#endif
1035
1036/**
1037 * Retrieves the number of bytes of a FIFOS register.
1038 *
1039 * @return Number of bytes of a given FIFOS register.
1040 */
1041DECLINLINE(uint16_t) hdaSDFIFOSToBytes(uint32_t u32RegFIFOS)
1042{
1043 uint16_t cb;
1044 switch (u32RegFIFOS)
1045 {
1046 /* Input */
1047 case HDA_SDINFIFO_120B: cb = 120; break;
1048 case HDA_SDINFIFO_160B: cb = 160; break;
1049
1050 /* Output */
1051 case HDA_SDONFIFO_16B: cb = 16; break;
1052 case HDA_SDONFIFO_32B: cb = 32; break;
1053 case HDA_SDONFIFO_64B: cb = 64; break;
1054 case HDA_SDONFIFO_128B: cb = 128; break;
1055 case HDA_SDONFIFO_192B: cb = 192; break;
1056 case HDA_SDONFIFO_256B: cb = 256; break;
1057 default:
1058 {
1059 cb = 0;
1060 AssertMsgFailed(("Wrong FIFO value\n"));
1061 break;
1062 }
1063 }
1064
1065 return cb;
1066}
1067
1068/**
1069 * Retrieves the number of bytes of a FIFOW register.
1070 *
1071 * @return Number of bytes of a given FIFOW register.
1072 */
1073DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1074{
1075 uint32_t cb;
1076 switch (u32RegFIFOW)
1077 {
1078 case HDA_SDFIFOW_8B: cb = 8; break;
1079 case HDA_SDFIFOW_16B: cb = 16; break;
1080 case HDA_SDFIFOW_32B: cb = 32; break;
1081 default: cb = 0; break;
1082 }
1083
1084#ifdef RT_STRICT
1085 Assert(RT_IS_POWER_OF_TWO(cb));
1086#endif
1087 return cb;
1088}
1089
1090#ifdef IN_RING3
1091/**
1092 * Returns the current BDLE to use for a stream.
1093 *
1094 * @return BDLE to use, NULL if none found.
1095 */
1096DECLINLINE(PHDABDLE) hdaStreamGetCurrentBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
1097{
1098 AssertPtrReturn(pThis, NULL);
1099 AssertPtrReturn(pStrmSt, NULL);
1100
1101 Assert(pStrmSt->State.paBDLE);
1102 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1103
1104 PHDABDLE pBDLE = &pStrmSt->State.paBDLE[pStrmSt->State.uCurBDLE];
1105 return pBDLE;
1106}
1107
1108/**
1109 * Returns the next BDLE to use for a stream.
1110 *
1111 * @return BDLE to use next, NULL if none found.
1112 */
1113DECLINLINE(PHDABDLE) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
1114{
1115 AssertPtrReturn(pThis, NULL);
1116 AssertPtrReturn(pStrmSt, NULL);
1117
1118 NOREF(pThis);
1119
1120 Assert(pStrmSt->State.paBDLE);
1121 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1122
1123#ifdef DEBUG
1124 uint32_t uOldBDLE = pStrmSt->State.uCurBDLE;
1125#endif
1126
1127 /*
1128 * Switch to the next BDLE entry and do a wrap around
1129 * if we reached the end of the Buffer Descriptor List (BDL).
1130 */
1131 pStrmSt->State.uCurBDLE++;
1132 if (pStrmSt->State.uCurBDLE == pStrmSt->State.cBDLE)
1133 {
1134 pStrmSt->State.uCurBDLE = 0;
1135
1136 hdaStreamUpdateLPIB(pThis, pStrmSt, 0);
1137 }
1138
1139 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1140
1141 PHDABDLE pBDLE = &pStrmSt->State.paBDLE[pStrmSt->State.uCurBDLE];
1142 AssertPtr(pBDLE);
1143
1144 hdaBDLEReset(pBDLE);
1145
1146#ifdef DEBUG
1147 LogFlowFunc(("uOldBDLE=%RU16, uCurBDLE=%RU16, cBDLE=%RU32, %R[bdle]\n",
1148 uOldBDLE, pStrmSt->State.uCurBDLE, pStrmSt->State.cBDLE, pBDLE));
1149#endif
1150 return pBDLE;
1151}
1152#endif
1153
1154/**
1155 * Retrieves the minimum number of bytes accumulated/free in the
1156 * FIFO before the controller will start a fetch/eviction of data.
1157 *
1158 * Uses SDFIFOW (FIFO Watermark Register).
1159 *
1160 * @return Number of bytes accumulated/free in the FIFO.
1161 */
1162DECLINLINE(uint8_t) hdaStreamGetFIFOW(PHDASTATE pThis, PHDASTREAM pStrmSt)
1163{
1164 AssertPtrReturn(pThis, 0);
1165 AssertPtrReturn(pStrmSt, 0);
1166
1167#ifdef VBOX_HDA_WITH_FIFO
1168 return hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, pStrmSt->u8Strm));
1169#else
1170 return 0;
1171#endif
1172}
1173
1174static int hdaProcessInterrupt(PHDASTATE pThis)
1175{
1176#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1177 ( INTCTL_SX((pThis), num) \
1178 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1179
1180 bool fIrq = false;
1181
1182 if (/* Controller Interrupt Enable (CIE). */
1183 HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1184 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1185 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1186 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1187 fIrq = true;
1188
1189 /** @todo Don't hardcode stream numbers here. */
1190 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1191 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1192 {
1193#ifdef IN_RING3
1194 LogFunc(("BCIS\n"));
1195#endif
1196 fIrq = true;
1197 }
1198
1199 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1200 {
1201 LogFunc(("%s\n", fIrq ? "Asserted" : "Deasserted"));
1202 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1203 }
1204
1205#undef IS_INTERRUPT_OCCURED_AND_ENABLED
1206
1207 return VINF_SUCCESS;
1208}
1209
1210/**
1211 * Looks up a register at the exact offset given by @a offReg.
1212 *
1213 * @returns Register index on success, -1 if not found.
1214 * @param pThis The HDA device state.
1215 * @param offReg The register offset.
1216 */
1217static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1218{
1219 /*
1220 * Aliases.
1221 */
1222 if (offReg >= g_aHdaRegAliases[0].offReg)
1223 {
1224 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1225 if (offReg == g_aHdaRegAliases[i].offReg)
1226 return g_aHdaRegAliases[i].idxAlias;
1227 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1228 return -1;
1229 }
1230
1231 /*
1232 * Binary search the
1233 */
1234 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1235 int idxLow = 0;
1236 for (;;)
1237 {
1238 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1239 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1240 {
1241 if (idxLow == idxMiddle)
1242 break;
1243 idxEnd = idxMiddle;
1244 }
1245 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1246 {
1247 idxLow = idxMiddle + 1;
1248 if (idxLow >= idxEnd)
1249 break;
1250 }
1251 else
1252 return idxMiddle;
1253 }
1254
1255#ifdef RT_STRICT
1256 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1257 Assert(g_aHdaRegMap[i].offset != offReg);
1258#endif
1259 return -1;
1260}
1261
1262/**
1263 * Looks up a register covering the offset given by @a offReg.
1264 *
1265 * @returns Register index on success, -1 if not found.
1266 * @param pThis The HDA device state.
1267 * @param offReg The register offset.
1268 */
1269static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1270{
1271 /*
1272 * Aliases.
1273 */
1274 if (offReg >= g_aHdaRegAliases[0].offReg)
1275 {
1276 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1277 {
1278 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1279 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1280 return g_aHdaRegAliases[i].idxAlias;
1281 }
1282 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1283 return -1;
1284 }
1285
1286 /*
1287 * Binary search the register map.
1288 */
1289 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1290 int idxLow = 0;
1291 for (;;)
1292 {
1293 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1294 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1295 {
1296 if (idxLow == idxMiddle)
1297 break;
1298 idxEnd = idxMiddle;
1299 }
1300 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1301 {
1302 idxLow = idxMiddle + 1;
1303 if (idxLow >= idxEnd)
1304 break;
1305 }
1306 else
1307 return idxMiddle;
1308 }
1309
1310#ifdef RT_STRICT
1311 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1312 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1313#endif
1314 return -1;
1315}
1316
1317#ifdef IN_RING3
1318static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1319{
1320 int rc = VINF_SUCCESS;
1321 if (fLocal)
1322 {
1323 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1324 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1325 if (RT_FAILURE(rc))
1326 AssertRCReturn(rc, rc);
1327#ifdef DEBUG_CMD_BUFFER
1328 uint8_t i = 0;
1329 do
1330 {
1331 LogFunc(("CORB%02x: ", i));
1332 uint8_t j = 0;
1333 do
1334 {
1335 const char *pszPrefix;
1336 if ((i + j) == HDA_REG(pThis, CORBRP));
1337 pszPrefix = "[R]";
1338 else if ((i + j) == HDA_REG(pThis, CORBWP));
1339 pszPrefix = "[W]";
1340 else
1341 pszPrefix = " "; /* three spaces */
1342 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1343 j++;
1344 } while (j < 8);
1345 LogFunc(("\n"));
1346 i += 8;
1347 } while(i != 0);
1348#endif
1349 }
1350 else
1351 {
1352 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1353 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1354 if (RT_FAILURE(rc))
1355 AssertRCReturn(rc, rc);
1356#ifdef DEBUG_CMD_BUFFER
1357 uint8_t i = 0;
1358 do {
1359 LogFunc(("RIRB%02x: ", i));
1360 uint8_t j = 0;
1361 do {
1362 const char *prefix;
1363 if ((i + j) == HDA_REG(pThis, RIRBWP))
1364 prefix = "[W]";
1365 else
1366 prefix = " ";
1367 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1368 } while (++j < 8);
1369 LogFunc(("\n"));
1370 i += 8;
1371 } while (i != 0);
1372#endif
1373 }
1374 return rc;
1375}
1376
1377static int hdaCORBCmdProcess(PHDASTATE pThis)
1378{
1379 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1380
1381 int rc = hdaCmdSync(pThis, true);
1382 if (RT_FAILURE(rc))
1383 AssertRCReturn(rc, rc);
1384
1385 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1386 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1387 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1388
1389 Assert((corbWp != corbRp));
1390 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1391
1392 while (corbRp != corbWp)
1393 {
1394 uint32_t cmd;
1395 uint64_t resp;
1396 pfn = NULL;
1397 corbRp++;
1398 cmd = pThis->pu32CorbBuf[corbRp];
1399
1400 rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* Codec index */), &pfn);
1401 if (RT_SUCCESS(rc))
1402 {
1403 AssertPtr(pfn);
1404 rc = pfn(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1405 }
1406
1407 if (RT_FAILURE(rc))
1408 AssertRCReturn(rc, rc);
1409 (rirbWp)++;
1410
1411 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1412 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1413 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1414 {
1415 LogFunc(("unexpected unsolicited response.\n"));
1416 HDA_REG(pThis, CORBRP) = corbRp;
1417 return rc;
1418 }
1419
1420 pThis->pu64RirbBuf[rirbWp] = resp;
1421
1422 pThis->u8RespIntCnt++;
1423 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1424 break;
1425 }
1426 HDA_REG(pThis, CORBRP) = corbRp;
1427 HDA_REG(pThis, RIRBWP) = rirbWp;
1428 rc = hdaCmdSync(pThis, false);
1429 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1430 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1431 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1432 {
1433 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1434
1435 pThis->u8RespIntCnt = 0;
1436 rc = hdaProcessInterrupt(pThis);
1437 }
1438 if (RT_FAILURE(rc))
1439 AssertRCReturn(rc, rc);
1440 return rc;
1441}
1442
1443static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1444{
1445 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1446 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1447
1448 pStrmSt->u8Strm = u8Strm;
1449 pStrmSt->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
1450 HDA_STREAM_REG(pThis, BDPU, u8Strm));
1451 pStrmSt->u16LVI = HDA_STREAM_REG(pThis, LVI, u8Strm);
1452 pStrmSt->u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1453 pStrmSt->u16FIFOS = hdaSDFIFOSToBytes(HDA_STREAM_REG(pThis, FIFOS, u8Strm));
1454
1455 hdaStreamDestroy(pStrmSt);
1456
1457 int rc = VINF_SUCCESS;
1458
1459 if (pStrmSt->u16LVI) /* Any BDLEs to fetch? */
1460 {
1461 uint32_t cbBDLE = 0;
1462
1463 pStrmSt->State.cBDLE = pStrmSt->u16LVI + 1; /* See 18.2.37: If LVI is n, then there are n + 1 entries. */
1464 pStrmSt->State.paBDLE = (PHDABDLE)RTMemAllocZ(sizeof(HDABDLE) * pStrmSt->State.cBDLE);
1465 if (pStrmSt->State.paBDLE)
1466 {
1467 for (uint16_t i = 0; i < pStrmSt->State.cBDLE; i++)
1468 {
1469 rc = hdaBDLEFetch(pThis, &pStrmSt->State.paBDLE[i], pStrmSt->u64BaseDMA, i);
1470 if (RT_FAILURE(rc))
1471 break;
1472
1473 cbBDLE += pStrmSt->State.paBDLE[i].u32BufSize;
1474 }
1475
1476#ifdef DEBUG
1477 hdaBDLEDumpAll(pThis, pStrmSt->u64BaseDMA, pStrmSt->State.cBDLE);
1478#endif
1479 if (RT_SUCCESS(rc))
1480 {
1481 if (pStrmSt->u32CBL != cbBDLE)
1482 LogRel(("HDA: Warning: CBL (%RU32) does not match BDL entries (%RU32); expect sound hickups\n",
1483 pStrmSt->u32CBL, cbBDLE));
1484
1485 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1486 }
1487 }
1488 else
1489 rc = VERR_NO_MEMORY;
1490 }
1491
1492 LogFunc(("[SD%RU8]: DMA=0x%x, LVI=%RU16, CBL=%RU32, FIFOS=%RU16\n",
1493 u8Strm, pStrmSt->u64BaseDMA, pStrmSt->u16LVI, pStrmSt->u32CBL, pStrmSt->u16FIFOS));
1494
1495 return rc;
1496}
1497
1498static void hdaStreamDestroy(PHDASTREAM pStrmSt)
1499{
1500 AssertPtrReturnVoid(pStrmSt);
1501
1502 if (pStrmSt->State.paBDLE)
1503 {
1504 Assert(pStrmSt->State.cBDLE);
1505 RTMemFree(pStrmSt->State.paBDLE);
1506 pStrmSt->State.paBDLE = NULL;
1507 }
1508
1509 pStrmSt->State.cBDLE = 0;
1510}
1511#endif
1512
1513static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1514{
1515 AssertPtrReturnVoid(pThis);
1516 AssertPtrReturnVoid(pStrmSt);
1517 AssertReturnVoid(u8Strm <= 7); /** @todo Use a define for MAX_STRAEMS! */
1518
1519 /*
1520 * Initialize stream state.
1521 */
1522 RT_BZERO(pStrmSt, sizeof(HDASTREAM));
1523
1524 /*
1525 * Initialize registers.
1526 */
1527 HDA_STREAM_REG(pThis, STS, u8Strm) = 0;
1528 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1529 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1530 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1531
1532 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39. */
1533 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1534 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1535 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = HDA_SDFIFOW_32B;
1536 HDA_STREAM_REG(pThis, LPIB, u8Strm) = 0;
1537 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1538 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1539 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1540 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1541 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1542
1543 LogFunc(("[SD%RU8] Reset\n", u8Strm));
1544}
1545
1546/* Register access handlers. */
1547
1548static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1549{
1550 *pu32Value = 0;
1551 return VINF_SUCCESS;
1552}
1553
1554static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1555{
1556 return VINF_SUCCESS;
1557}
1558
1559/* U8 */
1560static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1561{
1562 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1563 return hdaRegReadU32(pThis, iReg, pu32Value);
1564}
1565
1566static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1567{
1568 Assert((u32Value & 0xffffff00) == 0);
1569 return hdaRegWriteU32(pThis, iReg, u32Value);
1570}
1571
1572/* U16 */
1573static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1574{
1575 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1576 return hdaRegReadU32(pThis, iReg, pu32Value);
1577}
1578
1579static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1580{
1581 Assert((u32Value & 0xffff0000) == 0);
1582 return hdaRegWriteU32(pThis, iReg, u32Value);
1583}
1584
1585/* U24 */
1586static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1587{
1588 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1589 return hdaRegReadU32(pThis, iReg, pu32Value);
1590}
1591
1592static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1593{
1594 Assert((u32Value & 0xff000000) == 0);
1595 return hdaRegWriteU32(pThis, iReg, u32Value);
1596}
1597
1598/* U32 */
1599static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1600{
1601 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1602
1603 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1604 return VINF_SUCCESS;
1605}
1606
1607static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1608{
1609 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1610
1611 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1612 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1613 return VINF_SUCCESS;
1614}
1615
1616static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1617{
1618 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1619 {
1620 /* Exit reset state. */
1621 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1622 pThis->fInReset = false;
1623 }
1624 else
1625 {
1626#ifdef IN_RING3
1627 /* Enter reset state. */
1628 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1629 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1630 {
1631 LogFunc(("HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1632 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1633 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1634 }
1635 hdaReset(pThis->CTX_SUFF(pDevIns));
1636 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1637 pThis->fInReset = true;
1638#else
1639 return VINF_IOM_R3_MMIO_WRITE;
1640#endif
1641 }
1642 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1643 {
1644 /* Flush: GSTS:1 set, see 6.2.6. */
1645 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
1646 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1647 }
1648 return VINF_SUCCESS;
1649}
1650
1651static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1652{
1653 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1654
1655 uint32_t v = pThis->au32Regs[iRegMem];
1656 uint32_t nv = u32Value & HDA_STATES_SCSF;
1657 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1658 return VINF_SUCCESS;
1659}
1660
1661static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1662{
1663 uint32_t v = 0;
1664 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1665 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1666 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1667 || HDA_REG(pThis, STATESTS))
1668 {
1669 v |= RT_BIT(30); /* Touch CIS. */
1670 }
1671
1672#define HDA_IS_STREAM_EVENT(pThis, num) \
1673 ( (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1674 || (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1675 || (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1676
1677#define HDA_MARK_STREAM(pThis, num, v) \
1678 do { (v) |= HDA_IS_STREAM_EVENT((pThis), num) ? RT_BIT((num)) : 0; } while(0)
1679
1680 HDA_MARK_STREAM(pThis, 0, v);
1681 HDA_MARK_STREAM(pThis, 1, v);
1682 HDA_MARK_STREAM(pThis, 2, v);
1683 HDA_MARK_STREAM(pThis, 3, v);
1684 HDA_MARK_STREAM(pThis, 4, v);
1685 HDA_MARK_STREAM(pThis, 5, v);
1686 HDA_MARK_STREAM(pThis, 6, v);
1687 HDA_MARK_STREAM(pThis, 7, v);
1688
1689#undef HDA_IS_STREAM_EVENT
1690#undef HDA_MARK_STREAM
1691
1692 v |= v ? RT_BIT(31) : 0;
1693
1694 *pu32Value = v;
1695 return VINF_SUCCESS;
1696}
1697
1698static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1699{
1700 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1701 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1702 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1703
1704 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
1705
1706 *pu32Value = u32LPIB;
1707 return VINF_SUCCESS;
1708}
1709
1710static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1711{
1712 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1713 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1714 - pThis->u64BaseTS, 24, 1000);
1715 return VINF_SUCCESS;
1716}
1717
1718static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1719{
1720 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1721 {
1722 HDA_REG(pThis, CORBRP) = 0;
1723 }
1724#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1725 else
1726 return hdaRegWriteU8(pThis, iReg, u32Value);
1727#endif
1728 return VINF_SUCCESS;
1729}
1730
1731static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1732{
1733#ifdef IN_RING3
1734 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1735 AssertRC(rc);
1736 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1737 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1738 {
1739 return hdaCORBCmdProcess(pThis);
1740 }
1741 return rc;
1742#else
1743 return VINF_IOM_R3_MMIO_WRITE;
1744#endif
1745}
1746
1747static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1748{
1749 uint32_t v = HDA_REG(pThis, CORBSTS);
1750 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1751 return VINF_SUCCESS;
1752}
1753
1754static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1755{
1756#ifdef IN_RING3
1757 int rc;
1758 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1759 if (RT_FAILURE(rc))
1760 AssertRCReturn(rc, rc);
1761 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1762 return VINF_SUCCESS;
1763 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1764 return VINF_SUCCESS;
1765 rc = hdaCORBCmdProcess(pThis);
1766 return rc;
1767#else
1768 return VINF_IOM_R3_MMIO_WRITE;
1769#endif
1770}
1771
1772static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1773{
1774 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CBL, iReg);
1775 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1776
1777 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32Value));
1778
1779 return hdaRegWriteU32(pThis, iReg, u32Value);
1780}
1781
1782static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1783{
1784 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1785 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1786 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1787 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1788
1789 uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1790
1791 PHDASTREAM pStrmSt;
1792 switch (u8Strm)
1793 {
1794 case 0: /** @todo Use dynamic indices, based on stream assignment. */
1795 {
1796 pStrmSt = &pThis->StrmStLineIn;
1797 break;
1798 }
1799# ifdef VBOX_WITH_HDA_MIC_IN
1800 case 2: /** @todo Use dynamic indices, based on stream assignment. */
1801 {
1802 pStrmSt = &pThis->StrmStMicIn;
1803 break;
1804 }
1805# endif
1806 case 4: /** @todo Use dynamic indices, based on stream assignment. */
1807 {
1808 pStrmSt = &pThis->StrmStOut;
1809 break;
1810 }
1811
1812 default:
1813 {
1814 LogFunc(("Warning: Changing SDCTL on non-attached stream (iReg=0x%x)\n", iReg));
1815 return hdaRegWriteU24(pThis, iReg, u32Value); /* Write 3 bytes. */
1816 }
1817 }
1818
1819 LogFunc(("[SD%RU8]: %R[sdctl]\n", u8Strm, u32Value));
1820
1821 if (fInReset)
1822 {
1823 /* Guest is resetting HDA's stream, we're expecting guest will mark stream as exit. */
1824 Assert(!fReset);
1825 LogFunc(("Guest initiated exit of stream reset\n"));
1826 }
1827 else if (fReset)
1828 {
1829#ifdef IN_RING3
1830 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1831 Assert(!fInRun && !fRun);
1832
1833 LogFunc(("Guest initiated enter to stream reset\n"));
1834 hdaStreamReset(pThis, pStrmSt, u8Strm);
1835#else
1836 return VINF_IOM_R3_MMIO_WRITE;
1837#endif
1838 }
1839 else
1840 {
1841#ifdef IN_RING3
1842 /*
1843 * We enter here to change DMA states only.
1844 */
1845 if (fInRun != fRun)
1846 {
1847 Assert(!fReset && !fInReset);
1848
1849 PHDADRIVER pDrv;
1850 switch (u8Strm)
1851 {
1852 case 0: /** @todo Use a variable here. Later. */
1853 {
1854 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1855 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1856 pDrv->LineIn.pStrmIn, fRun);
1857 break;
1858 }
1859# ifdef VBOX_WITH_HDA_MIC_IN
1860 case 2: /** @todo Use a variable here. Later. */
1861 {
1862 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1863 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1864 pDrv->MicIn.pStrmIn, fRun);
1865 break;
1866 }
1867# endif
1868 case 4: /** @todo Use a variable here. Later. */
1869 {
1870 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1871 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1872 pDrv->Out.pStrmOut, fRun);
1873 break;
1874 }
1875 default:
1876 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1877 break;
1878 }
1879 }
1880
1881 if (pStrmSt)
1882 {
1883 int rc2 = hdaStreamInit(pThis, pStrmSt, u8Strm);
1884 AssertRC(rc2);
1885 }
1886
1887#else /* !IN_RING3 */
1888 return VINF_IOM_R3_MMIO_WRITE;
1889#endif /* IN_RING3 */
1890 }
1891
1892 return hdaRegWriteU24(pThis, iReg, u32Value);
1893}
1894
1895static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1896{
1897 uint32_t v = HDA_REG_IND(pThis, iReg);
1898 v &= ~(u32Value & v);
1899 HDA_REG_IND(pThis, iReg) = v;
1900 hdaProcessInterrupt(pThis);
1901 return VINF_SUCCESS;
1902}
1903
1904static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1905{
1906 /* Only can be modified if RUN bit is 0. */
1907 bool fIsRunning = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1908 if (fIsRunning)
1909 {
1910 AssertMsgFailed(("Cannot write to register when RUN bit is set\n"));
1911 return VINF_SUCCESS;
1912 }
1913
1914 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1915 if (RT_FAILURE(rc))
1916 AssertRCReturn(rc, VINF_SUCCESS);
1917 return rc;
1918}
1919
1920static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1921{
1922 switch (u32Value)
1923 {
1924 case HDA_SDFIFOW_8B:
1925 case HDA_SDFIFOW_16B:
1926 case HDA_SDFIFOW_32B:
1927 return hdaRegWriteU16(pThis, iReg, u32Value);
1928 default:
1929 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1930 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1931 }
1932 return VINF_SUCCESS; /* Never reached. */
1933}
1934
1935/**
1936 * @note This method could be called for changing value on Output Streams
1937 * only (ICH6 datasheet 18.2.39).
1938 */
1939static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1940{
1941 /** @todo Only allow updating FIFOS if RUN bit is 0? */
1942 uint32_t u32FIFOS = 0;
1943
1944 switch (iReg)
1945 {
1946 /* SDInFIFOS is RO, n=0-3. */
1947 case HDA_REG_SD0FIFOS:
1948 case HDA_REG_SD1FIFOS:
1949 case HDA_REG_SD2FIFOS:
1950 case HDA_REG_SD3FIFOS:
1951 {
1952 LogFunc(("Guest tries to change R/O value of FIFO size of input stream, ignoring\n"));
1953 break;
1954 }
1955 case HDA_REG_SD4FIFOS:
1956 case HDA_REG_SD5FIFOS:
1957 case HDA_REG_SD6FIFOS:
1958 case HDA_REG_SD7FIFOS:
1959 {
1960 switch(u32Value)
1961 {
1962 case HDA_SDONFIFO_16B:
1963 case HDA_SDONFIFO_32B:
1964 case HDA_SDONFIFO_64B:
1965 case HDA_SDONFIFO_128B:
1966 case HDA_SDONFIFO_192B:
1967 u32FIFOS = u32Value;
1968 break;
1969
1970 case HDA_SDONFIFO_256B: /** @todo r=andy Investigate this. */
1971 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1972 /* Fall through is intentional. */
1973 default:
1974 u32FIFOS = HDA_SDONFIFO_192B;
1975 break;
1976 }
1977
1978 break;
1979 }
1980 default:
1981 {
1982 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
1983 break;
1984 }
1985 }
1986
1987 if (u32FIFOS)
1988 {
1989 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", 0, hdaSDFIFOSToBytes(u32FIFOS)));
1990 /** @todo Update internal stream state with new FIFOS. */
1991
1992 return hdaRegWriteU16(pThis, iReg, u32FIFOS);
1993 }
1994
1995 return VINF_SUCCESS;
1996}
1997
1998#ifdef IN_RING3
1999static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
2000{
2001 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2002
2003# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2004
2005 int rc = VINF_SUCCESS;
2006
2007 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
2008 uint32_t u32HzMult = 1;
2009 uint32_t u32HzDiv = 1;
2010
2011 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2012 {
2013 case 0: u32HzMult = 1; break;
2014 case 1: u32HzMult = 2; break;
2015 case 2: u32HzMult = 3; break;
2016 case 3: u32HzMult = 4; break;
2017 default:
2018 LogFunc(("Unsupported multiplier %x\n",
2019 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2020 rc = VERR_NOT_SUPPORTED;
2021 break;
2022 }
2023 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2024 {
2025 case 0: u32HzDiv = 1; break;
2026 case 1: u32HzDiv = 2; break;
2027 case 2: u32HzDiv = 3; break;
2028 case 3: u32HzDiv = 4; break;
2029 case 4: u32HzDiv = 5; break;
2030 case 5: u32HzDiv = 6; break;
2031 case 6: u32HzDiv = 7; break;
2032 case 7: u32HzDiv = 8; break;
2033 default:
2034 LogFunc(("Unsupported divisor %x\n",
2035 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2036 rc = VERR_NOT_SUPPORTED;
2037 break;
2038 }
2039
2040 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
2041 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2042 {
2043 case 0:
2044 LogFunc(("Requested 8-bit\n"));
2045 enmFmt = AUD_FMT_S8;
2046 break;
2047 case 1:
2048 LogFunc(("Requested 16-bit\n"));
2049 enmFmt = AUD_FMT_S16;
2050 break;
2051 case 2:
2052 LogFunc(("Requested 20-bit\n"));
2053 break;
2054 case 3:
2055 LogFunc(("Requested 24-bit\n"));
2056 break;
2057 case 4:
2058 LogFunc(("Requested 32-bit\n"));
2059 enmFmt = AUD_FMT_S32;
2060 break;
2061 default:
2062 AssertMsgFailed(("Unsupported bits shift %x\n",
2063 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2064 rc = VERR_NOT_SUPPORTED;
2065 break;
2066 }
2067
2068 if (RT_SUCCESS(rc))
2069 {
2070 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2071 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
2072 pCfg->enmFormat = enmFmt;
2073 pCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2074 }
2075
2076# undef EXTRACT_VALUE
2077
2078 LogFlowFuncLeaveRC(rc);
2079 return rc;
2080}
2081#endif
2082
2083static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2084{
2085#ifdef IN_RING3
2086# ifdef VBOX_WITH_HDA_CODEC_EMU
2087 /* No reason to reopen voice with same settings. */
2088 if (u32Value == HDA_REG_IND(pThis, iReg))
2089 return VINF_SUCCESS;
2090
2091 PDMAUDIOSTREAMCFG as;
2092 int rc = hdaSdFmtToAudSettings(u32Value, &as);
2093 if (RT_FAILURE(rc))
2094 return rc;
2095
2096 PHDADRIVER pDrv;
2097 switch (iReg)
2098 {
2099 case HDA_REG_SD0FMT:
2100 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2101 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &as);
2102 break;
2103# ifdef VBOX_WITH_HDA_MIC_IN
2104 case HDA_REG_SD2FMT:
2105 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2106 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &as);
2107 break;
2108# endif
2109 default:
2110 LogFunc(("Warning: Attempt to change format on register %d\n", iReg));
2111 break;
2112 }
2113
2114 /** @todo r=andy rc gets lost; needs fixing. */
2115 return hdaRegWriteU16(pThis, iReg, u32Value);
2116# else /* !VBOX_WITH_HDA_CODEC_EMU */
2117 return hdaRegWriteU16(pThis, iReg, u32Value);
2118# endif
2119#else /* !IN_RING3 */
2120 return VINF_IOM_R3_MMIO_WRITE;
2121#endif
2122}
2123
2124static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2125{
2126 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2127 if (RT_FAILURE(rc))
2128 AssertRCReturn(rc, VINF_SUCCESS);
2129 return rc;
2130}
2131
2132static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2133{
2134 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2135 if (RT_FAILURE(rc))
2136 AssertRCReturn(rc, VINF_SUCCESS);
2137 return rc;
2138}
2139
2140static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2141{
2142 int rc = VINF_SUCCESS;
2143 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2144 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2145 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2146 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2147
2148 rc = hdaRegReadU32(pThis, iReg, pu32Value);
2149 return rc;
2150}
2151
2152static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2153{
2154 int rc = VINF_SUCCESS;
2155
2156 /*
2157 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2158 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2159 */
2160 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
2161 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
2162 {
2163#ifdef IN_RING3
2164 PFNHDACODECVERBPROCESSOR pfn = NULL;
2165 uint64_t resp;
2166 uint32_t cmd = HDA_REG(pThis, IC);
2167 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2168 {
2169 /*
2170 * 3.4.3 defines behavior of immediate Command status register.
2171 */
2172 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
2173 return rc;
2174 }
2175 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2176 LogFunc(("IC:%x\n", cmd));
2177
2178 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
2179 HDA_CODEC_CMD(cmd, 0 /* LUN */),
2180 &pfn);
2181 if (RT_FAILURE(rc))
2182 AssertRCReturn(rc, rc);
2183 rc = pfn(pThis->pCodec,
2184 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
2185 if (RT_FAILURE(rc))
2186 AssertRCReturn(rc, rc);
2187
2188 HDA_REG(pThis, IR) = (uint32_t)resp;
2189 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
2190 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
2191 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
2192#else /* !IN_RING3 */
2193 rc = VINF_IOM_R3_MMIO_WRITE;
2194#endif
2195 return rc;
2196 }
2197 /*
2198 * Once the guest read the response, it should clean the IRV bit of the IRS register.
2199 */
2200 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
2201 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
2202 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
2203 return rc;
2204}
2205
2206static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2207{
2208 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
2209 {
2210 HDA_REG(pThis, RIRBWP) = 0;
2211 }
2212 /* The remaining bits are O, see 6.2.22 */
2213 return VINF_SUCCESS;
2214}
2215
2216static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2217{
2218 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2219 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2220 if (RT_FAILURE(rc))
2221 AssertRCReturn(rc, rc);
2222
2223 switch(iReg)
2224 {
2225 case HDA_REG_CORBLBASE:
2226 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2227 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
2228 break;
2229 case HDA_REG_CORBUBASE:
2230 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2231 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2232 break;
2233 case HDA_REG_RIRBLBASE:
2234 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2235 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
2236 break;
2237 case HDA_REG_RIRBUBASE:
2238 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2239 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2240 break;
2241 case HDA_REG_DPLBASE:
2242 {
2243 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
2244 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
2245
2246 /* Also make sure to handle the DMA position enable bit. */
2247 bool fEnabled = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2248 if (pThis->fDMAPosition != fEnabled)
2249 {
2250 LogRel(("HDA: %s DMA position buffer\n", fEnabled ? "Enabled" : "Disabled"));
2251 pThis->fDMAPosition = fEnabled;
2252
2253 if (pThis->fDMAPosition)
2254 {
2255 /* Immediately tell the position. */
2256 hdaStreamUpdateLPIB(pThis, &pThis->StrmStLineIn, HDA_STREAM_REG(pThis, LPIB, pThis->StrmStLineIn.u8Strm));
2257 hdaStreamUpdateLPIB(pThis, &pThis->StrmStMicIn, HDA_STREAM_REG(pThis, LPIB, pThis->StrmStMicIn.u8Strm));
2258 hdaStreamUpdateLPIB(pThis, &pThis->StrmStOut, HDA_STREAM_REG(pThis, LPIB, pThis->StrmStOut.u8Strm));
2259 }
2260 }
2261 break;
2262 }
2263 case HDA_REG_DPUBASE:
2264 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
2265 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2266 break;
2267 default:
2268 AssertMsgFailed(("Invalid index\n"));
2269 break;
2270 }
2271
2272 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2273 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2274 return rc;
2275}
2276
2277static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2278{
2279 uint8_t v = HDA_REG(pThis, RIRBSTS);
2280 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2281
2282 return hdaProcessInterrupt(pThis);
2283}
2284
2285#ifdef IN_RING3
2286#ifdef LOG_ENABLED
2287static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE)
2288{
2289 uint32_t cbBDLE = 0;
2290
2291 for (uint16_t i = 0; i < cBDLE; i++)
2292 {
2293 uint8_t bdle[16]; /** @todo Use a define. */
2294 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * 16, bdle, 16); /** @todo Use a define. */
2295
2296 uint64_t addr = *(uint64_t *)bdle;
2297 uint32_t len = *(uint32_t *)&bdle[8];
2298 uint32_t ioc = *(uint32_t *)&bdle[12];
2299
2300 LogFlowFunc(("#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
2301 i, addr, len, RT_BOOL(ioc & 0x1)));
2302
2303 cbBDLE += len;
2304 }
2305
2306 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
2307
2308 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
2309 return;
2310
2311 for (int i = 0; i < 8; i++) /** @todo Use a define. */
2312 {
2313 uint32_t uDMACnt;
2314 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i * 8, /** @todo Use a define. */
2315 &uDMACnt, sizeof(&uDMACnt));
2316
2317 LogFlowFunc(("%s #%02d STREAM(0x%x)\n",
2318 i == HDA_SDCTL_NUM(pThis, 4) || i == HDA_SDCTL_NUM(pThis, 0) ? "*" : " ", i , uDMACnt));
2319 }
2320}
2321#endif
2322
2323/**
2324 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
2325 *
2326 * @param pThis Pointer to HDA state.
2327 * @param pBDLE Where to store the fetched result.
2328 * @param u64BaseDMA Address base of DMA engine to use.
2329 * @param u16Entry BDLE entry to fetch.
2330 */
2331static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
2332{
2333 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2334 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
2335 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
2336 /** @todo Compare u16Entry with LVI. */
2337
2338 uint8_t uBundleEntry[16]; /** @todo Define a BDLE length. */
2339 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * 16, /** @todo Define a BDLE length. */
2340 uBundleEntry, RT_ELEMENTS(uBundleEntry));
2341 if (RT_FAILURE(rc))
2342 return rc;
2343
2344 pBDLE->State.u32BDLIndex = u16Entry;
2345 pBDLE->u64BufAdr = *(uint64_t *) uBundleEntry;
2346 pBDLE->u32BufSize = *(uint32_t *)&uBundleEntry[8];
2347 if (pBDLE->u32BufSize < sizeof(uint16_t)) /* Must be at least one word. */
2348 return VERR_INVALID_STATE;
2349
2350 pBDLE->fIntOnCompletion = (*(uint32_t *)&uBundleEntry[12]) & 0x1;
2351
2352 return VINF_SUCCESS;
2353}
2354
2355static void hdaBDLEReset(PHDABDLE pBDLE)
2356{
2357 AssertPtrReturnVoid(pBDLE);
2358
2359 pBDLE->State.u32BufOff = 0;
2360 pBDLE->State.cbBelowFIFOW = 0;
2361}
2362
2363/**
2364 * Returns the number of outstanding stream data bytes which need to be processed
2365 * by the DMA engine assigned to this stream.
2366 *
2367 * @return Number of bytes for the DMA engine to process.
2368 */
2369DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStrmSt)
2370{
2371 AssertPtrReturn(pThis, 0);
2372 AssertPtrReturn(pStrmSt, 0);
2373
2374 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2375
2376 uint32_t cbFree = pStrmSt->u32CBL - HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2377 if (cbFree)
2378 {
2379 /* Limit to the available free space of the current BDLE. */
2380 cbFree = RT_MIN(cbFree, pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2381
2382 /* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
2383 cbFree = RT_MIN(cbFree, pStrmSt->u16FIFOS);
2384
2385 if (pBDLE->State.cbBelowFIFOW)
2386 {
2387 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
2388 * No need to read data from DMA then. */
2389 if (cbFree > pBDLE->State.cbBelowFIFOW)
2390 {
2391 /* Subtract the amount of bytes that still would fit in the stream's FIFO
2392 * and therefore do not need to be processed by DMA. */
2393 cbFree -= pBDLE->State.cbBelowFIFOW;
2394 }
2395 }
2396
2397 Log(("HDADEBUG: cb2Copy=%RU32, CVI(len:%RU32, pos:%RU32), CBLL=%RU32, FIFOS=%RU32, Avail=%RU32\n",
2398 cbFree, pBDLE->u32BufSize, pBDLE->State.u32BufOff, pStrmSt->u32CBL - HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), pStrmSt->u16FIFOS, 0));
2399 }
2400
2401 LogFlowFunc(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, cbFree=%RU32, %R[bdle]\n", pStrmSt->u8Strm,
2402 pStrmSt->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), cbFree, pBDLE));
2403 return cbFree;
2404}
2405
2406DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
2407{
2408 AssertPtrReturnVoid(pBDLE);
2409
2410 if (!cbData || !cbProcessed)
2411 return;
2412
2413 /* Fewer than cbBelowFIFOW bytes were copied.
2414 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2415 * where it might happen. */
2416 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
2417 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
2418 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
2419
2420#if 0
2421 if ( pBDLE->State.cbBelowFIFOW
2422 && pBDLE->State.cbBelowFIFOW <= cbWritten)
2423 {
2424 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
2425 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->u32BufSize));
2426 }
2427#endif
2428
2429 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
2430 Assert(pBDLE->State.cbBelowFIFOW == 0);
2431
2432 /* We always increment the position of DMA buffer counter because we're always reading
2433 * into an intermediate buffer. */
2434 pBDLE->State.u32BufOff += cbData;
2435 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2436
2437 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
2438}
2439
2440DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
2441{
2442 AssertPtrReturn(pThis, false);
2443 AssertPtrReturn(pStrmSt, false);
2444
2445 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2446 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2447
2448 /* Did we reach the CBL (Cyclic Buffer List) limit? */
2449 bool fCBLLimitReached = u32LPIB >= pStrmSt->u32CBL;
2450
2451 /* Do we need to use the next BDLE entry? Either because we reached
2452 * the CBL limit or our internal DMA buffer is full. */
2453 bool fNeedsNextBDLE = ( fCBLLimitReached
2454 || pBDLE->State.u32BufOff >= pBDLE->u32BufSize);
2455
2456 Assert(u32LPIB <= pStrmSt->u32CBL);
2457 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2458
2459 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
2460 pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
2461
2462 if (fCBLLimitReached)
2463 {
2464 /* Reset LPIB register. */
2465 u32LPIB -= RT_MIN(u32LPIB, pStrmSt->u32CBL);
2466 hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2467 }
2468
2469 if (fNeedsNextBDLE)
2470 {
2471 /* Reset current BDLE. */
2472 hdaBDLEReset(pBDLE);
2473 }
2474
2475 return fNeedsNextBDLE;
2476}
2477
2478DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbInc)
2479{
2480 AssertPtrReturnVoid(pThis);
2481 AssertPtrReturnVoid(pStrmSt);
2482
2483 LogFlowFunc(("[SD%RU8]: cbInc=%RU32\n", pStrmSt->u8Strm, cbInc));
2484
2485 Assert(cbInc <= pStrmSt->u16FIFOS);
2486
2487 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2488
2489 /*
2490 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
2491 * doesn't fetch anything via DMA, so just update LPIB.
2492 * (ICH6 datasheet 18.2.38).
2493 */
2494 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
2495 {
2496 const uint32_t u32LPIB = RT_MIN(HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2497 pStrmSt->u32CBL);
2498
2499 LogFlowFunc(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
2500 pStrmSt->u8Strm,
2501 HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2502 pStrmSt->u32CBL));
2503
2504 hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2505 }
2506}
2507
2508static bool hdaStreamTransferIsComplete(PHDASTATE pThis, PHDASTREAM pStrmSt)
2509{
2510 AssertPtrReturn(pThis, true);
2511 AssertPtrReturn(pStrmSt, true);
2512
2513 bool fIsComplete = false;
2514
2515 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2516 const uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2517
2518 if ( pBDLE->State.u32BufOff >= pBDLE->u32BufSize
2519 || u32LPIB >= pStrmSt->u32CBL)
2520 {
2521 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2522 Assert(u32LPIB <= pStrmSt->u32CBL);
2523
2524 if (/* IOC (Interrupt On Completion) bit set? */
2525 pBDLE->fIntOnCompletion
2526 /* All data put into the DMA FIFO? */
2527 && pBDLE->State.cbBelowFIFOW == 0
2528 )
2529 {
2530 /**
2531 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
2532 * last byte of data for the current descriptor has been fetched
2533 * from memory and put into the DMA FIFO.
2534 *
2535 ** @todo More carefully investigate BCIS flag.
2536 *
2537 * Speech synthesis works fine on Mac Guest if this bit isn't set
2538 * but in general sound quality gets worse.
2539 */
2540 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2541
2542 /*
2543 * If the ICE (IOCE, "Interrupt On Completion Enable") bit of the SDCTL register is set
2544 * we need to generate an interrupt.
2545 */
2546 if (HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2547 hdaProcessInterrupt(pThis);
2548 }
2549
2550 fIsComplete = true;
2551 }
2552
2553 LogFlowFunc(("[SD%RU8]: u32LPIB=%RU32, CBL=%RU32, %R[bdle] => %s\n",
2554 pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, pBDLE, fIsComplete ? "COMPLETE" : "INCOMPLETE"));
2555
2556 return fIsComplete;
2557}
2558
2559/**
2560 * hdaReadAudio - copies samples from audio backend to DMA.
2561 * Note: This function writes to the DMA buffer immediately,
2562 * but "reports bytes" when all conditions are met (FIFOW).
2563 */
2564static int hdaReadAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, PAUDMIXSINK pSink, uint32_t *pcbRead)
2565{
2566 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2567 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2568 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
2569 /* pcbRead is optional. */
2570
2571 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2572
2573 int rc;
2574 uint32_t cbRead = 0;
2575 uint32_t cbBuf = hdaStreamGetTransferSize(pThis, pStrmSt);
2576
2577 LogFlowFunc(("cbBuf=%RU32, %R[bdle]\n", cbBuf, pBDLE));
2578
2579 if (!cbBuf)
2580 {
2581 /* Nothing to write, bail out. */
2582 rc = VERR_NO_DATA;
2583 }
2584 else
2585 {
2586 uint32_t cbReadFromSink = 0;
2587 rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pBDLE->State.au8FIFO, cbBuf, &cbReadFromSink);
2588 if (RT_SUCCESS(rc))
2589 {
2590 Assert(cbReadFromSink);
2591 Assert(cbReadFromSink == cbBuf);
2592 Assert(cbReadFromSink <= pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2593
2594 /*
2595 * Write to the BDLE's DMA buffer.
2596 */
2597 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2598 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2599 pBDLE->State.au8FIFO, cbReadFromSink);
2600 AssertRC(rc);
2601
2602 if (pBDLE->State.cbBelowFIFOW + cbReadFromSink > hdaStreamGetFIFOW(pThis, pStrmSt))
2603 {
2604 pBDLE->State.u32BufOff += cbReadFromSink;
2605 pBDLE->State.cbBelowFIFOW = 0;
2606 //hdaBackendReadTransferReported(pBDLE, cbDMAData, cbRead, &cbRead, pcbAvail);
2607 }
2608 else
2609 {
2610 pBDLE->State.u32BufOff += cbReadFromSink;
2611 pBDLE->State.cbBelowFIFOW += cbReadFromSink;
2612 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2613 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbRead, pcbAvail);
2614
2615 rc = VERR_NO_DATA;
2616 }
2617 }
2618 }
2619
2620 //Assert(cbRead <= (SDFIFOS(pThis, pStrmSt->u8Strm) + 1));
2621
2622 LogFunc(("BDLE(off:%RU32, size:%RU32), cbTransferred=%RU32, rc=%Rrc\n",
2623 pBDLE->State.u32BufOff, pBDLE->u32BufSize, cbRead, rc));
2624
2625 if (RT_SUCCESS(rc))
2626 {
2627 if (pcbRead)
2628 *pcbRead = cbRead;
2629 }
2630
2631 return rc;
2632}
2633
2634static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t *pcbWritten)
2635{
2636 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2637 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2638 AssertPtrReturn(pcbWritten, VERR_INVALID_POINTER);
2639 /* pcbWritten is optional. */
2640
2641 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2642 int rc;
2643
2644 uint32_t cbWritten = 0;
2645 uint32_t cbData = hdaStreamGetTransferSize(pThis, pStrmSt);
2646
2647 LogFlowFunc(("cbData=%RU32, %R[bdle]\n", cbData, pBDLE));
2648
2649 /*
2650 * Copy from DMA to the corresponding stream buffer (if there are any bytes from the
2651 * previous unreported transfer we write at offset 'pBDLE->State.cbUnderFifoW').
2652 */
2653 if (!cbData)
2654 {
2655 rc = VINF_EOF;
2656 }
2657 else
2658 {
2659 /*
2660 * Read from the current BDLE's DMA buffer.
2661 */
2662 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2663 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2664 pBDLE->State.au8FIFO + pBDLE->State.cbBelowFIFOW, cbData);
2665 AssertRC(rc);
2666
2667#ifdef VBOX_WITH_STATISTICS
2668 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbData);
2669#endif
2670 /*
2671 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2672 */
2673 uint32_t cbToWrite = cbData + pBDLE->State.cbBelowFIFOW;
2674 if (cbToWrite >= hdaStreamGetFIFOW(pThis, pStrmSt))
2675 {
2676 uint32_t cbWrittenToStream;
2677 int rc2;
2678
2679 PHDADRIVER pDrv;
2680 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2681 {
2682 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2683 {
2684 rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2685 pBDLE->State.au8FIFO, cbToWrite, &cbWrittenToStream);
2686 if (RT_SUCCESS(rc2))
2687 {
2688 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2689 LogFlowFunc(("\tLUN#%RU8: Warning: Only written %RU32 / %RU32 bytes, expect lags\n",
2690 pDrv->uLUN, cbWrittenToStream, cbToWrite));
2691 }
2692 }
2693 else /* Stream disabled, not fatal. */
2694 {
2695 cbWrittenToStream = 0;
2696 rc2 = VERR_NOT_AVAILABLE;
2697 /* Keep going. */
2698 }
2699
2700 LogFlowFunc(("\tLUN#%RU8: cbToWrite=%RU32, cbWrittenToStream=%RU32, rc=%Rrc\n",
2701 pDrv->uLUN, cbToWrite, cbWrittenToStream, rc2));
2702 }
2703
2704 /* Always report all data as being written;
2705 * backends who were not able to catch up have to deal with it themselves. */
2706 cbWritten = cbToWrite;
2707
2708 hdaBDLEUpdate(pBDLE, cbData, cbWritten);
2709 }
2710 else
2711 {
2712 pBDLE->State.u32BufOff += cbWritten;
2713 pBDLE->State.cbBelowFIFOW += cbWritten;
2714 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2715
2716 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2717 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbAvail, NULL);
2718 rc = VINF_EOF;
2719 }
2720 }
2721
2722 Assert(cbWritten <= pStrmSt->u16FIFOS);
2723
2724 if (RT_SUCCESS(rc))
2725 {
2726 if (pcbWritten)
2727 *pcbWritten = cbWritten;
2728 }
2729
2730 LogFunc(("Returning cbWritten=%RU32, rc=%Rrc\n", cbWritten, rc));
2731 return rc;
2732}
2733
2734/**
2735 * @interface_method_impl{HDACODEC,pfnReset}
2736 */
2737static DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2738{
2739 PHDASTATE pThis = pCodec->pHDAState;
2740 NOREF(pThis);
2741 return VINF_SUCCESS;
2742}
2743
2744
2745static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2746{
2747 NOREF(pThis);
2748 NOREF(enmRecSource);
2749 LogFlowFuncEnter();
2750}
2751
2752static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2753{
2754 NOREF(pThis);
2755 LogFlowFuncEnter();
2756}
2757
2758static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2759 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2760 PPDMAUDIOSTREAMCFG pCfg)
2761{
2762 PAUDMIXSINK pSink;
2763
2764 switch (enmRecSource)
2765 {
2766# ifdef VBOX_WITH_HDA_MIC_IN
2767 case PDMAUDIORECSOURCE_MIC:
2768 pSink = pThis->pSinkMicIn;
2769 break;
2770# endif
2771 case PDMAUDIORECSOURCE_LINE_IN:
2772 pSink = pThis->pSinkLineIn;
2773 break;
2774 default:
2775 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2776 return VERR_NOT_SUPPORTED;
2777 }
2778
2779 int rc = VINF_SUCCESS;
2780 char *pszDesc;
2781
2782 PHDADRIVER pDrv;
2783 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2784 {
2785 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2786 {
2787 rc = VERR_NO_MEMORY;
2788 break;
2789 }
2790
2791 rc = pDrv->pConnector->pfnCreateIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2792 LogFlowFunc(("LUN#%RU8: Created input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2793 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2794 {
2795 AudioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2796 rc = AudioMixerAddStreamIn(pSink,
2797 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2798 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2799 }
2800
2801 RTStrFree(pszDesc);
2802 }
2803
2804 LogFlowFuncLeaveRC(rc);
2805 return rc;
2806}
2807
2808static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2809 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2810{
2811 int rc = VINF_SUCCESS;
2812 char *pszDesc;
2813
2814 PHDADRIVER pDrv;
2815 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2816 {
2817 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2818 {
2819 rc = VERR_NO_MEMORY;
2820 break;
2821 }
2822
2823 rc = pDrv->pConnector->pfnCreateOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
2824 LogFlowFunc(("LUN#%RU8: Created output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2825 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2826 {
2827 AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
2828 rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
2829 pDrv->pConnector, pDrv->Out.pStrmOut,
2830 0 /* uFlags */, &pDrv->Out.phStrmOut);
2831 }
2832
2833 RTStrFree(pszDesc);
2834 }
2835
2836 LogFlowFuncLeaveRC(rc);
2837 return rc;
2838}
2839
2840static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis, ENMSOUNDSOURCE enmSource,
2841 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2842{
2843 int rc = VINF_SUCCESS;
2844 PDMAUDIOVOLUME vol = { fMute, uVolLeft, uVolRight };
2845 PAUDMIXSINK pSink;
2846
2847 /* Convert the audio source to corresponding sink. */
2848 switch (enmSource)
2849 {
2850 case PO_INDEX:
2851 pSink = pThis->pSinkOutput;
2852 break;
2853 case PI_INDEX:
2854 pSink = pThis->pSinkLineIn;
2855 break;
2856 case MC_INDEX:
2857 pSink = pThis->pSinkMicIn;
2858 break;
2859 default:
2860 AssertFailedReturn(VERR_INVALID_PARAMETER);
2861 break;
2862 }
2863
2864 /* Set the volume. Codec already converted it to the correct range. */
2865 AudioMixerSetSinkVolume(pSink, &vol);
2866
2867 LogFlowFuncLeaveRC(rc);
2868 return rc;
2869}
2870
2871#ifndef VBOX_WITH_AUDIO_CALLBACKS
2872
2873static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2874{
2875 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2876 AssertPtr(pThis);
2877
2878 STAM_PROFILE_START(&pThis->StatTimer, a);
2879
2880 int rc = VINF_SUCCESS;
2881
2882 uint32_t cbInMax = 0;
2883 uint32_t cbOutMin = UINT32_MAX;
2884
2885 PHDADRIVER pDrv;
2886
2887 uint32_t cbIn, cbOut, cSamplesLive;
2888 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2889 {
2890 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2891 &cbIn, &cbOut, &cSamplesLive);
2892 if (RT_SUCCESS(rc))
2893 {
2894#ifdef DEBUG_TIMER
2895 LogFlowFunc(("\tLUN#%RU8: [1] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2896#endif
2897 if (cSamplesLive)
2898 {
2899 uint32_t cSamplesPlayed;
2900 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2901 if (RT_SUCCESS(rc2))
2902 LogFlowFunc(("LUN#%RU8: cSamplesLive=%RU32, cSamplesPlayed=%RU32\n",
2903 pDrv->uLUN, cSamplesLive, cSamplesPlayed));
2904
2905 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2906 &cbIn, &cbOut, &cSamplesLive);
2907#ifdef DEBUG_TIMER
2908 if (RT_SUCCESS(rc))
2909 LogFlowFunc(("\tLUN#%RU8: [2] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2910#endif
2911 }
2912
2913 cbInMax = RT_MAX(cbInMax, cbIn);
2914 cbOutMin = RT_MIN(cbOutMin, cbOut);
2915 }
2916 }
2917
2918#ifdef DEBUG_TIMER
2919 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
2920#endif
2921
2922 if (cbOutMin == UINT32_MAX)
2923 cbOutMin = 0;
2924
2925 /*
2926 * Playback.
2927 */
2928 if (cbOutMin)
2929 {
2930 Assert(cbOutMin != UINT32_MAX);
2931 hdaTransfer(pThis, PO_INDEX, NULL /* pcbProcessed */); /** @todo Add rc! */
2932 }
2933
2934 /*
2935 * Recording.
2936 */
2937 if (cbInMax)
2938 hdaTransfer(pThis, PI_INDEX, NULL /* pcbProcessed */); /** @todo Add rc! */
2939
2940 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
2941
2942 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2943}
2944
2945#else /* VBOX_WITH_AUDIO_CALLBACKS */
2946
2947static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
2948{
2949 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
2950 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
2951 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
2952 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
2953 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
2954
2955 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
2956 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
2957
2958 PPDMAUDIOCALLBACKDATAIN pData = (PPDMAUDIOCALLBACKDATAIN)pvUser;
2959 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAIN), VERR_INVALID_PARAMETER);
2960
2961 return hdaTransfer(pCtx->pThis, PI_INDEX, &pData->cbOutRead);
2962}
2963
2964static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
2965{
2966 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
2967 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
2968 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
2969 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
2970 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
2971
2972 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
2973 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
2974
2975 PPDMAUDIOCALLBACKDATAOUT pData = (PPDMAUDIOCALLBACKDATAOUT)pvUser;
2976 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAOUT), VERR_INVALID_PARAMETER);
2977
2978 PHDASTATE pThis = pCtx->pThis;
2979
2980 int rc = hdaTransfer(pCtx->pThis, PO_INDEX, &pData->cbOutWritten);
2981 if ( RT_SUCCESS(rc)
2982 && pData->cbOutWritten)
2983 {
2984 PHDADRIVER pDrv;
2985 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2986 {
2987 uint32_t cSamplesPlayed;
2988 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2989 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
2990 }
2991 }
2992}
2993#endif /* VBOX_WITH_AUDIO_CALLBACKS */
2994
2995static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t *pcbProcessed)
2996{
2997 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2998 /* pcbProcessed is optional. */
2999
3000 LogFlowFunc(("enmSrc=%RU32\n", enmSrc));
3001
3002 PHDASTREAM pStrmSt;
3003 switch (enmSrc)
3004 {
3005 case PI_INDEX:
3006 {
3007 pStrmSt = &pThis->StrmStLineIn;
3008 break;
3009 }
3010
3011#ifdef VBOX_WITH_HDA_MIC_IN
3012 case MC_INDEX:
3013 {
3014 pStrmSt = &pThis->StrmStMicIn;
3015 break;
3016 }
3017#endif
3018 case PO_INDEX:
3019 {
3020 pStrmSt = &pThis->StrmStOut;
3021 break;
3022 }
3023
3024 default:
3025 {
3026 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
3027 return VERR_NOT_SUPPORTED;
3028 }
3029 }
3030
3031 if (pStrmSt->State.cBDLE == 0) /* No buffers available? */
3032 {
3033 LogFlowFunc(("[SD%RU8] No buffers available\n", pStrmSt->u8Strm));
3034
3035 if (pcbProcessed)
3036 *pcbProcessed = 0;
3037 return VINF_SUCCESS;
3038 }
3039 AssertPtr(pStrmSt->State.paBDLE);
3040
3041 /* Is this stream running? */
3042 const bool fIsRunning = RT_BOOL(HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3043 if (!fIsRunning)
3044 {
3045 LogFlowFunc(("[SD%RU8]: Stream not running\n", pStrmSt->u8Strm));
3046
3047 if (pcbProcessed)
3048 *pcbProcessed = 0;
3049 return VINF_SUCCESS;
3050 }
3051
3052 Assert(pStrmSt->u8Strm <= 7); /** @todo Use a define for MAX_STRAEMS! */
3053 Assert(pStrmSt->u64BaseDMA);
3054 Assert(pStrmSt->u32CBL);
3055
3056 int rc;
3057 uint32_t cbProcessedTotal = 0;
3058 bool fIsComplete = false;
3059
3060 do
3061 {
3062 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
3063 if (hdaStreamNeedsNextBDLE(pThis, pStrmSt))
3064 hdaStreamGetNextBDLE(pThis, pStrmSt);
3065
3066 /* Set the FIFORDY bit on the stream while doing the transfer. */
3067 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3068
3069 uint32_t cbProcessed;
3070 switch (enmSrc)
3071 {
3072 case PI_INDEX:
3073 rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkLineIn, &cbProcessed);
3074 break;
3075 case PO_INDEX:
3076 rc = hdaWriteAudio(pThis, pStrmSt, &cbProcessed);
3077 break;
3078#ifdef VBOX_WITH_HDA_MIC_IN
3079 case MC_INDEX:
3080 rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkMicIn, &cbProcessed);
3081 break;
3082#endif
3083 default:
3084 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
3085 rc = VERR_NOT_SUPPORTED;
3086 break;
3087 }
3088
3089 /* Remove the FIFORDY bit again. */
3090 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3091
3092 if (RT_FAILURE(rc))
3093 break;
3094
3095 hdaStreamTransferUpdate(pThis, pStrmSt, cbProcessed);
3096
3097 cbProcessedTotal += cbProcessed;
3098
3099 LogFlowFunc(("cbProcessed=%RU32, cbProcessedTotal=%RU32, rc=%Rrc\n", cbProcessed, cbProcessedTotal, rc));
3100
3101 if (rc == VINF_EOF)
3102 fIsComplete = true;
3103
3104 if (!fIsComplete)
3105 fIsComplete = hdaStreamTransferIsComplete(pThis, pStrmSt);
3106
3107 } while (!fIsComplete);
3108
3109 if (RT_SUCCESS(rc))
3110 {
3111 if (pcbProcessed)
3112 *pcbProcessed = cbProcessedTotal;
3113 }
3114
3115 LogFlowFuncLeaveRC(rc);
3116 return rc;
3117}
3118#endif /* IN_RING3 */
3119
3120/* MMIO callbacks */
3121
3122/**
3123 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3124 *
3125 * @note During implementation, we discovered so-called "forgotten" or "hole"
3126 * registers whose description is not listed in the RPM, datasheet, or
3127 * spec.
3128 */
3129PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3130{
3131 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3132 int rc;
3133
3134 /*
3135 * Look up and log.
3136 */
3137 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3138 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
3139#ifdef LOG_ENABLED
3140 unsigned const cbLog = cb;
3141 uint32_t offRegLog = offReg;
3142#endif
3143
3144 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
3145 Assert(cb == 4); Assert((offReg & 3) == 0);
3146
3147 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3148 LogFunc(("\tAccess to registers except GCTL is blocked while reset\n"));
3149
3150 if (idxRegDsc == -1)
3151 LogRel(("HDA: Invalid read access @0x%x (bytes=%d)\n", offReg, cb));
3152
3153 if (idxRegDsc != -1)
3154 {
3155 /* ASSUMES gapless DWORD at end of map. */
3156 if (g_aHdaRegMap[idxRegDsc].size == 4)
3157 {
3158 /*
3159 * Straight forward DWORD access.
3160 */
3161 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3162 LogFunc(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
3163 }
3164 else
3165 {
3166 /*
3167 * Multi register read (unless there are trailing gaps).
3168 * ASSUMES that only DWORD reads have sideeffects.
3169 */
3170 uint32_t u32Value = 0;
3171 unsigned cbLeft = 4;
3172 do
3173 {
3174 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3175 uint32_t u32Tmp = 0;
3176
3177 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3178 LogFunc(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3179 if (rc != VINF_SUCCESS)
3180 break;
3181 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3182
3183 cbLeft -= cbReg;
3184 offReg += cbReg;
3185 idxRegDsc++;
3186 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3187
3188 if (rc == VINF_SUCCESS)
3189 *(uint32_t *)pv = u32Value;
3190 else
3191 Assert(!IOM_SUCCESS(rc));
3192 }
3193 }
3194 else
3195 {
3196 rc = VINF_IOM_MMIO_UNUSED_FF;
3197 LogFunc(("\tHole at %x is accessed for read\n", offReg));
3198 }
3199
3200 /*
3201 * Log the outcome.
3202 */
3203#ifdef LOG_ENABLED
3204 if (cbLog == 4)
3205 LogFunc(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
3206 else if (cbLog == 2)
3207 LogFunc(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
3208 else if (cbLog == 1)
3209 LogFunc(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
3210#endif
3211 return rc;
3212}
3213
3214
3215DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3216{
3217 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3218 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
3219
3220 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3221#ifdef LOG_ENABLED
3222 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
3223#endif
3224 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3225 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3226 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
3227 return rc;
3228}
3229
3230
3231/**
3232 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3233 */
3234PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
3235{
3236 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3237 int rc;
3238
3239 /*
3240 * The behavior of accesses that aren't aligned on natural boundraries is
3241 * undefined. Just reject them outright.
3242 */
3243 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3244 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
3245 if (GCPhysAddr & (cb - 1))
3246 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3247
3248 /*
3249 * Look up and log the access.
3250 */
3251 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3252 int idxRegDsc = hdaRegLookup(pThis, offReg);
3253 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3254 uint64_t u64Value;
3255 if (cb == 4) u64Value = *(uint32_t const *)pv;
3256 else if (cb == 2) u64Value = *(uint16_t const *)pv;
3257 else if (cb == 1) u64Value = *(uint8_t const *)pv;
3258 else if (cb == 8) u64Value = *(uint64_t const *)pv;
3259 else
3260 {
3261 u64Value = 0; /* shut up gcc. */
3262 AssertReleaseMsgFailed(("%u\n", cb));
3263 }
3264
3265#ifdef LOG_ENABLED
3266 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3267 if (idxRegDsc == -1)
3268 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
3269 else if (cb == 4)
3270 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3271 else if (cb == 2)
3272 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3273 else if (cb == 1)
3274 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3275
3276 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3277 LogFunc(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3278#endif
3279
3280 /*
3281 * Try for a direct hit first.
3282 */
3283 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3284 {
3285 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3286#ifdef LOG_ENABLED
3287 LogFunc(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3288#endif
3289 }
3290 /*
3291 * Partial or multiple register access, loop thru the requested memory.
3292 */
3293 else
3294 {
3295 /*
3296 * If it's an access beyond the start of the register, shift the input
3297 * value and fill in missing bits. Natural alignment rules means we
3298 * will only see 1 or 2 byte accesses of this kind, so no risk of
3299 * shifting out input values.
3300 */
3301 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
3302 {
3303 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3304 offReg -= cbBefore;
3305 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3306 u64Value <<= cbBefore * 8;
3307 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3308 LogFunc(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3309 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3310 }
3311
3312 /* Loop thru the write area, it may cover multiple registers. */
3313 rc = VINF_SUCCESS;
3314 for (;;)
3315 {
3316 uint32_t cbReg;
3317 if (idxRegDsc != -1)
3318 {
3319 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3320 cbReg = g_aHdaRegMap[idxRegDsc].size;
3321 if (cb < cbReg)
3322 {
3323 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3324 LogFunc(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3325 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3326 }
3327 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
3328 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3329 LogFunc(("\t%#x -> %#x\n", u32LogOldVal, pThis->au32Regs[idxRegMem]));
3330 }
3331 else
3332 {
3333 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3334 cbReg = 1;
3335 }
3336 if (rc != VINF_SUCCESS)
3337 break;
3338 if (cbReg >= cb)
3339 break;
3340
3341 /* Advance. */
3342 offReg += cbReg;
3343 cb -= cbReg;
3344 u64Value >>= cbReg * 8;
3345 if (idxRegDsc == -1)
3346 idxRegDsc = hdaRegLookup(pThis, offReg);
3347 else
3348 {
3349 idxRegDsc++;
3350 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3351 || g_aHdaRegMap[idxRegDsc].offset != offReg)
3352 {
3353 idxRegDsc = -1;
3354 }
3355 }
3356 }
3357 }
3358
3359 return rc;
3360}
3361
3362
3363/* PCI callback. */
3364
3365#ifdef IN_RING3
3366/**
3367 * @callback_method_impl{FNPCIIOREGIONMAP}
3368 */
3369static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
3370 PCIADDRESSSPACE enmType)
3371{
3372 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3373 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3374 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3375 int rc;
3376
3377 /*
3378 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3379 *
3380 * Let IOM talk DWORDs when reading, saves a lot of complications. On
3381 * writing though, we have to do it all ourselves because of sideeffects.
3382 */
3383 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3384 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
3385 IOMMMIO_FLAGS_READ_DWORD
3386 | IOMMMIO_FLAGS_WRITE_PASSTHRU,
3387 hdaMMIOWrite, hdaMMIORead, "HDA");
3388
3389 if (RT_FAILURE(rc))
3390 return rc;
3391
3392 if (pThis->fR0Enabled)
3393 {
3394 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
3395 "hdaMMIOWrite", "hdaMMIORead");
3396 if (RT_FAILURE(rc))
3397 return rc;
3398 }
3399
3400 if (pThis->fRCEnabled)
3401 {
3402 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
3403 "hdaMMIOWrite", "hdaMMIORead");
3404 if (RT_FAILURE(rc))
3405 return rc;
3406 }
3407
3408 pThis->MMIOBaseAddr = GCPhysAddress;
3409 return VINF_SUCCESS;
3410}
3411
3412
3413/* Saved state callbacks. */
3414
3415static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
3416{
3417 /* Save stream ID. */
3418 int rc = SSMR3PutU8(pSSM, pStrm->u8Strm);
3419 AssertRCReturn(rc, rc);
3420 Assert(pStrm->u8Strm <= 7); /** @todo Use a define. */
3421
3422 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields5, NULL);
3423 AssertRCReturn(rc, rc);
3424
3425 for (uint32_t i = 0; i < pStrm->State.cBDLE; i++)
3426 {
3427 rc = SSMR3PutStructEx(pSSM, &pStrm->State.paBDLE[i], sizeof(HDABDLE), 0 /*fFlags*/, g_aSSMBDLEStateFields5, NULL);
3428 AssertRCReturn(rc, rc);
3429 }
3430
3431 return rc;
3432}
3433
3434/**
3435 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3436 */
3437static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3438{
3439 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3440
3441 /* Save Codec nodes states. */
3442 hdaCodecSaveState(pThis->pCodec, pSSM);
3443
3444 /* Save MMIO registers. */
3445 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3446 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3447 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3448
3449 /* Save number of streams. */
3450 SSMR3PutU32(pSSM, 3);
3451
3452 /* Save stream states. */
3453 int rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStOut);
3454 AssertRCReturn(rc, rc);
3455 rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStMicIn);
3456 AssertRCReturn(rc, rc);
3457 rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStLineIn);
3458 AssertRCReturn(rc, rc);
3459
3460 return rc;
3461}
3462
3463
3464/**
3465 * @callback_method_impl{FNSSMDEVLOADEXEC}
3466 */
3467static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3468{
3469 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3470
3471 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3472
3473 LogFlowFunc(("uVersion=%RU32, uPass=%RU32\n", uVersion, uPass));
3474
3475 /*
3476 * Load Codec nodes states.
3477 */
3478 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3479 if (RT_FAILURE(rc))
3480 return rc;
3481
3482 /*
3483 * Load MMIO registers.
3484 */
3485 uint32_t cRegs;
3486 switch (uVersion)
3487 {
3488 case HDA_SSM_VERSION_1:
3489 /* Starting with r71199, we would save 112 instead of 113
3490 registers due to some code cleanups. This only affected trunk
3491 builds in the 4.1 development period. */
3492 cRegs = 113;
3493 if (SSMR3HandleRevision(pSSM) >= 71199)
3494 {
3495 uint32_t uVer = SSMR3HandleVersion(pSSM);
3496 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3497 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3498 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3499 cRegs = 112;
3500 }
3501 break;
3502
3503 case HDA_SSM_VERSION_2:
3504 case HDA_SSM_VERSION_3:
3505 cRegs = 112;
3506 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3507 break;
3508
3509 /* Since version 4 we store the register count to stay flexible. */
3510 case HDA_SSM_VERSION_4:
3511 case HDA_SSM_VERSION:
3512 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3513 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3514 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3515 break;
3516
3517 default:
3518 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3519 }
3520
3521 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3522 {
3523 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3524 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3525 }
3526 else
3527 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3528
3529 /*
3530 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3531 * *every* BDLE state, whereas it only needs to be stored
3532 * *once* for every stream. Most of the BDLE state we can
3533 * get out of the registers anyway, so just ignore those values.
3534 *
3535 * Also, only the current BDLE was saved, regardless whether
3536 * there were more than one (and there are at least two entries,
3537 * according to the spec).
3538 */
3539#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3540 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3541 AssertRCReturn(rc, rc); \
3542 rc = SSMR3Skip(pSSM, sizeof(uint64_t)); /* u64BdleCviAddr */ \
3543 AssertRCReturn(rc, rc); \
3544 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3545 AssertRCReturn(rc, rc); \
3546 rc = SSMR3GetU32(pSSM, &x->u32BDLIndex); /* u32BdleCvi */ \
3547 AssertRCReturn(rc, rc); \
3548 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleCviLen */ \
3549 AssertRCReturn(rc, rc); \
3550 rc = SSMR3GetU32(pSSM, &x->u32BufOff); /* u32BdleCviPos */ \
3551 AssertRCReturn(rc, rc); \
3552 rc = SSMR3Skip(pSSM, sizeof(uint8_t)); /* fBdleCviIoc */ \
3553 AssertRCReturn(rc, rc); \
3554 rc = SSMR3GetU32(pSSM, &x->cbBelowFIFOW); /* cbUnderFifoW */ \
3555 AssertRCReturn(rc, rc); \
3556 rc = SSMR3GetMem(pSSM, &x->au8FIFO, sizeof(x->au8FIFO)); \
3557 AssertRCReturn(rc, rc); \
3558 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3559 AssertRCReturn(rc, rc); \
3560
3561 /*
3562 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3563 */
3564 HDABDLESTATE StateBDLEDummy;
3565
3566 switch (uVersion)
3567 {
3568 case HDA_SSM_VERSION_1:
3569 case HDA_SSM_VERSION_2:
3570 case HDA_SSM_VERSION_3:
3571 case HDA_SSM_VERSION_4:
3572 {
3573 /* Only load the internal states.
3574 * The rest will be initialized from the saved registers later. */
3575
3576 /* Note: Only the *current* BDLE for a stream was saved! */
3577
3578 /* Output */
3579 rc = hdaStreamInit(pThis, &pThis->StrmStOut, 4 /* Stream number, hardcoded */);
3580 AssertRCBreak(rc);
3581 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStOut.State.cBDLE
3582 ? &pThis->StrmStOut.State.paBDLE[0].State : &StateBDLEDummy));
3583 /* Microphone-In */
3584 rc = hdaStreamInit(pThis, &pThis->StrmStMicIn, 2 /* Stream number, hardcoded */);
3585 AssertRCBreak(rc);
3586 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStMicIn.State.cBDLE
3587 ? &pThis->StrmStMicIn.State.paBDLE[0].State : &StateBDLEDummy));
3588 /* Line-In */
3589 rc = hdaStreamInit(pThis, &pThis->StrmStLineIn, 0 /* Stream number, hardcoded */);
3590 AssertRCBreak(rc);
3591 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStLineIn.State.cBDLE
3592 ? &pThis->StrmStLineIn.State.paBDLE[0].State : &StateBDLEDummy));
3593 break;
3594 }
3595
3596 /* Since v5 we support flexible stream and BDLE counts. */
3597 case HDA_SSM_VERSION:
3598 {
3599 uint32_t cStreams;
3600 rc = SSMR3GetU32(pSSM, &cStreams);
3601 AssertRCBreak(rc);
3602
3603 /* Load stream states. */
3604 for (uint32_t i = 0; i < cStreams; i++)
3605 {
3606 uint8_t uStreamID;
3607 rc = SSMR3GetU8(pSSM, &uStreamID);
3608 AssertRCBreak(rc);
3609
3610 PHDASTREAM pStrm;
3611 HDASTREAM StreamDummy;
3612
3613 switch (uStreamID)
3614 {
3615 case 0: /** @todo Use a define. */
3616 pStrm = &pThis->StrmStLineIn;
3617 break;
3618
3619 case 2: /** @todo Use a define. */
3620 pStrm = &pThis->StrmStMicIn;
3621 break;
3622
3623 case 4: /** @todo Use a define. */
3624 pStrm = &pThis->StrmStOut;
3625 break;
3626
3627 default:
3628 pStrm = &StreamDummy;
3629 break;
3630 }
3631
3632 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /* fFlags */, g_aSSMStreamStateFields5, NULL);
3633 AssertRCBreak(rc);
3634
3635 rc = hdaStreamInit(pThis, pStrm, uStreamID);
3636 AssertRCBreak(rc);
3637
3638 /* Load BDLE states. */
3639 for (uint32_t a = 0; a < pStrm->State.cBDLE; a++)
3640 {
3641 rc = SSMR3GetStructEx(pSSM, &pStrm->State.paBDLE[a].State, sizeof(HDABDLESTATE),
3642 0 /* fFlags */, g_aSSMBDLEStateFields5, NULL);
3643 AssertRCBreak(rc);
3644 }
3645
3646 /* Destroy dummy again. */
3647 if (pStrm == &StreamDummy)
3648 hdaStreamDestroy(pStrm);
3649 }
3650 break;
3651 }
3652
3653 default:
3654 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3655 }
3656
3657#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3658
3659 if (RT_SUCCESS(rc))
3660 {
3661 /*
3662 * Update stuff after the state changes.
3663 */
3664 bool fEnableIn = RT_BOOL(HDA_SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3665#ifdef VBOX_WITH_HDA_MIC_IN
3666 bool fEnableMicIn = RT_BOOL(HDA_SDCTL(pThis, 2) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3667#else
3668 bool fEnableMicIn = fEnableIn; /* Mic In == Line In */
3669#endif
3670 bool fEnableOut = RT_BOOL(HDA_SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3671
3672 PHDADRIVER pDrv;
3673 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3674 {
3675 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, fEnableIn);
3676 if (RT_FAILURE(rc))
3677 break;
3678 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, fEnableMicIn);
3679 if (RT_FAILURE(rc))
3680 break;
3681 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, fEnableOut);
3682 if (RT_FAILURE(rc))
3683 break;
3684 }
3685 }
3686
3687 if (RT_SUCCESS(rc))
3688 {
3689 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3690 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3691 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3692 }
3693
3694 LogFlowFuncLeaveRC(rc);
3695 return rc;
3696}
3697
3698#ifdef DEBUG
3699/* Debug and log type formatters. */
3700
3701/**
3702 * @callback_method_impl{FNRTSTRFORMATTYPE}
3703 */
3704static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3705 const char *pszType, void const *pvValue,
3706 int cchWidth, int cchPrecision, unsigned fFlags,
3707 void *pvUser)
3708{
3709 PHDABDLE pBDLE = (PHDABDLE)pvValue;
3710 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3711 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, DMA[%RU32 bytes @ 0x%x])",
3712 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW, pBDLE->u32BufSize, pBDLE->u64BufAdr);
3713}
3714
3715/**
3716 * @callback_method_impl{FNRTSTRFORMATTYPE}
3717 */
3718static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3719 const char *pszType, void const *pvValue,
3720 int cchWidth, int cchPrecision, unsigned fFlags,
3721 void *pvUser)
3722{
3723 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
3724 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3725 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
3726 uSDCTL,
3727 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
3728 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3729 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3730 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3731 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
3732 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3733 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3734 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3735}
3736
3737/**
3738 * @callback_method_impl{FNRTSTRFORMATTYPE}
3739 */
3740static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3741 const char *pszType, void const *pvValue,
3742 int cchWidth, int cchPrecision, unsigned fFlags,
3743 void *pvUser)
3744{
3745 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
3746 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, hdaSDFIFOSToBytes(uSDFIFOS));
3747}
3748
3749/**
3750 * @callback_method_impl{FNRTSTRFORMATTYPE}
3751 */
3752static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3753 const char *pszType, void const *pvValue,
3754 int cchWidth, int cchPrecision, unsigned fFlags,
3755 void *pvUser)
3756{
3757 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
3758 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
3759}
3760
3761/**
3762 * @callback_method_impl{FNRTSTRFORMATTYPE}
3763 */
3764static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3765 const char *pszType, void const *pvValue,
3766 int cchWidth, int cchPrecision, unsigned fFlags,
3767 void *pvUser)
3768{
3769 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3770 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3771 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3772 uSdSts,
3773 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3774 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3775 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3776 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3777}
3778
3779static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3780{
3781 int iReg = 0;
3782 for (; iReg < HDA_NREGS; ++iReg)
3783 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3784 return iReg;
3785 return -1;
3786}
3787
3788
3789static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
3790{
3791 Assert( pThis
3792 && iHdaIndex >= 0
3793 && iHdaIndex < HDA_NREGS);
3794 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
3795}
3796
3797/**
3798 * @callback_method_impl{FNDBGFHANDLERDEV}
3799 */
3800static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3801{
3802 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3803 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
3804 if (iHdaRegisterIndex != -1)
3805 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3806 else
3807 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
3808 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3809}
3810
3811static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
3812{
3813 Assert( pThis
3814 && iHdaStrmIndex >= 0
3815 && iHdaStrmIndex < 7);
3816 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
3817 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
3818 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
3819 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
3820 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
3821}
3822
3823static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
3824{
3825 /* todo: add args parsing */
3826 return -1;
3827}
3828
3829/**
3830 * @callback_method_impl{FNDBGFHANDLERDEV}
3831 */
3832static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3833{
3834 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3835 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
3836 if (iHdaStrmIndex != -1)
3837 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3838 else
3839 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
3840 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3841}
3842
3843/**
3844 * @callback_method_impl{FNDBGFHANDLERDEV}
3845 */
3846static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3847{
3848 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3849
3850 if (pThis->pCodec->pfnDbgListNodes)
3851 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
3852 else
3853 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3854}
3855
3856/**
3857 * @callback_method_impl{FNDBGFHANDLERDEV}
3858 */
3859static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3860{
3861 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3862
3863 if (pThis->pCodec->pfnDbgSelector)
3864 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
3865 else
3866 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3867}
3868
3869/**
3870 * @callback_method_impl{FNDBGFHANDLERDEV}
3871 */
3872static DECLCALLBACK(void) hdaInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3873{
3874 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3875
3876 if (pThis->pMixer)
3877 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
3878 else
3879 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
3880}
3881#endif /* DEBUG */
3882
3883/* PDMIBASE */
3884
3885/**
3886 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3887 */
3888static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3889{
3890 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
3891 Assert(&pThis->IBase == pInterface);
3892
3893 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3894 return NULL;
3895}
3896
3897
3898/* PDMDEVREG */
3899
3900/**
3901 * Reset notification.
3902 *
3903 * @returns VBox status code.
3904 * @param pDevIns The device instance data.
3905 *
3906 * @remark The original sources didn't install a reset handler, but it seems to
3907 * make sense to me so we'll do it.
3908 */
3909static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
3910{
3911 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3912
3913 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
3914 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3915 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3916 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3917 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3918 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
3919 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
3920 HDA_REG(pThis, CORBRP) = 0x0;
3921 HDA_REG(pThis, RIRBWP) = 0x0;
3922
3923 LogFunc(("Resetting ...\n"));
3924
3925 /* Stop any audio currently playing. */
3926 PHDADRIVER pDrv;
3927 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3928 {
3929 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
3930 /* Ignore rc. */
3931 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
3932 /* Ditto. */
3933 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
3934 /* Ditto. */
3935 }
3936
3937 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
3938
3939 if (pThis->pu32CorbBuf)
3940 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3941 else
3942 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3943
3944 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
3945 if (pThis->pu64RirbBuf)
3946 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3947 else
3948 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3949
3950 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
3951
3952 for (uint8_t u8Strm = 0; u8Strm < 8; u8Strm++) /** @todo Use a define here. */
3953 {
3954 PHDASTREAM pStrmSt = NULL;
3955 if (u8Strm == 0)
3956 pStrmSt = &pThis->StrmStOut;
3957# ifdef VBOX_WITH_HDA_MIC_IN
3958 else if (u8Strm == 2)
3959 pStrmSt = &pThis->StrmStMicIn;
3960# endif
3961 else if (u8Strm == 4)
3962 pStrmSt = &pThis->StrmStLineIn;
3963
3964 if (pStrmSt)
3965 {
3966 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
3967 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
3968
3969 hdaStreamReset(pThis, pStrmSt, u8Strm);
3970 }
3971 }
3972
3973 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3974 HDA_REG(pThis, STATESTS) = 0x1;
3975
3976 LogRel(("HDA: Reset\n"));
3977}
3978
3979/**
3980 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3981 */
3982static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
3983{
3984 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3985
3986 PHDADRIVER pDrv;
3987 while (!RTListIsEmpty(&pThis->lstDrv))
3988 {
3989 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
3990
3991 RTListNodeRemove(&pDrv->Node);
3992 RTMemFree(pDrv);
3993 }
3994
3995 if (pThis->pMixer)
3996 {
3997 AudioMixerDestroy(pThis->pMixer);
3998 pThis->pMixer = NULL;
3999 }
4000
4001 if (pThis->pCodec)
4002 {
4003 int rc = hdaCodecDestruct(pThis->pCodec);
4004 AssertRC(rc);
4005
4006 RTMemFree(pThis->pCodec);
4007 pThis->pCodec = NULL;
4008 }
4009
4010 RTMemFree(pThis->pu32CorbBuf);
4011 pThis->pu32CorbBuf = NULL;
4012
4013 RTMemFree(pThis->pu64RirbBuf);
4014 pThis->pu64RirbBuf = NULL;
4015
4016 hdaStreamDestroy(&pThis->StrmStLineIn);
4017 hdaStreamDestroy(&pThis->StrmStMicIn);
4018 hdaStreamDestroy(&pThis->StrmStOut);
4019
4020 return VINF_SUCCESS;
4021}
4022
4023/**
4024 * Attach command.
4025 *
4026 * This is called to let the device attach to a driver for a specified LUN
4027 * during runtime. This is not called during VM construction, the device
4028 * constructor have to attach to all the available drivers.
4029 *
4030 * @returns VBox status code.
4031 * @param pDevIns The device instance.
4032 * @param uLUN The logical unit which is being detached.
4033 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4034 */
4035static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4036{
4037 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4038
4039 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
4040 ("HDA device does not support hotplugging\n"),
4041 VERR_INVALID_PARAMETER);
4042
4043 /*
4044 * Attach driver.
4045 */
4046 char *pszDesc = NULL;
4047 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4048 AssertMsgReturn(pszDesc,
4049 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
4050 VERR_NO_MEMORY);
4051
4052 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
4053 &pThis->IBase, &pThis->pDrvBase, pszDesc);
4054 if (RT_SUCCESS(rc))
4055 {
4056 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4057 if (pDrv)
4058 {
4059 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
4060 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4061 pDrv->pHDAState = pThis;
4062 pDrv->uLUN = uLUN;
4063
4064 /*
4065 * For now we always set the driver at LUN 0 as our primary
4066 * host backend. This might change in the future.
4067 */
4068 if (pDrv->uLUN == 0)
4069 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
4070
4071 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
4072
4073 /* Attach to driver list. */
4074 RTListAppend(&pThis->lstDrv, &pDrv->Node);
4075 }
4076 else
4077 rc = VERR_NO_MEMORY;
4078 }
4079 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
4080 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
4081 {
4082 LogFunc(("No attached driver for LUN #%u\n", uLUN));
4083 }
4084 else if (RT_FAILURE(rc))
4085 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
4086 uLUN, pszDesc, rc));
4087
4088 RTStrFree(pszDesc);
4089
4090 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4091 return rc;
4092}
4093
4094static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4095{
4096 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
4097
4098 LogFlowFuncEnter();
4099}
4100
4101/**
4102 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4103 */
4104static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
4105{
4106 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4107 Assert(iInstance == 0);
4108 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4109
4110 /*
4111 * Validations.
4112 */
4113 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
4114 "RCEnabled\0"))
4115 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4116 N_ ("Invalid configuration for the Intel HDA device"));
4117
4118 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
4119 if (RT_FAILURE(rc))
4120 return PDMDEV_SET_ERROR(pDevIns, rc,
4121 N_("HDA configuration error: failed to read RCEnabled as boolean"));
4122 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
4123 if (RT_FAILURE(rc))
4124 return PDMDEV_SET_ERROR(pDevIns, rc,
4125 N_("HDA configuration error: failed to read R0Enabled as boolean"));
4126
4127 /*
4128 * Initialize data (most of it anyway).
4129 */
4130 pThis->pDevInsR3 = pDevIns;
4131 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4132 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4133 /* IBase */
4134 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
4135
4136 /* PCI Device */
4137 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
4138 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
4139
4140 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
4141 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
4142 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
4143 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
4144 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
4145 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
4146 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
4147 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
4148 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
4149 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
4150 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
4151
4152#if defined(HDA_AS_PCI_EXPRESS)
4153 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
4154#elif defined(VBOX_WITH_MSI_DEVICES)
4155 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
4156#else
4157 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
4158#endif
4159
4160 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
4161 /// of these values needs to be properly documented!
4162 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
4163 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
4164
4165 /* Power Management */
4166 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
4167 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
4168 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
4169
4170#ifdef HDA_AS_PCI_EXPRESS
4171 /* PCI Express */
4172 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
4173 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
4174 /* Device flags */
4175 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
4176 /* version */ 0x1 |
4177 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
4178 /* MSI */ (100) << 9 );
4179 /* Device capabilities */
4180 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
4181 /* Device control */
4182 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
4183 /* Device status */
4184 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
4185 /* Link caps */
4186 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
4187 /* Link control */
4188 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
4189 /* Link status */
4190 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
4191 /* Slot capabilities */
4192 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
4193 /* Slot control */
4194 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
4195 /* Slot status */
4196 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
4197 /* Root control */
4198 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
4199 /* Root capabilities */
4200 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
4201 /* Root status */
4202 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
4203 /* Device capabilities 2 */
4204 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
4205 /* Device control 2 */
4206 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
4207 /* Link control 2 */
4208 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
4209 /* Slot control 2 */
4210 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
4211#endif
4212
4213 /*
4214 * Register the PCI device.
4215 */
4216 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
4217 if (RT_FAILURE(rc))
4218 return rc;
4219
4220 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
4221 if (RT_FAILURE(rc))
4222 return rc;
4223
4224#ifdef VBOX_WITH_MSI_DEVICES
4225 PDMMSIREG MsiReg;
4226 RT_ZERO(MsiReg);
4227 MsiReg.cMsiVectors = 1;
4228 MsiReg.iMsiCapOffset = 0x60;
4229 MsiReg.iMsiNextOffset = 0x50;
4230 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4231 if (RT_FAILURE(rc))
4232 {
4233 /* That's OK, we can work without MSI */
4234 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
4235 }
4236#endif
4237
4238 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
4239 if (RT_FAILURE(rc))
4240 return rc;
4241
4242 RTListInit(&pThis->lstDrv);
4243
4244 uint8_t uLUN;
4245 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
4246 {
4247 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
4248 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
4249 if (RT_FAILURE(rc))
4250 {
4251 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4252 rc = VINF_SUCCESS;
4253
4254 break;
4255 }
4256
4257 uLUN++;
4258 }
4259
4260 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
4261
4262 if (RT_SUCCESS(rc))
4263 {
4264 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
4265 if (RT_SUCCESS(rc))
4266 {
4267 /* Set a default audio format for our mixer. */
4268 PDMAUDIOSTREAMCFG streamCfg;
4269 streamCfg.uHz = 44100;
4270 streamCfg.cChannels = 2;
4271 streamCfg.enmFormat = AUD_FMT_S16;
4272 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
4273
4274 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
4275 AssertRC(rc);
4276
4277 /* Add all required audio sinks. */
4278 rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output",
4279 AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
4280 AssertRC(rc);
4281
4282 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In",
4283 AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
4284 AssertRC(rc);
4285
4286 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
4287 AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
4288 AssertRC(rc);
4289
4290 /* There is no master volume control. Set the master to max. */
4291 PDMAUDIOVOLUME vol = { false, 255, 255 };
4292 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
4293 AssertRC(rc);
4294 }
4295 }
4296
4297 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
4298
4299 if (RT_SUCCESS(rc))
4300 {
4301 /* Construct codec. */
4302 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
4303 if (!pThis->pCodec)
4304 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
4305
4306 /* Audio driver callbacks for multiplexing. */
4307 pThis->pCodec->pfnCloseIn = hdaCloseIn;
4308 pThis->pCodec->pfnCloseOut = hdaCloseOut;
4309 pThis->pCodec->pfnOpenIn = hdaOpenIn;
4310 pThis->pCodec->pfnOpenOut = hdaOpenOut;
4311 pThis->pCodec->pfnReset = hdaCodecReset;
4312 pThis->pCodec->pfnSetVolume = hdaSetVolume;
4313
4314 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
4315
4316 /* Construct the codec. */
4317 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
4318 if (RT_FAILURE(rc))
4319 AssertRCReturn(rc, rc);
4320
4321 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
4322 verb F20 should provide device/codec recognition. */
4323 Assert(pThis->pCodec->u16VendorId);
4324 Assert(pThis->pCodec->u16DeviceId);
4325 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
4326 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
4327 }
4328
4329 if (RT_SUCCESS(rc))
4330 {
4331 hdaReset(pDevIns);
4332
4333 /*
4334 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4335 * hdaReset shouldn't affects these registers.
4336 */
4337 HDA_REG(pThis, WAKEEN) = 0x0;
4338 HDA_REG(pThis, STATESTS) = 0x0;
4339
4340#ifdef DEBUG
4341 /*
4342 * Debug and string formatter types.
4343 */
4344 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
4345 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
4346 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
4347 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
4348 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaInfoMixer);
4349
4350 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
4351 AssertRC(rc);
4352 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
4353 AssertRC(rc);
4354 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
4355 AssertRC(rc);
4356 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
4357 AssertRC(rc);
4358 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
4359 AssertRC(rc);
4360#endif /* DEBUG */
4361
4362 /*
4363 * Some debug assertions.
4364 */
4365 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
4366 {
4367 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
4368 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
4369
4370 /* binary search order. */
4371 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
4372 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4373 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4374
4375 /* alignment. */
4376 AssertReleaseMsg( pReg->size == 1
4377 || (pReg->size == 2 && (pReg->offset & 1) == 0)
4378 || (pReg->size == 3 && (pReg->offset & 3) == 0)
4379 || (pReg->size == 4 && (pReg->offset & 3) == 0),
4380 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4381
4382 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
4383 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
4384 if (pReg->offset & 3)
4385 {
4386 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
4387 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4388 if (pPrevReg)
4389 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
4390 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4391 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
4392 }
4393#if 0
4394 if ((pReg->offset + pReg->size) & 3)
4395 {
4396 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4397 if (pNextReg)
4398 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
4399 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4400 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4401 }
4402#endif
4403 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
4404 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
4405 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4406 }
4407 }
4408
4409# ifndef VBOX_WITH_AUDIO_CALLBACKS
4410 if (RT_SUCCESS(rc))
4411 {
4412 /* Start the emulation timer. */
4413 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
4414 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
4415 AssertRCReturn(rc, rc);
4416
4417 if (RT_SUCCESS(rc))
4418 {
4419 /** @todo Investigate why sounds is getting corrupted if the "ticks" value is too
4420 * low, e.g. "PDMDevHlpTMTimeVirtGetFreq / 200". */
4421 pThis->uTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 500; /** @todo Make this configurable! */
4422 if (pThis->uTicks < 100)
4423 pThis->uTicks = 100;
4424 LogFunc(("Timer ticks=%RU64\n", pThis->uTicks));
4425
4426 /* Fire off timer. */
4427 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
4428 }
4429 }
4430# else
4431 if (RT_SUCCESS(rc))
4432 {
4433 PHDADRIVER pDrv;
4434 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4435 {
4436 /* Only register primary driver.
4437 * The device emulation does the output multiplexing then. */
4438 if (pDrv->Flags != PDMAUDIODRVFLAG_PRIMARY)
4439 continue;
4440
4441 PDMAUDIOCALLBACK AudioCallbacks[2];
4442
4443 HDACALLBACKCTX Ctx = { pThis, pDrv };
4444
4445 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
4446 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
4447 AudioCallbacks[0].pvCtx = &Ctx;
4448 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
4449
4450 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
4451 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
4452 AudioCallbacks[1].pvCtx = &Ctx;
4453 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
4454
4455 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
4456 if (RT_FAILURE(rc))
4457 break;
4458 }
4459 }
4460# endif
4461
4462# ifdef VBOX_WITH_STATISTICS
4463 if (RT_SUCCESS(rc))
4464 {
4465 /*
4466 * Register statistics.
4467 */
4468# ifndef VBOX_WITH_AUDIO_CALLBACKS
4469 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
4470# endif
4471 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
4472 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
4473 }
4474# endif
4475
4476 LogFlowFuncLeaveRC(rc);
4477 return rc;
4478}
4479
4480/**
4481 * The device registration structure.
4482 */
4483const PDMDEVREG g_DeviceICH6_HDA =
4484{
4485 /* u32Version */
4486 PDM_DEVREG_VERSION,
4487 /* szName */
4488 "hda",
4489 /* szRCMod */
4490 "VBoxDDRC.rc",
4491 /* szR0Mod */
4492 "VBoxDDR0.r0",
4493 /* pszDescription */
4494 "Intel HD Audio Controller",
4495 /* fFlags */
4496 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
4497 /* fClass */
4498 PDM_DEVREG_CLASS_AUDIO,
4499 /* cMaxInstances */
4500 1,
4501 /* cbInstance */
4502 sizeof(HDASTATE),
4503 /* pfnConstruct */
4504 hdaConstruct,
4505 /* pfnDestruct */
4506 hdaDestruct,
4507 /* pfnRelocate */
4508 NULL,
4509 /* pfnMemSetup */
4510 NULL,
4511 /* pfnPowerOn */
4512 NULL,
4513 /* pfnReset */
4514 hdaReset,
4515 /* pfnSuspend */
4516 NULL,
4517 /* pfnResume */
4518 NULL,
4519 /* pfnAttach */
4520 NULL,
4521 /* pfnDetach */
4522 NULL,
4523 /* pfnQueryInterface. */
4524 NULL,
4525 /* pfnInitComplete */
4526 NULL,
4527 /* pfnPowerOff */
4528 NULL,
4529 /* pfnSoftReset */
4530 NULL,
4531 /* u32VersionEnd */
4532 PDM_DEVREG_VERSION
4533};
4534
4535#endif /* IN_RING3 */
4536#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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