VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 59085

Last change on this file since 59085 was 59069, checked in by vboxsync, 9 years ago

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1/* $Id: DevIchHda.cpp 59069 2015-12-09 15:56:21Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2015 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/list.h>
36#ifdef IN_RING3
37# include <iprt/mem.h>
38# include <iprt/string.h>
39# include <iprt/uuid.h>
40#endif
41
42#include "VBoxDD.h"
43
44#include "AudioMixBuffer.h"
45#include "AudioMixer.h"
46#include "DevIchHdaCodec.h"
47
48
49/*********************************************************************************************************************************
50* Defined Constants And Macros *
51*********************************************************************************************************************************/
52//#define HDA_AS_PCI_EXPRESS
53#define VBOX_WITH_INTEL_HDA
54
55#if (defined(DEBUG) && defined(DEBUG_andy))
56/* Enables experimental support for separate mic-in handling.
57 Do not enable this yet for regular builds, as this needs more testing first! */
58# define VBOX_WITH_HDA_MIC_IN
59#endif
60
61#if defined(VBOX_WITH_HP_HDA)
62/* HP Pavilion dv4t-1300 */
63# define HDA_PCI_VENDOR_ID 0x103c
64# define HDA_PCI_DEVICE_ID 0x30f7
65#elif defined(VBOX_WITH_INTEL_HDA)
66/* Intel HDA controller */
67# define HDA_PCI_VENDOR_ID 0x8086
68# define HDA_PCI_DEVICE_ID 0x2668
69#elif defined(VBOX_WITH_NVIDIA_HDA)
70/* nVidia HDA controller */
71# define HDA_PCI_VENDOR_ID 0x10de
72# define HDA_PCI_DEVICE_ID 0x0ac0
73#else
74# error "Please specify your HDA device vendor/device IDs"
75#endif
76
77/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
78 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
79 * is read only except for bit 15 like the HDA spec states.
80 *
81 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
82 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
83#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
84
85#define HDA_NREGS 114
86#define HDA_NREGS_SAVED 112
87
88/**
89 * NB: Register values stored in memory (au32Regs[]) are indexed through
90 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
91 * register descriptors in g_aHdaRegMap[] are indexed through the
92 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
93 *
94 * The au32Regs[] layout is kept unchanged for saved state
95 * compatibility. */
96
97/* Registers */
98#define HDA_REG_IND_NAME(x) HDA_REG_##x
99#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
100#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
101#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
102#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
103#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
104#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
105#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
106
107
108#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
109#define HDA_RMX_GCAP 0
110/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
111 * oss (15:12) - number of output streams supported
112 * iss (11:8) - number of input streams supported
113 * bss (7:3) - number of bidirectional streams supported
114 * bds (2:1) - number of serial data out signals supported
115 * b64sup (0) - 64 bit addressing supported.
116 */
117#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
118 ( (((oss) & 0xF) << 12) \
119 | (((iss) & 0xF) << 8) \
120 | (((bss) & 0x1F) << 3) \
121 | (((bds) & 0x3) << 2) \
122 | ((b64sup) & 1))
123
124#define HDA_REG_VMIN 1 /* 0x02 */
125#define HDA_RMX_VMIN 1
126
127#define HDA_REG_VMAJ 2 /* 0x03 */
128#define HDA_RMX_VMAJ 2
129
130#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
131#define HDA_RMX_OUTPAY 3
132
133#define HDA_REG_INPAY 4 /* 0x06-0x07 */
134#define HDA_RMX_INPAY 4
135
136#define HDA_REG_GCTL 5 /* 0x08-0x0B */
137#define HDA_RMX_GCTL 5
138#define HDA_GCTL_RST_SHIFT 0
139#define HDA_GCTL_FSH_SHIFT 1
140#define HDA_GCTL_UR_SHIFT 8
141
142#define HDA_REG_WAKEEN 6 /* 0x0C */
143#define HDA_RMX_WAKEEN 6
144
145#define HDA_REG_STATESTS 7 /* 0x0E */
146#define HDA_RMX_STATESTS 7
147#define HDA_STATES_SCSF 0x7
148
149#define HDA_REG_GSTS 8 /* 0x10-0x11*/
150#define HDA_RMX_GSTS 8
151#define HDA_GSTS_FSH_SHIFT 1
152
153#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
154#define HDA_RMX_OUTSTRMPAY 112
155
156#define HDA_REG_INSTRMPAY 10 /* 0x1a */
157#define HDA_RMX_INSTRMPAY 113
158
159#define HDA_REG_INTCTL 11 /* 0x20 */
160#define HDA_RMX_INTCTL 9
161#define HDA_INTCTL_GIE_SHIFT 31
162#define HDA_INTCTL_CIE_SHIFT 30
163#define HDA_INTCTL_S0_SHIFT 0
164#define HDA_INTCTL_S1_SHIFT 1
165#define HDA_INTCTL_S2_SHIFT 2
166#define HDA_INTCTL_S3_SHIFT 3
167#define HDA_INTCTL_S4_SHIFT 4
168#define HDA_INTCTL_S5_SHIFT 5
169#define HDA_INTCTL_S6_SHIFT 6
170#define HDA_INTCTL_S7_SHIFT 7
171#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
172
173#define HDA_REG_INTSTS 12 /* 0x24 */
174#define HDA_RMX_INTSTS 10
175#define HDA_INTSTS_GIS_SHIFT 31
176#define HDA_INTSTS_CIS_SHIFT 30
177#define HDA_INTSTS_S0_SHIFT 0
178#define HDA_INTSTS_S1_SHIFT 1
179#define HDA_INTSTS_S2_SHIFT 2
180#define HDA_INTSTS_S3_SHIFT 3
181#define HDA_INTSTS_S4_SHIFT 4
182#define HDA_INTSTS_S5_SHIFT 5
183#define HDA_INTSTS_S6_SHIFT 6
184#define HDA_INTSTS_S7_SHIFT 7
185#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
186
187#define HDA_REG_WALCLK 13 /* 0x24 */
188#define HDA_RMX_WALCLK /* Not defined! */
189
190/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
191 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
192 * the datasheet.
193 */
194#define HDA_REG_SSYNC 14 /* 0x34 */
195#define HDA_RMX_SSYNC 12
196
197#define HDA_REG_CORBLBASE 15 /* 0x40 */
198#define HDA_RMX_CORBLBASE 13
199
200#define HDA_REG_CORBUBASE 16 /* 0x44 */
201#define HDA_RMX_CORBUBASE 14
202
203#define HDA_REG_CORBWP 17 /* 0x48 */
204#define HDA_RMX_CORBWP 15
205
206#define HDA_REG_CORBRP 18 /* 0x4A */
207#define HDA_RMX_CORBRP 16
208#define HDA_CORBRP_RST_SHIFT 15
209#define HDA_CORBRP_WP_SHIFT 0
210#define HDA_CORBRP_WP_MASK 0xFF
211
212#define HDA_REG_CORBCTL 19 /* 0x4C */
213#define HDA_RMX_CORBCTL 17
214#define HDA_CORBCTL_DMA_SHIFT 1
215#define HDA_CORBCTL_CMEIE_SHIFT 0
216
217#define HDA_REG_CORBSTS 20 /* 0x4D */
218#define HDA_RMX_CORBSTS 18
219#define HDA_CORBSTS_CMEI_SHIFT 0
220
221#define HDA_REG_CORBSIZE 21 /* 0x4E */
222#define HDA_RMX_CORBSIZE 19
223#define HDA_CORBSIZE_SZ_CAP 0xF0
224#define HDA_CORBSIZE_SZ 0x3
225/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
226
227#define HDA_REG_RIRBLBASE 22 /* 0x50 */
228#define HDA_RMX_RIRBLBASE 20
229
230#define HDA_REG_RIRBUBASE 23 /* 0x54 */
231#define HDA_RMX_RIRBUBASE 21
232
233#define HDA_REG_RIRBWP 24 /* 0x58 */
234#define HDA_RMX_RIRBWP 22
235#define HDA_RIRBWP_RST_SHIFT 15
236#define HDA_RIRBWP_WP_MASK 0xFF
237
238#define HDA_REG_RINTCNT 25 /* 0x5A */
239#define HDA_RMX_RINTCNT 23
240#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
241
242#define HDA_REG_RIRBCTL 26 /* 0x5C */
243#define HDA_RMX_RIRBCTL 24
244#define HDA_RIRBCTL_RIC_SHIFT 0
245#define HDA_RIRBCTL_DMA_SHIFT 1
246#define HDA_ROI_DMA_SHIFT 2
247
248#define HDA_REG_RIRBSTS 27 /* 0x5D */
249#define HDA_RMX_RIRBSTS 25
250#define HDA_RIRBSTS_RINTFL_SHIFT 0
251#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
252
253#define HDA_REG_RIRBSIZE 28 /* 0x5E */
254#define HDA_RMX_RIRBSIZE 26
255#define HDA_RIRBSIZE_SZ_CAP 0xF0
256#define HDA_RIRBSIZE_SZ 0x3
257
258#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
259#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
260
261
262#define HDA_REG_IC 29 /* 0x60 */
263#define HDA_RMX_IC 27
264
265#define HDA_REG_IR 30 /* 0x64 */
266#define HDA_RMX_IR 28
267
268#define HDA_REG_IRS 31 /* 0x68 */
269#define HDA_RMX_IRS 29
270#define HDA_IRS_ICB_SHIFT 0
271#define HDA_IRS_IRV_SHIFT 1
272
273#define HDA_REG_DPLBASE 32 /* 0x70 */
274#define HDA_RMX_DPLBASE 30
275#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
276
277#define HDA_REG_DPUBASE 33 /* 0x74 */
278#define HDA_RMX_DPUBASE 31
279#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
280
281#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
282
283#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
284#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
285/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
286#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
287
288#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
289
290#define HDA_REG_SD0CTL 34 /* 0x80 */
291#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
292#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
293#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
294#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
295#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
296#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
297#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
298#define HDA_RMX_SD0CTL 32
299#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
300#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
301#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
302#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
303#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
304#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
305#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
306
307#define SD(func, num) SD##num##func
308
309#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
310#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
311#define HDA_SDCTL_NUM_MASK 0xF
312#define HDA_SDCTL_NUM_SHIFT 20
313#define HDA_SDCTL_DIR_SHIFT 19
314#define HDA_SDCTL_TP_SHIFT 18
315#define HDA_SDCTL_STRIPE_MASK 0x3
316#define HDA_SDCTL_STRIPE_SHIFT 16
317#define HDA_SDCTL_DEIE_SHIFT 4
318#define HDA_SDCTL_FEIE_SHIFT 3
319#define HDA_SDCTL_ICE_SHIFT 2
320#define HDA_SDCTL_RUN_SHIFT 1
321#define HDA_SDCTL_SRST_SHIFT 0
322
323#define HDA_REG_SD0STS 35 /* 0x83 */
324#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
325#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
326#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
327#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
328#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
329#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
330#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
331#define HDA_RMX_SD0STS 33
332#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
333#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
334#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
335#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
336#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
337#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
338#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
339
340#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
341#define HDA_SDSTS_FIFORDY_SHIFT 5
342#define HDA_SDSTS_DE_SHIFT 4
343#define HDA_SDSTS_FE_SHIFT 3
344#define HDA_SDSTS_BCIS_SHIFT 2
345
346#define HDA_REG_SD0LPIB 36 /* 0x84 */
347#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
348#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
349#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
350#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
351#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
352#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
353#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
354#define HDA_RMX_SD0LPIB 34
355#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
356#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
357#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
358#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
359#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
360#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
361#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
362
363#define HDA_REG_SD0CBL 37 /* 0x88 */
364#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
365#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
366#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
367#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
368#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
369#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
370#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
371#define HDA_RMX_SD0CBL 35
372#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
373#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
374#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
375#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
376#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
377#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
378#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
379
380#define HDA_REG_SD0LVI 38 /* 0x8C */
381#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
382#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
383#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
384#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
385#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
386#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
387#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
388#define HDA_RMX_SD0LVI 36
389#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
390#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
391#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
392#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
393#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
394#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
395#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
396
397#define HDA_REG_SD0FIFOW 39 /* 0x8E */
398#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
399#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
400#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
401#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
402#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
403#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
404#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
405#define HDA_RMX_SD0FIFOW 37
406#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
407#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
408#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
409#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
410#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
411#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
412#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
413
414/*
415 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
416 */
417#define HDA_SDFIFOW_8B 0x2
418#define HDA_SDFIFOW_16B 0x3
419#define HDA_SDFIFOW_32B 0x4
420
421#define HDA_REG_SD0FIFOS 40 /* 0x90 */
422#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
423#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
424#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
425#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
426#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
427#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
428#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
429#define HDA_RMX_SD0FIFOS 38
430#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
431#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
432#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
433#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
434#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
435#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
436#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
437
438/*
439 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
440 * formula: size - 1
441 * Other values not listed are not supported.
442 */
443#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
444#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
445
446#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
447#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
448#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
449#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
450#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
451#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
452#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
453
454#define HDA_REG_SD0FMT 41 /* 0x92 */
455#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
456#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
457#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
458#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
459#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
460#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
461#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
462#define HDA_RMX_SD0FMT 39
463#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
464#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
465#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
466#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
467#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
468#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
469#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
470
471#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
472#define HDA_SDFMT_BASE_RATE_SHIFT 14
473#define HDA_SDFMT_MULT_SHIFT 11
474#define HDA_SDFMT_MULT_MASK 0x7
475#define HDA_SDFMT_DIV_SHIFT 8
476#define HDA_SDFMT_DIV_MASK 0x7
477#define HDA_SDFMT_BITS_SHIFT 4
478#define HDA_SDFMT_BITS_MASK 0x7
479#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
480#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
481#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
482
483#define HDA_REG_SD0BDPL 42 /* 0x98 */
484#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
485#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
486#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
487#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
488#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
489#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
490#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
491#define HDA_RMX_SD0BDPL 40
492#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
493#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
494#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
495#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
496#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
497#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
498#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
499
500#define HDA_REG_SD0BDPU 43 /* 0x9C */
501#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
502#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
503#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
504#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
505#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
506#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
507#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
508#define HDA_RMX_SD0BDPU 41
509#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
510#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
511#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
512#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
513#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
514#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
515#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
516
517#define HDA_CODEC_CAD_SHIFT 28
518/* Encodes the (required) LUN into a codec command. */
519#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
520
521
522
523/*********************************************************************************************************************************
524* Structures and Typedefs *
525*********************************************************************************************************************************/
526
527/**
528 * Internal state of a Buffer Descriptor List Entry (BDLE),
529 * needed to keep track of the data needed for the actual device
530 * emulation.
531 */
532typedef struct HDABDLESTATE
533{
534 /** Own index within the BDL (Buffer Descriptor List). */
535 uint32_t u32BDLIndex;
536 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
537 * Used to check if we need fill up the FIFO again. */
538 uint32_t cbBelowFIFOW;
539 /** The buffer descriptor's internal DMA buffer. */
540 uint8_t au8FIFO[HDA_SDONFIFO_256B + 1];
541 /** Current offset in DMA buffer (in bytes).*/
542 uint32_t u32BufOff;
543 uint32_t Padding;
544} HDABDLESTATE, *PHDABDLESTATE;
545
546/**
547 * Buffer Descriptor List Entry (BDLE) (3.6.3).
548 *
549 * Contains only register values which do *not* change until a
550 * stream reset occurs.
551 */
552typedef struct HDABDLE
553{
554 /** Starting address of the actual buffer. Must be 128-bit aligned. */
555 uint64_t u64BufAdr;
556 /** Size of the actual buffer (in bytes). */
557 uint32_t u32BufSize;
558 /** Interrupt on completion; the controller will generate
559 * an interrupt when the last byte of the buffer has been
560 * fetched by the DMA engine. */
561 bool fIntOnCompletion;
562 /** Internal state of this BDLE.
563 * Not part of the actual BDLE registers. */
564 HDABDLESTATE State;
565} HDABDLE, *PHDABDLE;
566
567/**
568 * Internal state of a HDA stream.
569 */
570typedef struct HDASTREAMSTATE
571{
572 /** Number of BDLEs (Buffer Descriptor List Entry).
573 * Should be SDnLVI + 1 usually. */
574 uint16_t cBDLE;
575 /** Current BDLE to use. Wraps around to 0 if
576 * maximum (cBDLE) is reached. */
577 uint16_t uCurBDLE;
578 uint32_t Padding;
579 /** Array of BDLEs. */
580 R3PTRTYPE(PHDABDLE) paBDLE;
581} HDASTREAMSTATE, *PHDASTREAMSTATE;
582
583/**
584 * Structure for keeping a HDA stream state.
585 *
586 * Contains only register values which do *not* change until a
587 * stream reset occurs.
588 */
589typedef struct HDASTREAM
590{
591 /** Stream number (SDn). */
592 uint8_t u8Strm;
593 uint8_t Padding0[7];
594 /** DMA base address (SDnBDPU - SDnBDPL). */
595 uint64_t u64BaseDMA;
596 /** Cyclic Buffer Length (SDnCBL).
597 * Represents the size of the ring buffer. */
598 uint32_t u32CBL;
599 /** Format (SDnFMT). */
600 uint16_t u16FMT;
601 /** FIFO Size (FIFOS).
602 * Maximum number of bytes that may have been DMA'd into
603 * memory but not yet transmitted on the link.
604 *
605 * Must be a power of two. */
606 uint16_t u16FIFOS;
607 /** Last Valid Index (SDnLVI). */
608 uint16_t u16LVI;
609 uint16_t Padding1[3];
610 /** Internal state of this stream. */
611 HDASTREAMSTATE State;
612} HDASTREAM, *PHDASTREAM;
613
614typedef struct HDAINPUTSTREAM
615{
616 /** PCM line input stream. */
617 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
618 /** Mixer handle for line input stream. */
619 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
620} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
621
622typedef struct HDAOUTPUTSTREAM
623{
624 /** PCM output stream. */
625 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
626 /** Mixer handle for line output stream. */
627 R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
628} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
629
630/**
631 * Struct for maintaining a host backend driver.
632 * This driver must be associated to one, and only one,
633 * HDA codec. The HDA controller does the actual multiplexing
634 * of HDA codec data to various host backend drivers then.
635 *
636 * This HDA device uses a timer in order to synchronize all
637 * read/write accesses across all attached LUNs / backends.
638 */
639typedef struct HDADRIVER
640{
641 union
642 {
643 /** Node for storing this driver in our device driver
644 * list of HDASTATE. */
645 RTLISTNODE Node;
646 struct
647 {
648 R3PTRTYPE(void *) dummy1;
649 R3PTRTYPE(void *) dummy2;
650 } dummy;
651 };
652
653 /** Pointer to HDA controller (state). */
654 R3PTRTYPE(PHDASTATE) pHDAState;
655 /** Driver flags. */
656 PDMAUDIODRVFLAGS Flags;
657 uint8_t u32Padding0[3];
658 /** LUN to which this driver has been assigned. */
659 uint8_t uLUN;
660 /** Audio connector interface to the underlying
661 * host backend. */
662 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
663 /** Stream for line input. */
664 HDAINPUTSTREAM LineIn;
665 /** Stream for mic input. */
666 HDAINPUTSTREAM MicIn;
667 /** Stream for output. */
668 HDAOUTPUTSTREAM Out;
669} HDADRIVER;
670
671/**
672 * ICH Intel HD Audio Controller state.
673 */
674typedef struct HDASTATE
675{
676 /** The PCI device structure. */
677 PCIDevice PciDev;
678 /** R3 Pointer to the device instance. */
679 PPDMDEVINSR3 pDevInsR3;
680 /** R0 Pointer to the device instance. */
681 PPDMDEVINSR0 pDevInsR0;
682 /** R0 Pointer to the device instance. */
683 PPDMDEVINSRC pDevInsRC;
684 /** Padding for alignment. */
685 uint32_t u32Padding;
686 /** Pointer to the attached audio driver. */
687 R3PTRTYPE(PPDMIBASE) pDrvBase;
688 /** The base interface for LUN\#0. */
689 PDMIBASE IBase;
690 RTGCPHYS MMIOBaseAddr;
691 /** The HDA's register set. */
692 uint32_t au32Regs[HDA_NREGS];
693 /** Stream state for line-in. */
694 HDASTREAM StrmStLineIn;
695 /** Stream state for microphone-in. */
696 HDASTREAM StrmStMicIn;
697 /** Stream state for output. */
698 HDASTREAM StrmStOut;
699 /** CORB buffer base address. */
700 uint64_t u64CORBBase;
701 /** RIRB buffer base address. */
702 uint64_t u64RIRBBase;
703 /** DMA base address.
704 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
705 uint64_t u64DPBase;
706 /** DMA position buffer enable bit. */
707 bool fDMAPosition;
708 /** Padding for alignment. */
709 uint8_t u32Padding0[7];
710 /** Pointer to CORB buffer. */
711 R3PTRTYPE(uint32_t *) pu32CorbBuf;
712 /** Size in bytes of CORB buffer. */
713 uint32_t cbCorbBuf;
714 /** Padding for alignment. */
715 uint32_t u32Padding1;
716 /** Pointer to RIRB buffer. */
717 R3PTRTYPE(uint64_t *) pu64RirbBuf;
718 /** Size in bytes of RIRB buffer. */
719 uint32_t cbRirbBuf;
720 /** Indicates if HDA is in reset. */
721 bool fInReset;
722 /** Flag whether the R0 part is enabled. */
723 bool fR0Enabled;
724 /** Flag whether the RC part is enabled. */
725 bool fRCEnabled;
726#ifndef VBOX_WITH_AUDIO_CALLBACKS
727 /** The emulation timer for handling the attached
728 * LUN drivers. */
729 PTMTIMERR3 pTimer;
730 /** Timer ticks for handling the LUN drivers. */
731 uint64_t uTimerTicks;
732 /** Timestamp (delta) since last timer call. */
733 uint64_t uTimerTS;
734#endif
735#ifdef VBOX_WITH_STATISTICS
736# ifndef VBOX_WITH_AUDIO_CALLBACKS
737 STAMPROFILE StatTimer;
738# endif
739 STAMCOUNTER StatBytesRead;
740 STAMCOUNTER StatBytesWritten;
741#endif
742 /** Pointer to HDA codec to use. */
743 R3PTRTYPE(PHDACODEC) pCodec;
744 union
745 {
746 /** List of associated LUN drivers. */
747 RTLISTANCHOR lstDrv;
748 /** Padding for alignment. */
749 struct
750 {
751 R3PTRTYPE(void *) dummy1;
752 R3PTRTYPE(void *) dummy2;
753 } dummy;
754 };
755 /** The device' software mixer. */
756 R3PTRTYPE(PAUDIOMIXER) pMixer;
757 /** Audio sink for PCM output. */
758 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
759 /** Audio mixer sink for line input. */
760 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
761 /** Audio mixer sink for microphone input. */
762 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
763 uint64_t u64BaseTS;
764 /** Response Interrupt Count (RINTCNT). */
765 uint8_t u8RespIntCnt;
766 /** Padding for alignment. */
767 uint8_t au8Padding2[7];
768} HDASTATE;
769/** Pointer to the ICH Intel HD Audio Controller state. */
770typedef HDASTATE *PHDASTATE;
771
772#ifdef VBOX_WITH_AUDIO_CALLBACKS
773typedef struct HDACALLBACKCTX
774{
775 PHDASTATE pThis;
776 PHDADRIVER pDriver;
777} HDACALLBACKCTX, *PHDACALLBACKCTX;
778#endif
779
780/*********************************************************************************************************************************
781* Internal Functions *
782*********************************************************************************************************************************/
783#ifndef VBOX_DEVICE_STRUCT_TESTCASE
784static FNPDMDEVRESET hdaReset;
785
786/*
787 * Stubs.
788 */
789static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
790static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
791
792/*
793 * Global register set read/write functions.
794 */
795static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
796static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
797static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
798static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
799static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
800static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
801static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
802static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
803static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
804static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
805static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
806static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
807static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
808static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
809static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
810
811/*
812 * {IOB}SDn read/write functions.
813 */
814static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
815static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
816static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
817static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
818static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
819static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
820static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
821static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
822static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
823
824/*
825 * Generic register read/write functions.
826 */
827static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
828static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
829static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
830static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
831static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
832static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
833static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
834static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
835
836static void hdaStreamDestroy(PHDASTREAM pStrmSt);
837
838static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbMax, uint32_t *pcbProcessed);
839
840#ifdef IN_RING3
841static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
842static void hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t u32LPIB);
843# ifdef LOG_ENABLED
844static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t u16LVI);
845# endif
846static void hdaBDLEReset(PHDABDLE pBDLE);
847#endif
848
849
850/*********************************************************************************************************************************
851* Global Variables *
852*********************************************************************************************************************************/
853
854/** Offset of the SD0 register map. */
855#define HDA_REG_DESC_SD0_BASE 0x80
856
857/** Turn a short global register name into an memory index and a stringized name. */
858#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
859
860/** Turns a short stream register name into an memory index and a stringized name. */
861#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
862
863/** Same as above for a register *not* stored in memory. */
864#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
865
866/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
867#define HDA_REG_MAP_STRM(offset, name) \
868 /* offset size read mask write mask read callback write callback index + abbrev description */ \
869 /* ------- ------- ---------- ---------- -------------- ----------------- ------------------------------ ----------- */ \
870 /* Offset 0x80 (SD0) */ \
871 { offset, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
872 /* Offset 0x83 (SD0) */ \
873 { offset + 0x3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
874 /* Offset 0x84 (SD0) */ \
875 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
876 /* Offset 0x88 (SD0) */ \
877 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
878 /* Offset 0x8C (SD0) */ \
879 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
880 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
881 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
882 /* Offset 0x90 (SD0) */ \
883 { offset + 0x10, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16, hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
884 /* Offset 0x92 (SD0) */ \
885 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Format" }, \
886 /* Reserved: 0x94 - 0x98. */ \
887 /* Offset 0x98 (SD0) */ \
888 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
889 /* Offset 0x9C (SD0) */ \
890 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
891
892/** Defines a single audio stream register set (e.g. OSD0). */
893#define HDA_REG_MAP_DEF_STREAM(index, name) \
894 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
895
896/* See 302349 p 6.2. */
897static const struct HDAREGDESC
898{
899 /** Register offset in the register space. */
900 uint32_t offset;
901 /** Size in bytes. Registers of size > 4 are in fact tables. */
902 uint32_t size;
903 /** Readable bits. */
904 uint32_t readable;
905 /** Writable bits. */
906 uint32_t writable;
907 /** Read callback. */
908 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
909 /** Write callback. */
910 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
911 /** Index into the register storage array. */
912 uint32_t mem_idx;
913 /** Abbreviated name. */
914 const char *abbrev;
915 /** Descripton. */
916 const char *desc;
917} g_aHdaRegMap[HDA_NREGS] =
918
919{
920 /* offset size read mask write mask read callback write callback index + abbrev */
921 /*------- ------- ---------- ---------- ----------------------- ---------------------- ---------------- */
922 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
923 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
924 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
925 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
926 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
927 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
928 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
929 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , HDA_REG_IDX(STATESTS) }, /* State Change Status */
930 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
931 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
932 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
933 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
934 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
935 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
936 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
937 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
938 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
939 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
940 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
941 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
942 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
943 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
944 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
945 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
946 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
947 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
948 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
949 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
950 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
951 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
952 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
953 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
954 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
955 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
956 /* 4 Input Stream Descriptors (ISD). */
957 HDA_REG_MAP_DEF_STREAM(0, SD0),
958 HDA_REG_MAP_DEF_STREAM(1, SD1),
959 HDA_REG_MAP_DEF_STREAM(2, SD2),
960 HDA_REG_MAP_DEF_STREAM(3, SD3),
961 /* 4 Output Stream Descriptors (OSD). */
962 HDA_REG_MAP_DEF_STREAM(4, SD4),
963 HDA_REG_MAP_DEF_STREAM(5, SD5),
964 HDA_REG_MAP_DEF_STREAM(6, SD6),
965 HDA_REG_MAP_DEF_STREAM(7, SD7)
966};
967
968/**
969 * HDA register aliases (HDA spec 3.3.45).
970 * @remarks Sorted by offReg.
971 */
972static const struct
973{
974 /** The alias register offset. */
975 uint32_t offReg;
976 /** The register index. */
977 int idxAlias;
978} g_aHdaRegAliases[] =
979{
980 { 0x2084, HDA_REG_SD0LPIB },
981 { 0x20a4, HDA_REG_SD1LPIB },
982 { 0x20c4, HDA_REG_SD2LPIB },
983 { 0x20e4, HDA_REG_SD3LPIB },
984 { 0x2104, HDA_REG_SD4LPIB },
985 { 0x2124, HDA_REG_SD5LPIB },
986 { 0x2144, HDA_REG_SD6LPIB },
987 { 0x2164, HDA_REG_SD7LPIB },
988};
989
990#ifdef IN_RING3
991/** HDABDLESTATE field descriptors for the v5+ saved state. */
992static SSMFIELD const g_aSSMBDLEStateFields5[] =
993{
994 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
995 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
996 SSMFIELD_ENTRY(HDABDLESTATE, au8FIFO),
997 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
998 SSMFIELD_ENTRY_TERM()
999};
1000
1001/** HDASTREAMSTATE field descriptors for the v5+ saved state. */
1002static SSMFIELD const g_aSSMStreamStateFields5[] =
1003{
1004 SSMFIELD_ENTRY (HDASTREAMSTATE, cBDLE),
1005 SSMFIELD_ENTRY (HDASTREAMSTATE, uCurBDLE),
1006 SSMFIELD_ENTRY_IGNORE(HDASTREAMSTATE, paBDLE),
1007 SSMFIELD_ENTRY_TERM()
1008};
1009#endif
1010
1011/**
1012 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1013 */
1014static uint32_t const g_afMasks[5] =
1015{
1016 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1017};
1018
1019#ifdef IN_RING3
1020DECLINLINE(void) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t u32LPIB)
1021{
1022 AssertPtrReturnVoid(pThis);
1023 AssertPtrReturnVoid(pStrmSt);
1024
1025 Assert(u32LPIB <= pStrmSt->u32CBL);
1026
1027 LogFlowFunc(("uStrm=%RU8, LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1028 pStrmSt->u8Strm, u32LPIB, pThis->fDMAPosition));
1029
1030 /* Update LPIB in any case. */
1031 HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) = u32LPIB;
1032
1033 /* Do we need to tell the current DMA position? */
1034 if (pThis->fDMAPosition)
1035 {
1036 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1037 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStrmSt->u8Strm * 8),
1038 (void *)&u32LPIB, sizeof(uint32_t));
1039 AssertRC(rc2);
1040 }
1041}
1042#endif
1043
1044/**
1045 * Retrieves the number of bytes of a FIFOS register.
1046 *
1047 * @return Number of bytes of a given FIFOS register.
1048 */
1049DECLINLINE(uint16_t) hdaSDFIFOSToBytes(uint32_t u32RegFIFOS)
1050{
1051 uint16_t cb;
1052 switch (u32RegFIFOS)
1053 {
1054 /* Input */
1055 case HDA_SDINFIFO_120B: cb = 120; break;
1056 case HDA_SDINFIFO_160B: cb = 160; break;
1057
1058 /* Output */
1059 case HDA_SDONFIFO_16B: cb = 16; break;
1060 case HDA_SDONFIFO_32B: cb = 32; break;
1061 case HDA_SDONFIFO_64B: cb = 64; break;
1062 case HDA_SDONFIFO_128B: cb = 128; break;
1063 case HDA_SDONFIFO_192B: cb = 192; break;
1064 case HDA_SDONFIFO_256B: cb = 256; break;
1065 default:
1066 {
1067 cb = 0;
1068 AssertMsgFailed(("Wrong FIFO value\n"));
1069 break;
1070 }
1071 }
1072
1073 return cb;
1074}
1075
1076/**
1077 * Retrieves the number of bytes of a FIFOW register.
1078 *
1079 * @return Number of bytes of a given FIFOW register.
1080 */
1081DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1082{
1083 uint32_t cb;
1084 switch (u32RegFIFOW)
1085 {
1086 case HDA_SDFIFOW_8B: cb = 8; break;
1087 case HDA_SDFIFOW_16B: cb = 16; break;
1088 case HDA_SDFIFOW_32B: cb = 32; break;
1089 default: cb = 0; break;
1090 }
1091
1092#ifdef RT_STRICT
1093 Assert(RT_IS_POWER_OF_TWO(cb));
1094#endif
1095 return cb;
1096}
1097
1098#ifdef IN_RING3
1099/**
1100 * Returns the current BDLE to use for a stream.
1101 *
1102 * @return BDLE to use, NULL if none found.
1103 */
1104DECLINLINE(PHDABDLE) hdaStreamGetCurrentBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
1105{
1106 AssertPtrReturn(pThis, NULL);
1107 AssertPtrReturn(pStrmSt, NULL);
1108
1109 Assert(pStrmSt->State.paBDLE);
1110 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1111
1112 PHDABDLE pBDLE = &pStrmSt->State.paBDLE[pStrmSt->State.uCurBDLE];
1113 return pBDLE;
1114}
1115
1116/**
1117 * Returns the next BDLE to use for a stream.
1118 *
1119 * @return BDLE to use next, NULL if none found.
1120 */
1121DECLINLINE(PHDABDLE) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
1122{
1123 AssertPtrReturn(pThis, NULL);
1124 AssertPtrReturn(pStrmSt, NULL);
1125
1126 NOREF(pThis);
1127
1128 Assert(pStrmSt->State.paBDLE);
1129 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1130
1131#ifdef DEBUG
1132 uint32_t uOldBDLE = pStrmSt->State.uCurBDLE;
1133#endif
1134
1135 /*
1136 * Switch to the next BDLE entry and do a wrap around
1137 * if we reached the end of the Buffer Descriptor List (BDL).
1138 */
1139 pStrmSt->State.uCurBDLE++;
1140 if (pStrmSt->State.uCurBDLE == pStrmSt->State.cBDLE)
1141 {
1142 pStrmSt->State.uCurBDLE = 0;
1143
1144 hdaStreamUpdateLPIB(pThis, pStrmSt, 0);
1145 }
1146
1147 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1148
1149 PHDABDLE pBDLE = &pStrmSt->State.paBDLE[pStrmSt->State.uCurBDLE];
1150 AssertPtr(pBDLE);
1151
1152 hdaBDLEReset(pBDLE);
1153
1154#ifdef DEBUG
1155 LogFlowFunc(("uOldBDLE=%RU16, uCurBDLE=%RU16, cBDLE=%RU32, %R[bdle]\n",
1156 uOldBDLE, pStrmSt->State.uCurBDLE, pStrmSt->State.cBDLE, pBDLE));
1157#endif
1158 return pBDLE;
1159}
1160#endif
1161
1162/**
1163 * Retrieves the minimum number of bytes accumulated/free in the
1164 * FIFO before the controller will start a fetch/eviction of data.
1165 *
1166 * Uses SDFIFOW (FIFO Watermark Register).
1167 *
1168 * @return Number of bytes accumulated/free in the FIFO.
1169 */
1170DECLINLINE(uint8_t) hdaStreamGetFIFOW(PHDASTATE pThis, PHDASTREAM pStrmSt)
1171{
1172 AssertPtrReturn(pThis, 0);
1173 AssertPtrReturn(pStrmSt, 0);
1174
1175#ifdef VBOX_HDA_WITH_FIFO
1176 return hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, pStrmSt->u8Strm));
1177#else
1178 return 0;
1179#endif
1180}
1181
1182static int hdaProcessInterrupt(PHDASTATE pThis)
1183{
1184#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1185 ( INTCTL_SX((pThis), num) \
1186 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1187
1188 bool fIrq = false;
1189
1190 if (/* Controller Interrupt Enable (CIE). */
1191 HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1192 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1193 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1194 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1195 fIrq = true;
1196
1197 /** @todo Don't hardcode stream numbers here. */
1198 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1199 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1200 {
1201#ifdef IN_RING3
1202 LogFunc(("BCIS\n"));
1203#endif
1204 fIrq = true;
1205 }
1206
1207 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1208 {
1209 LogFunc(("%s\n", fIrq ? "Asserted" : "Deasserted"));
1210 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1211 }
1212
1213#undef IS_INTERRUPT_OCCURED_AND_ENABLED
1214
1215 return VINF_SUCCESS;
1216}
1217
1218/**
1219 * Looks up a register at the exact offset given by @a offReg.
1220 *
1221 * @returns Register index on success, -1 if not found.
1222 * @param pThis The HDA device state.
1223 * @param offReg The register offset.
1224 */
1225static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1226{
1227 /*
1228 * Aliases.
1229 */
1230 if (offReg >= g_aHdaRegAliases[0].offReg)
1231 {
1232 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1233 if (offReg == g_aHdaRegAliases[i].offReg)
1234 return g_aHdaRegAliases[i].idxAlias;
1235 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1236 return -1;
1237 }
1238
1239 /*
1240 * Binary search the
1241 */
1242 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1243 int idxLow = 0;
1244 for (;;)
1245 {
1246 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1247 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1248 {
1249 if (idxLow == idxMiddle)
1250 break;
1251 idxEnd = idxMiddle;
1252 }
1253 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1254 {
1255 idxLow = idxMiddle + 1;
1256 if (idxLow >= idxEnd)
1257 break;
1258 }
1259 else
1260 return idxMiddle;
1261 }
1262
1263#ifdef RT_STRICT
1264 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1265 Assert(g_aHdaRegMap[i].offset != offReg);
1266#endif
1267 return -1;
1268}
1269
1270/**
1271 * Looks up a register covering the offset given by @a offReg.
1272 *
1273 * @returns Register index on success, -1 if not found.
1274 * @param pThis The HDA device state.
1275 * @param offReg The register offset.
1276 */
1277static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1278{
1279 /*
1280 * Aliases.
1281 */
1282 if (offReg >= g_aHdaRegAliases[0].offReg)
1283 {
1284 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1285 {
1286 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1287 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1288 return g_aHdaRegAliases[i].idxAlias;
1289 }
1290 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1291 return -1;
1292 }
1293
1294 /*
1295 * Binary search the register map.
1296 */
1297 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1298 int idxLow = 0;
1299 for (;;)
1300 {
1301 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1302 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1303 {
1304 if (idxLow == idxMiddle)
1305 break;
1306 idxEnd = idxMiddle;
1307 }
1308 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1309 {
1310 idxLow = idxMiddle + 1;
1311 if (idxLow >= idxEnd)
1312 break;
1313 }
1314 else
1315 return idxMiddle;
1316 }
1317
1318#ifdef RT_STRICT
1319 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1320 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1321#endif
1322 return -1;
1323}
1324
1325#ifdef IN_RING3
1326static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1327{
1328 int rc = VINF_SUCCESS;
1329 if (fLocal)
1330 {
1331 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1332 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1333 if (RT_FAILURE(rc))
1334 AssertRCReturn(rc, rc);
1335#ifdef DEBUG_CMD_BUFFER
1336 uint8_t i = 0;
1337 do
1338 {
1339 LogFunc(("CORB%02x: ", i));
1340 uint8_t j = 0;
1341 do
1342 {
1343 const char *pszPrefix;
1344 if ((i + j) == HDA_REG(pThis, CORBRP));
1345 pszPrefix = "[R]";
1346 else if ((i + j) == HDA_REG(pThis, CORBWP));
1347 pszPrefix = "[W]";
1348 else
1349 pszPrefix = " "; /* three spaces */
1350 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1351 j++;
1352 } while (j < 8);
1353 LogFunc(("\n"));
1354 i += 8;
1355 } while(i != 0);
1356#endif
1357 }
1358 else
1359 {
1360 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1361 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1362 if (RT_FAILURE(rc))
1363 AssertRCReturn(rc, rc);
1364#ifdef DEBUG_CMD_BUFFER
1365 uint8_t i = 0;
1366 do {
1367 LogFunc(("RIRB%02x: ", i));
1368 uint8_t j = 0;
1369 do {
1370 const char *prefix;
1371 if ((i + j) == HDA_REG(pThis, RIRBWP))
1372 prefix = "[W]";
1373 else
1374 prefix = " ";
1375 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1376 } while (++j < 8);
1377 LogFunc(("\n"));
1378 i += 8;
1379 } while (i != 0);
1380#endif
1381 }
1382 return rc;
1383}
1384
1385static int hdaCORBCmdProcess(PHDASTATE pThis)
1386{
1387 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1388
1389 int rc = hdaCmdSync(pThis, true);
1390 if (RT_FAILURE(rc))
1391 AssertRCReturn(rc, rc);
1392
1393 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1394 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1395 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1396
1397 Assert((corbWp != corbRp));
1398 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1399
1400 while (corbRp != corbWp)
1401 {
1402 uint32_t cmd;
1403 uint64_t resp;
1404 pfn = NULL;
1405 corbRp++;
1406 cmd = pThis->pu32CorbBuf[corbRp];
1407
1408 rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* Codec index */), &pfn);
1409 if (RT_SUCCESS(rc))
1410 {
1411 AssertPtr(pfn);
1412 rc = pfn(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1413 }
1414
1415 if (RT_FAILURE(rc))
1416 AssertRCReturn(rc, rc);
1417 (rirbWp)++;
1418
1419 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1420 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1421 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1422 {
1423 LogFunc(("unexpected unsolicited response.\n"));
1424 HDA_REG(pThis, CORBRP) = corbRp;
1425 return rc;
1426 }
1427
1428 pThis->pu64RirbBuf[rirbWp] = resp;
1429
1430 pThis->u8RespIntCnt++;
1431 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1432 break;
1433 }
1434 HDA_REG(pThis, CORBRP) = corbRp;
1435 HDA_REG(pThis, RIRBWP) = rirbWp;
1436 rc = hdaCmdSync(pThis, false);
1437 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1438 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1439 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1440 {
1441 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1442
1443 pThis->u8RespIntCnt = 0;
1444 rc = hdaProcessInterrupt(pThis);
1445 }
1446 if (RT_FAILURE(rc))
1447 AssertRCReturn(rc, rc);
1448 return rc;
1449}
1450
1451static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1452{
1453 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1454 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1455
1456 pStrmSt->u8Strm = u8Strm;
1457 pStrmSt->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
1458 HDA_STREAM_REG(pThis, BDPU, u8Strm));
1459 pStrmSt->u16LVI = HDA_STREAM_REG(pThis, LVI, u8Strm);
1460 pStrmSt->u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1461 pStrmSt->u16FIFOS = hdaSDFIFOSToBytes(HDA_STREAM_REG(pThis, FIFOS, u8Strm));
1462
1463 hdaStreamDestroy(pStrmSt);
1464
1465 int rc = VINF_SUCCESS;
1466
1467 if (pStrmSt->u16LVI) /* Any BDLEs to fetch? */
1468 {
1469 uint32_t cbBDLE = 0;
1470
1471 pStrmSt->State.cBDLE = pStrmSt->u16LVI + 1; /* See 18.2.37: If LVI is n, then there are n + 1 entries. */
1472 pStrmSt->State.paBDLE = (PHDABDLE)RTMemAllocZ(sizeof(HDABDLE) * pStrmSt->State.cBDLE);
1473 if (pStrmSt->State.paBDLE)
1474 {
1475 for (uint16_t i = 0; i < pStrmSt->State.cBDLE; i++)
1476 {
1477 rc = hdaBDLEFetch(pThis, &pStrmSt->State.paBDLE[i], pStrmSt->u64BaseDMA, i);
1478 if (RT_FAILURE(rc))
1479 break;
1480
1481 cbBDLE += pStrmSt->State.paBDLE[i].u32BufSize;
1482 }
1483
1484#ifdef DEBUG
1485 hdaBDLEDumpAll(pThis, pStrmSt->u64BaseDMA, pStrmSt->State.cBDLE);
1486#endif
1487 if (RT_SUCCESS(rc))
1488 {
1489 if (pStrmSt->u32CBL != cbBDLE)
1490 LogRel(("HDA: Warning: CBL (%RU32) does not match BDL entries (%RU32); expect sound hickups\n",
1491 pStrmSt->u32CBL, cbBDLE));
1492
1493 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1494 }
1495 }
1496 else
1497 rc = VERR_NO_MEMORY;
1498 }
1499
1500 LogFunc(("[SD%RU8]: DMA=0x%x, LVI=%RU16, CBL=%RU32, FIFOS=%RU16\n",
1501 u8Strm, pStrmSt->u64BaseDMA, pStrmSt->u16LVI, pStrmSt->u32CBL, pStrmSt->u16FIFOS));
1502
1503 return rc;
1504}
1505
1506static void hdaStreamDestroy(PHDASTREAM pStrmSt)
1507{
1508 AssertPtrReturnVoid(pStrmSt);
1509
1510 if (pStrmSt->State.paBDLE)
1511 {
1512 Assert(pStrmSt->State.cBDLE);
1513 RTMemFree(pStrmSt->State.paBDLE);
1514 pStrmSt->State.paBDLE = NULL;
1515 }
1516
1517 pStrmSt->State.cBDLE = 0;
1518}
1519#endif
1520
1521static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1522{
1523 AssertPtrReturnVoid(pThis);
1524 AssertPtrReturnVoid(pStrmSt);
1525 AssertReturnVoid(u8Strm <= 7); /** @todo Use a define for MAX_STREAMS! */
1526
1527 /*
1528 * Initialize stream state.
1529 */
1530 RT_BZERO(pStrmSt, sizeof(HDASTREAM));
1531
1532 /*
1533 * Initialize registers.
1534 */
1535 HDA_STREAM_REG(pThis, STS, u8Strm) = 0;
1536 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1537 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1538 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1539
1540 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39. */
1541 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1542 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1543 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = HDA_SDFIFOW_32B;
1544 HDA_STREAM_REG(pThis, LPIB, u8Strm) = 0;
1545 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1546 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1547 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1548 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1549 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1550
1551 LogFunc(("[SD%RU8] Reset\n", u8Strm));
1552}
1553
1554/* Register access handlers. */
1555
1556static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1557{
1558 *pu32Value = 0;
1559 return VINF_SUCCESS;
1560}
1561
1562static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1563{
1564 return VINF_SUCCESS;
1565}
1566
1567/* U8 */
1568static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1569{
1570 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1571 return hdaRegReadU32(pThis, iReg, pu32Value);
1572}
1573
1574static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1575{
1576 Assert((u32Value & 0xffffff00) == 0);
1577 return hdaRegWriteU32(pThis, iReg, u32Value);
1578}
1579
1580/* U16 */
1581static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1582{
1583 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1584 return hdaRegReadU32(pThis, iReg, pu32Value);
1585}
1586
1587static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1588{
1589 Assert((u32Value & 0xffff0000) == 0);
1590 return hdaRegWriteU32(pThis, iReg, u32Value);
1591}
1592
1593/* U24 */
1594static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1595{
1596 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1597 return hdaRegReadU32(pThis, iReg, pu32Value);
1598}
1599
1600static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1601{
1602 Assert((u32Value & 0xff000000) == 0);
1603 return hdaRegWriteU32(pThis, iReg, u32Value);
1604}
1605
1606/* U32 */
1607static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1608{
1609 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1610
1611 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1612 return VINF_SUCCESS;
1613}
1614
1615static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1616{
1617 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1618
1619 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1620 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1621 return VINF_SUCCESS;
1622}
1623
1624static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1625{
1626 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1627 {
1628 /* Exit reset state. */
1629 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1630 pThis->fInReset = false;
1631 }
1632 else
1633 {
1634#ifdef IN_RING3
1635 /* Enter reset state. */
1636 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1637 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1638 {
1639 LogFunc(("HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1640 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1641 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1642 }
1643 hdaReset(pThis->CTX_SUFF(pDevIns));
1644 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1645 pThis->fInReset = true;
1646#else
1647 return VINF_IOM_R3_MMIO_WRITE;
1648#endif
1649 }
1650 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1651 {
1652 /* Flush: GSTS:1 set, see 6.2.6. */
1653 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
1654 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1655 }
1656 return VINF_SUCCESS;
1657}
1658
1659static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1660{
1661 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1662
1663 uint32_t v = pThis->au32Regs[iRegMem];
1664 uint32_t nv = u32Value & HDA_STATES_SCSF;
1665 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1666 return VINF_SUCCESS;
1667}
1668
1669static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1670{
1671 uint32_t v = 0;
1672 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1673 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1674 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1675 || HDA_REG(pThis, STATESTS))
1676 {
1677 v |= RT_BIT(30); /* Touch CIS. */
1678 }
1679
1680#define HDA_IS_STREAM_EVENT(pThis, num) \
1681 ( (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1682 || (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1683 || (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1684
1685#define HDA_MARK_STREAM(pThis, num, v) \
1686 do { (v) |= HDA_IS_STREAM_EVENT((pThis), num) ? RT_BIT((num)) : 0; } while(0)
1687
1688 HDA_MARK_STREAM(pThis, 0, v);
1689 HDA_MARK_STREAM(pThis, 1, v);
1690 HDA_MARK_STREAM(pThis, 2, v);
1691 HDA_MARK_STREAM(pThis, 3, v);
1692 HDA_MARK_STREAM(pThis, 4, v);
1693 HDA_MARK_STREAM(pThis, 5, v);
1694 HDA_MARK_STREAM(pThis, 6, v);
1695 HDA_MARK_STREAM(pThis, 7, v);
1696
1697#undef HDA_IS_STREAM_EVENT
1698#undef HDA_MARK_STREAM
1699
1700 v |= v ? RT_BIT(31) : 0;
1701
1702 *pu32Value = v;
1703 return VINF_SUCCESS;
1704}
1705
1706static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1707{
1708 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1709 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1710 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1711
1712 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
1713
1714 *pu32Value = u32LPIB;
1715 return VINF_SUCCESS;
1716}
1717
1718static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1719{
1720 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1721 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1722 - pThis->u64BaseTS, 24, 1000);
1723 LogFlowFunc(("%RU32\n", *pu32Value));
1724 return VINF_SUCCESS;
1725}
1726
1727static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1728{
1729 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1730 {
1731 HDA_REG(pThis, CORBRP) = 0;
1732 }
1733#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1734 else
1735 return hdaRegWriteU8(pThis, iReg, u32Value);
1736#endif
1737 return VINF_SUCCESS;
1738}
1739
1740static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1741{
1742#ifdef IN_RING3
1743 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1744 AssertRC(rc);
1745 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1746 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1747 {
1748 return hdaCORBCmdProcess(pThis);
1749 }
1750 return rc;
1751#else
1752 return VINF_IOM_R3_MMIO_WRITE;
1753#endif
1754}
1755
1756static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1757{
1758 uint32_t v = HDA_REG(pThis, CORBSTS);
1759 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1760 return VINF_SUCCESS;
1761}
1762
1763static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1764{
1765#ifdef IN_RING3
1766 int rc;
1767 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1768 if (RT_FAILURE(rc))
1769 AssertRCReturn(rc, rc);
1770 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1771 return VINF_SUCCESS;
1772 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1773 return VINF_SUCCESS;
1774 rc = hdaCORBCmdProcess(pThis);
1775 return rc;
1776#else
1777 return VINF_IOM_R3_MMIO_WRITE;
1778#endif
1779}
1780
1781static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1782{
1783 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CBL, iReg);
1784 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1785
1786 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32Value));
1787
1788 return hdaRegWriteU32(pThis, iReg, u32Value);
1789}
1790
1791static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1792{
1793 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1794 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1795 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1796 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1797
1798 uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1799
1800 PHDASTREAM pStrmSt;
1801 switch (u8Strm)
1802 {
1803 case 0: /** @todo Use dynamic indices, based on stream assignment. */
1804 {
1805 pStrmSt = &pThis->StrmStLineIn;
1806 break;
1807 }
1808# ifdef VBOX_WITH_HDA_MIC_IN
1809 case 2: /** @todo Use dynamic indices, based on stream assignment. */
1810 {
1811 pStrmSt = &pThis->StrmStMicIn;
1812 break;
1813 }
1814# endif
1815 case 4: /** @todo Use dynamic indices, based on stream assignment. */
1816 {
1817 pStrmSt = &pThis->StrmStOut;
1818 break;
1819 }
1820
1821 default:
1822 {
1823 LogFunc(("Warning: Changing SDCTL on non-attached stream (iReg=0x%x)\n", iReg));
1824 return hdaRegWriteU24(pThis, iReg, u32Value); /* Write 3 bytes. */
1825 }
1826 }
1827
1828 LogFunc(("[SD%RU8]: %R[sdctl]\n", u8Strm, u32Value));
1829
1830 if (fInReset)
1831 {
1832 /* Guest is resetting HDA's stream, we're expecting guest will mark stream as exit. */
1833 Assert(!fReset);
1834 LogFunc(("Guest initiated exit of stream reset\n"));
1835 }
1836 else if (fReset)
1837 {
1838#ifdef IN_RING3
1839 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1840 Assert(!fInRun && !fRun);
1841
1842 LogFunc(("Guest initiated enter to stream reset\n"));
1843 hdaStreamReset(pThis, pStrmSt, u8Strm);
1844#else
1845 return VINF_IOM_R3_MMIO_WRITE;
1846#endif
1847 }
1848 else
1849 {
1850#ifdef IN_RING3
1851 /*
1852 * We enter here to change DMA states only.
1853 */
1854 if (fInRun != fRun)
1855 {
1856 Assert(!fReset && !fInReset);
1857
1858 PHDADRIVER pDrv;
1859 switch (u8Strm)
1860 {
1861 case 0: /** @todo Use a variable here. Later. */
1862 {
1863 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1864 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1865 pDrv->LineIn.pStrmIn, fRun);
1866 break;
1867 }
1868# ifdef VBOX_WITH_HDA_MIC_IN
1869 case 2: /** @todo Use a variable here. Later. */
1870 {
1871 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1872 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1873 pDrv->MicIn.pStrmIn, fRun);
1874 break;
1875 }
1876# endif
1877 case 4: /** @todo Use a variable here. Later. */
1878 {
1879 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1880 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1881 pDrv->Out.pStrmOut, fRun);
1882 break;
1883 }
1884 default:
1885 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1886 break;
1887 }
1888 }
1889
1890 if (pStrmSt)
1891 {
1892 int rc2 = hdaStreamInit(pThis, pStrmSt, u8Strm);
1893 AssertRC(rc2);
1894 }
1895
1896#else /* !IN_RING3 */
1897 return VINF_IOM_R3_MMIO_WRITE;
1898#endif /* IN_RING3 */
1899 }
1900
1901 return hdaRegWriteU24(pThis, iReg, u32Value);
1902}
1903
1904static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1905{
1906 uint32_t v = HDA_REG_IND(pThis, iReg);
1907 v &= ~(u32Value & v);
1908 HDA_REG_IND(pThis, iReg) = v;
1909 hdaProcessInterrupt(pThis);
1910 return VINF_SUCCESS;
1911}
1912
1913static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1914{
1915 /* Only can be modified if RUN bit is 0. */
1916 bool fIsRunning = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1917 if (fIsRunning)
1918 {
1919 AssertMsgFailed(("Cannot write to register when RUN bit is set\n"));
1920 return VINF_SUCCESS;
1921 }
1922
1923 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1924 if (RT_FAILURE(rc))
1925 AssertRCReturn(rc, VINF_SUCCESS);
1926 return rc;
1927}
1928
1929static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1930{
1931 switch (u32Value)
1932 {
1933 case HDA_SDFIFOW_8B:
1934 case HDA_SDFIFOW_16B:
1935 case HDA_SDFIFOW_32B:
1936 return hdaRegWriteU16(pThis, iReg, u32Value);
1937 default:
1938 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1939 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1940 }
1941 return VINF_SUCCESS; /* Never reached. */
1942}
1943
1944/**
1945 * @note This method could be called for changing value on Output Streams
1946 * only (ICH6 datasheet 18.2.39).
1947 */
1948static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1949{
1950 /** @todo Only allow updating FIFOS if RUN bit is 0? */
1951 uint32_t u32FIFOS = 0;
1952
1953 switch (iReg)
1954 {
1955 /* SDInFIFOS is RO, n=0-3. */
1956 case HDA_REG_SD0FIFOS:
1957 case HDA_REG_SD1FIFOS:
1958 case HDA_REG_SD2FIFOS:
1959 case HDA_REG_SD3FIFOS:
1960 {
1961 LogFunc(("Guest tries to change R/O value of FIFO size of input stream, ignoring\n"));
1962 break;
1963 }
1964 case HDA_REG_SD4FIFOS:
1965 case HDA_REG_SD5FIFOS:
1966 case HDA_REG_SD6FIFOS:
1967 case HDA_REG_SD7FIFOS:
1968 {
1969 switch(u32Value)
1970 {
1971 case HDA_SDONFIFO_16B:
1972 case HDA_SDONFIFO_32B:
1973 case HDA_SDONFIFO_64B:
1974 case HDA_SDONFIFO_128B:
1975 case HDA_SDONFIFO_192B:
1976 u32FIFOS = u32Value;
1977 break;
1978
1979 case HDA_SDONFIFO_256B: /** @todo r=andy Investigate this. */
1980 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1981 /* Fall through is intentional. */
1982 default:
1983 u32FIFOS = HDA_SDONFIFO_192B;
1984 break;
1985 }
1986
1987 break;
1988 }
1989 default:
1990 {
1991 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
1992 break;
1993 }
1994 }
1995
1996 if (u32FIFOS)
1997 {
1998 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", 0, hdaSDFIFOSToBytes(u32FIFOS)));
1999 /** @todo Update internal stream state with new FIFOS. */
2000
2001 return hdaRegWriteU16(pThis, iReg, u32FIFOS);
2002 }
2003
2004 return VINF_SUCCESS;
2005}
2006
2007#ifdef IN_RING3
2008static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
2009{
2010 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2011
2012# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2013
2014 int rc = VINF_SUCCESS;
2015
2016 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
2017 uint32_t u32HzMult = 1;
2018 uint32_t u32HzDiv = 1;
2019
2020 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2021 {
2022 case 0: u32HzMult = 1; break;
2023 case 1: u32HzMult = 2; break;
2024 case 2: u32HzMult = 3; break;
2025 case 3: u32HzMult = 4; break;
2026 default:
2027 LogFunc(("Unsupported multiplier %x\n",
2028 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2029 rc = VERR_NOT_SUPPORTED;
2030 break;
2031 }
2032 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2033 {
2034 case 0: u32HzDiv = 1; break;
2035 case 1: u32HzDiv = 2; break;
2036 case 2: u32HzDiv = 3; break;
2037 case 3: u32HzDiv = 4; break;
2038 case 4: u32HzDiv = 5; break;
2039 case 5: u32HzDiv = 6; break;
2040 case 6: u32HzDiv = 7; break;
2041 case 7: u32HzDiv = 8; break;
2042 default:
2043 LogFunc(("Unsupported divisor %x\n",
2044 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2045 rc = VERR_NOT_SUPPORTED;
2046 break;
2047 }
2048
2049 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
2050 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2051 {
2052 case 0:
2053 LogFunc(("Requested 8-bit\n"));
2054 enmFmt = AUD_FMT_S8;
2055 break;
2056 case 1:
2057 LogFunc(("Requested 16-bit\n"));
2058 enmFmt = AUD_FMT_S16;
2059 break;
2060 case 2:
2061 LogFunc(("Requested 20-bit\n"));
2062 break;
2063 case 3:
2064 LogFunc(("Requested 24-bit\n"));
2065 break;
2066 case 4:
2067 LogFunc(("Requested 32-bit\n"));
2068 enmFmt = AUD_FMT_S32;
2069 break;
2070 default:
2071 AssertMsgFailed(("Unsupported bits shift %x\n",
2072 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2073 rc = VERR_NOT_SUPPORTED;
2074 break;
2075 }
2076
2077 if (RT_SUCCESS(rc))
2078 {
2079 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2080 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
2081 pCfg->enmFormat = enmFmt;
2082 pCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2083 }
2084
2085# undef EXTRACT_VALUE
2086
2087 LogFlowFuncLeaveRC(rc);
2088 return rc;
2089}
2090#endif
2091
2092static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2093{
2094#ifdef IN_RING3
2095# ifdef VBOX_WITH_HDA_CODEC_EMU
2096 /* No reason to re-open stream with same settings. */
2097 if (u32Value == HDA_REG_IND(pThis, iReg))
2098 return VINF_SUCCESS;
2099
2100 PDMAUDIOSTREAMCFG as;
2101 int rc = hdaSdFmtToAudSettings(u32Value, &as);
2102 if (RT_FAILURE(rc))
2103 return rc;
2104
2105 PHDADRIVER pDrv;
2106 switch (iReg)
2107 {
2108 case HDA_REG_SD0FMT:
2109 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2110 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &as);
2111 break;
2112# ifdef VBOX_WITH_HDA_MIC_IN
2113 case HDA_REG_SD2FMT:
2114 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2115 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &as);
2116 break;
2117# endif
2118 default:
2119 LogFunc(("Warning: Attempt to change format on register %RU32\n", iReg));
2120 break;
2121 }
2122
2123 /** @todo r=andy rc gets lost; needs fixing. */
2124 return hdaRegWriteU16(pThis, iReg, u32Value);
2125# else /* !VBOX_WITH_HDA_CODEC_EMU */
2126 return hdaRegWriteU16(pThis, iReg, u32Value);
2127# endif
2128#else /* !IN_RING3 */
2129 return VINF_IOM_R3_MMIO_WRITE;
2130#endif
2131}
2132
2133static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2134{
2135 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2136 if (RT_FAILURE(rc))
2137 AssertRCReturn(rc, VINF_SUCCESS);
2138 return rc;
2139}
2140
2141static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2142{
2143 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2144 if (RT_FAILURE(rc))
2145 AssertRCReturn(rc, VINF_SUCCESS);
2146 return rc;
2147}
2148
2149static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2150{
2151 int rc = VINF_SUCCESS;
2152 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2153 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2154 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2155 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2156
2157 rc = hdaRegReadU32(pThis, iReg, pu32Value);
2158 return rc;
2159}
2160
2161static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2162{
2163 int rc = VINF_SUCCESS;
2164
2165 /*
2166 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2167 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2168 */
2169 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
2170 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
2171 {
2172#ifdef IN_RING3
2173 PFNHDACODECVERBPROCESSOR pfn = NULL;
2174 uint64_t resp;
2175 uint32_t cmd = HDA_REG(pThis, IC);
2176 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2177 {
2178 /*
2179 * 3.4.3 defines behavior of immediate Command status register.
2180 */
2181 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
2182 return rc;
2183 }
2184 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2185 LogFunc(("IC:%x\n", cmd));
2186
2187 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
2188 HDA_CODEC_CMD(cmd, 0 /* LUN */),
2189 &pfn);
2190 if (RT_FAILURE(rc))
2191 AssertRCReturn(rc, rc);
2192 rc = pfn(pThis->pCodec,
2193 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
2194 if (RT_FAILURE(rc))
2195 AssertRCReturn(rc, rc);
2196
2197 HDA_REG(pThis, IR) = (uint32_t)resp;
2198 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
2199 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
2200 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
2201#else /* !IN_RING3 */
2202 rc = VINF_IOM_R3_MMIO_WRITE;
2203#endif
2204 return rc;
2205 }
2206 /*
2207 * Once the guest read the response, it should clean the IRV bit of the IRS register.
2208 */
2209 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
2210 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
2211 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
2212 return rc;
2213}
2214
2215static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2216{
2217 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
2218 {
2219 HDA_REG(pThis, RIRBWP) = 0;
2220 }
2221 /* The remaining bits are O, see 6.2.22 */
2222 return VINF_SUCCESS;
2223}
2224
2225static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2226{
2227 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2228 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2229 if (RT_FAILURE(rc))
2230 AssertRCReturn(rc, rc);
2231
2232 switch(iReg)
2233 {
2234 case HDA_REG_CORBLBASE:
2235 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2236 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
2237 break;
2238 case HDA_REG_CORBUBASE:
2239 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2240 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2241 break;
2242 case HDA_REG_RIRBLBASE:
2243 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2244 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
2245 break;
2246 case HDA_REG_RIRBUBASE:
2247 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2248 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2249 break;
2250 case HDA_REG_DPLBASE:
2251 {
2252 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
2253 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
2254
2255 /* Also make sure to handle the DMA position enable bit. */
2256 bool fEnabled = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2257 if (pThis->fDMAPosition != fEnabled)
2258 {
2259 LogRel(("HDA: %s DMA position buffer\n", fEnabled ? "Enabled" : "Disabled"));
2260 pThis->fDMAPosition = fEnabled;
2261 }
2262 break;
2263 }
2264 case HDA_REG_DPUBASE:
2265 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
2266 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2267 break;
2268 default:
2269 AssertMsgFailed(("Invalid index\n"));
2270 break;
2271 }
2272
2273 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2274 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2275 return rc;
2276}
2277
2278static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2279{
2280 uint8_t v = HDA_REG(pThis, RIRBSTS);
2281 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2282
2283 return hdaProcessInterrupt(pThis);
2284}
2285
2286#ifdef IN_RING3
2287#ifdef LOG_ENABLED
2288static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE)
2289{
2290 uint32_t cbBDLE = 0;
2291
2292 for (uint16_t i = 0; i < cBDLE; i++)
2293 {
2294 uint8_t bdle[16]; /** @todo Use a define. */
2295 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * 16, bdle, 16); /** @todo Use a define. */
2296
2297 uint64_t addr = *(uint64_t *)bdle;
2298 uint32_t len = *(uint32_t *)&bdle[8];
2299 uint32_t ioc = *(uint32_t *)&bdle[12];
2300
2301 LogFlowFunc(("#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
2302 i, addr, len, RT_BOOL(ioc & 0x1)));
2303
2304 cbBDLE += len;
2305 }
2306
2307 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
2308
2309 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
2310 return;
2311
2312 for (int i = 0; i < 8; i++) /** @todo Use a define for MAX_STREAMS! */
2313 {
2314 uint32_t uDMACnt;
2315 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i * 8, /** @todo Use a define. */
2316 &uDMACnt, sizeof(&uDMACnt));
2317
2318 LogFlowFunc(("%s #%02d STREAM(0x%x)\n",
2319 i == HDA_SDCTL_NUM(pThis, 4) || i == HDA_SDCTL_NUM(pThis, 0) ? "*" : " ", i , uDMACnt));
2320 }
2321}
2322#endif
2323
2324/**
2325 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
2326 *
2327 * @param pThis Pointer to HDA state.
2328 * @param pBDLE Where to store the fetched result.
2329 * @param u64BaseDMA Address base of DMA engine to use.
2330 * @param u16Entry BDLE entry to fetch.
2331 */
2332static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
2333{
2334 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2335 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
2336 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
2337 /** @todo Compare u16Entry with LVI. */
2338
2339 uint8_t uBundleEntry[16]; /** @todo Define a BDLE length. */
2340 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * 16, /** @todo Define a BDLE length. */
2341 uBundleEntry, RT_ELEMENTS(uBundleEntry));
2342 if (RT_FAILURE(rc))
2343 return rc;
2344
2345 pBDLE->State.u32BDLIndex = u16Entry;
2346 pBDLE->u64BufAdr = *(uint64_t *) uBundleEntry;
2347 pBDLE->u32BufSize = *(uint32_t *)&uBundleEntry[8];
2348 if (pBDLE->u32BufSize < sizeof(uint16_t)) /* Must be at least one word. */
2349 return VERR_INVALID_STATE;
2350
2351 pBDLE->fIntOnCompletion = (*(uint32_t *)&uBundleEntry[12]) & 0x1;
2352
2353 return VINF_SUCCESS;
2354}
2355
2356static void hdaBDLEReset(PHDABDLE pBDLE)
2357{
2358 AssertPtrReturnVoid(pBDLE);
2359
2360 pBDLE->State.u32BufOff = 0;
2361 pBDLE->State.cbBelowFIFOW = 0;
2362}
2363
2364/**
2365 * Returns the number of outstanding stream data bytes which need to be processed
2366 * by the DMA engine assigned to this stream.
2367 *
2368 * @return Number of bytes for the DMA engine to process.
2369 */
2370DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbMax)
2371{
2372 AssertPtrReturn(pThis, 0);
2373 AssertPtrReturn(pStrmSt, 0);
2374
2375 if (!cbMax)
2376 return 0;
2377
2378 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2379
2380 uint32_t cbFree = pStrmSt->u32CBL - HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2381 if (cbFree)
2382 {
2383 /* Limit to the available free space of the current BDLE. */
2384 cbFree = RT_MIN(cbFree, pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2385
2386 /* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
2387 cbFree = RT_MIN(cbFree, pStrmSt->u16FIFOS);
2388
2389 /* Make sure we only transfer as many bytes as requested. */
2390 cbFree = RT_MIN(cbFree, cbMax);
2391
2392 if (pBDLE->State.cbBelowFIFOW)
2393 {
2394 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
2395 * No need to read data from DMA then. */
2396 if (cbFree > pBDLE->State.cbBelowFIFOW)
2397 {
2398 /* Subtract the amount of bytes that still would fit in the stream's FIFO
2399 * and therefore do not need to be processed by DMA. */
2400 cbFree -= pBDLE->State.cbBelowFIFOW;
2401 }
2402 }
2403 }
2404
2405 LogFlowFunc(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, cbFree=%RU32, %R[bdle]\n", pStrmSt->u8Strm,
2406 pStrmSt->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), cbFree, pBDLE));
2407 return cbFree;
2408}
2409
2410DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
2411{
2412 AssertPtrReturnVoid(pBDLE);
2413
2414 if (!cbData || !cbProcessed)
2415 return;
2416
2417 /* Fewer than cbBelowFIFOW bytes were copied.
2418 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2419 * where it might happen. */
2420 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
2421 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
2422 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
2423
2424#if 0
2425 if ( pBDLE->State.cbBelowFIFOW
2426 && pBDLE->State.cbBelowFIFOW <= cbWritten)
2427 {
2428 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
2429 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->u32BufSize));
2430 }
2431#endif
2432
2433 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
2434 Assert(pBDLE->State.cbBelowFIFOW == 0);
2435
2436 /* We always increment the position of DMA buffer counter because we're always reading
2437 * into an intermediate buffer. */
2438 pBDLE->State.u32BufOff += cbData;
2439 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2440
2441 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
2442}
2443
2444DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
2445{
2446 AssertPtrReturn(pThis, false);
2447 AssertPtrReturn(pStrmSt, false);
2448
2449 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2450 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2451
2452 /* Did we reach the CBL (Cyclic Buffer List) limit? */
2453 bool fCBLLimitReached = u32LPIB >= pStrmSt->u32CBL;
2454
2455 /* Do we need to use the next BDLE entry? Either because we reached
2456 * the CBL limit or our internal DMA buffer is full. */
2457 bool fNeedsNextBDLE = ( fCBLLimitReached
2458 || ( pBDLE->State.u32BufOff
2459 && pBDLE->State.u32BufOff >= pBDLE->u32BufSize)
2460 );
2461
2462 Assert(u32LPIB <= pStrmSt->u32CBL);
2463 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2464
2465 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
2466 pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
2467
2468 if (fCBLLimitReached)
2469 {
2470 /* Reset LPIB register. */
2471 u32LPIB -= RT_MIN(u32LPIB, pStrmSt->u32CBL);
2472 hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2473 }
2474
2475 if (fNeedsNextBDLE)
2476 {
2477 /* Reset current BDLE. */
2478 hdaBDLEReset(pBDLE);
2479 }
2480
2481 return fNeedsNextBDLE;
2482}
2483
2484DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbInc)
2485{
2486 AssertPtrReturnVoid(pThis);
2487 AssertPtrReturnVoid(pStrmSt);
2488
2489 LogFlowFunc(("[SD%RU8]: cbInc=%RU32\n", pStrmSt->u8Strm, cbInc));
2490
2491 Assert(cbInc <= pStrmSt->u16FIFOS);
2492
2493 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2494
2495 /*
2496 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
2497 * doesn't fetch anything via DMA, so just update LPIB.
2498 * (ICH6 datasheet 18.2.38).
2499 */
2500 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
2501 {
2502 const uint32_t u32LPIB = RT_MIN(HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2503 pStrmSt->u32CBL);
2504
2505 LogFlowFunc(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
2506 pStrmSt->u8Strm,
2507 HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2508 pStrmSt->u32CBL));
2509
2510 hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2511 }
2512}
2513
2514static bool hdaStreamTransferIsComplete(PHDASTATE pThis, PHDASTREAM pStrmSt)
2515{
2516 AssertPtrReturn(pThis, true);
2517 AssertPtrReturn(pStrmSt, true);
2518
2519 bool fIsComplete = false;
2520
2521 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2522 const uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2523
2524 if ( pBDLE->State.u32BufOff >= pBDLE->u32BufSize
2525 || u32LPIB >= pStrmSt->u32CBL)
2526 {
2527 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2528 Assert(u32LPIB <= pStrmSt->u32CBL);
2529
2530 if (/* IOC (Interrupt On Completion) bit set? */
2531 pBDLE->fIntOnCompletion
2532 /* All data put into the DMA FIFO? */
2533 && pBDLE->State.cbBelowFIFOW == 0
2534 )
2535 {
2536 /**
2537 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
2538 * last byte of data for the current descriptor has been fetched
2539 * from memory and put into the DMA FIFO.
2540 *
2541 ** @todo More carefully investigate BCIS flag.
2542 *
2543 * Speech synthesis works fine on Mac Guest if this bit isn't set
2544 * but in general sound quality gets worse.
2545 */
2546 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2547
2548 /*
2549 * If the ICE (IOCE, "Interrupt On Completion Enable") bit of the SDCTL register is set
2550 * we need to generate an interrupt.
2551 */
2552 if (HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2553 hdaProcessInterrupt(pThis);
2554 }
2555
2556 fIsComplete = true;
2557 }
2558
2559 LogFlowFunc(("[SD%RU8]: u32LPIB=%RU32, CBL=%RU32, %R[bdle] => %s\n",
2560 pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, pBDLE, fIsComplete ? "COMPLETE" : "INCOMPLETE"));
2561
2562 return fIsComplete;
2563}
2564
2565/**
2566 * hdaReadAudio - copies samples from audio backend to DMA.
2567 * Note: This function writes to the DMA buffer immediately,
2568 * but "reports bytes" when all conditions are met (FIFOW).
2569 */
2570static int hdaReadAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, PAUDMIXSINK pSink, uint32_t cbMax, uint32_t *pcbRead)
2571{
2572 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2573 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2574 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
2575 /* pcbRead is optional. */
2576
2577 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2578
2579 int rc;
2580 uint32_t cbRead = 0;
2581 uint32_t cbBuf = hdaStreamGetTransferSize(pThis, pStrmSt, cbMax);
2582
2583 LogFlowFunc(("cbBuf=%RU32, %R[bdle]\n", cbBuf, pBDLE));
2584
2585 if (!cbBuf)
2586 {
2587 /* Nothing to write, bail out. */
2588 rc = VINF_EOF;
2589 }
2590 else
2591 {
2592 rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pBDLE->State.au8FIFO, cbBuf, &cbRead);
2593 if (RT_SUCCESS(rc))
2594 {
2595 Assert(cbRead);
2596 Assert(cbRead == cbBuf);
2597 Assert(cbRead <= pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2598
2599 /*
2600 * Write to the BDLE's DMA buffer.
2601 */
2602 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2603 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2604 pBDLE->State.au8FIFO, cbRead);
2605 AssertRC(rc);
2606
2607 if (pBDLE->State.cbBelowFIFOW + cbRead > hdaStreamGetFIFOW(pThis, pStrmSt))
2608 {
2609 pBDLE->State.u32BufOff += cbRead;
2610 pBDLE->State.cbBelowFIFOW = 0;
2611 //hdaBackendReadTransferReported(pBDLE, cbDMAData, cbRead, &cbRead, pcbAvail);
2612 }
2613 else
2614 {
2615 pBDLE->State.u32BufOff += cbRead;
2616 pBDLE->State.cbBelowFIFOW += cbRead;
2617 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2618 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbRead, pcbAvail);
2619
2620 rc = VERR_NO_DATA;
2621 }
2622 }
2623 }
2624
2625 Assert(cbRead <= pStrmSt->u16FIFOS);
2626
2627 if (RT_SUCCESS(rc))
2628 {
2629 if (pcbRead)
2630 *pcbRead = cbRead;
2631 }
2632
2633 LogFunc(("Returning cbRead=%RU32, rc=%Rrc\n", cbRead, rc));
2634 return rc;
2635}
2636
2637static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbMax, uint32_t *pcbWritten)
2638{
2639 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2640 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2641 AssertPtrReturn(pcbWritten, VERR_INVALID_POINTER);
2642 /* pcbWritten is optional. */
2643
2644 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2645 int rc;
2646
2647 uint32_t cbWritten = 0;
2648 uint32_t cbData = hdaStreamGetTransferSize(pThis, pStrmSt, cbMax);
2649
2650 LogFlowFunc(("cbData=%RU32, %R[bdle]\n", cbData, pBDLE));
2651
2652 /*
2653 * Copy from DMA to the corresponding stream buffer (if there are any bytes from the
2654 * previous unreported transfer we write at offset 'pBDLE->State.cbUnderFifoW').
2655 */
2656 if (!cbData)
2657 {
2658 rc = VINF_EOF;
2659 }
2660 else
2661 {
2662 /*
2663 * Read from the current BDLE's DMA buffer.
2664 */
2665 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2666 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2667 pBDLE->State.au8FIFO + pBDLE->State.cbBelowFIFOW, cbData);
2668 AssertRC(rc);
2669
2670#ifdef VBOX_WITH_STATISTICS
2671 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbData);
2672#endif
2673 /*
2674 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2675 */
2676 uint32_t cbToWrite = cbData + pBDLE->State.cbBelowFIFOW;
2677 if (cbToWrite >= hdaStreamGetFIFOW(pThis, pStrmSt))
2678 {
2679 uint32_t cbWrittenToStream;
2680 int rc2;
2681
2682 PHDADRIVER pDrv;
2683 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2684 {
2685 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2686 {
2687 rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2688 pBDLE->State.au8FIFO, cbToWrite, &cbWrittenToStream);
2689 if (RT_SUCCESS(rc2))
2690 {
2691 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2692 LogFlowFunc(("\tLUN#%RU8: Warning: Only written %RU32 / %RU32 bytes, expect lags\n",
2693 pDrv->uLUN, cbWrittenToStream, cbToWrite));
2694 }
2695 }
2696 else /* Stream disabled, not fatal. */
2697 {
2698 cbWrittenToStream = 0;
2699 rc2 = VERR_NOT_AVAILABLE;
2700 /* Keep going. */
2701 }
2702
2703 LogFlowFunc(("\tLUN#%RU8: cbToWrite=%RU32, cbWrittenToStream=%RU32, rc=%Rrc\n",
2704 pDrv->uLUN, cbToWrite, cbWrittenToStream, rc2));
2705 }
2706
2707 /* Always report all data as being written;
2708 * backends who were not able to catch up have to deal with it themselves. */
2709 cbWritten = cbToWrite;
2710
2711 hdaBDLEUpdate(pBDLE, cbData, cbWritten);
2712 }
2713 else
2714 {
2715 pBDLE->State.u32BufOff += cbWritten;
2716 pBDLE->State.cbBelowFIFOW += cbWritten;
2717 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2718
2719 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2720 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbAvail, NULL);
2721 rc = VINF_EOF;
2722 }
2723 }
2724
2725 Assert(cbWritten <= pStrmSt->u16FIFOS);
2726
2727 if (RT_SUCCESS(rc))
2728 {
2729 if (pcbWritten)
2730 *pcbWritten = cbWritten;
2731 }
2732
2733 LogFunc(("Returning cbWritten=%RU32, rc=%Rrc\n", cbWritten, rc));
2734 return rc;
2735}
2736
2737/**
2738 * @interface_method_impl{HDACODEC,pfnReset}
2739 */
2740static DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2741{
2742 PHDASTATE pThis = pCodec->pHDAState;
2743 NOREF(pThis);
2744 return VINF_SUCCESS;
2745}
2746
2747
2748static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2749{
2750 NOREF(pThis);
2751 NOREF(enmRecSource);
2752 LogFlowFuncEnter();
2753}
2754
2755static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2756{
2757 NOREF(pThis);
2758 LogFlowFuncEnter();
2759}
2760
2761static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2762 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2763 PPDMAUDIOSTREAMCFG pCfg)
2764{
2765 PAUDMIXSINK pSink;
2766
2767 switch (enmRecSource)
2768 {
2769# ifdef VBOX_WITH_HDA_MIC_IN
2770 case PDMAUDIORECSOURCE_MIC:
2771 pSink = pThis->pSinkMicIn;
2772 break;
2773# endif
2774 case PDMAUDIORECSOURCE_LINE_IN:
2775 pSink = pThis->pSinkLineIn;
2776 break;
2777 default:
2778 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2779 return VERR_NOT_SUPPORTED;
2780 }
2781
2782 int rc = VINF_SUCCESS;
2783 char *pszDesc;
2784
2785 PHDADRIVER pDrv;
2786 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2787 {
2788 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2789 {
2790 rc = VERR_NO_MEMORY;
2791 break;
2792 }
2793
2794 rc = pDrv->pConnector->pfnCreateIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2795 LogFlowFunc(("LUN#%RU8: Created input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2796 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2797 {
2798 AudioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2799 rc = AudioMixerAddStreamIn(pSink,
2800 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2801 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2802 }
2803
2804 RTStrFree(pszDesc);
2805 }
2806
2807 LogFlowFuncLeaveRC(rc);
2808 return rc;
2809}
2810
2811static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2812 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2813{
2814 int rc = VINF_SUCCESS;
2815 char *pszDesc;
2816
2817 PHDADRIVER pDrv;
2818 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2819 {
2820 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s (%RU32Hz, %RU8 %s)",
2821 pDrv->uLUN, pszName, pCfg->uHz, pCfg->cChannels, pCfg->cChannels > 1 ? "Channels" : "Channel") <= 0)
2822 {
2823 rc = VERR_NO_MEMORY;
2824 break;
2825 }
2826
2827 rc = pDrv->pConnector->pfnCreateOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
2828 LogFlowFunc(("LUN#%RU8: Created output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2829 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2830 {
2831 AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
2832 rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
2833 pDrv->pConnector, pDrv->Out.pStrmOut,
2834 0 /* uFlags */, &pDrv->Out.phStrmOut);
2835 }
2836
2837 RTStrFree(pszDesc);
2838 }
2839
2840 LogFlowFuncLeaveRC(rc);
2841 return rc;
2842}
2843
2844static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis, ENMSOUNDSOURCE enmSource,
2845 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2846{
2847 int rc = VINF_SUCCESS;
2848 PDMAUDIOVOLUME vol = { fMute, uVolLeft, uVolRight };
2849 PAUDMIXSINK pSink;
2850
2851 /* Convert the audio source to corresponding sink. */
2852 switch (enmSource)
2853 {
2854 case PO_INDEX:
2855 pSink = pThis->pSinkOutput;
2856 break;
2857 case PI_INDEX:
2858 pSink = pThis->pSinkLineIn;
2859 break;
2860 case MC_INDEX:
2861 pSink = pThis->pSinkMicIn;
2862 break;
2863 default:
2864 AssertFailedReturn(VERR_INVALID_PARAMETER);
2865 break;
2866 }
2867
2868 /* Set the volume. Codec already converted it to the correct range. */
2869 AudioMixerSetSinkVolume(pSink, &vol);
2870
2871 LogFlowFuncLeaveRC(rc);
2872 return rc;
2873}
2874
2875#ifndef VBOX_WITH_AUDIO_CALLBACKS
2876
2877static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2878{
2879 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2880 AssertPtrReturnVoid(pThis);
2881
2882 STAM_PROFILE_START(&pThis->StatTimer, a);
2883
2884 int rc = VINF_SUCCESS;
2885
2886 uint32_t cbInMax = 0;
2887 uint32_t cbOutMin = UINT32_MAX;
2888
2889 PHDADRIVER pDrv;
2890
2891 uint32_t cbIn, cbOut, cSamplesLive;
2892
2893 uint64_t uTicksNow = PDMDevHlpTMTimeVirtGet(pDevIns);
2894 uint64_t uTicksElapsed = uTicksNow - pThis->uTimerTS;
2895 uint64_t uTicksPerSec = PDMDevHlpTMTimeVirtGetFreq(pDevIns);
2896
2897 pThis->uTimerTS = uTicksNow;
2898
2899 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2900 {
2901 cbIn = cbOut = 0;
2902 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2903 &cbIn, &cbOut, NULL /* cSamplesLive */);
2904 if (RT_SUCCESS(rc))
2905 rc = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, NULL /* cSamplesPlayed */);
2906
2907 uint32_t cSamplesMin = (int)((2 * uTicksElapsed * pDrv->Out.pStrmOut->Props.uHz + uTicksPerSec) / uTicksPerSec / 2);
2908 uint32_t cbSamplesMin = AUDIOMIXBUF_S2B(&pDrv->Out.pStrmOut->MixBuf, cSamplesMin);
2909
2910 LogFlowFunc(("LUN#%RU8: rc=%Rrc, cbOut=%RU32, cSamplesMin=%RU32, cbSamplesMin=%RU32\n",
2911 pDrv->uLUN, rc, cbOut, cSamplesMin, cbSamplesMin));
2912
2913 if ( RT_FAILURE(rc)
2914 && cbSamplesMin > cbOut)
2915 {
2916 LogFlowFunc(("LUN#%RU8: Adj: %RU32 -> %RU32\n", pDrv->uLUN, cbOut, cbSamplesMin));
2917 cbOut = cbSamplesMin;
2918 }
2919
2920 cbOutMin = RT_MIN(cbOutMin, cbOut);
2921 cbInMax = RT_MAX(cbInMax, cbIn);
2922 }
2923
2924#ifdef DEBUG_TIMER
2925 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
2926#endif
2927
2928 if (cbOutMin == UINT32_MAX)
2929 cbOutMin = 0;
2930
2931 /*
2932 * Playback.
2933 */
2934 if (cbOutMin)
2935 {
2936 Assert(cbOutMin != UINT32_MAX);
2937 hdaTransfer(pThis, PO_INDEX, cbOutMin /* cbMax */, NULL /* pcbProcessed */); /** @todo Add rc! */
2938 }
2939
2940 /*
2941 * Recording.
2942 */
2943 if (cbInMax)
2944 hdaTransfer(pThis, PI_INDEX, cbInMax /* cbMax */, NULL /* pcbProcessed */); /** @todo Add rc! */
2945
2946 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTimerTicks);
2947
2948 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2949}
2950
2951#else /* VBOX_WITH_AUDIO_CALLBACKS */
2952
2953static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
2954{
2955 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
2956 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
2957 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
2958 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
2959 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
2960
2961 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
2962 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
2963
2964 PPDMAUDIOCALLBACKDATAIN pData = (PPDMAUDIOCALLBACKDATAIN)pvUser;
2965 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAIN), VERR_INVALID_PARAMETER);
2966
2967 return hdaTransfer(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
2968}
2969
2970static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
2971{
2972 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
2973 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
2974 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
2975 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
2976 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
2977
2978 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
2979 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
2980
2981 PPDMAUDIOCALLBACKDATAOUT pData = (PPDMAUDIOCALLBACKDATAOUT)pvUser;
2982 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAOUT), VERR_INVALID_PARAMETER);
2983
2984 PHDASTATE pThis = pCtx->pThis;
2985
2986 int rc = hdaTransfer(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
2987 if ( RT_SUCCESS(rc)
2988 && pData->cbOutWritten)
2989 {
2990 PHDADRIVER pDrv;
2991 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2992 {
2993 uint32_t cSamplesPlayed;
2994 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2995 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
2996 }
2997 }
2998}
2999#endif /* VBOX_WITH_AUDIO_CALLBACKS */
3000
3001static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbMax, uint32_t *pcbProcessed)
3002{
3003 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3004 /* pcbProcessed is optional. */
3005
3006 LogFlowFunc(("enmSrc=%RU32, cbMax=%RU32\n", enmSrc, cbMax));
3007
3008 PHDASTREAM pStrmSt;
3009 switch (enmSrc)
3010 {
3011 case PI_INDEX:
3012 {
3013 pStrmSt = &pThis->StrmStLineIn;
3014 break;
3015 }
3016
3017#ifdef VBOX_WITH_HDA_MIC_IN
3018 case MC_INDEX:
3019 {
3020 pStrmSt = &pThis->StrmStMicIn;
3021 break;
3022 }
3023#endif
3024 case PO_INDEX:
3025 {
3026 pStrmSt = &pThis->StrmStOut;
3027 break;
3028 }
3029
3030 default:
3031 {
3032 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
3033 return VERR_NOT_SUPPORTED;
3034 }
3035 }
3036
3037 if (pStrmSt->State.cBDLE == 0) /* No buffers available? */
3038 {
3039 LogFlowFunc(("[SD%RU8] No buffers available\n", pStrmSt->u8Strm));
3040
3041 if (pcbProcessed)
3042 *pcbProcessed = 0;
3043 return VINF_SUCCESS;
3044 }
3045 AssertPtr(pStrmSt->State.paBDLE);
3046
3047 /* Is this stream running? */
3048 const bool fIsRunning = RT_BOOL(HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3049 if (!fIsRunning)
3050 {
3051 LogFlowFunc(("[SD%RU8]: Stream not running\n", pStrmSt->u8Strm));
3052
3053 if (pcbProcessed)
3054 *pcbProcessed = 0;
3055 return VINF_SUCCESS;
3056 }
3057
3058 Assert(pStrmSt->u8Strm <= 7); /** @todo Use a define for MAX_STREAMS! */
3059 Assert(pStrmSt->u64BaseDMA);
3060 Assert(pStrmSt->u32CBL);
3061
3062 int rc = VINF_SUCCESS;
3063 uint32_t cbToProcess = cbMax;
3064 uint32_t cbProcessedTotal = 0;
3065 bool fIsComplete = false;
3066
3067 while (cbToProcess)
3068 {
3069 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
3070 if (hdaStreamNeedsNextBDLE(pThis, pStrmSt))
3071 hdaStreamGetNextBDLE(pThis, pStrmSt);
3072
3073 /* Set the FIFORDY bit on the stream while doing the transfer. */
3074 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3075
3076 uint32_t cbProcessed;
3077 switch (enmSrc)
3078 {
3079 case PI_INDEX:
3080 rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkLineIn, cbToProcess, &cbProcessed);
3081 break;
3082 case PO_INDEX:
3083 rc = hdaWriteAudio(pThis, pStrmSt, cbToProcess, &cbProcessed);
3084 break;
3085#ifdef VBOX_WITH_HDA_MIC_IN
3086 case MC_INDEX:
3087 rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkMicIn, cbToProcess, &cbProcessed);
3088 break;
3089#endif
3090 default:
3091 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
3092 rc = VERR_NOT_SUPPORTED;
3093 break;
3094 }
3095
3096 /* Remove the FIFORDY bit again. */
3097 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3098
3099 if (RT_FAILURE(rc))
3100 break;
3101
3102 hdaStreamTransferUpdate(pThis, pStrmSt, cbProcessed);
3103
3104 cbToProcess -= RT_MIN(cbToProcess, cbProcessed);
3105 cbProcessedTotal += cbProcessed;
3106
3107 LogFlowFunc(("cbProcessed=%RU32, cbToProcess=%RU32, cbProcessedTotal=%RU32, rc=%Rrc\n",
3108 cbProcessed, cbToProcess, cbProcessedTotal, rc));
3109
3110 if (rc == VINF_EOF)
3111 fIsComplete = true;
3112
3113 if (!fIsComplete)
3114 fIsComplete = hdaStreamTransferIsComplete(pThis, pStrmSt);
3115
3116 if (fIsComplete)
3117 break;
3118 }
3119
3120 if (RT_SUCCESS(rc))
3121 {
3122 if (pcbProcessed)
3123 *pcbProcessed = cbProcessedTotal;
3124 }
3125
3126 LogFlowFuncLeaveRC(rc);
3127 return rc;
3128}
3129#endif /* IN_RING3 */
3130
3131/* MMIO callbacks */
3132
3133/**
3134 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3135 *
3136 * @note During implementation, we discovered so-called "forgotten" or "hole"
3137 * registers whose description is not listed in the RPM, datasheet, or
3138 * spec.
3139 */
3140PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3141{
3142 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3143 int rc;
3144
3145 /*
3146 * Look up and log.
3147 */
3148 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3149 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
3150#ifdef LOG_ENABLED
3151 unsigned const cbLog = cb;
3152 uint32_t offRegLog = offReg;
3153#endif
3154
3155 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
3156 Assert(cb == 4); Assert((offReg & 3) == 0);
3157
3158 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3159 LogFunc(("\tAccess to registers except GCTL is blocked while reset\n"));
3160
3161 if (idxRegDsc == -1)
3162 LogRel(("HDA: Invalid read access @0x%x (bytes=%d)\n", offReg, cb));
3163
3164 if (idxRegDsc != -1)
3165 {
3166 /* ASSUMES gapless DWORD at end of map. */
3167 if (g_aHdaRegMap[idxRegDsc].size == 4)
3168 {
3169 /*
3170 * Straight forward DWORD access.
3171 */
3172 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3173 LogFunc(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
3174 }
3175 else
3176 {
3177 /*
3178 * Multi register read (unless there are trailing gaps).
3179 * ASSUMES that only DWORD reads have sideeffects.
3180 */
3181 uint32_t u32Value = 0;
3182 unsigned cbLeft = 4;
3183 do
3184 {
3185 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3186 uint32_t u32Tmp = 0;
3187
3188 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3189 LogFunc(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3190 if (rc != VINF_SUCCESS)
3191 break;
3192 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3193
3194 cbLeft -= cbReg;
3195 offReg += cbReg;
3196 idxRegDsc++;
3197 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3198
3199 if (rc == VINF_SUCCESS)
3200 *(uint32_t *)pv = u32Value;
3201 else
3202 Assert(!IOM_SUCCESS(rc));
3203 }
3204 }
3205 else
3206 {
3207 rc = VINF_IOM_MMIO_UNUSED_FF;
3208 LogFunc(("\tHole at %x is accessed for read\n", offReg));
3209 }
3210
3211 /*
3212 * Log the outcome.
3213 */
3214#ifdef LOG_ENABLED
3215 if (cbLog == 4)
3216 LogFunc(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
3217 else if (cbLog == 2)
3218 LogFunc(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
3219 else if (cbLog == 1)
3220 LogFunc(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
3221#endif
3222 return rc;
3223}
3224
3225
3226DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3227{
3228 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3229 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
3230
3231 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3232#ifdef LOG_ENABLED
3233 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
3234#endif
3235 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3236 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3237 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
3238 return rc;
3239}
3240
3241
3242/**
3243 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3244 */
3245PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
3246{
3247 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3248 int rc;
3249
3250 /*
3251 * The behavior of accesses that aren't aligned on natural boundraries is
3252 * undefined. Just reject them outright.
3253 */
3254 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3255 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
3256 if (GCPhysAddr & (cb - 1))
3257 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3258
3259 /*
3260 * Look up and log the access.
3261 */
3262 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3263 int idxRegDsc = hdaRegLookup(pThis, offReg);
3264 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3265 uint64_t u64Value;
3266 if (cb == 4) u64Value = *(uint32_t const *)pv;
3267 else if (cb == 2) u64Value = *(uint16_t const *)pv;
3268 else if (cb == 1) u64Value = *(uint8_t const *)pv;
3269 else if (cb == 8) u64Value = *(uint64_t const *)pv;
3270 else
3271 {
3272 u64Value = 0; /* shut up gcc. */
3273 AssertReleaseMsgFailed(("%u\n", cb));
3274 }
3275
3276#ifdef LOG_ENABLED
3277 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3278 if (idxRegDsc == -1)
3279 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
3280 else if (cb == 4)
3281 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3282 else if (cb == 2)
3283 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3284 else if (cb == 1)
3285 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3286
3287 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3288 LogFunc(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3289#endif
3290
3291 /*
3292 * Try for a direct hit first.
3293 */
3294 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3295 {
3296 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3297#ifdef LOG_ENABLED
3298 LogFunc(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3299#endif
3300 }
3301 /*
3302 * Partial or multiple register access, loop thru the requested memory.
3303 */
3304 else
3305 {
3306 /*
3307 * If it's an access beyond the start of the register, shift the input
3308 * value and fill in missing bits. Natural alignment rules means we
3309 * will only see 1 or 2 byte accesses of this kind, so no risk of
3310 * shifting out input values.
3311 */
3312 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
3313 {
3314 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3315 offReg -= cbBefore;
3316 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3317 u64Value <<= cbBefore * 8;
3318 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3319 LogFunc(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3320 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3321 }
3322
3323 /* Loop thru the write area, it may cover multiple registers. */
3324 rc = VINF_SUCCESS;
3325 for (;;)
3326 {
3327 uint32_t cbReg;
3328 if (idxRegDsc != -1)
3329 {
3330 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3331 cbReg = g_aHdaRegMap[idxRegDsc].size;
3332 if (cb < cbReg)
3333 {
3334 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3335 LogFunc(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3336 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3337 }
3338 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
3339 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3340 LogFunc(("\t%#x -> %#x\n", u32LogOldVal, pThis->au32Regs[idxRegMem]));
3341 }
3342 else
3343 {
3344 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3345 cbReg = 1;
3346 }
3347 if (rc != VINF_SUCCESS)
3348 break;
3349 if (cbReg >= cb)
3350 break;
3351
3352 /* Advance. */
3353 offReg += cbReg;
3354 cb -= cbReg;
3355 u64Value >>= cbReg * 8;
3356 if (idxRegDsc == -1)
3357 idxRegDsc = hdaRegLookup(pThis, offReg);
3358 else
3359 {
3360 idxRegDsc++;
3361 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3362 || g_aHdaRegMap[idxRegDsc].offset != offReg)
3363 {
3364 idxRegDsc = -1;
3365 }
3366 }
3367 }
3368 }
3369
3370 return rc;
3371}
3372
3373
3374/* PCI callback. */
3375
3376#ifdef IN_RING3
3377/**
3378 * @callback_method_impl{FNPCIIOREGIONMAP}
3379 */
3380static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
3381 PCIADDRESSSPACE enmType)
3382{
3383 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3384 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3385 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3386 int rc;
3387
3388 /*
3389 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3390 *
3391 * Let IOM talk DWORDs when reading, saves a lot of complications. On
3392 * writing though, we have to do it all ourselves because of sideeffects.
3393 */
3394 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3395 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
3396 IOMMMIO_FLAGS_READ_DWORD
3397 | IOMMMIO_FLAGS_WRITE_PASSTHRU,
3398 hdaMMIOWrite, hdaMMIORead, "HDA");
3399
3400 if (RT_FAILURE(rc))
3401 return rc;
3402
3403 if (pThis->fR0Enabled)
3404 {
3405 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
3406 "hdaMMIOWrite", "hdaMMIORead");
3407 if (RT_FAILURE(rc))
3408 return rc;
3409 }
3410
3411 if (pThis->fRCEnabled)
3412 {
3413 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
3414 "hdaMMIOWrite", "hdaMMIORead");
3415 if (RT_FAILURE(rc))
3416 return rc;
3417 }
3418
3419 pThis->MMIOBaseAddr = GCPhysAddress;
3420 return VINF_SUCCESS;
3421}
3422
3423
3424/* Saved state callbacks. */
3425
3426static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
3427{
3428 /* Save stream ID. */
3429 int rc = SSMR3PutU8(pSSM, pStrm->u8Strm);
3430 AssertRCReturn(rc, rc);
3431 Assert(pStrm->u8Strm <= 7); /** @todo Use a define. */
3432
3433 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields5, NULL);
3434 AssertRCReturn(rc, rc);
3435
3436 for (uint32_t i = 0; i < pStrm->State.cBDLE; i++)
3437 {
3438 rc = SSMR3PutStructEx(pSSM, &pStrm->State.paBDLE[i], sizeof(HDABDLE), 0 /*fFlags*/, g_aSSMBDLEStateFields5, NULL);
3439 AssertRCReturn(rc, rc);
3440 }
3441
3442 return rc;
3443}
3444
3445/**
3446 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3447 */
3448static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3449{
3450 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3451
3452 /* Save Codec nodes states. */
3453 hdaCodecSaveState(pThis->pCodec, pSSM);
3454
3455 /* Save MMIO registers. */
3456 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3457 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3458 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3459
3460 /* Save number of streams. */
3461 SSMR3PutU32(pSSM, 3);
3462
3463 /* Save stream states. */
3464 int rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStOut);
3465 AssertRCReturn(rc, rc);
3466 rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStMicIn);
3467 AssertRCReturn(rc, rc);
3468 rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStLineIn);
3469 AssertRCReturn(rc, rc);
3470
3471 return rc;
3472}
3473
3474
3475/**
3476 * @callback_method_impl{FNSSMDEVLOADEXEC}
3477 */
3478static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3479{
3480 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3481
3482 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3483
3484 LogFlowFunc(("uVersion=%RU32, uPass=%RU32\n", uVersion, uPass));
3485
3486 /*
3487 * Load Codec nodes states.
3488 */
3489 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3490 if (RT_FAILURE(rc))
3491 return rc;
3492
3493 /*
3494 * Load MMIO registers.
3495 */
3496 uint32_t cRegs;
3497 switch (uVersion)
3498 {
3499 case HDA_SSM_VERSION_1:
3500 /* Starting with r71199, we would save 112 instead of 113
3501 registers due to some code cleanups. This only affected trunk
3502 builds in the 4.1 development period. */
3503 cRegs = 113;
3504 if (SSMR3HandleRevision(pSSM) >= 71199)
3505 {
3506 uint32_t uVer = SSMR3HandleVersion(pSSM);
3507 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3508 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3509 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3510 cRegs = 112;
3511 }
3512 break;
3513
3514 case HDA_SSM_VERSION_2:
3515 case HDA_SSM_VERSION_3:
3516 cRegs = 112;
3517 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3518 break;
3519
3520 /* Since version 4 we store the register count to stay flexible. */
3521 case HDA_SSM_VERSION_4:
3522 case HDA_SSM_VERSION:
3523 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3524 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3525 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3526 break;
3527
3528 default:
3529 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3530 }
3531
3532 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3533 {
3534 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3535 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3536 }
3537 else
3538 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3539
3540 /*
3541 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3542 * *every* BDLE state, whereas it only needs to be stored
3543 * *once* for every stream. Most of the BDLE state we can
3544 * get out of the registers anyway, so just ignore those values.
3545 *
3546 * Also, only the current BDLE was saved, regardless whether
3547 * there were more than one (and there are at least two entries,
3548 * according to the spec).
3549 */
3550#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3551 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3552 AssertRCReturn(rc, rc); \
3553 rc = SSMR3Skip(pSSM, sizeof(uint64_t)); /* u64BdleCviAddr */ \
3554 AssertRCReturn(rc, rc); \
3555 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3556 AssertRCReturn(rc, rc); \
3557 rc = SSMR3GetU32(pSSM, &x->u32BDLIndex); /* u32BdleCvi */ \
3558 AssertRCReturn(rc, rc); \
3559 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleCviLen */ \
3560 AssertRCReturn(rc, rc); \
3561 rc = SSMR3GetU32(pSSM, &x->u32BufOff); /* u32BdleCviPos */ \
3562 AssertRCReturn(rc, rc); \
3563 rc = SSMR3Skip(pSSM, sizeof(uint8_t)); /* fBdleCviIoc */ \
3564 AssertRCReturn(rc, rc); \
3565 rc = SSMR3GetU32(pSSM, &x->cbBelowFIFOW); /* cbUnderFifoW */ \
3566 AssertRCReturn(rc, rc); \
3567 rc = SSMR3GetMem(pSSM, &x->au8FIFO, sizeof(x->au8FIFO)); \
3568 AssertRCReturn(rc, rc); \
3569 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3570 AssertRCReturn(rc, rc); \
3571
3572 /*
3573 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3574 */
3575 HDABDLESTATE StateBDLEDummy;
3576
3577 switch (uVersion)
3578 {
3579 case HDA_SSM_VERSION_1:
3580 case HDA_SSM_VERSION_2:
3581 case HDA_SSM_VERSION_3:
3582 case HDA_SSM_VERSION_4:
3583 {
3584 /* Only load the internal states.
3585 * The rest will be initialized from the saved registers later. */
3586
3587 /* Note: Only the *current* BDLE for a stream was saved! */
3588
3589 /* Output */
3590 rc = hdaStreamInit(pThis, &pThis->StrmStOut, 4 /* Stream number, hardcoded */);
3591 AssertRCBreak(rc);
3592 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStOut.State.cBDLE
3593 ? &pThis->StrmStOut.State.paBDLE[0].State : &StateBDLEDummy));
3594 /* Microphone-In */
3595 rc = hdaStreamInit(pThis, &pThis->StrmStMicIn, 2 /* Stream number, hardcoded */);
3596 AssertRCBreak(rc);
3597 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStMicIn.State.cBDLE
3598 ? &pThis->StrmStMicIn.State.paBDLE[0].State : &StateBDLEDummy));
3599 /* Line-In */
3600 rc = hdaStreamInit(pThis, &pThis->StrmStLineIn, 0 /* Stream number, hardcoded */);
3601 AssertRCBreak(rc);
3602 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStLineIn.State.cBDLE
3603 ? &pThis->StrmStLineIn.State.paBDLE[0].State : &StateBDLEDummy));
3604 break;
3605 }
3606
3607 /* Since v5 we support flexible stream and BDLE counts. */
3608 case HDA_SSM_VERSION:
3609 {
3610 uint32_t cStreams;
3611 rc = SSMR3GetU32(pSSM, &cStreams);
3612 AssertRCBreak(rc);
3613
3614 /* Load stream states. */
3615 for (uint32_t i = 0; i < cStreams; i++)
3616 {
3617 uint8_t uStreamID;
3618 rc = SSMR3GetU8(pSSM, &uStreamID);
3619 AssertRCBreak(rc);
3620
3621 PHDASTREAM pStrm;
3622 HDASTREAM StreamDummy;
3623
3624 switch (uStreamID)
3625 {
3626 case 0: /** @todo Use a define. */
3627 pStrm = &pThis->StrmStLineIn;
3628 break;
3629
3630 case 2: /** @todo Use a define. */
3631 pStrm = &pThis->StrmStMicIn;
3632 break;
3633
3634 case 4: /** @todo Use a define. */
3635 pStrm = &pThis->StrmStOut;
3636 break;
3637
3638 default:
3639 pStrm = &StreamDummy;
3640 break;
3641 }
3642
3643 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /* fFlags */, g_aSSMStreamStateFields5, NULL);
3644 AssertRCBreak(rc);
3645
3646 rc = hdaStreamInit(pThis, pStrm, uStreamID);
3647 AssertRCBreak(rc);
3648
3649 /* Load BDLE states. */
3650 for (uint32_t a = 0; a < pStrm->State.cBDLE; a++)
3651 {
3652 rc = SSMR3GetStructEx(pSSM, &pStrm->State.paBDLE[a].State, sizeof(HDABDLESTATE),
3653 0 /* fFlags */, g_aSSMBDLEStateFields5, NULL);
3654 AssertRCBreak(rc);
3655 }
3656
3657 /* Destroy dummy again. */
3658 if (pStrm == &StreamDummy)
3659 hdaStreamDestroy(pStrm);
3660 }
3661 break;
3662 }
3663
3664 default:
3665 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3666 }
3667
3668#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3669
3670 if (RT_SUCCESS(rc))
3671 {
3672 /*
3673 * Update stuff after the state changes.
3674 */
3675 bool fEnableIn = RT_BOOL(HDA_SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3676#ifdef VBOX_WITH_HDA_MIC_IN
3677 bool fEnableMicIn = RT_BOOL(HDA_SDCTL(pThis, 2) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3678#else
3679 bool fEnableMicIn = fEnableIn; /* Mic In == Line In */
3680#endif
3681 bool fEnableOut = RT_BOOL(HDA_SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3682
3683 PHDADRIVER pDrv;
3684 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3685 {
3686 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, fEnableIn);
3687 if (RT_FAILURE(rc))
3688 break;
3689 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, fEnableMicIn);
3690 if (RT_FAILURE(rc))
3691 break;
3692 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, fEnableOut);
3693 if (RT_FAILURE(rc))
3694 break;
3695 }
3696 }
3697
3698 if (RT_SUCCESS(rc))
3699 {
3700 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3701 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3702 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3703 }
3704
3705 LogFlowFuncLeaveRC(rc);
3706 return rc;
3707}
3708
3709#ifdef DEBUG
3710/* Debug and log type formatters. */
3711
3712/**
3713 * @callback_method_impl{FNRTSTRFORMATTYPE}
3714 */
3715static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3716 const char *pszType, void const *pvValue,
3717 int cchWidth, int cchPrecision, unsigned fFlags,
3718 void *pvUser)
3719{
3720 PHDABDLE pBDLE = (PHDABDLE)pvValue;
3721 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3722 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, DMA[%RU32 bytes @ 0x%x])",
3723 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW, pBDLE->u32BufSize, pBDLE->u64BufAdr);
3724}
3725
3726/**
3727 * @callback_method_impl{FNRTSTRFORMATTYPE}
3728 */
3729static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3730 const char *pszType, void const *pvValue,
3731 int cchWidth, int cchPrecision, unsigned fFlags,
3732 void *pvUser)
3733{
3734 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
3735 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3736 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
3737 uSDCTL,
3738 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
3739 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3740 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3741 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3742 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
3743 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3744 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3745 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3746}
3747
3748/**
3749 * @callback_method_impl{FNRTSTRFORMATTYPE}
3750 */
3751static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3752 const char *pszType, void const *pvValue,
3753 int cchWidth, int cchPrecision, unsigned fFlags,
3754 void *pvUser)
3755{
3756 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
3757 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, hdaSDFIFOSToBytes(uSDFIFOS));
3758}
3759
3760/**
3761 * @callback_method_impl{FNRTSTRFORMATTYPE}
3762 */
3763static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3764 const char *pszType, void const *pvValue,
3765 int cchWidth, int cchPrecision, unsigned fFlags,
3766 void *pvUser)
3767{
3768 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
3769 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
3770}
3771
3772/**
3773 * @callback_method_impl{FNRTSTRFORMATTYPE}
3774 */
3775static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3776 const char *pszType, void const *pvValue,
3777 int cchWidth, int cchPrecision, unsigned fFlags,
3778 void *pvUser)
3779{
3780 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3781 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3782 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3783 uSdSts,
3784 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3785 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3786 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3787 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3788}
3789
3790static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3791{
3792 int iReg = 0;
3793 for (; iReg < HDA_NREGS; ++iReg)
3794 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3795 return iReg;
3796 return -1;
3797}
3798
3799
3800static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
3801{
3802 Assert( pThis
3803 && iHdaIndex >= 0
3804 && iHdaIndex < HDA_NREGS);
3805 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
3806}
3807
3808/**
3809 * @callback_method_impl{FNDBGFHANDLERDEV}
3810 */
3811static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3812{
3813 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3814 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
3815 if (iHdaRegisterIndex != -1)
3816 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3817 else
3818 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
3819 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3820}
3821
3822static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
3823{
3824 Assert( pThis
3825 && iHdaStrmIndex >= 0
3826 && iHdaStrmIndex < 7);
3827 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
3828 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
3829 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
3830 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
3831 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
3832}
3833
3834static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
3835{
3836 /* todo: add args parsing */
3837 return -1;
3838}
3839
3840/**
3841 * @callback_method_impl{FNDBGFHANDLERDEV}
3842 */
3843static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3844{
3845 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3846 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
3847 if (iHdaStrmIndex != -1)
3848 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3849 else
3850 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
3851 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3852}
3853
3854/**
3855 * @callback_method_impl{FNDBGFHANDLERDEV}
3856 */
3857static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3858{
3859 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3860
3861 if (pThis->pCodec->pfnDbgListNodes)
3862 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
3863 else
3864 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3865}
3866
3867/**
3868 * @callback_method_impl{FNDBGFHANDLERDEV}
3869 */
3870static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3871{
3872 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3873
3874 if (pThis->pCodec->pfnDbgSelector)
3875 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
3876 else
3877 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3878}
3879
3880/**
3881 * @callback_method_impl{FNDBGFHANDLERDEV}
3882 */
3883static DECLCALLBACK(void) hdaInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3884{
3885 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3886
3887 if (pThis->pMixer)
3888 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
3889 else
3890 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
3891}
3892#endif /* DEBUG */
3893
3894/* PDMIBASE */
3895
3896/**
3897 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3898 */
3899static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3900{
3901 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
3902 Assert(&pThis->IBase == pInterface);
3903
3904 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3905 return NULL;
3906}
3907
3908
3909/* PDMDEVREG */
3910
3911/**
3912 * Reset notification.
3913 *
3914 * @returns VBox status code.
3915 * @param pDevIns The device instance data.
3916 *
3917 * @remark The original sources didn't install a reset handler, but it seems to
3918 * make sense to me so we'll do it.
3919 */
3920static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
3921{
3922 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3923
3924 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
3925 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3926 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3927 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3928 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3929 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
3930 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
3931 HDA_REG(pThis, CORBRP) = 0x0;
3932 HDA_REG(pThis, RIRBWP) = 0x0;
3933
3934 LogFunc(("Resetting ...\n"));
3935
3936 /* Stop any audio currently playing. */
3937 PHDADRIVER pDrv;
3938 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3939 {
3940 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
3941 /* Ignore rc. */
3942 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
3943 /* Ditto. */
3944 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
3945 /* Ditto. */
3946 }
3947
3948 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
3949
3950 if (pThis->pu32CorbBuf)
3951 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3952 else
3953 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3954
3955 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
3956 if (pThis->pu64RirbBuf)
3957 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3958 else
3959 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3960
3961 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
3962
3963 for (uint8_t u8Strm = 0; u8Strm < 8; u8Strm++) /** @todo Use a define here. */
3964 {
3965 PHDASTREAM pStrmSt = NULL;
3966 if (u8Strm == 0)
3967 pStrmSt = &pThis->StrmStOut;
3968# ifdef VBOX_WITH_HDA_MIC_IN
3969 else if (u8Strm == 2)
3970 pStrmSt = &pThis->StrmStMicIn;
3971# endif
3972 else if (u8Strm == 4)
3973 pStrmSt = &pThis->StrmStLineIn;
3974
3975 if (pStrmSt)
3976 {
3977 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
3978 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
3979
3980 hdaStreamReset(pThis, pStrmSt, u8Strm);
3981 }
3982 }
3983
3984 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3985 HDA_REG(pThis, STATESTS) = 0x1;
3986
3987 LogRel(("HDA: Reset\n"));
3988}
3989
3990/**
3991 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3992 */
3993static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
3994{
3995 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3996
3997 PHDADRIVER pDrv;
3998 while (!RTListIsEmpty(&pThis->lstDrv))
3999 {
4000 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
4001
4002 RTListNodeRemove(&pDrv->Node);
4003 RTMemFree(pDrv);
4004 }
4005
4006 if (pThis->pMixer)
4007 {
4008 AudioMixerDestroy(pThis->pMixer);
4009 pThis->pMixer = NULL;
4010 }
4011
4012 if (pThis->pCodec)
4013 {
4014 int rc = hdaCodecDestruct(pThis->pCodec);
4015 AssertRC(rc);
4016
4017 RTMemFree(pThis->pCodec);
4018 pThis->pCodec = NULL;
4019 }
4020
4021 RTMemFree(pThis->pu32CorbBuf);
4022 pThis->pu32CorbBuf = NULL;
4023
4024 RTMemFree(pThis->pu64RirbBuf);
4025 pThis->pu64RirbBuf = NULL;
4026
4027 hdaStreamDestroy(&pThis->StrmStLineIn);
4028 hdaStreamDestroy(&pThis->StrmStMicIn);
4029 hdaStreamDestroy(&pThis->StrmStOut);
4030
4031 return VINF_SUCCESS;
4032}
4033
4034/**
4035 * Attach command.
4036 *
4037 * This is called to let the device attach to a driver for a specified LUN
4038 * during runtime. This is not called during VM construction, the device
4039 * constructor have to attach to all the available drivers.
4040 *
4041 * @returns VBox status code.
4042 * @param pDevIns The device instance.
4043 * @param uLUN The logical unit which is being detached.
4044 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4045 */
4046static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4047{
4048 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4049
4050 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
4051 ("HDA device does not support hotplugging\n"),
4052 VERR_INVALID_PARAMETER);
4053
4054 /*
4055 * Attach driver.
4056 */
4057 char *pszDesc = NULL;
4058 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4059 AssertMsgReturn(pszDesc,
4060 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
4061 VERR_NO_MEMORY);
4062
4063 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
4064 &pThis->IBase, &pThis->pDrvBase, pszDesc);
4065 if (RT_SUCCESS(rc))
4066 {
4067 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4068 if (pDrv)
4069 {
4070 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
4071 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4072 pDrv->pHDAState = pThis;
4073 pDrv->uLUN = uLUN;
4074
4075 /*
4076 * For now we always set the driver at LUN 0 as our primary
4077 * host backend. This might change in the future.
4078 */
4079 if (pDrv->uLUN == 0)
4080 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
4081
4082 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
4083
4084 /* Attach to driver list. */
4085 RTListAppend(&pThis->lstDrv, &pDrv->Node);
4086 }
4087 else
4088 rc = VERR_NO_MEMORY;
4089 }
4090 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
4091 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
4092 {
4093 LogFunc(("No attached driver for LUN #%u\n", uLUN));
4094 }
4095 else if (RT_FAILURE(rc))
4096 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
4097 uLUN, pszDesc, rc));
4098
4099 RTStrFree(pszDesc);
4100
4101 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4102 return rc;
4103}
4104
4105static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4106{
4107 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
4108
4109 LogFlowFuncEnter();
4110}
4111
4112/**
4113 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4114 */
4115static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
4116{
4117 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4118 Assert(iInstance == 0);
4119 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4120
4121 /*
4122 * Validations.
4123 */
4124 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
4125 "RCEnabled\0"))
4126 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4127 N_ ("Invalid configuration for the Intel HDA device"));
4128
4129 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
4130 if (RT_FAILURE(rc))
4131 return PDMDEV_SET_ERROR(pDevIns, rc,
4132 N_("HDA configuration error: failed to read RCEnabled as boolean"));
4133 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
4134 if (RT_FAILURE(rc))
4135 return PDMDEV_SET_ERROR(pDevIns, rc,
4136 N_("HDA configuration error: failed to read R0Enabled as boolean"));
4137
4138 /*
4139 * Initialize data (most of it anyway).
4140 */
4141 pThis->pDevInsR3 = pDevIns;
4142 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4143 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4144 /* IBase */
4145 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
4146
4147 /* PCI Device */
4148 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
4149 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
4150
4151 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
4152 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
4153 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
4154 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
4155 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
4156 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
4157 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
4158 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
4159 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
4160 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
4161 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
4162
4163#if defined(HDA_AS_PCI_EXPRESS)
4164 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
4165#elif defined(VBOX_WITH_MSI_DEVICES)
4166 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
4167#else
4168 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
4169#endif
4170
4171 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
4172 /// of these values needs to be properly documented!
4173 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
4174 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
4175
4176 /* Power Management */
4177 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
4178 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
4179 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
4180
4181#ifdef HDA_AS_PCI_EXPRESS
4182 /* PCI Express */
4183 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
4184 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
4185 /* Device flags */
4186 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
4187 /* version */ 0x1 |
4188 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
4189 /* MSI */ (100) << 9 );
4190 /* Device capabilities */
4191 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
4192 /* Device control */
4193 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
4194 /* Device status */
4195 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
4196 /* Link caps */
4197 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
4198 /* Link control */
4199 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
4200 /* Link status */
4201 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
4202 /* Slot capabilities */
4203 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
4204 /* Slot control */
4205 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
4206 /* Slot status */
4207 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
4208 /* Root control */
4209 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
4210 /* Root capabilities */
4211 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
4212 /* Root status */
4213 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
4214 /* Device capabilities 2 */
4215 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
4216 /* Device control 2 */
4217 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
4218 /* Link control 2 */
4219 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
4220 /* Slot control 2 */
4221 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
4222#endif
4223
4224 /*
4225 * Register the PCI device.
4226 */
4227 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
4228 if (RT_FAILURE(rc))
4229 return rc;
4230
4231 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
4232 if (RT_FAILURE(rc))
4233 return rc;
4234
4235#ifdef VBOX_WITH_MSI_DEVICES
4236 PDMMSIREG MsiReg;
4237 RT_ZERO(MsiReg);
4238 MsiReg.cMsiVectors = 1;
4239 MsiReg.iMsiCapOffset = 0x60;
4240 MsiReg.iMsiNextOffset = 0x50;
4241 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4242 if (RT_FAILURE(rc))
4243 {
4244 /* That's OK, we can work without MSI */
4245 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
4246 }
4247#endif
4248
4249 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
4250 if (RT_FAILURE(rc))
4251 return rc;
4252
4253 RTListInit(&pThis->lstDrv);
4254
4255 uint8_t uLUN;
4256 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
4257 {
4258 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
4259 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
4260 if (RT_FAILURE(rc))
4261 {
4262 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4263 rc = VINF_SUCCESS;
4264
4265 break;
4266 }
4267
4268 uLUN++;
4269 }
4270
4271 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
4272
4273 if (RT_SUCCESS(rc))
4274 {
4275 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
4276 if (RT_SUCCESS(rc))
4277 {
4278 /* Set a default audio format for our mixer. */
4279 PDMAUDIOSTREAMCFG streamCfg;
4280 streamCfg.uHz = 44100;
4281 streamCfg.cChannels = 2;
4282 streamCfg.enmFormat = AUD_FMT_S16;
4283 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
4284
4285 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
4286 AssertRC(rc);
4287
4288 /* Add all required audio sinks. */
4289 rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output",
4290 AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
4291 AssertRC(rc);
4292
4293 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In",
4294 AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
4295 AssertRC(rc);
4296
4297 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
4298 AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
4299 AssertRC(rc);
4300
4301 /* There is no master volume control. Set the master to max. */
4302 PDMAUDIOVOLUME vol = { false, 255, 255 };
4303 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
4304 AssertRC(rc);
4305 }
4306 }
4307
4308 if (RT_SUCCESS(rc))
4309 {
4310 /* Construct codec. */
4311 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
4312 if (!pThis->pCodec)
4313 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
4314
4315 /* Audio driver callbacks for multiplexing. */
4316 pThis->pCodec->pfnCloseIn = hdaCloseIn;
4317 pThis->pCodec->pfnCloseOut = hdaCloseOut;
4318 pThis->pCodec->pfnOpenIn = hdaOpenIn;
4319 pThis->pCodec->pfnOpenOut = hdaOpenOut;
4320 pThis->pCodec->pfnReset = hdaCodecReset;
4321 pThis->pCodec->pfnSetVolume = hdaSetVolume;
4322
4323 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
4324
4325 /* Construct the codec. */
4326 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
4327 if (RT_FAILURE(rc))
4328 AssertRCReturn(rc, rc);
4329
4330 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
4331 verb F20 should provide device/codec recognition. */
4332 Assert(pThis->pCodec->u16VendorId);
4333 Assert(pThis->pCodec->u16DeviceId);
4334 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
4335 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
4336 }
4337
4338 if (RT_SUCCESS(rc))
4339 {
4340 hdaReset(pDevIns);
4341
4342 /*
4343 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4344 * hdaReset shouldn't affects these registers.
4345 */
4346 HDA_REG(pThis, WAKEEN) = 0x0;
4347 HDA_REG(pThis, STATESTS) = 0x0;
4348
4349#ifdef DEBUG
4350 /*
4351 * Debug and string formatter types.
4352 */
4353 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
4354 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
4355 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
4356 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
4357 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaInfoMixer);
4358
4359 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
4360 AssertRC(rc);
4361 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
4362 AssertRC(rc);
4363 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
4364 AssertRC(rc);
4365 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
4366 AssertRC(rc);
4367 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
4368 AssertRC(rc);
4369#endif /* DEBUG */
4370
4371 /*
4372 * Some debug assertions.
4373 */
4374 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
4375 {
4376 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
4377 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
4378
4379 /* binary search order. */
4380 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
4381 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4382 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4383
4384 /* alignment. */
4385 AssertReleaseMsg( pReg->size == 1
4386 || (pReg->size == 2 && (pReg->offset & 1) == 0)
4387 || (pReg->size == 3 && (pReg->offset & 3) == 0)
4388 || (pReg->size == 4 && (pReg->offset & 3) == 0),
4389 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4390
4391 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
4392 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
4393 if (pReg->offset & 3)
4394 {
4395 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
4396 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4397 if (pPrevReg)
4398 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
4399 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4400 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
4401 }
4402#if 0
4403 if ((pReg->offset + pReg->size) & 3)
4404 {
4405 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4406 if (pNextReg)
4407 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
4408 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4409 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4410 }
4411#endif
4412 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
4413 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
4414 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4415 }
4416 }
4417
4418# ifndef VBOX_WITH_AUDIO_CALLBACKS
4419 if (RT_SUCCESS(rc))
4420 {
4421 /* Start the emulation timer. */
4422 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
4423 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
4424 AssertRCReturn(rc, rc);
4425
4426 if (RT_SUCCESS(rc))
4427 {
4428 /** @todo Investigate why sounds is getting corrupted if the "ticks" value is too
4429 * low, e.g. "PDMDevHlpTMTimeVirtGetFreq / 200". */
4430 pThis->uTimerTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 500; /** @todo Make this configurable! */
4431 pThis->uTimerTS = PDMDevHlpTMTimeVirtGet(pDevIns);
4432 if (pThis->uTimerTicks < 100)
4433 pThis->uTimerTicks = 100;
4434 LogFunc(("Timer ticks=%RU64\n", pThis->uTimerTicks));
4435
4436 /* Fire off timer. */
4437 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTimerTicks);
4438 }
4439 }
4440# else
4441 if (RT_SUCCESS(rc))
4442 {
4443 PHDADRIVER pDrv;
4444 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4445 {
4446 /* Only register primary driver.
4447 * The device emulation does the output multiplexing then. */
4448 if (pDrv->Flags != PDMAUDIODRVFLAG_PRIMARY)
4449 continue;
4450
4451 PDMAUDIOCALLBACK AudioCallbacks[2];
4452
4453 HDACALLBACKCTX Ctx = { pThis, pDrv };
4454
4455 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
4456 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
4457 AudioCallbacks[0].pvCtx = &Ctx;
4458 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
4459
4460 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
4461 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
4462 AudioCallbacks[1].pvCtx = &Ctx;
4463 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
4464
4465 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
4466 if (RT_FAILURE(rc))
4467 break;
4468 }
4469 }
4470# endif
4471
4472# ifdef VBOX_WITH_STATISTICS
4473 if (RT_SUCCESS(rc))
4474 {
4475 /*
4476 * Register statistics.
4477 */
4478# ifndef VBOX_WITH_AUDIO_CALLBACKS
4479 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
4480# endif
4481 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
4482 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
4483 }
4484# endif
4485
4486 LogFlowFuncLeaveRC(rc);
4487 return rc;
4488}
4489
4490/**
4491 * The device registration structure.
4492 */
4493const PDMDEVREG g_DeviceICH6_HDA =
4494{
4495 /* u32Version */
4496 PDM_DEVREG_VERSION,
4497 /* szName */
4498 "hda",
4499 /* szRCMod */
4500 "VBoxDDRC.rc",
4501 /* szR0Mod */
4502 "VBoxDDR0.r0",
4503 /* pszDescription */
4504 "Intel HD Audio Controller",
4505 /* fFlags */
4506 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
4507 /* fClass */
4508 PDM_DEVREG_CLASS_AUDIO,
4509 /* cMaxInstances */
4510 1,
4511 /* cbInstance */
4512 sizeof(HDASTATE),
4513 /* pfnConstruct */
4514 hdaConstruct,
4515 /* pfnDestruct */
4516 hdaDestruct,
4517 /* pfnRelocate */
4518 NULL,
4519 /* pfnMemSetup */
4520 NULL,
4521 /* pfnPowerOn */
4522 NULL,
4523 /* pfnReset */
4524 hdaReset,
4525 /* pfnSuspend */
4526 NULL,
4527 /* pfnResume */
4528 NULL,
4529 /* pfnAttach */
4530 NULL,
4531 /* pfnDetach */
4532 NULL,
4533 /* pfnQueryInterface. */
4534 NULL,
4535 /* pfnInitComplete */
4536 NULL,
4537 /* pfnPowerOff */
4538 NULL,
4539 /* pfnSoftReset */
4540 NULL,
4541 /* u32VersionEnd */
4542 PDM_DEVREG_VERSION
4543};
4544
4545#endif /* IN_RING3 */
4546#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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