VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 59275

Last change on this file since 59275 was 59275, checked in by vboxsync, 9 years ago

Audio: Don't crash if backend is unable to initialize (bugref:8180).
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1/* $Id: DevIchHda.cpp 59275 2016-01-07 11:57:56Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2016 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/list.h>
36#ifdef IN_RING3
37# include <iprt/mem.h>
38# include <iprt/semaphore.h>
39# include <iprt/string.h>
40# include <iprt/uuid.h>
41#endif
42
43#include "VBoxDD.h"
44
45#include "AudioMixBuffer.h"
46#include "AudioMixer.h"
47#include "DevIchHdaCodec.h"
48#include "DrvAudio.h"
49
50
51/*********************************************************************************************************************************
52* Defined Constants And Macros *
53*********************************************************************************************************************************/
54//#define HDA_AS_PCI_EXPRESS
55#define VBOX_WITH_INTEL_HDA
56
57#if (defined(DEBUG) && defined(DEBUG_andy))
58/* Enables experimental support for separate mic-in handling.
59 Do not enable this yet for regular builds, as this needs more testing first! */
60# define VBOX_WITH_HDA_MIC_IN
61#endif
62
63#if defined(VBOX_WITH_HP_HDA)
64/* HP Pavilion dv4t-1300 */
65# define HDA_PCI_VENDOR_ID 0x103c
66# define HDA_PCI_DEVICE_ID 0x30f7
67#elif defined(VBOX_WITH_INTEL_HDA)
68/* Intel HDA controller */
69# define HDA_PCI_VENDOR_ID 0x8086
70# define HDA_PCI_DEVICE_ID 0x2668
71#elif defined(VBOX_WITH_NVIDIA_HDA)
72/* nVidia HDA controller */
73# define HDA_PCI_VENDOR_ID 0x10de
74# define HDA_PCI_DEVICE_ID 0x0ac0
75#else
76# error "Please specify your HDA device vendor/device IDs"
77#endif
78
79/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
80 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
81 * is read only except for bit 15 like the HDA spec states.
82 *
83 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
84 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
85#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
86
87#define HDA_NREGS 114
88#define HDA_NREGS_SAVED 112
89
90/**
91 * NB: Register values stored in memory (au32Regs[]) are indexed through
92 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
93 * register descriptors in g_aHdaRegMap[] are indexed through the
94 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
95 *
96 * The au32Regs[] layout is kept unchanged for saved state
97 * compatibility. */
98
99/* Registers */
100#define HDA_REG_IND_NAME(x) HDA_REG_##x
101#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
102#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
103#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
104#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
105#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
106#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
107#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
108
109
110#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
111#define HDA_RMX_GCAP 0
112/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
113 * oss (15:12) - number of output streams supported
114 * iss (11:8) - number of input streams supported
115 * bss (7:3) - number of bidirectional streams supported
116 * bds (2:1) - number of serial data out signals supported
117 * b64sup (0) - 64 bit addressing supported.
118 */
119#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
120 ( (((oss) & 0xF) << 12) \
121 | (((iss) & 0xF) << 8) \
122 | (((bss) & 0x1F) << 3) \
123 | (((bds) & 0x3) << 2) \
124 | ((b64sup) & 1))
125
126#define HDA_REG_VMIN 1 /* 0x02 */
127#define HDA_RMX_VMIN 1
128
129#define HDA_REG_VMAJ 2 /* 0x03 */
130#define HDA_RMX_VMAJ 2
131
132#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
133#define HDA_RMX_OUTPAY 3
134
135#define HDA_REG_INPAY 4 /* 0x06-0x07 */
136#define HDA_RMX_INPAY 4
137
138#define HDA_REG_GCTL 5 /* 0x08-0x0B */
139#define HDA_RMX_GCTL 5
140#define HDA_GCTL_RST_SHIFT 0
141#define HDA_GCTL_FSH_SHIFT 1
142#define HDA_GCTL_UR_SHIFT 8
143
144#define HDA_REG_WAKEEN 6 /* 0x0C */
145#define HDA_RMX_WAKEEN 6
146
147#define HDA_REG_STATESTS 7 /* 0x0E */
148#define HDA_RMX_STATESTS 7
149#define HDA_STATES_SCSF 0x7
150
151#define HDA_REG_GSTS 8 /* 0x10-0x11*/
152#define HDA_RMX_GSTS 8
153#define HDA_GSTS_FSH_SHIFT 1
154
155#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
156#define HDA_RMX_OUTSTRMPAY 112
157
158#define HDA_REG_INSTRMPAY 10 /* 0x1a */
159#define HDA_RMX_INSTRMPAY 113
160
161#define HDA_REG_INTCTL 11 /* 0x20 */
162#define HDA_RMX_INTCTL 9
163#define HDA_INTCTL_GIE_SHIFT 31
164#define HDA_INTCTL_CIE_SHIFT 30
165#define HDA_INTCTL_S0_SHIFT 0
166#define HDA_INTCTL_S1_SHIFT 1
167#define HDA_INTCTL_S2_SHIFT 2
168#define HDA_INTCTL_S3_SHIFT 3
169#define HDA_INTCTL_S4_SHIFT 4
170#define HDA_INTCTL_S5_SHIFT 5
171#define HDA_INTCTL_S6_SHIFT 6
172#define HDA_INTCTL_S7_SHIFT 7
173#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
174
175#define HDA_REG_INTSTS 12 /* 0x24 */
176#define HDA_RMX_INTSTS 10
177#define HDA_INTSTS_GIS_SHIFT 31
178#define HDA_INTSTS_CIS_SHIFT 30
179#define HDA_INTSTS_S0_SHIFT 0
180#define HDA_INTSTS_S1_SHIFT 1
181#define HDA_INTSTS_S2_SHIFT 2
182#define HDA_INTSTS_S3_SHIFT 3
183#define HDA_INTSTS_S4_SHIFT 4
184#define HDA_INTSTS_S5_SHIFT 5
185#define HDA_INTSTS_S6_SHIFT 6
186#define HDA_INTSTS_S7_SHIFT 7
187#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
188
189#define HDA_REG_WALCLK 13 /* 0x24 */
190#define HDA_RMX_WALCLK /* Not defined! */
191
192/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
193 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
194 * the datasheet.
195 */
196#define HDA_REG_SSYNC 14 /* 0x34 */
197#define HDA_RMX_SSYNC 12
198
199#define HDA_REG_CORBLBASE 15 /* 0x40 */
200#define HDA_RMX_CORBLBASE 13
201
202#define HDA_REG_CORBUBASE 16 /* 0x44 */
203#define HDA_RMX_CORBUBASE 14
204
205#define HDA_REG_CORBWP 17 /* 0x48 */
206#define HDA_RMX_CORBWP 15
207
208#define HDA_REG_CORBRP 18 /* 0x4A */
209#define HDA_RMX_CORBRP 16
210#define HDA_CORBRP_RST_SHIFT 15
211#define HDA_CORBRP_WP_SHIFT 0
212#define HDA_CORBRP_WP_MASK 0xFF
213
214#define HDA_REG_CORBCTL 19 /* 0x4C */
215#define HDA_RMX_CORBCTL 17
216#define HDA_CORBCTL_DMA_SHIFT 1
217#define HDA_CORBCTL_CMEIE_SHIFT 0
218
219#define HDA_REG_CORBSTS 20 /* 0x4D */
220#define HDA_RMX_CORBSTS 18
221#define HDA_CORBSTS_CMEI_SHIFT 0
222
223#define HDA_REG_CORBSIZE 21 /* 0x4E */
224#define HDA_RMX_CORBSIZE 19
225#define HDA_CORBSIZE_SZ_CAP 0xF0
226#define HDA_CORBSIZE_SZ 0x3
227/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
228
229#define HDA_REG_RIRBLBASE 22 /* 0x50 */
230#define HDA_RMX_RIRBLBASE 20
231
232#define HDA_REG_RIRBUBASE 23 /* 0x54 */
233#define HDA_RMX_RIRBUBASE 21
234
235#define HDA_REG_RIRBWP 24 /* 0x58 */
236#define HDA_RMX_RIRBWP 22
237#define HDA_RIRBWP_RST_SHIFT 15
238#define HDA_RIRBWP_WP_MASK 0xFF
239
240#define HDA_REG_RINTCNT 25 /* 0x5A */
241#define HDA_RMX_RINTCNT 23
242#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
243
244#define HDA_REG_RIRBCTL 26 /* 0x5C */
245#define HDA_RMX_RIRBCTL 24
246#define HDA_RIRBCTL_RIC_SHIFT 0
247#define HDA_RIRBCTL_DMA_SHIFT 1
248#define HDA_ROI_DMA_SHIFT 2
249
250#define HDA_REG_RIRBSTS 27 /* 0x5D */
251#define HDA_RMX_RIRBSTS 25
252#define HDA_RIRBSTS_RINTFL_SHIFT 0
253#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
254
255#define HDA_REG_RIRBSIZE 28 /* 0x5E */
256#define HDA_RMX_RIRBSIZE 26
257#define HDA_RIRBSIZE_SZ_CAP 0xF0
258#define HDA_RIRBSIZE_SZ 0x3
259
260#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
261#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
262
263
264#define HDA_REG_IC 29 /* 0x60 */
265#define HDA_RMX_IC 27
266
267#define HDA_REG_IR 30 /* 0x64 */
268#define HDA_RMX_IR 28
269
270#define HDA_REG_IRS 31 /* 0x68 */
271#define HDA_RMX_IRS 29
272#define HDA_IRS_ICB_SHIFT 0
273#define HDA_IRS_IRV_SHIFT 1
274
275#define HDA_REG_DPLBASE 32 /* 0x70 */
276#define HDA_RMX_DPLBASE 30
277#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
278
279#define HDA_REG_DPUBASE 33 /* 0x74 */
280#define HDA_RMX_DPUBASE 31
281#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
282
283#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
284
285#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
286#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
287/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
288#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
289
290#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
291
292#define HDA_REG_SD0CTL 34 /* 0x80 */
293#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
294#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
295#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
296#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
297#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
298#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
299#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
300#define HDA_RMX_SD0CTL 32
301#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
302#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
303#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
304#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
305#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
306#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
307#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
308
309#define SD(func, num) SD##num##func
310
311#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
312#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
313#define HDA_SDCTL_NUM_MASK 0xF
314#define HDA_SDCTL_NUM_SHIFT 20
315#define HDA_SDCTL_DIR_SHIFT 19
316#define HDA_SDCTL_TP_SHIFT 18
317#define HDA_SDCTL_STRIPE_MASK 0x3
318#define HDA_SDCTL_STRIPE_SHIFT 16
319#define HDA_SDCTL_DEIE_SHIFT 4
320#define HDA_SDCTL_FEIE_SHIFT 3
321#define HDA_SDCTL_ICE_SHIFT 2
322#define HDA_SDCTL_RUN_SHIFT 1
323#define HDA_SDCTL_SRST_SHIFT 0
324
325#define HDA_REG_SD0STS 35 /* 0x83 */
326#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
327#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
328#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
329#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
330#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
331#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
332#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
333#define HDA_RMX_SD0STS 33
334#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
335#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
336#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
337#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
338#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
339#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
340#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
341
342#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
343#define HDA_SDSTS_FIFORDY_SHIFT 5
344#define HDA_SDSTS_DE_SHIFT 4
345#define HDA_SDSTS_FE_SHIFT 3
346#define HDA_SDSTS_BCIS_SHIFT 2
347
348#define HDA_REG_SD0LPIB 36 /* 0x84 */
349#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
350#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
351#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
352#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
353#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
354#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
355#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
356#define HDA_RMX_SD0LPIB 34
357#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
358#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
359#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
360#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
361#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
362#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
363#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
364
365#define HDA_REG_SD0CBL 37 /* 0x88 */
366#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
367#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
368#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
369#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
370#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
371#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
372#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
373#define HDA_RMX_SD0CBL 35
374#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
375#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
376#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
377#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
378#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
379#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
380#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
381
382#define HDA_REG_SD0LVI 38 /* 0x8C */
383#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
384#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
385#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
386#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
387#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
388#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
389#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
390#define HDA_RMX_SD0LVI 36
391#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
392#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
393#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
394#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
395#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
396#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
397#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
398
399#define HDA_REG_SD0FIFOW 39 /* 0x8E */
400#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
401#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
402#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
403#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
404#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
405#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
406#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
407#define HDA_RMX_SD0FIFOW 37
408#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
409#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
410#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
411#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
412#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
413#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
414#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
415
416/*
417 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
418 */
419#define HDA_SDFIFOW_8B 0x2
420#define HDA_SDFIFOW_16B 0x3
421#define HDA_SDFIFOW_32B 0x4
422
423#define HDA_REG_SD0FIFOS 40 /* 0x90 */
424#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
425#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
426#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
427#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
428#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
429#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
430#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
431#define HDA_RMX_SD0FIFOS 38
432#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
433#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
434#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
435#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
436#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
437#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
438#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
439
440/*
441 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
442 * formula: size - 1
443 * Other values not listed are not supported.
444 */
445#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
446#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
447
448#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
449#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
450#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
451#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
452#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
453#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
454#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
455
456#define HDA_REG_SD0FMT 41 /* 0x92 */
457#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
458#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
459#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
460#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
461#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
462#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
463#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
464#define HDA_RMX_SD0FMT 39
465#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
466#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
467#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
468#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
469#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
470#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
471#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
472
473#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
474#define HDA_SDFMT_BASE_RATE_SHIFT 14
475#define HDA_SDFMT_MULT_SHIFT 11
476#define HDA_SDFMT_MULT_MASK 0x7
477#define HDA_SDFMT_DIV_SHIFT 8
478#define HDA_SDFMT_DIV_MASK 0x7
479#define HDA_SDFMT_BITS_SHIFT 4
480#define HDA_SDFMT_BITS_MASK 0x7
481#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
482#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
483#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
484
485#define HDA_REG_SD0BDPL 42 /* 0x98 */
486#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
487#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
488#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
489#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
490#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
491#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
492#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
493#define HDA_RMX_SD0BDPL 40
494#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
495#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
496#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
497#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
498#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
499#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
500#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
501
502#define HDA_REG_SD0BDPU 43 /* 0x9C */
503#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
504#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
505#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
506#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
507#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
508#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
509#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
510#define HDA_RMX_SD0BDPU 41
511#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
512#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
513#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
514#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
515#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
516#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
517#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
518
519#define HDA_CODEC_CAD_SHIFT 28
520/* Encodes the (required) LUN into a codec command. */
521#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
522
523
524
525/*********************************************************************************************************************************
526* Structures and Typedefs *
527*********************************************************************************************************************************/
528
529/**
530 * Internal state of a Buffer Descriptor List Entry (BDLE),
531 * needed to keep track of the data needed for the actual device
532 * emulation.
533 */
534typedef struct HDABDLESTATE
535{
536 /** Own index within the BDL (Buffer Descriptor List). */
537 uint32_t u32BDLIndex;
538 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
539 * Used to check if we need fill up the FIFO again. */
540 uint32_t cbBelowFIFOW;
541 /** The buffer descriptor's internal DMA buffer. */
542 uint8_t au8FIFO[HDA_SDONFIFO_256B + 1];
543 /** Current offset in DMA buffer (in bytes).*/
544 uint32_t u32BufOff;
545 uint32_t Padding;
546} HDABDLESTATE, *PHDABDLESTATE;
547
548/**
549 * Buffer Descriptor List Entry (BDLE) (3.6.3).
550 *
551 * Contains only register values which do *not* change until a
552 * stream reset occurs.
553 */
554typedef struct HDABDLE
555{
556 /** Starting address of the actual buffer. Must be 128-bit aligned. */
557 uint64_t u64BufAdr;
558 /** Size of the actual buffer (in bytes). */
559 uint32_t u32BufSize;
560 /** Interrupt on completion; the controller will generate
561 * an interrupt when the last byte of the buffer has been
562 * fetched by the DMA engine. */
563 bool fIntOnCompletion;
564 /** Internal state of this BDLE.
565 * Not part of the actual BDLE registers. */
566 HDABDLESTATE State;
567} HDABDLE, *PHDABDLE;
568
569/**
570 * Internal state of a HDA stream.
571 */
572typedef struct HDASTREAMSTATE
573{
574 /** Number of BDLEs (Buffer Descriptor List Entry).
575 * Should be SDnLVI + 1 usually. */
576 uint16_t cBDLE;
577 /** Current BDLE to use. Wraps around to 0 if
578 * maximum (cBDLE) is reached. */
579 uint16_t uCurBDLE;
580 /** Stop indicator. */
581 volatile bool fDoStop;
582 /** Flag indicating whether this stream is in an
583 * active (operative) state or not. */
584 volatile bool fActive;
585 /** Flag indicating whether this stream currently is
586 * in reset mode and therefore not acccessible by the guest. */
587 volatile bool fInReset;
588 /** Unused, padding. */
589 bool fPadding;
590 /** Event signalling that the stream's state has been changed. */
591 RTSEMEVENT hStateChangedEvent;
592 /** Array of BDLEs. */
593 R3PTRTYPE(PHDABDLE) paBDLE;
594} HDASTREAMSTATE, *PHDASTREAMSTATE;
595
596/**
597 * Structure for keeping a HDA stream state.
598 *
599 * Contains only register values which do *not* change until a
600 * stream reset occurs.
601 */
602typedef struct HDASTREAM
603{
604 /** Stream number (SDn). */
605 uint8_t u8Strm;
606 uint8_t Padding0[7];
607 /** DMA base address (SDnBDPU - SDnBDPL). */
608 uint64_t u64BaseDMA;
609 /** Cyclic Buffer Length (SDnCBL).
610 * Represents the size of the ring buffer. */
611 uint32_t u32CBL;
612 /** Format (SDnFMT). */
613 uint16_t u16FMT;
614 /** FIFO Size (FIFOS).
615 * Maximum number of bytes that may have been DMA'd into
616 * memory but not yet transmitted on the link.
617 *
618 * Must be a power of two. */
619 uint16_t u16FIFOS;
620 /** Last Valid Index (SDnLVI). */
621 uint16_t u16LVI;
622 uint16_t Padding1[3];
623 /** Internal state of this stream. */
624 HDASTREAMSTATE State;
625} HDASTREAM, *PHDASTREAM;
626
627typedef struct HDAINPUTSTREAM
628{
629 /** PCM line input stream. */
630 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
631 /** Mixer handle for line input stream. */
632 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
633} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
634
635typedef struct HDAOUTPUTSTREAM
636{
637 /** PCM output stream. */
638 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
639 /** Mixer handle for line output stream. */
640 R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
641} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
642
643/**
644 * Struct for maintaining a host backend driver.
645 * This driver must be associated to one, and only one,
646 * HDA codec. The HDA controller does the actual multiplexing
647 * of HDA codec data to various host backend drivers then.
648 *
649 * This HDA device uses a timer in order to synchronize all
650 * read/write accesses across all attached LUNs / backends.
651 */
652typedef struct HDADRIVER
653{
654 /** Node for storing this driver in our device driver list of HDASTATE. */
655 RTLISTNODER3 Node;
656 /** Pointer to HDA controller (state). */
657 R3PTRTYPE(PHDASTATE) pHDAState;
658 /** Driver flags. */
659 PDMAUDIODRVFLAGS Flags;
660 uint8_t u32Padding0[3];
661 /** LUN to which this driver has been assigned. */
662 uint8_t uLUN;
663 /** Audio connector interface to the underlying
664 * host backend. */
665 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
666 /** Stream for line input. */
667 HDAINPUTSTREAM LineIn;
668 /** Stream for mic input. */
669 HDAINPUTSTREAM MicIn;
670 /** Stream for output. */
671 HDAOUTPUTSTREAM Out;
672} HDADRIVER;
673
674/**
675 * ICH Intel HD Audio Controller state.
676 */
677typedef struct HDASTATE
678{
679 /** The PCI device structure. */
680 PCIDevice PciDev;
681 /** R3 Pointer to the device instance. */
682 PPDMDEVINSR3 pDevInsR3;
683 /** R0 Pointer to the device instance. */
684 PPDMDEVINSR0 pDevInsR0;
685 /** R0 Pointer to the device instance. */
686 PPDMDEVINSRC pDevInsRC;
687 /** Padding for alignment. */
688 uint32_t u32Padding;
689 /** Pointer to the attached audio driver. */
690 R3PTRTYPE(PPDMIBASE) pDrvBase;
691 /** The base interface for LUN\#0. */
692 PDMIBASE IBase;
693 RTGCPHYS MMIOBaseAddr;
694 /** The HDA's register set. */
695 uint32_t au32Regs[HDA_NREGS];
696 /** Stream state for line-in. */
697 HDASTREAM StrmStLineIn;
698 /** Stream state for microphone-in. */
699 HDASTREAM StrmStMicIn;
700 /** Stream state for output. */
701 HDASTREAM StrmStOut;
702 /** CORB buffer base address. */
703 uint64_t u64CORBBase;
704 /** RIRB buffer base address. */
705 uint64_t u64RIRBBase;
706 /** DMA base address.
707 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
708 uint64_t u64DPBase;
709 /** DMA position buffer enable bit. */
710 bool fDMAPosition;
711 /** Padding for alignment. */
712 uint8_t u32Padding0[7];
713 /** Pointer to CORB buffer. */
714 R3PTRTYPE(uint32_t *) pu32CorbBuf;
715 /** Size in bytes of CORB buffer. */
716 uint32_t cbCorbBuf;
717 /** Padding for alignment. */
718 uint32_t u32Padding1;
719 /** Pointer to RIRB buffer. */
720 R3PTRTYPE(uint64_t *) pu64RirbBuf;
721 /** Size in bytes of RIRB buffer. */
722 uint32_t cbRirbBuf;
723 /** Indicates if HDA is in reset. */
724 bool fInReset;
725 /** Flag whether the R0 part is enabled. */
726 bool fR0Enabled;
727 /** Flag whether the RC part is enabled. */
728 bool fRCEnabled;
729#ifndef VBOX_WITH_AUDIO_CALLBACKS
730 /** The timer for pumping data thru the attached LUN drivers. */
731 PTMTIMERR3 pTimer;
732 /** The timer interval for pumping data thru the LUN drivers in timer ticks. */
733 uint64_t cTimerTicks;
734 /** Timestamp of the last timer callback (hdaTimer).
735 * Used to calculate the time actually elapsed between two timer callbacks. */
736 uint64_t uTimerTS;
737#endif
738#ifdef VBOX_WITH_STATISTICS
739# ifndef VBOX_WITH_AUDIO_CALLBACKS
740 STAMPROFILE StatTimer;
741# endif
742 STAMCOUNTER StatBytesRead;
743 STAMCOUNTER StatBytesWritten;
744#endif
745 /** Pointer to HDA codec to use. */
746 R3PTRTYPE(PHDACODEC) pCodec;
747 /** List of associated LUN drivers (HDADRIVER). */
748 RTLISTANCHORR3 lstDrv;
749 /** The device' software mixer. */
750 R3PTRTYPE(PAUDIOMIXER) pMixer;
751 /** Audio sink for PCM output. */
752 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
753 /** Audio mixer sink for line input. */
754 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
755 /** Audio mixer sink for microphone input. */
756 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
757 uint64_t u64BaseTS;
758 /** Response Interrupt Count (RINTCNT). */
759 uint8_t u8RespIntCnt;
760 /** Padding for alignment. */
761 uint8_t au8Padding2[7];
762} HDASTATE;
763/** Pointer to the ICH Intel HD Audio Controller state. */
764typedef HDASTATE *PHDASTATE;
765
766#ifdef VBOX_WITH_AUDIO_CALLBACKS
767typedef struct HDACALLBACKCTX
768{
769 PHDASTATE pThis;
770 PHDADRIVER pDriver;
771} HDACALLBACKCTX, *PHDACALLBACKCTX;
772#endif
773
774/*********************************************************************************************************************************
775* Internal Functions *
776*********************************************************************************************************************************/
777#ifndef VBOX_DEVICE_STRUCT_TESTCASE
778static FNPDMDEVRESET hdaReset;
779
780/*
781 * Stubs.
782 */
783static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
784static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
785
786/*
787 * Global register set read/write functions.
788 */
789static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
790static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
791static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
792static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
793static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
794static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
795static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
796static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
797static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
798static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
799static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
800static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
801static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
802static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
803static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
804
805/*
806 * {IOB}SDn read/write functions.
807 */
808static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
809static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
810static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
811static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
812static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
813static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
814static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
815static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
816static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
817
818/*
819 * Generic register read/write functions.
820 */
821static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
822static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
823static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
824static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
825static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
826static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
827static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
828static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
829
830#ifdef IN_RING3
831static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm);
832static void hdaStreamDestroy(PHDASTREAM pStrmSt);
833static int hdaStreamStart(PHDASTREAM pStrmSt);
834static int hdaStreamStop(PHDASTREAM pStrmSt);
835static int hdaStreamWaitForStateChange(PHDASTREAM pStrmSt, RTMSINTERVAL msTimeout);
836static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbToProcess, uint32_t *pcbProcessed);
837#endif
838
839#ifdef IN_RING3
840static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
841static void hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t u32LPIB);
842# ifdef LOG_ENABLED
843static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t u16LVI);
844# endif
845static void hdaBDLEReset(PHDABDLE pBDLE);
846#endif
847
848
849/*********************************************************************************************************************************
850* Global Variables *
851*********************************************************************************************************************************/
852
853/** Offset of the SD0 register map. */
854#define HDA_REG_DESC_SD0_BASE 0x80
855
856/** Turn a short global register name into an memory index and a stringized name. */
857#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
858
859/** Turns a short stream register name into an memory index and a stringized name. */
860#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
861
862/** Same as above for a register *not* stored in memory. */
863#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
864
865/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
866#define HDA_REG_MAP_STRM(offset, name) \
867 /* offset size read mask write mask read callback write callback index + abbrev description */ \
868 /* ------- ------- ---------- ---------- -------------- ----------------- ------------------------------ ----------- */ \
869 /* Offset 0x80 (SD0) */ \
870 { offset, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
871 /* Offset 0x83 (SD0) */ \
872 { offset + 0x3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
873 /* Offset 0x84 (SD0) */ \
874 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
875 /* Offset 0x88 (SD0) */ \
876 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
877 /* Offset 0x8C (SD0) */ \
878 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
879 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
880 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
881 /* Offset 0x90 (SD0) */ \
882 { offset + 0x10, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16, hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
883 /* Offset 0x92 (SD0) */ \
884 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Format" }, \
885 /* Reserved: 0x94 - 0x98. */ \
886 /* Offset 0x98 (SD0) */ \
887 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
888 /* Offset 0x9C (SD0) */ \
889 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
890
891/** Defines a single audio stream register set (e.g. OSD0). */
892#define HDA_REG_MAP_DEF_STREAM(index, name) \
893 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
894
895/* See 302349 p 6.2. */
896static const struct HDAREGDESC
897{
898 /** Register offset in the register space. */
899 uint32_t offset;
900 /** Size in bytes. Registers of size > 4 are in fact tables. */
901 uint32_t size;
902 /** Readable bits. */
903 uint32_t readable;
904 /** Writable bits. */
905 uint32_t writable;
906 /** Read callback. */
907 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
908 /** Write callback. */
909 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
910 /** Index into the register storage array. */
911 uint32_t mem_idx;
912 /** Abbreviated name. */
913 const char *abbrev;
914 /** Descripton. */
915 const char *desc;
916} g_aHdaRegMap[HDA_NREGS] =
917
918{
919 /* offset size read mask write mask read callback write callback index + abbrev */
920 /*------- ------- ---------- ---------- ----------------------- ---------------------- ---------------- */
921 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
922 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
923 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
924 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
925 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
926 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
927 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
928 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , HDA_REG_IDX(STATESTS) }, /* State Change Status */
929 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
930 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
931 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
932 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
933 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
934 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
935 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
936 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
937 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
938 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
939 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
940 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
941 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
942 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
943 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
944 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
945 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
946 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
947 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
948 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
949 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
950 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
951 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
952 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
953 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
954 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
955 /* 4 Input Stream Descriptors (ISD). */
956 HDA_REG_MAP_DEF_STREAM(0, SD0),
957 HDA_REG_MAP_DEF_STREAM(1, SD1),
958 HDA_REG_MAP_DEF_STREAM(2, SD2),
959 HDA_REG_MAP_DEF_STREAM(3, SD3),
960 /* 4 Output Stream Descriptors (OSD). */
961 HDA_REG_MAP_DEF_STREAM(4, SD4),
962 HDA_REG_MAP_DEF_STREAM(5, SD5),
963 HDA_REG_MAP_DEF_STREAM(6, SD6),
964 HDA_REG_MAP_DEF_STREAM(7, SD7)
965};
966
967/**
968 * HDA register aliases (HDA spec 3.3.45).
969 * @remarks Sorted by offReg.
970 */
971static const struct
972{
973 /** The alias register offset. */
974 uint32_t offReg;
975 /** The register index. */
976 int idxAlias;
977} g_aHdaRegAliases[] =
978{
979 { 0x2084, HDA_REG_SD0LPIB },
980 { 0x20a4, HDA_REG_SD1LPIB },
981 { 0x20c4, HDA_REG_SD2LPIB },
982 { 0x20e4, HDA_REG_SD3LPIB },
983 { 0x2104, HDA_REG_SD4LPIB },
984 { 0x2124, HDA_REG_SD5LPIB },
985 { 0x2144, HDA_REG_SD6LPIB },
986 { 0x2164, HDA_REG_SD7LPIB },
987};
988
989#ifdef IN_RING3
990/** HDABDLESTATE field descriptors for the v5+ saved state. */
991static SSMFIELD const g_aSSMBDLEStateFields5[] =
992{
993 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
994 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
995 SSMFIELD_ENTRY(HDABDLESTATE, au8FIFO),
996 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
997 SSMFIELD_ENTRY_TERM()
998};
999
1000/** HDASTREAMSTATE field descriptors for the v5+ saved state. */
1001static SSMFIELD const g_aSSMStreamStateFields5[] =
1002{
1003 SSMFIELD_ENTRY (HDASTREAMSTATE, cBDLE),
1004 SSMFIELD_ENTRY (HDASTREAMSTATE, uCurBDLE),
1005 SSMFIELD_ENTRY_IGNORE(HDASTREAMSTATE, paBDLE),
1006 SSMFIELD_ENTRY_TERM()
1007};
1008#endif
1009
1010/**
1011 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1012 */
1013static uint32_t const g_afMasks[5] =
1014{
1015 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1016};
1017
1018#ifdef IN_RING3
1019DECLINLINE(void) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t u32LPIB)
1020{
1021 AssertPtrReturnVoid(pThis);
1022 AssertPtrReturnVoid(pStrmSt);
1023
1024 Assert(u32LPIB <= pStrmSt->u32CBL);
1025
1026 LogFlowFunc(("uStrm=%RU8, LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1027 pStrmSt->u8Strm, u32LPIB, pThis->fDMAPosition));
1028
1029 /* Update LPIB in any case. */
1030 HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) = u32LPIB;
1031
1032 /* Do we need to tell the current DMA position? */
1033 if (pThis->fDMAPosition)
1034 {
1035 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1036 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStrmSt->u8Strm * 8),
1037 (void *)&u32LPIB, sizeof(uint32_t));
1038 AssertRC(rc2);
1039 }
1040}
1041#endif
1042
1043/**
1044 * Retrieves the number of bytes of a FIFOS register.
1045 *
1046 * @return Number of bytes of a given FIFOS register.
1047 */
1048DECLINLINE(uint16_t) hdaSDFIFOSToBytes(uint32_t u32RegFIFOS)
1049{
1050 uint16_t cb;
1051 switch (u32RegFIFOS)
1052 {
1053 /* Input */
1054 case HDA_SDINFIFO_120B: cb = 120; break;
1055 case HDA_SDINFIFO_160B: cb = 160; break;
1056
1057 /* Output */
1058 case HDA_SDONFIFO_16B: cb = 16; break;
1059 case HDA_SDONFIFO_32B: cb = 32; break;
1060 case HDA_SDONFIFO_64B: cb = 64; break;
1061 case HDA_SDONFIFO_128B: cb = 128; break;
1062 case HDA_SDONFIFO_192B: cb = 192; break;
1063 case HDA_SDONFIFO_256B: cb = 256; break;
1064 default:
1065 {
1066 cb = 0; /* Can happen on stream reset. */
1067 break;
1068 }
1069 }
1070
1071 return cb;
1072}
1073
1074/**
1075 * Retrieves the number of bytes of a FIFOW register.
1076 *
1077 * @return Number of bytes of a given FIFOW register.
1078 */
1079DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1080{
1081 uint32_t cb;
1082 switch (u32RegFIFOW)
1083 {
1084 case HDA_SDFIFOW_8B: cb = 8; break;
1085 case HDA_SDFIFOW_16B: cb = 16; break;
1086 case HDA_SDFIFOW_32B: cb = 32; break;
1087 default: cb = 0; break;
1088 }
1089
1090#ifdef RT_STRICT
1091 Assert(RT_IS_POWER_OF_TWO(cb));
1092#endif
1093 return cb;
1094}
1095
1096#ifdef IN_RING3
1097/**
1098 * Returns the current BDLE to use for a stream.
1099 *
1100 * @return BDLE to use, NULL if none found.
1101 */
1102DECLINLINE(PHDABDLE) hdaStreamGetCurrentBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
1103{
1104 AssertPtrReturn(pThis, NULL);
1105 AssertPtrReturn(pStrmSt, NULL);
1106
1107 Assert(pStrmSt->State.paBDLE);
1108 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1109
1110 PHDABDLE pBDLE = &pStrmSt->State.paBDLE[pStrmSt->State.uCurBDLE];
1111 return pBDLE;
1112}
1113
1114/**
1115 * Returns the next BDLE to use for a stream.
1116 *
1117 * @return BDLE to use next, NULL if none found.
1118 */
1119DECLINLINE(PHDABDLE) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
1120{
1121 AssertPtrReturn(pThis, NULL);
1122 AssertPtrReturn(pStrmSt, NULL);
1123
1124 NOREF(pThis);
1125
1126 Assert(pStrmSt->State.paBDLE);
1127 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1128
1129#ifdef DEBUG
1130 uint32_t uOldBDLE = pStrmSt->State.uCurBDLE;
1131#endif
1132
1133 /*
1134 * Switch to the next BDLE entry and do a wrap around
1135 * if we reached the end of the Buffer Descriptor List (BDL).
1136 */
1137 pStrmSt->State.uCurBDLE++;
1138 if (pStrmSt->State.uCurBDLE == pStrmSt->State.cBDLE)
1139 {
1140 pStrmSt->State.uCurBDLE = 0;
1141
1142 hdaStreamUpdateLPIB(pThis, pStrmSt, 0);
1143 }
1144
1145 Assert(pStrmSt->State.uCurBDLE < pStrmSt->State.cBDLE);
1146
1147 PHDABDLE pBDLE = &pStrmSt->State.paBDLE[pStrmSt->State.uCurBDLE];
1148 AssertPtr(pBDLE);
1149
1150 hdaBDLEReset(pBDLE);
1151
1152#ifdef DEBUG
1153 LogFlowFunc(("[SD%RU8]: uOldBDLE=%RU16, uCurBDLE=%RU16, cBDLE=%RU32, %R[bdle]\n",
1154 pStrmSt->u8Strm, uOldBDLE, pStrmSt->State.uCurBDLE, pStrmSt->State.cBDLE, pBDLE));
1155#endif
1156 return pBDLE;
1157}
1158#endif
1159
1160/**
1161 * Retrieves the minimum number of bytes accumulated/free in the
1162 * FIFO before the controller will start a fetch/eviction of data.
1163 *
1164 * Uses SDFIFOW (FIFO Watermark Register).
1165 *
1166 * @return Number of bytes accumulated/free in the FIFO.
1167 */
1168DECLINLINE(uint8_t) hdaStreamGetFIFOW(PHDASTATE pThis, PHDASTREAM pStrmSt)
1169{
1170 AssertPtrReturn(pThis, 0);
1171 AssertPtrReturn(pStrmSt, 0);
1172
1173#ifdef VBOX_HDA_WITH_FIFO
1174 return hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, pStrmSt->u8Strm));
1175#else
1176 return 0;
1177#endif
1178}
1179
1180static int hdaProcessInterrupt(PHDASTATE pThis)
1181{
1182#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1183 ( INTCTL_SX((pThis), num) \
1184 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1185
1186 bool fIrq = false;
1187
1188 if (/* Controller Interrupt Enable (CIE). */
1189 HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1190 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1191 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1192 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1193 fIrq = true;
1194
1195 /** @todo Don't hardcode stream numbers here. */
1196 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1197 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1198 {
1199#ifdef IN_RING3
1200 LogFunc(("BCIS\n"));
1201#endif
1202 fIrq = true;
1203 }
1204
1205 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1206 {
1207 LogFunc(("%s\n", fIrq ? "Asserted" : "Deasserted"));
1208 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1209 }
1210
1211#undef IS_INTERRUPT_OCCURED_AND_ENABLED
1212
1213 return VINF_SUCCESS;
1214}
1215
1216/**
1217 * Looks up a register at the exact offset given by @a offReg.
1218 *
1219 * @returns Register index on success, -1 if not found.
1220 * @param pThis The HDA device state.
1221 * @param offReg The register offset.
1222 */
1223static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1224{
1225 /*
1226 * Aliases.
1227 */
1228 if (offReg >= g_aHdaRegAliases[0].offReg)
1229 {
1230 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1231 if (offReg == g_aHdaRegAliases[i].offReg)
1232 return g_aHdaRegAliases[i].idxAlias;
1233 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1234 return -1;
1235 }
1236
1237 /*
1238 * Binary search the
1239 */
1240 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1241 int idxLow = 0;
1242 for (;;)
1243 {
1244 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1245 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1246 {
1247 if (idxLow == idxMiddle)
1248 break;
1249 idxEnd = idxMiddle;
1250 }
1251 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1252 {
1253 idxLow = idxMiddle + 1;
1254 if (idxLow >= idxEnd)
1255 break;
1256 }
1257 else
1258 return idxMiddle;
1259 }
1260
1261#ifdef RT_STRICT
1262 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1263 Assert(g_aHdaRegMap[i].offset != offReg);
1264#endif
1265 return -1;
1266}
1267
1268/**
1269 * Looks up a register covering the offset given by @a offReg.
1270 *
1271 * @returns Register index on success, -1 if not found.
1272 * @param pThis The HDA device state.
1273 * @param offReg The register offset.
1274 */
1275static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1276{
1277 /*
1278 * Aliases.
1279 */
1280 if (offReg >= g_aHdaRegAliases[0].offReg)
1281 {
1282 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1283 {
1284 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1285 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1286 return g_aHdaRegAliases[i].idxAlias;
1287 }
1288 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1289 return -1;
1290 }
1291
1292 /*
1293 * Binary search the register map.
1294 */
1295 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1296 int idxLow = 0;
1297 for (;;)
1298 {
1299 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1300 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1301 {
1302 if (idxLow == idxMiddle)
1303 break;
1304 idxEnd = idxMiddle;
1305 }
1306 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1307 {
1308 idxLow = idxMiddle + 1;
1309 if (idxLow >= idxEnd)
1310 break;
1311 }
1312 else
1313 return idxMiddle;
1314 }
1315
1316#ifdef RT_STRICT
1317 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1318 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1319#endif
1320 return -1;
1321}
1322
1323#ifdef IN_RING3
1324static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1325{
1326 int rc = VINF_SUCCESS;
1327 if (fLocal)
1328 {
1329 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1330 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1331 if (RT_FAILURE(rc))
1332 AssertRCReturn(rc, rc);
1333#ifdef DEBUG_CMD_BUFFER
1334 uint8_t i = 0;
1335 do
1336 {
1337 LogFunc(("CORB%02x: ", i));
1338 uint8_t j = 0;
1339 do
1340 {
1341 const char *pszPrefix;
1342 if ((i + j) == HDA_REG(pThis, CORBRP));
1343 pszPrefix = "[R]";
1344 else if ((i + j) == HDA_REG(pThis, CORBWP));
1345 pszPrefix = "[W]";
1346 else
1347 pszPrefix = " "; /* three spaces */
1348 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1349 j++;
1350 } while (j < 8);
1351 LogFunc(("\n"));
1352 i += 8;
1353 } while(i != 0);
1354#endif
1355 }
1356 else
1357 {
1358 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1359 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1360 if (RT_FAILURE(rc))
1361 AssertRCReturn(rc, rc);
1362#ifdef DEBUG_CMD_BUFFER
1363 uint8_t i = 0;
1364 do {
1365 LogFunc(("RIRB%02x: ", i));
1366 uint8_t j = 0;
1367 do {
1368 const char *prefix;
1369 if ((i + j) == HDA_REG(pThis, RIRBWP))
1370 prefix = "[W]";
1371 else
1372 prefix = " ";
1373 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1374 } while (++j < 8);
1375 LogFunc(("\n"));
1376 i += 8;
1377 } while (i != 0);
1378#endif
1379 }
1380 return rc;
1381}
1382
1383static int hdaCORBCmdProcess(PHDASTATE pThis)
1384{
1385 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1386
1387 int rc = hdaCmdSync(pThis, true);
1388 if (RT_FAILURE(rc))
1389 AssertRCReturn(rc, rc);
1390
1391 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1392 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1393 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1394
1395 Assert((corbWp != corbRp));
1396 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1397
1398 while (corbRp != corbWp)
1399 {
1400 uint32_t cmd;
1401 uint64_t resp;
1402 pfn = NULL;
1403 corbRp++;
1404 cmd = pThis->pu32CorbBuf[corbRp];
1405
1406 rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* Codec index */), &pfn);
1407 if (RT_SUCCESS(rc))
1408 {
1409 AssertPtr(pfn);
1410 rc = pfn(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1411 }
1412
1413 if (RT_FAILURE(rc))
1414 AssertRCReturn(rc, rc);
1415 (rirbWp)++;
1416
1417 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1418 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1419 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1420 {
1421 LogFunc(("unexpected unsolicited response.\n"));
1422 HDA_REG(pThis, CORBRP) = corbRp;
1423 return rc;
1424 }
1425
1426 pThis->pu64RirbBuf[rirbWp] = resp;
1427
1428 pThis->u8RespIntCnt++;
1429 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1430 break;
1431 }
1432 HDA_REG(pThis, CORBRP) = corbRp;
1433 HDA_REG(pThis, RIRBWP) = rirbWp;
1434 rc = hdaCmdSync(pThis, false);
1435 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1436 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1437 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1438 {
1439 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1440
1441 pThis->u8RespIntCnt = 0;
1442 rc = hdaProcessInterrupt(pThis);
1443 }
1444 if (RT_FAILURE(rc))
1445 AssertRCReturn(rc, rc);
1446 return rc;
1447}
1448
1449static int hdaStreamCreate(PHDASTREAM pStrmSt)
1450{
1451 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1452
1453 int rc = RTSemEventCreate(&pStrmSt->State.hStateChangedEvent);
1454 AssertRC(rc);
1455
1456 pStrmSt->State.fActive = false;
1457 pStrmSt->State.fInReset = false;
1458 pStrmSt->State.fDoStop = false;
1459
1460 LogFlowFuncLeaveRC(rc);
1461 return rc;
1462}
1463
1464static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1465{
1466 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1467 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1468
1469 pStrmSt->u8Strm = u8Strm;
1470 pStrmSt->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
1471 HDA_STREAM_REG(pThis, BDPU, u8Strm));
1472 pStrmSt->u16LVI = HDA_STREAM_REG(pThis, LVI, u8Strm);
1473 pStrmSt->u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1474 pStrmSt->u16FIFOS = hdaSDFIFOSToBytes(HDA_STREAM_REG(pThis, FIFOS, u8Strm));
1475
1476 int rc = VINF_SUCCESS;
1477
1478 if (pStrmSt->State.paBDLE)
1479 {
1480 Assert(pStrmSt->State.cBDLE);
1481 RTMemFree(pStrmSt->State.paBDLE);
1482 pStrmSt->State.paBDLE = NULL;
1483 }
1484
1485 pStrmSt->State.cBDLE = 0;
1486
1487 if (pStrmSt->u16LVI) /* Any BDLEs to fetch? */
1488 {
1489 AssertMsg(pStrmSt->u64BaseDMA, ("No base DMA address set for stream %RU8\n", u8Strm));
1490
1491 uint32_t cbBDLE = 0;
1492
1493 pStrmSt->State.cBDLE = pStrmSt->u16LVI + 1; /* See 18.2.37: If LVI is n, then there are n + 1 entries. */
1494 pStrmSt->State.paBDLE = (PHDABDLE)RTMemAllocZ(sizeof(HDABDLE) * pStrmSt->State.cBDLE);
1495 if (pStrmSt->State.paBDLE)
1496 {
1497 for (uint16_t i = 0; i < pStrmSt->State.cBDLE; i++)
1498 {
1499 rc = hdaBDLEFetch(pThis, &pStrmSt->State.paBDLE[i], pStrmSt->u64BaseDMA, i);
1500 if (RT_FAILURE(rc))
1501 break;
1502
1503 cbBDLE += pStrmSt->State.paBDLE[i].u32BufSize;
1504 }
1505
1506#ifdef DEBUG
1507 hdaBDLEDumpAll(pThis, pStrmSt->u64BaseDMA, pStrmSt->State.cBDLE);
1508#endif
1509 if (RT_SUCCESS(rc))
1510 {
1511 if (pStrmSt->u32CBL != cbBDLE)
1512 {
1513 AssertMsgFailed(("CBL (%RU32) does not match BDL entries (%RU32)\n", pStrmSt->u32CBL, cbBDLE));
1514 LogRel(("HDA: Warning: CBL (%RU32) does not match BDL entries (%RU32); expect sound hickups\n",
1515 pStrmSt->u32CBL, cbBDLE));
1516 }
1517
1518 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1519 }
1520 }
1521 else
1522 rc = VERR_NO_MEMORY;
1523 }
1524
1525 LogFunc(("[SD%RU8]: DMA=0x%x, LVI=%RU16, CBL=%RU32, FIFOS=%RU16\n",
1526 u8Strm, pStrmSt->u64BaseDMA, pStrmSt->u16LVI, pStrmSt->u32CBL, pStrmSt->u16FIFOS));
1527
1528 return rc;
1529}
1530
1531static void hdaStreamDestroy(PHDASTREAM pStrmSt)
1532{
1533 AssertPtrReturnVoid(pStrmSt);
1534
1535 LogFlowFuncEnter();
1536
1537 int rc2 = hdaStreamStop(pStrmSt);
1538 AssertRC(rc2);
1539
1540 if (pStrmSt->State.hStateChangedEvent != NIL_RTSEMEVENT)
1541 {
1542 rc2 = RTSemEventDestroy(pStrmSt->State.hStateChangedEvent);
1543 AssertRC(rc2);
1544 }
1545
1546 /*
1547 * Destroy.
1548 */
1549 if (pStrmSt->State.paBDLE)
1550 {
1551 Assert(pStrmSt->State.cBDLE);
1552 RTMemFree(pStrmSt->State.paBDLE);
1553 pStrmSt->State.paBDLE = NULL;
1554 }
1555
1556 pStrmSt->State.cBDLE = 0;
1557
1558 LogFlowFuncLeave();
1559}
1560
1561static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1562{
1563 AssertPtrReturnVoid(pThis);
1564 AssertPtrReturnVoid(pStrmSt);
1565 AssertReturnVoid(u8Strm <= 7); /** @todo Use a define for MAX_STREAMS! */
1566
1567#ifdef VBOX_STRICT
1568 AssertReleaseMsg(!RT_BOOL(HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
1569 ("Cannot reset stream %RU8 while in running state\n", u8Strm));
1570#endif
1571
1572 /*
1573 * Set reset state.
1574 */
1575 Assert(ASMAtomicReadBool(&pStrmSt->State.fInReset) == false); /* No nested calls. */
1576 ASMAtomicXchgBool(&pStrmSt->State.fInReset, true);
1577
1578 /*
1579 * First, reset the internal stream state.
1580 */
1581 pStrmSt->u8Strm = u8Strm;
1582 pStrmSt->u64BaseDMA = 0;
1583 pStrmSt->u32CBL = 0;
1584 pStrmSt->u16FMT = 0;
1585 pStrmSt->u16FIFOS = 0;
1586 pStrmSt->u16LVI = 0;
1587
1588 /*
1589 * Second, initialize the registers.
1590 */
1591 HDA_STREAM_REG(pThis, STS, u8Strm) = 0;
1592 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1593 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1594 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1595 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39. */
1596 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1597 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1598 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = HDA_SDFIFOW_32B;
1599 HDA_STREAM_REG(pThis, LPIB, u8Strm) = 0;
1600 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1601 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1602 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1603 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1604 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1605
1606 /* Report that we're done resetting this stream. */
1607 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
1608
1609 LogFunc(("[SD%RU8]: Reset\n", u8Strm));
1610
1611 /* Exit reset mode. */
1612 ASMAtomicXchgBool(&pStrmSt->State.fInReset, false);
1613}
1614
1615static int hdaStreamStart(PHDASTREAM pStrmSt)
1616{
1617 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1618
1619 ASMAtomicXchgBool(&pStrmSt->State.fDoStop, false);
1620 ASMAtomicXchgBool(&pStrmSt->State.fActive, true);
1621
1622 LogFlowFuncLeave();
1623 return VINF_SUCCESS;
1624}
1625
1626static int hdaStreamStop(PHDASTREAM pStrmSt)
1627{
1628 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1629
1630 /* Already in stopped state? */
1631 bool fActive = ASMAtomicReadBool(&pStrmSt->State.fActive);
1632 if (!fActive)
1633 return VINF_SUCCESS;
1634
1635#if 0 /** @todo Does not work (yet), as EMT deadlocks then. */
1636 /*
1637 * Wait for the stream to stop.
1638 */
1639 ASMAtomicXchgBool(&pStrmSt->State.fDoStop, true);
1640
1641 int rc = hdaStreamWaitForStateChange(pStrmSt, 60 * 1000 /* ms timeout */);
1642 fActive = ASMAtomicReadBool(&pStrmSt->State.fActive);
1643 if ( /* Waiting failed? */
1644 RT_FAILURE(rc)
1645 /* Stream is still active? */
1646 || fActive)
1647 {
1648 AssertRC(rc);
1649 LogRel(("HDA: Warning: Unable to stop stream %RU8 (state: %s), rc=%Rrc\n",
1650 pStrmSt->u8Strm, fActive ? "active" : "stopped", rc));
1651 }
1652#else
1653 int rc = VINF_SUCCESS;
1654#endif
1655
1656 LogFlowFuncLeaveRC(rc);
1657 return rc;
1658}
1659
1660static int hdaStreamWaitForStateChange(PHDASTREAM pStrmSt, RTMSINTERVAL msTimeout)
1661{
1662 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1663
1664 LogFlowFunc(("[SD%RU8]: msTimeout=%RU32\n", pStrmSt->u8Strm, msTimeout));
1665 return RTSemEventWait(pStrmSt->State.hStateChangedEvent, msTimeout);
1666}
1667#endif /* IN_RING3 */
1668
1669/* Register access handlers. */
1670
1671static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1672{
1673 *pu32Value = 0;
1674 return VINF_SUCCESS;
1675}
1676
1677static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1678{
1679 return VINF_SUCCESS;
1680}
1681
1682/* U8 */
1683static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1684{
1685 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1686 return hdaRegReadU32(pThis, iReg, pu32Value);
1687}
1688
1689static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1690{
1691 Assert((u32Value & 0xffffff00) == 0);
1692 return hdaRegWriteU32(pThis, iReg, u32Value);
1693}
1694
1695/* U16 */
1696static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1697{
1698 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1699 return hdaRegReadU32(pThis, iReg, pu32Value);
1700}
1701
1702static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1703{
1704 Assert((u32Value & 0xffff0000) == 0);
1705 return hdaRegWriteU32(pThis, iReg, u32Value);
1706}
1707
1708/* U24 */
1709static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1710{
1711 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1712 return hdaRegReadU32(pThis, iReg, pu32Value);
1713}
1714
1715static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1716{
1717 Assert((u32Value & 0xff000000) == 0);
1718 return hdaRegWriteU32(pThis, iReg, u32Value);
1719}
1720
1721/* U32 */
1722static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1723{
1724 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1725
1726 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1727 return VINF_SUCCESS;
1728}
1729
1730static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1731{
1732 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1733
1734 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1735 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1736 return VINF_SUCCESS;
1737}
1738
1739static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1740{
1741 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1742 {
1743 /* Set the CRST bit to indicate that we're leaving reset mode. */
1744 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1745
1746 if (pThis->fInReset)
1747 {
1748 LogFunc(("Leaving reset\n"));
1749 pThis->fInReset = false;
1750 }
1751 }
1752 else
1753 {
1754#ifdef IN_RING3
1755 /* Enter reset state. */
1756 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1757 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1758 {
1759 LogFunc(("Entering reset with DMA(RIRB:%s, CORB:%s)\n",
1760 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1761 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1762 }
1763
1764 /* Clear the CRST bit to indicate that we're in reset mode. */
1765 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1766 pThis->fInReset = true;
1767
1768 /* As the CRST bit now is set, we now can proceed resetting stuff. */
1769 hdaReset(pThis->CTX_SUFF(pDevIns));
1770#else
1771 return VINF_IOM_R3_MMIO_WRITE;
1772#endif
1773 }
1774 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1775 {
1776 /* Flush: GSTS:1 set, see 6.2.6. */
1777 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
1778 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1779 }
1780 return VINF_SUCCESS;
1781}
1782
1783static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1784{
1785 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1786
1787 uint32_t v = pThis->au32Regs[iRegMem];
1788 uint32_t nv = u32Value & HDA_STATES_SCSF;
1789 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1790 return VINF_SUCCESS;
1791}
1792
1793static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1794{
1795 uint32_t v = 0;
1796 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1797 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1798 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1799 || HDA_REG(pThis, STATESTS))
1800 {
1801 v |= RT_BIT(30); /* Touch CIS. */
1802 }
1803
1804#define HDA_IS_STREAM_EVENT(pThis, num) \
1805 ( (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1806 || (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1807 || (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1808
1809#define HDA_MARK_STREAM(pThis, num, v) \
1810 do { (v) |= HDA_IS_STREAM_EVENT((pThis), num) ? RT_BIT((num)) : 0; } while(0)
1811
1812 HDA_MARK_STREAM(pThis, 0, v);
1813 HDA_MARK_STREAM(pThis, 1, v);
1814 HDA_MARK_STREAM(pThis, 2, v);
1815 HDA_MARK_STREAM(pThis, 3, v);
1816 HDA_MARK_STREAM(pThis, 4, v);
1817 HDA_MARK_STREAM(pThis, 5, v);
1818 HDA_MARK_STREAM(pThis, 6, v);
1819 HDA_MARK_STREAM(pThis, 7, v);
1820
1821#undef HDA_IS_STREAM_EVENT
1822#undef HDA_MARK_STREAM
1823
1824 v |= v ? RT_BIT(31) : 0;
1825
1826 *pu32Value = v;
1827 return VINF_SUCCESS;
1828}
1829
1830static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1831{
1832 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1833 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1834 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1835
1836 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
1837
1838 *pu32Value = u32LPIB;
1839 return VINF_SUCCESS;
1840}
1841
1842static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1843{
1844 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1845 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1846 - pThis->u64BaseTS, 24, 1000);
1847 LogFlowFunc(("%RU32\n", *pu32Value));
1848 return VINF_SUCCESS;
1849}
1850
1851static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1852{
1853 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1854 {
1855 HDA_REG(pThis, CORBRP) = 0;
1856 }
1857#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1858 else
1859 return hdaRegWriteU8(pThis, iReg, u32Value);
1860#endif
1861 return VINF_SUCCESS;
1862}
1863
1864static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1865{
1866#ifdef IN_RING3
1867 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1868 AssertRC(rc);
1869 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1870 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1871 {
1872 return hdaCORBCmdProcess(pThis);
1873 }
1874 return rc;
1875#else
1876 return VINF_IOM_R3_MMIO_WRITE;
1877#endif
1878}
1879
1880static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1881{
1882 uint32_t v = HDA_REG(pThis, CORBSTS);
1883 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1884 return VINF_SUCCESS;
1885}
1886
1887static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1888{
1889#ifdef IN_RING3
1890 int rc;
1891 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1892 if (RT_FAILURE(rc))
1893 AssertRCReturn(rc, rc);
1894 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1895 return VINF_SUCCESS;
1896 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1897 return VINF_SUCCESS;
1898 rc = hdaCORBCmdProcess(pThis);
1899 return rc;
1900#else
1901 return VINF_IOM_R3_MMIO_WRITE;
1902#endif
1903}
1904
1905static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1906{
1907 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CBL, iReg);
1908 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1909
1910 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32Value));
1911
1912 return hdaRegWriteU32(pThis, iReg, u32Value);
1913}
1914
1915static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1916{
1917 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1918 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1919 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1920 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1921
1922 uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1923
1924 PHDASTREAM pStrmSt;
1925 switch (u8Strm)
1926 {
1927 case 0: /** @todo Use dynamic indices, based on stream assignment. */
1928 {
1929 pStrmSt = &pThis->StrmStLineIn;
1930 break;
1931 }
1932# ifdef VBOX_WITH_HDA_MIC_IN
1933 case 2: /** @todo Use dynamic indices, based on stream assignment. */
1934 {
1935 pStrmSt = &pThis->StrmStMicIn;
1936 break;
1937 }
1938# endif
1939 case 4: /** @todo Use dynamic indices, based on stream assignment. */
1940 {
1941 pStrmSt = &pThis->StrmStOut;
1942 break;
1943 }
1944
1945 default:
1946 {
1947 LogFunc(("Warning: Changing SDCTL on non-attached stream (iReg=0x%x)\n", iReg));
1948 return hdaRegWriteU24(pThis, iReg, u32Value); /* Write 3 bytes. */
1949 }
1950 }
1951
1952 LogFunc(("[SD%RU8]: fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
1953 u8Strm, fRun, fInRun, fReset, fInReset, u32Value));
1954
1955 if (fInReset)
1956 {
1957 /* Guest is resetting HDA's stream, we're expecting guest will mark stream as exit. */
1958 Assert(!fReset);
1959 LogFunc(("Guest initiated exit of stream reset\n"));
1960 }
1961 else if (fReset)
1962 {
1963#ifdef IN_RING3
1964 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1965 Assert(!fInRun && !fRun);
1966
1967 LogFunc(("Guest initiated enter to stream reset\n"));
1968 hdaStreamReset(pThis, pStrmSt, u8Strm);
1969#else
1970 return VINF_IOM_R3_MMIO_WRITE;
1971#endif
1972 }
1973 else
1974 {
1975#ifdef IN_RING3
1976 /*
1977 * Only (re-)initialize the stream when not running.
1978 */
1979 if (!fRun && !fInRun)
1980 {
1981 int rc2 = hdaStreamInit(pThis, pStrmSt, u8Strm);
1982 AssertRC(rc2);
1983 }
1984
1985 /*
1986 * We enter here to change DMA states only.
1987 */
1988 if (fInRun != fRun)
1989 {
1990 Assert(!fReset && !fInReset);
1991 LogFunc(("[SD%RU8]: fRun=%RTbool\n", u8Strm, fRun));
1992
1993 PHDADRIVER pDrv;
1994 switch (u8Strm)
1995 {
1996 case 0: /** @todo Use a variable here. Later. */
1997 {
1998 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1999 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
2000 pDrv->LineIn.pStrmIn, fRun);
2001 break;
2002 }
2003# ifdef VBOX_WITH_HDA_MIC_IN
2004 case 2: /** @todo Use a variable here. Later. */
2005 {
2006 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2007 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
2008 pDrv->MicIn.pStrmIn, fRun);
2009 break;
2010 }
2011# endif
2012 case 4: /** @todo Use a variable here. Later. */
2013 {
2014 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2015 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
2016 pDrv->Out.pStrmOut, fRun);
2017 break;
2018 }
2019 default:
2020 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
2021 break;
2022 }
2023 }
2024#else /* !IN_RING3 */
2025 return VINF_IOM_R3_MMIO_WRITE;
2026#endif /* IN_RING3 */
2027 }
2028
2029 return hdaRegWriteU24(pThis, iReg, u32Value);
2030}
2031
2032static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2033{
2034 uint32_t v = HDA_REG_IND(pThis, iReg);
2035 v &= ~(u32Value & v);
2036 HDA_REG_IND(pThis, iReg) = v;
2037 hdaProcessInterrupt(pThis);
2038 return VINF_SUCCESS;
2039}
2040
2041static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2042{
2043 /* Only can be modified if RUN bit is 0. */
2044 bool fIsRunning = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2045 if (fIsRunning)
2046 {
2047 AssertMsgFailed(("Cannot write to register when RUN bit is set\n"));
2048 return VINF_SUCCESS;
2049 }
2050
2051 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2052 if (RT_FAILURE(rc))
2053 AssertRCReturn(rc, VINF_SUCCESS);
2054 return rc;
2055}
2056
2057static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2058{
2059 switch (u32Value)
2060 {
2061 case HDA_SDFIFOW_8B:
2062 case HDA_SDFIFOW_16B:
2063 case HDA_SDFIFOW_32B:
2064 return hdaRegWriteU16(pThis, iReg, u32Value);
2065 default:
2066 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
2067 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
2068 }
2069 return VINF_SUCCESS; /* Never reached. */
2070}
2071
2072/**
2073 * @note This method could be called for changing value on Output Streams
2074 * only (ICH6 datasheet 18.2.39).
2075 */
2076static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2077{
2078 /** @todo Only allow updating FIFOS if RUN bit is 0? */
2079 uint32_t u32FIFOS = 0;
2080
2081 switch (iReg)
2082 {
2083 /* SDInFIFOS is RO, n=0-3. */
2084 case HDA_REG_SD0FIFOS:
2085 case HDA_REG_SD1FIFOS:
2086 case HDA_REG_SD2FIFOS:
2087 case HDA_REG_SD3FIFOS:
2088 {
2089 LogFunc(("Guest tries to change R/O value of FIFO size of input stream, ignoring\n"));
2090 break;
2091 }
2092 case HDA_REG_SD4FIFOS:
2093 case HDA_REG_SD5FIFOS:
2094 case HDA_REG_SD6FIFOS:
2095 case HDA_REG_SD7FIFOS:
2096 {
2097 switch(u32Value)
2098 {
2099 case HDA_SDONFIFO_16B:
2100 case HDA_SDONFIFO_32B:
2101 case HDA_SDONFIFO_64B:
2102 case HDA_SDONFIFO_128B:
2103 case HDA_SDONFIFO_192B:
2104 u32FIFOS = u32Value;
2105 break;
2106
2107 case HDA_SDONFIFO_256B: /** @todo r=andy Investigate this. */
2108 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
2109 /* Fall through is intentional. */
2110 default:
2111 u32FIFOS = HDA_SDONFIFO_192B;
2112 break;
2113 }
2114
2115 break;
2116 }
2117 default:
2118 {
2119 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
2120 break;
2121 }
2122 }
2123
2124 if (u32FIFOS)
2125 {
2126 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", 0, hdaSDFIFOSToBytes(u32FIFOS)));
2127 /** @todo Update internal stream state with new FIFOS. */
2128
2129 return hdaRegWriteU16(pThis, iReg, u32FIFOS);
2130 }
2131
2132 return VINF_SUCCESS;
2133}
2134
2135#ifdef IN_RING3
2136static int hdaSDFMTToStrmCfg(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
2137{
2138 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2139
2140# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2141
2142 int rc = VINF_SUCCESS;
2143
2144 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
2145 uint32_t u32HzMult = 1;
2146 uint32_t u32HzDiv = 1;
2147
2148 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2149 {
2150 case 0: u32HzMult = 1; break;
2151 case 1: u32HzMult = 2; break;
2152 case 2: u32HzMult = 3; break;
2153 case 3: u32HzMult = 4; break;
2154 default:
2155 LogFunc(("Unsupported multiplier %x\n",
2156 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2157 rc = VERR_NOT_SUPPORTED;
2158 break;
2159 }
2160 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2161 {
2162 case 0: u32HzDiv = 1; break;
2163 case 1: u32HzDiv = 2; break;
2164 case 2: u32HzDiv = 3; break;
2165 case 3: u32HzDiv = 4; break;
2166 case 4: u32HzDiv = 5; break;
2167 case 5: u32HzDiv = 6; break;
2168 case 6: u32HzDiv = 7; break;
2169 case 7: u32HzDiv = 8; break;
2170 default:
2171 LogFunc(("Unsupported divisor %x\n",
2172 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2173 rc = VERR_NOT_SUPPORTED;
2174 break;
2175 }
2176
2177 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
2178 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2179 {
2180 case 0:
2181 LogFunc(("Requested 8-bit\n"));
2182 enmFmt = AUD_FMT_S8;
2183 break;
2184 case 1:
2185 LogFunc(("Requested 16-bit\n"));
2186 enmFmt = AUD_FMT_S16;
2187 break;
2188 case 2:
2189 LogFunc(("Requested 20-bit\n"));
2190 break;
2191 case 3:
2192 LogFunc(("Requested 24-bit\n"));
2193 break;
2194 case 4:
2195 LogFunc(("Requested 32-bit\n"));
2196 enmFmt = AUD_FMT_S32;
2197 break;
2198 default:
2199 AssertMsgFailed(("Unsupported bits shift %x\n",
2200 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2201 rc = VERR_NOT_SUPPORTED;
2202 break;
2203 }
2204
2205 if (RT_SUCCESS(rc))
2206 {
2207 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2208 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
2209 pCfg->enmFormat = enmFmt;
2210 pCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2211 }
2212
2213# undef EXTRACT_VALUE
2214
2215 LogFlowFuncLeaveRC(rc);
2216 return rc;
2217}
2218#endif
2219
2220static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2221{
2222#ifdef IN_RING3
2223# ifdef VBOX_WITH_HDA_CODEC_EMU
2224 /* No reason to re-open stream with same settings. */
2225 if (u32Value == HDA_REG_IND(pThis, iReg))
2226 return VINF_SUCCESS;
2227
2228 PDMAUDIOSTREAMCFG strmCfg;
2229 int rc = hdaSDFMTToStrmCfg(u32Value, &strmCfg);
2230 if (RT_FAILURE(rc))
2231 return rc;
2232
2233 PHDADRIVER pDrv;
2234 switch (iReg)
2235 {
2236 case HDA_REG_SD0FMT:
2237 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2238 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &strmCfg);
2239 break;
2240# ifdef VBOX_WITH_HDA_MIC_IN
2241 case HDA_REG_SD2FMT:
2242 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2243 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &strmCfg);
2244 break;
2245# endif
2246 default:
2247 LogFunc(("Warning: Attempt to change format on register %RU32\n", iReg));
2248 break;
2249 }
2250
2251 /** @todo r=andy rc gets lost; needs fixing. */
2252 return hdaRegWriteU16(pThis, iReg, u32Value);
2253# else /* !VBOX_WITH_HDA_CODEC_EMU */
2254 return hdaRegWriteU16(pThis, iReg, u32Value);
2255# endif
2256#else /* !IN_RING3 */
2257 return VINF_IOM_R3_MMIO_WRITE;
2258#endif
2259}
2260
2261static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2262{
2263 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2264 if (RT_FAILURE(rc))
2265 AssertRCReturn(rc, VINF_SUCCESS);
2266 return rc;
2267}
2268
2269static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2270{
2271 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2272 if (RT_FAILURE(rc))
2273 AssertRCReturn(rc, VINF_SUCCESS);
2274 return rc;
2275}
2276
2277static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2278{
2279 int rc = VINF_SUCCESS;
2280 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2281 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2282 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2283 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2284
2285 rc = hdaRegReadU32(pThis, iReg, pu32Value);
2286 return rc;
2287}
2288
2289static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2290{
2291 int rc = VINF_SUCCESS;
2292
2293 /*
2294 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2295 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2296 */
2297 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
2298 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
2299 {
2300#ifdef IN_RING3
2301 PFNHDACODECVERBPROCESSOR pfn = NULL;
2302 uint64_t resp;
2303 uint32_t cmd = HDA_REG(pThis, IC);
2304 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2305 {
2306 /*
2307 * 3.4.3 defines behavior of immediate Command status register.
2308 */
2309 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
2310 return rc;
2311 }
2312 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2313 LogFunc(("IC:%x\n", cmd));
2314
2315 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
2316 HDA_CODEC_CMD(cmd, 0 /* LUN */),
2317 &pfn);
2318 if (RT_FAILURE(rc))
2319 AssertRCReturn(rc, rc);
2320 rc = pfn(pThis->pCodec,
2321 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
2322 if (RT_FAILURE(rc))
2323 AssertRCReturn(rc, rc);
2324
2325 HDA_REG(pThis, IR) = (uint32_t)resp;
2326 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
2327 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
2328 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
2329#else /* !IN_RING3 */
2330 rc = VINF_IOM_R3_MMIO_WRITE;
2331#endif
2332 return rc;
2333 }
2334 /*
2335 * Once the guest read the response, it should clean the IRV bit of the IRS register.
2336 */
2337 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
2338 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
2339 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
2340 return rc;
2341}
2342
2343static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2344{
2345 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
2346 {
2347 HDA_REG(pThis, RIRBWP) = 0;
2348 }
2349 /* The remaining bits are O, see 6.2.22 */
2350 return VINF_SUCCESS;
2351}
2352
2353static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2354{
2355 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2356 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2357 if (RT_FAILURE(rc))
2358 AssertRCReturn(rc, rc);
2359
2360 switch(iReg)
2361 {
2362 case HDA_REG_CORBLBASE:
2363 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2364 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
2365 break;
2366 case HDA_REG_CORBUBASE:
2367 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2368 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2369 break;
2370 case HDA_REG_RIRBLBASE:
2371 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2372 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
2373 break;
2374 case HDA_REG_RIRBUBASE:
2375 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2376 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2377 break;
2378 case HDA_REG_DPLBASE:
2379 {
2380 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
2381 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
2382
2383 /* Also make sure to handle the DMA position enable bit. */
2384 bool fEnabled = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2385 if (pThis->fDMAPosition != fEnabled)
2386 {
2387 LogRel(("HDA: %s DMA position buffer\n", fEnabled ? "Enabled" : "Disabled"));
2388 pThis->fDMAPosition = fEnabled;
2389 }
2390 break;
2391 }
2392 case HDA_REG_DPUBASE:
2393 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
2394 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2395 break;
2396 default:
2397 AssertMsgFailed(("Invalid index\n"));
2398 break;
2399 }
2400
2401 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2402 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2403 return rc;
2404}
2405
2406static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2407{
2408 uint8_t v = HDA_REG(pThis, RIRBSTS);
2409 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2410
2411 return hdaProcessInterrupt(pThis);
2412}
2413
2414#ifdef IN_RING3
2415#ifdef LOG_ENABLED
2416static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE)
2417{
2418 uint32_t cbBDLE = 0;
2419
2420 for (uint16_t i = 0; i < cBDLE; i++)
2421 {
2422 uint8_t bdle[16]; /** @todo Use a define. */
2423 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * 16, bdle, 16); /** @todo Use a define. */
2424
2425 uint64_t addr = *(uint64_t *)bdle;
2426 uint32_t len = *(uint32_t *)&bdle[8];
2427 uint32_t ioc = *(uint32_t *)&bdle[12];
2428
2429 LogFlowFunc(("#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
2430 i, addr, len, RT_BOOL(ioc & 0x1)));
2431
2432 cbBDLE += len;
2433 }
2434
2435 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
2436
2437 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
2438 return;
2439
2440 for (int i = 0; i < 8; i++) /** @todo Use a define for MAX_STREAMS! */
2441 {
2442 uint32_t uDMACnt;
2443 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i * 8, /** @todo Use a define. */
2444 &uDMACnt, sizeof(&uDMACnt));
2445
2446 LogFlowFunc(("%s #%02d STREAM(0x%x)\n",
2447 i == HDA_SDCTL_NUM(pThis, 4) || i == HDA_SDCTL_NUM(pThis, 0) ? "*" : " ", i , uDMACnt));
2448 }
2449}
2450#endif
2451
2452/**
2453 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
2454 *
2455 * @param pThis Pointer to HDA state.
2456 * @param pBDLE Where to store the fetched result.
2457 * @param u64BaseDMA Address base of DMA engine to use.
2458 * @param u16Entry BDLE entry to fetch.
2459 */
2460static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
2461{
2462 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2463 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
2464 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
2465 /** @todo Compare u16Entry with LVI. */
2466
2467 uint8_t uBundleEntry[16]; /** @todo Define a BDLE length. */
2468 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * 16, /** @todo Define a BDLE length. */
2469 uBundleEntry, RT_ELEMENTS(uBundleEntry));
2470 if (RT_FAILURE(rc))
2471 return rc;
2472
2473 pBDLE->State.u32BDLIndex = u16Entry;
2474 pBDLE->u64BufAdr = *(uint64_t *) uBundleEntry;
2475 pBDLE->u32BufSize = *(uint32_t *)&uBundleEntry[8];
2476 if (pBDLE->u32BufSize < sizeof(uint16_t)) /* Must be at least one word. */
2477 return VERR_INVALID_STATE;
2478
2479 pBDLE->fIntOnCompletion = (*(uint32_t *)&uBundleEntry[12]) & 0x1;
2480
2481 return VINF_SUCCESS;
2482}
2483
2484static void hdaBDLEReset(PHDABDLE pBDLE)
2485{
2486 AssertPtrReturnVoid(pBDLE);
2487
2488 pBDLE->State.u32BufOff = 0;
2489 pBDLE->State.cbBelowFIFOW = 0;
2490}
2491
2492/**
2493 * Returns the number of outstanding stream data bytes which need to be processed
2494 * by the DMA engine assigned to this stream.
2495 *
2496 * @return Number of bytes for the DMA engine to process.
2497 */
2498DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbMax)
2499{
2500 AssertPtrReturn(pThis, 0);
2501 AssertPtrReturn(pStrmSt, 0);
2502
2503 if (!cbMax)
2504 return 0;
2505
2506 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2507
2508 uint32_t cbFree = pStrmSt->u32CBL - HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2509 if (cbFree)
2510 {
2511 /* Limit to the available free space of the current BDLE. */
2512 cbFree = RT_MIN(cbFree, pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2513
2514 /* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
2515 cbFree = RT_MIN(cbFree, pStrmSt->u16FIFOS);
2516
2517 /* Make sure we only transfer as many bytes as requested. */
2518 cbFree = RT_MIN(cbFree, cbMax);
2519
2520 if (pBDLE->State.cbBelowFIFOW)
2521 {
2522 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
2523 * No need to read data from DMA then. */
2524 if (cbFree > pBDLE->State.cbBelowFIFOW)
2525 {
2526 /* Subtract the amount of bytes that still would fit in the stream's FIFO
2527 * and therefore do not need to be processed by DMA. */
2528 cbFree -= pBDLE->State.cbBelowFIFOW;
2529 }
2530 }
2531 }
2532
2533 LogFlowFunc(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, cbFree=%RU32, %R[bdle]\n", pStrmSt->u8Strm,
2534 pStrmSt->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), cbFree, pBDLE));
2535 return cbFree;
2536}
2537
2538DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
2539{
2540 AssertPtrReturnVoid(pBDLE);
2541
2542 if (!cbData || !cbProcessed)
2543 return;
2544
2545 /* Fewer than cbBelowFIFOW bytes were copied.
2546 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2547 * where it might happen. */
2548 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
2549 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
2550 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
2551
2552#if 0
2553 if ( pBDLE->State.cbBelowFIFOW
2554 && pBDLE->State.cbBelowFIFOW <= cbWritten)
2555 {
2556 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
2557 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->u32BufSize));
2558 }
2559#endif
2560
2561 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
2562 Assert(pBDLE->State.cbBelowFIFOW == 0);
2563
2564 /* We always increment the position of DMA buffer counter because we're always reading
2565 * into an intermediate buffer. */
2566 pBDLE->State.u32BufOff += cbData;
2567 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2568
2569 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
2570}
2571
2572DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
2573{
2574 AssertPtrReturn(pThis, false);
2575 AssertPtrReturn(pStrmSt, false);
2576
2577 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2578 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2579
2580 /* Did we reach the CBL (Cyclic Buffer List) limit? */
2581 bool fCBLLimitReached = u32LPIB >= pStrmSt->u32CBL;
2582
2583 /* Do we need to use the next BDLE entry? Either because we reached
2584 * the CBL limit or our internal DMA buffer is full. */
2585 bool fNeedsNextBDLE = ( fCBLLimitReached
2586 || ( pBDLE->State.u32BufOff
2587 && pBDLE->State.u32BufOff >= pBDLE->u32BufSize)
2588 );
2589
2590 Assert(u32LPIB <= pStrmSt->u32CBL);
2591 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2592
2593 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
2594 pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
2595
2596 if (fCBLLimitReached)
2597 {
2598 /* Reset LPIB register. */
2599 u32LPIB -= RT_MIN(u32LPIB, pStrmSt->u32CBL);
2600 hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2601 }
2602
2603 if (fNeedsNextBDLE)
2604 {
2605 /* Reset current BDLE. */
2606 hdaBDLEReset(pBDLE);
2607 }
2608
2609 return fNeedsNextBDLE;
2610}
2611
2612DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbInc)
2613{
2614 AssertPtrReturnVoid(pThis);
2615 AssertPtrReturnVoid(pStrmSt);
2616
2617 LogFlowFunc(("[SD%RU8]: cbInc=%RU32\n", pStrmSt->u8Strm, cbInc));
2618
2619 Assert(cbInc <= pStrmSt->u16FIFOS);
2620
2621 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2622
2623 /*
2624 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
2625 * doesn't fetch anything via DMA, so just update LPIB.
2626 * (ICH6 datasheet 18.2.38).
2627 */
2628 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
2629 {
2630 const uint32_t u32LPIB = RT_MIN(HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2631 pStrmSt->u32CBL);
2632
2633 LogFlowFunc(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
2634 pStrmSt->u8Strm,
2635 HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2636 pStrmSt->u32CBL));
2637
2638 hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2639 }
2640}
2641
2642static bool hdaStreamTransferIsComplete(PHDASTATE pThis, PHDASTREAM pStrmSt)
2643{
2644 AssertPtrReturn(pThis, true);
2645 AssertPtrReturn(pStrmSt, true);
2646
2647 bool fIsComplete = false;
2648
2649 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2650 const uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2651
2652 if ( pBDLE->State.u32BufOff >= pBDLE->u32BufSize
2653 || u32LPIB >= pStrmSt->u32CBL)
2654 {
2655 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2656 Assert(u32LPIB <= pStrmSt->u32CBL);
2657
2658 if (/* IOC (Interrupt On Completion) bit set? */
2659 pBDLE->fIntOnCompletion
2660 /* All data put into the DMA FIFO? */
2661 && pBDLE->State.cbBelowFIFOW == 0
2662 )
2663 {
2664 /**
2665 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
2666 * last byte of data for the current descriptor has been fetched
2667 * from memory and put into the DMA FIFO.
2668 *
2669 ** @todo More carefully investigate BCIS flag.
2670 *
2671 * Speech synthesis works fine on Mac Guest if this bit isn't set
2672 * but in general sound quality gets worse.
2673 */
2674 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2675
2676 /*
2677 * If the ICE (IOCE, "Interrupt On Completion Enable") bit of the SDCTL register is set
2678 * we need to generate an interrupt.
2679 */
2680 if (HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2681 hdaProcessInterrupt(pThis);
2682 }
2683
2684 fIsComplete = true;
2685 }
2686
2687 LogFlowFunc(("[SD%RU8]: u32LPIB=%RU32, CBL=%RU32, %R[bdle] => %s\n",
2688 pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, pBDLE, fIsComplete ? "COMPLETE" : "INCOMPLETE"));
2689
2690 return fIsComplete;
2691}
2692
2693/**
2694 * hdaReadAudio - copies samples from audio backend to DMA.
2695 * Note: This function writes to the DMA buffer immediately,
2696 * but "reports bytes" when all conditions are met (FIFOW).
2697 */
2698static int hdaReadAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, PAUDMIXSINK pSink, uint32_t cbMax, uint32_t *pcbRead)
2699{
2700 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2701 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2702 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
2703 /* pcbRead is optional. */
2704
2705 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2706
2707 int rc;
2708 uint32_t cbRead = 0;
2709 uint32_t cbBuf = hdaStreamGetTransferSize(pThis, pStrmSt, cbMax);
2710
2711 LogFlowFunc(("cbBuf=%RU32, %R[bdle]\n", cbBuf, pBDLE));
2712
2713 if (!cbBuf)
2714 {
2715 /* Nothing to write, bail out. */
2716 rc = VINF_EOF;
2717 }
2718 else
2719 {
2720 rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pBDLE->State.au8FIFO, cbBuf, &cbRead);
2721 if (RT_SUCCESS(rc))
2722 {
2723 Assert(cbRead);
2724 Assert(cbRead == cbBuf);
2725 Assert(cbRead <= pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2726
2727 /*
2728 * Write to the BDLE's DMA buffer.
2729 */
2730 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2731 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2732 pBDLE->State.au8FIFO, cbRead);
2733 AssertRC(rc);
2734
2735 if (pBDLE->State.cbBelowFIFOW + cbRead > hdaStreamGetFIFOW(pThis, pStrmSt))
2736 {
2737 pBDLE->State.u32BufOff += cbRead;
2738 pBDLE->State.cbBelowFIFOW = 0;
2739 //hdaBackendReadTransferReported(pBDLE, cbDMAData, cbRead, &cbRead, pcbAvail);
2740 }
2741 else
2742 {
2743 pBDLE->State.u32BufOff += cbRead;
2744 pBDLE->State.cbBelowFIFOW += cbRead;
2745 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2746 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbRead, pcbAvail);
2747
2748 rc = VERR_NO_DATA;
2749 }
2750 }
2751 }
2752
2753 Assert(cbRead <= pStrmSt->u16FIFOS);
2754
2755 if (RT_SUCCESS(rc))
2756 {
2757 if (pcbRead)
2758 *pcbRead = cbRead;
2759 }
2760
2761 LogFunc(("Returning cbRead=%RU32, rc=%Rrc\n", cbRead, rc));
2762 return rc;
2763}
2764
2765static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbMax, uint32_t *pcbWritten)
2766{
2767 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2768 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2769 AssertPtrReturn(pcbWritten, VERR_INVALID_POINTER);
2770 /* pcbWritten is optional. */
2771
2772 PHDABDLE pBDLE = hdaStreamGetCurrentBDLE(pThis, pStrmSt);
2773 int rc;
2774
2775 uint32_t cbWritten = 0;
2776 uint32_t cbData = hdaStreamGetTransferSize(pThis, pStrmSt, cbMax);
2777
2778 LogFlowFunc(("cbData=%RU32, %R[bdle]\n", cbData, pBDLE));
2779
2780 /*
2781 * Copy from DMA to the corresponding stream buffer (if there are any bytes from the
2782 * previous unreported transfer we write at offset 'pBDLE->State.cbUnderFifoW').
2783 */
2784 if (!cbData)
2785 {
2786 rc = VINF_EOF;
2787 }
2788 else
2789 {
2790 /*
2791 * Read from the current BDLE's DMA buffer.
2792 */
2793 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2794 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2795 pBDLE->State.au8FIFO + pBDLE->State.cbBelowFIFOW, cbData);
2796 AssertRC(rc);
2797
2798#ifdef VBOX_WITH_STATISTICS
2799 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbData);
2800#endif
2801 /*
2802 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2803 */
2804 uint32_t cbToWrite = cbData + pBDLE->State.cbBelowFIFOW;
2805 if (cbToWrite >= hdaStreamGetFIFOW(pThis, pStrmSt))
2806 {
2807 uint32_t cbWrittenToStream;
2808 int rc2;
2809
2810 PHDADRIVER pDrv;
2811 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2812 {
2813 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2814 {
2815 rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2816 pBDLE->State.au8FIFO, cbToWrite, &cbWrittenToStream);
2817 if (RT_SUCCESS(rc2))
2818 {
2819 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2820 LogFlowFunc(("\tLUN#%RU8: Warning: Only written %RU32 / %RU32 bytes, expect lags\n",
2821 pDrv->uLUN, cbWrittenToStream, cbToWrite));
2822 }
2823 }
2824 else /* Stream disabled, not fatal. */
2825 {
2826 cbWrittenToStream = 0;
2827 rc2 = VERR_NOT_AVAILABLE;
2828 /* Keep going. */
2829 }
2830
2831 LogFlowFunc(("\tLUN#%RU8: cbToWrite=%RU32, cbWrittenToStream=%RU32, rc=%Rrc\n",
2832 pDrv->uLUN, cbToWrite, cbWrittenToStream, rc2));
2833 }
2834
2835 /* Always report all data as being written;
2836 * backends who were not able to catch up have to deal with it themselves. */
2837 cbWritten = cbToWrite;
2838
2839 hdaBDLEUpdate(pBDLE, cbData, cbWritten);
2840 }
2841 else
2842 {
2843 pBDLE->State.u32BufOff += cbWritten;
2844 pBDLE->State.cbBelowFIFOW += cbWritten;
2845 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2846
2847 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2848 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbAvail, NULL);
2849 rc = VINF_EOF;
2850 }
2851 }
2852
2853 Assert(cbWritten <= pStrmSt->u16FIFOS);
2854
2855 if (RT_SUCCESS(rc))
2856 {
2857 if (pcbWritten)
2858 *pcbWritten = cbWritten;
2859 }
2860
2861 LogFunc(("Returning cbWritten=%RU32, rc=%Rrc\n", cbWritten, rc));
2862 return rc;
2863}
2864
2865/**
2866 * @interface_method_impl{HDACODEC,pfnReset}
2867 */
2868static DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2869{
2870 PHDASTATE pThis = pCodec->pHDAState;
2871 NOREF(pThis);
2872 return VINF_SUCCESS;
2873}
2874
2875
2876static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2877{
2878 NOREF(pThis);
2879 NOREF(enmRecSource);
2880 LogFlowFuncEnter();
2881}
2882
2883static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2884{
2885 NOREF(pThis);
2886 LogFlowFuncEnter();
2887}
2888
2889static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2890 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2891 PPDMAUDIOSTREAMCFG pCfg)
2892{
2893 PAUDMIXSINK pSink;
2894
2895 switch (enmRecSource)
2896 {
2897# ifdef VBOX_WITH_HDA_MIC_IN
2898 case PDMAUDIORECSOURCE_MIC:
2899 pSink = pThis->pSinkMicIn;
2900 break;
2901# endif
2902 case PDMAUDIORECSOURCE_LINE_IN:
2903 pSink = pThis->pSinkLineIn;
2904 break;
2905 default:
2906 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2907 return VERR_NOT_SUPPORTED;
2908 }
2909
2910 int rc = VINF_SUCCESS;
2911 char *pszDesc;
2912
2913 PHDADRIVER pDrv;
2914 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2915 {
2916 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2917 {
2918 rc = VERR_NO_MEMORY;
2919 break;
2920 }
2921
2922 rc = pDrv->pConnector->pfnCreateIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2923 LogFlowFunc(("LUN#%RU8: Created input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2924 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2925 {
2926 AudioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2927 rc = AudioMixerAddStreamIn(pSink,
2928 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2929 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2930 }
2931
2932 RTStrFree(pszDesc);
2933 }
2934
2935 LogFlowFuncLeaveRC(rc);
2936 return rc;
2937}
2938
2939static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2940 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2941{
2942 int rc = VINF_SUCCESS;
2943 char *pszDesc;
2944
2945 PHDADRIVER pDrv;
2946 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2947 {
2948 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s (%RU32Hz, %RU8 %s)",
2949 pDrv->uLUN, pszName, pCfg->uHz, pCfg->cChannels, pCfg->cChannels > 1 ? "Channels" : "Channel") <= 0)
2950 {
2951 rc = VERR_NO_MEMORY;
2952 break;
2953 }
2954
2955 rc = pDrv->pConnector->pfnCreateOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
2956 LogFlowFunc(("LUN#%RU8: Created output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2957 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2958 {
2959 AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
2960 rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
2961 pDrv->pConnector, pDrv->Out.pStrmOut,
2962 0 /* uFlags */, &pDrv->Out.phStrmOut);
2963 }
2964
2965 RTStrFree(pszDesc);
2966 }
2967
2968 LogFlowFuncLeaveRC(rc);
2969 return rc;
2970}
2971
2972static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis, ENMSOUNDSOURCE enmSource,
2973 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2974{
2975 int rc = VINF_SUCCESS;
2976 PDMAUDIOVOLUME vol = { fMute, uVolLeft, uVolRight };
2977 PAUDMIXSINK pSink;
2978
2979 /* Convert the audio source to corresponding sink. */
2980 switch (enmSource)
2981 {
2982 case PO_INDEX:
2983 pSink = pThis->pSinkOutput;
2984 break;
2985 case PI_INDEX:
2986 pSink = pThis->pSinkLineIn;
2987 break;
2988 case MC_INDEX:
2989 pSink = pThis->pSinkMicIn;
2990 break;
2991 default:
2992 AssertFailedReturn(VERR_INVALID_PARAMETER);
2993 break;
2994 }
2995
2996 /* Set the volume. Codec already converted it to the correct range. */
2997 AudioMixerSetSinkVolume(pSink, &vol);
2998
2999 LogFlowFuncLeaveRC(rc);
3000 return rc;
3001}
3002
3003#ifndef VBOX_WITH_AUDIO_CALLBACKS
3004
3005static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3006{
3007 PHDASTATE pThis = (PHDASTATE)pvUser;
3008 Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
3009 AssertPtr(pThis);
3010
3011 STAM_PROFILE_START(&pThis->StatTimer, a);
3012
3013 uint32_t cbInMax = 0;
3014 uint32_t cbOutMin = UINT32_MAX;
3015
3016 PHDADRIVER pDrv;
3017
3018 uint64_t cTicksNow = TMTimerGet(pTimer);
3019 uint64_t cTicksElapsed = cTicksNow - pThis->uTimerTS;
3020 uint64_t cTicksPerSec = TMTimerGetFreq(pTimer);
3021
3022 pThis->uTimerTS = cTicksNow;
3023
3024 /*
3025 * Calculate the codec's (fixed) sampling rate.
3026 */
3027 AssertPtr(pThis->pCodec);
3028 PDMPCMPROPS codecStrmProps;
3029
3030 int rc = DrvAudioStreamCfgToProps(&pThis->pCodec->strmCfg, &codecStrmProps);
3031 AssertRC(rc);
3032
3033 uint32_t cCodecSamplesMin = (int)((2 * cTicksElapsed * pThis->pCodec->strmCfg.uHz + cTicksPerSec) / cTicksPerSec / 2);
3034 uint32_t cbCodecSamplesMin = cCodecSamplesMin << codecStrmProps.cShift;
3035
3036 /*
3037 * Process all driver nodes.
3038 */
3039 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3040 {
3041 uint32_t cbIn = 0;
3042 uint32_t cbOut = 0;
3043
3044 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector, &cbIn, &cbOut, NULL /* pcSamplesLive */);
3045 if (RT_SUCCESS(rc))
3046 rc = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, NULL /* pcSamplesPlayed */);
3047
3048#ifdef DEBUG_TIMER
3049 LogFlowFunc(("LUN#%RU8: rc=%Rrc, cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, rc, cbIn, cbOut));
3050#endif
3051 /* If we there was an error handling (available) output or there simply is no output available,
3052 * then calculate the minimum data rate which must be processed by the device emulation in order
3053 * to function correctly.
3054 *
3055 * This is not the optimal solution, but as we have to deal with this on a timer-based approach
3056 * (until we have the audio callbacks) we need to have device' DMA engines running. */
3057 if (!pDrv->pConnector->pfnIsValidOut(pDrv->pConnector, pDrv->Out.pStrmOut))
3058 {
3059 /* Use the codec's (fixed) sampling rate. */
3060 cbOut = RT_MAX(cbOut, cbCodecSamplesMin);
3061 continue;
3062 }
3063
3064 const bool fIsActiveOut = pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut);
3065 if ( RT_FAILURE(rc)
3066 || !fIsActiveOut)
3067 {
3068 uint32_t cSamplesMin = (int)((2 * cTicksElapsed * pDrv->Out.pStrmOut->Props.uHz + cTicksPerSec) / cTicksPerSec / 2);
3069 uint32_t cbSamplesMin = AUDIOMIXBUF_S2B(&pDrv->Out.pStrmOut->MixBuf, cSamplesMin);
3070
3071#ifdef DEBUG_TIMER
3072 LogFlowFunc(("\trc=%Rrc, cSamplesMin=%RU32, cbSamplesMin=%RU32\n", rc, cSamplesMin, cbSamplesMin));
3073#endif
3074 cbOut = RT_MAX(cbOut, cbSamplesMin);
3075 }
3076
3077 cbOutMin = RT_MIN(cbOutMin, cbOut);
3078 cbInMax = RT_MAX(cbInMax, cbIn);
3079 }
3080
3081#ifdef DEBUG_TIMER
3082 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
3083#endif
3084
3085 if (cbOutMin == UINT32_MAX)
3086 cbOutMin = 0;
3087
3088 /* Do the actual device transfers. */
3089 hdaTransfer(pThis, PO_INDEX, cbOutMin /* cbToProcess */, NULL /* pcbProcessed */);
3090 hdaTransfer(pThis, PI_INDEX, cbInMax /* cbToProcess */, NULL /* pcbProcessed */);
3091
3092 /* Kick the timer again. */
3093 uint64_t cTicks = pThis->cTimerTicks;
3094 /** @todo adjust cTicks down by now much cbOutMin represents. */
3095 TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
3096
3097 STAM_PROFILE_STOP(&pThis->StatTimer, a);
3098}
3099
3100#else /* VBOX_WITH_AUDIO_CALLBACKS */
3101
3102static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
3103{
3104 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
3105 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
3106 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
3107 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
3108 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
3109
3110 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
3111 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
3112
3113 PPDMAUDIOCALLBACKDATAIN pData = (PPDMAUDIOCALLBACKDATAIN)pvUser;
3114 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAIN), VERR_INVALID_PARAMETER);
3115
3116 return hdaTransfer(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
3117}
3118
3119static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
3120{
3121 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
3122 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
3123 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
3124 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
3125 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
3126
3127 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
3128 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
3129
3130 PPDMAUDIOCALLBACKDATAOUT pData = (PPDMAUDIOCALLBACKDATAOUT)pvUser;
3131 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAOUT), VERR_INVALID_PARAMETER);
3132
3133 PHDASTATE pThis = pCtx->pThis;
3134
3135 int rc = hdaTransfer(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
3136 if ( RT_SUCCESS(rc)
3137 && pData->cbOutWritten)
3138 {
3139 PHDADRIVER pDrv;
3140 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3141 {
3142 uint32_t cSamplesPlayed;
3143 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
3144 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
3145 }
3146 }
3147}
3148#endif /* VBOX_WITH_AUDIO_CALLBACKS */
3149
3150static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbToProcess, uint32_t *pcbProcessed)
3151{
3152 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3153 /* pcbProcessed is optional. */
3154
3155 LogFlowFunc(("enmSrc=%RU32, cbToProcess=%RU32\n", enmSrc, cbToProcess));
3156
3157 if (ASMAtomicReadBool(&pThis->fInReset)) /* HDA controller in reset mode? Bail out. */
3158 {
3159 LogFlowFunc(("In reset mode, skipping\n"));
3160
3161 if (pcbProcessed)
3162 *pcbProcessed = 0;
3163 return VINF_SUCCESS;
3164 }
3165
3166 PHDASTREAM pStrmSt;
3167 switch (enmSrc)
3168 {
3169 case PI_INDEX:
3170 {
3171 pStrmSt = &pThis->StrmStLineIn;
3172 break;
3173 }
3174
3175#ifdef VBOX_WITH_HDA_MIC_IN
3176 case MC_INDEX:
3177 {
3178 pStrmSt = &pThis->StrmStMicIn;
3179 break;
3180 }
3181#endif
3182 case PO_INDEX:
3183 {
3184 pStrmSt = &pThis->StrmStOut;
3185 break;
3186 }
3187
3188 default:
3189 {
3190 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
3191 return VERR_NOT_SUPPORTED;
3192 }
3193 }
3194
3195 int rc = VINF_SUCCESS;
3196 bool fProceed = true;
3197
3198 /* Stop request received? */
3199 if (ASMAtomicReadBool(&pStrmSt->State.fDoStop))
3200 {
3201 pStrmSt->State.fActive = false;
3202
3203 rc = RTSemEventSignal(pStrmSt->State.hStateChangedEvent);
3204 AssertRC(rc);
3205
3206 fProceed = false;
3207 }
3208 /* Is the stream not in a running state currently? */
3209 else if (!(HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)))
3210 fProceed = false;
3211 /* There must be BDLEs defined in order to have a working stream. */
3212 else if (pStrmSt->State.cBDLE == 0)
3213 fProceed = false;
3214 /* Nothing to process? */
3215 else if (!cbToProcess)
3216 fProceed = false;
3217
3218 if (!fProceed)
3219 {
3220 if (pcbProcessed)
3221 *pcbProcessed = 0;
3222 return VINF_SUCCESS;
3223 }
3224
3225 /* Sanity checks. */
3226 Assert(pStrmSt->u8Strm <= 7); /** @todo Use a define for MAX_STREAMS! */
3227 Assert(pStrmSt->u64BaseDMA);
3228 Assert(pStrmSt->u32CBL);
3229
3230 /* State sanity checks. */
3231 AssertPtr(pStrmSt->State.paBDLE);
3232 Assert(ASMAtomicReadBool(&pStrmSt->State.fInReset) == false);
3233
3234 uint32_t cbProcessedTotal = 0;
3235 bool fIsComplete = false;
3236
3237 while (cbToProcess)
3238 {
3239 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
3240 if (hdaStreamNeedsNextBDLE(pThis, pStrmSt))
3241 hdaStreamGetNextBDLE(pThis, pStrmSt);
3242
3243 /* Set the FIFORDY bit on the stream while doing the transfer. */
3244 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3245
3246 uint32_t cbProcessed;
3247 switch (enmSrc)
3248 {
3249 case PI_INDEX:
3250 rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkLineIn, cbToProcess, &cbProcessed);
3251 break;
3252 case PO_INDEX:
3253 rc = hdaWriteAudio(pThis, pStrmSt, cbToProcess, &cbProcessed);
3254 break;
3255#ifdef VBOX_WITH_HDA_MIC_IN
3256 case MC_INDEX:
3257 rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkMicIn, cbToProcess, &cbProcessed);
3258 break;
3259#endif
3260 default:
3261 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
3262 rc = VERR_NOT_SUPPORTED;
3263 break;
3264 }
3265
3266 /* Remove the FIFORDY bit again. */
3267 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3268
3269 if (RT_FAILURE(rc))
3270 break;
3271
3272 hdaStreamTransferUpdate(pThis, pStrmSt, cbProcessed);
3273
3274 cbToProcess -= RT_MIN(cbToProcess, cbProcessed);
3275 cbProcessedTotal += cbProcessed;
3276
3277 LogFlowFunc(("cbProcessed=%RU32, cbToProcess=%RU32, cbProcessedTotal=%RU32, rc=%Rrc\n",
3278 cbProcessed, cbToProcess, cbProcessedTotal, rc));
3279
3280 if (rc == VINF_EOF)
3281 fIsComplete = true;
3282
3283 if (!fIsComplete)
3284 fIsComplete = hdaStreamTransferIsComplete(pThis, pStrmSt);
3285
3286 if (fIsComplete)
3287 break;
3288 }
3289
3290 if (RT_SUCCESS(rc))
3291 {
3292 if (pcbProcessed)
3293 *pcbProcessed = cbProcessedTotal;
3294 }
3295
3296 LogFlowFuncLeaveRC(rc);
3297 return rc;
3298}
3299#endif /* IN_RING3 */
3300
3301/* MMIO callbacks */
3302
3303/**
3304 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3305 *
3306 * @note During implementation, we discovered so-called "forgotten" or "hole"
3307 * registers whose description is not listed in the RPM, datasheet, or
3308 * spec.
3309 */
3310PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3311{
3312 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3313 int rc;
3314
3315 /*
3316 * Look up and log.
3317 */
3318 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3319 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
3320#ifdef LOG_ENABLED
3321 unsigned const cbLog = cb;
3322 uint32_t offRegLog = offReg;
3323#endif
3324
3325 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
3326 Assert(cb == 4); Assert((offReg & 3) == 0);
3327
3328 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3329 LogFunc(("\tAccess to registers except GCTL is blocked while reset\n"));
3330
3331 if (idxRegDsc == -1)
3332 LogRel(("HDA: Invalid read access @0x%x (bytes=%d)\n", offReg, cb));
3333
3334 if (idxRegDsc != -1)
3335 {
3336 /* ASSUMES gapless DWORD at end of map. */
3337 if (g_aHdaRegMap[idxRegDsc].size == 4)
3338 {
3339 /*
3340 * Straight forward DWORD access.
3341 */
3342 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3343 LogFunc(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
3344 }
3345 else
3346 {
3347 /*
3348 * Multi register read (unless there are trailing gaps).
3349 * ASSUMES that only DWORD reads have sideeffects.
3350 */
3351 uint32_t u32Value = 0;
3352 unsigned cbLeft = 4;
3353 do
3354 {
3355 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3356 uint32_t u32Tmp = 0;
3357
3358 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3359 LogFunc(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3360 if (rc != VINF_SUCCESS)
3361 break;
3362 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3363
3364 cbLeft -= cbReg;
3365 offReg += cbReg;
3366 idxRegDsc++;
3367 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3368
3369 if (rc == VINF_SUCCESS)
3370 *(uint32_t *)pv = u32Value;
3371 else
3372 Assert(!IOM_SUCCESS(rc));
3373 }
3374 }
3375 else
3376 {
3377 rc = VINF_IOM_MMIO_UNUSED_FF;
3378 LogFunc(("\tHole at %x is accessed for read\n", offReg));
3379 }
3380
3381 /*
3382 * Log the outcome.
3383 */
3384#ifdef LOG_ENABLED
3385 if (cbLog == 4)
3386 LogFunc(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
3387 else if (cbLog == 2)
3388 LogFunc(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
3389 else if (cbLog == 1)
3390 LogFunc(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
3391#endif
3392 return rc;
3393}
3394
3395
3396DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3397{
3398 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3399 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
3400
3401 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3402#ifdef LOG_ENABLED
3403 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
3404#endif
3405 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3406 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3407 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
3408 return rc;
3409}
3410
3411
3412/**
3413 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3414 */
3415PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
3416{
3417 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3418 int rc;
3419
3420 /*
3421 * The behavior of accesses that aren't aligned on natural boundraries is
3422 * undefined. Just reject them outright.
3423 */
3424 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3425 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
3426 if (GCPhysAddr & (cb - 1))
3427 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3428
3429 /*
3430 * Look up and log the access.
3431 */
3432 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3433 int idxRegDsc = hdaRegLookup(pThis, offReg);
3434 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3435 uint64_t u64Value;
3436 if (cb == 4) u64Value = *(uint32_t const *)pv;
3437 else if (cb == 2) u64Value = *(uint16_t const *)pv;
3438 else if (cb == 1) u64Value = *(uint8_t const *)pv;
3439 else if (cb == 8) u64Value = *(uint64_t const *)pv;
3440 else
3441 {
3442 u64Value = 0; /* shut up gcc. */
3443 AssertReleaseMsgFailed(("%u\n", cb));
3444 }
3445
3446#ifdef LOG_ENABLED
3447 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3448 if (idxRegDsc == -1)
3449 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
3450 else if (cb == 4)
3451 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3452 else if (cb == 2)
3453 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3454 else if (cb == 1)
3455 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3456
3457 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3458 LogFunc(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3459#endif
3460
3461 /*
3462 * Try for a direct hit first.
3463 */
3464 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3465 {
3466 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3467#ifdef LOG_ENABLED
3468 LogFunc(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3469#endif
3470 }
3471 /*
3472 * Partial or multiple register access, loop thru the requested memory.
3473 */
3474 else
3475 {
3476 /*
3477 * If it's an access beyond the start of the register, shift the input
3478 * value and fill in missing bits. Natural alignment rules means we
3479 * will only see 1 or 2 byte accesses of this kind, so no risk of
3480 * shifting out input values.
3481 */
3482 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
3483 {
3484 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3485 offReg -= cbBefore;
3486 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3487 u64Value <<= cbBefore * 8;
3488 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3489 LogFunc(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3490 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3491 }
3492
3493 /* Loop thru the write area, it may cover multiple registers. */
3494 rc = VINF_SUCCESS;
3495 for (;;)
3496 {
3497 uint32_t cbReg;
3498 if (idxRegDsc != -1)
3499 {
3500 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3501 cbReg = g_aHdaRegMap[idxRegDsc].size;
3502 if (cb < cbReg)
3503 {
3504 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3505 LogFunc(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3506 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3507 }
3508 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
3509 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3510 LogFunc(("\t%#x -> %#x\n", u32LogOldVal, pThis->au32Regs[idxRegMem]));
3511 }
3512 else
3513 {
3514 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3515 cbReg = 1;
3516 }
3517 if (rc != VINF_SUCCESS)
3518 break;
3519 if (cbReg >= cb)
3520 break;
3521
3522 /* Advance. */
3523 offReg += cbReg;
3524 cb -= cbReg;
3525 u64Value >>= cbReg * 8;
3526 if (idxRegDsc == -1)
3527 idxRegDsc = hdaRegLookup(pThis, offReg);
3528 else
3529 {
3530 idxRegDsc++;
3531 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3532 || g_aHdaRegMap[idxRegDsc].offset != offReg)
3533 {
3534 idxRegDsc = -1;
3535 }
3536 }
3537 }
3538 }
3539
3540 return rc;
3541}
3542
3543
3544/* PCI callback. */
3545
3546#ifdef IN_RING3
3547/**
3548 * @callback_method_impl{FNPCIIOREGIONMAP}
3549 */
3550static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
3551 PCIADDRESSSPACE enmType)
3552{
3553 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3554 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3555 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3556 int rc;
3557
3558 /*
3559 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3560 *
3561 * Let IOM talk DWORDs when reading, saves a lot of complications. On
3562 * writing though, we have to do it all ourselves because of sideeffects.
3563 */
3564 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3565 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
3566 IOMMMIO_FLAGS_READ_DWORD
3567 | IOMMMIO_FLAGS_WRITE_PASSTHRU,
3568 hdaMMIOWrite, hdaMMIORead, "HDA");
3569
3570 if (RT_FAILURE(rc))
3571 return rc;
3572
3573 if (pThis->fR0Enabled)
3574 {
3575 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
3576 "hdaMMIOWrite", "hdaMMIORead");
3577 if (RT_FAILURE(rc))
3578 return rc;
3579 }
3580
3581 if (pThis->fRCEnabled)
3582 {
3583 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
3584 "hdaMMIOWrite", "hdaMMIORead");
3585 if (RT_FAILURE(rc))
3586 return rc;
3587 }
3588
3589 pThis->MMIOBaseAddr = GCPhysAddress;
3590 return VINF_SUCCESS;
3591}
3592
3593
3594/* Saved state callbacks. */
3595
3596static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
3597{
3598 /* Save stream ID. */
3599 int rc = SSMR3PutU8(pSSM, pStrm->u8Strm);
3600 AssertRCReturn(rc, rc);
3601 Assert(pStrm->u8Strm <= 7); /** @todo Use a define. */
3602
3603 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields5, NULL);
3604 AssertRCReturn(rc, rc);
3605
3606 for (uint32_t i = 0; i < pStrm->State.cBDLE; i++)
3607 {
3608 rc = SSMR3PutStructEx(pSSM, &pStrm->State.paBDLE[i].State, sizeof(HDABDLESTATE),
3609 0 /*fFlags*/, g_aSSMBDLEStateFields5, NULL);
3610 AssertRCReturn(rc, rc);
3611 }
3612
3613 return rc;
3614}
3615
3616/**
3617 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3618 */
3619static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3620{
3621 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3622
3623 /* Save Codec nodes states. */
3624 hdaCodecSaveState(pThis->pCodec, pSSM);
3625
3626 /* Save MMIO registers. */
3627 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3628 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3629 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3630
3631 /* Save number of streams. */
3632 SSMR3PutU32(pSSM, 3);
3633
3634 /* Save stream states. */
3635 int rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStOut);
3636 AssertRCReturn(rc, rc);
3637 rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStMicIn);
3638 AssertRCReturn(rc, rc);
3639 rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStLineIn);
3640 AssertRCReturn(rc, rc);
3641
3642 return rc;
3643}
3644
3645
3646/**
3647 * @callback_method_impl{FNSSMDEVLOADEXEC}
3648 */
3649static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3650{
3651 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3652
3653 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3654
3655 LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3656
3657 /*
3658 * Load Codec nodes states.
3659 */
3660 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3661 if (RT_FAILURE(rc))
3662 {
3663 LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
3664 return rc;
3665 }
3666
3667 /*
3668 * Load MMIO registers.
3669 */
3670 uint32_t cRegs;
3671 switch (uVersion)
3672 {
3673 case HDA_SSM_VERSION_1:
3674 /* Starting with r71199, we would save 112 instead of 113
3675 registers due to some code cleanups. This only affected trunk
3676 builds in the 4.1 development period. */
3677 cRegs = 113;
3678 if (SSMR3HandleRevision(pSSM) >= 71199)
3679 {
3680 uint32_t uVer = SSMR3HandleVersion(pSSM);
3681 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3682 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3683 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3684 cRegs = 112;
3685 }
3686 break;
3687
3688 case HDA_SSM_VERSION_2:
3689 case HDA_SSM_VERSION_3:
3690 cRegs = 112;
3691 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3692 break;
3693
3694 /* Since version 4 we store the register count to stay flexible. */
3695 case HDA_SSM_VERSION_4:
3696 case HDA_SSM_VERSION_5:
3697 case HDA_SSM_VERSION:
3698 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3699 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3700 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3701 break;
3702
3703 default:
3704 LogRel(("HDA: Unsupported / too new saved state version (%RU32)\n", uVersion));
3705 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3706 }
3707
3708 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3709 {
3710 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3711 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3712 }
3713 else
3714 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3715
3716 /*
3717 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3718 * *every* BDLE state, whereas it only needs to be stored
3719 * *once* for every stream. Most of the BDLE state we can
3720 * get out of the registers anyway, so just ignore those values.
3721 *
3722 * Also, only the current BDLE was saved, regardless whether
3723 * there were more than one (and there are at least two entries,
3724 * according to the spec).
3725 */
3726#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3727 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3728 AssertRCReturn(rc, rc); \
3729 rc = SSMR3Skip(pSSM, sizeof(uint64_t)); /* u64BdleCviAddr */ \
3730 AssertRCReturn(rc, rc); \
3731 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3732 AssertRCReturn(rc, rc); \
3733 rc = SSMR3GetU32(pSSM, &x->u32BDLIndex); /* u32BdleCvi */ \
3734 AssertRCReturn(rc, rc); \
3735 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleCviLen */ \
3736 AssertRCReturn(rc, rc); \
3737 rc = SSMR3GetU32(pSSM, &x->u32BufOff); /* u32BdleCviPos */ \
3738 AssertRCReturn(rc, rc); \
3739 rc = SSMR3Skip(pSSM, sizeof(uint8_t)); /* fBdleCviIoc */ \
3740 AssertRCReturn(rc, rc); \
3741 rc = SSMR3GetU32(pSSM, &x->cbBelowFIFOW); /* cbUnderFifoW */ \
3742 AssertRCReturn(rc, rc); \
3743 rc = SSMR3GetMem(pSSM, &x->au8FIFO, sizeof(x->au8FIFO)); \
3744 AssertRCReturn(rc, rc); \
3745 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3746 AssertRCReturn(rc, rc); \
3747
3748 /*
3749 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3750 */
3751 HDABDLESTATE StateBDLEDummy;
3752
3753 switch (uVersion)
3754 {
3755 case HDA_SSM_VERSION_1:
3756 case HDA_SSM_VERSION_2:
3757 case HDA_SSM_VERSION_3:
3758 case HDA_SSM_VERSION_4:
3759 {
3760 /* Only load the internal states.
3761 * The rest will be initialized from the saved registers later. */
3762
3763 /* Note: Only the *current* BDLE for a stream was saved! */
3764
3765 /* Output */
3766 rc = hdaStreamInit(pThis, &pThis->StrmStOut, 4 /* Stream number, hardcoded */);
3767 if (RT_FAILURE(rc))
3768 break;
3769 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStOut.State.cBDLE
3770 ? &pThis->StrmStOut.State.paBDLE[0].State : &StateBDLEDummy));
3771 /* Microphone-In */
3772 rc = hdaStreamInit(pThis, &pThis->StrmStMicIn, 2 /* Stream number, hardcoded */);
3773 if (RT_FAILURE(rc))
3774 break;
3775 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStMicIn.State.cBDLE
3776 ? &pThis->StrmStMicIn.State.paBDLE[0].State : &StateBDLEDummy));
3777 /* Line-In */
3778 rc = hdaStreamInit(pThis, &pThis->StrmStLineIn, 0 /* Stream number, hardcoded */);
3779 if (RT_FAILURE(rc))
3780 break;
3781 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, ( pThis->StrmStLineIn.State.cBDLE
3782 ? &pThis->StrmStLineIn.State.paBDLE[0].State : &StateBDLEDummy));
3783 break;
3784 }
3785
3786 /* Since v5 we support flexible stream and BDLE counts. */
3787 case HDA_SSM_VERSION_5:
3788 case HDA_SSM_VERSION:
3789 {
3790 uint32_t cStreams;
3791 rc = SSMR3GetU32(pSSM, &cStreams);
3792 if (RT_FAILURE(rc))
3793 break;
3794
3795 LogRel2(("hdaLoadExec: cStreams=%RU32\n", cStreams));
3796
3797 /* Load stream states. */
3798 for (uint32_t i = 0; i < cStreams; i++)
3799 {
3800 uint8_t uStreamID;
3801 rc = SSMR3GetU8(pSSM, &uStreamID);
3802 if (RT_FAILURE(rc))
3803 break;
3804
3805 PHDASTREAM pStrm;
3806 HDASTREAM StreamDummy;
3807
3808 switch (uStreamID)
3809 {
3810 case 0: /** @todo Use a define. */
3811 pStrm = &pThis->StrmStLineIn;
3812 break;
3813
3814 case 2: /** @todo Use a define. */
3815 pStrm = &pThis->StrmStMicIn;
3816 break;
3817
3818 case 4: /** @todo Use a define. */
3819 pStrm = &pThis->StrmStOut;
3820 break;
3821
3822 default:
3823 pStrm = &StreamDummy;
3824 break;
3825 }
3826
3827 RT_BZERO(pStrm, sizeof(HDASTREAM));
3828 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /* fFlags */, g_aSSMStreamStateFields5, NULL);
3829 if (RT_FAILURE(rc))
3830 break;
3831
3832 rc = hdaStreamInit(pThis, pStrm, uStreamID);
3833 if (RT_FAILURE(rc))
3834 {
3835 LogRel(("HDA: Stream #%RU32: Inititialization of stream (ID=%RU8, cBDLE=%RU32) failed, rc=%Rrc\n", i, uStreamID, pStrm->State.cBDLE, rc));
3836 break;
3837 }
3838
3839 /* Load BDLE states. */
3840 for (uint32_t a = 0; a < pStrm->State.cBDLE; a++)
3841 {
3842 if (uVersion == HDA_SSM_VERSION_5)
3843 {
3844 /* v5 saved the entire HDABDLE struct instead of only HDABDLESTATE,
3845 * so skip. */
3846 rc = SSMR3Skip(pSSM, 0x120 /* sizeof(HDABLDE) in v5 */);
3847 }
3848 else
3849 {
3850 rc = SSMR3GetStructEx(pSSM, &pStrm->State.paBDLE[a].State, sizeof(HDABDLESTATE),
3851 0 /* fFlags */, g_aSSMBDLEStateFields5, NULL);
3852 }
3853 if (RT_FAILURE(rc))
3854 break;
3855 }
3856
3857 /* Destroy dummy again. */
3858 if (pStrm == &StreamDummy)
3859 hdaStreamDestroy(pStrm);
3860 }
3861 break;
3862 }
3863
3864 default:
3865 AssertReleaseFailed(); /* Never reached. */
3866 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3867 }
3868
3869#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3870
3871 if (RT_SUCCESS(rc))
3872 {
3873 /*
3874 * Update stuff after the state changes.
3875 */
3876 bool fEnableIn = RT_BOOL(HDA_SDCTL(pThis, 0 /** @todo Use a define. */) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3877#ifdef VBOX_WITH_HDA_MIC_IN
3878 bool fEnableMicIn = RT_BOOL(HDA_SDCTL(pThis, 2 /** @todo Use a define. */) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3879#endif
3880 bool fEnableOut = RT_BOOL(HDA_SDCTL(pThis, 4 /** @todo Use a define. */) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3881
3882 PHDADRIVER pDrv;
3883 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3884 {
3885 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, fEnableIn);
3886 if (RT_FAILURE(rc))
3887 break;
3888#ifdef VBOX_WITH_HDA_MIC_IN
3889 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, fEnableMicIn);
3890 if (RT_FAILURE(rc))
3891 break;
3892#endif
3893 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, fEnableOut);
3894 if (RT_FAILURE(rc))
3895 break;
3896 }
3897 }
3898
3899 if (RT_SUCCESS(rc))
3900 {
3901 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3902 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3903 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3904 }
3905 else
3906 LogRel(("HDA: Failed loading device state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
3907
3908 LogFlowFuncLeaveRC(rc);
3909 return rc;
3910}
3911
3912#ifdef DEBUG
3913/* Debug and log type formatters. */
3914
3915/**
3916 * @callback_method_impl{FNRTSTRFORMATTYPE}
3917 */
3918static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3919 const char *pszType, void const *pvValue,
3920 int cchWidth, int cchPrecision, unsigned fFlags,
3921 void *pvUser)
3922{
3923 PHDABDLE pBDLE = (PHDABDLE)pvValue;
3924 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3925 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, DMA[%RU32 bytes @ 0x%x])",
3926 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW, pBDLE->u32BufSize, pBDLE->u64BufAdr);
3927}
3928
3929/**
3930 * @callback_method_impl{FNRTSTRFORMATTYPE}
3931 */
3932static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3933 const char *pszType, void const *pvValue,
3934 int cchWidth, int cchPrecision, unsigned fFlags,
3935 void *pvUser)
3936{
3937 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
3938 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3939 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
3940 uSDCTL,
3941 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
3942 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3943 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3944 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3945 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
3946 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3947 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3948 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3949}
3950
3951/**
3952 * @callback_method_impl{FNRTSTRFORMATTYPE}
3953 */
3954static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3955 const char *pszType, void const *pvValue,
3956 int cchWidth, int cchPrecision, unsigned fFlags,
3957 void *pvUser)
3958{
3959 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
3960 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, hdaSDFIFOSToBytes(uSDFIFOS));
3961}
3962
3963/**
3964 * @callback_method_impl{FNRTSTRFORMATTYPE}
3965 */
3966static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3967 const char *pszType, void const *pvValue,
3968 int cchWidth, int cchPrecision, unsigned fFlags,
3969 void *pvUser)
3970{
3971 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
3972 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
3973}
3974
3975/**
3976 * @callback_method_impl{FNRTSTRFORMATTYPE}
3977 */
3978static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3979 const char *pszType, void const *pvValue,
3980 int cchWidth, int cchPrecision, unsigned fFlags,
3981 void *pvUser)
3982{
3983 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3984 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3985 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3986 uSdSts,
3987 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3988 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3989 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3990 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3991}
3992
3993static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3994{
3995 int iReg = 0;
3996 for (; iReg < HDA_NREGS; ++iReg)
3997 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3998 return iReg;
3999 return -1;
4000}
4001
4002
4003static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
4004{
4005 Assert( pThis
4006 && iHdaIndex >= 0
4007 && iHdaIndex < HDA_NREGS);
4008 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
4009}
4010
4011/**
4012 * @callback_method_impl{FNDBGFHANDLERDEV}
4013 */
4014static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4015{
4016 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4017 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
4018 if (iHdaRegisterIndex != -1)
4019 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4020 else
4021 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
4022 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4023}
4024
4025static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
4026{
4027 Assert( pThis
4028 && iHdaStrmIndex >= 0
4029 && iHdaStrmIndex < 7);
4030 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
4031 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
4032 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
4033 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
4034 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
4035}
4036
4037static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
4038{
4039 /* todo: add args parsing */
4040 return -1;
4041}
4042
4043/**
4044 * @callback_method_impl{FNDBGFHANDLERDEV}
4045 */
4046static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4047{
4048 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4049 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
4050 if (iHdaStrmIndex != -1)
4051 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
4052 else
4053 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
4054 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
4055}
4056
4057/**
4058 * @callback_method_impl{FNDBGFHANDLERDEV}
4059 */
4060static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4061{
4062 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4063
4064 if (pThis->pCodec->pfnDbgListNodes)
4065 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
4066 else
4067 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4068}
4069
4070/**
4071 * @callback_method_impl{FNDBGFHANDLERDEV}
4072 */
4073static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4074{
4075 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4076
4077 if (pThis->pCodec->pfnDbgSelector)
4078 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
4079 else
4080 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4081}
4082
4083/**
4084 * @callback_method_impl{FNDBGFHANDLERDEV}
4085 */
4086static DECLCALLBACK(void) hdaInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4087{
4088 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4089
4090 if (pThis->pMixer)
4091 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
4092 else
4093 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
4094}
4095#endif /* DEBUG */
4096
4097/* PDMIBASE */
4098
4099/**
4100 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
4101 */
4102static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
4103{
4104 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
4105 Assert(&pThis->IBase == pInterface);
4106
4107 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4108 return NULL;
4109}
4110
4111
4112/* PDMDEVREG */
4113
4114/**
4115 * Reset notification.
4116 *
4117 * @returns VBox status code.
4118 * @param pDevIns The device instance data.
4119 *
4120 * @remark The original sources didn't install a reset handler, but it seems to
4121 * make sense to me so we'll do it.
4122 */
4123static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
4124{
4125 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4126
4127 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
4128 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
4129 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
4130 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
4131 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
4132 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
4133 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
4134 HDA_REG(pThis, CORBRP) = 0x0;
4135 HDA_REG(pThis, RIRBWP) = 0x0;
4136
4137 LogFunc(("Resetting ...\n"));
4138
4139 /*
4140 * Stop any audio currently playing and/or recording.
4141 */
4142 PHDADRIVER pDrv;
4143 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4144 {
4145 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
4146#ifdef VBOX_WITH_HDA_MIC_IN
4147 /* Ignore rc. */
4148 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
4149#endif
4150 /* Ditto. */
4151 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
4152 /* Ditto. */
4153 }
4154
4155 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
4156
4157 if (pThis->pu32CorbBuf)
4158 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
4159 else
4160 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
4161
4162 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
4163 if (pThis->pu64RirbBuf)
4164 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
4165 else
4166 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
4167
4168 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
4169
4170 /*
4171 * Stop the timer, if any.
4172 */
4173 int rc2;
4174 if (pThis->pTimer)
4175 {
4176 rc2 = TMTimerStop(pThis->pTimer);
4177 AssertRC(rc2);
4178 }
4179
4180 for (uint8_t u8Strm = 0; u8Strm < 8; u8Strm++) /** @todo Use a define here. */
4181 {
4182 PHDASTREAM pStrmSt = NULL;
4183 if (u8Strm == 0)
4184 pStrmSt = &pThis->StrmStOut;
4185# ifdef VBOX_WITH_HDA_MIC_IN
4186 else if (u8Strm == 2)
4187 pStrmSt = &pThis->StrmStMicIn;
4188# endif
4189 else if (u8Strm == 4)
4190 pStrmSt = &pThis->StrmStLineIn;
4191
4192 if (pStrmSt)
4193 {
4194 /* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
4195 HDA_STREAM_REG(pThis, CTL, u8Strm) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN);
4196
4197 hdaStreamReset(pThis, pStrmSt, u8Strm);
4198 }
4199 }
4200
4201 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
4202 HDA_REG(pThis, STATESTS) = 0x1;
4203
4204 /*
4205 * Start timer again, if any.
4206 */
4207 if (pThis->pTimer)
4208 {
4209 rc2 = TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
4210 AssertRC(rc2);
4211 }
4212
4213 LogRel(("HDA: Reset\n"));
4214}
4215
4216/**
4217 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4218 */
4219static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
4220{
4221 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4222
4223 PHDADRIVER pDrv;
4224 while (!RTListIsEmpty(&pThis->lstDrv))
4225 {
4226 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
4227
4228 RTListNodeRemove(&pDrv->Node);
4229 RTMemFree(pDrv);
4230 }
4231
4232 if (pThis->pMixer)
4233 {
4234 AudioMixerDestroy(pThis->pMixer);
4235 pThis->pMixer = NULL;
4236 }
4237
4238 if (pThis->pCodec)
4239 {
4240 int rc = hdaCodecDestruct(pThis->pCodec);
4241 AssertRC(rc);
4242
4243 RTMemFree(pThis->pCodec);
4244 pThis->pCodec = NULL;
4245 }
4246
4247 RTMemFree(pThis->pu32CorbBuf);
4248 pThis->pu32CorbBuf = NULL;
4249
4250 RTMemFree(pThis->pu64RirbBuf);
4251 pThis->pu64RirbBuf = NULL;
4252
4253 hdaStreamDestroy(&pThis->StrmStLineIn);
4254 hdaStreamDestroy(&pThis->StrmStMicIn);
4255 hdaStreamDestroy(&pThis->StrmStOut);
4256
4257 return VINF_SUCCESS;
4258}
4259
4260/**
4261 * Attach command.
4262 *
4263 * This is called to let the device attach to a driver for a specified LUN
4264 * during runtime. This is not called during VM construction, the device
4265 * constructor have to attach to all the available drivers.
4266 *
4267 * @returns VBox status code.
4268 * @param pDevIns The device instance.
4269 * @param uLUN The logical unit which is being detached.
4270 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4271 */
4272static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4273{
4274 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4275
4276 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
4277 ("HDA device does not support hotplugging\n"),
4278 VERR_INVALID_PARAMETER);
4279
4280 /*
4281 * Attach driver.
4282 */
4283 char *pszDesc = NULL;
4284 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4285 AssertMsgReturn(pszDesc,
4286 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
4287 VERR_NO_MEMORY);
4288
4289 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
4290 &pThis->IBase, &pThis->pDrvBase, pszDesc);
4291 if (RT_SUCCESS(rc))
4292 {
4293 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4294 if (pDrv)
4295 {
4296 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
4297 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4298 pDrv->pHDAState = pThis;
4299 pDrv->uLUN = uLUN;
4300
4301 /*
4302 * For now we always set the driver at LUN 0 as our primary
4303 * host backend. This might change in the future.
4304 */
4305 if (pDrv->uLUN == 0)
4306 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
4307
4308 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
4309
4310 /* Attach to driver list. */
4311 RTListAppend(&pThis->lstDrv, &pDrv->Node);
4312 }
4313 else
4314 rc = VERR_NO_MEMORY;
4315 }
4316 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
4317 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
4318 {
4319 LogFunc(("No attached driver for LUN #%u\n", uLUN));
4320 }
4321 else if (RT_FAILURE(rc))
4322 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
4323 uLUN, pszDesc, rc));
4324
4325 RTStrFree(pszDesc);
4326
4327 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4328 return rc;
4329}
4330
4331static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4332{
4333 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
4334
4335 LogFlowFuncEnter();
4336}
4337
4338/**
4339 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4340 */
4341static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
4342{
4343 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4344 Assert(iInstance == 0);
4345 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4346
4347 /*
4348 * Validations.
4349 */
4350 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
4351 "RCEnabled\0"
4352 "TimerHz\0"))
4353 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4354 N_ ("Invalid configuration for the Intel HDA device"));
4355
4356 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
4357 if (RT_FAILURE(rc))
4358 return PDMDEV_SET_ERROR(pDevIns, rc,
4359 N_("HDA configuration error: failed to read RCEnabled as boolean"));
4360 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
4361 if (RT_FAILURE(rc))
4362 return PDMDEV_SET_ERROR(pDevIns, rc,
4363 N_("HDA configuration error: failed to read R0Enabled as boolean"));
4364#ifndef VBOX_WITH_AUDIO_CALLBACKS
4365 uint16_t uTimerHz;
4366 rc = CFGMR3QueryU16Def(pCfgHandle, "TimerHz", &uTimerHz, 200 /* Hz */);
4367 if (RT_FAILURE(rc))
4368 return PDMDEV_SET_ERROR(pDevIns, rc,
4369 N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4370#endif
4371
4372 /*
4373 * Initialize data (most of it anyway).
4374 */
4375 pThis->pDevInsR3 = pDevIns;
4376 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4377 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4378 /* IBase */
4379 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
4380
4381 /* PCI Device */
4382 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
4383 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
4384
4385 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
4386 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
4387 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
4388 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
4389 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
4390 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
4391 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
4392 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
4393 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
4394 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
4395 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
4396
4397#if defined(HDA_AS_PCI_EXPRESS)
4398 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
4399#elif defined(VBOX_WITH_MSI_DEVICES)
4400 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
4401#else
4402 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
4403#endif
4404
4405 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
4406 /// of these values needs to be properly documented!
4407 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
4408 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
4409
4410 /* Power Management */
4411 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
4412 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
4413 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
4414
4415#ifdef HDA_AS_PCI_EXPRESS
4416 /* PCI Express */
4417 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
4418 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
4419 /* Device flags */
4420 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
4421 /* version */ 0x1 |
4422 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
4423 /* MSI */ (100) << 9 );
4424 /* Device capabilities */
4425 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
4426 /* Device control */
4427 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
4428 /* Device status */
4429 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
4430 /* Link caps */
4431 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
4432 /* Link control */
4433 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
4434 /* Link status */
4435 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
4436 /* Slot capabilities */
4437 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
4438 /* Slot control */
4439 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
4440 /* Slot status */
4441 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
4442 /* Root control */
4443 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
4444 /* Root capabilities */
4445 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
4446 /* Root status */
4447 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
4448 /* Device capabilities 2 */
4449 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
4450 /* Device control 2 */
4451 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
4452 /* Link control 2 */
4453 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
4454 /* Slot control 2 */
4455 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
4456#endif
4457
4458 /*
4459 * Register the PCI device.
4460 */
4461 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
4462 if (RT_FAILURE(rc))
4463 return rc;
4464
4465 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
4466 if (RT_FAILURE(rc))
4467 return rc;
4468
4469#ifdef VBOX_WITH_MSI_DEVICES
4470 PDMMSIREG MsiReg;
4471 RT_ZERO(MsiReg);
4472 MsiReg.cMsiVectors = 1;
4473 MsiReg.iMsiCapOffset = 0x60;
4474 MsiReg.iMsiNextOffset = 0x50;
4475 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4476 if (RT_FAILURE(rc))
4477 {
4478 /* That's OK, we can work without MSI */
4479 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
4480 }
4481#endif
4482
4483 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
4484 if (RT_FAILURE(rc))
4485 return rc;
4486
4487 RTListInit(&pThis->lstDrv);
4488
4489 uint8_t uLUN;
4490 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
4491 {
4492 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
4493 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
4494 if (RT_FAILURE(rc))
4495 {
4496 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4497 rc = VINF_SUCCESS;
4498
4499 break;
4500 }
4501
4502 uLUN++;
4503 }
4504
4505 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
4506
4507 if (RT_SUCCESS(rc))
4508 {
4509 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
4510 if (RT_SUCCESS(rc))
4511 {
4512 /* Set a default audio format for our mixer. */
4513 PDMAUDIOSTREAMCFG streamCfg;
4514 streamCfg.uHz = 44100;
4515 streamCfg.cChannels = 2;
4516 streamCfg.enmFormat = AUD_FMT_S16;
4517 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
4518
4519 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
4520 AssertRC(rc);
4521
4522 /* Add all required audio sinks. */
4523 rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output",
4524 AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
4525 AssertRC(rc);
4526
4527 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In",
4528 AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
4529 AssertRC(rc);
4530
4531 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
4532 AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
4533 AssertRC(rc);
4534
4535 /* There is no master volume control. Set the master to max. */
4536 PDMAUDIOVOLUME vol = { false, 255, 255 };
4537 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
4538 AssertRC(rc);
4539 }
4540 }
4541
4542 if (RT_SUCCESS(rc))
4543 {
4544 /* Construct codec. */
4545 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
4546 if (!pThis->pCodec)
4547 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
4548
4549 /* Audio driver callbacks for multiplexing. */
4550 pThis->pCodec->pfnCloseIn = hdaCloseIn;
4551 pThis->pCodec->pfnCloseOut = hdaCloseOut;
4552 pThis->pCodec->pfnOpenIn = hdaOpenIn;
4553 pThis->pCodec->pfnOpenOut = hdaOpenOut;
4554 pThis->pCodec->pfnReset = hdaCodecReset;
4555 pThis->pCodec->pfnSetVolume = hdaSetVolume;
4556
4557 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
4558
4559 /* Construct the codec. */
4560 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
4561 if (RT_FAILURE(rc))
4562 AssertRCReturn(rc, rc);
4563
4564 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
4565 verb F20 should provide device/codec recognition. */
4566 Assert(pThis->pCodec->u16VendorId);
4567 Assert(pThis->pCodec->u16DeviceId);
4568 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
4569 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
4570 }
4571
4572 if (RT_SUCCESS(rc))
4573 {
4574 rc = hdaStreamCreate(&pThis->StrmStLineIn);
4575 AssertRC(rc);
4576#ifdef VBOX_WITH_HDA_MIC_IN
4577 rc = hdaStreamCreate(&pThis->StrmStMicIn);
4578 AssertRC(rc);
4579#endif
4580 rc = hdaStreamCreate(&pThis->StrmStOut);
4581 AssertRC(rc);
4582 }
4583
4584 if (RT_SUCCESS(rc))
4585 {
4586 hdaReset(pDevIns);
4587
4588 /*
4589 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4590 * hdaReset shouldn't affects these registers.
4591 */
4592 HDA_REG(pThis, WAKEEN) = 0x0;
4593 HDA_REG(pThis, STATESTS) = 0x0;
4594
4595#ifdef DEBUG
4596 /*
4597 * Debug and string formatter types.
4598 */
4599 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
4600 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
4601 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
4602 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
4603 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaInfoMixer);
4604
4605 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
4606 AssertRC(rc);
4607 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
4608 AssertRC(rc);
4609 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
4610 AssertRC(rc);
4611 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
4612 AssertRC(rc);
4613 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
4614 AssertRC(rc);
4615#endif /* DEBUG */
4616
4617 /*
4618 * Some debug assertions.
4619 */
4620 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
4621 {
4622 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
4623 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
4624
4625 /* binary search order. */
4626 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
4627 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4628 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4629
4630 /* alignment. */
4631 AssertReleaseMsg( pReg->size == 1
4632 || (pReg->size == 2 && (pReg->offset & 1) == 0)
4633 || (pReg->size == 3 && (pReg->offset & 3) == 0)
4634 || (pReg->size == 4 && (pReg->offset & 3) == 0),
4635 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4636
4637 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
4638 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
4639 if (pReg->offset & 3)
4640 {
4641 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
4642 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4643 if (pPrevReg)
4644 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
4645 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4646 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
4647 }
4648#if 0
4649 if ((pReg->offset + pReg->size) & 3)
4650 {
4651 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4652 if (pNextReg)
4653 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
4654 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4655 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4656 }
4657#endif
4658 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
4659 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
4660 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4661 }
4662 }
4663
4664# ifndef VBOX_WITH_AUDIO_CALLBACKS
4665 if (RT_SUCCESS(rc))
4666 {
4667 /* Start the emulation timer. */
4668 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
4669 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
4670 AssertRCReturn(rc, rc);
4671
4672 if (RT_SUCCESS(rc))
4673 {
4674 pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
4675 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
4676 LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
4677
4678 /* Fire off timer. */
4679 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
4680 }
4681 }
4682# else
4683 if (RT_SUCCESS(rc))
4684 {
4685 PHDADRIVER pDrv;
4686 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4687 {
4688 /* Only register primary driver.
4689 * The device emulation does the output multiplexing then. */
4690 if (pDrv->Flags != PDMAUDIODRVFLAG_PRIMARY)
4691 continue;
4692
4693 PDMAUDIOCALLBACK AudioCallbacks[2];
4694
4695 HDACALLBACKCTX Ctx = { pThis, pDrv };
4696
4697 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
4698 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
4699 AudioCallbacks[0].pvCtx = &Ctx;
4700 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
4701
4702 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
4703 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
4704 AudioCallbacks[1].pvCtx = &Ctx;
4705 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
4706
4707 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
4708 if (RT_FAILURE(rc))
4709 break;
4710 }
4711 }
4712# endif
4713
4714# ifdef VBOX_WITH_STATISTICS
4715 if (RT_SUCCESS(rc))
4716 {
4717 /*
4718 * Register statistics.
4719 */
4720# ifndef VBOX_WITH_AUDIO_CALLBACKS
4721 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
4722# endif
4723 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
4724 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
4725 }
4726# endif
4727
4728 LogFlowFuncLeaveRC(rc);
4729 return rc;
4730}
4731
4732/**
4733 * The device registration structure.
4734 */
4735const PDMDEVREG g_DeviceICH6_HDA =
4736{
4737 /* u32Version */
4738 PDM_DEVREG_VERSION,
4739 /* szName */
4740 "hda",
4741 /* szRCMod */
4742 "VBoxDDRC.rc",
4743 /* szR0Mod */
4744 "VBoxDDR0.r0",
4745 /* pszDescription */
4746 "Intel HD Audio Controller",
4747 /* fFlags */
4748 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
4749 /* fClass */
4750 PDM_DEVREG_CLASS_AUDIO,
4751 /* cMaxInstances */
4752 1,
4753 /* cbInstance */
4754 sizeof(HDASTATE),
4755 /* pfnConstruct */
4756 hdaConstruct,
4757 /* pfnDestruct */
4758 hdaDestruct,
4759 /* pfnRelocate */
4760 NULL,
4761 /* pfnMemSetup */
4762 NULL,
4763 /* pfnPowerOn */
4764 NULL,
4765 /* pfnReset */
4766 hdaReset,
4767 /* pfnSuspend */
4768 NULL,
4769 /* pfnResume */
4770 NULL,
4771 /* pfnAttach */
4772 NULL,
4773 /* pfnDetach */
4774 NULL,
4775 /* pfnQueryInterface. */
4776 NULL,
4777 /* pfnInitComplete */
4778 NULL,
4779 /* pfnPowerOff */
4780 NULL,
4781 /* pfnSoftReset */
4782 NULL,
4783 /* u32VersionEnd */
4784 PDM_DEVREG_VERSION
4785};
4786
4787#endif /* IN_RING3 */
4788#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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