DevIchHda.cpp@ 59376

Last change on this file since 59376 was 59376, checked in by vboxsync, 9 years ago
Audio: if the backend couldn't be initialized (ie pfnInit() failed), use the NULL audio driver
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 185.0 KB

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1	/* $Id: DevIchHda.cpp 59376 2016-01-18 12:59:36Z vboxsync $ */
2	/** @file
3	* DevIchHda - VBox ICH Intel HD Audio Controller.
4	*
5	* Implemented against the specifications found in "High Definition Audio
6	* Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7	* HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8	*/
9
10	/*
11	* Copyright (C) 2006-2016 Oracle Corporation
12	*
13	* This file is part of VirtualBox Open Source Edition (OSE), as
14	* available from http://www.virtualbox.org. This file is free software;
15	* you can redistribute it and/or modify it under the terms of the GNU
16	* General Public License (GPL) as published by the Free Software
17	* Foundation, in version 2 as it comes in the "COPYING" file of the
18	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20	*/
21
22
23	/*********************************************************************************************************************************
24	* Header Files *
25	*********************************************************************************************************************************/
26	#define LOG_GROUP LOG_GROUP_DEV_HDA
27	#include <VBox/log.h>
28	#include <VBox/vmm/pdmdev.h>
29	#include <VBox/vmm/pdmaudioifs.h>
30	#include <VBox/version.h>
31
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-math.h>
35	#include <iprt/list.h>
36	#ifdef IN_RING3
37	# include <iprt/mem.h>
38	# include <iprt/semaphore.h>
39	# include <iprt/string.h>
40	# include <iprt/uuid.h>
41	#endif
42
43	#include "VBoxDD.h"
44
45	#include "AudioMixBuffer.h"
46	#include "AudioMixer.h"
47	#include "DevIchHdaCodec.h"
48	#include "DrvAudio.h"
49
50
51	/*********************************************************************************************************************************
52	* Defined Constants And Macros *
53	*********************************************************************************************************************************/
54	//#define HDA_AS_PCI_EXPRESS
55	#define VBOX_WITH_INTEL_HDA
56
57	#ifdef DEBUG_andy
58	/* Enables experimental support for separate mic-in handling.
59	Do not enable this yet for regular builds, as this needs more testing first! */
60	//# define VBOX_WITH_HDA_MIC_IN
61	#endif
62
63	#if defined(VBOX_WITH_HP_HDA)
64	/* HP Pavilion dv4t-1300 */
65	# define HDA_PCI_VENDOR_ID 0x103c
66	# define HDA_PCI_DEVICE_ID 0x30f7
67	#elif defined(VBOX_WITH_INTEL_HDA)
68	/* Intel HDA controller */
69	# define HDA_PCI_VENDOR_ID 0x8086
70	# define HDA_PCI_DEVICE_ID 0x2668
71	#elif defined(VBOX_WITH_NVIDIA_HDA)
72	/* nVidia HDA controller */
73	# define HDA_PCI_VENDOR_ID 0x10de
74	# define HDA_PCI_DEVICE_ID 0x0ac0
75	#else
76	# error "Please specify your HDA device vendor/device IDs"
77	#endif
78
79	/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
80	* updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
81	* is read only except for bit 15 like the HDA spec states.
82	*
83	* Btw. the CORBRPRST implementation is incomplete according to both docs (sw
84	* writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
85	#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
86
87	#define HDA_NREGS 114
88	#define HDA_NREGS_SAVED 112
89
90	/**
91	* NB: Register values stored in memory (au32Regs[]) are indexed through
92	* the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
93	* register descriptors in g_aHdaRegMap[] are indexed through the
94	* HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
95	*
96	* The au32Regs[] layout is kept unchanged for saved state
97	* compatibility. */
98
99	/* Registers */
100	#define HDA_REG_IND_NAME(x) HDA_REG_##x
101	#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
102	#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
103	#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
104	#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
105	#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
106	#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
107	#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
108
109
110	#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
111	#define HDA_RMX_GCAP 0
112	/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
113	* oss (15:12) - number of output streams supported
114	* iss (11:8) - number of input streams supported
115	* bss (7:3) - number of bidirectional streams supported
116	* bds (2:1) - number of serial data out signals supported
117	* b64sup (0) - 64 bit addressing supported.
118	*/
119	#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
120	( (((oss) & 0xF) << 12) \
121	\| (((iss) & 0xF) << 8) \
122	\| (((bss) & 0x1F) << 3) \
123	\| (((bds) & 0x3) << 2) \
124	\| ((b64sup) & 1))
125
126	#define HDA_REG_VMIN 1 /* 0x02 */
127	#define HDA_RMX_VMIN 1
128
129	#define HDA_REG_VMAJ 2 /* 0x03 */
130	#define HDA_RMX_VMAJ 2
131
132	#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
133	#define HDA_RMX_OUTPAY 3
134
135	#define HDA_REG_INPAY 4 /* 0x06-0x07 */
136	#define HDA_RMX_INPAY 4
137
138	#define HDA_REG_GCTL 5 /* 0x08-0x0B */
139	#define HDA_RMX_GCTL 5
140	#define HDA_GCTL_RST_SHIFT 0
141	#define HDA_GCTL_FSH_SHIFT 1
142	#define HDA_GCTL_UR_SHIFT 8
143
144	#define HDA_REG_WAKEEN 6 /* 0x0C */
145	#define HDA_RMX_WAKEEN 6
146
147	#define HDA_REG_STATESTS 7 /* 0x0E */
148	#define HDA_RMX_STATESTS 7
149	#define HDA_STATES_SCSF 0x7
150
151	#define HDA_REG_GSTS 8 /* 0x10-0x11*/
152	#define HDA_RMX_GSTS 8
153	#define HDA_GSTS_FSH_SHIFT 1
154
155	#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
156	#define HDA_RMX_OUTSTRMPAY 112
157
158	#define HDA_REG_INSTRMPAY 10 /* 0x1a */
159	#define HDA_RMX_INSTRMPAY 113
160
161	#define HDA_REG_INTCTL 11 /* 0x20 */
162	#define HDA_RMX_INTCTL 9
163	#define HDA_INTCTL_GIE_SHIFT 31
164	#define HDA_INTCTL_CIE_SHIFT 30
165	#define HDA_INTCTL_S0_SHIFT 0
166	#define HDA_INTCTL_S1_SHIFT 1
167	#define HDA_INTCTL_S2_SHIFT 2
168	#define HDA_INTCTL_S3_SHIFT 3
169	#define HDA_INTCTL_S4_SHIFT 4
170	#define HDA_INTCTL_S5_SHIFT 5
171	#define HDA_INTCTL_S6_SHIFT 6
172	#define HDA_INTCTL_S7_SHIFT 7
173	#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
174
175	#define HDA_REG_INTSTS 12 /* 0x24 */
176	#define HDA_RMX_INTSTS 10
177	#define HDA_INTSTS_GIS_SHIFT 31
178	#define HDA_INTSTS_CIS_SHIFT 30
179	#define HDA_INTSTS_S0_SHIFT 0
180	#define HDA_INTSTS_S1_SHIFT 1
181	#define HDA_INTSTS_S2_SHIFT 2
182	#define HDA_INTSTS_S3_SHIFT 3
183	#define HDA_INTSTS_S4_SHIFT 4
184	#define HDA_INTSTS_S5_SHIFT 5
185	#define HDA_INTSTS_S6_SHIFT 6
186	#define HDA_INTSTS_S7_SHIFT 7
187	#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
188
189	#define HDA_REG_WALCLK 13 /* 0x24 */
190	#define HDA_RMX_WALCLK /* Not defined! */
191
192	/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
193	* ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
194	* the datasheet.
195	*/
196	#define HDA_REG_SSYNC 14 /* 0x34 */
197	#define HDA_RMX_SSYNC 12
198
199	#define HDA_REG_CORBLBASE 15 /* 0x40 */
200	#define HDA_RMX_CORBLBASE 13
201
202	#define HDA_REG_CORBUBASE 16 /* 0x44 */
203	#define HDA_RMX_CORBUBASE 14
204
205	#define HDA_REG_CORBWP 17 /* 0x48 */
206	#define HDA_RMX_CORBWP 15
207
208	#define HDA_REG_CORBRP 18 /* 0x4A */
209	#define HDA_RMX_CORBRP 16
210	#define HDA_CORBRP_RST_SHIFT 15
211	#define HDA_CORBRP_WP_SHIFT 0
212	#define HDA_CORBRP_WP_MASK 0xFF
213
214	#define HDA_REG_CORBCTL 19 /* 0x4C */
215	#define HDA_RMX_CORBCTL 17
216	#define HDA_CORBCTL_DMA_SHIFT 1
217	#define HDA_CORBCTL_CMEIE_SHIFT 0
218
219	#define HDA_REG_CORBSTS 20 /* 0x4D */
220	#define HDA_RMX_CORBSTS 18
221	#define HDA_CORBSTS_CMEI_SHIFT 0
222
223	#define HDA_REG_CORBSIZE 21 /* 0x4E */
224	#define HDA_RMX_CORBSIZE 19
225	#define HDA_CORBSIZE_SZ_CAP 0xF0
226	#define HDA_CORBSIZE_SZ 0x3
227	/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
228
229	#define HDA_REG_RIRBLBASE 22 /* 0x50 */
230	#define HDA_RMX_RIRBLBASE 20
231
232	#define HDA_REG_RIRBUBASE 23 /* 0x54 */
233	#define HDA_RMX_RIRBUBASE 21
234
235	#define HDA_REG_RIRBWP 24 /* 0x58 */
236	#define HDA_RMX_RIRBWP 22
237	#define HDA_RIRBWP_RST_SHIFT 15
238	#define HDA_RIRBWP_WP_MASK 0xFF
239
240	#define HDA_REG_RINTCNT 25 /* 0x5A */
241	#define HDA_RMX_RINTCNT 23
242	#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
243
244	#define HDA_REG_RIRBCTL 26 /* 0x5C */
245	#define HDA_RMX_RIRBCTL 24
246	#define HDA_RIRBCTL_RIC_SHIFT 0
247	#define HDA_RIRBCTL_DMA_SHIFT 1
248	#define HDA_ROI_DMA_SHIFT 2
249
250	#define HDA_REG_RIRBSTS 27 /* 0x5D */
251	#define HDA_RMX_RIRBSTS 25
252	#define HDA_RIRBSTS_RINTFL_SHIFT 0
253	#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
254
255	#define HDA_REG_RIRBSIZE 28 /* 0x5E */
256	#define HDA_RMX_RIRBSIZE 26
257	#define HDA_RIRBSIZE_SZ_CAP 0xF0
258	#define HDA_RIRBSIZE_SZ 0x3
259
260	#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
261	#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
262
263
264	#define HDA_REG_IC 29 /* 0x60 */
265	#define HDA_RMX_IC 27
266
267	#define HDA_REG_IR 30 /* 0x64 */
268	#define HDA_RMX_IR 28
269
270	#define HDA_REG_IRS 31 /* 0x68 */
271	#define HDA_RMX_IRS 29
272	#define HDA_IRS_ICB_SHIFT 0
273	#define HDA_IRS_IRV_SHIFT 1
274
275	#define HDA_REG_DPLBASE 32 /* 0x70 */
276	#define HDA_RMX_DPLBASE 30
277	#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
278
279	#define HDA_REG_DPUBASE 33 /* 0x74 */
280	#define HDA_RMX_DPUBASE 31
281	#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
282
283	#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
284
285	#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
286	#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
287	/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
288	#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
289
290	#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
291
292	#define HDA_REG_SD0CTL 34 /* 0x80 */
293	#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
294	#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
295	#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
296	#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
297	#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
298	#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
299	#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
300	#define HDA_RMX_SD0CTL 32
301	#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
302	#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
303	#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
304	#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
305	#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
306	#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
307	#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
308
309	#define SD(func, num) SD##num##func
310
311	#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
312	#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
313	#define HDA_SDCTL_NUM_MASK 0xF
314	#define HDA_SDCTL_NUM_SHIFT 20
315	#define HDA_SDCTL_DIR_SHIFT 19
316	#define HDA_SDCTL_TP_SHIFT 18
317	#define HDA_SDCTL_STRIPE_MASK 0x3
318	#define HDA_SDCTL_STRIPE_SHIFT 16
319	#define HDA_SDCTL_DEIE_SHIFT 4
320	#define HDA_SDCTL_FEIE_SHIFT 3
321	#define HDA_SDCTL_ICE_SHIFT 2
322	#define HDA_SDCTL_RUN_SHIFT 1
323	#define HDA_SDCTL_SRST_SHIFT 0
324
325	#define HDA_REG_SD0STS 35 /* 0x83 */
326	#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
327	#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
328	#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
329	#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
330	#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
331	#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
332	#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
333	#define HDA_RMX_SD0STS 33
334	#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
335	#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
336	#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
337	#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
338	#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
339	#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
340	#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
341
342	#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
343	#define HDA_SDSTS_FIFORDY_SHIFT 5
344	#define HDA_SDSTS_DE_SHIFT 4
345	#define HDA_SDSTS_FE_SHIFT 3
346	#define HDA_SDSTS_BCIS_SHIFT 2
347
348	#define HDA_REG_SD0LPIB 36 /* 0x84 */
349	#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
350	#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
351	#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
352	#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
353	#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
354	#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
355	#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
356	#define HDA_RMX_SD0LPIB 34
357	#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
358	#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
359	#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
360	#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
361	#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
362	#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
363	#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
364
365	#define HDA_REG_SD0CBL 37 /* 0x88 */
366	#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
367	#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
368	#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
369	#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
370	#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
371	#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
372	#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
373	#define HDA_RMX_SD0CBL 35
374	#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
375	#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
376	#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
377	#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
378	#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
379	#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
380	#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
381
382	#define HDA_REG_SD0LVI 38 /* 0x8C */
383	#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
384	#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
385	#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
386	#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
387	#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
388	#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
389	#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
390	#define HDA_RMX_SD0LVI 36
391	#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
392	#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
393	#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
394	#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
395	#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
396	#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
397	#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
398
399	#define HDA_REG_SD0FIFOW 39 /* 0x8E */
400	#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
401	#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
402	#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
403	#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
404	#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
405	#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
406	#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
407	#define HDA_RMX_SD0FIFOW 37
408	#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
409	#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
410	#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
411	#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
412	#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
413	#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
414	#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
415
416	/*
417	* ICH6 datasheet defined limits for FIFOW values (18.2.38).
418	*/
419	#define HDA_SDFIFOW_8B 0x2
420	#define HDA_SDFIFOW_16B 0x3
421	#define HDA_SDFIFOW_32B 0x4
422
423	#define HDA_REG_SD0FIFOS 40 /* 0x90 */
424	#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
425	#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
426	#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
427	#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
428	#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
429	#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
430	#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
431	#define HDA_RMX_SD0FIFOS 38
432	#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
433	#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
434	#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
435	#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
436	#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
437	#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
438	#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
439
440	/*
441	* ICH6 datasheet defines limits for FIFOS registers (18.2.39)
442	* formula: size - 1
443	* Other values not listed are not supported.
444	*/
445	#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
446	#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
447
448	#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
449	#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
450	#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
451	#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
452	#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
453	#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
454	#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
455
456	#define HDA_REG_SD0FMT 41 /* 0x92 */
457	#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
458	#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
459	#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
460	#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
461	#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
462	#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
463	#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
464	#define HDA_RMX_SD0FMT 39
465	#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
466	#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
467	#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
468	#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
469	#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
470	#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
471	#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
472
473	#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
474	#define HDA_SDFMT_BASE_RATE_SHIFT 14
475	#define HDA_SDFMT_MULT_SHIFT 11
476	#define HDA_SDFMT_MULT_MASK 0x7
477	#define HDA_SDFMT_DIV_SHIFT 8
478	#define HDA_SDFMT_DIV_MASK 0x7
479	#define HDA_SDFMT_BITS_SHIFT 4
480	#define HDA_SDFMT_BITS_MASK 0x7
481	#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
482	#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
483	#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
484
485	#define HDA_REG_SD0BDPL 42 /* 0x98 */
486	#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
487	#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
488	#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
489	#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
490	#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
491	#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
492	#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
493	#define HDA_RMX_SD0BDPL 40
494	#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
495	#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
496	#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
497	#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
498	#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
499	#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
500	#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
501
502	#define HDA_REG_SD0BDPU 43 /* 0x9C */
503	#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
504	#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
505	#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
506	#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
507	#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
508	#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
509	#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
510	#define HDA_RMX_SD0BDPU 41
511	#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
512	#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
513	#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
514	#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
515	#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
516	#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
517	#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
518
519	#define HDA_CODEC_CAD_SHIFT 28
520	/* Encodes the (required) LUN into a codec command. */
521	#define HDA_CODEC_CMD(cmd, lun) ((cmd) \| (lun << HDA_CODEC_CAD_SHIFT))
522
523
524
525	/*********************************************************************************************************************************
526	* Structures and Typedefs *
527	*********************************************************************************************************************************/
528
529	/**
530	* Internal state of a Buffer Descriptor List Entry (BDLE),
531	* needed to keep track of the data needed for the actual device
532	* emulation.
533	*/
534	typedef struct HDABDLESTATE
535	{
536	/** Own index within the BDL (Buffer Descriptor List). */
537	uint32_t u32BDLIndex;
538	/** Number of bytes below the stream's FIFO watermark (SDFIFOW).
539	* Used to check if we need fill up the FIFO again. */
540	uint32_t cbBelowFIFOW;
541	/** The buffer descriptor's internal DMA buffer. */
542	uint8_t au8FIFO[HDA_SDONFIFO_256B + 1];
543	/** Current offset in DMA buffer (in bytes).*/
544	uint32_t u32BufOff;
545	uint32_t Padding;
546	} HDABDLESTATE, *PHDABDLESTATE;
547
548	/**
549	* Buffer Descriptor List Entry (BDLE) (3.6.3).
550	*
551	* Contains only register values which do not change until a
552	* stream reset occurs.
553	*/
554	typedef struct HDABDLE
555	{
556	/** Starting address of the actual buffer. Must be 128-bit aligned. */
557	uint64_t u64BufAdr;
558	/** Size of the actual buffer (in bytes). */
559	uint32_t u32BufSize;
560	/** Interrupt on completion; the controller will generate
561	* an interrupt when the last byte of the buffer has been
562	* fetched by the DMA engine. */
563	bool fIntOnCompletion;
564	/** Internal state of this BDLE.
565	* Not part of the actual BDLE registers. */
566	HDABDLESTATE State;
567	} HDABDLE, *PHDABDLE;
568
569	/**
570	* Internal state of a HDA stream.
571	*/
572	typedef struct HDASTREAMSTATE
573	{
574	/** Current BDLE to use. Wraps around to 0 if
575	* maximum (cBDLE) is reached. */
576	uint16_t uCurBDLE;
577	/** Stop indicator. */
578	volatile bool fDoStop;
579	/** Flag indicating whether this stream is in an
580	* active (operative) state or not. */
581	volatile bool fActive;
582	/** Flag indicating whether this stream currently is
583	* in reset mode and therefore not acccessible by the guest. */
584	volatile bool fInReset;
585	/** Unused, padding. */
586	bool fPadding;
587	/** Event signalling that the stream's state has been changed. */
588	RTSEMEVENT hStateChangedEvent;
589	/** Current BDLE (Buffer Descriptor List Entry). */
590	HDABDLE BDLE;
591	} HDASTREAMSTATE, *PHDASTREAMSTATE;
592
593	/**
594	* Structure for keeping a HDA stream state.
595	*
596	* Contains only register values which do not change until a
597	* stream reset occurs.
598	*/
599	typedef struct HDASTREAM
600	{
601	/** Stream number (SDn). */
602	uint8_t u8Strm;
603	uint8_t Padding0[7];
604	/** DMA base address (SDnBDPU - SDnBDPL). */
605	uint64_t u64BaseDMA;
606	/** Cyclic Buffer Length (SDnCBL).
607	* Represents the size of the ring buffer. */
608	uint32_t u32CBL;
609	/** Format (SDnFMT). */
610	uint16_t u16FMT;
611	/** FIFO Size (FIFOS).
612	* Maximum number of bytes that may have been DMA'd into
613	* memory but not yet transmitted on the link.
614	*
615	* Must be a power of two. */
616	uint16_t u16FIFOS;
617	/** Last Valid Index (SDnLVI). */
618	uint16_t u16LVI;
619	uint16_t Padding1[3];
620	/** Internal state of this stream. */
621	HDASTREAMSTATE State;
622	} HDASTREAM, *PHDASTREAM;
623
624	typedef struct HDAINPUTSTREAM
625	{
626	/** PCM line input stream. */
627	R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
628	/** Mixer handle for line input stream. */
629	R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
630	} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
631
632	typedef struct HDAOUTPUTSTREAM
633	{
634	/** PCM output stream. */
635	R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
636	/** Mixer handle for line output stream. */
637	R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
638	} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
639
640	/**
641	* Struct for maintaining a host backend driver.
642	* This driver must be associated to one, and only one,
643	* HDA codec. The HDA controller does the actual multiplexing
644	* of HDA codec data to various host backend drivers then.
645	*
646	* This HDA device uses a timer in order to synchronize all
647	* read/write accesses across all attached LUNs / backends.
648	*/
649	typedef struct HDADRIVER
650	{
651	/** Node for storing this driver in our device driver list of HDASTATE. */
652	RTLISTNODER3 Node;
653	/** Pointer to HDA controller (state). */
654	R3PTRTYPE(PHDASTATE) pHDAState;
655	/** Driver flags. */
656	PDMAUDIODRVFLAGS Flags;
657	uint8_t u32Padding0[2];
658	/** LUN to which this driver has been assigned. */
659	uint8_t uLUN;
660	/** Whether this driver is in an attached state or not. */
661	bool fAttached;
662	/** Pointer to attached driver base interface. */
663	R3PTRTYPE(PPDMIBASE) pDrvBase;
664	/** Audio connector interface to the underlying host backend. */
665	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
666	/** Stream for line input. */
667	HDAINPUTSTREAM LineIn;
668	/** Stream for mic input. */
669	HDAINPUTSTREAM MicIn;
670	/** Stream for output. */
671	HDAOUTPUTSTREAM Out;
672	} HDADRIVER;
673
674	/**
675	* ICH Intel HD Audio Controller state.
676	*/
677	typedef struct HDASTATE
678	{
679	/** The PCI device structure. */
680	PCIDevice PciDev;
681	/** R3 Pointer to the device instance. */
682	PPDMDEVINSR3 pDevInsR3;
683	/** R0 Pointer to the device instance. */
684	PPDMDEVINSR0 pDevInsR0;
685	/** R0 Pointer to the device instance. */
686	PPDMDEVINSRC pDevInsRC;
687	/** Padding for alignment. */
688	uint32_t u32Padding;
689	/** The base interface for LUN\#0. */
690	PDMIBASE IBase;
691	RTGCPHYS MMIOBaseAddr;
692	/** The HDA's register set. */
693	uint32_t au32Regs[HDA_NREGS];
694	/** Stream state for line-in. */
695	HDASTREAM StrmStLineIn;
696	/** Stream state for microphone-in. */
697	HDASTREAM StrmStMicIn;
698	/** Stream state for output. */
699	HDASTREAM StrmStOut;
700	/** CORB buffer base address. */
701	uint64_t u64CORBBase;
702	/** RIRB buffer base address. */
703	uint64_t u64RIRBBase;
704	/** DMA base address.
705	* Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
706	uint64_t u64DPBase;
707	/** DMA position buffer enable bit. */
708	bool fDMAPosition;
709	/** Padding for alignment. */
710	uint8_t u32Padding0[7];
711	/** Pointer to CORB buffer. */
712	R3PTRTYPE(uint32_t *) pu32CorbBuf;
713	/** Size in bytes of CORB buffer. */
714	uint32_t cbCorbBuf;
715	/** Padding for alignment. */
716	uint32_t u32Padding1;
717	/** Pointer to RIRB buffer. */
718	R3PTRTYPE(uint64_t *) pu64RirbBuf;
719	/** Size in bytes of RIRB buffer. */
720	uint32_t cbRirbBuf;
721	/** Indicates if HDA is in reset. */
722	bool fInReset;
723	/** Flag whether the R0 part is enabled. */
724	bool fR0Enabled;
725	/** Flag whether the RC part is enabled. */
726	bool fRCEnabled;
727	#ifndef VBOX_WITH_AUDIO_CALLBACKS
728	/** The timer for pumping data thru the attached LUN drivers. */
729	PTMTIMERR3 pTimer;
730	/** The timer interval for pumping data thru the LUN drivers in timer ticks. */
731	uint64_t cTimerTicks;
732	/** Timestamp of the last timer callback (hdaTimer).
733	* Used to calculate the time actually elapsed between two timer callbacks. */
734	uint64_t uTimerTS;
735	#endif
736	#ifdef VBOX_WITH_STATISTICS
737	# ifndef VBOX_WITH_AUDIO_CALLBACKS
738	STAMPROFILE StatTimer;
739	# endif
740	STAMCOUNTER StatBytesRead;
741	STAMCOUNTER StatBytesWritten;
742	#endif
743	/** Pointer to HDA codec to use. */
744	R3PTRTYPE(PHDACODEC) pCodec;
745	/** List of associated LUN drivers (HDADRIVER). */
746	RTLISTANCHORR3 lstDrv;
747	/** The device' software mixer. */
748	R3PTRTYPE(PAUDIOMIXER) pMixer;
749	/** Audio sink for PCM output. */
750	R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
751	/** Audio mixer sink for line input. */
752	R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
753	/** Audio mixer sink for microphone input. */
754	R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
755	uint64_t u64BaseTS;
756	/** Response Interrupt Count (RINTCNT). */
757	uint8_t u8RespIntCnt;
758	/** Padding for alignment. */
759	uint8_t au8Padding2[7];
760	} HDASTATE;
761	/** Pointer to the ICH Intel HD Audio Controller state. */
762	typedef HDASTATE *PHDASTATE;
763
764	#ifdef VBOX_WITH_AUDIO_CALLBACKS
765	typedef struct HDACALLBACKCTX
766	{
767	PHDASTATE pThis;
768	PHDADRIVER pDriver;
769	} HDACALLBACKCTX, *PHDACALLBACKCTX;
770	#endif
771
772	/*********************************************************************************************************************************
773	* Internal Functions *
774	*********************************************************************************************************************************/
775	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
776	static FNPDMDEVRESET hdaReset;
777
778	/*
779	* Stubs.
780	*/
781	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
782	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
783
784	/*
785	* Global register set read/write functions.
786	*/
787	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
788	static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
789	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
790	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
791	static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
792	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
793	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
794	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
795	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
796	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
797	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
798	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
799	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
800	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
801	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
802
803	/*
804	* {IOB}SDn read/write functions.
805	*/
806	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
807	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
808	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
809	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
810	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
811	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
812	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
813	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
814	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
815	inline bool hdaRegWriteSDIsAllowed(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
816
817	/*
818	* Generic register read/write functions.
819	*/
820	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
821	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
822	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
823	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
824	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
825	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
826	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
827	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
828
829	#ifdef IN_RING3
830	static void hdaStreamDestroy(PHDASTREAM pStrmSt);
831	static int hdaStreamStart(PHDASTREAM pStrmSt);
832	static int hdaStreamStop(PHDASTREAM pStrmSt);
833	static int hdaStreamWaitForStateChange(PHDASTREAM pStrmSt, RTMSINTERVAL msTimeout);
834	static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbToProcess, uint32_t *pcbProcessed);
835	#endif
836
837	#ifdef IN_RING3
838	static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
839	static void hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t u32LPIB);
840	# ifdef LOG_ENABLED
841	static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE);
842	# endif
843	#endif
844
845
846	/*********************************************************************************************************************************
847	* Global Variables *
848	*********************************************************************************************************************************/
849
850	/** Offset of the SD0 register map. */
851	#define HDA_REG_DESC_SD0_BASE 0x80
852
853	/** Turn a short global register name into an memory index and a stringized name. */
854	#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
855
856	/** Turns a short stream register name into an memory index and a stringized name. */
857	#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
858
859	/** Same as above for a register not stored in memory. */
860	#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
861
862	/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
863	#define HDA_REG_MAP_STRM(offset, name) \
864	/* offset size read mask write mask read callback write callback index + abbrev description */ \
865	/* ------- ------- ---------- ---------- -------------- ----------------- ------------------------------ ----------- */ \
866	/* Offset 0x80 (SD0) */ \
867	{ offset, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
868	/* Offset 0x83 (SD0) */ \
869	{ offset + 0x3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
870	/* Offset 0x84 (SD0) */ \
871	{ offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
872	/* Offset 0x88 (SD0) */ \
873	{ offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
874	/* Offset 0x8C (SD0) */ \
875	{ offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
876	/* Reserved: FIFO Watermark. ** @todo Document this! */ \
877	{ offset + 0xE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
878	/* Offset 0x90 (SD0) */ \
879	{ offset + 0x10, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16, hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
880	/* Offset 0x92 (SD0) */ \
881	{ offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Format" }, \
882	/* Reserved: 0x94 - 0x98. */ \
883	/* Offset 0x98 (SD0) */ \
884	{ offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
885	/* Offset 0x9C (SD0) */ \
886	{ offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
887
888	/** Defines a single audio stream register set (e.g. OSD0). */
889	#define HDA_REG_MAP_DEF_STREAM(index, name) \
890	HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
891
892	/* See 302349 p 6.2. */
893	static const struct HDAREGDESC
894	{
895	/** Register offset in the register space. */
896	uint32_t offset;
897	/** Size in bytes. Registers of size > 4 are in fact tables. */
898	uint32_t size;
899	/** Readable bits. */
900	uint32_t readable;
901	/** Writable bits. */
902	uint32_t writable;
903	/** Read callback. */
904	int (pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
905	/** Write callback. */
906	int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
907	/** Index into the register storage array. */
908	uint32_t mem_idx;
909	/** Abbreviated name. */
910	const char *abbrev;
911	/** Descripton. */
912	const char *desc;
913	} g_aHdaRegMap[HDA_NREGS] =
914
915	{
916	/* offset size read mask write mask read callback write callback index + abbrev */
917	/------- ------- ---------- ---------- ----------------------- ---------------------- ---------------- /
918	{ 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
919	{ 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
920	{ 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
921	{ 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
922	{ 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
923	{ 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
924	{ 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
925	{ 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , HDA_REG_IDX(STATESTS) }, /* State Change Status */
926	{ 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
927	{ 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
928	{ 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
929	{ 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
930	{ 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
931	{ 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
932	{ 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
933	{ 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
934	{ 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
935	{ 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
936	{ 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
937	{ 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
938	{ 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
939	{ 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
940	{ 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
941	{ 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
942	{ 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
943	{ 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
944	{ 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
945	{ 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
946	{ 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
947	{ 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
948	{ 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
949	{ 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
950	{ 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
951	{ 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
952	/* 4 Input Stream Descriptors (ISD). */
953	HDA_REG_MAP_DEF_STREAM(0, SD0),
954	HDA_REG_MAP_DEF_STREAM(1, SD1),
955	HDA_REG_MAP_DEF_STREAM(2, SD2),
956	HDA_REG_MAP_DEF_STREAM(3, SD3),
957	/* 4 Output Stream Descriptors (OSD). */
958	HDA_REG_MAP_DEF_STREAM(4, SD4),
959	HDA_REG_MAP_DEF_STREAM(5, SD5),
960	HDA_REG_MAP_DEF_STREAM(6, SD6),
961	HDA_REG_MAP_DEF_STREAM(7, SD7)
962	};
963
964	/**
965	* HDA register aliases (HDA spec 3.3.45).
966	* @remarks Sorted by offReg.
967	*/
968	static const struct
969	{
970	/** The alias register offset. */
971	uint32_t offReg;
972	/** The register index. */
973	int idxAlias;
974	} g_aHdaRegAliases[] =
975	{
976	{ 0x2084, HDA_REG_SD0LPIB },
977	{ 0x20a4, HDA_REG_SD1LPIB },
978	{ 0x20c4, HDA_REG_SD2LPIB },
979	{ 0x20e4, HDA_REG_SD3LPIB },
980	{ 0x2104, HDA_REG_SD4LPIB },
981	{ 0x2124, HDA_REG_SD5LPIB },
982	{ 0x2144, HDA_REG_SD6LPIB },
983	{ 0x2164, HDA_REG_SD7LPIB },
984	};
985
986	#ifdef IN_RING3
987	/** HDABDLE field descriptors for the v6+ saved state. */
988	static SSMFIELD const g_aSSMBDLEFields6[] =
989	{
990	SSMFIELD_ENTRY(HDABDLE, u64BufAdr),
991	SSMFIELD_ENTRY(HDABDLE, u32BufSize),
992	SSMFIELD_ENTRY(HDABDLE, fIntOnCompletion),
993	SSMFIELD_ENTRY_TERM()
994	};
995
996	/** HDABDLESTATE field descriptors for the v6+ saved state. */
997	static SSMFIELD const g_aSSMBDLEStateFields6[] =
998	{
999	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
1000	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
1001	SSMFIELD_ENTRY(HDABDLESTATE, au8FIFO),
1002	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
1003	SSMFIELD_ENTRY_TERM()
1004	};
1005
1006	/** HDASTREAMSTATE field descriptors for the v6+ saved state. */
1007	static SSMFIELD const g_aSSMStreamStateFields6[] =
1008	{
1009	SSMFIELD_ENTRY_OLD(cBDLE, 2),
1010	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
1011	SSMFIELD_ENTRY(HDASTREAMSTATE, fDoStop),
1012	SSMFIELD_ENTRY(HDASTREAMSTATE, fActive),
1013	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
1014	SSMFIELD_ENTRY_TERM()
1015	};
1016	#endif
1017
1018	/**
1019	* 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1020	*/
1021	static uint32_t const g_afMasks[5] =
1022	{
1023	UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1024	};
1025
1026	#ifdef IN_RING3
1027	DECLINLINE(void) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t u32LPIB)
1028	{
1029	AssertPtrReturnVoid(pThis);
1030	AssertPtrReturnVoid(pStrmSt);
1031
1032	Assert(u32LPIB <= pStrmSt->u32CBL);
1033
1034	LogFlowFunc(("uStrm=%RU8, LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1035	pStrmSt->u8Strm, u32LPIB, pThis->fDMAPosition));
1036
1037	/* Update LPIB in any case. */
1038	HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) = u32LPIB;
1039
1040	/* Do we need to tell the current DMA position? */
1041	if (pThis->fDMAPosition)
1042	{
1043	int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1044	(pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStrmSt->u8Strm * 2 * sizeof(uint32_t)),
1045	(void *)&u32LPIB, sizeof(uint32_t));
1046	AssertRC(rc2);
1047	#ifdef DEBUG
1048	hdaBDLEDumpAll(pThis, pStrmSt->u64BaseDMA, pStrmSt->State.uCurBDLE);
1049	#endif
1050	}
1051	}
1052	#endif
1053
1054	/**
1055	* Retrieves the number of bytes of a FIFOS register.
1056	*
1057	* @return Number of bytes of a given FIFOS register.
1058	*/
1059	DECLINLINE(uint16_t) hdaSDFIFOSToBytes(uint32_t u32RegFIFOS)
1060	{
1061	uint16_t cb;
1062	switch (u32RegFIFOS)
1063	{
1064	/* Input */
1065	case HDA_SDINFIFO_120B: cb = 120; break;
1066	case HDA_SDINFIFO_160B: cb = 160; break;
1067
1068	/* Output */
1069	case HDA_SDONFIFO_16B: cb = 16; break;
1070	case HDA_SDONFIFO_32B: cb = 32; break;
1071	case HDA_SDONFIFO_64B: cb = 64; break;
1072	case HDA_SDONFIFO_128B: cb = 128; break;
1073	case HDA_SDONFIFO_192B: cb = 192; break;
1074	case HDA_SDONFIFO_256B: cb = 256; break;
1075	default:
1076	{
1077	cb = 0; /* Can happen on stream reset. */
1078	break;
1079	}
1080	}
1081
1082	return cb;
1083	}
1084
1085	/**
1086	* Retrieves the number of bytes of a FIFOW register.
1087	*
1088	* @return Number of bytes of a given FIFOW register.
1089	*/
1090	DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1091	{
1092	uint32_t cb;
1093	switch (u32RegFIFOW)
1094	{
1095	case HDA_SDFIFOW_8B: cb = 8; break;
1096	case HDA_SDFIFOW_16B: cb = 16; break;
1097	case HDA_SDFIFOW_32B: cb = 32; break;
1098	default: cb = 0; break;
1099	}
1100
1101	#ifdef RT_STRICT
1102	Assert(RT_IS_POWER_OF_TWO(cb));
1103	#endif
1104	return cb;
1105	}
1106
1107	#ifdef IN_RING3
1108	/**
1109	* Fetches the next BDLE to use for a stream.
1110	*
1111	* @return IPRT status code.
1112	*/
1113	DECLINLINE(int) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
1114	{
1115	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1116	AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1117
1118	NOREF(pThis);
1119
1120	Assert(pStrmSt->State.uCurBDLE < pStrmSt->u16LVI + 1);
1121
1122	#ifdef DEBUG
1123	uint32_t uOldBDLE = pStrmSt->State.uCurBDLE;
1124	#endif
1125
1126	/*
1127	* Switch to the next BDLE entry and do a wrap around
1128	* if we reached the end of the Buffer Descriptor List (BDL).
1129	*/
1130	pStrmSt->State.uCurBDLE++;
1131	if (pStrmSt->State.uCurBDLE == pStrmSt->u16LVI + 1)
1132	{
1133	pStrmSt->State.uCurBDLE = 0;
1134
1135	hdaStreamUpdateLPIB(pThis, pStrmSt, 0);
1136	}
1137
1138	Assert(pStrmSt->State.uCurBDLE < pStrmSt->u16LVI + 1);
1139
1140	int rc = hdaBDLEFetch(pThis, &pStrmSt->State.BDLE, pStrmSt->u64BaseDMA, pStrmSt->State.uCurBDLE);
1141
1142	#ifdef DEBUG
1143	LogFlowFunc(("[SD%RU8]: uOldBDLE=%RU16, uCurBDLE=%RU16, LVI=%RU32, %R[bdle]\n",
1144	pStrmSt->u8Strm, uOldBDLE, pStrmSt->State.uCurBDLE, pStrmSt->u16LVI, &pStrmSt->State.BDLE));
1145	#endif
1146	return rc;
1147	}
1148	#endif
1149
1150	/**
1151	* Retrieves the minimum number of bytes accumulated/free in the
1152	* FIFO before the controller will start a fetch/eviction of data.
1153	*
1154	* Uses SDFIFOW (FIFO Watermark Register).
1155	*
1156	* @return Number of bytes accumulated/free in the FIFO.
1157	*/
1158	DECLINLINE(uint8_t) hdaStreamGetFIFOW(PHDASTATE pThis, PHDASTREAM pStrmSt)
1159	{
1160	AssertPtrReturn(pThis, 0);
1161	AssertPtrReturn(pStrmSt, 0);
1162
1163	#ifdef VBOX_HDA_WITH_FIFO
1164	return hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, pStrmSt->u8Strm));
1165	#else
1166	return 0;
1167	#endif
1168	}
1169
1170	static int hdaProcessInterrupt(PHDASTATE pThis)
1171	{
1172	#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1173	( INTCTL_SX((pThis), num) \
1174	&& (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1175
1176	bool fIrq = false;
1177
1178	if (/* Controller Interrupt Enable (CIE). */
1179	HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1180	&& ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1181	\|\| HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1182	\|\| (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1183	fIrq = true;
1184
1185	/** @todo Don't hardcode stream numbers here. */
1186	if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1187	\|\| IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1188	{
1189	#ifdef IN_RING3
1190	LogFunc(("BCIS\n"));
1191	#endif
1192	fIrq = true;
1193	}
1194
1195	if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1196	{
1197	LogFunc(("%s\n", fIrq ? "Asserted" : "Deasserted"));
1198	PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1199	}
1200
1201	#undef IS_INTERRUPT_OCCURED_AND_ENABLED
1202
1203	return VINF_SUCCESS;
1204	}
1205
1206	/**
1207	* Looks up a register at the exact offset given by @a offReg.
1208	*
1209	* @returns Register index on success, -1 if not found.
1210	* @param pThis The HDA device state.
1211	* @param offReg The register offset.
1212	*/
1213	static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1214	{
1215	/*
1216	* Aliases.
1217	*/
1218	if (offReg >= g_aHdaRegAliases[0].offReg)
1219	{
1220	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1221	if (offReg == g_aHdaRegAliases[i].offReg)
1222	return g_aHdaRegAliases[i].idxAlias;
1223	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1224	return -1;
1225	}
1226
1227	/*
1228	* Binary search the
1229	*/
1230	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1231	int idxLow = 0;
1232	for (;;)
1233	{
1234	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1235	if (offReg < g_aHdaRegMap[idxMiddle].offset)
1236	{
1237	if (idxLow == idxMiddle)
1238	break;
1239	idxEnd = idxMiddle;
1240	}
1241	else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1242	{
1243	idxLow = idxMiddle + 1;
1244	if (idxLow >= idxEnd)
1245	break;
1246	}
1247	else
1248	return idxMiddle;
1249	}
1250
1251	#ifdef RT_STRICT
1252	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1253	Assert(g_aHdaRegMap[i].offset != offReg);
1254	#endif
1255	return -1;
1256	}
1257
1258	/**
1259	* Looks up a register covering the offset given by @a offReg.
1260	*
1261	* @returns Register index on success, -1 if not found.
1262	* @param pThis The HDA device state.
1263	* @param offReg The register offset.
1264	*/
1265	static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1266	{
1267	/*
1268	* Aliases.
1269	*/
1270	if (offReg >= g_aHdaRegAliases[0].offReg)
1271	{
1272	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1273	{
1274	uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1275	if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1276	return g_aHdaRegAliases[i].idxAlias;
1277	}
1278	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1279	return -1;
1280	}
1281
1282	/*
1283	* Binary search the register map.
1284	*/
1285	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1286	int idxLow = 0;
1287	for (;;)
1288	{
1289	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1290	if (offReg < g_aHdaRegMap[idxMiddle].offset)
1291	{
1292	if (idxLow == idxMiddle)
1293	break;
1294	idxEnd = idxMiddle;
1295	}
1296	else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1297	{
1298	idxLow = idxMiddle + 1;
1299	if (idxLow >= idxEnd)
1300	break;
1301	}
1302	else
1303	return idxMiddle;
1304	}
1305
1306	#ifdef RT_STRICT
1307	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1308	Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1309	#endif
1310	return -1;
1311	}
1312
1313	#ifdef IN_RING3
1314	static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1315	{
1316	int rc = VINF_SUCCESS;
1317	if (fLocal)
1318	{
1319	Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1320	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1321	if (RT_FAILURE(rc))
1322	AssertRCReturn(rc, rc);
1323	#ifdef DEBUG_CMD_BUFFER
1324	uint8_t i = 0;
1325	do
1326	{
1327	LogFunc(("CORB%02x: ", i));
1328	uint8_t j = 0;
1329	do
1330	{
1331	const char *pszPrefix;
1332	if ((i + j) == HDA_REG(pThis, CORBRP));
1333	pszPrefix = "[R]";
1334	else if ((i + j) == HDA_REG(pThis, CORBWP));
1335	pszPrefix = "[W]";
1336	else
1337	pszPrefix = " "; /* three spaces */
1338	LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1339	j++;
1340	} while (j < 8);
1341	LogFunc(("\n"));
1342	i += 8;
1343	} while(i != 0);
1344	#endif
1345	}
1346	else
1347	{
1348	Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1349	rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1350	if (RT_FAILURE(rc))
1351	AssertRCReturn(rc, rc);
1352	#ifdef DEBUG_CMD_BUFFER
1353	uint8_t i = 0;
1354	do {
1355	LogFunc(("RIRB%02x: ", i));
1356	uint8_t j = 0;
1357	do {
1358	const char *prefix;
1359	if ((i + j) == HDA_REG(pThis, RIRBWP))
1360	prefix = "[W]";
1361	else
1362	prefix = " ";
1363	LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1364	} while (++j < 8);
1365	LogFunc(("\n"));
1366	i += 8;
1367	} while (i != 0);
1368	#endif
1369	}
1370	return rc;
1371	}
1372
1373	static int hdaCORBCmdProcess(PHDASTATE pThis)
1374	{
1375	PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1376
1377	int rc = hdaCmdSync(pThis, true);
1378	if (RT_FAILURE(rc))
1379	AssertRCReturn(rc, rc);
1380
1381	uint8_t corbRp = HDA_REG(pThis, CORBRP);
1382	uint8_t corbWp = HDA_REG(pThis, CORBWP);
1383	uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1384
1385	Assert((corbWp != corbRp));
1386	LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1387
1388	while (corbRp != corbWp)
1389	{
1390	uint32_t cmd;
1391	uint64_t resp;
1392	pfn = NULL;
1393	corbRp++;
1394	cmd = pThis->pu32CorbBuf[corbRp];
1395
1396	rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* Codec index */), &pfn);
1397	if (RT_SUCCESS(rc))
1398	{
1399	AssertPtr(pfn);
1400	rc = pfn(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1401	}
1402
1403	if (RT_FAILURE(rc))
1404	AssertRCReturn(rc, rc);
1405	(rirbWp)++;
1406
1407	LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1408	if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1409	&& !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1410	{
1411	LogFunc(("unexpected unsolicited response.\n"));
1412	HDA_REG(pThis, CORBRP) = corbRp;
1413	return rc;
1414	}
1415
1416	pThis->pu64RirbBuf[rirbWp] = resp;
1417
1418	pThis->u8RespIntCnt++;
1419	if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1420	break;
1421	}
1422	HDA_REG(pThis, CORBRP) = corbRp;
1423	HDA_REG(pThis, RIRBWP) = rirbWp;
1424	rc = hdaCmdSync(pThis, false);
1425	LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1426	HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1427	if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1428	{
1429	HDA_REG(pThis, RIRBSTS) \|= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1430
1431	pThis->u8RespIntCnt = 0;
1432	rc = hdaProcessInterrupt(pThis);
1433	}
1434	if (RT_FAILURE(rc))
1435	AssertRCReturn(rc, rc);
1436	return rc;
1437	}
1438
1439	static int hdaStreamCreate(PHDASTREAM pStrmSt)
1440	{
1441	AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1442
1443	int rc = RTSemEventCreate(&pStrmSt->State.hStateChangedEvent);
1444	AssertRC(rc);
1445
1446	pStrmSt->u8Strm = UINT8_MAX;
1447
1448	pStrmSt->State.fActive = false;
1449	pStrmSt->State.fInReset = false;
1450	pStrmSt->State.fDoStop = false;
1451
1452	LogFlowFuncLeaveRC(rc);
1453	return rc;
1454	}
1455
1456	static void hdaStreamDestroy(PHDASTREAM pStrmSt)
1457	{
1458	AssertPtrReturnVoid(pStrmSt);
1459
1460	LogFlowFunc(("[SD%RU8]: Destroy\n", pStrmSt->u8Strm));
1461
1462	int rc2 = hdaStreamStop(pStrmSt);
1463	AssertRC(rc2);
1464
1465	if (pStrmSt->State.hStateChangedEvent != NIL_RTSEMEVENT)
1466	{
1467	rc2 = RTSemEventDestroy(pStrmSt->State.hStateChangedEvent);
1468	AssertRC(rc2);
1469	}
1470
1471	LogFlowFuncLeave();
1472	}
1473
1474	static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1475	{
1476	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1477	AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1478
1479	pStrmSt->u8Strm = u8Strm;
1480	pStrmSt->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrmSt->u8Strm),
1481	HDA_STREAM_REG(pThis, BDPU, pStrmSt->u8Strm));
1482	pStrmSt->u16LVI = HDA_STREAM_REG(pThis, LVI, pStrmSt->u8Strm);
1483	pStrmSt->u32CBL = HDA_STREAM_REG(pThis, CBL, pStrmSt->u8Strm);
1484	pStrmSt->u16FIFOS = hdaSDFIFOSToBytes(HDA_STREAM_REG(pThis, FIFOS, pStrmSt->u8Strm));
1485
1486	RT_ZERO(pStrmSt->State.BDLE);
1487	pStrmSt->State.uCurBDLE = 0;
1488
1489	LogFlowFunc(("[SD%RU8]: DMA @ 0x%x (%RU32 bytes), LVI=%RU16, FIFOS=%RU16\n",
1490	pStrmSt->u8Strm, pStrmSt->u64BaseDMA, pStrmSt->u32CBL, pStrmSt->u16LVI, pStrmSt->u16FIFOS));
1491
1492	#ifdef DEBUG
1493	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
1494	HDA_STREAM_REG(pThis, BDPU, u8Strm));
1495	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, u8Strm);
1496	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1497
1498	LogFlowFunc(("\t-> DMA @ 0x%x, LVI=%RU16, CBL=%RU32\n", u64BaseDMA, u16LVI, u32CBL));
1499
1500	hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
1501	#endif
1502
1503	return VINF_SUCCESS;
1504	}
1505
1506	static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1507	{
1508	AssertPtrReturnVoid(pThis);
1509	AssertPtrReturnVoid(pStrmSt);
1510	AssertReturnVoid(u8Strm <= 7); /** @todo Use a define for MAX_STREAMS! */
1511
1512	#ifdef VBOX_STRICT
1513	AssertReleaseMsg(!RT_BOOL(HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
1514	("Cannot reset stream %RU8 while in running state\n", u8Strm));
1515	#endif
1516
1517	/*
1518	* Set reset state.
1519	*/
1520	Assert(ASMAtomicReadBool(&pStrmSt->State.fInReset) == false); /* No nested calls. */
1521	ASMAtomicXchgBool(&pStrmSt->State.fInReset, true);
1522
1523	/*
1524	* First, reset the internal stream state.
1525	*/
1526	RT_BZERO(pStrmSt, sizeof(HDASTREAM));
1527
1528	/*
1529	* Second, initialize the registers.
1530	*/
1531	HDA_STREAM_REG(pThis, STS, u8Strm) = 0;
1532	/* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1533	* bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1534	HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 \| (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1535	/* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39. */
1536	HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1537	/* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1538	HDA_STREAM_REG(pThis, FIFOW, u8Strm) = HDA_SDFIFOW_32B;
1539	HDA_STREAM_REG(pThis, LPIB, u8Strm) = 0;
1540	HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1541	HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1542	HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1543	HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1544	HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1545
1546	/*
1547	* Third, set the internal state according to the just set registers.
1548	*/
1549	pStrmSt->u8Strm = u8Strm;
1550	pStrmSt->u16FIFOS = HDA_STREAM_REG(pThis, FIFOS, u8Strm);
1551
1552
1553	/* Report that we're done resetting this stream. */
1554	HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
1555
1556	LogFunc(("[SD%RU8]: Reset\n", u8Strm));
1557
1558	/* Exit reset mode. */
1559	ASMAtomicXchgBool(&pStrmSt->State.fInReset, false);
1560	}
1561
1562	static int hdaStreamStart(PHDASTREAM pStrmSt)
1563	{
1564	AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1565
1566	ASMAtomicXchgBool(&pStrmSt->State.fDoStop, false);
1567	ASMAtomicXchgBool(&pStrmSt->State.fActive, true);
1568
1569	LogFlowFuncLeave();
1570	return VINF_SUCCESS;
1571	}
1572
1573	static int hdaStreamStop(PHDASTREAM pStrmSt)
1574	{
1575	AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1576
1577	/* Already in stopped state? */
1578	bool fActive = ASMAtomicReadBool(&pStrmSt->State.fActive);
1579	if (!fActive)
1580	return VINF_SUCCESS;
1581
1582	#if 0 /** @todo Does not work (yet), as EMT deadlocks then. */
1583	/*
1584	* Wait for the stream to stop.
1585	*/
1586	ASMAtomicXchgBool(&pStrmSt->State.fDoStop, true);
1587
1588	int rc = hdaStreamWaitForStateChange(pStrmSt, 60 * 1000 /* ms timeout */);
1589	fActive = ASMAtomicReadBool(&pStrmSt->State.fActive);
1590	if ( /* Waiting failed? */
1591	RT_FAILURE(rc)
1592	/* Stream is still active? */
1593	\|\| fActive)
1594	{
1595	AssertRC(rc);
1596	LogRel(("HDA: Warning: Unable to stop stream %RU8 (state: %s), rc=%Rrc\n",
1597	pStrmSt->u8Strm, fActive ? "active" : "stopped", rc));
1598	}
1599	#else
1600	int rc = VINF_SUCCESS;
1601	#endif
1602
1603	LogFlowFuncLeaveRC(rc);
1604	return rc;
1605	}
1606
1607	static int hdaStreamWaitForStateChange(PHDASTREAM pStrmSt, RTMSINTERVAL msTimeout)
1608	{
1609	AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1610
1611	LogFlowFunc(("[SD%RU8]: msTimeout=%RU32\n", pStrmSt->u8Strm, msTimeout));
1612	return RTSemEventWait(pStrmSt->State.hStateChangedEvent, msTimeout);
1613	}
1614	#endif /* IN_RING3 */
1615
1616	/* Register access handlers. */
1617
1618	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1619	{
1620	*pu32Value = 0;
1621	return VINF_SUCCESS;
1622	}
1623
1624	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1625	{
1626	return VINF_SUCCESS;
1627	}
1628
1629	/* U8 */
1630	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1631	{
1632	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1633	return hdaRegReadU32(pThis, iReg, pu32Value);
1634	}
1635
1636	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1637	{
1638	Assert((u32Value & 0xffffff00) == 0);
1639	return hdaRegWriteU32(pThis, iReg, u32Value);
1640	}
1641
1642	/* U16 */
1643	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1644	{
1645	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1646	return hdaRegReadU32(pThis, iReg, pu32Value);
1647	}
1648
1649	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1650	{
1651	Assert((u32Value & 0xffff0000) == 0);
1652	return hdaRegWriteU32(pThis, iReg, u32Value);
1653	}
1654
1655	/* U24 */
1656	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1657	{
1658	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1659	return hdaRegReadU32(pThis, iReg, pu32Value);
1660	}
1661
1662	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1663	{
1664	Assert((u32Value & 0xff000000) == 0);
1665	return hdaRegWriteU32(pThis, iReg, u32Value);
1666	}
1667
1668	/* U32 */
1669	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1670	{
1671	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1672
1673	*pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1674	return VINF_SUCCESS;
1675	}
1676
1677	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1678	{
1679	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1680
1681	pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1682	\| (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1683	return VINF_SUCCESS;
1684	}
1685
1686	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1687	{
1688	if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1689	{
1690	/* Set the CRST bit to indicate that we're leaving reset mode. */
1691	HDA_REG(pThis, GCTL) \|= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1692
1693	if (pThis->fInReset)
1694	{
1695	LogFunc(("Leaving reset\n"));
1696	pThis->fInReset = false;
1697	}
1698	}
1699	else
1700	{
1701	#ifdef IN_RING3
1702	/* Enter reset state. */
1703	if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1704	\|\| HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1705	{
1706	LogFunc(("Entering reset with DMA(RIRB:%s, CORB:%s)\n",
1707	HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1708	HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1709	}
1710
1711	/* Clear the CRST bit to indicate that we're in reset mode. */
1712	HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1713	pThis->fInReset = true;
1714
1715	/* As the CRST bit now is set, we now can proceed resetting stuff. */
1716	hdaReset(pThis->CTX_SUFF(pDevIns));
1717	#else
1718	return VINF_IOM_R3_MMIO_WRITE;
1719	#endif
1720	}
1721	if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1722	{
1723	/* Flush: GSTS:1 set, see 6.2.6. */
1724	HDA_REG(pThis, GSTS) \|= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
1725	/* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1726	}
1727	return VINF_SUCCESS;
1728	}
1729
1730	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1731	{
1732	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1733
1734	uint32_t v = pThis->au32Regs[iRegMem];
1735	uint32_t nv = u32Value & HDA_STATES_SCSF;
1736	pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1737	return VINF_SUCCESS;
1738	}
1739
1740	static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1741	{
1742	uint32_t v = 0;
1743	if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1744	\|\| HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1745	\|\| HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1746	\|\| HDA_REG(pThis, STATESTS))
1747	{
1748	v \|= RT_BIT(30); /* Touch CIS. */
1749	}
1750
1751	#define HDA_IS_STREAM_EVENT(pThis, num) \
1752	( (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1753	\|\| (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1754	\|\| (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1755
1756	#define HDA_MARK_STREAM(pThis, num, v) \
1757	do { (v) \|= HDA_IS_STREAM_EVENT((pThis), num) ? RT_BIT((num)) : 0; } while(0)
1758
1759	HDA_MARK_STREAM(pThis, 0, v);
1760	HDA_MARK_STREAM(pThis, 1, v);
1761	HDA_MARK_STREAM(pThis, 2, v);
1762	HDA_MARK_STREAM(pThis, 3, v);
1763	HDA_MARK_STREAM(pThis, 4, v);
1764	HDA_MARK_STREAM(pThis, 5, v);
1765	HDA_MARK_STREAM(pThis, 6, v);
1766	HDA_MARK_STREAM(pThis, 7, v);
1767
1768	#undef HDA_IS_STREAM_EVENT
1769	#undef HDA_MARK_STREAM
1770
1771	v \|= v ? RT_BIT(31) : 0;
1772
1773	*pu32Value = v;
1774	return VINF_SUCCESS;
1775	}
1776
1777	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1778	{
1779	const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1780	uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1781	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1782
1783	LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
1784
1785	*pu32Value = u32LPIB;
1786	return VINF_SUCCESS;
1787	}
1788
1789	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1790	{
1791	/* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1792	*pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1793	- pThis->u64BaseTS, 24, 1000);
1794	LogFlowFunc(("%RU32\n", *pu32Value));
1795	return VINF_SUCCESS;
1796	}
1797
1798	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1799	{
1800	if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1801	{
1802	HDA_REG(pThis, CORBRP) = 0;
1803	}
1804	#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1805	else
1806	return hdaRegWriteU8(pThis, iReg, u32Value);
1807	#endif
1808	return VINF_SUCCESS;
1809	}
1810
1811	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1812	{
1813	#ifdef IN_RING3
1814	int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1815	AssertRC(rc);
1816	if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1817	&& HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1818	{
1819	return hdaCORBCmdProcess(pThis);
1820	}
1821	return rc;
1822	#else
1823	return VINF_IOM_R3_MMIO_WRITE;
1824	#endif
1825	}
1826
1827	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1828	{
1829	uint32_t v = HDA_REG(pThis, CORBSTS);
1830	HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1831	return VINF_SUCCESS;
1832	}
1833
1834	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1835	{
1836	#ifdef IN_RING3
1837	int rc;
1838	rc = hdaRegWriteU16(pThis, iReg, u32Value);
1839	if (RT_FAILURE(rc))
1840	AssertRCReturn(rc, rc);
1841	if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1842	return VINF_SUCCESS;
1843	if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1844	return VINF_SUCCESS;
1845	rc = hdaCORBCmdProcess(pThis);
1846	return rc;
1847	#else
1848	return VINF_IOM_R3_MMIO_WRITE;
1849	#endif
1850	}
1851
1852	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1853	{
1854	const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CBL, iReg);
1855	uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1856
1857	LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32Value));
1858
1859	return hdaRegWriteU32(pThis, iReg, u32Value);
1860	}
1861
1862	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1863	{
1864	bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1865	bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1866	bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1867	bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1868
1869	uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1870
1871	PHDASTREAM pStrmSt;
1872	switch (u8Strm)
1873	{
1874	case 0: /** @todo Use dynamic indices, based on stream assignment. */
1875	{
1876	pStrmSt = &pThis->StrmStLineIn;
1877	break;
1878	}
1879	# ifdef VBOX_WITH_HDA_MIC_IN
1880	case 2: /** @todo Use dynamic indices, based on stream assignment. */
1881	{
1882	pStrmSt = &pThis->StrmStMicIn;
1883	break;
1884	}
1885	# endif
1886	case 4: /** @todo Use dynamic indices, based on stream assignment. */
1887	{
1888	pStrmSt = &pThis->StrmStOut;
1889	break;
1890	}
1891
1892	default:
1893	{
1894	LogFunc(("Warning: Changing SDCTL on non-attached stream (iReg=0x%x)\n", iReg));
1895	return hdaRegWriteU24(pThis, iReg, u32Value); /* Write 3 bytes. */
1896	}
1897	}
1898
1899	LogFunc(("[SD%RU8]: fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
1900	u8Strm, fRun, fInRun, fReset, fInReset, u32Value));
1901
1902	if (fInReset)
1903	{
1904	/* Guest is resetting HDA's stream, we're expecting guest will mark stream as exit. */
1905	Assert(!fReset);
1906	LogFunc(("Guest initiated exit of stream reset\n"));
1907	}
1908	else if (fReset)
1909	{
1910	#ifdef IN_RING3
1911	/* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1912	Assert(!fInRun && !fRun);
1913
1914	LogFunc(("Guest initiated enter to stream reset\n"));
1915	hdaStreamReset(pThis, pStrmSt, u8Strm);
1916	#else
1917	return VINF_IOM_R3_MMIO_WRITE;
1918	#endif
1919	}
1920	else
1921	{
1922	#ifdef IN_RING3
1923	/*
1924	* We enter here to change DMA states only.
1925	*/
1926	if (fInRun != fRun)
1927	{
1928	Assert(!fReset && !fInReset);
1929	LogFunc(("[SD%RU8]: fRun=%RTbool\n", u8Strm, fRun));
1930
1931	PHDADRIVER pDrv;
1932	switch (u8Strm)
1933	{
1934	case 0: /** @todo Use a variable here. Later. */
1935	{
1936	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1937	pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1938	pDrv->LineIn.pStrmIn, fRun);
1939	break;
1940	}
1941	# ifdef VBOX_WITH_HDA_MIC_IN
1942	case 2: /** @todo Use a variable here. Later. */
1943	{
1944	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1945	pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1946	pDrv->MicIn.pStrmIn, fRun);
1947	break;
1948	}
1949	# endif
1950	case 4: /** @todo Use a variable here. Later. */
1951	{
1952	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1953	pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1954	pDrv->Out.pStrmOut, fRun);
1955	break;
1956	}
1957	default:
1958	AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1959	break;
1960	}
1961	}
1962
1963	if (!fInRun && !fRun)
1964	hdaStreamInit(pThis, pStrmSt, u8Strm);
1965
1966	#else /* !IN_RING3 */
1967	return VINF_IOM_R3_MMIO_WRITE;
1968	#endif /* IN_RING3 */
1969	}
1970
1971	return hdaRegWriteU24(pThis, iReg, u32Value);
1972	}
1973
1974	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1975	{
1976	uint32_t v = HDA_REG_IND(pThis, iReg);
1977	v &= ~(u32Value & v);
1978	HDA_REG_IND(pThis, iReg) = v;
1979	hdaProcessInterrupt(pThis);
1980	return VINF_SUCCESS;
1981	}
1982
1983	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1984	{
1985	if (!hdaRegWriteSDIsAllowed(pThis, iReg, u32Value))
1986	return VINF_SUCCESS;
1987
1988	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1989	if (RT_FAILURE(rc))
1990	AssertRCReturn(rc, VINF_SUCCESS);
1991	return rc;
1992	}
1993
1994	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1995	{
1996	switch (u32Value)
1997	{
1998	case HDA_SDFIFOW_8B:
1999	case HDA_SDFIFOW_16B:
2000	case HDA_SDFIFOW_32B:
2001	return hdaRegWriteU16(pThis, iReg, u32Value);
2002	default:
2003	LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
2004	return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
2005	}
2006	return VINF_SUCCESS; /* Never reached. */
2007	}
2008
2009	/**
2010	* @note This method could be called for changing value on Output Streams
2011	* only (ICH6 datasheet 18.2.39).
2012	*/
2013	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2014	{
2015	/** @todo Only allow updating FIFOS if RUN bit is 0? */
2016	uint32_t u32FIFOS = 0;
2017
2018	switch (iReg)
2019	{
2020	/* SDInFIFOS is RO, n=0-3. */
2021	case HDA_REG_SD0FIFOS:
2022	case HDA_REG_SD1FIFOS:
2023	case HDA_REG_SD2FIFOS:
2024	case HDA_REG_SD3FIFOS:
2025	{
2026	LogFunc(("Guest tries to change R/O value of FIFO size of input stream, ignoring\n"));
2027	break;
2028	}
2029	case HDA_REG_SD4FIFOS:
2030	case HDA_REG_SD5FIFOS:
2031	case HDA_REG_SD6FIFOS:
2032	case HDA_REG_SD7FIFOS:
2033	{
2034	switch(u32Value)
2035	{
2036	case HDA_SDONFIFO_16B:
2037	case HDA_SDONFIFO_32B:
2038	case HDA_SDONFIFO_64B:
2039	case HDA_SDONFIFO_128B:
2040	case HDA_SDONFIFO_192B:
2041	u32FIFOS = u32Value;
2042	break;
2043
2044	case HDA_SDONFIFO_256B: /** @todo r=andy Investigate this. */
2045	LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
2046	/* Fall through is intentional. */
2047	default:
2048	u32FIFOS = HDA_SDONFIFO_192B;
2049	break;
2050	}
2051
2052	break;
2053	}
2054	default:
2055	{
2056	AssertMsgFailed(("Something weird happened with register lookup routine\n"));
2057	break;
2058	}
2059	}
2060
2061	if (u32FIFOS)
2062	{
2063	LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", 0, hdaSDFIFOSToBytes(u32FIFOS)));
2064	/** @todo Update internal stream state with new FIFOS. */
2065
2066	return hdaRegWriteU16(pThis, iReg, u32FIFOS);
2067	}
2068
2069	return VINF_SUCCESS;
2070	}
2071
2072	#ifdef IN_RING3
2073	static int hdaSDFMTToStrmCfg(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
2074	{
2075	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2076
2077	# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2078
2079	int rc = VINF_SUCCESS;
2080
2081	uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
2082	uint32_t u32HzMult = 1;
2083	uint32_t u32HzDiv = 1;
2084
2085	switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2086	{
2087	case 0: u32HzMult = 1; break;
2088	case 1: u32HzMult = 2; break;
2089	case 2: u32HzMult = 3; break;
2090	case 3: u32HzMult = 4; break;
2091	default:
2092	LogFunc(("Unsupported multiplier %x\n",
2093	EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2094	rc = VERR_NOT_SUPPORTED;
2095	break;
2096	}
2097	switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2098	{
2099	case 0: u32HzDiv = 1; break;
2100	case 1: u32HzDiv = 2; break;
2101	case 2: u32HzDiv = 3; break;
2102	case 3: u32HzDiv = 4; break;
2103	case 4: u32HzDiv = 5; break;
2104	case 5: u32HzDiv = 6; break;
2105	case 6: u32HzDiv = 7; break;
2106	case 7: u32HzDiv = 8; break;
2107	default:
2108	LogFunc(("Unsupported divisor %x\n",
2109	EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2110	rc = VERR_NOT_SUPPORTED;
2111	break;
2112	}
2113
2114	PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
2115	switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2116	{
2117	case 0:
2118	LogFunc(("Requested 8-bit\n"));
2119	enmFmt = AUD_FMT_S8;
2120	break;
2121	case 1:
2122	LogFunc(("Requested 16-bit\n"));
2123	enmFmt = AUD_FMT_S16;
2124	break;
2125	case 2:
2126	LogFunc(("Requested 20-bit\n"));
2127	break;
2128	case 3:
2129	LogFunc(("Requested 24-bit\n"));
2130	break;
2131	case 4:
2132	LogFunc(("Requested 32-bit\n"));
2133	enmFmt = AUD_FMT_S32;
2134	break;
2135	default:
2136	AssertMsgFailed(("Unsupported bits shift %x\n",
2137	EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2138	rc = VERR_NOT_SUPPORTED;
2139	break;
2140	}
2141
2142	if (RT_SUCCESS(rc))
2143	{
2144	pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2145	pCfg->cChannels = (u32SdFmt & 0xf) + 1;
2146	pCfg->enmFormat = enmFmt;
2147	pCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2148	}
2149
2150	# undef EXTRACT_VALUE
2151
2152	LogFlowFuncLeaveRC(rc);
2153	return rc;
2154	}
2155	#endif
2156
2157	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2158	{
2159	#ifdef IN_RING3
2160	# ifdef VBOX_WITH_HDA_CODEC_EMU
2161	/* No reason to re-open stream with same settings. */
2162	if (u32Value == HDA_REG_IND(pThis, iReg))
2163	return VINF_SUCCESS;
2164
2165	PDMAUDIOSTREAMCFG strmCfg;
2166	int rc = hdaSDFMTToStrmCfg(u32Value, &strmCfg);
2167	if (RT_FAILURE(rc))
2168	return rc;
2169
2170	PHDADRIVER pDrv;
2171	switch (iReg)
2172	{
2173	case HDA_REG_SD0FMT:
2174	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2175	rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &strmCfg);
2176	break;
2177	# ifdef VBOX_WITH_HDA_MIC_IN
2178	case HDA_REG_SD2FMT:
2179	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2180	rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &strmCfg);
2181	break;
2182	# endif
2183	default:
2184	LogFunc(("Warning: Attempt to change format on register %RU32\n", iReg));
2185	break;
2186	}
2187
2188	/** @todo r=andy rc gets lost; needs fixing. */
2189	return hdaRegWriteU16(pThis, iReg, u32Value);
2190	# else /* !VBOX_WITH_HDA_CODEC_EMU */
2191	return hdaRegWriteU16(pThis, iReg, u32Value);
2192	# endif
2193	#else /* !IN_RING3 */
2194	return VINF_IOM_R3_MMIO_WRITE;
2195	#endif
2196	}
2197
2198	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2199	{
2200	if (!hdaRegWriteSDIsAllowed(pThis, iReg, u32Value))
2201	return VINF_SUCCESS;
2202
2203	LogFlowFunc(("[SD%RU8]: DMA BDPL -> 0x%x\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2204
2205	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2206	if (RT_FAILURE(rc))
2207	AssertRCReturn(rc, VINF_SUCCESS);
2208	return rc;
2209	}
2210
2211	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2212	{
2213	if (!hdaRegWriteSDIsAllowed(pThis, iReg, u32Value))
2214	return VINF_SUCCESS;
2215
2216	LogFlowFunc(("[SD%RU8]: DMA BDPU -> 0x%x\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2217
2218	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2219	if (RT_FAILURE(rc))
2220	AssertRCReturn(rc, VINF_SUCCESS);
2221	return rc;
2222	}
2223
2224	/**
2225	* Checks whether a write to a specific SDnXXX register is allowed or not.
2226	*
2227	* @return bool Returns @true if write is allowed, @false if not.
2228	* @param pThis Pointer to HDA state.
2229	* @param iReg Register to write.
2230	* @param u32Value Value to write.
2231	*/
2232	inline bool hdaRegWriteSDIsAllowed(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2233	{
2234	/* Check if the SD's RUN bit is set. */
2235	bool fIsRunning = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2236	if (fIsRunning)
2237	{
2238	#ifdef VBOX_STRICT
2239	AssertMsgFailed(("[SD%RU8]: Cannot write to register 0x%x (0x%x) when RUN bit is set\n",
2240	HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), iReg, u32Value));
2241	#endif
2242	return false;
2243	}
2244
2245	return true;
2246	}
2247
2248	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2249	{
2250	int rc = VINF_SUCCESS;
2251	/* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2252	if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2253	\|\| HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2254	HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2255
2256	rc = hdaRegReadU32(pThis, iReg, pu32Value);
2257	return rc;
2258	}
2259
2260	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2261	{
2262	int rc = VINF_SUCCESS;
2263
2264	/*
2265	* If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2266	* write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2267	*/
2268	if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
2269	&& !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
2270	{
2271	#ifdef IN_RING3
2272	PFNHDACODECVERBPROCESSOR pfn = NULL;
2273	uint64_t resp;
2274	uint32_t cmd = HDA_REG(pThis, IC);
2275	if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2276	{
2277	/*
2278	* 3.4.3 defines behavior of immediate Command status register.
2279	*/
2280	LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
2281	return rc;
2282	}
2283	HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2284	LogFunc(("IC:%x\n", cmd));
2285
2286	rc = pThis->pCodec->pfnLookup(pThis->pCodec,
2287	HDA_CODEC_CMD(cmd, 0 /* LUN */),
2288	&pfn);
2289	if (RT_FAILURE(rc))
2290	AssertRCReturn(rc, rc);
2291	rc = pfn(pThis->pCodec,
2292	HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
2293	if (RT_FAILURE(rc))
2294	AssertRCReturn(rc, rc);
2295
2296	HDA_REG(pThis, IR) = (uint32_t)resp;
2297	LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
2298	HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
2299	HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
2300	#else /* !IN_RING3 */
2301	rc = VINF_IOM_R3_MMIO_WRITE;
2302	#endif
2303	return rc;
2304	}
2305	/*
2306	* Once the guest read the response, it should clean the IRV bit of the IRS register.
2307	*/
2308	if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
2309	&& HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
2310	HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
2311	return rc;
2312	}
2313
2314	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2315	{
2316	if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
2317	{
2318	HDA_REG(pThis, RIRBWP) = 0;
2319	}
2320	/* The remaining bits are O, see 6.2.22 */
2321	return VINF_SUCCESS;
2322	}
2323
2324	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2325	{
2326	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2327	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2328	if (RT_FAILURE(rc))
2329	AssertRCReturn(rc, rc);
2330
2331	switch(iReg)
2332	{
2333	case HDA_REG_CORBLBASE:
2334	pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2335	pThis->u64CORBBase \|= pThis->au32Regs[iRegMem];
2336	break;
2337	case HDA_REG_CORBUBASE:
2338	pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2339	pThis->u64CORBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2340	break;
2341	case HDA_REG_RIRBLBASE:
2342	pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2343	pThis->u64RIRBBase \|= pThis->au32Regs[iRegMem];
2344	break;
2345	case HDA_REG_RIRBUBASE:
2346	pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2347	pThis->u64RIRBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2348	break;
2349	case HDA_REG_DPLBASE:
2350	{
2351	pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
2352	pThis->u64DPBase \|= pThis->au32Regs[iRegMem];
2353
2354	/* Also make sure to handle the DMA position enable bit. */
2355	pThis->fDMAPosition = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2356	LogRel(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
2357	break;
2358	}
2359	case HDA_REG_DPUBASE:
2360	pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
2361	pThis->u64DPBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2362	break;
2363	default:
2364	AssertMsgFailed(("Invalid index\n"));
2365	break;
2366	}
2367
2368	LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2369	pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2370	return rc;
2371	}
2372
2373	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2374	{
2375	uint8_t v = HDA_REG(pThis, RIRBSTS);
2376	HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2377
2378	return hdaProcessInterrupt(pThis);
2379	}
2380
2381	#ifdef IN_RING3
2382	#ifdef LOG_ENABLED
2383	static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE)
2384	{
2385	LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BaseDMA, cBDLE));
2386	if (!u64BaseDMA)
2387	return;
2388
2389	uint32_t cbBDLE = 0;
2390	for (uint16_t i = 0; i < cBDLE; i++)
2391	{
2392	uint8_t bdle[16]; /** @todo Use a define. */
2393	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * 16, bdle, 16); /** @todo Use a define. */
2394
2395	uint64_t addr = (uint64_t )bdle;
2396	uint32_t len = (uint32_t )&bdle[8];
2397	uint32_t ioc = (uint32_t )&bdle[12];
2398
2399	LogFlowFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
2400	i, addr, len, RT_BOOL(ioc & 0x1)));
2401
2402	cbBDLE += len;
2403	}
2404
2405	LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
2406
2407	if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
2408	return;
2409
2410	LogFlowFunc(("DMA counters:\n", cbBDLE));
2411
2412	for (int i = 0; i < 8; i++) /** @todo Use a define for MAX_STREAMS! */
2413	{
2414	uint32_t uDMACnt;
2415	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
2416	&uDMACnt, sizeof(&uDMACnt));
2417
2418	LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
2419	}
2420	}
2421	#endif
2422
2423	/**
2424	* Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
2425	*
2426	* @param pThis Pointer to HDA state.
2427	* @param pBDLE Where to store the fetched result.
2428	* @param u64BaseDMA Address base of DMA engine to use.
2429	* @param u16Entry BDLE entry to fetch.
2430	*/
2431	static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
2432	{
2433	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2434	AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
2435	AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
2436	/** @todo Compare u16Entry with LVI. */
2437
2438	uint8_t uBundleEntry[16]; /** @todo Define a BDLE length. */
2439	int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * 16, /** @todo Define a BDLE length. */
2440	uBundleEntry, RT_ELEMENTS(uBundleEntry));
2441	if (RT_FAILURE(rc))
2442	return rc;
2443
2444	RT_BZERO(pBDLE, sizeof(HDABDLE));
2445
2446	pBDLE->State.u32BDLIndex = u16Entry;
2447	pBDLE->u64BufAdr = (uint64_t ) uBundleEntry;
2448	pBDLE->u32BufSize = (uint32_t )&uBundleEntry[8];
2449	if (pBDLE->u32BufSize < sizeof(uint16_t)) /* Must be at least one word. */
2450	return VERR_INVALID_STATE;
2451
2452	pBDLE->fIntOnCompletion = ((uint32_t )&uBundleEntry[12]) & 0x1;
2453
2454	return VINF_SUCCESS;
2455	}
2456
2457	/**
2458	* Returns the number of outstanding stream data bytes which need to be processed
2459	* by the DMA engine assigned to this stream.
2460	*
2461	* @return Number of bytes for the DMA engine to process.
2462	*/
2463	DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbMax)
2464	{
2465	AssertPtrReturn(pThis, 0);
2466	AssertPtrReturn(pStrmSt, 0);
2467
2468	if (!cbMax)
2469	return 0;
2470
2471	PHDABDLE pBDLE = &pStrmSt->State.BDLE;
2472
2473	uint32_t cbFree = pStrmSt->u32CBL - HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2474	if (cbFree)
2475	{
2476	/* Limit to the available free space of the current BDLE. */
2477	cbFree = RT_MIN(cbFree, pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2478
2479	/* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
2480	cbFree = RT_MIN(cbFree, pStrmSt->u16FIFOS);
2481
2482	/* Make sure we only transfer as many bytes as requested. */
2483	cbFree = RT_MIN(cbFree, cbMax);
2484
2485	if (pBDLE->State.cbBelowFIFOW)
2486	{
2487	/* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
2488	* No need to read data from DMA then. */
2489	if (cbFree > pBDLE->State.cbBelowFIFOW)
2490	{
2491	/* Subtract the amount of bytes that still would fit in the stream's FIFO
2492	* and therefore do not need to be processed by DMA. */
2493	cbFree -= pBDLE->State.cbBelowFIFOW;
2494	}
2495	}
2496	}
2497
2498	LogFlowFunc(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, cbFree=%RU32, %R[bdle]\n", pStrmSt->u8Strm,
2499	pStrmSt->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), cbFree, pBDLE));
2500	return cbFree;
2501	}
2502
2503	DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
2504	{
2505	AssertPtrReturnVoid(pBDLE);
2506
2507	if (!cbData \|\| !cbProcessed)
2508	return;
2509
2510	/* Fewer than cbBelowFIFOW bytes were copied.
2511	* Probably we need to move the buffer, but it is rather hard to imagine a situation
2512	* where it might happen. */
2513	AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
2514	("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
2515	cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
2516
2517	#if 0
2518	if ( pBDLE->State.cbBelowFIFOW
2519	&& pBDLE->State.cbBelowFIFOW <= cbWritten)
2520	{
2521	LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
2522	pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->u32BufSize));
2523	}
2524	#endif
2525
2526	pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
2527	Assert(pBDLE->State.cbBelowFIFOW == 0);
2528
2529	/* We always increment the position of DMA buffer counter because we're always reading
2530	* into an intermediate buffer. */
2531	pBDLE->State.u32BufOff += cbData;
2532	Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2533
2534	LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
2535	}
2536
2537	DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
2538	{
2539	AssertPtrReturn(pThis, false);
2540	AssertPtrReturn(pStrmSt, false);
2541
2542	PHDABDLE pBDLE = &pStrmSt->State.BDLE;
2543	uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2544
2545	/* Did we reach the CBL (Cyclic Buffer List) limit? */
2546	bool fCBLLimitReached = u32LPIB >= pStrmSt->u32CBL;
2547
2548	/* Do we need to use the next BDLE entry? Either because we reached
2549	* the CBL limit or our internal DMA buffer is full. */
2550	bool fNeedsNextBDLE = ( fCBLLimitReached
2551	\|\| (pBDLE->State.u32BufOff >= pBDLE->u32BufSize));
2552
2553	Assert(u32LPIB <= pStrmSt->u32CBL);
2554	Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2555
2556	LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
2557	pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
2558
2559	if (fCBLLimitReached)
2560	{
2561	/* Reset LPIB register. */
2562	u32LPIB -= RT_MIN(u32LPIB, pStrmSt->u32CBL);
2563	hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2564	}
2565
2566	return fNeedsNextBDLE;
2567	}
2568
2569	DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbInc)
2570	{
2571	AssertPtrReturnVoid(pThis);
2572	AssertPtrReturnVoid(pStrmSt);
2573
2574	LogFlowFunc(("[SD%RU8]: cbInc=%RU32\n", pStrmSt->u8Strm, cbInc));
2575
2576	Assert(cbInc <= pStrmSt->u16FIFOS);
2577
2578	PHDABDLE pBDLE = &pStrmSt->State.BDLE;
2579
2580	/*
2581	* If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
2582	* doesn't fetch anything via DMA, so just update LPIB.
2583	* (ICH6 datasheet 18.2.38).
2584	*/
2585	if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
2586	{
2587	const uint32_t u32LPIB = RT_MIN(HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2588	pStrmSt->u32CBL);
2589
2590	LogFlowFunc(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
2591	pStrmSt->u8Strm,
2592	HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2593	pStrmSt->u32CBL));
2594
2595	hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2596	}
2597	}
2598
2599	static bool hdaStreamTransferIsComplete(PHDASTATE pThis, PHDASTREAM pStrmSt)
2600	{
2601	AssertPtrReturn(pThis, true);
2602	AssertPtrReturn(pStrmSt, true);
2603
2604	bool fIsComplete = false;
2605
2606	PHDABDLE pBDLE = &pStrmSt->State.BDLE;
2607	const uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2608
2609	if ( pBDLE->State.u32BufOff >= pBDLE->u32BufSize
2610	\|\| u32LPIB >= pStrmSt->u32CBL)
2611	{
2612	Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2613	Assert(u32LPIB <= pStrmSt->u32CBL);
2614
2615	if (/* IOC (Interrupt On Completion) bit set? */
2616	pBDLE->fIntOnCompletion
2617	/* All data put into the DMA FIFO? */
2618	&& pBDLE->State.cbBelowFIFOW == 0
2619	)
2620	{
2621	/**
2622	* Set the BCIS (Buffer Completion Interrupt Status) flag as the
2623	* last byte of data for the current descriptor has been fetched
2624	* from memory and put into the DMA FIFO.
2625	*
2626	** @todo More carefully investigate BCIS flag.
2627	*
2628	* Speech synthesis works fine on Mac Guest if this bit isn't set
2629	* but in general sound quality gets worse.
2630	*/
2631	HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) \|= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2632
2633	/*
2634	* If the ICE (IOCE, "Interrupt On Completion Enable") bit of the SDCTL register is set
2635	* we need to generate an interrupt.
2636	*/
2637	if (HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2638	hdaProcessInterrupt(pThis);
2639	}
2640
2641	fIsComplete = true;
2642	}
2643
2644	LogFlowFunc(("[SD%RU8]: u32LPIB=%RU32, CBL=%RU32, %R[bdle] => %s\n",
2645	pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, pBDLE, fIsComplete ? "COMPLETE" : "INCOMPLETE"));
2646
2647	return fIsComplete;
2648	}
2649
2650	/**
2651	* hdaReadAudio - copies samples from audio backend to DMA.
2652	* Note: This function writes to the DMA buffer immediately,
2653	* but "reports bytes" when all conditions are met (FIFOW).
2654	*/
2655	static int hdaReadAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, PAUDMIXSINK pSink, uint32_t cbMax, uint32_t *pcbRead)
2656	{
2657	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2658	AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2659	AssertPtrReturn(pSink, VERR_INVALID_POINTER);
2660	/* pcbRead is optional. */
2661
2662	PHDABDLE pBDLE = &pStrmSt->State.BDLE;
2663
2664	int rc;
2665	uint32_t cbRead = 0;
2666	uint32_t cbBuf = hdaStreamGetTransferSize(pThis, pStrmSt, cbMax);
2667
2668	LogFlowFunc(("cbBuf=%RU32, %R[bdle]\n", cbBuf, pBDLE));
2669
2670	if (!cbBuf)
2671	{
2672	/* Nothing to write, bail out. */
2673	rc = VINF_EOF;
2674	}
2675	else
2676	{
2677	rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pBDLE->State.au8FIFO, cbBuf, &cbRead);
2678	if (RT_SUCCESS(rc))
2679	{
2680	Assert(cbRead);
2681	Assert(cbRead == cbBuf);
2682	Assert(cbRead <= pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2683
2684	/*
2685	* Write to the BDLE's DMA buffer.
2686	*/
2687	rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2688	pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2689	pBDLE->State.au8FIFO, cbRead);
2690	AssertRC(rc);
2691
2692	if (pBDLE->State.cbBelowFIFOW + cbRead > hdaStreamGetFIFOW(pThis, pStrmSt))
2693	{
2694	pBDLE->State.u32BufOff += cbRead;
2695	pBDLE->State.cbBelowFIFOW = 0;
2696	//hdaBackendReadTransferReported(pBDLE, cbDMAData, cbRead, &cbRead, pcbAvail);
2697	}
2698	else
2699	{
2700	pBDLE->State.u32BufOff += cbRead;
2701	pBDLE->State.cbBelowFIFOW += cbRead;
2702	Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2703	//hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbRead, pcbAvail);
2704
2705	rc = VERR_NO_DATA;
2706	}
2707	}
2708	}
2709
2710	Assert(cbRead <= pStrmSt->u16FIFOS);
2711
2712	if (RT_SUCCESS(rc))
2713	{
2714	if (pcbRead)
2715	*pcbRead = cbRead;
2716	}
2717
2718	LogFunc(("Returning cbRead=%RU32, rc=%Rrc\n", cbRead, rc));
2719	return rc;
2720	}
2721
2722	static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbMax, uint32_t *pcbWritten)
2723	{
2724	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2725	AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2726	AssertPtrReturn(pcbWritten, VERR_INVALID_POINTER);
2727	/* pcbWritten is optional. */
2728
2729	PHDABDLE pBDLE = &pStrmSt->State.BDLE;
2730
2731	uint32_t cbWritten = 0;
2732	uint32_t cbData = hdaStreamGetTransferSize(pThis, pStrmSt, cbMax);
2733
2734	LogFlowFunc(("cbData=%RU32, %R[bdle]\n", cbData, pBDLE));
2735
2736	/*
2737	* Copy from DMA to the corresponding stream buffer (if there are any bytes from the
2738	* previous unreported transfer we write at offset 'pBDLE->State.cbUnderFifoW').
2739	*/
2740	int rc;
2741	if (!cbData)
2742	{
2743	rc = VINF_EOF;
2744	}
2745	else
2746	{
2747	/*
2748	* Read from the current BDLE's DMA buffer.
2749	*/
2750	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2751	pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2752	pBDLE->State.au8FIFO + pBDLE->State.cbBelowFIFOW, cbData);
2753	AssertRC(rc);
2754
2755	#ifdef VBOX_WITH_STATISTICS
2756	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbData);
2757	#endif
2758	/*
2759	* Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2760	*/
2761	uint32_t cbToWrite = cbData + pBDLE->State.cbBelowFIFOW;
2762	if (cbToWrite >= hdaStreamGetFIFOW(pThis, pStrmSt))
2763	{
2764	uint32_t cbWrittenToStream;
2765	int rc2;
2766
2767	PHDADRIVER pDrv;
2768	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2769	{
2770	if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2771	{
2772	rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2773	pBDLE->State.au8FIFO, cbToWrite, &cbWrittenToStream);
2774	if (RT_SUCCESS(rc2))
2775	{
2776	if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2777	LogFlowFunc(("\tLUN#%RU8: Warning: Only written %RU32 / %RU32 bytes, expect lags\n",
2778	pDrv->uLUN, cbWrittenToStream, cbToWrite));
2779	}
2780	}
2781	else /* Stream disabled, not fatal. */
2782	{
2783	cbWrittenToStream = 0;
2784	rc2 = VERR_NOT_AVAILABLE;
2785	/* Keep going. */
2786	}
2787
2788	LogFlowFunc(("\tLUN#%RU8: cbToWrite=%RU32, cbWrittenToStream=%RU32, rc=%Rrc\n",
2789	pDrv->uLUN, cbToWrite, cbWrittenToStream, rc2));
2790	}
2791
2792	/* Always report all data as being written;
2793	* backends who were not able to catch up have to deal with it themselves. */
2794	cbWritten = cbToWrite;
2795
2796	hdaBDLEUpdate(pBDLE, cbData, cbWritten);
2797	}
2798	else
2799	{
2800	pBDLE->State.u32BufOff += cbWritten;
2801	pBDLE->State.cbBelowFIFOW += cbWritten;
2802	Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2803
2804	/* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2805	//hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbAvail, NULL);
2806	rc = VINF_EOF;
2807	}
2808	}
2809
2810	Assert(cbWritten <= pStrmSt->u16FIFOS);
2811
2812	if (RT_SUCCESS(rc))
2813	{
2814	if (pcbWritten)
2815	*pcbWritten = cbWritten;
2816	}
2817
2818	LogFunc(("Returning cbWritten=%RU32, rc=%Rrc\n", cbWritten, rc));
2819	return rc;
2820	}
2821
2822	/**
2823	* @interface_method_impl{HDACODEC,pfnReset}
2824	*/
2825	static DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2826	{
2827	PHDASTATE pThis = pCodec->pHDAState;
2828	NOREF(pThis);
2829	return VINF_SUCCESS;
2830	}
2831
2832
2833	static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2834	{
2835	NOREF(pThis);
2836	NOREF(enmRecSource);
2837	LogFlowFuncEnter();
2838	}
2839
2840	static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2841	{
2842	NOREF(pThis);
2843	LogFlowFuncEnter();
2844	}
2845
2846	static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2847	const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2848	PPDMAUDIOSTREAMCFG pCfg)
2849	{
2850	PAUDMIXSINK pSink;
2851
2852	switch (enmRecSource)
2853	{
2854	# ifdef VBOX_WITH_HDA_MIC_IN
2855	case PDMAUDIORECSOURCE_MIC:
2856	pSink = pThis->pSinkMicIn;
2857	break;
2858	# endif
2859	case PDMAUDIORECSOURCE_LINE_IN:
2860	pSink = pThis->pSinkLineIn;
2861	break;
2862	default:
2863	AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2864	return VERR_NOT_SUPPORTED;
2865	}
2866
2867	int rc = VINF_SUCCESS;
2868	char *pszDesc;
2869
2870	PHDADRIVER pDrv;
2871	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2872	{
2873	if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2874	{
2875	rc = VERR_NO_MEMORY;
2876	break;
2877	}
2878
2879	rc = pDrv->pConnector->pfnCreateIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2880	LogFlowFunc(("LUN#%RU8: Created input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2881	if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2882	{
2883	AudioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2884	rc = AudioMixerAddStreamIn(pSink,
2885	pDrv->pConnector, pDrv->LineIn.pStrmIn,
2886	0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2887	}
2888
2889	RTStrFree(pszDesc);
2890	}
2891
2892	LogFlowFuncLeaveRC(rc);
2893	return rc;
2894	}
2895
2896	static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2897	const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2898	{
2899	int rc = VINF_SUCCESS;
2900	char *pszDesc;
2901
2902	PHDADRIVER pDrv;
2903	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2904	{
2905	if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s (%RU32Hz, %RU8 %s)",
2906	pDrv->uLUN, pszName, pCfg->uHz, pCfg->cChannels, pCfg->cChannels > 1 ? "Channels" : "Channel") <= 0)
2907	{
2908	rc = VERR_NO_MEMORY;
2909	break;
2910	}
2911
2912	rc = pDrv->pConnector->pfnCreateOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
2913	LogFlowFunc(("LUN#%RU8: Created output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2914	if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2915	{
2916	AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
2917	rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
2918	pDrv->pConnector, pDrv->Out.pStrmOut,
2919	0 /* uFlags */, &pDrv->Out.phStrmOut);
2920	}
2921
2922	RTStrFree(pszDesc);
2923	}
2924
2925	LogFlowFuncLeaveRC(rc);
2926	return rc;
2927	}
2928
2929	static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis, ENMSOUNDSOURCE enmSource,
2930	bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2931	{
2932	int rc = VINF_SUCCESS;
2933	PDMAUDIOVOLUME vol = { fMute, uVolLeft, uVolRight };
2934	PAUDMIXSINK pSink;
2935
2936	/* Convert the audio source to corresponding sink. */
2937	switch (enmSource)
2938	{
2939	case PO_INDEX:
2940	pSink = pThis->pSinkOutput;
2941	break;
2942	case PI_INDEX:
2943	pSink = pThis->pSinkLineIn;
2944	break;
2945	case MC_INDEX:
2946	pSink = pThis->pSinkMicIn;
2947	break;
2948	default:
2949	AssertFailedReturn(VERR_INVALID_PARAMETER);
2950	break;
2951	}
2952
2953	/* Set the volume. Codec already converted it to the correct range. */
2954	AudioMixerSetSinkVolume(pSink, &vol);
2955
2956	LogFlowFuncLeaveRC(rc);
2957	return rc;
2958	}
2959
2960	#ifndef VBOX_WITH_AUDIO_CALLBACKS
2961
2962	static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2963	{
2964	PHDASTATE pThis = (PHDASTATE)pvUser;
2965	Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
2966	AssertPtr(pThis);
2967
2968	STAM_PROFILE_START(&pThis->StatTimer, a);
2969
2970	uint32_t cbInMax = 0;
2971	uint32_t cbOutMin = UINT32_MAX;
2972
2973	PHDADRIVER pDrv;
2974
2975	uint64_t cTicksNow = TMTimerGet(pTimer);
2976	uint64_t cTicksElapsed = cTicksNow - pThis->uTimerTS;
2977	uint64_t cTicksPerSec = TMTimerGetFreq(pTimer);
2978
2979	pThis->uTimerTS = cTicksNow;
2980
2981	/*
2982	* Calculate the codec's (fixed) sampling rate.
2983	*/
2984	AssertPtr(pThis->pCodec);
2985	PDMPCMPROPS codecStrmProps;
2986
2987	int rc = DrvAudioStreamCfgToProps(&pThis->pCodec->strmCfg, &codecStrmProps);
2988	AssertRC(rc);
2989
2990	uint32_t cCodecSamplesMin = (int)((2 * cTicksElapsed * pThis->pCodec->strmCfg.uHz + cTicksPerSec) / cTicksPerSec / 2);
2991	uint32_t cbCodecSamplesMin = cCodecSamplesMin << codecStrmProps.cShift;
2992
2993	/*
2994	* Process all driver nodes.
2995	*/
2996	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2997	{
2998	uint32_t cbIn = 0;
2999	uint32_t cbOut = 0;
3000
3001	rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector, &cbIn, &cbOut, NULL /* pcSamplesLive */);
3002	if (RT_SUCCESS(rc))
3003	rc = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, NULL /* pcSamplesPlayed */);
3004
3005	#ifdef DEBUG_TIMER
3006	LogFlowFunc(("LUN#%RU8: rc=%Rrc, cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, rc, cbIn, cbOut));
3007	#endif
3008	/* If we there was an error handling (available) output or there simply is no output available,
3009	* then calculate the minimum data rate which must be processed by the device emulation in order
3010	* to function correctly.
3011	*
3012	* This is not the optimal solution, but as we have to deal with this on a timer-based approach
3013	* (until we have the audio callbacks) we need to have device' DMA engines running. */
3014	if (!pDrv->pConnector->pfnIsValidOut(pDrv->pConnector, pDrv->Out.pStrmOut))
3015	{
3016	/* Use the codec's (fixed) sampling rate. */
3017	cbOut = RT_MAX(cbOut, cbCodecSamplesMin);
3018	continue;
3019	}
3020
3021	const bool fIsActiveOut = pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut);
3022	if ( RT_FAILURE(rc)
3023	\|\| !fIsActiveOut)
3024	{
3025	uint32_t cSamplesMin = (int)((2 * cTicksElapsed * pDrv->Out.pStrmOut->Props.uHz + cTicksPerSec) / cTicksPerSec / 2);
3026	uint32_t cbSamplesMin = AUDIOMIXBUF_S2B(&pDrv->Out.pStrmOut->MixBuf, cSamplesMin);
3027
3028	#ifdef DEBUG_TIMER
3029	LogFlowFunc(("\trc=%Rrc, cSamplesMin=%RU32, cbSamplesMin=%RU32\n", rc, cSamplesMin, cbSamplesMin));
3030	#endif
3031	cbOut = RT_MAX(cbOut, cbSamplesMin);
3032	}
3033
3034	cbOutMin = RT_MIN(cbOutMin, cbOut);
3035	cbInMax = RT_MAX(cbInMax, cbIn);
3036	}
3037
3038	#ifdef DEBUG_TIMER
3039	LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
3040	#endif
3041
3042	if (cbOutMin == UINT32_MAX)
3043	cbOutMin = 0;
3044
3045	/* Do the actual device transfers. */
3046	hdaTransfer(pThis, PO_INDEX, cbOutMin /* cbToProcess /, NULL / pcbProcessed */);
3047	hdaTransfer(pThis, PI_INDEX, cbInMax /* cbToProcess /, NULL / pcbProcessed */);
3048
3049	/* Kick the timer again. */
3050	uint64_t cTicks = pThis->cTimerTicks;
3051	/** @todo adjust cTicks down by now much cbOutMin represents. */
3052	TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
3053
3054	STAM_PROFILE_STOP(&pThis->StatTimer, a);
3055	}
3056
3057	#else /* VBOX_WITH_AUDIO_CALLBACKS */
3058
3059	static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCALLBACKTYPE enmType, void pvCtx, size_t cbCtx, void pvUser, size_t cbUser)
3060	{
3061	Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
3062	AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
3063	AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
3064	AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
3065	AssertReturn(cbUser, VERR_INVALID_PARAMETER);
3066
3067	PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
3068	AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
3069
3070	PPDMAUDIOCALLBACKDATAIN pData = (PPDMAUDIOCALLBACKDATAIN)pvUser;
3071	AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAIN), VERR_INVALID_PARAMETER);
3072
3073	return hdaTransfer(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
3074	}
3075
3076	static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCALLBACKTYPE enmType, void pvCtx, size_t cbCtx, void pvUser, size_t cbUser)
3077	{
3078	Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
3079	AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
3080	AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
3081	AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
3082	AssertReturn(cbUser, VERR_INVALID_PARAMETER);
3083
3084	PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
3085	AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
3086
3087	PPDMAUDIOCALLBACKDATAOUT pData = (PPDMAUDIOCALLBACKDATAOUT)pvUser;
3088	AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAOUT), VERR_INVALID_PARAMETER);
3089
3090	PHDASTATE pThis = pCtx->pThis;
3091
3092	int rc = hdaTransfer(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
3093	if ( RT_SUCCESS(rc)
3094	&& pData->cbOutWritten)
3095	{
3096	PHDADRIVER pDrv;
3097	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3098	{
3099	uint32_t cSamplesPlayed;
3100	int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
3101	LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
3102	}
3103	}
3104	}
3105	#endif /* VBOX_WITH_AUDIO_CALLBACKS */
3106
3107	static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbToProcess, uint32_t *pcbProcessed)
3108	{
3109	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3110	/* pcbProcessed is optional. */
3111
3112	if (ASMAtomicReadBool(&pThis->fInReset)) /* HDA controller in reset mode? Bail out. */
3113	{
3114	LogFlowFunc(("In reset mode, skipping\n"));
3115
3116	if (pcbProcessed)
3117	*pcbProcessed = 0;
3118	return VINF_SUCCESS;
3119	}
3120
3121	PHDASTREAM pStrmSt;
3122	switch (enmSrc)
3123	{
3124	case PI_INDEX:
3125	{
3126	pStrmSt = &pThis->StrmStLineIn;
3127	break;
3128	}
3129
3130	#ifdef VBOX_WITH_HDA_MIC_IN
3131	case MC_INDEX:
3132	{
3133	pStrmSt = &pThis->StrmStMicIn;
3134	break;
3135	}
3136	#endif
3137	case PO_INDEX:
3138	{
3139	pStrmSt = &pThis->StrmStOut;
3140	break;
3141	}
3142
3143	default:
3144	{
3145	AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
3146	return VERR_NOT_SUPPORTED;
3147	}
3148	}
3149
3150	int rc = VINF_SUCCESS;
3151	bool fProceed = true;
3152
3153	/* Stop request received? */
3154	if (ASMAtomicReadBool(&pStrmSt->State.fDoStop))
3155	{
3156	pStrmSt->State.fActive = false;
3157
3158	rc = RTSemEventSignal(pStrmSt->State.hStateChangedEvent);
3159	AssertRC(rc);
3160
3161	fProceed = false;
3162	}
3163	/* Is the stream not in a running state currently? */
3164	else if (!(HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)))
3165	fProceed = false;
3166	/* Nothing to process? */
3167	else if (!cbToProcess)
3168	fProceed = false;
3169
3170	if (!fProceed)
3171	{
3172	if (pcbProcessed)
3173	*pcbProcessed = 0;
3174	return VINF_SUCCESS;
3175	}
3176
3177	LogFlowFunc(("enmSrc=%RU32, cbToProcess=%RU32\n", enmSrc, cbToProcess));
3178
3179	/* Sanity checks. */
3180	Assert(pStrmSt->u8Strm <= 7); /** @todo Use a define for MAX_STREAMS! */
3181	Assert(pStrmSt->u64BaseDMA);
3182	Assert(pStrmSt->u32CBL);
3183
3184	/* State sanity checks. */
3185	Assert(ASMAtomicReadBool(&pStrmSt->State.fInReset) == false);
3186
3187	uint32_t cbProcessedTotal = 0;
3188	bool fIsComplete = false;
3189
3190	while (cbToProcess)
3191	{
3192	/* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
3193	if (hdaStreamNeedsNextBDLE(pThis, pStrmSt))
3194	hdaStreamGetNextBDLE(pThis, pStrmSt);
3195
3196	/* Set the FIFORDY bit on the stream while doing the transfer. */
3197	HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) \|= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3198
3199	uint32_t cbProcessed;
3200	switch (enmSrc)
3201	{
3202	case PI_INDEX:
3203	rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkLineIn, cbToProcess, &cbProcessed);
3204	break;
3205	case PO_INDEX:
3206	rc = hdaWriteAudio(pThis, pStrmSt, cbToProcess, &cbProcessed);
3207	break;
3208	#ifdef VBOX_WITH_HDA_MIC_IN
3209	case MC_INDEX:
3210	rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkMicIn, cbToProcess, &cbProcessed);
3211	break;
3212	#endif
3213	default:
3214	AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
3215	rc = VERR_NOT_SUPPORTED;
3216	break;
3217	}
3218
3219	/* Remove the FIFORDY bit again. */
3220	HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3221
3222	if (RT_FAILURE(rc))
3223	break;
3224
3225	hdaStreamTransferUpdate(pThis, pStrmSt, cbProcessed);
3226
3227	cbToProcess -= RT_MIN(cbToProcess, cbProcessed);
3228	cbProcessedTotal += cbProcessed;
3229
3230	LogFlowFunc(("cbProcessed=%RU32, cbToProcess=%RU32, cbProcessedTotal=%RU32, rc=%Rrc\n",
3231	cbProcessed, cbToProcess, cbProcessedTotal, rc));
3232
3233	if (rc == VINF_EOF)
3234	fIsComplete = true;
3235
3236	if (!fIsComplete)
3237	fIsComplete = hdaStreamTransferIsComplete(pThis, pStrmSt);
3238
3239	if (fIsComplete)
3240	break;
3241	}
3242
3243	if (RT_SUCCESS(rc))
3244	{
3245	if (pcbProcessed)
3246	*pcbProcessed = cbProcessedTotal;
3247	}
3248
3249	LogFlowFuncLeaveRC(rc);
3250	return rc;
3251	}
3252	#endif /* IN_RING3 */
3253
3254	/* MMIO callbacks */
3255
3256	/**
3257	* @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3258	*
3259	* @note During implementation, we discovered so-called "forgotten" or "hole"
3260	* registers whose description is not listed in the RPM, datasheet, or
3261	* spec.
3262	*/
3263	PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3264	{
3265	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3266	int rc;
3267
3268	/*
3269	* Look up and log.
3270	*/
3271	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3272	int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
3273	#ifdef LOG_ENABLED
3274	unsigned const cbLog = cb;
3275	uint32_t offRegLog = offReg;
3276	#endif
3277
3278	LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
3279	Assert(cb == 4); Assert((offReg & 3) == 0);
3280
3281	if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3282	LogFunc(("\tAccess to registers except GCTL is blocked while reset\n"));
3283
3284	if (idxRegDsc == -1)
3285	LogRel(("HDA: Invalid read access @0x%x (bytes=%d)\n", offReg, cb));
3286
3287	if (idxRegDsc != -1)
3288	{
3289	/* ASSUMES gapless DWORD at end of map. */
3290	if (g_aHdaRegMap[idxRegDsc].size == 4)
3291	{
3292	/*
3293	* Straight forward DWORD access.
3294	*/
3295	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3296	LogFunc(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, (uint32_t )pv, rc));
3297	}
3298	else
3299	{
3300	/*
3301	* Multi register read (unless there are trailing gaps).
3302	* ASSUMES that only DWORD reads have sideeffects.
3303	*/
3304	uint32_t u32Value = 0;
3305	unsigned cbLeft = 4;
3306	do
3307	{
3308	uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3309	uint32_t u32Tmp = 0;
3310
3311	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3312	LogFunc(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3313	if (rc != VINF_SUCCESS)
3314	break;
3315	u32Value \|= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3316
3317	cbLeft -= cbReg;
3318	offReg += cbReg;
3319	idxRegDsc++;
3320	} while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3321
3322	if (rc == VINF_SUCCESS)
3323	(uint32_t )pv = u32Value;
3324	else
3325	Assert(!IOM_SUCCESS(rc));
3326	}
3327	}
3328	else
3329	{
3330	rc = VINF_IOM_MMIO_UNUSED_FF;
3331	LogFunc(("\tHole at %x is accessed for read\n", offReg));
3332	}
3333
3334	/*
3335	* Log the outcome.
3336	*/
3337	#ifdef LOG_ENABLED
3338	if (cbLog == 4)
3339	LogFunc(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, (uint32_t )pv, rc));
3340	else if (cbLog == 2)
3341	LogFunc(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, (uint16_t )pv, rc));
3342	else if (cbLog == 1)
3343	LogFunc(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, (uint8_t )pv, rc));
3344	#endif
3345	return rc;
3346	}
3347
3348
3349	DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3350	{
3351	if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3352	{
3353	LogRel2(("HDA: Access to register 0x%x is blocked while reset\n", idxRegDsc));
3354	return VINF_SUCCESS;
3355	}
3356
3357	uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3358	#ifdef LOG_ENABLED
3359	uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
3360	#endif
3361	int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3362	LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3363	g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
3364	return rc;
3365	}
3366
3367
3368	/**
3369	* @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3370	*/
3371	PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
3372	{
3373	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3374	int rc;
3375
3376	/*
3377	* The behavior of accesses that aren't aligned on natural boundraries is
3378	* undefined. Just reject them outright.
3379	*/
3380	/** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3381	Assert(cb == 1 \|\| cb == 2 \|\| cb == 4 \|\| cb == 8);
3382	if (GCPhysAddr & (cb - 1))
3383	return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3384
3385	/*
3386	* Look up and log the access.
3387	*/
3388	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3389	int idxRegDsc = hdaRegLookup(pThis, offReg);
3390	uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3391	uint64_t u64Value;
3392	if (cb == 4) u64Value = (uint32_t const )pv;
3393	else if (cb == 2) u64Value = (uint16_t const )pv;
3394	else if (cb == 1) u64Value = (uint8_t const )pv;
3395	else if (cb == 8) u64Value = (uint64_t const )pv;
3396	else
3397	{
3398	u64Value = 0; /* shut up gcc. */
3399	AssertReleaseMsgFailed(("%u\n", cb));
3400	}
3401
3402	#ifdef LOG_ENABLED
3403	uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3404	if (idxRegDsc == -1)
3405	LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, (uint32_t const )pv, cb));
3406	else if (cb == 4)
3407	LogFunc(("@%#05x u32=%#010x %s\n", offReg, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3408	else if (cb == 2)
3409	LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, (uint16_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3410	else if (cb == 1)
3411	LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, (uint8_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3412
3413	if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3414	LogFunc(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3415	#endif
3416
3417	/*
3418	* Try for a direct hit first.
3419	*/
3420	if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3421	{
3422	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3423	#ifdef LOG_ENABLED
3424	LogFunc(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3425	#endif
3426	}
3427	/*
3428	* Partial or multiple register access, loop thru the requested memory.
3429	*/
3430	else
3431	{
3432	/*
3433	* If it's an access beyond the start of the register, shift the input
3434	* value and fill in missing bits. Natural alignment rules means we
3435	* will only see 1 or 2 byte accesses of this kind, so no risk of
3436	* shifting out input values.
3437	*/
3438	if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
3439	{
3440	uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3441	offReg -= cbBefore;
3442	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3443	u64Value <<= cbBefore * 8;
3444	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3445	LogFunc(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3446	cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3447	}
3448
3449	/* Loop thru the write area, it may cover multiple registers. */
3450	rc = VINF_SUCCESS;
3451	for (;;)
3452	{
3453	uint32_t cbReg;
3454	if (idxRegDsc != -1)
3455	{
3456	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3457	cbReg = g_aHdaRegMap[idxRegDsc].size;
3458	if (cb < cbReg)
3459	{
3460	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3461	LogFunc(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3462	g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3463	}
3464	uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
3465	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3466	LogFunc(("\t%#x -> %#x\n", u32LogOldVal, pThis->au32Regs[idxRegMem]));
3467	}
3468	else
3469	{
3470	LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3471	cbReg = 1;
3472	}
3473	if (rc != VINF_SUCCESS)
3474	break;
3475	if (cbReg >= cb)
3476	break;
3477
3478	/* Advance. */
3479	offReg += cbReg;
3480	cb -= cbReg;
3481	u64Value >>= cbReg * 8;
3482	if (idxRegDsc == -1)
3483	idxRegDsc = hdaRegLookup(pThis, offReg);
3484	else
3485	{
3486	idxRegDsc++;
3487	if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3488	\|\| g_aHdaRegMap[idxRegDsc].offset != offReg)
3489	{
3490	idxRegDsc = -1;
3491	}
3492	}
3493	}
3494	}
3495
3496	return rc;
3497	}
3498
3499
3500	/* PCI callback. */
3501
3502	#ifdef IN_RING3
3503	/**
3504	* @callback_method_impl{FNPCIIOREGIONMAP}
3505	*/
3506	static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
3507	PCIADDRESSSPACE enmType)
3508	{
3509	PPDMDEVINS pDevIns = pPciDev->pDevIns;
3510	PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3511	RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3512	int rc;
3513
3514	/*
3515	* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3516	*
3517	* Let IOM talk DWORDs when reading, saves a lot of complications. On
3518	* writing though, we have to do it all ourselves because of sideeffects.
3519	*/
3520	Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3521	rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
3522	IOMMMIO_FLAGS_READ_DWORD
3523	\| IOMMMIO_FLAGS_WRITE_PASSTHRU,
3524	hdaMMIOWrite, hdaMMIORead, "HDA");
3525
3526	if (RT_FAILURE(rc))
3527	return rc;
3528
3529	if (pThis->fR0Enabled)
3530	{
3531	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
3532	"hdaMMIOWrite", "hdaMMIORead");
3533	if (RT_FAILURE(rc))
3534	return rc;
3535	}
3536
3537	if (pThis->fRCEnabled)
3538	{
3539	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
3540	"hdaMMIOWrite", "hdaMMIORead");
3541	if (RT_FAILURE(rc))
3542	return rc;
3543	}
3544
3545	pThis->MMIOBaseAddr = GCPhysAddress;
3546	return VINF_SUCCESS;
3547	}
3548
3549
3550	/* Saved state callbacks. */
3551
3552	static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
3553	{
3554	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3555
3556	LogFlowFunc(("[SD%RU8]\n", pStrm->u8Strm));
3557
3558	/* Save stream ID. */
3559	int rc = SSMR3PutU8(pSSM, pStrm->u8Strm);
3560	AssertRCReturn(rc, rc);
3561	Assert(pStrm->u8Strm <= 7); /** @todo Use a define. */
3562
3563	rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /fFlags/, g_aSSMStreamStateFields6, NULL);
3564	AssertRCReturn(rc, rc);
3565
3566	#ifdef DEBUG /* Sanity checks. */
3567	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrm->u8Strm),
3568	HDA_STREAM_REG(pThis, BDPU, pStrm->u8Strm));
3569	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStrm->u8Strm);
3570	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStrm->u8Strm);
3571
3572	hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
3573
3574	Assert(u64BaseDMA == pStrm->u64BaseDMA);
3575	Assert(u16LVI == pStrm->u16LVI);
3576	Assert(u32CBL == pStrm->u32CBL);
3577	#endif
3578
3579	rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
3580	0 /fFlags/, g_aSSMBDLEFields6, NULL);
3581	AssertRCReturn(rc, rc);
3582
3583	rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
3584	0 /fFlags/, g_aSSMBDLEStateFields6, NULL);
3585	AssertRCReturn(rc, rc);
3586
3587	#ifdef DEBUG /* Sanity checks. */
3588	PHDABDLE pBDLE = &pStrm->State.BDLE;
3589	if (u64BaseDMA)
3590	{
3591	Assert(pStrm->State.uCurBDLE <= u16LVI + 1);
3592
3593	HDABDLE curBDLE;
3594	rc = hdaBDLEFetch(pThis, &curBDLE, u64BaseDMA, pStrm->State.uCurBDLE);
3595	AssertRC(rc);
3596
3597	Assert(curBDLE.u32BufSize == pBDLE->u32BufSize);
3598	Assert(curBDLE.u64BufAdr == pBDLE->u64BufAdr);
3599	Assert(curBDLE.fIntOnCompletion == pBDLE->fIntOnCompletion);
3600	}
3601	else
3602	{
3603	Assert(pBDLE->u64BufAdr == 0);
3604	Assert(pBDLE->u32BufSize == 0);
3605	}
3606	#endif
3607	return rc;
3608	}
3609
3610	/**
3611	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3612	*/
3613	static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3614	{
3615	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3616
3617	/* Save Codec nodes states. */
3618	hdaCodecSaveState(pThis->pCodec, pSSM);
3619
3620	/* Save MMIO registers. */
3621	AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3622	SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3623	SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3624
3625	/* Save number of streams. */
3626	#ifdef VBOX_WITH_HDA_MIC_IN
3627	SSMR3PutU32(pSSM, 3);
3628	#else
3629	SSMR3PutU32(pSSM, 2);
3630	#endif
3631
3632	/* Save stream states. */
3633	int rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStOut);
3634	AssertRCReturn(rc, rc);
3635	#ifdef VBOX_WITH_HDA_MIC_IN
3636	rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStMicIn);
3637	AssertRCReturn(rc, rc);
3638	#endif
3639	rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStLineIn);
3640	AssertRCReturn(rc, rc);
3641
3642	return rc;
3643	}
3644
3645
3646	/**
3647	* @callback_method_impl{FNSSMDEVLOADEXEC}
3648	*/
3649	static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3650	{
3651	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3652
3653	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3654
3655	LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3656
3657	/*
3658	* Load Codec nodes states.
3659	*/
3660	int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3661	if (RT_FAILURE(rc))
3662	{
3663	LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
3664	return rc;
3665	}
3666
3667	/*
3668	* Load MMIO registers.
3669	*/
3670	uint32_t cRegs;
3671	switch (uVersion)
3672	{
3673	case HDA_SSM_VERSION_1:
3674	/* Starting with r71199, we would save 112 instead of 113
3675	registers due to some code cleanups. This only affected trunk
3676	builds in the 4.1 development period. */
3677	cRegs = 113;
3678	if (SSMR3HandleRevision(pSSM) >= 71199)
3679	{
3680	uint32_t uVer = SSMR3HandleVersion(pSSM);
3681	if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3682	&& VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3683	&& VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3684	cRegs = 112;
3685	}
3686	break;
3687
3688	case HDA_SSM_VERSION_2:
3689	case HDA_SSM_VERSION_3:
3690	cRegs = 112;
3691	AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3692	break;
3693
3694	/* Since version 4 we store the register count to stay flexible. */
3695	case HDA_SSM_VERSION_4:
3696	case HDA_SSM_VERSION_5:
3697	case HDA_SSM_VERSION:
3698	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3699	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3700	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3701	break;
3702
3703	default:
3704	LogRel(("HDA: Unsupported / too new saved state version (%RU32)\n", uVersion));
3705	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3706	}
3707
3708	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3709	{
3710	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3711	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3712	}
3713	else
3714	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3715
3716	/*
3717	* Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3718	* every BDLE state, whereas it only needs to be stored
3719	* once for every stream. Most of the BDLE state we can
3720	* get out of the registers anyway, so just ignore those values.
3721	*
3722	* Also, only the current BDLE was saved, regardless whether
3723	* there were more than one (and there are at least two entries,
3724	* according to the spec).
3725	*/
3726	#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3727	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3728	AssertRCReturn(rc, rc); \
3729	rc = SSMR3GetU64(pSSM, &x.u64BufAdr); /* u64BdleCviAddr */ \
3730	AssertRCReturn(rc, rc); \
3731	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3732	AssertRCReturn(rc, rc); \
3733	rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
3734	AssertRCReturn(rc, rc); \
3735	rc = SSMR3GetU32(pSSM, &x.u32BufSize); /* u32BdleCviLen */ \
3736	AssertRCReturn(rc, rc); \
3737	rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
3738	AssertRCReturn(rc, rc); \
3739	rc = SSMR3GetBool(pSSM, &x.fIntOnCompletion); /* fBdleCviIoc */ \
3740	AssertRCReturn(rc, rc); \
3741	rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
3742	AssertRCReturn(rc, rc); \
3743	rc = SSMR3GetMem(pSSM, &x.State.au8FIFO, sizeof(x.State.au8FIFO)); \
3744	AssertRCReturn(rc, rc); \
3745	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3746	AssertRCReturn(rc, rc); \
3747
3748	/*
3749	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3750	*/
3751	switch (uVersion)
3752	{
3753	case HDA_SSM_VERSION_1:
3754	case HDA_SSM_VERSION_2:
3755	case HDA_SSM_VERSION_3:
3756	case HDA_SSM_VERSION_4:
3757	{
3758	/* Only load the internal states.
3759	* The rest will be initialized from the saved registers later. */
3760
3761	/* Note 1: Only the current BDLE for a stream was saved! */
3762	/* Note 2: The stream's saving order is/was fixed, so don't touch! */
3763
3764	/* Output */
3765	rc = hdaStreamInit(pThis, &pThis->StrmStOut, 4 /* Stream number, hardcoded */);
3766	if (RT_FAILURE(rc))
3767	break;
3768	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pThis->StrmStOut.State.BDLE);
3769	pThis->StrmStOut.State.uCurBDLE = pThis->StrmStOut.State.BDLE.State.u32BDLIndex;
3770
3771	/* Microphone-In */
3772	rc = hdaStreamInit(pThis, &pThis->StrmStMicIn, 2 /* Stream number, hardcoded */);
3773	if (RT_FAILURE(rc))
3774	break;
3775	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pThis->StrmStMicIn.State.BDLE);
3776	pThis->StrmStMicIn.State.uCurBDLE = pThis->StrmStMicIn.State.BDLE.State.u32BDLIndex;
3777
3778	/* Line-In */
3779	rc = hdaStreamInit(pThis, &pThis->StrmStLineIn, 0 /* Stream number, hardcoded */);
3780	if (RT_FAILURE(rc))
3781	break;
3782	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pThis->StrmStLineIn.State.BDLE);
3783	pThis->StrmStLineIn.State.uCurBDLE = pThis->StrmStLineIn.State.BDLE.State.u32BDLIndex;
3784	break;
3785	}
3786
3787	/* Since v5 we support flexible stream and BDLE counts. */
3788	case HDA_SSM_VERSION_5:
3789	case HDA_SSM_VERSION:
3790	{
3791	uint32_t cStreams;
3792	rc = SSMR3GetU32(pSSM, &cStreams);
3793	if (RT_FAILURE(rc))
3794	break;
3795
3796	LogRel2(("hdaLoadExec: cStreams=%RU32\n", cStreams));
3797
3798	/* Load stream states. */
3799	for (uint32_t i = 0; i < cStreams; i++)
3800	{
3801	uint8_t uStreamID;
3802	rc = SSMR3GetU8(pSSM, &uStreamID);
3803	if (RT_FAILURE(rc))
3804	break;
3805
3806	PHDASTREAM pStrm;
3807	HDASTREAM StreamDummy;
3808
3809	switch (uStreamID)
3810	{
3811	case 0: /** @todo Implement dynamic stream IDs. */
3812	pStrm = &pThis->StrmStLineIn;
3813	break;
3814	#ifdef VBOX_WITH_HDA_MIC_IN
3815	case 2: /** @todo Implement dynamic stream IDs. */
3816	pStrm = &pThis->StrmStMicIn;
3817	break;
3818	#endif
3819	case 4: /** @todo Implement dynamic stream IDs. */
3820	pStrm = &pThis->StrmStOut;
3821	break;
3822
3823	default:
3824	pStrm = &StreamDummy;
3825
3826	LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uStreamID));
3827	break;
3828	}
3829
3830	RT_BZERO(pStrm, sizeof(HDASTREAM));
3831
3832	rc = hdaStreamInit(pThis, pStrm, uStreamID);
3833	if (RT_FAILURE(rc))
3834	{
3835	LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uStreamID, rc));
3836	break;
3837	}
3838
3839	if (uVersion == HDA_SSM_VERSION_5)
3840	{
3841	/* Get the current BDLE entry and skip the rest. */
3842	uint16_t cBDLE;
3843
3844	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3845	AssertRC(rc);
3846	rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
3847	AssertRC(rc);
3848	rc = SSMR3GetU16(pSSM, &pStrm->State.uCurBDLE); /* uCurBDLE */
3849	AssertRC(rc);
3850	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3851	AssertRC(rc);
3852
3853	uint32_t u32BDLEIndex;
3854	for (uint16_t a = 0; a < cBDLE; a++)
3855	{
3856	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3857	AssertRC(rc);
3858	rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
3859	AssertRC(rc);
3860
3861	/* Does the current BDLE index match the current BDLE to process? */
3862	if (u32BDLEIndex == pStrm->State.uCurBDLE)
3863	{
3864	rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
3865	AssertRC(rc);
3866	rc = SSMR3GetMem(pSSM,
3867	&pStrm->State.BDLE.State.au8FIFO,
3868	sizeof(pStrm->State.BDLE.State.au8FIFO)); /* au8FIFO */
3869	AssertRC(rc);
3870	rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.u32BufOff); /* u32BufOff */
3871	AssertRC(rc);
3872	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3873	AssertRC(rc);
3874	}
3875	else /* Skip not current BDLEs. */
3876	{
3877	rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
3878	+ sizeof(uint8_t) * 256 /* au8FIFO */
3879	+ sizeof(uint32_t) /* u32BufOff */
3880	+ sizeof(uint32_t)); /* End marker */
3881	AssertRC(rc);
3882	}
3883	}
3884	}
3885	else
3886	{
3887	rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE),
3888	0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
3889	if (RT_FAILURE(rc))
3890	break;
3891
3892	rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
3893	0 /* fFlags */, g_aSSMBDLEFields6, NULL);
3894	if (RT_FAILURE(rc))
3895	break;
3896
3897	rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
3898	0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
3899	if (RT_FAILURE(rc))
3900	break;
3901	}
3902	}
3903	break;
3904	}
3905
3906	default:
3907	AssertReleaseFailed(); /* Never reached. */
3908	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3909	}
3910
3911	#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3912
3913	if (RT_SUCCESS(rc))
3914	{
3915	/*
3916	* Update stuff after the state changes.
3917	*/
3918	bool fEnableIn = RT_BOOL(HDA_SDCTL(pThis, 0 /** @todo Use a define. */) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3919	#ifdef VBOX_WITH_HDA_MIC_IN
3920	bool fEnableMicIn = RT_BOOL(HDA_SDCTL(pThis, 2 /** @todo Use a define. */) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3921	#endif
3922	bool fEnableOut = RT_BOOL(HDA_SDCTL(pThis, 4 /** @todo Use a define. */) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3923
3924	PHDADRIVER pDrv;
3925	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3926	{
3927	rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, fEnableIn);
3928	if (RT_FAILURE(rc))
3929	break;
3930	#ifdef VBOX_WITH_HDA_MIC_IN
3931	rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, fEnableMicIn);
3932	if (RT_FAILURE(rc))
3933	break;
3934	#endif
3935	rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, fEnableOut);
3936	if (RT_FAILURE(rc))
3937	break;
3938	}
3939	}
3940
3941	if (RT_SUCCESS(rc))
3942	{
3943	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3944	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3945	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3946
3947	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
3948	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
3949	}
3950	else
3951	LogRel(("HDA: Failed loading device state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
3952
3953	LogFlowFuncLeaveRC(rc);
3954	return rc;
3955	}
3956
3957	#ifdef DEBUG
3958	/* Debug and log type formatters. */
3959
3960	/**
3961	* @callback_method_impl{FNRTSTRFORMATTYPE}
3962	*/
3963	static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3964	const char pszType, void const pvValue,
3965	int cchWidth, int cchPrecision, unsigned fFlags,
3966	void *pvUser)
3967	{
3968	PHDABDLE pBDLE = (PHDABDLE)pvValue;
3969	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3970	"BDLE(idx:%RU32, off:%RU32, fifow:%RU32, DMA[%RU32 bytes @ 0x%x])",
3971	pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW, pBDLE->u32BufSize, pBDLE->u64BufAdr);
3972	}
3973
3974	/**
3975	* @callback_method_impl{FNRTSTRFORMATTYPE}
3976	*/
3977	static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3978	const char pszType, void const pvValue,
3979	int cchWidth, int cchPrecision, unsigned fFlags,
3980	void *pvUser)
3981	{
3982	uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
3983	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3984	"SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
3985	uSDCTL,
3986	(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
3987	RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3988	(uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3989	RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3990	RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
3991	RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3992	RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3993	RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3994	}
3995
3996	/**
3997	* @callback_method_impl{FNRTSTRFORMATTYPE}
3998	*/
3999	static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4000	const char pszType, void const pvValue,
4001	int cchWidth, int cchPrecision, unsigned fFlags,
4002	void *pvUser)
4003	{
4004	uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
4005	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, hdaSDFIFOSToBytes(uSDFIFOS));
4006	}
4007
4008	/**
4009	* @callback_method_impl{FNRTSTRFORMATTYPE}
4010	*/
4011	static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4012	const char pszType, void const pvValue,
4013	int cchWidth, int cchPrecision, unsigned fFlags,
4014	void *pvUser)
4015	{
4016	uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
4017	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
4018	}
4019
4020	/**
4021	* @callback_method_impl{FNRTSTRFORMATTYPE}
4022	*/
4023	static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4024	const char pszType, void const pvValue,
4025	int cchWidth, int cchPrecision, unsigned fFlags,
4026	void *pvUser)
4027	{
4028	uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
4029	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4030	"SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
4031	uSdSts,
4032	RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
4033	RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
4034	RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
4035	RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
4036	}
4037
4038	static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
4039	{
4040	int iReg = 0;
4041	for (; iReg < HDA_NREGS; ++iReg)
4042	if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
4043	return iReg;
4044	return -1;
4045	}
4046
4047
4048	static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
4049	{
4050	Assert( pThis
4051	&& iHdaIndex >= 0
4052	&& iHdaIndex < HDA_NREGS);
4053	pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
4054	}
4055
4056	/**
4057	* @callback_method_impl{FNDBGFHANDLERDEV}
4058	*/
4059	static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4060	{
4061	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4062	int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
4063	if (iHdaRegisterIndex != -1)
4064	hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4065	else
4066	for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
4067	hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4068	}
4069
4070	static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
4071	{
4072	Assert( pThis
4073	&& iHdaStrmIndex >= 0
4074	&& iHdaStrmIndex < 7);
4075	pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
4076	pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
4077	pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
4078	pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
4079	pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
4080	}
4081
4082	static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
4083	{
4084	/* todo: add args parsing */
4085	return -1;
4086	}
4087
4088	/**
4089	* @callback_method_impl{FNDBGFHANDLERDEV}
4090	*/
4091	static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4092	{
4093	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4094	int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
4095	if (iHdaStrmIndex != -1)
4096	hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
4097	else
4098	for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
4099	hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
4100	}
4101
4102	/**
4103	* @callback_method_impl{FNDBGFHANDLERDEV}
4104	*/
4105	static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4106	{
4107	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4108
4109	if (pThis->pCodec->pfnDbgListNodes)
4110	pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
4111	else
4112	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4113	}
4114
4115	/**
4116	* @callback_method_impl{FNDBGFHANDLERDEV}
4117	*/
4118	static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4119	{
4120	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4121
4122	if (pThis->pCodec->pfnDbgSelector)
4123	pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
4124	else
4125	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4126	}
4127
4128	/**
4129	* @callback_method_impl{FNDBGFHANDLERDEV}
4130	*/
4131	static DECLCALLBACK(void) hdaInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4132	{
4133	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4134
4135	if (pThis->pMixer)
4136	AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
4137	else
4138	pHlp->pfnPrintf(pHlp, "Mixer not available\n");
4139	}
4140	#endif /* DEBUG */
4141
4142	/* PDMIBASE */
4143
4144	/**
4145	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4146	*/
4147	static DECLCALLBACK(void ) hdaQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
4148	{
4149	PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
4150	Assert(&pThis->IBase == pInterface);
4151
4152	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4153	return NULL;
4154	}
4155
4156
4157	/* PDMDEVREG */
4158
4159	/**
4160	* Reset notification.
4161	*
4162	* @returns VBox status code.
4163	* @param pDevIns The device instance data.
4164	*
4165	* @remark The original sources didn't install a reset handler, but it seems to
4166	* make sense to me so we'll do it.
4167	*/
4168	static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
4169	{
4170	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4171
4172	HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
4173	HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
4174	HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
4175	HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
4176	HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
4177	HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
4178	HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
4179	HDA_REG(pThis, CORBRP) = 0x0;
4180	HDA_REG(pThis, RIRBWP) = 0x0;
4181
4182	LogFunc(("Resetting ...\n"));
4183
4184	# ifndef VBOX_WITH_AUDIO_CALLBACKS
4185	/*
4186	* Stop the timer, if any.
4187	*/
4188	int rc2;
4189	if (pThis->pTimer)
4190	{
4191	rc2 = TMTimerStop(pThis->pTimer);
4192	AssertRC(rc2);
4193	}
4194	# endif
4195
4196	/*
4197	* Stop any audio currently playing and/or recording.
4198	*/
4199	PHDADRIVER pDrv;
4200	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4201	{
4202	pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
4203	# ifdef VBOX_WITH_HDA_MIC_IN
4204	/* Ignore rc. */
4205	pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
4206	# endif
4207	/* Ditto. */
4208	pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
4209	/* Ditto. */
4210	}
4211
4212	pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
4213
4214	if (pThis->pu32CorbBuf)
4215	RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
4216	else
4217	pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
4218
4219	pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
4220	if (pThis->pu64RirbBuf)
4221	RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
4222	else
4223	pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
4224
4225	pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
4226
4227	for (uint8_t u8Strm = 0; u8Strm < 8; u8Strm++) /** @todo Use a define here. */
4228	{
4229	PHDASTREAM pStrmSt = NULL;
4230	if (u8Strm == 0) /** @todo Implement dynamic stream IDs. */
4231	pStrmSt = &pThis->StrmStLineIn;
4232	# ifdef VBOX_WITH_HDA_MIC_IN
4233	else if (u8Strm == 2) /** @todo Implement dynamic stream IDs. */
4234	pStrmSt = &pThis->StrmStMicIn;
4235	# endif
4236	else if (u8Strm == 4) /** @todo Implement dynamic stream IDs. */
4237	pStrmSt = &pThis->StrmStOut;
4238
4239	if (pStrmSt)
4240	{
4241	/* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
4242	HDA_STREAM_REG(pThis, CTL, u8Strm) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN);
4243
4244	hdaStreamReset(pThis, pStrmSt, u8Strm);
4245	}
4246	}
4247
4248	/* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
4249	HDA_REG(pThis, STATESTS) = 0x1;
4250
4251	# ifndef VBOX_WITH_AUDIO_CALLBACKS
4252	/*
4253	* Start timer again, if any.
4254	*/
4255	if (pThis->pTimer)
4256	{
4257	LogFunc(("Restarting timer\n"));
4258	rc2 = TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
4259	AssertRC(rc2);
4260	}
4261	# endif
4262
4263	LogRel(("HDA: Reset\n"));
4264	}
4265
4266	/**
4267	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4268	*/
4269	static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
4270	{
4271	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4272
4273	PHDADRIVER pDrv;
4274	while (!RTListIsEmpty(&pThis->lstDrv))
4275	{
4276	pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
4277
4278	RTListNodeRemove(&pDrv->Node);
4279	RTMemFree(pDrv);
4280	}
4281
4282	if (pThis->pMixer)
4283	{
4284	AudioMixerDestroy(pThis->pMixer);
4285	pThis->pMixer = NULL;
4286	}
4287
4288	if (pThis->pCodec)
4289	{
4290	int rc = hdaCodecDestruct(pThis->pCodec);
4291	AssertRC(rc);
4292
4293	RTMemFree(pThis->pCodec);
4294	pThis->pCodec = NULL;
4295	}
4296
4297	RTMemFree(pThis->pu32CorbBuf);
4298	pThis->pu32CorbBuf = NULL;
4299
4300	RTMemFree(pThis->pu64RirbBuf);
4301	pThis->pu64RirbBuf = NULL;
4302
4303	hdaStreamDestroy(&pThis->StrmStLineIn);
4304	hdaStreamDestroy(&pThis->StrmStMicIn);
4305	hdaStreamDestroy(&pThis->StrmStOut);
4306
4307	return VINF_SUCCESS;
4308	}
4309
4310
4311	/**
4312	* Attach command, internal version.
4313	*
4314	* This is called to let the device attach to a driver for a specified LUN
4315	* during runtime. This is not called during VM construction, the device
4316	* constructor has to attach to all the available drivers.
4317	*
4318	* @returns VBox status code.
4319	* @param pDevIns The device instance.
4320	* @param pDrv Driver to (re-)use for (re-)attaching to.
4321	* If NULL is specified, a new driver will be created and appended
4322	* to the driver list.
4323	* @param uLUN The logical unit which is being detached.
4324	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4325	*/
4326	static int hdaAttachInternal(PPDMDEVINS pDevIns, PHDADRIVER pDrv, unsigned uLUN, uint32_t fFlags)
4327	{
4328	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4329
4330	/*
4331	* Attach driver.
4332	*/
4333	char *pszDesc = NULL;
4334	if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4335	AssertReleaseMsgReturn(pszDesc,
4336	("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
4337	VERR_NO_MEMORY);
4338
4339	PPDMIBASE pDrvBase;
4340	int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
4341	&pThis->IBase, &pDrvBase, pszDesc);
4342	if (RT_SUCCESS(rc))
4343	{
4344	if (pDrv == NULL)
4345	pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4346	if (pDrv)
4347	{
4348	pDrv->pDrvBase = pDrvBase;
4349	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
4350	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4351	pDrv->pHDAState = pThis;
4352	pDrv->uLUN = uLUN;
4353
4354	/*
4355	* For now we always set the driver at LUN 0 as our primary
4356	* host backend. This might change in the future.
4357	*/
4358	if (pDrv->uLUN == 0)
4359	pDrv->Flags \|= PDMAUDIODRVFLAG_PRIMARY;
4360
4361	LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
4362
4363	/* Attach to driver list if not attached yet. */
4364	if (!pDrv->fAttached)
4365	{
4366	RTListAppend(&pThis->lstDrv, &pDrv->Node);
4367	pDrv->fAttached = true;
4368	}
4369	}
4370	else
4371	rc = VERR_NO_MEMORY;
4372	}
4373	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4374	{
4375	LogFunc(("No attached driver for LUN #%u\n", uLUN));
4376	}
4377	else if (RT_FAILURE(rc))
4378	AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
4379	uLUN, pszDesc, rc));
4380
4381	if (RT_FAILURE(rc))
4382	{
4383	/* Only free this string on failure;
4384	* must remain valid for the live of the driver instance. */
4385	RTStrFree(pszDesc);
4386	}
4387
4388	LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4389	return rc;
4390	}
4391
4392	/**
4393	* Attach command.
4394	*
4395	* This is called to let the device attach to a driver for a specified LUN
4396	* during runtime. This is not called during VM construction, the device
4397	* constructor has to attach to all the available drivers.
4398	*
4399	* @returns VBox status code.
4400	* @param pDevIns The device instance.
4401	* @param uLUN The logical unit which is being detached.
4402	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4403	*/
4404	static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4405	{
4406	return hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
4407	}
4408
4409	static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4410	{
4411	LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4412	}
4413
4414	/**
4415	* Re-attach.
4416	*
4417	* @returns VBox status code.
4418	* @param pThis Device instance.
4419	* @param pDrv Driver instance used for attaching to.
4420	* If NULL is specified, a new driver will be created and appended
4421	* to the driver list.
4422	* @param uLUN The logical unit which is being re-detached.
4423	* @param pszDriver Driver name.
4424	*/
4425	static int hdaReattach(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
4426	{
4427	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4428	AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
4429
4430	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4431	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
4432	PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
4433
4434	/* Remove LUN branch. */
4435	CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
4436
4437	if (pDrv)
4438	{
4439	/* Re-use a driver instance => detach the driver before. */
4440	int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
4441	if (RT_FAILURE(rc))
4442	return rc;
4443	}
4444
4445	#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
4446
4447	int rc = VINF_SUCCESS;
4448	do
4449	{
4450	PCFGMNODE pLunL0;
4451	rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
4452	rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
4453	rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
4454
4455	PCFGMNODE pLunL1, pLunL2;
4456	rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
4457	rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
4458	rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
4459
4460	rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
4461
4462	} while (0);
4463
4464	if (RT_SUCCESS(rc))
4465	rc = hdaAttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
4466
4467	LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
4468
4469	#undef RC_CHECK
4470
4471	return rc;
4472	}
4473
4474	/**
4475	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4476	*/
4477	static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4478	{
4479	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4480	Assert(iInstance == 0);
4481	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4482
4483	/*
4484	* Validations.
4485	*/
4486	if (!CFGMR3AreValuesValid(pCfg, "R0Enabled\0"
4487	"RCEnabled\0"
4488	"TimerHz\0"))
4489	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4490	N_ ("Invalid configuration for the Intel HDA device"));
4491
4492	int rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &pThis->fRCEnabled, false);
4493	if (RT_FAILURE(rc))
4494	return PDMDEV_SET_ERROR(pDevIns, rc,
4495	N_("HDA configuration error: failed to read RCEnabled as boolean"));
4496	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
4497	if (RT_FAILURE(rc))
4498	return PDMDEV_SET_ERROR(pDevIns, rc,
4499	N_("HDA configuration error: failed to read R0Enabled as boolean"));
4500	#ifndef VBOX_WITH_AUDIO_CALLBACKS
4501	uint16_t uTimerHz;
4502	rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, 200 /* Hz */);
4503	if (RT_FAILURE(rc))
4504	return PDMDEV_SET_ERROR(pDevIns, rc,
4505	N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4506	#endif
4507
4508	/*
4509	* Initialize data (most of it anyway).
4510	*/
4511	pThis->pDevInsR3 = pDevIns;
4512	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4513	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4514	/* IBase */
4515	pThis->IBase.pfnQueryInterface = hdaQueryInterface;
4516
4517	/* PCI Device */
4518	PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
4519	PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
4520
4521	PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
4522	PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
4523	PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
4524	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
4525	PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
4526	PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
4527	PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
4528	PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
4529	false /* fIoSpace /, false / fPrefetchable /, true / f64Bit */, 0x00000000);
4530	PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
4531	PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
4532
4533	#if defined(HDA_AS_PCI_EXPRESS)
4534	PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
4535	#elif defined(VBOX_WITH_MSI_DEVICES)
4536	PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
4537	#else
4538	PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
4539	#endif
4540
4541	/// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
4542	/// of these values needs to be properly documented!
4543	/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
4544	PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
4545
4546	/* Power Management */
4547	PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
4548	PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
4549	PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI \| 0x02 /* version, PM1.1 */ );
4550
4551	#ifdef HDA_AS_PCI_EXPRESS
4552	/* PCI Express */
4553	PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
4554	PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
4555	/* Device flags */
4556	PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
4557	/* version */ 0x1 \|
4558	/* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) \|
4559	/* MSI */ (100) << 9 );
4560	/* Device capabilities */
4561	PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
4562	/* Device control */
4563	PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
4564	/* Device status */
4565	PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
4566	/* Link caps */
4567	PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
4568	/* Link control */
4569	PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
4570	/* Link status */
4571	PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
4572	/* Slot capabilities */
4573	PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
4574	/* Slot control */
4575	PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
4576	/* Slot status */
4577	PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
4578	/* Root control */
4579	PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
4580	/* Root capabilities */
4581	PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
4582	/* Root status */
4583	PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
4584	/* Device capabilities 2 */
4585	PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
4586	/* Device control 2 */
4587	PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
4588	/* Link control 2 */
4589	PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
4590	/* Slot control 2 */
4591	PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
4592	#endif
4593
4594	/*
4595	* Register the PCI device.
4596	*/
4597	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
4598	if (RT_FAILURE(rc))
4599	return rc;
4600
4601	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
4602	if (RT_FAILURE(rc))
4603	return rc;
4604
4605	#ifdef VBOX_WITH_MSI_DEVICES
4606	PDMMSIREG MsiReg;
4607	RT_ZERO(MsiReg);
4608	MsiReg.cMsiVectors = 1;
4609	MsiReg.iMsiCapOffset = 0x60;
4610	MsiReg.iMsiNextOffset = 0x50;
4611	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4612	if (RT_FAILURE(rc))
4613	{
4614	/* That's OK, we can work without MSI */
4615	PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
4616	}
4617	#endif
4618
4619	rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
4620	if (RT_FAILURE(rc))
4621	return rc;
4622
4623	RTListInit(&pThis->lstDrv);
4624
4625	uint8_t uLUN;
4626	for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
4627	{
4628	LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
4629	rc = hdaAttachInternal(pDevIns, NULL /* pDrv /, uLUN, 0 / fFlags */);
4630	if (RT_FAILURE(rc))
4631	{
4632	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4633	rc = VINF_SUCCESS;
4634	else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
4635	{
4636	hdaReattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
4637	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4638	N_("No audio devices could be opened. Selecting the NULL audio backend "
4639	"with the consequence that no sound is audible"));
4640	/* attaching to the NULL audio backend will never fail */
4641	rc = VINF_SUCCESS;
4642	}
4643	break;
4644	}
4645	}
4646
4647	LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
4648
4649	if (RT_SUCCESS(rc))
4650	{
4651	rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
4652	if (RT_SUCCESS(rc))
4653	{
4654	/* Set a default audio format for our mixer. */
4655	PDMAUDIOSTREAMCFG streamCfg;
4656	streamCfg.uHz = 44100;
4657	streamCfg.cChannels = 2;
4658	streamCfg.enmFormat = AUD_FMT_S16;
4659	streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
4660
4661	rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
4662	AssertRC(rc);
4663
4664	/* Add all required audio sinks. */
4665	rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output",
4666	AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
4667	AssertRC(rc);
4668
4669	rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In",
4670	AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
4671	AssertRC(rc);
4672
4673	rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
4674	AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
4675	AssertRC(rc);
4676
4677	/* There is no master volume control. Set the master to max. */
4678	PDMAUDIOVOLUME vol = { false, 255, 255 };
4679	rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
4680	AssertRC(rc);
4681	}
4682	}
4683
4684	if (RT_SUCCESS(rc))
4685	{
4686	/* Construct codec. */
4687	pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
4688	if (!pThis->pCodec)
4689	return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
4690
4691	/* Audio driver callbacks for multiplexing. */
4692	pThis->pCodec->pfnCloseIn = hdaCloseIn;
4693	pThis->pCodec->pfnCloseOut = hdaCloseOut;
4694	pThis->pCodec->pfnOpenIn = hdaOpenIn;
4695	pThis->pCodec->pfnOpenOut = hdaOpenOut;
4696	pThis->pCodec->pfnReset = hdaCodecReset;
4697	pThis->pCodec->pfnSetVolume = hdaSetVolume;
4698
4699	pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
4700
4701	/* Construct the codec. */
4702	rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
4703	if (RT_FAILURE(rc))
4704	AssertRCReturn(rc, rc);
4705
4706	/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
4707	verb F20 should provide device/codec recognition. */
4708	Assert(pThis->pCodec->u16VendorId);
4709	Assert(pThis->pCodec->u16DeviceId);
4710	PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
4711	PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
4712	}
4713
4714	if (RT_SUCCESS(rc))
4715	{
4716	rc = hdaStreamCreate(&pThis->StrmStLineIn);
4717	AssertRC(rc);
4718	#ifdef VBOX_WITH_HDA_MIC_IN
4719	rc = hdaStreamCreate(&pThis->StrmStMicIn);
4720	AssertRC(rc);
4721	#endif
4722	rc = hdaStreamCreate(&pThis->StrmStOut);
4723	AssertRC(rc);
4724
4725	PHDADRIVER pDrv;
4726	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4727	{
4728	/*
4729	* Only primary drivers are critical for the VM to run. Everything else
4730	* might not worth showing an own error message box in the GUI.
4731	*/
4732	if (!(pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY))
4733	continue;
4734
4735	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
4736	AssertPtr(pCon);
4737
4738	uint8_t cFailed = 0;
4739	if (!pCon->pfnIsValidIn (pCon, pDrv->LineIn.pStrmIn))
4740	cFailed++;
4741	#ifdef VBOX_WITH_HDA_MIC_IN
4742	if (!pCon->pfnIsValidIn (pCon, pDrv->MicIn.pStrmIn))
4743	cFailed++;
4744	#endif
4745	if (!pCon->pfnIsValidOut(pCon, pDrv->Out.pStrmOut))
4746	cFailed++;
4747
4748	#ifdef VBOX_WITH_HDA_MIC_IN
4749	if (cFailed == 3)
4750	#else
4751	if (cFailed == 2)
4752	#endif
4753	{
4754	LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
4755
4756	hdaReset(pDevIns);
4757	hdaReattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
4758
4759	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4760	N_("No audio devices could be opened. Selecting the NULL audio backend "
4761	"with the consequence that no sound is audible"));
4762	}
4763	else if (cFailed)
4764	{
4765	if (!pDrv->pConnector->pfnIsValidIn (pDrv->pConnector, pDrv->LineIn.pStrmIn))
4766	LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU32!\n", pDrv->uLUN));
4767	#ifdef VBOX_WITH_HDA_MIC_IN
4768	if (!pDrv->pConnector->pfnIsValidIn (pDrv->pConnector, pDrv->MicIn.pStrmIn))
4769	LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU32!\n", pDrv->uLUN));
4770	#endif
4771	if (!pDrv->pConnector->pfnIsValidOut(pDrv->pConnector, pDrv->Out.pStrmOut))
4772	LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU32!\n", pDrv->uLUN));
4773
4774	char szMissingStreams[255];
4775	size_t len = 0;
4776	if (!pCon->pfnIsValidIn (pCon, pDrv->LineIn.pStrmIn))
4777	len = RTStrPrintf(szMissingStreams,
4778	sizeof(szMissingStreams), "PCM Input");
4779	#ifdef VBOX_WITH_HDA_MIC_IN
4780	if (!pCon->pfnIsValidIn (pCon, pDrv->MicIn.pStrmIn))
4781	len += RTStrPrintf(szMissingStreams + len,
4782	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
4783	#endif
4784	if (!pCon->pfnIsValidOut(pCon, pDrv->Out.pStrmOut))
4785	len += RTStrPrintf(szMissingStreams + len,
4786	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
4787
4788	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4789	N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
4790	"output or depending on audio input may hang. Make sure your host audio device "
4791	"is working properly. Check the logfile for error messages of the audio "
4792	"subsystem"), szMissingStreams);
4793	}
4794	}
4795	}
4796
4797	if (RT_SUCCESS(rc))
4798	{
4799	hdaReset(pDevIns);
4800
4801	/*
4802	* 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4803	* hdaReset shouldn't affects these registers.
4804	*/
4805	HDA_REG(pThis, WAKEEN) = 0x0;
4806	HDA_REG(pThis, STATESTS) = 0x0;
4807
4808	#ifdef DEBUG
4809	/*
4810	* Debug and string formatter types.
4811	*/
4812	PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
4813	PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
4814	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
4815	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
4816	PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaInfoMixer);
4817
4818	rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
4819	AssertRC(rc);
4820	rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
4821	AssertRC(rc);
4822	rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
4823	AssertRC(rc);
4824	rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
4825	AssertRC(rc);
4826	rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
4827	AssertRC(rc);
4828	#endif /* DEBUG */
4829
4830	/*
4831	* Some debug assertions.
4832	*/
4833	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
4834	{
4835	struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
4836	struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
4837
4838	/* binary search order. */
4839	AssertReleaseMsg(!pNextReg \|\| pReg->offset + pReg->size <= pNextReg->offset,
4840	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4841	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4842
4843	/* alignment. */
4844	AssertReleaseMsg( pReg->size == 1
4845	\|\| (pReg->size == 2 && (pReg->offset & 1) == 0)
4846	\|\| (pReg->size == 3 && (pReg->offset & 3) == 0)
4847	\|\| (pReg->size == 4 && (pReg->offset & 3) == 0),
4848	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4849
4850	/* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
4851	AssertRelease(((pReg->offset + pReg->size) & 3) == 0 \|\| pNextReg);
4852	if (pReg->offset & 3)
4853	{
4854	struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
4855	AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4856	if (pPrevReg)
4857	AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
4858	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4859	i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
4860	}
4861	#if 0
4862	if ((pReg->offset + pReg->size) & 3)
4863	{
4864	AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4865	if (pNextReg)
4866	AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
4867	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4868	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4869	}
4870	#endif
4871	/* The final entry is a full DWORD, no gaps! Allows shortcuts. */
4872	AssertReleaseMsg(pNextReg \|\| ((pReg->offset + pReg->size) & 3) == 0,
4873	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4874	}
4875	}
4876
4877	# ifndef VBOX_WITH_AUDIO_CALLBACKS
4878	if (RT_SUCCESS(rc))
4879	{
4880	/* Start the emulation timer. */
4881	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
4882	TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
4883	AssertRCReturn(rc, rc);
4884
4885	if (RT_SUCCESS(rc))
4886	{
4887	pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
4888	pThis->uTimerTS = TMTimerGet(pThis->pTimer);
4889	LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
4890
4891	/* Fire off timer. */
4892	TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
4893	}
4894	}
4895	# else
4896	if (RT_SUCCESS(rc))
4897	{
4898	PHDADRIVER pDrv;
4899	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4900	{
4901	/* Only register primary driver.
4902	* The device emulation does the output multiplexing then. */
4903	if (pDrv->Flags != PDMAUDIODRVFLAG_PRIMARY)
4904	continue;
4905
4906	PDMAUDIOCALLBACK AudioCallbacks[2];
4907
4908	HDACALLBACKCTX Ctx = { pThis, pDrv };
4909
4910	AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
4911	AudioCallbacks[0].pfnCallback = hdaCallbackInput;
4912	AudioCallbacks[0].pvCtx = &Ctx;
4913	AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
4914
4915	AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
4916	AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
4917	AudioCallbacks[1].pvCtx = &Ctx;
4918	AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
4919
4920	rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
4921	if (RT_FAILURE(rc))
4922	break;
4923	}
4924	}
4925	# endif
4926
4927	# ifdef VBOX_WITH_STATISTICS
4928	if (RT_SUCCESS(rc))
4929	{
4930	/*
4931	* Register statistics.
4932	*/
4933	# ifndef VBOX_WITH_AUDIO_CALLBACKS
4934	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
4935	# endif
4936	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
4937	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
4938	}
4939	# endif
4940
4941	LogFlowFuncLeaveRC(rc);
4942	return rc;
4943	}
4944
4945	/**
4946	* The device registration structure.
4947	*/
4948	const PDMDEVREG g_DeviceICH6_HDA =
4949	{
4950	/* u32Version */
4951	PDM_DEVREG_VERSION,
4952	/* szName */
4953	"hda",
4954	/* szRCMod */
4955	"VBoxDDRC.rc",
4956	/* szR0Mod */
4957	"VBoxDDR0.r0",
4958	/* pszDescription */
4959	"Intel HD Audio Controller",
4960	/* fFlags */
4961	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
4962	/* fClass */
4963	PDM_DEVREG_CLASS_AUDIO,
4964	/* cMaxInstances */
4965	1,
4966	/* cbInstance */
4967	sizeof(HDASTATE),
4968	/* pfnConstruct */
4969	hdaConstruct,
4970	/* pfnDestruct */
4971	hdaDestruct,
4972	/* pfnRelocate */
4973	NULL,
4974	/* pfnMemSetup */
4975	NULL,
4976	/* pfnPowerOn */
4977	NULL,
4978	/* pfnReset */
4979	hdaReset,
4980	/* pfnSuspend */
4981	NULL,
4982	/* pfnResume */
4983	NULL,
4984	/* pfnAttach */
4985	hdaAttach,
4986	/* pfnDetach */
4987	hdaDetach,
4988	/* pfnQueryInterface. */
4989	NULL,
4990	/* pfnInitComplete */
4991	NULL,
4992	/* pfnPowerOff */
4993	NULL,
4994	/* pfnSoftReset */
4995	NULL,
4996	/* u32VersionEnd */
4997	PDM_DEVREG_VERSION
4998	};
4999
5000	#endif /* IN_RING3 */
5001	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 59376

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