VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 61158

Last change on this file since 61158 was 61158, checked in by vboxsync, 9 years ago

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1/* $Id: DevIchHda.cpp 61158 2016-05-24 12:05:33Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2016 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/file.h>
36#include <iprt/list.h>
37#ifdef IN_RING3
38# include <iprt/mem.h>
39# include <iprt/semaphore.h>
40# include <iprt/string.h>
41# include <iprt/uuid.h>
42#endif
43
44#include "VBoxDD.h"
45
46#include "AudioMixBuffer.h"
47#include "AudioMixer.h"
48#include "DevIchHdaCodec.h"
49#include "DevIchHdaCommon.h"
50#include "DrvAudio.h"
51
52
53/*********************************************************************************************************************************
54* Defined Constants And Macros *
55*********************************************************************************************************************************/
56//#define HDA_AS_PCI_EXPRESS
57#define VBOX_WITH_INTEL_HDA
58
59#ifdef DEBUG_andy
60/* Enables experimental support for separate mic-in handling.
61 Do not enable this yet for regular builds, as this needs more testing first! */
62//# define VBOX_WITH_HDA_MIC_IN
63#endif
64
65#if defined(VBOX_WITH_HP_HDA)
66/* HP Pavilion dv4t-1300 */
67# define HDA_PCI_VENDOR_ID 0x103c
68# define HDA_PCI_DEVICE_ID 0x30f7
69#elif defined(VBOX_WITH_INTEL_HDA)
70/* Intel HDA controller */
71# define HDA_PCI_VENDOR_ID 0x8086
72# define HDA_PCI_DEVICE_ID 0x2668
73#elif defined(VBOX_WITH_NVIDIA_HDA)
74/* nVidia HDA controller */
75# define HDA_PCI_VENDOR_ID 0x10de
76# define HDA_PCI_DEVICE_ID 0x0ac0
77#else
78# error "Please specify your HDA device vendor/device IDs"
79#endif
80
81/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
82 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
83 * is read only except for bit 15 like the HDA spec states.
84 *
85 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
86 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
87#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
88
89/* Make sure that interleaving streams support is enabled if the 5.1 code is being used. */
90#if defined (VBOX_WITH_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT)
91# define VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
92#endif
93
94/**
95 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
96 * Bidirectional streams are currently *not* supported.
97 *
98 * Note: When changing any of those values, be prepared for some saved state
99 * fixups / trouble!
100 */
101#define HDA_MAX_SDI 4
102#define HDA_MAX_SDO 4
103#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
104AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
105
106/** Number of general registers. */
107#define HDA_NUM_GENERAL_REGS 34
108/** Number of total registers in the HDA's register map. */
109#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
110/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
111#define HDA_MAX_TAGS 16
112
113/**
114 * NB: Register values stored in memory (au32Regs[]) are indexed through
115 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
116 * register descriptors in g_aHdaRegMap[] are indexed through the
117 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
118 *
119 * The au32Regs[] layout is kept unchanged for saved state
120 * compatibility.
121 */
122
123/* Registers */
124#define HDA_REG_IND_NAME(x) HDA_REG_##x
125#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
126#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
127#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
128#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
129#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
130#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
131#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
132
133
134#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
135#define HDA_RMX_GCAP 0
136/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
137 * oss (15:12) - number of output streams supported
138 * iss (11:8) - number of input streams supported
139 * bss (7:3) - number of bidirectional streams supported
140 * bds (2:1) - number of serial data out (SDO) signals supported
141 * b64sup (0) - 64 bit addressing supported.
142 */
143#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
144 ( (((oss) & 0xF) << 12) \
145 | (((iss) & 0xF) << 8) \
146 | (((bss) & 0x1F) << 3) \
147 | (((bds) & 0x3) << 1) \
148 | ((b64sup) & 1))
149
150#define HDA_REG_VMIN 1 /* 0x02 */
151#define HDA_RMX_VMIN 1
152
153#define HDA_REG_VMAJ 2 /* 0x03 */
154#define HDA_RMX_VMAJ 2
155
156#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
157#define HDA_RMX_OUTPAY 3
158
159#define HDA_REG_INPAY 4 /* 0x06-0x07 */
160#define HDA_RMX_INPAY 4
161
162#define HDA_REG_GCTL 5 /* 0x08-0x0B */
163#define HDA_RMX_GCTL 5
164#define HDA_GCTL_RST_SHIFT 0
165#define HDA_GCTL_FSH_SHIFT 1
166#define HDA_GCTL_UR_SHIFT 8
167
168#define HDA_REG_WAKEEN 6 /* 0x0C */
169#define HDA_RMX_WAKEEN 6
170
171#define HDA_REG_STATESTS 7 /* 0x0E */
172#define HDA_RMX_STATESTS 7
173#define HDA_STATES_SCSF 0x7
174
175#define HDA_REG_GSTS 8 /* 0x10-0x11*/
176#define HDA_RMX_GSTS 8
177#define HDA_GSTS_FSH_SHIFT 1
178
179#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
180#define HDA_RMX_OUTSTRMPAY 112
181
182#define HDA_REG_INSTRMPAY 10 /* 0x1a */
183#define HDA_RMX_INSTRMPAY 113
184
185#define HDA_REG_INTCTL 11 /* 0x20 */
186#define HDA_RMX_INTCTL 9
187#define HDA_INTCTL_GIE_SHIFT 31
188#define HDA_INTCTL_CIE_SHIFT 30
189#define HDA_INTCTL_S0_SHIFT 0
190#define HDA_INTCTL_S1_SHIFT 1
191#define HDA_INTCTL_S2_SHIFT 2
192#define HDA_INTCTL_S3_SHIFT 3
193#define HDA_INTCTL_S4_SHIFT 4
194#define HDA_INTCTL_S5_SHIFT 5
195#define HDA_INTCTL_S6_SHIFT 6
196#define HDA_INTCTL_S7_SHIFT 7
197#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
198
199#define HDA_REG_INTSTS 12 /* 0x24 */
200#define HDA_RMX_INTSTS 10
201#define HDA_INTSTS_GIS_SHIFT 31
202#define HDA_INTSTS_CIS_SHIFT 30
203#define HDA_INTSTS_S0_SHIFT 0
204#define HDA_INTSTS_S1_SHIFT 1
205#define HDA_INTSTS_S2_SHIFT 2
206#define HDA_INTSTS_S3_SHIFT 3
207#define HDA_INTSTS_S4_SHIFT 4
208#define HDA_INTSTS_S5_SHIFT 5
209#define HDA_INTSTS_S6_SHIFT 6
210#define HDA_INTSTS_S7_SHIFT 7
211#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
212
213#define HDA_REG_WALCLK 13 /* 0x30 */
214#define HDA_RMX_WALCLK /* Not defined! */
215
216/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
217 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
218 * the datasheet.
219 */
220#define HDA_REG_SSYNC 14 /* 0x38 */
221#define HDA_RMX_SSYNC 12
222
223#define HDA_REG_CORBLBASE 15 /* 0x40 */
224#define HDA_RMX_CORBLBASE 13
225
226#define HDA_REG_CORBUBASE 16 /* 0x44 */
227#define HDA_RMX_CORBUBASE 14
228
229#define HDA_REG_CORBWP 17 /* 0x48 */
230#define HDA_RMX_CORBWP 15
231
232#define HDA_REG_CORBRP 18 /* 0x4A */
233#define HDA_RMX_CORBRP 16
234#define HDA_CORBRP_RST_SHIFT 15
235#define HDA_CORBRP_WP_SHIFT 0
236#define HDA_CORBRP_WP_MASK 0xFF
237
238#define HDA_REG_CORBCTL 19 /* 0x4C */
239#define HDA_RMX_CORBCTL 17
240#define HDA_CORBCTL_DMA_SHIFT 1
241#define HDA_CORBCTL_CMEIE_SHIFT 0
242
243#define HDA_REG_CORBSTS 20 /* 0x4D */
244#define HDA_RMX_CORBSTS 18
245#define HDA_CORBSTS_CMEI_SHIFT 0
246
247#define HDA_REG_CORBSIZE 21 /* 0x4E */
248#define HDA_RMX_CORBSIZE 19
249#define HDA_CORBSIZE_SZ_CAP 0xF0
250#define HDA_CORBSIZE_SZ 0x3
251/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
252
253#define HDA_REG_RIRBLBASE 22 /* 0x50 */
254#define HDA_RMX_RIRBLBASE 20
255
256#define HDA_REG_RIRBUBASE 23 /* 0x54 */
257#define HDA_RMX_RIRBUBASE 21
258
259#define HDA_REG_RIRBWP 24 /* 0x58 */
260#define HDA_RMX_RIRBWP 22
261#define HDA_RIRBWP_RST_SHIFT 15
262#define HDA_RIRBWP_WP_MASK 0xFF
263
264#define HDA_REG_RINTCNT 25 /* 0x5A */
265#define HDA_RMX_RINTCNT 23
266#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
267
268#define HDA_REG_RIRBCTL 26 /* 0x5C */
269#define HDA_RMX_RIRBCTL 24
270#define HDA_RIRBCTL_RIC_SHIFT 0
271#define HDA_RIRBCTL_DMA_SHIFT 1
272#define HDA_ROI_DMA_SHIFT 2
273
274#define HDA_REG_RIRBSTS 27 /* 0x5D */
275#define HDA_RMX_RIRBSTS 25
276#define HDA_RIRBSTS_RINTFL_SHIFT 0
277#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
278
279#define HDA_REG_RIRBSIZE 28 /* 0x5E */
280#define HDA_RMX_RIRBSIZE 26
281#define HDA_RIRBSIZE_SZ_CAP 0xF0
282#define HDA_RIRBSIZE_SZ 0x3
283
284#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
285#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
286
287
288#define HDA_REG_IC 29 /* 0x60 */
289#define HDA_RMX_IC 27
290
291#define HDA_REG_IR 30 /* 0x64 */
292#define HDA_RMX_IR 28
293
294#define HDA_REG_IRS 31 /* 0x68 */
295#define HDA_RMX_IRS 29
296#define HDA_IRS_ICB_SHIFT 0
297#define HDA_IRS_IRV_SHIFT 1
298
299#define HDA_REG_DPLBASE 32 /* 0x70 */
300#define HDA_RMX_DPLBASE 30
301#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
302
303#define HDA_REG_DPUBASE 33 /* 0x74 */
304#define HDA_RMX_DPUBASE 31
305#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
306
307#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
308
309#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
310#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
311/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
312#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
313
314#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
315
316/** @todo Condense marcos! */
317
318#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80 */
319#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
320#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
321#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
322#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
323#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
324#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
325#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
326#define HDA_RMX_SD0CTL 32
327#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
328#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
329#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
330#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
331#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
332#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
333#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
334
335#define SD(func, num) SD##num##func
336
337#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
338#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
339#define HDA_SDCTL_NUM_MASK 0xF
340#define HDA_SDCTL_NUM_SHIFT 20
341#define HDA_SDCTL_DIR_SHIFT 19
342#define HDA_SDCTL_TP_SHIFT 18
343#define HDA_SDCTL_STRIPE_MASK 0x3
344#define HDA_SDCTL_STRIPE_SHIFT 16
345#define HDA_SDCTL_DEIE_SHIFT 4
346#define HDA_SDCTL_FEIE_SHIFT 3
347#define HDA_SDCTL_ICE_SHIFT 2
348#define HDA_SDCTL_RUN_SHIFT 1
349#define HDA_SDCTL_SRST_SHIFT 0
350
351#define HDA_REG_SD0STS 35 /* 0x83 */
352#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
353#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
354#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
355#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
356#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
357#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
358#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
359#define HDA_RMX_SD0STS 33
360#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
361#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
362#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
363#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
364#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
365#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
366#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
367
368#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
369#define HDA_SDSTS_FIFORDY_SHIFT 5
370#define HDA_SDSTS_DE_SHIFT 4
371#define HDA_SDSTS_FE_SHIFT 3
372#define HDA_SDSTS_BCIS_SHIFT 2
373
374#define HDA_REG_SD0LPIB 36 /* 0x84 */
375#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
376#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
377#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
378#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
379#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
380#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
381#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
382#define HDA_RMX_SD0LPIB 34
383#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
384#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
385#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
386#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
387#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
388#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
389#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
390
391#define HDA_REG_SD0CBL 37 /* 0x88 */
392#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
393#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
394#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
395#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
396#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
397#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
398#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
399#define HDA_RMX_SD0CBL 35
400#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
401#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
402#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
403#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
404#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
405#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
406#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
407
408#define HDA_REG_SD0LVI 38 /* 0x8C */
409#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
410#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
411#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
412#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
413#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
414#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
415#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
416#define HDA_RMX_SD0LVI 36
417#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
418#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
419#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
420#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
421#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
422#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
423#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
424
425#define HDA_REG_SD0FIFOW 39 /* 0x8E */
426#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
427#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
428#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
429#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
430#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
431#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
432#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
433#define HDA_RMX_SD0FIFOW 37
434#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
435#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
436#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
437#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
438#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
439#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
440#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
441
442/*
443 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
444 */
445#define HDA_SDFIFOW_8B 0x2
446#define HDA_SDFIFOW_16B 0x3
447#define HDA_SDFIFOW_32B 0x4
448
449#define HDA_REG_SD0FIFOS 40 /* 0x90 */
450#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
451#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
452#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
453#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
454#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
455#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
456#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
457#define HDA_RMX_SD0FIFOS 38
458#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
459#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
460#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
461#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
462#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
463#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
464#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
465
466/*
467 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
468 * formula: size - 1
469 * Other values not listed are not supported.
470 */
471#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
472#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
473
474#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
475#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
476#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
477#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
478#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
479#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
480#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
481
482#define HDA_REG_SD0FMT 41 /* 0x92 */
483#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
484#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
485#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
486#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
487#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
488#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
489#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
490#define HDA_RMX_SD0FMT 39
491#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
492#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
493#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
494#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
495#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
496#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
497#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
498
499#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
500#define HDA_SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
501#define HDA_SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
502#define HDA_SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
503
504#define HDA_REG_SD0BDPL 42 /* 0x98 */
505#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
506#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
507#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
508#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
509#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
510#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
511#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
512#define HDA_RMX_SD0BDPL 40
513#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
514#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
515#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
516#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
517#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
518#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
519#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
520
521#define HDA_REG_SD0BDPU 43 /* 0x9C */
522#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
523#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
524#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
525#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
526#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
527#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
528#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
529#define HDA_RMX_SD0BDPU 41
530#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
531#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
532#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
533#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
534#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
535#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
536#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
537
538#define HDA_CODEC_CAD_SHIFT 28
539/* Encodes the (required) LUN into a codec command. */
540#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
541
542
543
544/*********************************************************************************************************************************
545* Structures and Typedefs *
546*********************************************************************************************************************************/
547
548/**
549 * Internal state of a Buffer Descriptor List Entry (BDLE),
550 * needed to keep track of the data needed for the actual device
551 * emulation.
552 */
553typedef struct HDABDLESTATE
554{
555 /** Own index within the BDL (Buffer Descriptor List). */
556 uint32_t u32BDLIndex;
557 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
558 * Used to check if we need fill up the FIFO again. */
559 uint32_t cbBelowFIFOW;
560 /** The buffer descriptor's internal DMA buffer. */
561 uint8_t au8FIFO[HDA_SDOFIFO_256B + 1];
562 /** Current offset in DMA buffer (in bytes).*/
563 uint32_t u32BufOff;
564 uint32_t Padding;
565} HDABDLESTATE, *PHDABDLESTATE;
566
567/**
568 * Buffer Descriptor List Entry (BDLE) (3.6.3).
569 *
570 * Contains only register values which do *not* change until a
571 * stream reset occurs.
572 */
573typedef struct HDABDLE
574{
575 /** Starting address of the actual buffer. Must be 128-bit aligned. */
576 uint64_t u64BufAdr;
577 /** Size of the actual buffer (in bytes). */
578 uint32_t u32BufSize;
579 /** Interrupt on completion; the controller will generate
580 * an interrupt when the last byte of the buffer has been
581 * fetched by the DMA engine. */
582 bool fIntOnCompletion;
583 /** Internal state of this BDLE.
584 * Not part of the actual BDLE registers. */
585 HDABDLESTATE State;
586} HDABDLE, *PHDABDLE;
587
588/**
589 * Structure for keeping an audio stream data mapping.
590 */
591typedef struct HDASTREAMMAPPING
592{
593 /** The stream's layout. */
594 PDMAUDIOSTREAMLAYOUT enmLayout;
595 /** Number of audio channels in this stream. */
596 uint8_t cChannels;
597 /** Array audio channels. */
598 R3PTRTYPE(PPDMAUDIOSTREAMCHANNEL) paChannels;
599 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
600} HDASTREAMMAPPING, *PHDASTREAMMAPPING;
601
602/**
603 * Internal state of a HDA stream.
604 */
605typedef struct HDASTREAMSTATE
606{
607 /** Current BDLE to use. Wraps around to 0 if
608 * maximum (cBDLE) is reached. */
609 uint16_t uCurBDLE;
610 /** Stop indicator. */
611 volatile bool fDoStop;
612 /** Flag indicating whether this stream is in an
613 * active (operative) state or not. */
614 volatile bool fActive;
615 /** Flag indicating whether this stream currently is
616 * in reset mode and therefore not acccessible by the guest. */
617 volatile bool fInReset;
618 /** Unused, padding. */
619 bool fPadding;
620 /** Mutex semaphore handle to serialize access. */
621 RTSEMMUTEX hMtx;
622 /** Event signalling that the stream's state has been changed. */
623 RTSEMEVENT hStateChangedEvent;
624 /** This stream's data mapping. */
625 HDASTREAMMAPPING Mapping;
626 /** Current BDLE (Buffer Descriptor List Entry). */
627 HDABDLE BDLE;
628} HDASTREAMSTATE, *PHDASTREAMSTATE;
629
630/**
631 * Structure defining an HDA mixer sink.
632 * Its purpose is to know which audio mixer sink is bound to
633 * which SDn (SDI/SDO) device stream.
634 *
635 * This is needed in order to handle interleaved streams
636 * (that is, multiple channels in one stream) or non-interleaved
637 * streams (each channel has a dedicated stream).
638 *
639 * This is only known to the actual device emulation level.
640 */
641typedef struct HDAMIXERSINK
642{
643 /** SDn ID this sink is assigned to. 0 if not assigned. */
644 uint8_t uSD;
645 /** Channel ID of SDn ID. Only valid if SDn ID is valid. */
646 uint8_t uChannel;
647 uint8_t Padding[3];
648 /** Pointer to the actual audio mixer sink. */
649 R3PTRTYPE(PAUDMIXSINK) pMixSink;
650} HDAMIXERSINK, *PHDAMIXERSINK;
651
652/**
653 * Structure for keeping a HDA stream state.
654 *
655 * Contains only register values which do *not* change until a
656 * stream reset occurs.
657 */
658typedef struct HDASTREAM
659{
660 /** Stream descriptor number (SDn). */
661 uint8_t u8SD;
662 uint8_t Padding0[7];
663 /** DMA base address (SDnBDPU - SDnBDPL). */
664 uint64_t u64BDLBase;
665 /** Cyclic Buffer Length (SDnCBL).
666 * Represents the size of the ring buffer. */
667 uint32_t u32CBL;
668 /** Format (SDnFMT). */
669 uint16_t u16FMT;
670 /** FIFO Size (FIFOS).
671 * Maximum number of bytes that may have been DMA'd into
672 * memory but not yet transmitted on the link.
673 *
674 * Must be a power of two. */
675 uint16_t u16FIFOS;
676 /** Last Valid Index (SDnLVI). */
677 uint16_t u16LVI;
678 uint16_t Padding1[3];
679 /** Pointer to HDA sink this stream is attached to. */
680 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
681 /** Internal state of this stream. */
682 HDASTREAMSTATE State;
683} HDASTREAM, *PHDASTREAM;
684
685/**
686 * Structure for mapping a stream tag to an HDA stream.
687 */
688typedef struct HDATAG
689{
690 /** Own stream tag. */
691 uint8_t uTag;
692 uint8_t Padding[7];
693 /** Pointer to associated stream. */
694 R3PTRTYPE(PHDASTREAM) pStrm;
695} HDATAG, *PHDATAG;
696
697/**
698 * Structure defining an HDA mixer stream.
699 * This is being used together with an audio mixer instance.
700 */
701typedef struct HDAMIXERSTREAM
702{
703 union
704 {
705 /** Desired playback destination (for an output stream). */
706 PDMAUDIOPLAYBACKDEST Dest;
707 /** Desired recording source (for an input stream). */
708 PDMAUDIORECSOURCE Source;
709 } DestSource;
710 uint8_t Padding1[4];
711 /** Associated mixer handle. */
712 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
713} HDAMIXERSTREAM, *PHDAMIXERSTREAM;
714
715/**
716 * Struct for maintaining a host backend driver.
717 * This driver must be associated to one, and only one,
718 * HDA codec. The HDA controller does the actual multiplexing
719 * of HDA codec data to various host backend drivers then.
720 *
721 * This HDA device uses a timer in order to synchronize all
722 * read/write accesses across all attached LUNs / backends.
723 */
724typedef struct HDADRIVER
725{
726 /** Node for storing this driver in our device driver list of HDASTATE. */
727 RTLISTNODER3 Node;
728 /** Pointer to HDA controller (state). */
729 R3PTRTYPE(PHDASTATE) pHDAState;
730 /** Driver flags. */
731 PDMAUDIODRVFLAGS Flags;
732 uint8_t u32Padding0[2];
733 /** LUN to which this driver has been assigned. */
734 uint8_t uLUN;
735 /** Whether this driver is in an attached state or not. */
736 bool fAttached;
737 /** Pointer to attached driver base interface. */
738 R3PTRTYPE(PPDMIBASE) pDrvBase;
739 /** Audio connector interface to the underlying host backend. */
740 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
741 /** Mixer stream for line input. */
742 HDAMIXERSTREAM LineIn;
743#ifdef VBOX_WITH_HDA_MIC_IN
744 /** Mixer stream for mic input. */
745 HDAMIXERSTREAM MicIn;
746#endif
747 /** Mixer stream for front output. */
748 HDAMIXERSTREAM Front;
749#ifdef VBOX_WITH_HDA_51_SURROUND
750 /** Mixer stream for center/LFE output. */
751 HDAMIXERSTREAM CenterLFE;
752 /** Mixer stream for rear output. */
753 HDAMIXERSTREAM Rear;
754#endif
755} HDADRIVER;
756
757/**
758 * ICH Intel HD Audio Controller state.
759 */
760typedef struct HDASTATE
761{
762 /** The PCI device structure. */
763 PCIDevice PciDev;
764 /** R3 Pointer to the device instance. */
765 PPDMDEVINSR3 pDevInsR3;
766 /** R0 Pointer to the device instance. */
767 PPDMDEVINSR0 pDevInsR0;
768 /** R0 Pointer to the device instance. */
769 PPDMDEVINSRC pDevInsRC;
770 /** Padding for alignment. */
771 uint32_t u32Padding;
772 /** The base interface for LUN\#0. */
773 PDMIBASE IBase;
774 RTGCPHYS MMIOBaseAddr;
775 /** The HDA's register set. */
776 uint32_t au32Regs[HDA_NUM_REGS];
777 /** Internal stream states. */
778 HDASTREAM aStreams[HDA_MAX_STREAMS];
779 /** Mapping table between stream tags and stream states. */
780 HDATAG aTags[HDA_MAX_TAGS];
781 /** CORB buffer base address. */
782 uint64_t u64CORBBase;
783 /** RIRB buffer base address. */
784 uint64_t u64RIRBBase;
785 /** DMA base address.
786 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
787 uint64_t u64DPBase;
788 /** DMA position buffer enable bit. */
789 bool fDMAPosition;
790 /** Padding for alignment. */
791 uint8_t u8Padding0[7];
792 /** Pointer to CORB buffer. */
793 R3PTRTYPE(uint32_t *) pu32CorbBuf;
794 /** Size in bytes of CORB buffer. */
795 uint32_t cbCorbBuf;
796 /** Padding for alignment. */
797 uint32_t u32Padding1;
798 /** Pointer to RIRB buffer. */
799 R3PTRTYPE(uint64_t *) pu64RirbBuf;
800 /** Size in bytes of RIRB buffer. */
801 uint32_t cbRirbBuf;
802 /** Indicates if HDA controller is in reset mode. */
803 bool fInReset;
804 /** Flag whether the R0 part is enabled. */
805 bool fR0Enabled;
806 /** Flag whether the RC part is enabled. */
807 bool fRCEnabled;
808 /** Number of active (running) SDn streams. */
809 uint8_t cStreamsActive;
810#ifndef VBOX_WITH_AUDIO_CALLBACKS
811 /** The timer for pumping data thru the attached LUN drivers. */
812 PTMTIMERR3 pTimer;
813 /** Flag indicating whether the timer is active or not. */
814 bool fTimerActive;
815 uint8_t u8Padding1[7];
816 /** Timer ticks per Hz. */
817 uint64_t cTimerTicks;
818 /** Timestamp of the last timer callback (hdaTimer).
819 * Used to calculate the time actually elapsed between two timer callbacks. */
820 uint64_t uTimerTS;
821#endif
822#ifdef VBOX_WITH_STATISTICS
823# ifndef VBOX_WITH_AUDIO_CALLBACKS
824 STAMPROFILE StatTimer;
825# endif
826 STAMCOUNTER StatBytesRead;
827 STAMCOUNTER StatBytesWritten;
828#endif
829 /** Pointer to HDA codec to use. */
830 R3PTRTYPE(PHDACODEC) pCodec;
831 /** List of associated LUN drivers (HDADRIVER). */
832 RTLISTANCHORR3 lstDrv;
833 /** The device' software mixer. */
834 R3PTRTYPE(PAUDIOMIXER) pMixer;
835 /** HDA sink for (front) output. */
836 HDAMIXERSINK SinkFront;
837#ifdef VBOX_WITH_HDA_51_SURROUND
838 /** HDA sink for center / LFE output. */
839 HDAMIXERSINK SinkCenterLFE;
840 /** HDA sink for rear output. */
841 HDAMIXERSINK SinkRear;
842#endif
843 /** HDA mixer sink for line input. */
844 HDAMIXERSINK SinkLineIn;
845#ifdef VBOX_WITH_HDA_MIC_IN
846 /** Audio mixer sink for microphone input. */
847 HDAMIXERSINK SinkMicIn;
848#endif
849 uint64_t u64BaseTS;
850 /** Response Interrupt Count (RINTCNT). */
851 uint8_t u8RespIntCnt;
852 /** Padding for alignment. */
853 uint8_t au8Padding2[7];
854} HDASTATE;
855/** Pointer to the ICH Intel HD Audio Controller state. */
856typedef HDASTATE *PHDASTATE;
857
858#ifdef VBOX_WITH_AUDIO_CALLBACKS
859typedef struct HDACALLBACKCTX
860{
861 PHDASTATE pThis;
862 PHDADRIVER pDriver;
863} HDACALLBACKCTX, *PHDACALLBACKCTX;
864#endif
865
866/*********************************************************************************************************************************
867* Internal Functions *
868*********************************************************************************************************************************/
869#ifndef VBOX_DEVICE_STRUCT_TESTCASE
870static FNPDMDEVRESET hdaReset;
871
872/*
873 * Stubs.
874 */
875static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
876static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
877
878/*
879 * Global register set read/write functions.
880 */
881static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
882static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
883static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
884static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
885static int hdaRegReadSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
886static int hdaRegWriteSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
887static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
888static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
889static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
890static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
891static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
892static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
893static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
894static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
895static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
896static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
897static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
898
899/*
900 * {IOB}SDn read/write functions.
901 */
902static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
903static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
904static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
905static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
906static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
907static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
908static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
909static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
910static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
911DECLINLINE(int) hdaRegWriteSDLock(PHDASTATE pThis, PHDASTREAM pStream, uint32_t iReg, uint32_t u32Value);
912DECLINLINE(void) hdaRegWriteSDUnlock(PHDASTREAM pStream);
913
914/*
915 * Generic register read/write functions.
916 */
917static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
918static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
919static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
920static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
921static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
922static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
923static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
924static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
925
926#ifdef IN_RING3
927static void hdaStreamDestroy(PHDASTREAM pStream);
928static int hdaStreamSetActive(PHDASTATE pThis, PHDASTREAM pStream, bool fActive);
929static int hdaStreamStart(PHDASTREAM pStream);
930static int hdaStreamStop(PHDASTREAM pStream);
931static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout);
932static int hdaTransfer(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToProcess, uint32_t *pcbProcessed);
933#endif
934
935#ifdef IN_RING3
936static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg);
937static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping);
938static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping);
939#endif
940
941#ifdef IN_RING3
942static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
943DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB);
944# ifdef LOG_ENABLED
945static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE);
946# endif
947#endif
948static int hdaProcessInterrupt(PHDASTATE pThis);
949
950/*
951 * Timer routines.
952 */
953#ifndef VBOX_WITH_AUDIO_CALLBACKS
954static void hdaTimerMaybeStart(PHDASTATE pThis);
955static void hdaTimerMaybeStop(PHDASTATE pThis);
956static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
957#endif
958
959/*********************************************************************************************************************************
960* Global Variables *
961*********************************************************************************************************************************/
962
963/** Offset of the SD0 register map. */
964#define HDA_REG_DESC_SD0_BASE 0x80
965
966/** Turn a short global register name into an memory index and a stringized name. */
967#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
968
969/** Turns a short stream register name into an memory index and a stringized name. */
970#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
971
972/** Same as above for a register *not* stored in memory. */
973#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
974
975/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
976#define HDA_REG_MAP_STRM(offset, name) \
977 /* offset size read mask write mask read callback write callback index + abbrev description */ \
978 /* ------- ------- ---------- ---------- -------------- ----------------- ------------------------------ ----------- */ \
979 /* Offset 0x80 (SD0) */ \
980 { offset, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
981 /* Offset 0x83 (SD0) */ \
982 { offset + 0x3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
983 /* Offset 0x84 (SD0) */ \
984 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
985 /* Offset 0x88 (SD0) */ \
986 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
987 /* Offset 0x8C (SD0) */ \
988 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
989 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
990 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteU16, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
991 /* Offset 0x90 (SD0) */ \
992 { offset + 0x10, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16, hdaRegWriteU16, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
993 /* Offset 0x92 (SD0) */ \
994 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
995 /* Reserved: 0x94 - 0x98. */ \
996 /* Offset 0x98 (SD0) */ \
997 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
998 /* Offset 0x9C (SD0) */ \
999 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
1000
1001/** Defines a single audio stream register set (e.g. OSD0). */
1002#define HDA_REG_MAP_DEF_STREAM(index, name) \
1003 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
1004
1005/* See 302349 p 6.2. */
1006static const struct HDAREGDESC
1007{
1008 /** Register offset in the register space. */
1009 uint32_t offset;
1010 /** Size in bytes. Registers of size > 4 are in fact tables. */
1011 uint32_t size;
1012 /** Readable bits. */
1013 uint32_t readable;
1014 /** Writable bits. */
1015 uint32_t writable;
1016 /** Read callback. */
1017 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
1018 /** Write callback. */
1019 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
1020 /** Index into the register storage array. */
1021 uint32_t mem_idx;
1022 /** Abbreviated name. */
1023 const char *abbrev;
1024 /** Descripton. */
1025 const char *desc;
1026} g_aHdaRegMap[HDA_NUM_REGS] =
1027
1028{
1029 /* offset size read mask write mask read callback write callback index + abbrev */
1030 /*------- ------- ---------- ---------- ----------------------- ---------------------- ---------------- */
1031 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
1032 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
1033 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
1034 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
1035 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
1036 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
1037 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
1038 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , HDA_REG_IDX(STATESTS) }, /* State Change Status */
1039 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
1040 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
1041 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
1042 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
1043 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
1044 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
1045 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
1046 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
1047 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
1048 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
1049 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
1050 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
1051 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
1052 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
1053 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
1054 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
1055 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
1056 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
1057 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
1058 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
1059 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
1060 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
1061 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
1062 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
1063 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
1064 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
1065 /* 4 Serial Data In (SDI). */
1066 HDA_REG_MAP_DEF_STREAM(0, SD0),
1067 HDA_REG_MAP_DEF_STREAM(1, SD1),
1068 HDA_REG_MAP_DEF_STREAM(2, SD2),
1069 HDA_REG_MAP_DEF_STREAM(3, SD3),
1070 /* 4 Serial Data Out (SDO). */
1071 HDA_REG_MAP_DEF_STREAM(4, SD4),
1072 HDA_REG_MAP_DEF_STREAM(5, SD5),
1073 HDA_REG_MAP_DEF_STREAM(6, SD6),
1074 HDA_REG_MAP_DEF_STREAM(7, SD7)
1075};
1076
1077/**
1078 * HDA register aliases (HDA spec 3.3.45).
1079 * @remarks Sorted by offReg.
1080 */
1081static const struct
1082{
1083 /** The alias register offset. */
1084 uint32_t offReg;
1085 /** The register index. */
1086 int idxAlias;
1087} g_aHdaRegAliases[] =
1088{
1089 { 0x2084, HDA_REG_SD0LPIB },
1090 { 0x20a4, HDA_REG_SD1LPIB },
1091 { 0x20c4, HDA_REG_SD2LPIB },
1092 { 0x20e4, HDA_REG_SD3LPIB },
1093 { 0x2104, HDA_REG_SD4LPIB },
1094 { 0x2124, HDA_REG_SD5LPIB },
1095 { 0x2144, HDA_REG_SD6LPIB },
1096 { 0x2164, HDA_REG_SD7LPIB },
1097};
1098
1099#ifdef IN_RING3
1100/** HDABDLE field descriptors for the v6+ saved state. */
1101static SSMFIELD const g_aSSMBDLEFields6[] =
1102{
1103 SSMFIELD_ENTRY(HDABDLE, u64BufAdr),
1104 SSMFIELD_ENTRY(HDABDLE, u32BufSize),
1105 SSMFIELD_ENTRY(HDABDLE, fIntOnCompletion),
1106 SSMFIELD_ENTRY_TERM()
1107};
1108
1109/** HDABDLESTATE field descriptors for the v6+ saved state. */
1110static SSMFIELD const g_aSSMBDLEStateFields6[] =
1111{
1112 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
1113 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
1114 SSMFIELD_ENTRY(HDABDLESTATE, au8FIFO),
1115 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
1116 SSMFIELD_ENTRY_TERM()
1117};
1118
1119/** HDASTREAMSTATE field descriptors for the v6+ saved state. */
1120static SSMFIELD const g_aSSMStreamStateFields6[] =
1121{
1122 SSMFIELD_ENTRY_OLD(cBDLE, 2),
1123 SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
1124 SSMFIELD_ENTRY(HDASTREAMSTATE, fDoStop),
1125 SSMFIELD_ENTRY(HDASTREAMSTATE, fActive),
1126 SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
1127 SSMFIELD_ENTRY_TERM()
1128};
1129#endif
1130
1131/**
1132 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1133 */
1134static uint32_t const g_afMasks[5] =
1135{
1136 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1137};
1138
1139#ifdef IN_RING3
1140DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB)
1141{
1142 AssertPtrReturn(pThis, 0);
1143 AssertPtrReturn(pStream, 0);
1144
1145 Assert(u32LPIB <= pStream->u32CBL);
1146
1147 LogFlowFunc(("[SD%RU8]: LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1148 pStream->u8SD, u32LPIB, pThis->fDMAPosition));
1149
1150 /* Update LPIB in any case. */
1151 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) = u32LPIB;
1152
1153 /* Do we need to tell the current DMA position? */
1154 if (pThis->fDMAPosition)
1155 {
1156 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1157 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStream->u8SD * 2 * sizeof(uint32_t)),
1158 (void *)&u32LPIB, sizeof(uint32_t));
1159 AssertRC(rc2);
1160 }
1161
1162 return u32LPIB;
1163}
1164#endif
1165
1166/**
1167 * Retrieves the number of bytes of a FIFOS register.
1168 *
1169 * @return Number of bytes of a given FIFOS register.
1170 */
1171DECLINLINE(uint16_t) hdaSDFIFOSToBytes(uint32_t u32RegFIFOS)
1172{
1173 uint16_t cb;
1174 switch (u32RegFIFOS)
1175 {
1176 /* Input */
1177 case HDA_SDIFIFO_120B: cb = 120; break;
1178 case HDA_SDIFIFO_160B: cb = 160; break;
1179
1180 /* Output */
1181 case HDA_SDOFIFO_16B: cb = 16; break;
1182 case HDA_SDOFIFO_32B: cb = 32; break;
1183 case HDA_SDOFIFO_64B: cb = 64; break;
1184 case HDA_SDOFIFO_128B: cb = 128; break;
1185 case HDA_SDOFIFO_192B: cb = 192; break;
1186 case HDA_SDOFIFO_256B: cb = 256; break;
1187 default:
1188 {
1189 cb = 0; /* Can happen on stream reset. */
1190 break;
1191 }
1192 }
1193
1194 return cb;
1195}
1196
1197/**
1198 * Retrieves the number of bytes of a FIFOW register.
1199 *
1200 * @return Number of bytes of a given FIFOW register.
1201 */
1202DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1203{
1204 uint32_t cb;
1205 switch (u32RegFIFOW)
1206 {
1207 case HDA_SDFIFOW_8B: cb = 8; break;
1208 case HDA_SDFIFOW_16B: cb = 16; break;
1209 case HDA_SDFIFOW_32B: cb = 32; break;
1210 default: cb = 0; break;
1211 }
1212
1213#ifdef RT_STRICT
1214 Assert(RT_IS_POWER_OF_TWO(cb));
1215#endif
1216 return cb;
1217}
1218
1219#ifdef IN_RING3
1220/**
1221 * Fetches the next BDLE to use for a stream.
1222 *
1223 * @return IPRT status code.
1224 */
1225DECLINLINE(int) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
1226{
1227 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1228 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1229
1230 NOREF(pThis);
1231
1232 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1233
1234 LogFlowFuncEnter();
1235
1236#ifdef DEBUG
1237 uint32_t uOldBDLE = pStream->State.uCurBDLE;
1238#endif
1239
1240 PHDABDLE pBDLE = &pStream->State.BDLE;
1241
1242 /*
1243 * Switch to the next BDLE entry and do a wrap around
1244 * if we reached the end of the Buffer Descriptor List (BDL).
1245 */
1246 pStream->State.uCurBDLE++;
1247 if (pStream->State.uCurBDLE == pStream->u16LVI + 1)
1248 {
1249 pStream->State.uCurBDLE = 0;
1250
1251 hdaStreamUpdateLPIB(pThis, pStream, 0);
1252 }
1253
1254 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1255
1256 /* Fetch the next BDLE entry. */
1257 int rc = hdaBDLEFetch(pThis, pBDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
1258
1259#ifdef DEBUG
1260 LogFlowFunc(("[SD%RU8]: uOldBDLE=%RU16, uCurBDLE=%RU16, LVI=%RU32, rc=%Rrc, %R[bdle]\n",
1261 pStream->u8SD, uOldBDLE, pStream->State.uCurBDLE, pStream->u16LVI, rc, pBDLE));
1262#endif
1263
1264 return rc;
1265}
1266#endif /* IN_RING3 */
1267
1268/**
1269 * Returns the audio direction of a specified stream descriptor.
1270 *
1271 * The register layout specifies that input streams (SDI) come first,
1272 * followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
1273 * is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
1274 *
1275 * Note: SDnFMT register does not provide that information, so we have to judge
1276 * for ourselves.
1277 *
1278 * @return Audio direction.
1279 */
1280DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
1281{
1282 AssertReturn(uSD <= HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
1283
1284 if (uSD < HDA_MAX_SDI)
1285 return PDMAUDIODIR_IN;
1286
1287 return PDMAUDIODIR_OUT;
1288}
1289
1290/**
1291 * Returns the HDA stream of specified stream descriptor number.
1292 *
1293 * @return Pointer to HDA stream, or NULL if none found.
1294 */
1295DECLINLINE(PHDASTREAM) hdaStreamFromSD(PHDASTATE pThis, uint8_t uSD)
1296{
1297 AssertPtrReturn(pThis, NULL);
1298 AssertReturn(uSD <= HDA_MAX_STREAMS, NULL);
1299
1300 if (uSD >= HDA_MAX_STREAMS)
1301 return NULL;
1302
1303 return &pThis->aStreams[uSD];
1304}
1305
1306/**
1307 * Returns the HDA stream of specified HDA sink.
1308 *
1309 * @return Pointer to HDA stream, or NULL if none found.
1310 */
1311DECLINLINE(PHDASTREAM) hdaGetStreamFromSink(PHDASTATE pThis, PHDAMIXERSINK pSink)
1312{
1313 AssertPtrReturn(pThis, NULL);
1314 AssertPtrReturn(pSink, NULL);
1315
1316 /** @todo Do something with the channel mapping here? */
1317 return hdaStreamFromSD(pThis, pSink->uSD);
1318}
1319
1320/**
1321 * Retrieves the minimum number of bytes accumulated/free in the
1322 * FIFO before the controller will start a fetch/eviction of data.
1323 *
1324 * Uses SDFIFOW (FIFO Watermark Register).
1325 *
1326 * @return Number of bytes accumulated/free in the FIFO.
1327 */
1328DECLINLINE(uint8_t) hdaStreamGetFIFOW(PHDASTATE pThis, PHDASTREAM pStream)
1329{
1330 AssertPtrReturn(pThis, 0);
1331 AssertPtrReturn(pStream, 0);
1332
1333#ifdef VBOX_HDA_WITH_FIFO
1334 return hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, pStream->u8SD));
1335#else
1336 return 0;
1337#endif
1338}
1339
1340static int hdaProcessInterrupt(PHDASTATE pThis)
1341{
1342#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1343 ( INTCTL_SX((pThis), num) \
1344 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1345
1346 int iLevel = 0;
1347
1348 /** @todo Optimize IRQ handling. */
1349
1350 if (/* Controller Interrupt Enable (CIE). */
1351 HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1352 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1353 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1354 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1355 {
1356 iLevel = 1;
1357 }
1358
1359 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1360 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 1)
1361 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 2)
1362 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 3)
1363 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4)
1364 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 5)
1365 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 6)
1366 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 7))
1367 {
1368 iLevel = 1;
1369 }
1370
1371 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1372 {
1373 Log3Func(("Level=%d\n", iLevel));
1374 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , iLevel);
1375 }
1376
1377#undef IS_INTERRUPT_OCCURED_AND_ENABLED
1378
1379 return VINF_SUCCESS;
1380}
1381
1382/**
1383 * Looks up a register at the exact offset given by @a offReg.
1384 *
1385 * @returns Register index on success, -1 if not found.
1386 * @param pThis The HDA device state.
1387 * @param offReg The register offset.
1388 */
1389static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1390{
1391 /*
1392 * Aliases.
1393 */
1394 if (offReg >= g_aHdaRegAliases[0].offReg)
1395 {
1396 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1397 if (offReg == g_aHdaRegAliases[i].offReg)
1398 return g_aHdaRegAliases[i].idxAlias;
1399 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1400 return -1;
1401 }
1402
1403 /*
1404 * Binary search the
1405 */
1406 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1407 int idxLow = 0;
1408 for (;;)
1409 {
1410 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1411 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1412 {
1413 if (idxLow == idxMiddle)
1414 break;
1415 idxEnd = idxMiddle;
1416 }
1417 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1418 {
1419 idxLow = idxMiddle + 1;
1420 if (idxLow >= idxEnd)
1421 break;
1422 }
1423 else
1424 return idxMiddle;
1425 }
1426
1427#ifdef RT_STRICT
1428 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1429 Assert(g_aHdaRegMap[i].offset != offReg);
1430#endif
1431 return -1;
1432}
1433
1434/**
1435 * Looks up a register covering the offset given by @a offReg.
1436 *
1437 * @returns Register index on success, -1 if not found.
1438 * @param pThis The HDA device state.
1439 * @param offReg The register offset.
1440 */
1441static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1442{
1443 /*
1444 * Aliases.
1445 */
1446 if (offReg >= g_aHdaRegAliases[0].offReg)
1447 {
1448 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1449 {
1450 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1451 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1452 return g_aHdaRegAliases[i].idxAlias;
1453 }
1454 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1455 return -1;
1456 }
1457
1458 /*
1459 * Binary search the register map.
1460 */
1461 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1462 int idxLow = 0;
1463 for (;;)
1464 {
1465 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1466 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1467 {
1468 if (idxLow == idxMiddle)
1469 break;
1470 idxEnd = idxMiddle;
1471 }
1472 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1473 {
1474 idxLow = idxMiddle + 1;
1475 if (idxLow >= idxEnd)
1476 break;
1477 }
1478 else
1479 return idxMiddle;
1480 }
1481
1482#ifdef RT_STRICT
1483 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1484 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1485#endif
1486 return -1;
1487}
1488
1489#ifdef IN_RING3
1490static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1491{
1492 int rc = VINF_SUCCESS;
1493 if (fLocal)
1494 {
1495 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1496 Assert(pThis->u64CORBBase);
1497 AssertPtr(pThis->pu32CorbBuf);
1498 Assert(pThis->cbCorbBuf);
1499
1500 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1501 if (RT_FAILURE(rc))
1502 AssertRCReturn(rc, rc);
1503#ifdef DEBUG_CMD_BUFFER
1504 uint8_t i = 0;
1505 do
1506 {
1507 LogFunc(("CORB%02x: ", i));
1508 uint8_t j = 0;
1509 do
1510 {
1511 const char *pszPrefix;
1512 if ((i + j) == HDA_REG(pThis, CORBRP));
1513 pszPrefix = "[R]";
1514 else if ((i + j) == HDA_REG(pThis, CORBWP));
1515 pszPrefix = "[W]";
1516 else
1517 pszPrefix = " "; /* three spaces */
1518 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1519 j++;
1520 } while (j < 8);
1521 LogFunc(("\n"));
1522 i += 8;
1523 } while(i != 0);
1524#endif
1525 }
1526 else
1527 {
1528 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1529 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1530 if (RT_FAILURE(rc))
1531 AssertRCReturn(rc, rc);
1532#ifdef DEBUG_CMD_BUFFER
1533 uint8_t i = 0;
1534 do {
1535 LogFunc(("RIRB%02x: ", i));
1536 uint8_t j = 0;
1537 do {
1538 const char *prefix;
1539 if ((i + j) == HDA_REG(pThis, RIRBWP))
1540 prefix = "[W]";
1541 else
1542 prefix = " ";
1543 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1544 } while (++j < 8);
1545 LogFunc(("\n"));
1546 i += 8;
1547 } while (i != 0);
1548#endif
1549 }
1550 return rc;
1551}
1552
1553static int hdaCORBCmdProcess(PHDASTATE pThis)
1554{
1555 int rc = hdaCmdSync(pThis, true);
1556 if (RT_FAILURE(rc))
1557 AssertRCReturn(rc, rc);
1558
1559 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1560 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1561 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1562
1563 Assert((corbWp != corbRp));
1564 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1565
1566 while (corbRp != corbWp)
1567 {
1568 uint64_t uResp;
1569 uint32_t uCmd = pThis->pu32CorbBuf[++corbRp];
1570
1571 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
1572 if (RT_FAILURE(rc2))
1573 LogFunc(("Codec lookup failed with rc=%Rrc\n", rc2));
1574
1575 (rirbWp)++;
1576
1577 if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
1578 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1579 {
1580 LogFunc(("Unexpected unsolicited response\n"));
1581 HDA_REG(pThis, CORBRP) = corbRp;
1582 return rc;
1583 }
1584
1585 pThis->pu64RirbBuf[rirbWp] = uResp;
1586
1587 pThis->u8RespIntCnt++;
1588 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1589 break;
1590 }
1591
1592 HDA_REG(pThis, CORBRP) = corbRp;
1593 HDA_REG(pThis, RIRBWP) = rirbWp;
1594
1595 rc = hdaCmdSync(pThis, false);
1596
1597 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1598
1599 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1600 {
1601 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1602
1603 pThis->u8RespIntCnt = 0;
1604 rc = hdaProcessInterrupt(pThis);
1605 }
1606
1607 if (RT_FAILURE(rc))
1608 AssertRCReturn(rc, rc);
1609 return rc;
1610}
1611
1612static int hdaStreamCreate(PHDASTREAM pStream, uint8_t uSD)
1613{
1614 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1615 AssertReturn(uSD <= HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
1616
1617 int rc = RTSemEventCreate(&pStream->State.hStateChangedEvent);
1618 if (RT_SUCCESS(rc))
1619 rc = RTSemMutexCreate(&pStream->State.hMtx);
1620
1621 if (RT_SUCCESS(rc))
1622 {
1623 pStream->u8SD = uSD;
1624 pStream->pMixSink = NULL;
1625
1626 pStream->State.fActive = false;
1627 pStream->State.fInReset = false;
1628 pStream->State.fDoStop = false;
1629 }
1630
1631 LogFlowFunc(("uSD=%RU8\n", uSD));
1632 return rc;
1633}
1634
1635static void hdaStreamDestroy(PHDASTREAM pStream)
1636{
1637 AssertPtrReturnVoid(pStream);
1638
1639 LogFlowFunc(("[SD%RU8]: Destroying ...\n", pStream->u8SD));
1640
1641 int rc2 = hdaStreamStop(pStream);
1642 AssertRC(rc2);
1643
1644 hdaStreamMapDestroy(&pStream->State.Mapping);
1645
1646 if (pStream->State.hMtx != NIL_RTSEMMUTEX)
1647 {
1648 rc2 = RTSemMutexDestroy(pStream->State.hMtx);
1649 AssertRC(rc2);
1650 pStream->State.hMtx = NIL_RTSEMMUTEX;
1651 }
1652
1653 if (pStream->State.hStateChangedEvent != NIL_RTSEMEVENT)
1654 {
1655 rc2 = RTSemEventDestroy(pStream->State.hStateChangedEvent);
1656 AssertRC(rc2);
1657 pStream->State.hStateChangedEvent = NIL_RTSEMEVENT;
1658 }
1659
1660 LogFlowFuncLeave();
1661}
1662
1663static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStream, uint8_t u8SD)
1664{
1665 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1666 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1667
1668 pStream->u8SD = u8SD;
1669 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1670 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1671 pStream->u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1672 pStream->u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1673 pStream->u16FIFOS = hdaSDFIFOSToBytes(HDA_STREAM_REG(pThis, FIFOS, pStream->u8SD));
1674
1675 RT_ZERO(pStream->State.BDLE);
1676 pStream->State.uCurBDLE = 0;
1677
1678 hdaStreamMapReset(&pStream->State.Mapping);
1679
1680 LogFlowFunc(("[SD%RU8]: DMA @ 0x%x (%RU32 bytes), LVI=%RU16, FIFOS=%RU16\n",
1681 pStream->u8SD, pStream->u64BDLBase, pStream->u32CBL, pStream->u16LVI, pStream->u16FIFOS));
1682
1683#ifdef DEBUG
1684 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1685 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1686 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1687 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1688
1689 LogFlowFunc(("\t-> DMA @ 0x%x, LVI=%RU16, CBL=%RU32\n", u64BaseDMA, u16LVI, u32CBL));
1690
1691 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
1692#endif
1693
1694 return VINF_SUCCESS;
1695}
1696
1697static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStream)
1698{
1699 AssertPtrReturnVoid(pThis);
1700 AssertPtrReturnVoid(pStream);
1701
1702 const uint8_t uSD = pStream->u8SD;
1703
1704#ifdef VBOX_STRICT
1705 AssertReleaseMsg(!RT_BOOL(HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
1706 ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
1707#endif
1708
1709 LogFunc(("[SD%RU8]: Reset\n", uSD));
1710
1711 /*
1712 * Set reset state.
1713 */
1714 Assert(ASMAtomicReadBool(&pStream->State.fInReset) == false); /* No nested calls. */
1715 ASMAtomicXchgBool(&pStream->State.fInReset, true);
1716
1717 /*
1718 * First, reset the internal stream state.
1719 */
1720 RT_ZERO(pStream->State.BDLE);
1721 pStream->State.uCurBDLE = 0;
1722
1723 /*
1724 * Second, initialize the registers.
1725 */
1726 HDA_STREAM_REG(pThis, STS, uSD) = HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1727 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1728 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1729 HDA_STREAM_REG(pThis, CTL, uSD) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1730 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39. */
1731 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
1732 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1733 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
1734 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
1735 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
1736 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
1737 HDA_STREAM_REG(pThis, FMT, uSD) = HDA_SDFMT_MAKE(HDA_SDFMT_TYPE_PCM, HDA_SDFMT_BASE_44KHZ,
1738 HDA_SDFMT_MULT_1X, HDA_SDFMT_DIV_1X, HDA_SDFMT_16_BIT,
1739 HDA_SDFMT_CHAN_STEREO);
1740 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
1741 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
1742
1743 int rc2 = hdaStreamInit(pThis, pStream, uSD);
1744 AssertRC(rc2);
1745
1746 /* Report that we're done resetting this stream. */
1747 HDA_STREAM_REG(pThis, CTL, uSD) = 0;
1748
1749 /* Exit reset state. */
1750 ASMAtomicXchgBool(&pStream->State.fInReset, false);
1751}
1752
1753static int hdaStreamSetActive(PHDASTATE pThis, PHDASTREAM pStream, bool fActive)
1754{
1755 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1756 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1757
1758 AUDMIXSINKCMD enmCmd = fActive
1759 ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE;
1760
1761 /* First, enable or disable the stream's sink, if any. */
1762 AssertPtr(pStream->pMixSink);
1763 if (pStream->pMixSink->pMixSink)
1764 AudioMixerSinkCtl(pStream->pMixSink->pMixSink, enmCmd);
1765
1766 /* Second, see if we need to start or stop the timer. */
1767 if (!fActive)
1768 {
1769 if (pThis->cStreamsActive) /* Disable can be called mupltiple times. */
1770 pThis->cStreamsActive--;
1771
1772#ifndef VBOX_WITH_AUDIO_CALLBACKS
1773 hdaTimerMaybeStop(pThis);
1774#endif
1775 }
1776 else
1777 {
1778 pThis->cStreamsActive++;
1779#ifndef VBOX_WITH_AUDIO_CALLBACKS
1780 hdaTimerMaybeStart(pThis);
1781#endif
1782 }
1783
1784 LogFlowFunc(("u8Strm=%RU8, fActive=%RTbool, cStreamsActive=%RU8\n", pStream->u8SD, fActive, pThis->cStreamsActive));
1785
1786 return VINF_SUCCESS;
1787}
1788
1789static void hdaStreamAssignToSink(PHDASTREAM pStream, PHDAMIXERSINK pMixSink)
1790{
1791 AssertPtrReturnVoid(pStream);
1792
1793 int rc2 = RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
1794 if (RT_SUCCESS(rc2))
1795 {
1796 pStream->pMixSink = pMixSink;
1797
1798 rc2 = RTSemMutexRelease(pStream->State.hMtx);
1799 AssertRC(rc2);
1800 }
1801}
1802
1803static int hdaStreamStart(PHDASTREAM pStream)
1804{
1805 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1806
1807 ASMAtomicXchgBool(&pStream->State.fDoStop, false);
1808 ASMAtomicXchgBool(&pStream->State.fActive, true);
1809
1810 LogFlowFuncLeave();
1811 return VINF_SUCCESS;
1812}
1813
1814static int hdaStreamStop(PHDASTREAM pStream)
1815{
1816 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1817
1818 /* Already in stopped state? */
1819 bool fActive = ASMAtomicReadBool(&pStream->State.fActive);
1820 if (!fActive)
1821 return VINF_SUCCESS;
1822
1823#if 0 /** @todo Does not work (yet), as EMT deadlocks then. */
1824 /*
1825 * Wait for the stream to stop.
1826 */
1827 ASMAtomicXchgBool(&pStream->State.fDoStop, true);
1828
1829 int rc = hdaStreamWaitForStateChange(pStream, 60 * 1000 /* ms timeout */);
1830 fActive = ASMAtomicReadBool(&pStream->State.fActive);
1831 if ( /* Waiting failed? */
1832 RT_FAILURE(rc)
1833 /* Stream is still active? */
1834 || fActive)
1835 {
1836 AssertRC(rc);
1837 LogRel(("HDA: Warning: Unable to stop stream %RU8 (state: %s), rc=%Rrc\n",
1838 pStream->u8Strm, fActive ? "active" : "stopped", rc));
1839 }
1840#else
1841 int rc = VINF_SUCCESS;
1842#endif
1843
1844 LogFlowFuncLeaveRC(rc);
1845 return rc;
1846}
1847
1848static int hdaStreamChannelExtract(PPDMAUDIOSTREAMCHANNEL pChan, const void *pvBuf, size_t cbBuf)
1849{
1850 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1851 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
1852 AssertReturn(cbBuf, VERR_INVALID_PARAMETER);
1853
1854 AssertRelease(pChan->cbOff <= cbBuf);
1855
1856 const uint8_t *pu8Buf = (const uint8_t *)pvBuf;
1857
1858 size_t cbSrc = cbBuf - pChan->cbOff;
1859 const uint8_t *pvSrc = &pu8Buf[pChan->cbOff];
1860
1861 size_t cbDst;
1862 uint8_t *pvDst;
1863 RTCircBufAcquireWriteBlock(pChan->Data.pCircBuf, cbBuf, (void **)&pvDst, &cbDst);
1864
1865 cbSrc = RT_MIN(cbSrc, cbDst);
1866
1867 while (cbSrc)
1868 {
1869 AssertBreak(cbDst >= cbSrc);
1870
1871 /* Enough data for at least one next frame? */
1872 if (cbSrc < pChan->cbFrame)
1873 break;
1874
1875 memcpy(pvDst, pvSrc, pChan->cbFrame);
1876
1877 /* Advance to next channel frame in stream. */
1878 pvSrc += pChan->cbStep;
1879 Assert(cbSrc >= pChan->cbStep);
1880 cbSrc -= pChan->cbStep;
1881
1882 /* Advance destination by one frame. */
1883 pvDst += pChan->cbFrame;
1884 Assert(cbDst >= pChan->cbFrame);
1885 cbDst -= pChan->cbFrame;
1886
1887 /* Adjust offset. */
1888 pChan->cbOff += pChan->cbFrame;
1889 }
1890
1891 RTCircBufReleaseWriteBlock(pChan->Data.pCircBuf, cbDst);
1892
1893 return VINF_SUCCESS;
1894}
1895
1896static int hdaStreamChannelAdvance(PPDMAUDIOSTREAMCHANNEL pChan, size_t cbAdv)
1897{
1898 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1899
1900 if (!cbAdv)
1901 return VINF_SUCCESS;
1902
1903 return VINF_SUCCESS;
1904}
1905
1906static int hdaStreamChannelDataInit(PPDMAUDIOSTREAMCHANNELDATA pChanData, uint32_t fFlags)
1907{
1908 int rc = RTCircBufCreate(&pChanData->pCircBuf, 256); /** @todo Make this configurable? */
1909 if (RT_SUCCESS(rc))
1910 {
1911 pChanData->fFlags = fFlags;
1912 }
1913
1914 return rc;
1915}
1916
1917/**
1918 * Frees a stream channel data block again.
1919 *
1920 * @param pChanData Pointer to channel data to free.
1921 */
1922static void hdaStreamChannelDataDestroy(PPDMAUDIOSTREAMCHANNELDATA pChanData)
1923{
1924 if (!pChanData)
1925 return;
1926
1927 if (pChanData->pCircBuf)
1928 {
1929 RTCircBufDestroy(pChanData->pCircBuf);
1930 pChanData->pCircBuf = NULL;
1931 }
1932
1933 pChanData->fFlags = PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE;
1934}
1935
1936static int hdaStreamChannelAcquireData(PPDMAUDIOSTREAMCHANNELDATA pChanData, void *pvData, size_t *pcbData)
1937{
1938 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
1939 AssertPtrReturn(pvData, VERR_INVALID_POINTER);
1940 AssertPtrReturn(pcbData, VERR_INVALID_POINTER);
1941
1942 RTCircBufAcquireReadBlock(pChanData->pCircBuf, 256 /** @todo Make this configurarble? */, &pvData, &pChanData->cbAcq);
1943
1944 *pcbData = pChanData->cbAcq;
1945 return VINF_SUCCESS;
1946}
1947
1948static int hdaStreamChannelReleaseData(PPDMAUDIOSTREAMCHANNELDATA pChanData)
1949{
1950 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
1951 RTCircBufReleaseReadBlock(pChanData->pCircBuf, pChanData->cbAcq);
1952
1953 return VINF_SUCCESS;
1954}
1955
1956static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout)
1957{
1958 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1959
1960 LogFlowFunc(("[SD%RU8]: msTimeout=%RU32\n", pStream->u8SD, msTimeout));
1961 return RTSemEventWait(pStream->State.hStateChangedEvent, msTimeout);
1962}
1963#endif /* IN_RING3 */
1964
1965/* Register access handlers. */
1966
1967static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1968{
1969 *pu32Value = 0;
1970 return VINF_SUCCESS;
1971}
1972
1973static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1974{
1975 return VINF_SUCCESS;
1976}
1977
1978/* U8 */
1979static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1980{
1981 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1982 return hdaRegReadU32(pThis, iReg, pu32Value);
1983}
1984
1985static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1986{
1987 Assert((u32Value & 0xffffff00) == 0);
1988 return hdaRegWriteU32(pThis, iReg, u32Value);
1989}
1990
1991/* U16 */
1992static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1993{
1994 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1995 return hdaRegReadU32(pThis, iReg, pu32Value);
1996}
1997
1998static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1999{
2000 Assert((u32Value & 0xffff0000) == 0);
2001 return hdaRegWriteU32(pThis, iReg, u32Value);
2002}
2003
2004/* U24 */
2005static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2006{
2007 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
2008 return hdaRegReadU32(pThis, iReg, pu32Value);
2009}
2010
2011static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2012{
2013 Assert((u32Value & 0xff000000) == 0);
2014 return hdaRegWriteU32(pThis, iReg, u32Value);
2015}
2016
2017/* U32 */
2018static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2019{
2020 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2021
2022 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
2023 return VINF_SUCCESS;
2024}
2025
2026static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2027{
2028 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2029
2030 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
2031 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
2032 return VINF_SUCCESS;
2033}
2034
2035static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2036{
2037 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
2038 {
2039 /* Set the CRST bit to indicate that we're leaving reset mode. */
2040 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2041
2042 if (pThis->fInReset)
2043 {
2044 LogFunc(("Guest leaving HDA reset\n"));
2045 pThis->fInReset = false;
2046 }
2047 }
2048 else
2049 {
2050#ifdef IN_RING3
2051 /* Enter reset state. */
2052 LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
2053 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
2054 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
2055
2056 /* Clear the CRST bit to indicate that we're in reset state. */
2057 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2058 pThis->fInReset = true;
2059
2060 hdaReset(pThis->CTX_SUFF(pDevIns));
2061#else
2062 return VINF_IOM_R3_MMIO_WRITE;
2063#endif
2064 }
2065
2066 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
2067 {
2068 /* Flush: GSTS:1 set, see 6.2.6. */
2069 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
2070 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
2071 }
2072 return VINF_SUCCESS;
2073}
2074
2075static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2076{
2077 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2078
2079 uint32_t v = pThis->au32Regs[iRegMem];
2080 uint32_t nv = u32Value & HDA_STATES_SCSF;
2081 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
2082 return VINF_SUCCESS;
2083}
2084
2085static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2086{
2087 uint32_t v = 0;
2088 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
2089 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
2090 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
2091 || HDA_REG(pThis, STATESTS))
2092 {
2093 v |= RT_BIT(30); /* Touch CIS. */
2094 }
2095
2096#define HDA_MARK_STREAM(x) \
2097 if (/* Descriptor Error */ \
2098 (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
2099 /* FIFO Error */ \
2100 || (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
2101 /* Buffer Completion Interrupt Status */ \
2102 || (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))) \
2103 { \
2104 Log3Func(("[SD%RU8] BCIS: Marked\n", x)); \
2105 v |= RT_BIT(x); \
2106 }
2107
2108 HDA_MARK_STREAM(0);
2109 HDA_MARK_STREAM(1);
2110 HDA_MARK_STREAM(2);
2111 HDA_MARK_STREAM(3);
2112 HDA_MARK_STREAM(4);
2113 HDA_MARK_STREAM(5);
2114 HDA_MARK_STREAM(6);
2115 HDA_MARK_STREAM(7);
2116
2117#undef HDA_MARK_STREAM
2118
2119 /* "OR" bit of all interrupt status bits. */
2120 v |= v ? RT_BIT(31) : 0;
2121
2122 *pu32Value = v;
2123 return VINF_SUCCESS;
2124}
2125
2126static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2127{
2128 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
2129 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
2130 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
2131
2132 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
2133
2134 *pu32Value = u32LPIB;
2135 return VINF_SUCCESS;
2136}
2137
2138static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2139{
2140 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2141 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
2142 - pThis->u64BaseTS, 24, 1000);
2143 LogFlowFunc(("%RU32\n", *pu32Value));
2144 return VINF_SUCCESS;
2145}
2146
2147static int hdaRegReadSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2148{
2149 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2150 *pu32Value = HDA_REG(pThis, SSYNC);
2151 LogFlowFunc(("%RU32\n", *pu32Value));
2152 return VINF_SUCCESS;
2153}
2154
2155static int hdaRegWriteSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2156{
2157 LogFlowFunc(("%RU32\n", u32Value));
2158 return hdaRegWriteU32(pThis, iReg, u32Value);
2159}
2160
2161static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2162{
2163 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
2164 {
2165 HDA_REG(pThis, CORBRP) = 0;
2166 }
2167#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
2168 else
2169 return hdaRegWriteU8(pThis, iReg, u32Value);
2170#endif
2171 return VINF_SUCCESS;
2172}
2173
2174static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2175{
2176#ifdef IN_RING3
2177 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
2178 AssertRC(rc);
2179 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2180 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
2181 {
2182 return hdaCORBCmdProcess(pThis);
2183 }
2184 return rc;
2185#else
2186 return VINF_IOM_R3_MMIO_WRITE;
2187#endif
2188}
2189
2190static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2191{
2192 uint32_t v = HDA_REG(pThis, CORBSTS);
2193 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
2194 return VINF_SUCCESS;
2195}
2196
2197static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2198{
2199#ifdef IN_RING3
2200 int rc;
2201 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2202 if (RT_FAILURE(rc))
2203 AssertRCReturn(rc, rc);
2204 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
2205 return VINF_SUCCESS;
2206 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2207 return VINF_SUCCESS;
2208 rc = hdaCORBCmdProcess(pThis);
2209 return rc;
2210#else /* !IN_RING3 */
2211 return VINF_IOM_R3_MMIO_WRITE;
2212#endif /* IN_RING3 */
2213}
2214
2215static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2216{
2217#ifdef IN_RING3
2218 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2219 return VINF_SUCCESS;
2220
2221 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
2222 if (!pStream)
2223 {
2224 LogFunc(("[SD%RU8]: Warning: Changing SDCBL on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2225 return hdaRegWriteU32(pThis, iReg, u32Value);
2226 }
2227
2228 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2229 AssertRC(rc2);
2230
2231 pStream->u32CBL = u32Value;
2232
2233 /* Reset BDLE state. */
2234 RT_ZERO(pStream->State.BDLE);
2235 pStream->State.uCurBDLE = 0;
2236
2237 rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2238 AssertRC(rc2);
2239
2240 LogFlowFunc(("[SD%RU8]: CBL=%RU32\n", pStream->u8SD, u32Value));
2241 hdaRegWriteSDUnlock(pStream);
2242
2243 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2244#else /* !IN_RING3 */
2245 return VINF_IOM_R3_MMIO_WRITE;
2246#endif /* IN_RING3 */
2247}
2248
2249static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2250{
2251 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2252 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2253 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2254 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2255
2256 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2257 return VINF_SUCCESS;
2258
2259 /* Get the stream descriptor. */
2260 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
2261
2262 /*
2263 * Extract the stream tag the guest wants to use for this specific
2264 * stream descriptor (SDn). This only can happen if the stream is in a non-running
2265 * state, so we're doing the lookup and assignment here.
2266 *
2267 * So depending on the guest OS, SD3 can use stream tag 4, for example.
2268 */
2269 uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
2270 if (uTag > HDA_MAX_TAGS)
2271 {
2272 LogFunc(("[SD%RU8]: Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
2273 return hdaRegWriteU24(pThis, iReg, u32Value);
2274 }
2275
2276#ifdef IN_RING3
2277 PHDATAG pTag = &pThis->aTags[uTag];
2278 AssertPtr(pTag);
2279
2280 LogFunc(("[SD%RU8]: Using stream tag=%RU8\n", uSD, uTag));
2281
2282 /* Assign new values. */
2283 pTag->uTag = uTag;
2284 pTag->pStrm = hdaStreamFromSD(pThis, uSD);
2285
2286 PHDASTREAM pStream = pTag->pStrm;
2287 AssertPtr(pStream);
2288
2289 /* Note: Do not use hdaRegWriteSDLock() here, as SDnCTL might change the RUN bit. */
2290 int rc2 = RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
2291 AssertRC(rc2);
2292#endif /* IN_RING3 */
2293
2294 LogFunc(("[SD%RU8]: fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
2295 uSD, fRun, fInRun, fReset, fInReset, u32Value));
2296
2297 if (fInReset)
2298 {
2299 Assert(!fReset);
2300 Assert(!fInRun && !fRun);
2301
2302 /* Report that we're done resetting this stream by clearing SRST. */
2303 HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
2304
2305 LogFunc(("[SD%RU8]: Guest initiated exit of stream reset\n", uSD));
2306 }
2307 else if (fReset)
2308 {
2309#ifdef IN_RING3
2310 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
2311 Assert(!fInRun && !fRun);
2312
2313 LogFunc(("[SD%RU8]: Guest initiated enter to stream reset\n", pStream->u8SD));
2314 hdaStreamReset(pThis, pStream);
2315#endif
2316 }
2317 else
2318 {
2319#ifdef IN_RING3
2320 /*
2321 * We enter here to change DMA states only.
2322 */
2323 if (fInRun != fRun)
2324 {
2325 Assert(!fReset && !fInReset);
2326 LogFunc(("[SD%RU8]: fRun=%RTbool\n", pStream->u8SD, fRun));
2327
2328 hdaStreamSetActive(pThis, pStream, fRun);
2329
2330 if (fRun)
2331 {
2332 /* (Re-)Fetch the current BDLE entry. */
2333 rc2 = hdaBDLEFetch(pThis, &pStream->State.BDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
2334 AssertRC(rc2);
2335 }
2336 }
2337
2338 if (!fInRun && !fRun)
2339 hdaStreamInit(pThis, pStream, pStream->u8SD);
2340#endif /* IN_RING3 */
2341 }
2342
2343 /* Make sure to handle interrupts here as well. */
2344 hdaProcessInterrupt(pThis);
2345
2346#ifdef IN_RING3
2347 rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
2348 AssertRC(rc2);
2349
2350 hdaRegWriteSDUnlock(pStream);
2351 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2352#else
2353 return VINF_IOM_R3_MMIO_WRITE;
2354#endif
2355}
2356
2357static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2358{
2359 uint32_t v = HDA_REG_IND(pThis, iReg);
2360 /* Clear (zero) FIFOE and DESE bits when writing 1 to it. */
2361 v &= ~(u32Value & v);
2362
2363 HDA_REG_IND(pThis, iReg) = v;
2364
2365 hdaProcessInterrupt(pThis);
2366 return VINF_SUCCESS;
2367}
2368
2369static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2370{
2371#ifdef IN_RING3
2372 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2373 return VINF_SUCCESS;
2374
2375 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, LVI, iReg));
2376 if (!pStream)
2377 {
2378 LogFunc(("[SD%RU8]: Warning: Changing SDLVI on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2379 return hdaRegWriteU16(pThis, iReg, u32Value);
2380 }
2381
2382 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2383 AssertRC(rc2);
2384
2385 /** @todo Validate LVI. */
2386 pStream->u16LVI = u32Value;
2387
2388 /* Reset BDLE state. */
2389 RT_ZERO(pStream->State.BDLE);
2390 pStream->State.uCurBDLE = 0;
2391
2392 rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
2393 AssertRC(rc2);
2394
2395 LogFlowFunc(("[SD%RU8]: LVI=%RU32\n", pStream->u8SD, u32Value));
2396 hdaRegWriteSDUnlock(pStream);
2397
2398 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2399#else /* !IN_RING3 */
2400 return VINF_IOM_R3_MMIO_WRITE;
2401#endif /* IN_RING3 */
2402}
2403
2404static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2405{
2406 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
2407 /** @todo Only allow updating FIFOS if RUN bit is 0? */
2408 uint32_t u32FIFOW = 0;
2409
2410 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
2411 {
2412 LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to stream #%RU8, ignoring\n", uSD));
2413 return VINF_SUCCESS;
2414 }
2415
2416 switch (u32Value)
2417 {
2418 case HDA_SDFIFOW_8B:
2419 case HDA_SDFIFOW_16B:
2420 case HDA_SDFIFOW_32B:
2421 u32FIFOW = u32Value;
2422 break;
2423 default:
2424 LogRel(("HDA: Warning: Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
2425 u32Value, uSD));
2426 u32FIFOW = HDA_SDFIFOW_32B;
2427 break;
2428 }
2429
2430 if (u32FIFOW)
2431 {
2432 LogFunc(("[SD%RU8]: Updating FIFOW to %RU32 bytes\n", uSD, hdaSDFIFOSToBytes(u32FIFOW)));
2433 /** @todo Update internal stream state with new FIFOS. */
2434
2435 return hdaRegWriteU16(pThis, iReg, u32FIFOW);
2436 }
2437
2438 return VINF_SUCCESS; /* Never reached. */
2439}
2440
2441/**
2442 * @note This method could be called for changing value on Output Streams
2443 * only (ICH6 datasheet 18.2.39).
2444 */
2445static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2446{
2447 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
2448 /** @todo Only allow updating FIFOS if RUN bit is 0? */
2449 uint32_t u32FIFOS = 0;
2450
2451 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
2452 {
2453 LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to stream #%RU8, ignoring\n", uSD));
2454 return VINF_SUCCESS;
2455 }
2456
2457 switch(u32Value)
2458 {
2459 case HDA_SDOFIFO_16B:
2460 case HDA_SDOFIFO_32B:
2461 case HDA_SDOFIFO_64B:
2462 case HDA_SDOFIFO_128B:
2463 case HDA_SDOFIFO_192B:
2464 u32FIFOS = u32Value;
2465 break;
2466
2467 case HDA_SDOFIFO_256B: /** @todo r=andy Investigate this. */
2468 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
2469 /* Fall through is intentional. */
2470 default:
2471 LogRel(("HDA: Warning: Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
2472 u32Value, uSD));
2473 u32FIFOS = HDA_SDOFIFO_192B;
2474 break;
2475 }
2476
2477 if (u32FIFOS)
2478 {
2479 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n",
2480 HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg), hdaSDFIFOSToBytes(u32FIFOS)));
2481 /** @todo Update internal stream state with new FIFOS. */
2482
2483 return hdaRegWriteU16(pThis, iReg, u32FIFOS);
2484 }
2485
2486 return VINF_SUCCESS;
2487}
2488
2489#ifdef IN_RING3
2490static int hdaSDFMTToStrmCfg(uint32_t u32SDFMT, PPDMAUDIOSTREAMCFG pStrmCfg)
2491{
2492 AssertPtrReturn(pStrmCfg, VERR_INVALID_POINTER);
2493
2494# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2495
2496 int rc = VINF_SUCCESS;
2497
2498 uint32_t u32Hz = EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BASE_RATE_MASK, HDA_SDFMT_BASE_RATE_SHIFT)
2499 ? 44100 : 48000;
2500 uint32_t u32HzMult = 1;
2501 uint32_t u32HzDiv = 1;
2502
2503 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2504 {
2505 case 0: u32HzMult = 1; break;
2506 case 1: u32HzMult = 2; break;
2507 case 2: u32HzMult = 3; break;
2508 case 3: u32HzMult = 4; break;
2509 default:
2510 LogFunc(("Unsupported multiplier %x\n",
2511 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2512 rc = VERR_NOT_SUPPORTED;
2513 break;
2514 }
2515 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2516 {
2517 case 0: u32HzDiv = 1; break;
2518 case 1: u32HzDiv = 2; break;
2519 case 2: u32HzDiv = 3; break;
2520 case 3: u32HzDiv = 4; break;
2521 case 4: u32HzDiv = 5; break;
2522 case 5: u32HzDiv = 6; break;
2523 case 6: u32HzDiv = 7; break;
2524 case 7: u32HzDiv = 8; break;
2525 default:
2526 LogFunc(("Unsupported divisor %x\n",
2527 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2528 rc = VERR_NOT_SUPPORTED;
2529 break;
2530 }
2531
2532 PDMAUDIOFMT enmFmt;
2533 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2534 {
2535 case 0:
2536 enmFmt = PDMAUDIOFMT_S8;
2537 break;
2538 case 1:
2539 enmFmt = PDMAUDIOFMT_S16;
2540 break;
2541 case 4:
2542 enmFmt = PDMAUDIOFMT_S32;
2543 break;
2544 default:
2545 AssertMsgFailed(("Unsupported bits per sample %x\n",
2546 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2547 rc = VERR_NOT_SUPPORTED;
2548 break;
2549 }
2550
2551 if (RT_SUCCESS(rc))
2552 {
2553 pStrmCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2554 pStrmCfg->cChannels = (u32SDFMT & 0xf) + 1;
2555 pStrmCfg->enmFormat = enmFmt;
2556 pStrmCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2557 }
2558
2559# undef EXTRACT_VALUE
2560 return rc;
2561}
2562
2563static int hdaAddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2564{
2565 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2566 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2567
2568 AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
2569
2570 LogFlowFunc(("Stream=%s\n", pCfg->szName));
2571
2572 int rc = VINF_SUCCESS;
2573
2574 bool fUseFront = true; /* Always use front out by default. */
2575#ifdef VBOX_WITH_HDA_51_SURROUND
2576 bool fUseRear;
2577 bool fUseCenter;
2578 bool fUseLFE;
2579
2580 fUseRear = fUseCenter = fUseLFE = false;
2581
2582 /*
2583 * Use commonly used setups for speaker configurations.
2584 */
2585
2586 /** @todo Make the following configurable through mixer API and/or CFGM? */
2587 switch (pCfg->cChannels)
2588 {
2589 case 3: /* 2.1: Front (Stereo) + LFE. */
2590 {
2591 fUseLFE = true;
2592 break;
2593 }
2594
2595 case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
2596 {
2597 fUseRear = true;
2598 break;
2599 }
2600
2601 case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
2602 {
2603 fUseRear = true;
2604 fUseLFE = true;
2605 break;
2606 }
2607
2608 case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
2609 {
2610 fUseRear = true;
2611 fUseCenter = true;
2612 fUseLFE = true;
2613 break;
2614 }
2615
2616 default: /* Unknown; fall back to 2 front channels (stereo). */
2617 {
2618 rc = VERR_NOT_SUPPORTED;
2619 break;
2620 }
2621 }
2622#else /* !VBOX_WITH_HDA_51_SURROUND */
2623 /* Only support mono or stereo channels. */
2624 if ( pCfg->cChannels != 1 /* Mono */
2625 && pCfg->cChannels != 2 /* Stereo */)
2626 {
2627 rc = VERR_NOT_SUPPORTED;
2628 }
2629#endif
2630
2631 if (rc == VERR_NOT_SUPPORTED)
2632 {
2633 LogRel(("HDA: Unsupported channel count (%RU8), falling back to stereo channels\n", pCfg->cChannels));
2634 pCfg->cChannels = 2;
2635
2636 rc = VINF_SUCCESS;
2637 }
2638
2639 do
2640 {
2641 if (RT_FAILURE(rc))
2642 break;
2643
2644 if (fUseFront)
2645 {
2646 if (!RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front"))
2647 {
2648 rc = VERR_BUFFER_OVERFLOW;
2649 break;
2650 }
2651
2652 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
2653 pCfg->cChannels = 2;
2654 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT);
2655 if (RT_SUCCESS(rc))
2656 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
2657 }
2658
2659#ifdef VBOX_WITH_HDA_51_SURROUND
2660 if ( RT_SUCCESS(rc)
2661 && (fUseCenter || fUseLFE))
2662 {
2663 if (!RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE"))
2664 {
2665 rc = VERR_BUFFER_OVERFLOW;
2666 break;
2667 }
2668
2669 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
2670 pCfg->cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
2671 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE);
2672 if (RT_SUCCESS(rc))
2673 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
2674 }
2675
2676 if ( RT_SUCCESS(rc)
2677 && fUseRear)
2678 {
2679 if (!RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear"))
2680 {
2681 rc = VERR_BUFFER_OVERFLOW;
2682 break;
2683 }
2684
2685 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
2686 pCfg->cChannels = 2;
2687 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR);
2688 if (RT_SUCCESS(rc))
2689 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
2690 }
2691#endif /* VBOX_WITH_HDA_51_SURROUND */
2692
2693 } while (0);
2694
2695 LogFlowFuncLeaveRC(rc);
2696 return rc;
2697}
2698
2699static int hdaAddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2700{
2701 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2702 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2703
2704 AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
2705
2706 LogFlowFunc(("Stream=%s\n", pCfg->szName));
2707
2708 int rc;
2709
2710 switch (pCfg->DestSource.Source)
2711 {
2712 case PDMAUDIORECSOURCE_LINE:
2713 {
2714 pCfg->DestSource.Source = PDMAUDIORECSOURCE_LINE;
2715 pCfg->cChannels = 2;
2716 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN);
2717 if (RT_SUCCESS(rc))
2718 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
2719 break;
2720 }
2721#ifdef VBOX_WITH_HDA_MIC_IN
2722 case PDMAUDIORECSOURCE_MIC:
2723 {
2724 pCfg->DestSource.Source = PDMAUDIORECSOURCE_MIC;
2725 pCfg->cChannels = 2;
2726 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN);
2727 if (RT_SUCCESS(rc))
2728 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
2729 break;
2730 }
2731#endif
2732 default:
2733 rc = VERR_NOT_SUPPORTED;
2734 break;
2735 }
2736
2737 LogFlowFuncLeaveRC(rc);
2738 return rc;
2739}
2740#endif /* IN_RING3 */
2741
2742static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2743{
2744#ifdef IN_RING3
2745 PDMAUDIOSTREAMCFG strmCfg;
2746 RT_ZERO(strmCfg);
2747
2748 int rc = hdaSDFMTToStrmCfg(u32Value, &strmCfg);
2749 if (RT_FAILURE(rc))
2750 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2751
2752 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg));
2753 if (!pStream)
2754 {
2755 LogFunc(("[SD%RU8]: Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2756 HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2757 return hdaRegWriteU16(pThis, iReg, u32Value);
2758 }
2759
2760 rc = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2761 AssertRC(rc);
2762
2763 LogFunc(("[SD%RU8]: Hz=%RU32, Channels=%RU8, enmFmt=%RU32\n",
2764 pStream->u8SD, strmCfg.uHz, strmCfg.cChannels, strmCfg.enmFormat));
2765
2766 /* Set audio direction. */
2767 strmCfg.enmDir = hdaGetDirFromSD(pStream->u8SD);
2768
2769 /*
2770 * Initialize the stream mapping in any case, regardless if
2771 * we support surround audio or not. This is needed to handle
2772 * the supported channels within a single audio stream, e.g. mono/stereo.
2773 *
2774 * In other words, the stream mapping *always* knowns the real
2775 * number of channels in a single audio stream.
2776 */
2777 rc = hdaStreamMapInit(&pStream->State.Mapping, &strmCfg);
2778 AssertRC(rc);
2779
2780 if (RT_SUCCESS(rc))
2781 {
2782 int rc2;
2783 PHDADRIVER pDrv;
2784 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2785 {
2786 switch (strmCfg.enmDir)
2787 {
2788 case PDMAUDIODIR_OUT:
2789 rc2 = hdaAddStreamOut(pThis, &strmCfg);
2790 break;
2791
2792 case PDMAUDIODIR_IN:
2793 rc2 = hdaAddStreamIn(pThis, &strmCfg);
2794 break;
2795
2796 default:
2797 rc2 = VERR_NOT_SUPPORTED;
2798 AssertFailed();
2799 break;
2800 }
2801
2802 if ( RT_FAILURE(rc2)
2803 && (pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY)) /* We only care about primary drivers here, the rest may fail. */
2804 {
2805 if (RT_SUCCESS(rc))
2806 rc = rc2;
2807 /* Keep going. */
2808 }
2809 }
2810
2811 /* If (re-)opening the stream by the codec above failed, don't write the new
2812 * format to the register so that the guest is aware it didn't work. */
2813 if (RT_SUCCESS(rc))
2814 {
2815 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2816 AssertRC(rc);
2817 }
2818 else
2819 LogFunc(("[SD%RU8]: (Re-)Opening stream failed with rc=%Rrc\n", pStream->u8SD, rc));
2820
2821 hdaRegWriteSDUnlock(pStream);
2822 }
2823
2824 return VINF_SUCCESS; /* Never return failure. */
2825#else /* !IN_RING3 */
2826 return VINF_IOM_R3_MMIO_WRITE;
2827#endif
2828}
2829
2830/* Note: Will be called for both, BDPL and BDPU, registers. */
2831DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t u8Strm)
2832{
2833#ifdef IN_RING3
2834 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2835 return VINF_SUCCESS;
2836
2837 PHDASTREAM pStream = hdaStreamFromSD(pThis, u8Strm);
2838 if (!pStream)
2839 {
2840 LogFunc(("[SD%RU8]: Warning: Changing SDBPL/SDBPU on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2841 return hdaRegWriteU32(pThis, iReg, u32Value);
2842 }
2843
2844 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2845 AssertRC(rc2);
2846
2847 rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2848 AssertRC(rc2);
2849
2850 /* Update BDL base. */
2851 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2852 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2853 /* Reset BDLE state. */
2854 RT_ZERO(pStream->State.BDLE);
2855 pStream->State.uCurBDLE = 0;
2856
2857 LogFlowFunc(("[SD%RU8]: BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2858 hdaRegWriteSDUnlock(pStream);
2859
2860 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2861#else /* !IN_RING3 */
2862 return VINF_IOM_R3_MMIO_WRITE;
2863#endif /* IN_RING3 */
2864}
2865
2866static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2867{
2868 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2869}
2870
2871static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2872{
2873 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2874}
2875
2876#ifdef IN_RING3
2877/**
2878 * XXX
2879 *
2880 * @return bool Returns @true if write is allowed, @false if not.
2881 * @param pThis Pointer to HDA state.
2882 * @param iReg Register to write.
2883 * @param u32Value Value to write.
2884 */
2885DECLINLINE(int) hdaRegWriteSDLock(PHDASTATE pThis, PHDASTREAM pStream, uint32_t iReg, uint32_t u32Value)
2886{
2887 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2888 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
2889
2890#ifdef VBOX_STRICT
2891 /* Check if the SD's RUN bit is set. */
2892 uint32_t u32SDCTL = HDA_STREAM_REG(pThis, CTL, pStream->u8SD);
2893 bool fIsRunning = RT_BOOL(u32SDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2894 if (fIsRunning)
2895 {
2896 LogFunc(("[SD%RU8]: Warning: Cannot write to register 0x%x (0x%x) when RUN bit is set (%R[sdctl])\n",
2897 pStream->u8SD, iReg, u32Value, u32SDCTL));
2898# ifdef DEBUG_andy
2899 AssertFailed();
2900# endif
2901 return VERR_ACCESS_DENIED;
2902 }
2903#endif
2904
2905 return RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
2906}
2907
2908DECLINLINE(void) hdaRegWriteSDUnlock(PHDASTREAM pStream)
2909{
2910 AssertPtrReturnVoid(pStream);
2911
2912 int rc2 = RTSemMutexRelease(pStream->State.hMtx);
2913 AssertRC(rc2);
2914}
2915#endif /* IN_RING3 */
2916
2917static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2918{
2919 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2920 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2921 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2922 {
2923 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2924 }
2925
2926 return hdaRegReadU32(pThis, iReg, pu32Value);
2927}
2928
2929static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2930{
2931 int rc = VINF_SUCCESS;
2932
2933 /*
2934 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2935 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2936 */
2937 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
2938 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
2939 {
2940#ifdef IN_RING3
2941 uint32_t uCmd = HDA_REG(pThis, IC);
2942
2943 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2944 {
2945 /*
2946 * 3.4.3: Defines behavior of immediate Command status register.
2947 */
2948 LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
2949 return rc;
2950 }
2951
2952 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2953
2954 uint64_t uResp;
2955 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
2956 HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
2957 if (RT_FAILURE(rc2))
2958 LogFunc(("Codec lookup failed with rc=%Rrc\n", rc2));
2959
2960 HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
2961 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
2962 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
2963#else /* !IN_RING3 */
2964 rc = VINF_IOM_R3_MMIO_WRITE;
2965#endif
2966 return rc;
2967 }
2968
2969 /*
2970 * Once the guest read the response, it should clean the IRV bit of the IRS register.
2971 */
2972 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
2973 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
2974 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
2975 return rc;
2976}
2977
2978static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2979{
2980 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
2981 HDA_REG(pThis, RIRBWP) = 0;
2982
2983 /* The remaining bits are O, see 6.2.22. */
2984 return VINF_SUCCESS;
2985}
2986
2987static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2988{
2989 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2990 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2991 if (RT_FAILURE(rc))
2992 AssertRCReturn(rc, rc);
2993
2994 switch(iReg)
2995 {
2996 case HDA_REG_CORBLBASE:
2997 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2998 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
2999 break;
3000 case HDA_REG_CORBUBASE:
3001 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
3002 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3003 break;
3004 case HDA_REG_RIRBLBASE:
3005 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
3006 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
3007 break;
3008 case HDA_REG_RIRBUBASE:
3009 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
3010 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3011 break;
3012 case HDA_REG_DPLBASE:
3013 {
3014 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
3015 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
3016
3017 /* Also make sure to handle the DMA position enable bit. */
3018 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
3019 LogRel(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
3020 break;
3021 }
3022 case HDA_REG_DPUBASE:
3023 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
3024 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3025 break;
3026 default:
3027 AssertMsgFailed(("Invalid index\n"));
3028 break;
3029 }
3030
3031 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
3032 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
3033 return rc;
3034}
3035
3036static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3037{
3038 uint8_t v = HDA_REG(pThis, RIRBSTS);
3039 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
3040
3041 return hdaProcessInterrupt(pThis);
3042}
3043
3044#ifdef IN_RING3
3045#ifdef LOG_ENABLED
3046static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE)
3047{
3048 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
3049 if (!u64BDLBase)
3050 return;
3051
3052 uint32_t cbBDLE = 0;
3053 for (uint16_t i = 0; i < cBDLE; i++)
3054 {
3055 uint8_t bdle[16]; /** @todo Use a define. */
3056 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BDLBase + i * 16, bdle, 16); /** @todo Use a define. */
3057
3058 uint64_t addr = *(uint64_t *)bdle;
3059 uint32_t len = *(uint32_t *)&bdle[8];
3060 uint32_t ioc = *(uint32_t *)&bdle[12];
3061
3062 LogFlowFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
3063 i, addr, len, RT_BOOL(ioc & 0x1)));
3064
3065 cbBDLE += len;
3066 }
3067
3068 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
3069
3070 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
3071 return;
3072
3073 LogFlowFunc(("DMA counters:\n"));
3074
3075 for (int i = 0; i < cBDLE; i++)
3076 {
3077 uint32_t uDMACnt;
3078 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
3079 &uDMACnt, sizeof(uDMACnt));
3080
3081 LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
3082 }
3083}
3084#endif
3085
3086/**
3087 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
3088 *
3089 * @param pThis Pointer to HDA state.
3090 * @param pBDLE Where to store the fetched result.
3091 * @param u64BaseDMA Address base of DMA engine to use.
3092 * @param u16Entry BDLE entry to fetch.
3093 */
3094static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
3095{
3096 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3097 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
3098 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
3099
3100 if (!u64BaseDMA)
3101 {
3102 LogRel2(("HDA: Unable to fetch BDLE #%RU16 - no base DMA address set (yet)\n", u16Entry));
3103 return VERR_NOT_FOUND;
3104 }
3105 /** @todo Compare u16Entry with LVI. */
3106
3107 uint8_t uBundleEntry[16]; /** @todo Define a BDLE length. */
3108 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * 16, /** @todo Define a BDLE length. */
3109 uBundleEntry, RT_ELEMENTS(uBundleEntry));
3110 if (RT_FAILURE(rc))
3111 return rc;
3112
3113 RT_BZERO(pBDLE, sizeof(HDABDLE));
3114
3115 pBDLE->State.u32BDLIndex = u16Entry;
3116 pBDLE->u64BufAdr = *(uint64_t *) uBundleEntry;
3117 pBDLE->u32BufSize = *(uint32_t *)&uBundleEntry[8];
3118 if (pBDLE->u32BufSize < sizeof(uint16_t)) /* Must be at least one word. */
3119 return VERR_INVALID_STATE;
3120
3121 pBDLE->fIntOnCompletion = (*(uint32_t *)&uBundleEntry[12]) & RT_BIT(0);
3122
3123 return VINF_SUCCESS;
3124}
3125
3126/**
3127 * Returns the number of outstanding stream data bytes which need to be processed
3128 * by the DMA engine assigned to this stream.
3129 *
3130 * @return Number of bytes for the DMA engine to process.
3131 */
3132DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax)
3133{
3134 AssertPtrReturn(pThis, 0);
3135 AssertPtrReturn(pStream, 0);
3136
3137 if (!cbMax)
3138 return 0;
3139
3140 PHDABDLE pBDLE = &pStream->State.BDLE;
3141
3142 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3143 Assert(u32LPIB <= pStream->u32CBL);
3144
3145 uint32_t cbFree = pStream->u32CBL - u32LPIB;
3146 if (cbFree)
3147 {
3148 /* Limit to the available free space of the current BDLE. */
3149 cbFree = RT_MIN(cbFree, pBDLE->u32BufSize - pBDLE->State.u32BufOff);
3150
3151 /* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
3152 // cbFree = RT_MIN(cbFree, uint32_t(pStream->u16FIFOS));
3153
3154 /* Make sure we only transfer as many bytes as requested. */
3155 cbFree = RT_MIN(cbFree, cbMax);
3156
3157 if (pBDLE->State.cbBelowFIFOW)
3158 {
3159 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
3160 * No need to read data from DMA then. */
3161 if (cbFree > pBDLE->State.cbBelowFIFOW)
3162 {
3163 /* Subtract the amount of bytes that still would fit in the stream's FIFO
3164 * and therefore do not need to be processed by DMA. */
3165 cbFree -= pBDLE->State.cbBelowFIFOW;
3166 }
3167 }
3168 }
3169
3170 LogFlowFunc(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, FIFOS=%RU16, cbFree=%RU32, %R[bdle]\n", pStream->u8SD,
3171 pStream->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), pStream->u16FIFOS, cbFree, pBDLE));
3172 return cbFree;
3173}
3174
3175DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
3176{
3177 AssertPtrReturnVoid(pBDLE);
3178
3179 if (!cbData || !cbProcessed)
3180 return;
3181
3182 /* Fewer than cbBelowFIFOW bytes were copied.
3183 * Probably we need to move the buffer, but it is rather hard to imagine a situation
3184 * where it might happen. */
3185 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
3186 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
3187 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
3188
3189#if 0
3190 if ( pBDLE->State.cbBelowFIFOW
3191 && pBDLE->State.cbBelowFIFOW <= cbWritten)
3192 {
3193 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
3194 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->u32BufSize));
3195 }
3196#endif
3197
3198 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
3199 Assert(pBDLE->State.cbBelowFIFOW == 0);
3200
3201 /* We always increment the position of DMA buffer counter because we're always reading
3202 * into an intermediate buffer. */
3203 pBDLE->State.u32BufOff += cbData;
3204 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3205
3206 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
3207}
3208
3209#ifdef IN_RING3
3210/**
3211 * Initializes a stream mapping structure according to the given stream configuration.
3212 *
3213 * @return IPRT status code.
3214 * @param pMapping Pointer to mapping to initialize.
3215 * @param pCfg Pointer to stream configuration to use.
3216 */
3217static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg)
3218{
3219 AssertPtrReturn(pMapping, VERR_INVALID_POINTER);
3220 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3221
3222 AssertReturn(pCfg->cChannels, VERR_INVALID_PARAMETER);
3223
3224 hdaStreamMapReset(pMapping);
3225
3226 pMapping->paChannels = (PPDMAUDIOSTREAMCHANNEL)RTMemAlloc(sizeof(PDMAUDIOSTREAMCHANNEL) * pCfg->cChannels);
3227 if (!pMapping->paChannels)
3228 return VERR_NO_MEMORY;
3229
3230 PDMPCMPROPS Props;
3231 int rc = DrvAudioStreamCfgToProps(pCfg, &Props);
3232 if (RT_FAILURE(rc))
3233 return rc;
3234
3235 Assert(RT_IS_POWER_OF_TWO(Props.cBits));
3236
3237 /** @todo We assume all channels in a stream have the same format. */
3238 PPDMAUDIOSTREAMCHANNEL pChan = pMapping->paChannels;
3239 for (uint8_t i = 0; i < pCfg->cChannels; i++)
3240 {
3241 pChan->uChannel = i;
3242 pChan->cbStep = (Props.cBits / 2);
3243 pChan->cbFrame = pChan->cbStep * pCfg->cChannels;
3244 pChan->cbFirst = i * pChan->cbStep;
3245 pChan->cbOff = pChan->cbFirst;
3246
3247 int rc2 = hdaStreamChannelDataInit(&pChan->Data, PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE);
3248 if (RT_SUCCESS(rc))
3249 rc = rc2;
3250
3251 if (RT_FAILURE(rc))
3252 break;
3253
3254 pChan++;
3255 }
3256
3257 if ( RT_SUCCESS(rc)
3258 /* Create circular buffer if not created yet. */
3259 && !pMapping->pCircBuf)
3260 {
3261 rc = RTCircBufCreate(&pMapping->pCircBuf, _4K); /** @todo Make size configurable? */
3262 }
3263
3264 if (RT_SUCCESS(rc))
3265 {
3266 pMapping->cChannels = pCfg->cChannels;
3267#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3268 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_INTERLEAVED;
3269#else
3270 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
3271#endif
3272 }
3273
3274 return rc;
3275}
3276
3277/**
3278 * Destroys a given stream mapping.
3279 *
3280 * @param pMapping Pointer to mapping to destroy.
3281 */
3282static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping)
3283{
3284 hdaStreamMapReset(pMapping);
3285
3286 if (pMapping->pCircBuf)
3287 {
3288 RTCircBufDestroy(pMapping->pCircBuf);
3289 pMapping->pCircBuf = NULL;
3290 }
3291}
3292
3293/**
3294 * Resets a given stream mapping.
3295 *
3296 * @param pMapping Pointer to mapping to reset.
3297 */
3298static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping)
3299{
3300 AssertPtrReturnVoid(pMapping);
3301
3302 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_UNKNOWN;
3303
3304 if (pMapping->cChannels)
3305 {
3306 for (uint8_t i = 0; i < pMapping->cChannels; i++)
3307 hdaStreamChannelDataDestroy(&pMapping->paChannels[i].Data);
3308
3309 AssertPtr(pMapping->paChannels);
3310 RTMemFree(pMapping->paChannels);
3311 pMapping->paChannels = NULL;
3312
3313 pMapping->cChannels = 0;
3314 }
3315}
3316#endif /* IN_RING3 */
3317
3318DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
3319{
3320 AssertPtrReturn(pThis, false);
3321 AssertPtrReturn(pStream, false);
3322
3323 PHDABDLE pBDLE = &pStream->State.BDLE;
3324 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3325
3326 /* Did we reach the CBL (Cyclic Buffer List) limit? */
3327 bool fCBLLimitReached = u32LPIB >= pStream->u32CBL;
3328
3329 /* Do we need to use the next BDLE entry? Either because we reached
3330 * the CBL limit or our internal DMA buffer is full. */
3331 bool fNeedsNextBDLE = ( fCBLLimitReached
3332 || (pBDLE->State.u32BufOff >= pBDLE->u32BufSize));
3333
3334 Assert(u32LPIB <= pStream->u32CBL);
3335 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3336
3337 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
3338 pStream->u8SD, u32LPIB, pStream->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
3339
3340 return fNeedsNextBDLE;
3341}
3342
3343DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbInc)
3344{
3345 AssertPtrReturnVoid(pThis);
3346 AssertPtrReturnVoid(pStream);
3347
3348 LogFlowFunc(("[SD%RU8]: cbInc=%RU32\n", pStream->u8SD, cbInc));
3349
3350 //Assert(cbInc <= pStream->u16FIFOS);
3351
3352 if (!cbInc) /* Nothing to do? Bail out early. */
3353 return;
3354
3355 PHDABDLE pBDLE = &pStream->State.BDLE;
3356
3357 /*
3358 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
3359 * doesn't fetch anything via DMA, so just update LPIB.
3360 * (ICH6 datasheet 18.2.38).
3361 */
3362 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
3363 {
3364 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3365
3366 AssertMsg(((u32LPIB + cbInc) <= pStream->u32CBL),
3367 ("[SD%RU8] Increment (%RU32) exceeds CBL (%RU32): LPIB (%RU32)\n",
3368 pStream->u8SD, cbInc, pStream->u32CBL, u32LPIB));
3369
3370 u32LPIB = RT_MIN(u32LPIB + cbInc, pStream->u32CBL);
3371
3372 LogFlowFunc(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
3373 pStream->u8SD,
3374 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) + cbInc,
3375 pStream->u32CBL));
3376
3377 hdaStreamUpdateLPIB(pThis, pStream, u32LPIB);
3378 }
3379}
3380
3381static bool hdaStreamTransferIsComplete(PHDASTATE pThis, PHDASTREAM pStream, bool *pfInterrupt)
3382{
3383 AssertPtrReturn(pThis, true);
3384 AssertPtrReturn(pStream, true);
3385
3386 bool fInterrupt = false;
3387 bool fIsComplete = false;
3388
3389 PHDABDLE pBDLE = &pStream->State.BDLE;
3390 const uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3391
3392 /* Check if the current BDLE entry is complete (full). */
3393 if (pBDLE->State.u32BufOff >= pBDLE->u32BufSize)
3394 {
3395 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3396
3397 if (/* IOC (Interrupt On Completion) bit set? */
3398 pBDLE->fIntOnCompletion
3399 /* All data put into the DMA FIFO? */
3400 && pBDLE->State.cbBelowFIFOW == 0
3401 )
3402 {
3403 LogFlowFunc(("[SD%RU8]: %R[bdle] => COMPLETE\n", pStream->u8SD, pBDLE));
3404
3405 /*
3406 * If the ICE (IOCE, "Interrupt On Completion Enable") bit of the SDCTL register is set
3407 * we need to generate an interrupt.
3408 */
3409 if (HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
3410 fInterrupt = true;
3411 }
3412
3413 fIsComplete = true;
3414 }
3415
3416 if (pfInterrupt)
3417 *pfInterrupt = fInterrupt;
3418
3419 LogFlowFunc(("[SD%RU8]: u32LPIB=%RU32, CBL=%RU32, fIsComplete=%RTbool, fInterrupt=%RTbool, %R[bdle]\n",
3420 pStream->u8SD, u32LPIB, pStream->u32CBL, fIsComplete, fInterrupt, pBDLE));
3421
3422 return fIsComplete;
3423}
3424
3425/**
3426 * hdaReadAudio - copies samples from audio backend to DMA.
3427 * Note: This function writes to the DMA buffer immediately,
3428 * but "reports bytes" when all conditions are met (FIFOW).
3429 */
3430static int hdaReadAudio(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax, uint32_t *pcbRead)
3431{
3432 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3433 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
3434 /* pcbRead is optional. */
3435
3436 int rc;
3437 uint32_t cbRead = 0;
3438
3439 do
3440 {
3441 PHDABDLE pBDLE = &pStream->State.BDLE;
3442
3443 uint32_t cbBuf = hdaStreamGetTransferSize(pThis, pStream, cbMax);
3444 Log3Func(("cbBuf=%RU32, %R[bdle]\n", cbBuf, pBDLE));
3445
3446 if (!cbBuf)
3447 {
3448 rc = VINF_EOF;
3449 break;
3450 }
3451
3452 AssertPtr(pStream->pMixSink);
3453 AssertPtr(pStream->pMixSink->pMixSink);
3454 rc = AudioMixerSinkRead(pStream->pMixSink->pMixSink, AUDMIXOP_BLEND, pBDLE->State.au8FIFO, cbBuf, &cbRead);
3455 if (RT_FAILURE(rc))
3456 break;
3457
3458 if (!cbRead)
3459 {
3460 rc = VINF_EOF;
3461 break;
3462 }
3463
3464 /* Sanity checks. */
3465 Assert(cbRead <= cbBuf);
3466 Assert(cbRead <= pBDLE->u32BufSize - pBDLE->State.u32BufOff);
3467 //Assert(cbRead <= pStream->u16FIFOS);
3468
3469 /*
3470 * Write to the BDLE's DMA buffer.
3471 */
3472 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
3473 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
3474 pBDLE->State.au8FIFO, cbRead);
3475 AssertRC(rc);
3476
3477 if (pBDLE->State.cbBelowFIFOW + cbRead > hdaStreamGetFIFOW(pThis, pStream))
3478 {
3479 pBDLE->State.u32BufOff += cbRead;
3480 pBDLE->State.cbBelowFIFOW = 0;
3481 //hdaBackendReadTransferReported(pBDLE, cbDMAData, cbRead, &cbRead, pcbAvail);
3482 }
3483 else
3484 {
3485 pBDLE->State.u32BufOff += cbRead;
3486 pBDLE->State.cbBelowFIFOW += cbRead;
3487 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStream));
3488 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbRead, pcbAvail);
3489
3490 rc = VERR_NO_DATA;
3491 }
3492
3493 } while (0);
3494
3495 if (RT_SUCCESS(rc))
3496 {
3497 if (pcbRead)
3498 *pcbRead = cbRead;
3499 }
3500
3501 Log3Func(("Returning cbRead=%RU32, rc=%Rrc\n", cbRead, rc));
3502 return rc;
3503}
3504
3505static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax, uint32_t *pcbWritten)
3506{
3507 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3508 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
3509 AssertPtrReturn(pcbWritten, VERR_INVALID_POINTER);
3510 /* pcbWritten is optional. */
3511
3512 PHDABDLE pBDLE = &pStream->State.BDLE;
3513
3514 uint32_t cbWritten = 0;
3515 uint32_t cbToWrite = hdaStreamGetTransferSize(pThis, pStream, cbMax);
3516
3517 Log3Func(("cbToWrite=%RU32, %R[bdle]\n", cbToWrite, pBDLE));
3518
3519 /*
3520 * Copy from DMA to the corresponding stream buffer (if there are any bytes from the
3521 * previous unreported transfer we write at offset 'pBDLE->State.cbUnderFifoW').
3522 */
3523 int rc;
3524 if (!cbToWrite)
3525 {
3526 rc = VINF_EOF;
3527 }
3528 else
3529 {
3530 void *pvBuf = pBDLE->State.au8FIFO + pBDLE->State.cbBelowFIFOW;
3531 Assert(cbToWrite >= pBDLE->State.cbBelowFIFOW);
3532 uint32_t cbBuf = cbToWrite - pBDLE->State.cbBelowFIFOW;
3533
3534 /*
3535 * Read from the current BDLE's DMA buffer.
3536 */
3537 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3538 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
3539 pvBuf, cbBuf);
3540 AssertRC(rc);
3541#if defined (RT_OS_LINUX) && defined(DEBUG_andy)
3542 RTFILE fh;
3543 RTFileOpen(&fh, "/tmp/hdaWriteAudio-hda.pcm",
3544 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
3545 RTFileWrite(fh, pvBuf, cbBuf, NULL);
3546 RTFileClose(fh);
3547#endif
3548
3549#ifdef VBOX_WITH_STATISTICS
3550 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBuf);
3551#endif
3552 /*
3553 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
3554 */
3555 if (cbBuf >= hdaStreamGetFIFOW(pThis, pStream))
3556 {
3557 PHDASTREAMMAPPING pMapping = &pStream->State.Mapping;
3558
3559 /** @todo Which channel is which? */
3560#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3561 PPDMAUDIOSTREAMCHANNEL pChanFront = &pMapping->paChannels[0];
3562#endif
3563#ifdef VBOX_WITH_HDA_51_SURROUND
3564 PPDMAUDIOSTREAMCHANNEL pChanCenterLFE = &pMapping->paChannels[2]; /** @todo FIX! */
3565 PPDMAUDIOSTREAMCHANNEL pChanRear = &pMapping->paChannels[4]; /** @todo FIX! */
3566#endif
3567 int rc2;
3568
3569 void *pvDataFront = NULL;
3570 size_t cbDataFront;
3571#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3572 rc2 = hdaStreamChannelExtract(pChanFront, pvBuf, cbBuf);
3573 AssertRC(rc2);
3574
3575 rc2 = hdaStreamChannelAcquireData(&pChanFront->Data, pvDataFront, &cbDataFront);
3576 AssertRC(rc2);
3577#else
3578 /* Use stuff in the whole FIFO to use for the channel data. */
3579 pvDataFront = pvBuf;
3580 cbDataFront = cbBuf;
3581#endif
3582#ifdef VBOX_WITH_HDA_51_SURROUND
3583 void *pvDataCenterLFE;
3584 size_t cbDataCenterLFE;
3585 rc2 = hdaStreamChannelExtract(pChanCenterLFE, pvBuf, cbBuf);
3586 AssertRC(rc2);
3587
3588 rc2 = hdaStreamChannelAcquireData(&pChanCenterLFE->Data, pvDataCenterLFE, &cbDataCenterLFE);
3589 AssertRC(rc2);
3590
3591 void *pvDataRear;
3592 size_t cbDataRear;
3593 rc2 = hdaStreamChannelExtract(pChanRear, pvBuf, cbBuf);
3594 AssertRC(rc2);
3595
3596 rc2 = hdaStreamChannelAcquireData(&pChanRear->Data, pvDataRear, &cbDataRear);
3597 AssertRC(rc2);
3598#endif
3599 /*
3600 * Write data to according mixer sinks.
3601 */
3602 rc2 = AudioMixerSinkWrite(pThis->SinkFront.pMixSink, AUDMIXOP_COPY, pvDataFront, cbDataFront,
3603 NULL /* pcbWritten */);
3604 AssertRC(rc2);
3605#ifdef VBOX_WITH_HDA_51_SURROUND
3606 rc2 = AudioMixerSinkWrite(pThis->SinkCenterLFE, AUDMIXOP_COPY, pvDataCenterLFE, cbDataCenterLFE,
3607 NULL /* pcbWritten */);
3608 AssertRC(rc2);
3609 rc2 = AudioMixerSinkWrite(pThis->SinkRear, AUDMIXOP_COPY, pvDataRear, cbDataRear,
3610 NULL /* pcbWritten */);
3611 AssertRC(rc2);
3612#endif
3613
3614#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3615 hdaStreamChannelReleaseData(&pChanFront->Data);
3616#endif
3617#ifdef VBOX_WITH_HDA_51_SURROUND
3618 hdaStreamChannelReleaseData(&pChanCenterLFE->Data);
3619 hdaStreamChannelReleaseData(&pChanRear->Data);
3620#endif
3621
3622 /* Always report all data as being written;
3623 * backends who were not able to catch up have to deal with it themselves. */
3624 cbWritten = cbToWrite;
3625
3626 hdaBDLEUpdate(pBDLE, cbToWrite, cbWritten);
3627 }
3628 else
3629 {
3630 pBDLE->State.u32BufOff += cbWritten;
3631 pBDLE->State.cbBelowFIFOW += cbWritten;
3632 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStream));
3633
3634 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
3635 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbAvail, NULL);
3636 rc = VINF_EOF;
3637 }
3638 }
3639
3640 //Assert(cbWritten <= pStream->u16FIFOS);
3641
3642 if (RT_SUCCESS(rc))
3643 {
3644 if (pcbWritten)
3645 *pcbWritten = cbWritten;
3646 }
3647
3648 Log3Func(("Returning cbMax=%RU32, cbWritten=%RU32, rc=%Rrc\n", cbMax, cbWritten, rc));
3649 return rc;
3650}
3651
3652/**
3653 * @interface_method_impl{HDACODEC,pfnReset}
3654 */
3655static DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
3656{
3657 PHDASTATE pThis = pCodec->pHDAState;
3658 NOREF(pThis);
3659 return VINF_SUCCESS;
3660}
3661
3662/**
3663 * Retrieves a corresponding sink for a given mixer control.
3664 * Returns NULL if no sink is found.
3665 *
3666 * @return PHDAMIXERSINK
3667 * @param pThis HDA state.
3668 * @param enmMixerCtl Mixer control to get the corresponding sink for.
3669 */
3670static PHDAMIXERSINK hdaMixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3671{
3672 PHDAMIXERSINK pSink;
3673
3674 switch (enmMixerCtl)
3675 {
3676 case PDMAUDIOMIXERCTL_VOLUME:
3677 /* Fall through is intentional. */
3678 case PDMAUDIOMIXERCTL_FRONT:
3679 pSink = &pThis->SinkFront;
3680 break;
3681#ifdef VBOX_WITH_HDA_51_SURROUND
3682 case PDMAUDIOMIXERCTL_CENTER_LFE:
3683 pSink = &pThis->SinkCenterLFE;
3684 break;
3685 case PDMAUDIOMIXERCTL_REAR:
3686 pSink = &pThis->SinkRear;
3687 break;
3688#endif
3689 case PDMAUDIOMIXERCTL_LINE_IN:
3690 pSink = &pThis->SinkLineIn;
3691 break;
3692#ifdef VBOX_WITH_HDA_MIC_IN
3693 case PDMAUDIOMIXERCTL_MIC_IN:
3694 pSink = &pThis->SinkMicIn;
3695 break;
3696#endif
3697 default:
3698 pSink = NULL;
3699 AssertMsgFailed(("Unhandled mixer control\n"));
3700 break;
3701 }
3702
3703 return pSink;
3704}
3705
3706static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PHDAMIXERSINK pSink, PPDMAUDIOSTREAMCFG pCfg)
3707{
3708 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3709 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
3710 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3711
3712 LogFunc(("Sink=%s, Stream=%s\n", pSink->pMixSink->pszName, pCfg->szName));
3713
3714 /* Update the sink's format. */
3715 PDMPCMPROPS PCMProps;
3716 int rc = DrvAudioStreamCfgToProps(pCfg, &PCMProps);
3717 if (RT_SUCCESS(rc))
3718 rc = AudioMixerSinkSetFormat(pSink->pMixSink, &PCMProps);
3719
3720 if (RT_FAILURE(rc))
3721 return rc;
3722
3723 PHDADRIVER pDrv;
3724 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3725 {
3726 int rc2 = VINF_SUCCESS;
3727 PHDAMIXERSTREAM pStream;
3728
3729 if (pCfg->enmDir == PDMAUDIODIR_IN)
3730 {
3731 switch (pCfg->DestSource.Source)
3732 {
3733 case PDMAUDIORECSOURCE_LINE:
3734 pStream = &pDrv->LineIn;
3735 break;
3736#ifdef VBOX_WITH_HDA_MIC_IN
3737 case PDMAUDIORECSOURCE_MIC:
3738 pStream = &pDrv->MicIn;
3739 break;
3740#endif
3741 default:
3742 rc2 = VERR_NOT_SUPPORTED;
3743 break;
3744 }
3745 }
3746 else if (pCfg->enmDir == PDMAUDIODIR_OUT)
3747 {
3748 switch (pCfg->DestSource.Dest)
3749 {
3750 case PDMAUDIOPLAYBACKDEST_FRONT:
3751 pStream = &pDrv->Front;
3752 break;
3753#ifdef VBOX_WITH_HDA_51_SURROUND
3754 case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
3755 pStream = &pDrv->CenterLFE;
3756 break;
3757 case PDMAUDIOPLAYBACKDEST_REAR:
3758 pStream = &pDrv->Rear;
3759 break;
3760#endif
3761 default:
3762 rc2 = VERR_NOT_SUPPORTED;
3763 break;
3764 }
3765 }
3766 else
3767 rc2 = VERR_NOT_SUPPORTED;
3768
3769 if (RT_SUCCESS(rc2))
3770 {
3771 AudioMixerSinkRemoveStream(pSink->pMixSink, pStream->pMixStrm);
3772
3773 AudioMixerStreamDestroy(pStream->pMixStrm);
3774 pStream->pMixStrm = NULL;
3775
3776 PAUDMIXSTREAM pMixStrm;
3777 rc2 = AudioMixerCreateStream(pThis->pMixer, pDrv->pConnector, pCfg, 0 /* fFlags */, &pMixStrm);
3778 if (RT_SUCCESS(rc2))
3779 {
3780 rc2 = AudioMixerSinkAddStream(pSink->pMixSink, pMixStrm);
3781 LogFlowFunc(("LUN#%RU8: Added \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pCfg->szName , rc2));
3782 }
3783
3784 if (RT_SUCCESS(rc2))
3785 pStream->pMixStrm = pMixStrm;
3786 }
3787
3788 if (RT_SUCCESS(rc))
3789 rc = rc2;
3790 }
3791
3792 LogFlowFuncLeaveRC(rc);
3793 return rc;
3794}
3795
3796/**
3797 * Adds a new audio stream to a specific mixer control.
3798 * Depending on the mixer control the stream then gets assigned to one of the internal
3799 * mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
3800 *
3801 * @return IPRT status code.
3802 * @param pThis HDA state.
3803 * @param enmMixerCtl Mixer control to assign new stream to.
3804 * @param pCfg Stream configuration for the new stream.
3805 */
3806static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
3807{
3808 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3809 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3810
3811 int rc;
3812
3813 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3814 if (pSink)
3815 {
3816 rc = hdaMixerAddStream(pThis, pSink, pCfg);
3817
3818 AssertPtr(pSink->pMixSink);
3819 LogFlowFunc(("Sink=%s, enmMixerCtl=%ld\n", pSink->pMixSink->pszName, enmMixerCtl));
3820 }
3821 else
3822 rc = VERR_NOT_FOUND;
3823
3824 LogFlowFuncLeaveRC(rc);
3825 return rc;
3826}
3827
3828/**
3829 * Removes a specified mixer control from the HDA's mixer.
3830 *
3831 * @return IPRT status code.
3832 * @param pThis HDA state.
3833 * @param enmMixerCtl Mixer control to remove.
3834 */
3835static DECLCALLBACK(int) hdaMixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3836{
3837 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3838
3839 int rc;
3840
3841 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3842 if (pSink)
3843 {
3844 PHDADRIVER pDrv;
3845 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3846 {
3847 PAUDMIXSTREAM pMixStream = NULL;
3848 switch (enmMixerCtl)
3849 {
3850 /*
3851 * Input.
3852 */
3853 case PDMAUDIOMIXERCTL_LINE_IN:
3854 pMixStream = pDrv->LineIn.pMixStrm;
3855 pDrv->LineIn.pMixStrm = NULL;
3856 break;
3857#ifdef VBOX_WITH_HDA_MIC_IN
3858 case PDMAUDIOMIXERCTL_MIC_IN:
3859 pMixStream = pDrv->MicIn.pMixStrm;
3860 pDrv->MicIn.pMixStrm = NULL;
3861 break;
3862#endif
3863 /*
3864 * Output.
3865 */
3866 case PDMAUDIOMIXERCTL_FRONT:
3867 pMixStream = pDrv->Front.pMixStrm;
3868 pDrv->Front.pMixStrm = NULL;
3869 break;
3870#ifdef VBOX_WITH_HDA_51_SURROUND
3871 case PDMAUDIOMIXERCTL_CENTER_LFE:
3872 pMixStream = pDrv->CenterLFE.pMixStrm;
3873 pDrv->CenterLFE.pMixStrm = NULL;
3874 break;
3875 case PDMAUDIOMIXERCTL_REAR:
3876 pMixStream = pDrv->Rear.pMixStrm;
3877 pDrv->Rear.pMixStrm = NULL;
3878 break;
3879#endif
3880 default:
3881 AssertMsgFailed(("Mixer control %ld not implemented\n", enmMixerCtl));
3882 break;
3883 }
3884
3885 if (pMixStream)
3886 {
3887 AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
3888 AudioMixerStreamDestroy(pMixStream);
3889 }
3890 }
3891
3892 AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
3893 rc = VINF_SUCCESS;
3894 }
3895 else
3896 rc = VERR_NOT_FOUND;
3897
3898 LogFlowFunc(("enmMixerCtl=%ld, rc=%Rrc\n", enmMixerCtl, rc));
3899 return rc;
3900}
3901
3902/**
3903 * Sets a SDn stream number and channel to a particular mixer control.
3904 *
3905 * @returns IPRT status code.
3906 * @param pThis HDA State.
3907 * @param enmMixerCtl Mixer control to set SD stream number and channel for.
3908 * @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
3909 * @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
3910 */
3911static DECLCALLBACK(int) hdaMixerSetStream(PHDASTATE pThis,
3912 PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
3913{
3914 LogFlowFunc(("enmMixerCtl=%RU32, uSD=%RU8, uChannel=%RU8\n", enmMixerCtl, uSD, uChannel));
3915
3916 if (uSD == 0) /* Stream number 0 is reserved. */
3917 {
3918 LogFlowFunc(("Invalid SDn (%RU8) number for mixer control %ld, ignoring\n", uSD, enmMixerCtl));
3919 return VINF_SUCCESS;
3920 }
3921 /* uChannel is optional. */
3922
3923 /* SDn0 starts as 1. */
3924 Assert(uSD);
3925 uSD--;
3926
3927 int rc;
3928
3929 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3930 if (pSink)
3931 {
3932 if ( (uSD < HDA_MAX_SDI)
3933 && AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
3934 {
3935 uSD += HDA_MAX_SDI;
3936 }
3937
3938 LogFlowFunc(("%s: Setting to stream ID=%RU8, channel=%RU8, enmMixerCtl=%RU32\n",
3939 pSink->pMixSink->pszName, uSD, uChannel, enmMixerCtl));
3940
3941 Assert(uSD < HDA_MAX_STREAMS);
3942
3943 PHDASTREAM pStream = hdaStreamFromSD(pThis, pSink->uSD);
3944 if (pStream)
3945 {
3946 pSink->uSD = uSD;
3947 pSink->uChannel = uChannel;
3948
3949 /* Make sure that the stream also has this sink set. */
3950 hdaStreamAssignToSink(pStream, pSink);
3951
3952 rc = VINF_SUCCESS;
3953 }
3954 else
3955 {
3956 LogRel(("HDA: Guest wanted to assign invalid stream ID=%RU8 (channel %RU8) to mixer control %RU32, skipping\n",
3957 uSD, uChannel, enmMixerCtl));
3958 rc = VERR_INVALID_PARAMETER;
3959 }
3960 }
3961 else
3962 rc = VERR_NOT_FOUND;
3963
3964 LogFlowFuncLeaveRC(rc);
3965 return rc;
3966}
3967
3968/**
3969 * Sets the volume of a specified mixer control.
3970 *
3971 * @return IPRT status code.
3972 * @param pThis HDA State.
3973 * @param enmMixerCtl Mixer control to set volume for.
3974 * @param pVol Pointer to volume data to set.
3975 */
3976static DECLCALLBACK(int) hdaMixerSetVolume(PHDASTATE pThis,
3977 PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
3978{
3979 int rc;
3980
3981 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3982 if (pSink)
3983 {
3984 /* Set the volume.
3985 * We assume that the codec already converted it to the correct range. */
3986 rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
3987 }
3988 else
3989 rc = VERR_NOT_FOUND;
3990
3991 LogFlowFuncLeaveRC(rc);
3992 return rc;
3993}
3994
3995#ifndef VBOX_WITH_AUDIO_CALLBACKS
3996
3997static void hdaTimerMaybeStart(PHDASTATE pThis)
3998{
3999 LogFlowFunc(("cStreamsActive=%RU8\n", pThis->cStreamsActive));
4000
4001 if (pThis->cStreamsActive == 0) /* Only start the timer if there are no active streams. */
4002 return;
4003
4004 if (!pThis->pTimer)
4005 return;
4006
4007 LogFlowFuncEnter();
4008
4009 /* Set timer flag. */
4010 ASMAtomicXchgBool(&pThis->fTimerActive, true);
4011
4012 /* Update current time timestamp. */
4013 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
4014
4015 /* Fire off timer. */
4016 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
4017}
4018
4019static void hdaTimerMaybeStop(PHDASTATE pThis)
4020{
4021 LogFlowFunc(("cStreamsActive=%RU8\n", pThis->cStreamsActive));
4022
4023 if (pThis->cStreamsActive) /* Some streams still active? Bail out. */
4024 return;
4025
4026 if (!pThis->pTimer)
4027 return;
4028
4029 LogFlowFuncEnter();
4030
4031 /* Set timer flag. */
4032 ASMAtomicXchgBool(&pThis->fTimerActive, false);
4033}
4034
4035static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
4036{
4037 PHDASTATE pThis = (PHDASTATE)pvUser;
4038 Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
4039 AssertPtr(pThis);
4040
4041 STAM_PROFILE_START(&pThis->StatTimer, a);
4042
4043 uint32_t cbInMax = 0;
4044 uint32_t cbOutMin = UINT32_MAX;
4045
4046 uint64_t cTicksNow = TMTimerGet(pTimer);
4047 uint64_t cTicksElapsed = cTicksNow - pThis->uTimerTS;
4048
4049 /* Update current time timestamp. */
4050 pThis->uTimerTS = cTicksNow;
4051
4052 PHDASTREAM pStreamLineIn = hdaGetStreamFromSink(pThis, &pThis->SinkLineIn);
4053#ifdef VBOX_WITH_HDA_MIC_IN
4054 PHDASTREAM pStreamMicIn = hdaGetStreamFromSink(pThis, &pThis->SinkMicIn);
4055#endif
4056 PHDASTREAM pStreamFront = hdaGetStreamFromSink(pThis, &pThis->SinkFront);
4057#ifdef VBOX_WITH_HDA_51_SURROUND
4058 /** @todo See note below. */
4059#endif
4060
4061 uint32_t cbLineIn;
4062 AudioMixerSinkTimerUpdate(pThis->SinkLineIn.pMixSink, pThis->cTimerTicks, cTicksElapsed, &cbLineIn);
4063 if (cbLineIn)
4064 hdaTransfer(pThis, pStreamLineIn, cbLineIn, NULL); /** @todo Add rc! */
4065
4066#ifdef VBOX_WITH_HDA_MIC_IN
4067 uint32_t cbMicIn;
4068 AudioMixerSinkTimerUpdate(pThis->SinkMicIn.pMixSink , pThis->cTimerTicks, cTicksElapsed, &cbMicIn);
4069#endif
4070
4071 uint32_t cbFront;
4072 AudioMixerSinkTimerUpdate(pThis->SinkFront.pMixSink, pThis->cTimerTicks, cTicksElapsed, &cbFront);
4073#ifdef VBOX_WITH_HDA_51_SURROUND
4074 uint32_t cbCenterLFE;
4075 AudioMixerSinkTimerUpdate(pThis->SinkCenterLFE.pMixSink, pThis->cTimerTicks, cTicksElapsed, &cbCenterLFE);
4076 uint32_t cbRear;
4077 AudioMixerSinkTimerUpdate(pThis->SinkRear.pMixSink, pThis->cTimerTicks, cTicksElapsed, &cbRear);
4078#endif
4079
4080 if (cbFront)
4081 hdaTransfer(pThis, pStreamFront, cbFront, NULL); /** @todo Add rc! */
4082#ifdef VBOX_WITH_HDA_51_SURROUND
4083 /*
4084 * Only call hdaTransfer if CenterLFE and/or Rear are on different SDs,
4085 * otherwise we have to use the interleaved streams support for getting the data
4086 * out of the Front sink (depending on the mapping layout).
4087 */
4088#endif
4089
4090 if ( ASMAtomicReadBool(&pThis->fTimerActive)
4091 || AudioMixerSinkHasData(pThis->SinkFront.pMixSink)
4092#ifdef VBOX_WITH_HDA_51_SURROUND
4093 || AudioMixerSinkHasData(pThis->SinkCenterLFE.pMixSink)
4094 || AudioMixerSinkHasData(pThis->SinkRear.pMixSink)
4095#endif
4096 || AudioMixerSinkHasData(pThis->SinkLineIn.pMixSink))
4097 {
4098 /* Kick the timer again. */
4099 uint64_t cTicks = pThis->cTimerTicks;
4100 /** @todo adjust cTicks down by now much cbOutMin represents. */
4101 TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
4102 }
4103
4104 STAM_PROFILE_STOP(&pThis->StatTimer, a);
4105}
4106
4107#else /* VBOX_WITH_AUDIO_CALLBACKS */
4108
4109static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4110{
4111 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
4112 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4113 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4114 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4115 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4116
4117 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4118 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4119
4120 PPDMAUDIOCALLBACKDATAIN pData = (PPDMAUDIOCALLBACKDATAIN)pvUser;
4121 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAIN), VERR_INVALID_PARAMETER);
4122
4123 return hdaTransfer(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
4124}
4125
4126static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4127{
4128 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
4129 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4130 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4131 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4132 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4133
4134 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4135 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4136
4137 PPDMAUDIOCALLBACKDATAOUT pData = (PPDMAUDIOCALLBACKDATAOUT)pvUser;
4138 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAOUT), VERR_INVALID_PARAMETER);
4139
4140 PHDASTATE pThis = pCtx->pThis;
4141
4142 int rc = hdaTransfer(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
4143 if ( RT_SUCCESS(rc)
4144 && pData->cbOutWritten)
4145 {
4146 PHDADRIVER pDrv;
4147 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4148 {
4149 uint32_t cSamplesPlayed;
4150 int rc2 = pDrv->pConnector->pfnPlay(pDrv->pConnector, &cSamplesPlayed);
4151 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
4152 }
4153 }
4154}
4155#endif /* VBOX_WITH_AUDIO_CALLBACKS */
4156
4157static int hdaTransfer(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToProcess, uint32_t *pcbProcessed)
4158{
4159 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4160 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4161 /* pcbProcessed is optional. */
4162
4163 if (ASMAtomicReadBool(&pThis->fInReset)) /* HDA controller in reset mode? Bail out. */
4164 {
4165 LogFlowFunc(("In reset mode, skipping\n"));
4166
4167 if (pcbProcessed)
4168 *pcbProcessed = 0;
4169 return VINF_SUCCESS;
4170 }
4171
4172 bool fProceed = true;
4173 int rc = RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
4174 if (RT_FAILURE(rc))
4175 return rc;
4176
4177 /* Stop request received? */
4178 if (pStream->State.fDoStop)
4179 {
4180 pStream->State.fActive = false;
4181
4182 rc = RTSemEventSignal(pStream->State.hStateChangedEvent);
4183 AssertRC(rc);
4184
4185 fProceed = false;
4186 }
4187 /* Is the stream not in a running state currently? */
4188 else if (!(HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)))
4189 fProceed = false;
4190 /* Nothing to process? */
4191 else if (!cbToProcess)
4192 fProceed = false;
4193
4194 if ((HDA_STREAM_REG(pThis, STS, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
4195 {
4196 Log3Func(("[SD%RU8]: BCIS set\n", pStream->u8SD));
4197 fProceed = false;
4198 }
4199
4200 if (!fProceed)
4201 {
4202 Log3Func(("[SD%RU8] Skipping\n", pStream->u8SD));
4203
4204 rc = RTSemMutexRelease(pStream->State.hMtx);
4205 AssertRC(rc);
4206
4207 if (pcbProcessed)
4208 *pcbProcessed = 0;
4209 return VINF_SUCCESS;
4210 }
4211
4212 /* Sanity checks. */
4213 Assert(pStream->u8SD <= HDA_MAX_STREAMS);
4214 Assert(pStream->u64BDLBase);
4215 Assert(pStream->u32CBL);
4216
4217 /* State sanity checks. */
4218 Assert(pStream->State.fInReset == false);
4219
4220 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
4221 Assert(u32LPIB <= pStream->u32CBL);
4222
4223 uint32_t cbLeft = cbToProcess;
4224 uint32_t cbTotal = 0;
4225
4226 bool fInterrupt = false;
4227
4228 Log3Func(("cbLeft=%RU32\n", cbLeft));
4229
4230#define FOO
4231
4232#ifdef FOO
4233 uint8_t u8FIFO[_16K+1];
4234 size_t u8FIFOff = 0;
4235#endif
4236
4237 /* Set the FIFORDY bit on the stream while doing the transfer. */
4238 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
4239
4240 while (cbLeft)
4241 {
4242 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
4243 if (hdaStreamNeedsNextBDLE(pThis, pStream))
4244 {
4245 rc = hdaStreamGetNextBDLE(pThis, pStream);
4246 if (RT_FAILURE(rc))
4247 break;
4248 }
4249
4250 uint32_t cbProcessed = 0;
4251 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
4252 rc = hdaReadAudio (pThis, pStream, cbLeft, &cbProcessed);
4253 else
4254 {
4255#ifndef FOO
4256 rc = hdaWriteAudio(pThis, pStream, cbLeft, &cbProcessed);
4257#else
4258 uint32_t cbToWrite = hdaStreamGetTransferSize(pThis, pStream, cbLeft);
4259
4260 void *pvBuf = u8FIFO + u8FIFOff;
4261 int32_t cbBuf = cbToWrite;
4262
4263 PHDABDLE pBDLE = &pStream->State.BDLE;
4264
4265 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
4266 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
4267 pvBuf, cbBuf);
4268
4269 hdaBDLEUpdate(pBDLE, cbToWrite, cbToWrite);
4270
4271 LogFlowFunc(("u8FIFOff=%zu, cbLeft=%RU32, cbToWrite=%RU32\n", u8FIFOff, cbLeft, cbToWrite));
4272
4273 u8FIFOff += cbToWrite;
4274 Assert(u8FIFOff <= sizeof(u8FIFO));
4275
4276 cbProcessed = cbToWrite;
4277#endif
4278 }
4279
4280 if (RT_FAILURE(rc))
4281 break;
4282
4283 hdaStreamTransferUpdate(pThis, pStream, cbProcessed);
4284
4285 Assert(cbLeft >= cbProcessed);
4286 cbLeft -= cbProcessed;
4287 cbTotal += cbProcessed;
4288
4289 LogFlowFunc(("cbProcessed=%RU32, cbLeft=%RU32, cbTotal=%RU32, rc=%Rrc\n",
4290 cbProcessed, cbLeft, cbTotal, rc));
4291
4292 if (rc == VINF_EOF)
4293 break;
4294
4295 if (hdaStreamTransferIsComplete(pThis, pStream, &fInterrupt))
4296 break;
4297 }
4298
4299 /* Remove the FIFORDY bit again. */
4300 HDA_STREAM_REG(pThis, STS, pStream->u8SD) &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
4301
4302#ifdef FOO
4303 #if defined (RT_OS_LINUX) && defined(DEBUG_andy)
4304 RTFILE fh;
4305 RTFileOpen(&fh, "/tmp/hdaWriteAudio.pcm",
4306 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4307 RTFileWrite(fh, u8FIFO, u8FIFOff, NULL);
4308 RTFileClose(fh);
4309 #endif
4310#if 1
4311 AudioMixerSinkWrite(pThis->SinkFront.pMixSink, AUDMIXOP_COPY, u8FIFO, u8FIFOff,
4312 NULL /* pcbWritten */);
4313#endif
4314#endif
4315
4316#ifdef FOO
4317 if (fInterrupt)
4318 {
4319 /**
4320 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
4321 * last byte of data for the current descriptor has been fetched
4322 * from memory and put into the DMA FIFO.
4323 *
4324 * Speech synthesis works fine on Mac Guest if this bit isn't set
4325 * but in general sound quality gets worse.
4326 *
4327 * This must be set in *any* case.
4328 */
4329 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
4330 Log3Func(("[SD%RU8]: BCIS: Set\n", pStream->u8SD));
4331
4332 hdaProcessInterrupt(pThis);
4333 }
4334#endif
4335
4336 Log3Func(("Written %RU32 / %RU32 (left: %RU32), rc=%Rrc\n", cbTotal, cbToProcess, cbLeft, rc));
4337
4338 if (RT_SUCCESS(rc))
4339 {
4340 if (pcbProcessed)
4341 *pcbProcessed = cbTotal;
4342 }
4343
4344 int rc2 = RTSemMutexRelease(pStream->State.hMtx);
4345 if (RT_SUCCESS(rc))
4346 rc = rc2;
4347
4348 return rc;
4349}
4350#endif /* IN_RING3 */
4351
4352/* MMIO callbacks */
4353
4354/**
4355 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
4356 *
4357 * @note During implementation, we discovered so-called "forgotten" or "hole"
4358 * registers whose description is not listed in the RPM, datasheet, or
4359 * spec.
4360 */
4361PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4362{
4363 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4364 int rc;
4365
4366 /*
4367 * Look up and log.
4368 */
4369 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4370 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
4371#ifdef LOG_ENABLED
4372 unsigned const cbLog = cb;
4373 uint32_t offRegLog = offReg;
4374#endif
4375
4376 Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
4377 Assert(cb == 4); Assert((offReg & 3) == 0);
4378
4379 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4380 LogFunc(("Access to registers except GCTL is blocked while reset\n"));
4381
4382 if (idxRegDsc == -1)
4383 LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
4384
4385 if (idxRegDsc != -1)
4386 {
4387 /* ASSUMES gapless DWORD at end of map. */
4388 if (g_aHdaRegMap[idxRegDsc].size == 4)
4389 {
4390 /*
4391 * Straight forward DWORD access.
4392 */
4393 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
4394 Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
4395 }
4396 else
4397 {
4398 /*
4399 * Multi register read (unless there are trailing gaps).
4400 * ASSUMES that only DWORD reads have sideeffects.
4401 */
4402 uint32_t u32Value = 0;
4403 unsigned cbLeft = 4;
4404 do
4405 {
4406 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
4407 uint32_t u32Tmp = 0;
4408
4409 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
4410 Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
4411 if (rc != VINF_SUCCESS)
4412 break;
4413 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
4414
4415 cbLeft -= cbReg;
4416 offReg += cbReg;
4417 idxRegDsc++;
4418 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
4419
4420 if (rc == VINF_SUCCESS)
4421 *(uint32_t *)pv = u32Value;
4422 else
4423 Assert(!IOM_SUCCESS(rc));
4424 }
4425 }
4426 else
4427 {
4428 rc = VINF_IOM_MMIO_UNUSED_FF;
4429 Log3Func(("\tHole at %x is accessed for read\n", offReg));
4430 }
4431
4432 /*
4433 * Log the outcome.
4434 */
4435#ifdef LOG_ENABLED
4436 if (cbLog == 4)
4437 Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
4438 else if (cbLog == 2)
4439 Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
4440 else if (cbLog == 1)
4441 Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
4442#endif
4443 return rc;
4444}
4445
4446
4447DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
4448{
4449 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4450 {
4451 LogRel2(("HDA: Warning: Access to register 0x%x is blocked while reset\n", idxRegDsc));
4452 return VINF_SUCCESS;
4453 }
4454
4455 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4456#ifdef LOG_ENABLED
4457 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
4458#endif
4459 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
4460 Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
4461 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
4462 return rc;
4463}
4464
4465
4466/**
4467 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
4468 */
4469PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
4470{
4471 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4472 int rc;
4473
4474 /*
4475 * The behavior of accesses that aren't aligned on natural boundraries is
4476 * undefined. Just reject them outright.
4477 */
4478 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
4479 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
4480 if (GCPhysAddr & (cb - 1))
4481 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
4482
4483 /*
4484 * Look up and log the access.
4485 */
4486 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4487 int idxRegDsc = hdaRegLookup(pThis, offReg);
4488 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
4489 uint64_t u64Value;
4490 if (cb == 4) u64Value = *(uint32_t const *)pv;
4491 else if (cb == 2) u64Value = *(uint16_t const *)pv;
4492 else if (cb == 1) u64Value = *(uint8_t const *)pv;
4493 else if (cb == 8) u64Value = *(uint64_t const *)pv;
4494 else
4495 {
4496 u64Value = 0; /* shut up gcc. */
4497 AssertReleaseMsgFailed(("%u\n", cb));
4498 }
4499
4500#ifdef LOG_ENABLED
4501 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
4502 if (idxRegDsc == -1)
4503 Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
4504 else if (cb == 4)
4505 Log3Func(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4506 else if (cb == 2)
4507 Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4508 else if (cb == 1)
4509 Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4510
4511 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
4512 Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
4513#endif
4514
4515 /*
4516 * Try for a direct hit first.
4517 */
4518 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
4519 {
4520 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
4521 Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
4522 }
4523 /*
4524 * Partial or multiple register access, loop thru the requested memory.
4525 */
4526 else
4527 {
4528 /*
4529 * If it's an access beyond the start of the register, shift the input
4530 * value and fill in missing bits. Natural alignment rules means we
4531 * will only see 1 or 2 byte accesses of this kind, so no risk of
4532 * shifting out input values.
4533 */
4534 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
4535 {
4536 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
4537 offReg -= cbBefore;
4538 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4539 u64Value <<= cbBefore * 8;
4540 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
4541 Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
4542 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
4543 }
4544
4545 /* Loop thru the write area, it may cover multiple registers. */
4546 rc = VINF_SUCCESS;
4547 for (;;)
4548 {
4549 uint32_t cbReg;
4550 if (idxRegDsc != -1)
4551 {
4552 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4553 cbReg = g_aHdaRegMap[idxRegDsc].size;
4554 if (cb < cbReg)
4555 {
4556 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
4557 Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
4558 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
4559 }
4560 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
4561 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
4562 Log3Func(("\t%#x -> %#x\n", u32LogOldVal, pThis->au32Regs[idxRegMem]));
4563 }
4564 else
4565 {
4566 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
4567 cbReg = 1;
4568 }
4569 if (rc != VINF_SUCCESS)
4570 break;
4571 if (cbReg >= cb)
4572 break;
4573
4574 /* Advance. */
4575 offReg += cbReg;
4576 cb -= cbReg;
4577 u64Value >>= cbReg * 8;
4578 if (idxRegDsc == -1)
4579 idxRegDsc = hdaRegLookup(pThis, offReg);
4580 else
4581 {
4582 idxRegDsc++;
4583 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
4584 || g_aHdaRegMap[idxRegDsc].offset != offReg)
4585 {
4586 idxRegDsc = -1;
4587 }
4588 }
4589 }
4590 }
4591
4592 return rc;
4593}
4594
4595
4596/* PCI callback. */
4597
4598#ifdef IN_RING3
4599/**
4600 * @callback_method_impl{FNPCIIOREGIONMAP}
4601 */
4602static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
4603 PCIADDRESSSPACE enmType)
4604{
4605 PPDMDEVINS pDevIns = pPciDev->pDevIns;
4606 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
4607 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
4608 int rc;
4609
4610 /*
4611 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
4612 *
4613 * Let IOM talk DWORDs when reading, saves a lot of complications. On
4614 * writing though, we have to do it all ourselves because of sideeffects.
4615 */
4616 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
4617 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
4618 IOMMMIO_FLAGS_READ_DWORD
4619 | IOMMMIO_FLAGS_WRITE_PASSTHRU,
4620 hdaMMIOWrite, hdaMMIORead, "HDA");
4621
4622 if (RT_FAILURE(rc))
4623 return rc;
4624
4625 if (pThis->fR0Enabled)
4626 {
4627 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
4628 "hdaMMIOWrite", "hdaMMIORead");
4629 if (RT_FAILURE(rc))
4630 return rc;
4631 }
4632
4633 if (pThis->fRCEnabled)
4634 {
4635 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
4636 "hdaMMIOWrite", "hdaMMIORead");
4637 if (RT_FAILURE(rc))
4638 return rc;
4639 }
4640
4641 pThis->MMIOBaseAddr = GCPhysAddress;
4642 return VINF_SUCCESS;
4643}
4644
4645
4646/* Saved state callbacks. */
4647
4648static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
4649{
4650 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4651
4652 LogFlowFunc(("[SD%RU8]\n", pStrm->u8SD));
4653
4654 /* Save stream ID. */
4655 int rc = SSMR3PutU8(pSSM, pStrm->u8SD);
4656 AssertRCReturn(rc, rc);
4657 Assert(pStrm->u8SD <= HDA_MAX_STREAMS);
4658
4659 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields6, NULL);
4660 AssertRCReturn(rc, rc);
4661
4662#ifdef DEBUG /* Sanity checks. */
4663 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrm->u8SD),
4664 HDA_STREAM_REG(pThis, BDPU, pStrm->u8SD));
4665 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStrm->u8SD);
4666 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStrm->u8SD);
4667
4668 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
4669
4670 Assert(u64BaseDMA == pStrm->u64BDLBase);
4671 Assert(u16LVI == pStrm->u16LVI);
4672 Assert(u32CBL == pStrm->u32CBL);
4673#endif
4674
4675 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
4676 0 /*fFlags*/, g_aSSMBDLEFields6, NULL);
4677 AssertRCReturn(rc, rc);
4678
4679 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
4680 0 /*fFlags*/, g_aSSMBDLEStateFields6, NULL);
4681 AssertRCReturn(rc, rc);
4682
4683#ifdef DEBUG /* Sanity checks. */
4684 PHDABDLE pBDLE = &pStrm->State.BDLE;
4685 if (u64BaseDMA)
4686 {
4687 Assert(pStrm->State.uCurBDLE <= u16LVI + 1);
4688
4689 HDABDLE curBDLE;
4690 rc = hdaBDLEFetch(pThis, &curBDLE, u64BaseDMA, pStrm->State.uCurBDLE);
4691 AssertRC(rc);
4692
4693 Assert(curBDLE.u32BufSize == pBDLE->u32BufSize);
4694 Assert(curBDLE.u64BufAdr == pBDLE->u64BufAdr);
4695 Assert(curBDLE.fIntOnCompletion == pBDLE->fIntOnCompletion);
4696 }
4697 else
4698 {
4699 Assert(pBDLE->u64BufAdr == 0);
4700 Assert(pBDLE->u32BufSize == 0);
4701 }
4702#endif
4703 return rc;
4704}
4705
4706/**
4707 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4708 */
4709static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4710{
4711 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4712
4713 /* Save Codec nodes states. */
4714 hdaCodecSaveState(pThis->pCodec, pSSM);
4715
4716 /* Save MMIO registers. */
4717 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
4718 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4719
4720 /* Save number of streams. */
4721 SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
4722
4723 /* Save stream states. */
4724 int rc;
4725 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4726 {
4727 rc = hdaSaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
4728 AssertRCReturn(rc, rc);
4729 }
4730
4731 return rc;
4732}
4733
4734
4735/**
4736 * @callback_method_impl{FNSSMDEVLOADEXEC}
4737 */
4738static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4739{
4740 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4741
4742 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
4743
4744 LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
4745
4746 /*
4747 * Load Codec nodes states.
4748 */
4749 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
4750 if (RT_FAILURE(rc))
4751 {
4752 LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
4753 return rc;
4754 }
4755
4756 /*
4757 * Load MMIO registers.
4758 */
4759 uint32_t cRegs;
4760 switch (uVersion)
4761 {
4762 case HDA_SSM_VERSION_1:
4763 /* Starting with r71199, we would save 112 instead of 113
4764 registers due to some code cleanups. This only affected trunk
4765 builds in the 4.1 development period. */
4766 cRegs = 113;
4767 if (SSMR3HandleRevision(pSSM) >= 71199)
4768 {
4769 uint32_t uVer = SSMR3HandleVersion(pSSM);
4770 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
4771 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
4772 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
4773 cRegs = 112;
4774 }
4775 break;
4776
4777 case HDA_SSM_VERSION_2:
4778 case HDA_SSM_VERSION_3:
4779 cRegs = 112;
4780 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
4781 break;
4782
4783 /* Since version 4 we store the register count to stay flexible. */
4784 case HDA_SSM_VERSION_4:
4785 case HDA_SSM_VERSION_5:
4786 case HDA_SSM_VERSION:
4787 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
4788 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
4789 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
4790 break;
4791
4792 default:
4793 LogRel(("HDA: Unsupported / too new saved state version (%RU32)\n", uVersion));
4794 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4795 }
4796
4797 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
4798 {
4799 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4800 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
4801 }
4802 else
4803 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
4804
4805 /*
4806 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
4807 * *every* BDLE state, whereas it only needs to be stored
4808 * *once* for every stream. Most of the BDLE state we can
4809 * get out of the registers anyway, so just ignore those values.
4810 *
4811 * Also, only the current BDLE was saved, regardless whether
4812 * there were more than one (and there are at least two entries,
4813 * according to the spec).
4814 */
4815#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
4816 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
4817 AssertRCReturn(rc, rc); \
4818 rc = SSMR3GetU64(pSSM, &x.u64BufAdr); /* u64BdleCviAddr */ \
4819 AssertRCReturn(rc, rc); \
4820 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
4821 AssertRCReturn(rc, rc); \
4822 rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
4823 AssertRCReturn(rc, rc); \
4824 rc = SSMR3GetU32(pSSM, &x.u32BufSize); /* u32BdleCviLen */ \
4825 AssertRCReturn(rc, rc); \
4826 rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
4827 AssertRCReturn(rc, rc); \
4828 rc = SSMR3GetBool(pSSM, &x.fIntOnCompletion); /* fBdleCviIoc */ \
4829 AssertRCReturn(rc, rc); \
4830 rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
4831 AssertRCReturn(rc, rc); \
4832 rc = SSMR3GetMem(pSSM, &x.State.au8FIFO, sizeof(x.State.au8FIFO)); \
4833 AssertRCReturn(rc, rc); \
4834 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
4835 AssertRCReturn(rc, rc); \
4836
4837 /*
4838 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
4839 */
4840 switch (uVersion)
4841 {
4842 case HDA_SSM_VERSION_1:
4843 case HDA_SSM_VERSION_2:
4844 case HDA_SSM_VERSION_3:
4845 case HDA_SSM_VERSION_4:
4846 {
4847 /* Only load the internal states.
4848 * The rest will be initialized from the saved registers later. */
4849
4850 /* Note 1: Only the *current* BDLE for a stream was saved! */
4851 /* Note 2: The stream's saving order is/was fixed, so don't touch! */
4852
4853 /* Output */
4854 PHDASTREAM pStream = &pThis->aStreams[4];
4855 rc = hdaStreamInit(pThis, pStream, 4 /* Stream descriptor, hardcoded */);
4856 if (RT_FAILURE(rc))
4857 break;
4858 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
4859 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
4860
4861 /* Microphone-In */
4862 pStream = &pThis->aStreams[2];
4863 rc = hdaStreamInit(pThis, pStream, 2 /* Stream descriptor, hardcoded */);
4864 if (RT_FAILURE(rc))
4865 break;
4866 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
4867 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
4868
4869 /* Line-In */
4870 pStream = &pThis->aStreams[0];
4871 rc = hdaStreamInit(pThis, pStream, 0 /* Stream descriptor, hardcoded */);
4872 if (RT_FAILURE(rc))
4873 break;
4874 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
4875 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
4876 break;
4877 }
4878
4879 /* Since v5 we support flexible stream and BDLE counts. */
4880 case HDA_SSM_VERSION_5:
4881 case HDA_SSM_VERSION:
4882 {
4883 uint32_t cStreams;
4884 rc = SSMR3GetU32(pSSM, &cStreams);
4885 if (RT_FAILURE(rc))
4886 break;
4887
4888 LogRel2(("hdaLoadExec: cStreams=%RU32\n", cStreams));
4889
4890 /* Load stream states. */
4891 for (uint32_t i = 0; i < cStreams; i++)
4892 {
4893 uint8_t uSD;
4894 rc = SSMR3GetU8(pSSM, &uSD);
4895 if (RT_FAILURE(rc))
4896 break;
4897
4898 PHDASTREAM pStrm = hdaStreamFromSD(pThis, uSD);
4899 HDASTREAM StreamDummy;
4900
4901 if (!pStrm)
4902 {
4903 RT_ZERO(StreamDummy);
4904 pStrm = &StreamDummy;
4905 LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uSD));
4906 break;
4907 }
4908
4909 rc = hdaStreamInit(pThis, pStrm, uSD);
4910 if (RT_FAILURE(rc))
4911 {
4912 LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uSD, rc));
4913 break;
4914 }
4915
4916 if (uVersion == HDA_SSM_VERSION_5)
4917 {
4918 /* Get the current BDLE entry and skip the rest. */
4919 uint16_t cBDLE;
4920
4921 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
4922 AssertRC(rc);
4923 rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
4924 AssertRC(rc);
4925 rc = SSMR3GetU16(pSSM, &pStrm->State.uCurBDLE); /* uCurBDLE */
4926 AssertRC(rc);
4927 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
4928 AssertRC(rc);
4929
4930 uint32_t u32BDLEIndex;
4931 for (uint16_t a = 0; a < cBDLE; a++)
4932 {
4933 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
4934 AssertRC(rc);
4935 rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
4936 AssertRC(rc);
4937
4938 /* Does the current BDLE index match the current BDLE to process? */
4939 if (u32BDLEIndex == pStrm->State.uCurBDLE)
4940 {
4941 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
4942 AssertRC(rc);
4943 rc = SSMR3GetMem(pSSM,
4944 &pStrm->State.BDLE.State.au8FIFO,
4945 sizeof(pStrm->State.BDLE.State.au8FIFO)); /* au8FIFO */
4946 AssertRC(rc);
4947 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.u32BufOff); /* u32BufOff */
4948 AssertRC(rc);
4949 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
4950 AssertRC(rc);
4951 }
4952 else /* Skip not current BDLEs. */
4953 {
4954 rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
4955 + sizeof(uint8_t) * 256 /* au8FIFO */
4956 + sizeof(uint32_t) /* u32BufOff */
4957 + sizeof(uint32_t)); /* End marker */
4958 AssertRC(rc);
4959 }
4960 }
4961 }
4962 else
4963 {
4964 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE),
4965 0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
4966 if (RT_FAILURE(rc))
4967 break;
4968
4969 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
4970 0 /* fFlags */, g_aSSMBDLEFields6, NULL);
4971 if (RT_FAILURE(rc))
4972 break;
4973
4974 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
4975 0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
4976 if (RT_FAILURE(rc))
4977 break;
4978 }
4979 }
4980 break;
4981 }
4982
4983 default:
4984 AssertReleaseFailed(); /* Never reached. */
4985 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4986 }
4987
4988#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
4989
4990 if (RT_SUCCESS(rc))
4991 {
4992 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
4993 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
4994 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
4995
4996 /* Also make sure to update the DMA position bit if this was enabled when saving the state. */
4997 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
4998 }
4999
5000 if (RT_SUCCESS(rc))
5001 {
5002 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5003 {
5004 PHDASTREAM pStream = hdaStreamFromSD(pThis, i);
5005 if (pStream)
5006 {
5007 bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
5008 LogFlowFunc(("[SD%RU8]: fActive=%RTbool\n", i, fActive));
5009 int rc2 = hdaStreamSetActive(pThis, pStream, fActive);
5010 AssertRC(rc2);
5011 }
5012 }
5013 }
5014
5015 if (RT_FAILURE(rc))
5016 LogRel(("HDA: Failed loading device state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5017
5018 LogFlowFuncLeaveRC(rc);
5019 return rc;
5020}
5021
5022#ifdef DEBUG
5023/* Debug and log type formatters. */
5024
5025/**
5026 * @callback_method_impl{FNRTSTRFORMATTYPE}
5027 */
5028static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5029 const char *pszType, void const *pvValue,
5030 int cchWidth, int cchPrecision, unsigned fFlags,
5031 void *pvUser)
5032{
5033 PHDABDLE pBDLE = (PHDABDLE)pvValue;
5034 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5035 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
5036 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW, pBDLE->fIntOnCompletion,
5037 pBDLE->u32BufSize, pBDLE->u64BufAdr);
5038}
5039
5040/**
5041 * @callback_method_impl{FNRTSTRFORMATTYPE}
5042 */
5043static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5044 const char *pszType, void const *pvValue,
5045 int cchWidth, int cchPrecision, unsigned fFlags,
5046 void *pvUser)
5047{
5048 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
5049 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5050 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
5051 uSDCTL,
5052 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
5053 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
5054 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
5055 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
5056 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
5057 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
5058 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
5059 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
5060}
5061
5062/**
5063 * @callback_method_impl{FNRTSTRFORMATTYPE}
5064 */
5065static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5066 const char *pszType, void const *pvValue,
5067 int cchWidth, int cchPrecision, unsigned fFlags,
5068 void *pvUser)
5069{
5070 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
5071 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, hdaSDFIFOSToBytes(uSDFIFOS));
5072}
5073
5074/**
5075 * @callback_method_impl{FNRTSTRFORMATTYPE}
5076 */
5077static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5078 const char *pszType, void const *pvValue,
5079 int cchWidth, int cchPrecision, unsigned fFlags,
5080 void *pvUser)
5081{
5082 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
5083 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
5084}
5085
5086/**
5087 * @callback_method_impl{FNRTSTRFORMATTYPE}
5088 */
5089static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5090 const char *pszType, void const *pvValue,
5091 int cchWidth, int cchPrecision, unsigned fFlags,
5092 void *pvUser)
5093{
5094 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
5095 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5096 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
5097 uSdSts,
5098 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
5099 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
5100 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
5101 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
5102}
5103
5104static int hdaDbgLookupRegByName(PHDASTATE pThis, const char *pszArgs)
5105{
5106 int iReg = 0;
5107 for (; iReg < HDA_NUM_REGS; ++iReg)
5108 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
5109 return iReg;
5110 return -1;
5111}
5112
5113
5114static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
5115{
5116 Assert( pThis
5117 && iHdaIndex >= 0
5118 && iHdaIndex < HDA_NUM_REGS);
5119 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
5120}
5121
5122/**
5123 * @callback_method_impl{FNDBGFHANDLERDEV}
5124 */
5125static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5126{
5127 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5128 int iHdaRegisterIndex = hdaDbgLookupRegByName(pThis, pszArgs);
5129 if (iHdaRegisterIndex != -1)
5130 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5131 else
5132 {
5133 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
5134 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5135 }
5136}
5137
5138static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5139{
5140 Assert( pThis
5141 && iIdx >= 0
5142 && iIdx < HDA_MAX_STREAMS);
5143
5144 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5145
5146 pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
5147 pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
5148 pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
5149 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
5150 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
5151 pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStrm->State.BDLE);
5152}
5153
5154static void hdaDbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5155{
5156 Assert( pThis
5157 && iIdx >= 0
5158 && iIdx < HDA_MAX_STREAMS);
5159
5160 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5161 const PHDABDLE pBDLE = &pStrm->State.BDLE;
5162
5163 pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
5164 pHlp->pfnPrintf(pHlp, "\t%R[bdle]\n", pBDLE);
5165
5166 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
5167 HDA_STREAM_REG(pThis, BDPU, iIdx));
5168 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
5169 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
5170
5171 if (!u64BaseDMA)
5172 return;
5173
5174 uint32_t cbBDLE = 0;
5175 for (uint16_t i = 0; i < u16LVI + 1; i++)
5176 {
5177 uint8_t bdle[16]; /** @todo Use a define. */
5178 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * 16, bdle, 16); /** @todo Use a define. */
5179
5180 uint64_t addr = *(uint64_t *)bdle;
5181 uint32_t len = *(uint32_t *)&bdle[8];
5182 uint32_t ioc = *(uint32_t *)&bdle[12];
5183
5184 pHlp->pfnPrintf(pHlp, "\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
5185 i, addr, len, RT_BOOL(ioc & 0x1));
5186
5187 cbBDLE += len;
5188 }
5189
5190 pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
5191
5192 pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", pThis->u64DPBase);
5193 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
5194 {
5195 pHlp->pfnPrintf(pHlp, "No counters found\n");
5196 return;
5197 }
5198
5199 for (int i = 0; i < u16LVI + 1; i++)
5200 {
5201 uint32_t uDMACnt;
5202 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
5203 &uDMACnt, sizeof(uDMACnt));
5204
5205 pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
5206 }
5207}
5208
5209static int hdaDbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
5210{
5211 /** @todo Add args parsing. */
5212 return -1;
5213}
5214
5215/**
5216 * @callback_method_impl{FNDBGFHANDLERDEV}
5217 */
5218static DECLCALLBACK(void) hdaDbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5219{
5220 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5221 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5222 if (iHdaStreamdex != -1)
5223 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5224 else
5225 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5226 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5227}
5228
5229/**
5230 * @callback_method_impl{FNDBGFHANDLERDEV}
5231 */
5232static DECLCALLBACK(void) hdaDbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5233{
5234 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5235 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5236 if (iHdaStreamdex != -1)
5237 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5238 else
5239 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5240 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5241}
5242
5243/**
5244 * @callback_method_impl{FNDBGFHANDLERDEV}
5245 */
5246static DECLCALLBACK(void) hdaDbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5247{
5248 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5249
5250 if (pThis->pCodec->pfnDbgListNodes)
5251 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
5252 else
5253 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5254}
5255
5256/**
5257 * @callback_method_impl{FNDBGFHANDLERDEV}
5258 */
5259static DECLCALLBACK(void) hdaDbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5260{
5261 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5262
5263 if (pThis->pCodec->pfnDbgSelector)
5264 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
5265 else
5266 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5267}
5268
5269/**
5270 * @callback_method_impl{FNDBGFHANDLERDEV}
5271 */
5272static DECLCALLBACK(void) hdaDbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5273{
5274 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5275
5276 if (pThis->pMixer)
5277 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
5278 else
5279 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
5280}
5281#endif /* DEBUG */
5282
5283/* PDMIBASE */
5284
5285/**
5286 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5287 */
5288static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
5289{
5290 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
5291 Assert(&pThis->IBase == pInterface);
5292
5293 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5294 return NULL;
5295}
5296
5297
5298/* PDMDEVREG */
5299
5300/**
5301 * Reset notification.
5302 *
5303 * @returns VBox status code.
5304 * @param pDevIns The device instance data.
5305 *
5306 * @remark The original sources didn't install a reset handler, but it seems to
5307 * make sense to me so we'll do it.
5308 */
5309static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
5310{
5311 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5312
5313 LogFlowFuncEnter();
5314
5315# ifndef VBOX_WITH_AUDIO_CALLBACKS
5316 /*
5317 * Stop the timer, if any.
5318 */
5319 hdaTimerMaybeStop(pThis);
5320# endif
5321
5322 /* See 6.2.1. */
5323 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO /* Ouput streams */,
5324 HDA_MAX_SDI /* Input streams */,
5325 0 /* Bidirectional output streams */,
5326 0 /* Serial data out signals */,
5327 1 /* 64-bit */);
5328 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
5329 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
5330 /* Announce the full 60 words output payload. */
5331 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
5332 /* Announce the full 29 words input payload. */
5333 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
5334 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
5335 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
5336 HDA_REG(pThis, CORBRP) = 0x0;
5337 HDA_REG(pThis, RIRBWP) = 0x0;
5338
5339 /*
5340 * Stop any audio currently playing and/or recording.
5341 */
5342 AudioMixerSinkCtl(pThis->SinkFront.pMixSink, AUDMIXSINKCMD_DISABLE);
5343# ifdef VBOX_WITH_HDA_MIC_IN
5344 AudioMixerSinkCtl(pThis->SinkMicIn.pMixSink, AUDMIXSINKCMD_DISABLE);
5345# endif
5346 AudioMixerSinkCtl(pThis->SinkLineIn.pMixSink, AUDMIXSINKCMD_DISABLE);
5347# ifdef VBOX_WITH_HDA_51_SURROUND
5348 AudioMixerSinkCtl(pThis->SinkCenterLFE.pMixSink, AUDMIXSINKCMD_DISABLE);
5349 AudioMixerSinkCtl(pThis->SinkRear.pMixSink, AUDMIXSINKCMD_DISABLE);
5350# endif
5351
5352 /*
5353 * Set some sensible defaults for which HDA sinks
5354 * are connected to which stream number.
5355 *
5356 * We use SD0 for input and SD4 for output by default.
5357 * These stream numbers can be changed by the guest dynamically lateron.
5358 */
5359#ifdef VBOX_WITH_HDA_MIC_IN
5360 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 */, 0 /* Channel */);
5361#endif
5362 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 */, 0 /* Channel */);
5363
5364 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 */, 0 /* Channel */);
5365#ifdef VBOX_WITH_HDA_51_SURROUND
5366 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 */, 0 /* Channel */);
5367 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 */, 0 /* Channel */);
5368#endif
5369
5370 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
5371
5372 if (pThis->pu32CorbBuf)
5373 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
5374 else
5375 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5376
5377 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
5378 if (pThis->pu64RirbBuf)
5379 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
5380 else
5381 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5382
5383 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
5384
5385 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5386 {
5387 /* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
5388 HDA_STREAM_REG(pThis, CTL, i) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN);
5389 hdaStreamReset(pThis, &pThis->aStreams[i]);
5390 }
5391
5392 /* Clear stream tags <-> objects mapping table. */
5393 RT_ZERO(pThis->aTags);
5394
5395 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
5396 HDA_REG(pThis, STATESTS) = 0x1;
5397
5398# ifndef VBOX_WITH_AUDIO_CALLBACKS
5399 hdaTimerMaybeStart(pThis);
5400# endif
5401
5402 LogFlowFuncLeave();
5403 LogRel(("HDA: Reset\n"));
5404}
5405
5406/**
5407 * @interface_method_impl{PDMDEVREG,pfnDestruct}
5408 */
5409static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
5410{
5411 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5412
5413 PHDADRIVER pDrv;
5414 while (!RTListIsEmpty(&pThis->lstDrv))
5415 {
5416 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
5417
5418 RTListNodeRemove(&pDrv->Node);
5419 RTMemFree(pDrv);
5420 }
5421
5422 if (pThis->pCodec)
5423 {
5424 hdaCodecDestruct(pThis->pCodec);
5425
5426 RTMemFree(pThis->pCodec);
5427 pThis->pCodec = NULL;
5428 }
5429
5430 RTMemFree(pThis->pu32CorbBuf);
5431 pThis->pu32CorbBuf = NULL;
5432
5433 RTMemFree(pThis->pu64RirbBuf);
5434 pThis->pu64RirbBuf = NULL;
5435
5436 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5437 hdaStreamDestroy(&pThis->aStreams[i]);
5438
5439 return VINF_SUCCESS;
5440}
5441
5442
5443/**
5444 * Attach command, internal version.
5445 *
5446 * This is called to let the device attach to a driver for a specified LUN
5447 * during runtime. This is not called during VM construction, the device
5448 * constructor has to attach to all the available drivers.
5449 *
5450 * @returns VBox status code.
5451 * @param pDevIns The device instance.
5452 * @param pDrv Driver to (re-)use for (re-)attaching to.
5453 * If NULL is specified, a new driver will be created and appended
5454 * to the driver list.
5455 * @param uLUN The logical unit which is being detached.
5456 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5457 */
5458static int hdaAttachInternal(PPDMDEVINS pDevIns, PHDADRIVER pDrv, unsigned uLUN, uint32_t fFlags)
5459{
5460 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5461
5462 /*
5463 * Attach driver.
5464 */
5465 char *pszDesc = NULL;
5466 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
5467 AssertReleaseMsgReturn(pszDesc,
5468 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
5469 VERR_NO_MEMORY);
5470
5471 PPDMIBASE pDrvBase;
5472 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
5473 &pThis->IBase, &pDrvBase, pszDesc);
5474 if (RT_SUCCESS(rc))
5475 {
5476 if (pDrv == NULL)
5477 pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
5478 if (pDrv)
5479 {
5480 pDrv->pDrvBase = pDrvBase;
5481 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
5482 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
5483 pDrv->pHDAState = pThis;
5484 pDrv->uLUN = uLUN;
5485
5486 /*
5487 * For now we always set the driver at LUN 0 as our primary
5488 * host backend. This might change in the future.
5489 */
5490 if (pDrv->uLUN == 0)
5491 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
5492
5493 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
5494
5495 /* Attach to driver list if not attached yet. */
5496 if (!pDrv->fAttached)
5497 {
5498 RTListAppend(&pThis->lstDrv, &pDrv->Node);
5499 pDrv->fAttached = true;
5500 }
5501 }
5502 else
5503 rc = VERR_NO_MEMORY;
5504 }
5505 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5506 LogFunc(("No attached driver for LUN #%u\n", uLUN));
5507
5508 if (RT_FAILURE(rc))
5509 {
5510 /* Only free this string on failure;
5511 * must remain valid for the live of the driver instance. */
5512 RTStrFree(pszDesc);
5513 }
5514
5515 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
5516 return rc;
5517}
5518
5519/**
5520 * Attach command.
5521 *
5522 * This is called to let the device attach to a driver for a specified LUN
5523 * during runtime. This is not called during VM construction, the device
5524 * constructor has to attach to all the available drivers.
5525 *
5526 * @returns VBox status code.
5527 * @param pDevIns The device instance.
5528 * @param uLUN The logical unit which is being detached.
5529 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5530 */
5531static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5532{
5533 return hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
5534}
5535
5536static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5537{
5538 LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
5539}
5540
5541/**
5542 * Powers off the device.
5543 *
5544 * @param pDevIns Device instance to power off.
5545 */
5546static DECLCALLBACK(void) hdaPowerOff(PPDMDEVINS pDevIns)
5547{
5548 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5549
5550 LogRel2(("HDA: Powering off ...\n"));
5551
5552 /* Ditto goes for the codec, which in turn uses the mixer. */
5553 hdaCodecPowerOff(pThis->pCodec);
5554
5555 /**
5556 * Note: Destroy the mixer while powering off and *not* in hdaDestruct,
5557 * giving the mixer the chance to release any references held to
5558 * PDM audio streams it maintains.
5559 */
5560 if (pThis->pMixer)
5561 {
5562 AudioMixerDestroy(pThis->pMixer);
5563 pThis->pMixer = NULL;
5564 }
5565}
5566
5567/**
5568 * Re-attaches a new driver to the device's driver chain.
5569 *
5570 * @returns VBox status code.
5571 * @param pThis Device instance to re-attach driver to.
5572 * @param pDrv Driver instance used for attaching to.
5573 * If NULL is specified, a new driver will be created and appended
5574 * to the driver list.
5575 * @param uLUN The logical unit which is being re-detached.
5576 * @param pszDriver Driver name.
5577 */
5578static int hdaReattach(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
5579{
5580 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
5581 AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
5582
5583 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
5584 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
5585 PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
5586
5587 /* Remove LUN branch. */
5588 CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
5589
5590 if (pDrv)
5591 {
5592 /* Re-use a driver instance => detach the driver before. */
5593 int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
5594 if (RT_FAILURE(rc))
5595 return rc;
5596 }
5597
5598#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
5599
5600 int rc = VINF_SUCCESS;
5601 do
5602 {
5603 PCFGMNODE pLunL0;
5604 rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
5605 rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
5606 rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
5607
5608 PCFGMNODE pLunL1, pLunL2;
5609 rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
5610 rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
5611 rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
5612
5613 rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
5614
5615 } while (0);
5616
5617 if (RT_SUCCESS(rc))
5618 rc = hdaAttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
5619
5620 LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
5621
5622#undef RC_CHECK
5623
5624 return rc;
5625}
5626
5627/**
5628 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5629 */
5630static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5631{
5632 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5633 Assert(iInstance == 0);
5634 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5635
5636 /*
5637 * Validations.
5638 */
5639 if (!CFGMR3AreValuesValid(pCfg, "R0Enabled\0"
5640 "RCEnabled\0"
5641 "TimerHz\0"))
5642 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5643 N_ ("Invalid configuration for the Intel HDA device"));
5644
5645 int rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &pThis->fRCEnabled, false);
5646 if (RT_FAILURE(rc))
5647 return PDMDEV_SET_ERROR(pDevIns, rc,
5648 N_("HDA configuration error: failed to read RCEnabled as boolean"));
5649 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
5650 if (RT_FAILURE(rc))
5651 return PDMDEV_SET_ERROR(pDevIns, rc,
5652 N_("HDA configuration error: failed to read R0Enabled as boolean"));
5653#ifndef VBOX_WITH_AUDIO_CALLBACKS
5654 uint16_t uTimerHz;
5655 rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, 100 /* Hz */);
5656 if (RT_FAILURE(rc))
5657 return PDMDEV_SET_ERROR(pDevIns, rc,
5658 N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
5659#endif
5660
5661 /*
5662 * Initialize data (most of it anyway).
5663 */
5664 pThis->pDevInsR3 = pDevIns;
5665 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5666 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5667 /* IBase */
5668 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
5669
5670 /* PCI Device */
5671 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
5672 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
5673
5674 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
5675 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
5676 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
5677 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
5678 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
5679 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
5680 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
5681 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
5682 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
5683 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
5684 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
5685
5686#if defined(HDA_AS_PCI_EXPRESS)
5687 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
5688#elif defined(VBOX_WITH_MSI_DEVICES)
5689 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
5690#else
5691 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
5692#endif
5693
5694 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
5695 /// of these values needs to be properly documented!
5696 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
5697 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
5698
5699 /* Power Management */
5700 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
5701 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
5702 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
5703
5704#ifdef HDA_AS_PCI_EXPRESS
5705 /* PCI Express */
5706 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
5707 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
5708 /* Device flags */
5709 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
5710 /* version */ 0x1 |
5711 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
5712 /* MSI */ (100) << 9 );
5713 /* Device capabilities */
5714 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
5715 /* Device control */
5716 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
5717 /* Device status */
5718 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
5719 /* Link caps */
5720 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
5721 /* Link control */
5722 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
5723 /* Link status */
5724 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
5725 /* Slot capabilities */
5726 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
5727 /* Slot control */
5728 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
5729 /* Slot status */
5730 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
5731 /* Root control */
5732 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
5733 /* Root capabilities */
5734 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
5735 /* Root status */
5736 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
5737 /* Device capabilities 2 */
5738 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
5739 /* Device control 2 */
5740 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
5741 /* Link control 2 */
5742 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
5743 /* Slot control 2 */
5744 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
5745#endif
5746
5747 /*
5748 * Register the PCI device.
5749 */
5750 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5751 if (RT_FAILURE(rc))
5752 return rc;
5753
5754 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
5755 if (RT_FAILURE(rc))
5756 return rc;
5757
5758#ifdef VBOX_WITH_MSI_DEVICES
5759 PDMMSIREG MsiReg;
5760 RT_ZERO(MsiReg);
5761 MsiReg.cMsiVectors = 1;
5762 MsiReg.iMsiCapOffset = 0x60;
5763 MsiReg.iMsiNextOffset = 0x50;
5764 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5765 if (RT_FAILURE(rc))
5766 {
5767 /* That's OK, we can work without MSI */
5768 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
5769 }
5770#endif
5771
5772 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
5773 if (RT_FAILURE(rc))
5774 return rc;
5775
5776 RTListInit(&pThis->lstDrv);
5777
5778 uint8_t uLUN;
5779 for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
5780 {
5781 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
5782 rc = hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, 0 /* fFlags */);
5783 if (RT_FAILURE(rc))
5784 {
5785 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5786 rc = VINF_SUCCESS;
5787 else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
5788 {
5789 hdaReattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
5790 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
5791 N_("No audio devices could be opened. Selecting the NULL audio backend "
5792 "with the consequence that no sound is audible"));
5793 /* attaching to the NULL audio backend will never fail */
5794 rc = VINF_SUCCESS;
5795 }
5796 break;
5797 }
5798 }
5799
5800 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
5801
5802 if (RT_SUCCESS(rc))
5803 {
5804 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
5805 if (RT_SUCCESS(rc))
5806 {
5807 /* Set a default audio format for our mixer. */
5808 PDMAUDIOSTREAMCFG streamCfg;
5809 streamCfg.uHz = 44100;
5810 streamCfg.cChannels = 2;
5811 streamCfg.enmFormat = PDMAUDIOFMT_S16;
5812 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
5813
5814 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
5815 AssertRC(rc);
5816
5817 /*
5818 * Add mixer output sinks.
5819 */
5820#ifdef VBOX_WITH_HDA_51_SURROUND
5821 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
5822 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5823 AssertRC(rc);
5824 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
5825 AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
5826 AssertRC(rc);
5827 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
5828 AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
5829 AssertRC(rc);
5830#else
5831 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
5832 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5833 AssertRC(rc);
5834#endif
5835 /*
5836 * Add mixer input sinks.
5837 */
5838 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
5839 AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
5840 AssertRC(rc);
5841#ifdef VBOX_WITH_HDA_MIC_IN
5842 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
5843 AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
5844 AssertRC(rc);
5845#endif
5846 /* There is no master volume control. Set the master to max. */
5847 PDMAUDIOVOLUME vol = { false, 255, 255 };
5848 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
5849 AssertRC(rc);
5850 }
5851 }
5852
5853 if (RT_SUCCESS(rc))
5854 {
5855 /* Construct codec. */
5856 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
5857 if (!pThis->pCodec)
5858 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
5859
5860 /* Set codec callbacks. */
5861 pThis->pCodec->pfnMixerAddStream = hdaMixerAddStream;
5862 pThis->pCodec->pfnMixerRemoveStream = hdaMixerRemoveStream;
5863 pThis->pCodec->pfnMixerSetStream = hdaMixerSetStream;
5864 pThis->pCodec->pfnMixerSetVolume = hdaMixerSetVolume;
5865 pThis->pCodec->pfnReset = hdaCodecReset;
5866
5867 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
5868
5869 /* Construct the codec. */
5870 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
5871 if (RT_FAILURE(rc))
5872 AssertRCReturn(rc, rc);
5873
5874 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
5875 verb F20 should provide device/codec recognition. */
5876 Assert(pThis->pCodec->u16VendorId);
5877 Assert(pThis->pCodec->u16DeviceId);
5878 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
5879 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
5880 }
5881
5882 if (RT_SUCCESS(rc))
5883 {
5884 /*
5885 * Create all hardware streams.
5886 */
5887 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5888 {
5889 rc = hdaStreamCreate(&pThis->aStreams[i], i /* uSD */);
5890 AssertRC(rc);
5891 }
5892
5893 /*
5894 * Initialize the driver chain.
5895 */
5896 PHDADRIVER pDrv;
5897 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
5898 {
5899 /*
5900 * Only primary drivers are critical for the VM to run. Everything else
5901 * might not worth showing an own error message box in the GUI.
5902 */
5903 if (!(pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY))
5904 continue;
5905
5906 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
5907 AssertPtr(pCon);
5908
5909 bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
5910#ifdef VBOX_WITH_HDA_MIC_IN
5911 bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
5912#endif
5913 bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
5914#ifdef VBOX_WITH_HDA_51_SURROUND
5915 /** @todo Anything to do here? */
5916#endif
5917
5918 if ( !fValidLineIn
5919#ifdef VBOX_WITH_HDA_MIC_IN
5920 && !fValidMicIn
5921#endif
5922 && !fValidOut)
5923 {
5924 LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
5925
5926 hdaReset(pDevIns);
5927 hdaReattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
5928
5929 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
5930 N_("No audio devices could be opened. Selecting the NULL audio backend "
5931 "with the consequence that no sound is audible"));
5932 }
5933 else
5934 {
5935 bool fWarn = false;
5936
5937 PDMAUDIOBACKENDCFG backendCfg;
5938 int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
5939 if (RT_SUCCESS(rc2))
5940 {
5941 if (backendCfg.cSources)
5942 {
5943#ifdef VBOX_WITH_HDA_MIC_IN
5944 /* If the audio backend supports two or more input streams at once,
5945 * warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
5946 if (backendCfg.cMaxStreamsIn >= 2)
5947 fWarn = !fValidLineIn || !fValidMicIn;
5948 /* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
5949 * *not* ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
5950 * One of the two simply is not in use then. */
5951 else if (backendCfg.cMaxStreamsIn == 1)
5952 fWarn = !fValidLineIn && !fValidMicIn;
5953 /* Don't warn if our backend is not able of supporting any input streams at all. */
5954#else
5955 /* We only have line-in as input source. */
5956 fWarn = !fValidLineIn;
5957#endif
5958 }
5959
5960 if ( !fWarn
5961 && backendCfg.cSinks)
5962 {
5963 fWarn = !fValidOut;
5964 }
5965 }
5966 else
5967 AssertReleaseMsgFailed(("Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n",
5968 pDrv->uLUN, rc2));
5969
5970 if (fWarn)
5971 {
5972 char szMissingStreams[255];
5973 size_t len = 0;
5974 if (!fValidLineIn)
5975 {
5976 LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
5977 len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
5978 }
5979#ifdef VBOX_WITH_HDA_MIC_IN
5980 if (!fValidMicIn)
5981 {
5982 LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
5983 len += RTStrPrintf(szMissingStreams + len,
5984 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
5985 }
5986#endif
5987 if (!fValidOut)
5988 {
5989 LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
5990 len += RTStrPrintf(szMissingStreams + len,
5991 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
5992 }
5993
5994 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
5995 N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
5996 "output or depending on audio input may hang. Make sure your host audio device "
5997 "is working properly. Check the logfile for error messages of the audio "
5998 "subsystem"), szMissingStreams);
5999 }
6000 }
6001 }
6002 }
6003
6004 if (RT_SUCCESS(rc))
6005 {
6006 hdaReset(pDevIns);
6007
6008 /*
6009 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
6010 * hdaReset shouldn't affects these registers.
6011 */
6012 HDA_REG(pThis, WAKEEN) = 0x0;
6013 HDA_REG(pThis, STATESTS) = 0x0;
6014
6015#ifdef DEBUG
6016 /*
6017 * Debug and string formatter types.
6018 */
6019 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
6020 PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaDbgInfoBDLE);
6021 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgInfoStream);
6022 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaDbgInfoCodecNodes);
6023 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaDbgInfoCodecSelector);
6024 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaDbgInfoMixer);
6025
6026 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
6027 AssertRC(rc);
6028 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
6029 AssertRC(rc);
6030 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
6031 AssertRC(rc);
6032 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
6033 AssertRC(rc);
6034 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
6035 AssertRC(rc);
6036#endif /* DEBUG */
6037
6038 /*
6039 * Some debug assertions.
6040 */
6041 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
6042 {
6043 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
6044 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
6045
6046 /* binary search order. */
6047 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
6048 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6049 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6050
6051 /* alignment. */
6052 AssertReleaseMsg( pReg->size == 1
6053 || (pReg->size == 2 && (pReg->offset & 1) == 0)
6054 || (pReg->size == 3 && (pReg->offset & 3) == 0)
6055 || (pReg->size == 4 && (pReg->offset & 3) == 0),
6056 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6057
6058 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
6059 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
6060 if (pReg->offset & 3)
6061 {
6062 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
6063 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6064 if (pPrevReg)
6065 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
6066 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6067 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
6068 }
6069#if 0
6070 if ((pReg->offset + pReg->size) & 3)
6071 {
6072 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6073 if (pNextReg)
6074 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
6075 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6076 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6077 }
6078#endif
6079 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
6080 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
6081 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6082 }
6083 }
6084
6085# ifndef VBOX_WITH_AUDIO_CALLBACKS
6086 if (RT_SUCCESS(rc))
6087 {
6088 /* Start the emulation timer. */
6089 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
6090 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
6091 AssertRCReturn(rc, rc);
6092
6093 if (RT_SUCCESS(rc))
6094 {
6095 pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
6096 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
6097 LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
6098
6099 hdaTimerMaybeStart(pThis);
6100 }
6101 }
6102# else
6103 if (RT_SUCCESS(rc))
6104 {
6105 PHDADRIVER pDrv;
6106 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6107 {
6108 /* Only register primary driver.
6109 * The device emulation does the output multiplexing then. */
6110 if (pDrv->Flags != PDMAUDIODRVFLAG_PRIMARY)
6111 continue;
6112
6113 PDMAUDIOCALLBACK AudioCallbacks[2];
6114
6115 HDACALLBACKCTX Ctx = { pThis, pDrv };
6116
6117 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
6118 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
6119 AudioCallbacks[0].pvCtx = &Ctx;
6120 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
6121
6122 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
6123 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
6124 AudioCallbacks[1].pvCtx = &Ctx;
6125 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
6126
6127 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
6128 if (RT_FAILURE(rc))
6129 break;
6130 }
6131 }
6132# endif
6133
6134# ifdef VBOX_WITH_STATISTICS
6135 if (RT_SUCCESS(rc))
6136 {
6137 /*
6138 * Register statistics.
6139 */
6140# ifndef VBOX_WITH_AUDIO_CALLBACKS
6141 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
6142# endif
6143 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
6144 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
6145 }
6146# endif
6147
6148 LogFlowFuncLeaveRC(rc);
6149 return rc;
6150}
6151
6152/**
6153 * The device registration structure.
6154 */
6155const PDMDEVREG g_DeviceICH6_HDA =
6156{
6157 /* u32Version */
6158 PDM_DEVREG_VERSION,
6159 /* szName */
6160 "hda",
6161 /* szRCMod */
6162 "VBoxDDRC.rc",
6163 /* szR0Mod */
6164 "VBoxDDR0.r0",
6165 /* pszDescription */
6166 "Intel HD Audio Controller",
6167 /* fFlags */
6168 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
6169 /* fClass */
6170 PDM_DEVREG_CLASS_AUDIO,
6171 /* cMaxInstances */
6172 1,
6173 /* cbInstance */
6174 sizeof(HDASTATE),
6175 /* pfnConstruct */
6176 hdaConstruct,
6177 /* pfnDestruct */
6178 hdaDestruct,
6179 /* pfnRelocate */
6180 NULL,
6181 /* pfnMemSetup */
6182 NULL,
6183 /* pfnPowerOn */
6184 NULL,
6185 /* pfnReset */
6186 hdaReset,
6187 /* pfnSuspend */
6188 NULL,
6189 /* pfnResume */
6190 NULL,
6191 /* pfnAttach */
6192 hdaAttach,
6193 /* pfnDetach */
6194 hdaDetach,
6195 /* pfnQueryInterface. */
6196 NULL,
6197 /* pfnInitComplete */
6198 NULL,
6199 /* pfnPowerOff */
6200 hdaPowerOff,
6201 /* pfnSoftReset */
6202 NULL,
6203 /* u32VersionEnd */
6204 PDM_DEVREG_VERSION
6205};
6206
6207#endif /* IN_RING3 */
6208#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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