VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 61417

Last change on this file since 61417 was 61417, checked in by vboxsync, 9 years ago

Audio/DevIchHda.cpp: Saved state fixes.
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1/* $Id: DevIchHda.cpp 61417 2016-06-02 16:16:21Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2016 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/file.h>
36#include <iprt/list.h>
37#ifdef IN_RING3
38# include <iprt/mem.h>
39# include <iprt/semaphore.h>
40# include <iprt/string.h>
41# include <iprt/uuid.h>
42#endif
43
44#include "VBoxDD.h"
45
46#include "AudioMixBuffer.h"
47#include "AudioMixer.h"
48#include "DevIchHdaCodec.h"
49#include "DevIchHdaCommon.h"
50#include "DrvAudio.h"
51
52
53/*********************************************************************************************************************************
54* Defined Constants And Macros *
55*********************************************************************************************************************************/
56//#define HDA_AS_PCI_EXPRESS
57#define VBOX_WITH_INTEL_HDA
58
59#ifdef DEBUG_andy
60/* Enables experimental support for separate mic-in handling.
61 Do not enable this yet for regular builds, as this needs more testing first! */
62//# define VBOX_WITH_HDA_MIC_IN
63#endif
64
65#if defined(VBOX_WITH_HP_HDA)
66/* HP Pavilion dv4t-1300 */
67# define HDA_PCI_VENDOR_ID 0x103c
68# define HDA_PCI_DEVICE_ID 0x30f7
69#elif defined(VBOX_WITH_INTEL_HDA)
70/* Intel HDA controller */
71# define HDA_PCI_VENDOR_ID 0x8086
72# define HDA_PCI_DEVICE_ID 0x2668
73#elif defined(VBOX_WITH_NVIDIA_HDA)
74/* nVidia HDA controller */
75# define HDA_PCI_VENDOR_ID 0x10de
76# define HDA_PCI_DEVICE_ID 0x0ac0
77#else
78# error "Please specify your HDA device vendor/device IDs"
79#endif
80
81/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
82 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
83 * is read only except for bit 15 like the HDA spec states.
84 *
85 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
86 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
87#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
88
89/* Make sure that interleaving streams support is enabled if the 5.1 code is being used. */
90#if defined (VBOX_WITH_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT)
91# define VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
92#endif
93
94/**
95 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
96 * Bidirectional streams are currently *not* supported.
97 *
98 * Note: When changing any of those values, be prepared for some saved state
99 * fixups / trouble!
100 */
101#define HDA_MAX_SDI 4
102#define HDA_MAX_SDO 4
103#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
104AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
105
106/** Number of general registers. */
107#define HDA_NUM_GENERAL_REGS 34
108/** Number of total registers in the HDA's register map. */
109#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
110/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
111#define HDA_MAX_TAGS 16
112
113/**
114 * NB: Register values stored in memory (au32Regs[]) are indexed through
115 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
116 * register descriptors in g_aHdaRegMap[] are indexed through the
117 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
118 *
119 * The au32Regs[] layout is kept unchanged for saved state
120 * compatibility.
121 */
122
123/* Registers */
124#define HDA_REG_IND_NAME(x) HDA_REG_##x
125#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
126#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
127#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
128#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
129#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
130#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
131#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
132
133
134#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
135#define HDA_RMX_GCAP 0
136/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
137 * oss (15:12) - number of output streams supported
138 * iss (11:8) - number of input streams supported
139 * bss (7:3) - number of bidirectional streams supported
140 * bds (2:1) - number of serial data out (SDO) signals supported
141 * b64sup (0) - 64 bit addressing supported.
142 */
143#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
144 ( (((oss) & 0xF) << 12) \
145 | (((iss) & 0xF) << 8) \
146 | (((bss) & 0x1F) << 3) \
147 | (((bds) & 0x3) << 1) \
148 | ((b64sup) & 1))
149
150#define HDA_REG_VMIN 1 /* 0x02 */
151#define HDA_RMX_VMIN 1
152
153#define HDA_REG_VMAJ 2 /* 0x03 */
154#define HDA_RMX_VMAJ 2
155
156#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
157#define HDA_RMX_OUTPAY 3
158
159#define HDA_REG_INPAY 4 /* 0x06-0x07 */
160#define HDA_RMX_INPAY 4
161
162#define HDA_REG_GCTL 5 /* 0x08-0x0B */
163#define HDA_RMX_GCTL 5
164#define HDA_GCTL_RST_SHIFT 0
165#define HDA_GCTL_FSH_SHIFT 1
166#define HDA_GCTL_UR_SHIFT 8
167
168#define HDA_REG_WAKEEN 6 /* 0x0C */
169#define HDA_RMX_WAKEEN 6
170
171#define HDA_REG_STATESTS 7 /* 0x0E */
172#define HDA_RMX_STATESTS 7
173#define HDA_STATES_SCSF 0x7
174
175#define HDA_REG_GSTS 8 /* 0x10-0x11*/
176#define HDA_RMX_GSTS 8
177#define HDA_GSTS_FSH_SHIFT 1
178
179#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
180#define HDA_RMX_OUTSTRMPAY 112
181
182#define HDA_REG_INSTRMPAY 10 /* 0x1a */
183#define HDA_RMX_INSTRMPAY 113
184
185#define HDA_REG_INTCTL 11 /* 0x20 */
186#define HDA_RMX_INTCTL 9
187#define HDA_INTCTL_GIE_SHIFT 31
188#define HDA_INTCTL_CIE_SHIFT 30
189#define HDA_INTCTL_S0_SHIFT 0
190#define HDA_INTCTL_S1_SHIFT 1
191#define HDA_INTCTL_S2_SHIFT 2
192#define HDA_INTCTL_S3_SHIFT 3
193#define HDA_INTCTL_S4_SHIFT 4
194#define HDA_INTCTL_S5_SHIFT 5
195#define HDA_INTCTL_S6_SHIFT 6
196#define HDA_INTCTL_S7_SHIFT 7
197#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
198
199#define HDA_REG_INTSTS 12 /* 0x24 */
200#define HDA_RMX_INTSTS 10
201#define HDA_INTSTS_GIS_SHIFT 31
202#define HDA_INTSTS_CIS_SHIFT 30
203#define HDA_INTSTS_S0_SHIFT 0
204#define HDA_INTSTS_S1_SHIFT 1
205#define HDA_INTSTS_S2_SHIFT 2
206#define HDA_INTSTS_S3_SHIFT 3
207#define HDA_INTSTS_S4_SHIFT 4
208#define HDA_INTSTS_S5_SHIFT 5
209#define HDA_INTSTS_S6_SHIFT 6
210#define HDA_INTSTS_S7_SHIFT 7
211#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
212
213#define HDA_REG_WALCLK 13 /* 0x30 */
214#define HDA_RMX_WALCLK /* Not defined! */
215
216/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
217 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
218 * the datasheet.
219 */
220#define HDA_REG_SSYNC 14 /* 0x38 */
221#define HDA_RMX_SSYNC 12
222
223#define HDA_REG_CORBLBASE 15 /* 0x40 */
224#define HDA_RMX_CORBLBASE 13
225
226#define HDA_REG_CORBUBASE 16 /* 0x44 */
227#define HDA_RMX_CORBUBASE 14
228
229#define HDA_REG_CORBWP 17 /* 0x48 */
230#define HDA_RMX_CORBWP 15
231
232#define HDA_REG_CORBRP 18 /* 0x4A */
233#define HDA_RMX_CORBRP 16
234#define HDA_CORBRP_RST_SHIFT 15
235#define HDA_CORBRP_WP_SHIFT 0
236#define HDA_CORBRP_WP_MASK 0xFF
237
238#define HDA_REG_CORBCTL 19 /* 0x4C */
239#define HDA_RMX_CORBCTL 17
240#define HDA_CORBCTL_DMA_SHIFT 1
241#define HDA_CORBCTL_CMEIE_SHIFT 0
242
243#define HDA_REG_CORBSTS 20 /* 0x4D */
244#define HDA_RMX_CORBSTS 18
245#define HDA_CORBSTS_CMEI_SHIFT 0
246
247#define HDA_REG_CORBSIZE 21 /* 0x4E */
248#define HDA_RMX_CORBSIZE 19
249#define HDA_CORBSIZE_SZ_CAP 0xF0
250#define HDA_CORBSIZE_SZ 0x3
251/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
252
253#define HDA_REG_RIRBLBASE 22 /* 0x50 */
254#define HDA_RMX_RIRBLBASE 20
255
256#define HDA_REG_RIRBUBASE 23 /* 0x54 */
257#define HDA_RMX_RIRBUBASE 21
258
259#define HDA_REG_RIRBWP 24 /* 0x58 */
260#define HDA_RMX_RIRBWP 22
261#define HDA_RIRBWP_RST_SHIFT 15
262#define HDA_RIRBWP_WP_MASK 0xFF
263
264#define HDA_REG_RINTCNT 25 /* 0x5A */
265#define HDA_RMX_RINTCNT 23
266#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
267
268#define HDA_REG_RIRBCTL 26 /* 0x5C */
269#define HDA_RMX_RIRBCTL 24
270#define HDA_RIRBCTL_RIC_SHIFT 0
271#define HDA_RIRBCTL_DMA_SHIFT 1
272#define HDA_ROI_DMA_SHIFT 2
273
274#define HDA_REG_RIRBSTS 27 /* 0x5D */
275#define HDA_RMX_RIRBSTS 25
276#define HDA_RIRBSTS_RINTFL_SHIFT 0
277#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
278
279#define HDA_REG_RIRBSIZE 28 /* 0x5E */
280#define HDA_RMX_RIRBSIZE 26
281#define HDA_RIRBSIZE_SZ_CAP 0xF0
282#define HDA_RIRBSIZE_SZ 0x3
283
284#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
285#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
286
287
288#define HDA_REG_IC 29 /* 0x60 */
289#define HDA_RMX_IC 27
290
291#define HDA_REG_IR 30 /* 0x64 */
292#define HDA_RMX_IR 28
293
294#define HDA_REG_IRS 31 /* 0x68 */
295#define HDA_RMX_IRS 29
296#define HDA_IRS_ICB_SHIFT 0
297#define HDA_IRS_IRV_SHIFT 1
298
299#define HDA_REG_DPLBASE 32 /* 0x70 */
300#define HDA_RMX_DPLBASE 30
301#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
302
303#define HDA_REG_DPUBASE 33 /* 0x74 */
304#define HDA_RMX_DPUBASE 31
305#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
306
307#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
308
309#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
310#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
311/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
312#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
313
314#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
315
316/** @todo Condense marcos! */
317
318#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80 */
319#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
320#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
321#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
322#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
323#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
324#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
325#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
326#define HDA_RMX_SD0CTL 32
327#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
328#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
329#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
330#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
331#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
332#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
333#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
334
335#define SD(func, num) SD##num##func
336
337#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
338#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
339#define HDA_SDCTL_NUM_MASK 0xF
340#define HDA_SDCTL_NUM_SHIFT 20
341#define HDA_SDCTL_DIR_SHIFT 19
342#define HDA_SDCTL_TP_SHIFT 18
343#define HDA_SDCTL_STRIPE_MASK 0x3
344#define HDA_SDCTL_STRIPE_SHIFT 16
345#define HDA_SDCTL_DEIE_SHIFT 4
346#define HDA_SDCTL_FEIE_SHIFT 3
347#define HDA_SDCTL_ICE_SHIFT 2
348#define HDA_SDCTL_RUN_SHIFT 1
349#define HDA_SDCTL_SRST_SHIFT 0
350
351#define HDA_REG_SD0STS 35 /* 0x83 */
352#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
353#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
354#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
355#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
356#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
357#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
358#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
359#define HDA_RMX_SD0STS 33
360#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
361#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
362#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
363#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
364#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
365#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
366#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
367
368#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
369#define HDA_SDSTS_FIFORDY_SHIFT 5
370#define HDA_SDSTS_DE_SHIFT 4
371#define HDA_SDSTS_FE_SHIFT 3
372#define HDA_SDSTS_BCIS_SHIFT 2
373
374#define HDA_REG_SD0LPIB 36 /* 0x84 */
375#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
376#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
377#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
378#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
379#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
380#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
381#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
382#define HDA_RMX_SD0LPIB 34
383#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
384#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
385#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
386#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
387#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
388#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
389#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
390
391#define HDA_REG_SD0CBL 37 /* 0x88 */
392#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
393#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
394#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
395#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
396#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
397#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
398#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
399#define HDA_RMX_SD0CBL 35
400#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
401#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
402#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
403#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
404#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
405#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
406#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
407
408#define HDA_REG_SD0LVI 38 /* 0x8C */
409#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
410#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
411#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
412#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
413#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
414#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
415#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
416#define HDA_RMX_SD0LVI 36
417#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
418#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
419#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
420#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
421#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
422#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
423#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
424
425#define HDA_REG_SD0FIFOW 39 /* 0x8E */
426#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
427#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
428#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
429#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
430#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
431#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
432#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
433#define HDA_RMX_SD0FIFOW 37
434#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
435#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
436#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
437#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
438#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
439#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
440#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
441
442/*
443 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
444 */
445#define HDA_SDFIFOW_8B 0x2
446#define HDA_SDFIFOW_16B 0x3
447#define HDA_SDFIFOW_32B 0x4
448
449#define HDA_REG_SD0FIFOS 40 /* 0x90 */
450#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
451#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
452#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
453#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
454#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
455#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
456#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
457#define HDA_RMX_SD0FIFOS 38
458#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
459#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
460#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
461#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
462#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
463#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
464#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
465
466/*
467 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
468 * formula: size - 1
469 * Other values not listed are not supported.
470 */
471#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
472#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
473
474#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
475#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
476#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
477#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
478#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
479#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
480#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
481
482#define HDA_REG_SD0FMT 41 /* 0x92 */
483#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
484#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
485#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
486#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
487#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
488#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
489#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
490#define HDA_RMX_SD0FMT 39
491#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
492#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
493#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
494#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
495#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
496#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
497#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
498
499#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
500#define HDA_SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
501#define HDA_SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
502#define HDA_SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
503
504#define HDA_REG_SD0BDPL 42 /* 0x98 */
505#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
506#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
507#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
508#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
509#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
510#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
511#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
512#define HDA_RMX_SD0BDPL 40
513#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
514#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
515#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
516#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
517#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
518#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
519#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
520
521#define HDA_REG_SD0BDPU 43 /* 0x9C */
522#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
523#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
524#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
525#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
526#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
527#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
528#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
529#define HDA_RMX_SD0BDPU 41
530#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
531#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
532#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
533#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
534#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
535#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
536#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
537
538#define HDA_CODEC_CAD_SHIFT 28
539/* Encodes the (required) LUN into a codec command. */
540#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
541
542
543
544/*********************************************************************************************************************************
545* Structures and Typedefs *
546*********************************************************************************************************************************/
547
548/**
549 * Internal state of a Buffer Descriptor List Entry (BDLE),
550 * needed to keep track of the data needed for the actual device
551 * emulation.
552 */
553typedef struct HDABDLESTATE
554{
555 /** Own index within the BDL (Buffer Descriptor List). */
556 uint32_t u32BDLIndex;
557 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
558 * Used to check if we need fill up the FIFO again. */
559 uint32_t cbBelowFIFOW;
560 /** The buffer descriptor's internal DMA buffer. */
561 uint8_t au8FIFO[HDA_SDOFIFO_256B + 1];
562 /** Current offset in DMA buffer (in bytes).*/
563 uint32_t u32BufOff;
564 uint32_t Padding;
565} HDABDLESTATE, *PHDABDLESTATE;
566
567/**
568 * Buffer Descriptor List Entry (BDLE) (3.6.3).
569 *
570 * Contains only register values which do *not* change until a
571 * stream reset occurs.
572 */
573typedef struct HDABDLE
574{
575 /** Starting address of the actual buffer. Must be 128-bit aligned. */
576 uint64_t u64BufAdr;
577 /** Size of the actual buffer (in bytes). */
578 uint32_t u32BufSize;
579 /** Interrupt on completion; the controller will generate
580 * an interrupt when the last byte of the buffer has been
581 * fetched by the DMA engine. */
582 bool fIntOnCompletion;
583 /** Internal state of this BDLE.
584 * Not part of the actual BDLE registers. */
585 HDABDLESTATE State;
586} HDABDLE, *PHDABDLE;
587
588/**
589 * Structure for keeping an audio stream data mapping.
590 */
591typedef struct HDASTREAMMAPPING
592{
593 /** The stream's layout. */
594 PDMAUDIOSTREAMLAYOUT enmLayout;
595 /** Number of audio channels in this stream. */
596 uint8_t cChannels;
597 /** Array audio channels. */
598 R3PTRTYPE(PPDMAUDIOSTREAMCHANNEL) paChannels;
599 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
600} HDASTREAMMAPPING, *PHDASTREAMMAPPING;
601
602/**
603 * Internal state of a HDA stream.
604 */
605typedef struct HDASTREAMSTATE
606{
607 /** Current BDLE to use. Wraps around to 0 if
608 * maximum (cBDLE) is reached. */
609 uint16_t uCurBDLE;
610 /** Stop indicator. */
611 volatile bool fDoStop;
612 /** Flag indicating whether this stream is in an
613 * active (operative) state or not. */
614 volatile bool fActive;
615 /** Flag indicating whether this stream currently is
616 * in reset mode and therefore not acccessible by the guest. */
617 volatile bool fInReset;
618 /** Unused, padding. */
619 bool fPadding;
620 /** Mutex semaphore handle to serialize access. */
621 RTSEMMUTEX hMtx;
622 /** Event signalling that the stream's state has been changed. */
623 RTSEMEVENT hStateChangedEvent;
624 /** This stream's data mapping. */
625 HDASTREAMMAPPING Mapping;
626 /** Current BDLE (Buffer Descriptor List Entry). */
627 HDABDLE BDLE;
628} HDASTREAMSTATE, *PHDASTREAMSTATE;
629
630/**
631 * Structure defining an HDA mixer sink.
632 * Its purpose is to know which audio mixer sink is bound to
633 * which SDn (SDI/SDO) device stream.
634 *
635 * This is needed in order to handle interleaved streams
636 * (that is, multiple channels in one stream) or non-interleaved
637 * streams (each channel has a dedicated stream).
638 *
639 * This is only known to the actual device emulation level.
640 */
641typedef struct HDAMIXERSINK
642{
643 /** SDn ID this sink is assigned to. 0 if not assigned. */
644 uint8_t uSD;
645 /** Channel ID of SDn ID. Only valid if SDn ID is valid. */
646 uint8_t uChannel;
647 uint8_t Padding[3];
648 /** Pointer to the actual audio mixer sink. */
649 R3PTRTYPE(PAUDMIXSINK) pMixSink;
650} HDAMIXERSINK, *PHDAMIXERSINK;
651
652/**
653 * Structure for keeping a HDA stream state.
654 *
655 * Contains only register values which do *not* change until a
656 * stream reset occurs.
657 */
658typedef struct HDASTREAM
659{
660 /** Stream descriptor number (SDn). */
661 uint8_t u8SD;
662 uint8_t Padding0[7];
663 /** DMA base address (SDnBDPU - SDnBDPL). */
664 uint64_t u64BDLBase;
665 /** Cyclic Buffer Length (SDnCBL).
666 * Represents the size of the ring buffer. */
667 uint32_t u32CBL;
668 /** Format (SDnFMT). */
669 uint16_t u16FMT;
670 /** FIFO Size (FIFOS).
671 * Maximum number of bytes that may have been DMA'd into
672 * memory but not yet transmitted on the link.
673 *
674 * Must be a power of two. */
675 uint16_t u16FIFOS;
676 /** Last Valid Index (SDnLVI). */
677 uint16_t u16LVI;
678 uint16_t Padding1[3];
679 /** Pointer to HDA sink this stream is attached to. */
680 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
681 /** Internal state of this stream. */
682 HDASTREAMSTATE State;
683} HDASTREAM, *PHDASTREAM;
684
685/**
686 * Structure for mapping a stream tag to an HDA stream.
687 */
688typedef struct HDATAG
689{
690 /** Own stream tag. */
691 uint8_t uTag;
692 uint8_t Padding[7];
693 /** Pointer to associated stream. */
694 R3PTRTYPE(PHDASTREAM) pStrm;
695} HDATAG, *PHDATAG;
696
697/**
698 * Structure defining an HDA mixer stream.
699 * This is being used together with an audio mixer instance.
700 */
701typedef struct HDAMIXERSTREAM
702{
703 union
704 {
705 /** Desired playback destination (for an output stream). */
706 PDMAUDIOPLAYBACKDEST Dest;
707 /** Desired recording source (for an input stream). */
708 PDMAUDIORECSOURCE Source;
709 } DestSource;
710 uint8_t Padding1[4];
711 /** Associated mixer handle. */
712 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
713} HDAMIXERSTREAM, *PHDAMIXERSTREAM;
714
715/**
716 * Struct for maintaining a host backend driver.
717 * This driver must be associated to one, and only one,
718 * HDA codec. The HDA controller does the actual multiplexing
719 * of HDA codec data to various host backend drivers then.
720 *
721 * This HDA device uses a timer in order to synchronize all
722 * read/write accesses across all attached LUNs / backends.
723 */
724typedef struct HDADRIVER
725{
726 /** Node for storing this driver in our device driver list of HDASTATE. */
727 RTLISTNODER3 Node;
728 /** Pointer to HDA controller (state). */
729 R3PTRTYPE(PHDASTATE) pHDAState;
730 /** Driver flags. */
731 PDMAUDIODRVFLAGS Flags;
732 uint8_t u32Padding0[2];
733 /** LUN to which this driver has been assigned. */
734 uint8_t uLUN;
735 /** Whether this driver is in an attached state or not. */
736 bool fAttached;
737 /** Pointer to attached driver base interface. */
738 R3PTRTYPE(PPDMIBASE) pDrvBase;
739 /** Audio connector interface to the underlying host backend. */
740 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
741 /** Mixer stream for line input. */
742 HDAMIXERSTREAM LineIn;
743#ifdef VBOX_WITH_HDA_MIC_IN
744 /** Mixer stream for mic input. */
745 HDAMIXERSTREAM MicIn;
746#endif
747 /** Mixer stream for front output. */
748 HDAMIXERSTREAM Front;
749#ifdef VBOX_WITH_HDA_51_SURROUND
750 /** Mixer stream for center/LFE output. */
751 HDAMIXERSTREAM CenterLFE;
752 /** Mixer stream for rear output. */
753 HDAMIXERSTREAM Rear;
754#endif
755} HDADRIVER;
756
757/**
758 * ICH Intel HD Audio Controller state.
759 */
760typedef struct HDASTATE
761{
762 /** The PCI device structure. */
763 PCIDevice PciDev;
764 /** R3 Pointer to the device instance. */
765 PPDMDEVINSR3 pDevInsR3;
766 /** R0 Pointer to the device instance. */
767 PPDMDEVINSR0 pDevInsR0;
768 /** R0 Pointer to the device instance. */
769 PPDMDEVINSRC pDevInsRC;
770 /** Padding for alignment. */
771 uint32_t u32Padding;
772 /** The base interface for LUN\#0. */
773 PDMIBASE IBase;
774 RTGCPHYS MMIOBaseAddr;
775 /** The HDA's register set. */
776 uint32_t au32Regs[HDA_NUM_REGS];
777 /** Internal stream states. */
778 HDASTREAM aStreams[HDA_MAX_STREAMS];
779 /** Mapping table between stream tags and stream states. */
780 HDATAG aTags[HDA_MAX_TAGS];
781 /** CORB buffer base address. */
782 uint64_t u64CORBBase;
783 /** RIRB buffer base address. */
784 uint64_t u64RIRBBase;
785 /** DMA base address.
786 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
787 uint64_t u64DPBase;
788 /** DMA position buffer enable bit. */
789 bool fDMAPosition;
790 /** Padding for alignment. */
791 uint8_t u8Padding0[7];
792 /** Pointer to CORB buffer. */
793 R3PTRTYPE(uint32_t *) pu32CorbBuf;
794 /** Size in bytes of CORB buffer. */
795 uint32_t cbCorbBuf;
796 /** Padding for alignment. */
797 uint32_t u32Padding1;
798 /** Pointer to RIRB buffer. */
799 R3PTRTYPE(uint64_t *) pu64RirbBuf;
800 /** Size in bytes of RIRB buffer. */
801 uint32_t cbRirbBuf;
802 /** Indicates if HDA controller is in reset mode. */
803 bool fInReset;
804 /** Flag whether the R0 part is enabled. */
805 bool fR0Enabled;
806 /** Flag whether the RC part is enabled. */
807 bool fRCEnabled;
808 /** Number of active (running) SDn streams. */
809 uint8_t cStreamsActive;
810#ifndef VBOX_WITH_AUDIO_CALLBACKS
811 /** The timer for pumping data thru the attached LUN drivers. */
812 PTMTIMERR3 pTimer;
813 /** Flag indicating whether the timer is active or not. */
814 bool fTimerActive;
815 uint8_t u8Padding1[7];
816 /** Timer ticks per Hz. */
817 uint64_t cTimerTicks;
818 /** Timestamp of the last timer callback (hdaTimer).
819 * Used to calculate the time actually elapsed between two timer callbacks. */
820 uint64_t uTimerTS;
821#endif
822#ifdef VBOX_WITH_STATISTICS
823# ifndef VBOX_WITH_AUDIO_CALLBACKS
824 STAMPROFILE StatTimer;
825# endif
826 STAMCOUNTER StatBytesRead;
827 STAMCOUNTER StatBytesWritten;
828#endif
829 /** Pointer to HDA codec to use. */
830 R3PTRTYPE(PHDACODEC) pCodec;
831 /** List of associated LUN drivers (HDADRIVER). */
832 RTLISTANCHORR3 lstDrv;
833 /** The device' software mixer. */
834 R3PTRTYPE(PAUDIOMIXER) pMixer;
835 /** HDA sink for (front) output. */
836 HDAMIXERSINK SinkFront;
837#ifdef VBOX_WITH_HDA_51_SURROUND
838 /** HDA sink for center / LFE output. */
839 HDAMIXERSINK SinkCenterLFE;
840 /** HDA sink for rear output. */
841 HDAMIXERSINK SinkRear;
842#endif
843 /** HDA mixer sink for line input. */
844 HDAMIXERSINK SinkLineIn;
845#ifdef VBOX_WITH_HDA_MIC_IN
846 /** Audio mixer sink for microphone input. */
847 HDAMIXERSINK SinkMicIn;
848#endif
849 uint64_t u64BaseTS;
850 /** Response Interrupt Count (RINTCNT). */
851 uint8_t u8RespIntCnt;
852 /** Padding for alignment. */
853 uint8_t au8Padding2[7];
854} HDASTATE;
855/** Pointer to the ICH Intel HD Audio Controller state. */
856typedef HDASTATE *PHDASTATE;
857
858#ifdef VBOX_WITH_AUDIO_CALLBACKS
859typedef struct HDACALLBACKCTX
860{
861 PHDASTATE pThis;
862 PHDADRIVER pDriver;
863} HDACALLBACKCTX, *PHDACALLBACKCTX;
864#endif
865
866/*********************************************************************************************************************************
867* Internal Functions *
868*********************************************************************************************************************************/
869#ifndef VBOX_DEVICE_STRUCT_TESTCASE
870static FNPDMDEVRESET hdaReset;
871
872/*
873 * Stubs.
874 */
875static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
876static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
877
878/*
879 * Global register set read/write functions.
880 */
881static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
882static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
883static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
884static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
885static int hdaRegReadSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
886static int hdaRegWriteSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
887static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
888static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
889static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
890static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
891static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
892static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
893static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
894static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
895static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
896static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
897static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
898
899/*
900 * {IOB}SDn read/write functions.
901 */
902static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
903static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
904static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
905static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
906static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
907static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
908static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
909static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
910static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
911DECLINLINE(int) hdaRegWriteSDLock(PHDASTATE pThis, PHDASTREAM pStream, uint32_t iReg, uint32_t u32Value);
912DECLINLINE(void) hdaRegWriteSDUnlock(PHDASTREAM pStream);
913
914/*
915 * Generic register read/write functions.
916 */
917static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
918static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
919static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
920static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
921static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
922static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
923static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
924static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
925
926#ifdef IN_RING3
927static void hdaStreamDestroy(PHDASTREAM pStream);
928static int hdaStreamSetActive(PHDASTATE pThis, PHDASTREAM pStream, bool fActive);
929static int hdaStreamStart(PHDASTREAM pStream);
930static int hdaStreamStop(PHDASTREAM pStream);
931static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout);
932static int hdaTransfer(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToProcess, uint32_t *pcbProcessed);
933#endif
934
935#ifdef IN_RING3
936static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg);
937static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping);
938static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping);
939#endif
940
941#ifdef IN_RING3
942static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
943DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB);
944# ifdef LOG_ENABLED
945static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE);
946# endif
947#endif
948static int hdaProcessInterrupt(PHDASTATE pThis);
949
950/*
951 * Timer routines.
952 */
953#ifndef VBOX_WITH_AUDIO_CALLBACKS
954static void hdaTimerMaybeStart(PHDASTATE pThis);
955static void hdaTimerMaybeStop(PHDASTATE pThis);
956static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
957#endif
958
959/*********************************************************************************************************************************
960* Global Variables *
961*********************************************************************************************************************************/
962
963/** Offset of the SD0 register map. */
964#define HDA_REG_DESC_SD0_BASE 0x80
965
966/** Turn a short global register name into an memory index and a stringized name. */
967#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
968
969/** Turns a short stream register name into an memory index and a stringized name. */
970#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
971
972/** Same as above for a register *not* stored in memory. */
973#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
974
975/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
976#define HDA_REG_MAP_STRM(offset, name) \
977 /* offset size read mask write mask read callback write callback index + abbrev description */ \
978 /* ------- ------- ---------- ---------- -------------- ----------------- ------------------------------ ----------- */ \
979 /* Offset 0x80 (SD0) */ \
980 { offset, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
981 /* Offset 0x83 (SD0) */ \
982 { offset + 0x3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
983 /* Offset 0x84 (SD0) */ \
984 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
985 /* Offset 0x88 (SD0) */ \
986 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
987 /* Offset 0x8C (SD0) */ \
988 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
989 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
990 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteU16, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
991 /* Offset 0x90 (SD0) */ \
992 { offset + 0x10, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16, hdaRegWriteU16, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
993 /* Offset 0x92 (SD0) */ \
994 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
995 /* Reserved: 0x94 - 0x98. */ \
996 /* Offset 0x98 (SD0) */ \
997 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
998 /* Offset 0x9C (SD0) */ \
999 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
1000
1001/** Defines a single audio stream register set (e.g. OSD0). */
1002#define HDA_REG_MAP_DEF_STREAM(index, name) \
1003 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
1004
1005/* See 302349 p 6.2. */
1006static const struct HDAREGDESC
1007{
1008 /** Register offset in the register space. */
1009 uint32_t offset;
1010 /** Size in bytes. Registers of size > 4 are in fact tables. */
1011 uint32_t size;
1012 /** Readable bits. */
1013 uint32_t readable;
1014 /** Writable bits. */
1015 uint32_t writable;
1016 /** Read callback. */
1017 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
1018 /** Write callback. */
1019 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
1020 /** Index into the register storage array. */
1021 uint32_t mem_idx;
1022 /** Abbreviated name. */
1023 const char *abbrev;
1024 /** Descripton. */
1025 const char *desc;
1026} g_aHdaRegMap[HDA_NUM_REGS] =
1027
1028{
1029 /* offset size read mask write mask read callback write callback index + abbrev */
1030 /*------- ------- ---------- ---------- ----------------------- ---------------------- ---------------- */
1031 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
1032 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
1033 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
1034 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
1035 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
1036 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
1037 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
1038 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , HDA_REG_IDX(STATESTS) }, /* State Change Status */
1039 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
1040 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
1041 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
1042 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
1043 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
1044 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
1045 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
1046 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
1047 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
1048 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
1049 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
1050 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
1051 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
1052 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
1053 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
1054 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
1055 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
1056 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
1057 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
1058 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
1059 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
1060 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
1061 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
1062 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
1063 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
1064 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
1065 /* 4 Serial Data In (SDI). */
1066 HDA_REG_MAP_DEF_STREAM(0, SD0),
1067 HDA_REG_MAP_DEF_STREAM(1, SD1),
1068 HDA_REG_MAP_DEF_STREAM(2, SD2),
1069 HDA_REG_MAP_DEF_STREAM(3, SD3),
1070 /* 4 Serial Data Out (SDO). */
1071 HDA_REG_MAP_DEF_STREAM(4, SD4),
1072 HDA_REG_MAP_DEF_STREAM(5, SD5),
1073 HDA_REG_MAP_DEF_STREAM(6, SD6),
1074 HDA_REG_MAP_DEF_STREAM(7, SD7)
1075};
1076
1077/**
1078 * HDA register aliases (HDA spec 3.3.45).
1079 * @remarks Sorted by offReg.
1080 */
1081static const struct
1082{
1083 /** The alias register offset. */
1084 uint32_t offReg;
1085 /** The register index. */
1086 int idxAlias;
1087} g_aHdaRegAliases[] =
1088{
1089 { 0x2084, HDA_REG_SD0LPIB },
1090 { 0x20a4, HDA_REG_SD1LPIB },
1091 { 0x20c4, HDA_REG_SD2LPIB },
1092 { 0x20e4, HDA_REG_SD3LPIB },
1093 { 0x2104, HDA_REG_SD4LPIB },
1094 { 0x2124, HDA_REG_SD5LPIB },
1095 { 0x2144, HDA_REG_SD6LPIB },
1096 { 0x2164, HDA_REG_SD7LPIB },
1097};
1098
1099#ifdef IN_RING3
1100/** HDABDLE field descriptors for the v6+ saved state. */
1101static SSMFIELD const g_aSSMBDLEFields6[] =
1102{
1103 SSMFIELD_ENTRY(HDABDLE, u64BufAdr),
1104 SSMFIELD_ENTRY(HDABDLE, u32BufSize),
1105 SSMFIELD_ENTRY(HDABDLE, fIntOnCompletion),
1106 SSMFIELD_ENTRY_TERM()
1107};
1108
1109/** HDABDLESTATE field descriptors for the v6+ saved state. */
1110static SSMFIELD const g_aSSMBDLEStateFields6[] =
1111{
1112 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
1113 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
1114 SSMFIELD_ENTRY(HDABDLESTATE, au8FIFO),
1115 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
1116 SSMFIELD_ENTRY_TERM()
1117};
1118
1119/** HDASTREAMSTATE field descriptors for the v6+ saved state. */
1120static SSMFIELD const g_aSSMStreamStateFields6[] =
1121{
1122 SSMFIELD_ENTRY_OLD(cBDLE, 2),
1123 SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
1124 SSMFIELD_ENTRY(HDASTREAMSTATE, fDoStop),
1125 SSMFIELD_ENTRY(HDASTREAMSTATE, fActive),
1126 SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
1127 SSMFIELD_ENTRY_TERM()
1128};
1129#endif
1130
1131/**
1132 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1133 */
1134static uint32_t const g_afMasks[5] =
1135{
1136 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1137};
1138
1139#ifdef IN_RING3
1140DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB)
1141{
1142 AssertPtrReturn(pThis, 0);
1143 AssertPtrReturn(pStream, 0);
1144
1145 Assert(u32LPIB <= pStream->u32CBL);
1146
1147 LogFlowFunc(("[SD%RU8]: LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1148 pStream->u8SD, u32LPIB, pThis->fDMAPosition));
1149
1150 /* Update LPIB in any case. */
1151 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) = u32LPIB;
1152
1153 /* Do we need to tell the current DMA position? */
1154 if (pThis->fDMAPosition)
1155 {
1156 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1157 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStream->u8SD * 2 * sizeof(uint32_t)),
1158 (void *)&u32LPIB, sizeof(uint32_t));
1159 AssertRC(rc2);
1160 }
1161
1162 return u32LPIB;
1163}
1164#endif
1165
1166/**
1167 * Retrieves the number of bytes of a FIFOS register.
1168 *
1169 * @return Number of bytes of a given FIFOS register.
1170 */
1171DECLINLINE(uint16_t) hdaSDFIFOSToBytes(uint32_t u32RegFIFOS)
1172{
1173 uint16_t cb;
1174 switch (u32RegFIFOS)
1175 {
1176 /* Input */
1177 case HDA_SDIFIFO_120B: cb = 120; break;
1178 case HDA_SDIFIFO_160B: cb = 160; break;
1179
1180 /* Output */
1181 case HDA_SDOFIFO_16B: cb = 16; break;
1182 case HDA_SDOFIFO_32B: cb = 32; break;
1183 case HDA_SDOFIFO_64B: cb = 64; break;
1184 case HDA_SDOFIFO_128B: cb = 128; break;
1185 case HDA_SDOFIFO_192B: cb = 192; break;
1186 case HDA_SDOFIFO_256B: cb = 256; break;
1187 default:
1188 {
1189 cb = 0; /* Can happen on stream reset. */
1190 break;
1191 }
1192 }
1193
1194 return cb;
1195}
1196
1197/**
1198 * Retrieves the number of bytes of a FIFOW register.
1199 *
1200 * @return Number of bytes of a given FIFOW register.
1201 */
1202DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1203{
1204 uint32_t cb;
1205 switch (u32RegFIFOW)
1206 {
1207 case HDA_SDFIFOW_8B: cb = 8; break;
1208 case HDA_SDFIFOW_16B: cb = 16; break;
1209 case HDA_SDFIFOW_32B: cb = 32; break;
1210 default: cb = 0; break;
1211 }
1212
1213#ifdef RT_STRICT
1214 Assert(RT_IS_POWER_OF_TWO(cb));
1215#endif
1216 return cb;
1217}
1218
1219#ifdef IN_RING3
1220/**
1221 * Fetches the next BDLE to use for a stream.
1222 *
1223 * @return IPRT status code.
1224 */
1225DECLINLINE(int) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
1226{
1227 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1228 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1229
1230 NOREF(pThis);
1231
1232 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1233
1234 LogFlowFuncEnter();
1235
1236#ifdef DEBUG
1237 uint32_t uOldBDLE = pStream->State.uCurBDLE;
1238#endif
1239
1240 PHDABDLE pBDLE = &pStream->State.BDLE;
1241
1242 /*
1243 * Switch to the next BDLE entry and do a wrap around
1244 * if we reached the end of the Buffer Descriptor List (BDL).
1245 */
1246 pStream->State.uCurBDLE++;
1247 if (pStream->State.uCurBDLE == pStream->u16LVI + 1)
1248 {
1249 pStream->State.uCurBDLE = 0;
1250
1251 hdaStreamUpdateLPIB(pThis, pStream, 0);
1252 }
1253
1254 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1255
1256 /* Fetch the next BDLE entry. */
1257 int rc = hdaBDLEFetch(pThis, pBDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
1258
1259#ifdef DEBUG
1260 LogFlowFunc(("[SD%RU8]: uOldBDLE=%RU16, uCurBDLE=%RU16, LVI=%RU32, rc=%Rrc, %R[bdle]\n",
1261 pStream->u8SD, uOldBDLE, pStream->State.uCurBDLE, pStream->u16LVI, rc, pBDLE));
1262#endif
1263
1264 return rc;
1265}
1266#endif /* IN_RING3 */
1267
1268/**
1269 * Returns the audio direction of a specified stream descriptor.
1270 *
1271 * The register layout specifies that input streams (SDI) come first,
1272 * followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
1273 * is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
1274 *
1275 * Note: SDnFMT register does not provide that information, so we have to judge
1276 * for ourselves.
1277 *
1278 * @return Audio direction.
1279 */
1280DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
1281{
1282 AssertReturn(uSD <= HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
1283
1284 if (uSD < HDA_MAX_SDI)
1285 return PDMAUDIODIR_IN;
1286
1287 return PDMAUDIODIR_OUT;
1288}
1289
1290/**
1291 * Returns the HDA stream of specified stream descriptor number.
1292 *
1293 * @return Pointer to HDA stream, or NULL if none found.
1294 */
1295DECLINLINE(PHDASTREAM) hdaStreamFromSD(PHDASTATE pThis, uint8_t uSD)
1296{
1297 AssertPtrReturn(pThis, NULL);
1298 AssertReturn(uSD <= HDA_MAX_STREAMS, NULL);
1299
1300 if (uSD >= HDA_MAX_STREAMS)
1301 return NULL;
1302
1303 return &pThis->aStreams[uSD];
1304}
1305
1306/**
1307 * Returns the HDA stream of specified HDA sink.
1308 *
1309 * @return Pointer to HDA stream, or NULL if none found.
1310 */
1311DECLINLINE(PHDASTREAM) hdaGetStreamFromSink(PHDASTATE pThis, PHDAMIXERSINK pSink)
1312{
1313 AssertPtrReturn(pThis, NULL);
1314 AssertPtrReturn(pSink, NULL);
1315
1316 /** @todo Do something with the channel mapping here? */
1317 return hdaStreamFromSD(pThis, pSink->uSD);
1318}
1319
1320/**
1321 * Retrieves the minimum number of bytes accumulated/free in the
1322 * FIFO before the controller will start a fetch/eviction of data.
1323 *
1324 * Uses SDFIFOW (FIFO Watermark Register).
1325 *
1326 * @return Number of bytes accumulated/free in the FIFO.
1327 */
1328DECLINLINE(uint8_t) hdaStreamGetFIFOW(PHDASTATE pThis, PHDASTREAM pStream)
1329{
1330 AssertPtrReturn(pThis, 0);
1331 AssertPtrReturn(pStream, 0);
1332
1333#ifdef VBOX_HDA_WITH_FIFO
1334 return hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, pStream->u8SD));
1335#else
1336 return 0;
1337#endif
1338}
1339
1340static int hdaProcessInterrupt(PHDASTATE pThis)
1341{
1342#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1343 ( INTCTL_SX((pThis), num) \
1344 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1345
1346 int iLevel = 0;
1347
1348 /** @todo Optimize IRQ handling. */
1349
1350 if (/* Controller Interrupt Enable (CIE). */
1351 HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1352 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1353 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1354 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1355 {
1356 iLevel = 1;
1357 }
1358
1359 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1360 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 1)
1361 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 2)
1362 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 3)
1363 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4)
1364 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 5)
1365 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 6)
1366 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 7))
1367 {
1368 iLevel = 1;
1369 }
1370
1371 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1372 {
1373 Log3Func(("Level=%d\n", iLevel));
1374 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , iLevel);
1375 }
1376
1377#undef IS_INTERRUPT_OCCURED_AND_ENABLED
1378
1379 return VINF_SUCCESS;
1380}
1381
1382/**
1383 * Looks up a register at the exact offset given by @a offReg.
1384 *
1385 * @returns Register index on success, -1 if not found.
1386 * @param pThis The HDA device state.
1387 * @param offReg The register offset.
1388 */
1389static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1390{
1391 /*
1392 * Aliases.
1393 */
1394 if (offReg >= g_aHdaRegAliases[0].offReg)
1395 {
1396 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1397 if (offReg == g_aHdaRegAliases[i].offReg)
1398 return g_aHdaRegAliases[i].idxAlias;
1399 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1400 return -1;
1401 }
1402
1403 /*
1404 * Binary search the
1405 */
1406 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1407 int idxLow = 0;
1408 for (;;)
1409 {
1410 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1411 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1412 {
1413 if (idxLow == idxMiddle)
1414 break;
1415 idxEnd = idxMiddle;
1416 }
1417 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1418 {
1419 idxLow = idxMiddle + 1;
1420 if (idxLow >= idxEnd)
1421 break;
1422 }
1423 else
1424 return idxMiddle;
1425 }
1426
1427#ifdef RT_STRICT
1428 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1429 Assert(g_aHdaRegMap[i].offset != offReg);
1430#endif
1431 return -1;
1432}
1433
1434/**
1435 * Looks up a register covering the offset given by @a offReg.
1436 *
1437 * @returns Register index on success, -1 if not found.
1438 * @param pThis The HDA device state.
1439 * @param offReg The register offset.
1440 */
1441static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1442{
1443 /*
1444 * Aliases.
1445 */
1446 if (offReg >= g_aHdaRegAliases[0].offReg)
1447 {
1448 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1449 {
1450 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1451 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1452 return g_aHdaRegAliases[i].idxAlias;
1453 }
1454 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1455 return -1;
1456 }
1457
1458 /*
1459 * Binary search the register map.
1460 */
1461 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1462 int idxLow = 0;
1463 for (;;)
1464 {
1465 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1466 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1467 {
1468 if (idxLow == idxMiddle)
1469 break;
1470 idxEnd = idxMiddle;
1471 }
1472 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1473 {
1474 idxLow = idxMiddle + 1;
1475 if (idxLow >= idxEnd)
1476 break;
1477 }
1478 else
1479 return idxMiddle;
1480 }
1481
1482#ifdef RT_STRICT
1483 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1484 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1485#endif
1486 return -1;
1487}
1488
1489#ifdef IN_RING3
1490static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1491{
1492 int rc = VINF_SUCCESS;
1493 if (fLocal)
1494 {
1495 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1496 Assert(pThis->u64CORBBase);
1497 AssertPtr(pThis->pu32CorbBuf);
1498 Assert(pThis->cbCorbBuf);
1499
1500 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1501 if (RT_FAILURE(rc))
1502 AssertRCReturn(rc, rc);
1503#ifdef DEBUG_CMD_BUFFER
1504 uint8_t i = 0;
1505 do
1506 {
1507 LogFunc(("CORB%02x: ", i));
1508 uint8_t j = 0;
1509 do
1510 {
1511 const char *pszPrefix;
1512 if ((i + j) == HDA_REG(pThis, CORBRP));
1513 pszPrefix = "[R]";
1514 else if ((i + j) == HDA_REG(pThis, CORBWP));
1515 pszPrefix = "[W]";
1516 else
1517 pszPrefix = " "; /* three spaces */
1518 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1519 j++;
1520 } while (j < 8);
1521 LogFunc(("\n"));
1522 i += 8;
1523 } while(i != 0);
1524#endif
1525 }
1526 else
1527 {
1528 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1529 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1530 if (RT_FAILURE(rc))
1531 AssertRCReturn(rc, rc);
1532#ifdef DEBUG_CMD_BUFFER
1533 uint8_t i = 0;
1534 do {
1535 LogFunc(("RIRB%02x: ", i));
1536 uint8_t j = 0;
1537 do {
1538 const char *prefix;
1539 if ((i + j) == HDA_REG(pThis, RIRBWP))
1540 prefix = "[W]";
1541 else
1542 prefix = " ";
1543 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1544 } while (++j < 8);
1545 LogFunc(("\n"));
1546 i += 8;
1547 } while (i != 0);
1548#endif
1549 }
1550 return rc;
1551}
1552
1553static int hdaCORBCmdProcess(PHDASTATE pThis)
1554{
1555 int rc = hdaCmdSync(pThis, true);
1556 if (RT_FAILURE(rc))
1557 AssertRCReturn(rc, rc);
1558
1559 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1560 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1561 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1562
1563 Assert((corbWp != corbRp));
1564 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1565
1566 while (corbRp != corbWp)
1567 {
1568 uint64_t uResp;
1569 uint32_t uCmd = pThis->pu32CorbBuf[++corbRp];
1570
1571 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
1572 if (RT_FAILURE(rc2))
1573 LogFunc(("Codec lookup failed with rc=%Rrc\n", rc2));
1574
1575 (rirbWp)++;
1576
1577 if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
1578 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1579 {
1580 LogFunc(("Unexpected unsolicited response\n"));
1581 HDA_REG(pThis, CORBRP) = corbRp;
1582 return rc;
1583 }
1584
1585 pThis->pu64RirbBuf[rirbWp] = uResp;
1586
1587 pThis->u8RespIntCnt++;
1588 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1589 break;
1590 }
1591
1592 HDA_REG(pThis, CORBRP) = corbRp;
1593 HDA_REG(pThis, RIRBWP) = rirbWp;
1594
1595 rc = hdaCmdSync(pThis, false);
1596
1597 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1598
1599 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1600 {
1601 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1602
1603 pThis->u8RespIntCnt = 0;
1604 rc = hdaProcessInterrupt(pThis);
1605 }
1606
1607 if (RT_FAILURE(rc))
1608 AssertRCReturn(rc, rc);
1609 return rc;
1610}
1611
1612static int hdaStreamCreate(PHDASTREAM pStream, uint8_t uSD)
1613{
1614 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1615 AssertReturn(uSD <= HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
1616
1617 int rc = RTSemEventCreate(&pStream->State.hStateChangedEvent);
1618 if (RT_SUCCESS(rc))
1619 rc = RTSemMutexCreate(&pStream->State.hMtx);
1620
1621 if (RT_SUCCESS(rc))
1622 {
1623 pStream->u8SD = uSD;
1624 pStream->pMixSink = NULL;
1625
1626 pStream->State.fActive = false;
1627 pStream->State.fInReset = false;
1628 pStream->State.fDoStop = false;
1629 }
1630
1631 LogFlowFunc(("uSD=%RU8\n", uSD));
1632 return rc;
1633}
1634
1635static void hdaStreamDestroy(PHDASTREAM pStream)
1636{
1637 AssertPtrReturnVoid(pStream);
1638
1639 LogFlowFunc(("[SD%RU8]: Destroying ...\n", pStream->u8SD));
1640
1641 int rc2 = hdaStreamStop(pStream);
1642 AssertRC(rc2);
1643
1644 hdaStreamMapDestroy(&pStream->State.Mapping);
1645
1646 if (pStream->State.hMtx != NIL_RTSEMMUTEX)
1647 {
1648 rc2 = RTSemMutexDestroy(pStream->State.hMtx);
1649 AssertRC(rc2);
1650 pStream->State.hMtx = NIL_RTSEMMUTEX;
1651 }
1652
1653 if (pStream->State.hStateChangedEvent != NIL_RTSEMEVENT)
1654 {
1655 rc2 = RTSemEventDestroy(pStream->State.hStateChangedEvent);
1656 AssertRC(rc2);
1657 pStream->State.hStateChangedEvent = NIL_RTSEMEVENT;
1658 }
1659
1660 LogFlowFuncLeave();
1661}
1662
1663static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStream, uint8_t u8SD)
1664{
1665 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1666 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1667
1668 pStream->u8SD = u8SD;
1669 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1670 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1671 pStream->u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1672 pStream->u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1673 pStream->u16FIFOS = hdaSDFIFOSToBytes(HDA_STREAM_REG(pThis, FIFOS, pStream->u8SD));
1674
1675 RT_ZERO(pStream->State.BDLE);
1676 pStream->State.uCurBDLE = 0;
1677
1678 hdaStreamMapReset(&pStream->State.Mapping);
1679
1680 LogFlowFunc(("[SD%RU8]: DMA @ 0x%x (%RU32 bytes), LVI=%RU16, FIFOS=%RU16\n",
1681 pStream->u8SD, pStream->u64BDLBase, pStream->u32CBL, pStream->u16LVI, pStream->u16FIFOS));
1682
1683#ifdef DEBUG
1684 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1685 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1686 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1687 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1688
1689 LogFlowFunc(("\t-> DMA @ 0x%x, LVI=%RU16, CBL=%RU32\n", u64BaseDMA, u16LVI, u32CBL));
1690
1691 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
1692#endif
1693
1694 return VINF_SUCCESS;
1695}
1696
1697static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStream)
1698{
1699 AssertPtrReturnVoid(pThis);
1700 AssertPtrReturnVoid(pStream);
1701
1702 const uint8_t uSD = pStream->u8SD;
1703
1704#ifdef VBOX_STRICT
1705 AssertReleaseMsg(!RT_BOOL(HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
1706 ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
1707#endif
1708
1709 LogFunc(("[SD%RU8]: Reset\n", uSD));
1710
1711 /*
1712 * Set reset state.
1713 */
1714 Assert(ASMAtomicReadBool(&pStream->State.fInReset) == false); /* No nested calls. */
1715 ASMAtomicXchgBool(&pStream->State.fInReset, true);
1716
1717 /*
1718 * First, reset the internal stream state.
1719 */
1720 RT_ZERO(pStream->State.BDLE);
1721 pStream->State.uCurBDLE = 0;
1722
1723 /*
1724 * Second, initialize the registers.
1725 */
1726 HDA_STREAM_REG(pThis, STS, uSD) = HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1727 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1728 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1729 HDA_STREAM_REG(pThis, CTL, uSD) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1730 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39. */
1731 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
1732 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1733 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
1734 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
1735 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
1736 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
1737 HDA_STREAM_REG(pThis, FMT, uSD) = HDA_SDFMT_MAKE(HDA_SDFMT_TYPE_PCM, HDA_SDFMT_BASE_44KHZ,
1738 HDA_SDFMT_MULT_1X, HDA_SDFMT_DIV_1X, HDA_SDFMT_16_BIT,
1739 HDA_SDFMT_CHAN_STEREO);
1740 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
1741 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
1742
1743 int rc2 = hdaStreamInit(pThis, pStream, uSD);
1744 AssertRC(rc2);
1745
1746 /* Report that we're done resetting this stream. */
1747 HDA_STREAM_REG(pThis, CTL, uSD) = 0;
1748
1749 /* Exit reset state. */
1750 ASMAtomicXchgBool(&pStream->State.fInReset, false);
1751}
1752
1753static bool hdaStreamIsActive(PHDASTATE pThis, PHDASTREAM pStream)
1754{
1755 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1756 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1757
1758 bool fActive = false;
1759
1760 AssertPtr(pStream->pMixSink);
1761 if (pStream->pMixSink->pMixSink)
1762 fActive = AudioMixerSinkHasData(pStream->pMixSink->pMixSink);
1763
1764 LogFlowFunc(("SD=%RU8, fActive=%RTbool\n", pStream->u8SD, fActive));
1765 return fActive;
1766}
1767
1768static int hdaStreamSetActive(PHDASTATE pThis, PHDASTREAM pStream, bool fActive)
1769{
1770 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1771 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1772
1773 if (!pStream->pMixSink) /* No mixer sink assigned? Bail out early. */
1774 {
1775 LogFlowFunc(("u8Strm=%RU8 has no mixer sink assigned\n", pStream->u8SD));
1776 return VINF_SUCCESS;
1777 }
1778
1779 AUDMIXSINKCMD enmCmd = fActive
1780 ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE;
1781
1782 /* First, enable or disable the stream's sink, if any. */
1783 if (pStream->pMixSink->pMixSink)
1784 AudioMixerSinkCtl(pStream->pMixSink->pMixSink, enmCmd);
1785
1786 /* Second, see if we need to start or stop the timer. */
1787 if (!fActive)
1788 {
1789 if (pThis->cStreamsActive) /* Disable can be called mupltiple times. */
1790 pThis->cStreamsActive--;
1791
1792#ifndef VBOX_WITH_AUDIO_CALLBACKS
1793 hdaTimerMaybeStop(pThis);
1794#endif
1795 }
1796 else
1797 {
1798 pThis->cStreamsActive++;
1799#ifndef VBOX_WITH_AUDIO_CALLBACKS
1800 hdaTimerMaybeStart(pThis);
1801#endif
1802 }
1803
1804 LogFlowFunc(("u8Strm=%RU8, fActive=%RTbool, cStreamsActive=%RU8\n", pStream->u8SD, fActive, pThis->cStreamsActive));
1805 return VINF_SUCCESS;
1806}
1807
1808static void hdaStreamAssignToSink(PHDASTREAM pStream, PHDAMIXERSINK pMixSink)
1809{
1810 AssertPtrReturnVoid(pStream);
1811
1812 int rc2 = RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
1813 if (RT_SUCCESS(rc2))
1814 {
1815 pStream->pMixSink = pMixSink;
1816
1817 rc2 = RTSemMutexRelease(pStream->State.hMtx);
1818 AssertRC(rc2);
1819 }
1820}
1821
1822static int hdaStreamStart(PHDASTREAM pStream)
1823{
1824 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1825
1826 ASMAtomicXchgBool(&pStream->State.fDoStop, false);
1827 ASMAtomicXchgBool(&pStream->State.fActive, true);
1828
1829 LogFlowFuncLeave();
1830 return VINF_SUCCESS;
1831}
1832
1833static int hdaStreamStop(PHDASTREAM pStream)
1834{
1835 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1836
1837 /* Already in stopped state? */
1838 bool fActive = ASMAtomicReadBool(&pStream->State.fActive);
1839 if (!fActive)
1840 return VINF_SUCCESS;
1841
1842#if 0 /** @todo Does not work (yet), as EMT deadlocks then. */
1843 /*
1844 * Wait for the stream to stop.
1845 */
1846 ASMAtomicXchgBool(&pStream->State.fDoStop, true);
1847
1848 int rc = hdaStreamWaitForStateChange(pStream, 60 * 1000 /* ms timeout */);
1849 fActive = ASMAtomicReadBool(&pStream->State.fActive);
1850 if ( /* Waiting failed? */
1851 RT_FAILURE(rc)
1852 /* Stream is still active? */
1853 || fActive)
1854 {
1855 AssertRC(rc);
1856 LogRel(("HDA: Warning: Unable to stop stream %RU8 (state: %s), rc=%Rrc\n",
1857 pStream->u8Strm, fActive ? "active" : "stopped", rc));
1858 }
1859#else
1860 int rc = VINF_SUCCESS;
1861#endif
1862
1863 LogFlowFuncLeaveRC(rc);
1864 return rc;
1865}
1866
1867static int hdaStreamChannelExtract(PPDMAUDIOSTREAMCHANNEL pChan, const void *pvBuf, size_t cbBuf)
1868{
1869 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1870 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
1871 AssertReturn(cbBuf, VERR_INVALID_PARAMETER);
1872
1873 AssertRelease(pChan->cbOff <= cbBuf);
1874
1875 const uint8_t *pu8Buf = (const uint8_t *)pvBuf;
1876
1877 size_t cbSrc = cbBuf - pChan->cbOff;
1878 const uint8_t *pvSrc = &pu8Buf[pChan->cbOff];
1879
1880 size_t cbDst;
1881 uint8_t *pvDst;
1882 RTCircBufAcquireWriteBlock(pChan->Data.pCircBuf, cbBuf, (void **)&pvDst, &cbDst);
1883
1884 cbSrc = RT_MIN(cbSrc, cbDst);
1885
1886 while (cbSrc)
1887 {
1888 AssertBreak(cbDst >= cbSrc);
1889
1890 /* Enough data for at least one next frame? */
1891 if (cbSrc < pChan->cbFrame)
1892 break;
1893
1894 memcpy(pvDst, pvSrc, pChan->cbFrame);
1895
1896 /* Advance to next channel frame in stream. */
1897 pvSrc += pChan->cbStep;
1898 Assert(cbSrc >= pChan->cbStep);
1899 cbSrc -= pChan->cbStep;
1900
1901 /* Advance destination by one frame. */
1902 pvDst += pChan->cbFrame;
1903 Assert(cbDst >= pChan->cbFrame);
1904 cbDst -= pChan->cbFrame;
1905
1906 /* Adjust offset. */
1907 pChan->cbOff += pChan->cbFrame;
1908 }
1909
1910 RTCircBufReleaseWriteBlock(pChan->Data.pCircBuf, cbDst);
1911
1912 return VINF_SUCCESS;
1913}
1914
1915static int hdaStreamChannelAdvance(PPDMAUDIOSTREAMCHANNEL pChan, size_t cbAdv)
1916{
1917 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1918
1919 if (!cbAdv)
1920 return VINF_SUCCESS;
1921
1922 return VINF_SUCCESS;
1923}
1924
1925static int hdaStreamChannelDataInit(PPDMAUDIOSTREAMCHANNELDATA pChanData, uint32_t fFlags)
1926{
1927 int rc = RTCircBufCreate(&pChanData->pCircBuf, 256); /** @todo Make this configurable? */
1928 if (RT_SUCCESS(rc))
1929 {
1930 pChanData->fFlags = fFlags;
1931 }
1932
1933 return rc;
1934}
1935
1936/**
1937 * Frees a stream channel data block again.
1938 *
1939 * @param pChanData Pointer to channel data to free.
1940 */
1941static void hdaStreamChannelDataDestroy(PPDMAUDIOSTREAMCHANNELDATA pChanData)
1942{
1943 if (!pChanData)
1944 return;
1945
1946 if (pChanData->pCircBuf)
1947 {
1948 RTCircBufDestroy(pChanData->pCircBuf);
1949 pChanData->pCircBuf = NULL;
1950 }
1951
1952 pChanData->fFlags = PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE;
1953}
1954
1955static int hdaStreamChannelAcquireData(PPDMAUDIOSTREAMCHANNELDATA pChanData, void *pvData, size_t *pcbData)
1956{
1957 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
1958 AssertPtrReturn(pvData, VERR_INVALID_POINTER);
1959 AssertPtrReturn(pcbData, VERR_INVALID_POINTER);
1960
1961 RTCircBufAcquireReadBlock(pChanData->pCircBuf, 256 /** @todo Make this configurarble? */, &pvData, &pChanData->cbAcq);
1962
1963 *pcbData = pChanData->cbAcq;
1964 return VINF_SUCCESS;
1965}
1966
1967static int hdaStreamChannelReleaseData(PPDMAUDIOSTREAMCHANNELDATA pChanData)
1968{
1969 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
1970 RTCircBufReleaseReadBlock(pChanData->pCircBuf, pChanData->cbAcq);
1971
1972 return VINF_SUCCESS;
1973}
1974
1975static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout)
1976{
1977 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1978
1979 LogFlowFunc(("[SD%RU8]: msTimeout=%RU32\n", pStream->u8SD, msTimeout));
1980 return RTSemEventWait(pStream->State.hStateChangedEvent, msTimeout);
1981}
1982#endif /* IN_RING3 */
1983
1984/* Register access handlers. */
1985
1986static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1987{
1988 *pu32Value = 0;
1989 return VINF_SUCCESS;
1990}
1991
1992static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1993{
1994 return VINF_SUCCESS;
1995}
1996
1997/* U8 */
1998static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1999{
2000 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
2001 return hdaRegReadU32(pThis, iReg, pu32Value);
2002}
2003
2004static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2005{
2006 Assert((u32Value & 0xffffff00) == 0);
2007 return hdaRegWriteU32(pThis, iReg, u32Value);
2008}
2009
2010/* U16 */
2011static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2012{
2013 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
2014 return hdaRegReadU32(pThis, iReg, pu32Value);
2015}
2016
2017static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2018{
2019 Assert((u32Value & 0xffff0000) == 0);
2020 return hdaRegWriteU32(pThis, iReg, u32Value);
2021}
2022
2023/* U24 */
2024static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2025{
2026 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
2027 return hdaRegReadU32(pThis, iReg, pu32Value);
2028}
2029
2030static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2031{
2032 Assert((u32Value & 0xff000000) == 0);
2033 return hdaRegWriteU32(pThis, iReg, u32Value);
2034}
2035
2036/* U32 */
2037static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2038{
2039 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2040
2041 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
2042 return VINF_SUCCESS;
2043}
2044
2045static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2046{
2047 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2048
2049 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
2050 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
2051 return VINF_SUCCESS;
2052}
2053
2054static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2055{
2056 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
2057 {
2058 /* Set the CRST bit to indicate that we're leaving reset mode. */
2059 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2060
2061 if (pThis->fInReset)
2062 {
2063 LogFunc(("Guest leaving HDA reset\n"));
2064 pThis->fInReset = false;
2065 }
2066 }
2067 else
2068 {
2069#ifdef IN_RING3
2070 /* Enter reset state. */
2071 LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
2072 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
2073 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
2074
2075 /* Clear the CRST bit to indicate that we're in reset state. */
2076 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2077 pThis->fInReset = true;
2078
2079 hdaReset(pThis->CTX_SUFF(pDevIns));
2080#else
2081 return VINF_IOM_R3_MMIO_WRITE;
2082#endif
2083 }
2084
2085 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
2086 {
2087 /* Flush: GSTS:1 set, see 6.2.6. */
2088 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
2089 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
2090 }
2091 return VINF_SUCCESS;
2092}
2093
2094static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2095{
2096 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2097
2098 uint32_t v = pThis->au32Regs[iRegMem];
2099 uint32_t nv = u32Value & HDA_STATES_SCSF;
2100 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
2101 return VINF_SUCCESS;
2102}
2103
2104static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2105{
2106 uint32_t v = 0;
2107 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
2108 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
2109 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
2110 || HDA_REG(pThis, STATESTS))
2111 {
2112 v |= RT_BIT(30); /* Touch CIS. */
2113 }
2114
2115#define HDA_MARK_STREAM(x) \
2116 if (/* Descriptor Error */ \
2117 (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
2118 /* FIFO Error */ \
2119 || (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
2120 /* Buffer Completion Interrupt Status */ \
2121 || (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))) \
2122 { \
2123 Log3Func(("[SD%RU8] BCIS: Marked\n", x)); \
2124 v |= RT_BIT(x); \
2125 }
2126
2127 HDA_MARK_STREAM(0);
2128 HDA_MARK_STREAM(1);
2129 HDA_MARK_STREAM(2);
2130 HDA_MARK_STREAM(3);
2131 HDA_MARK_STREAM(4);
2132 HDA_MARK_STREAM(5);
2133 HDA_MARK_STREAM(6);
2134 HDA_MARK_STREAM(7);
2135
2136#undef HDA_MARK_STREAM
2137
2138 /* "OR" bit of all interrupt status bits. */
2139 v |= v ? RT_BIT(31) : 0;
2140
2141 *pu32Value = v;
2142 return VINF_SUCCESS;
2143}
2144
2145static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2146{
2147 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
2148 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
2149 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
2150
2151 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
2152
2153 *pu32Value = u32LPIB;
2154 return VINF_SUCCESS;
2155}
2156
2157static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2158{
2159 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2160 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
2161 - pThis->u64BaseTS, 24, 1000);
2162 LogFlowFunc(("%RU32\n", *pu32Value));
2163 return VINF_SUCCESS;
2164}
2165
2166static int hdaRegReadSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2167{
2168 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2169 *pu32Value = HDA_REG(pThis, SSYNC);
2170 LogFlowFunc(("%RU32\n", *pu32Value));
2171 return VINF_SUCCESS;
2172}
2173
2174static int hdaRegWriteSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2175{
2176 LogFlowFunc(("%RU32\n", u32Value));
2177 return hdaRegWriteU32(pThis, iReg, u32Value);
2178}
2179
2180static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2181{
2182 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
2183 {
2184 HDA_REG(pThis, CORBRP) = 0;
2185 }
2186#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
2187 else
2188 return hdaRegWriteU8(pThis, iReg, u32Value);
2189#endif
2190 return VINF_SUCCESS;
2191}
2192
2193static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2194{
2195#ifdef IN_RING3
2196 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
2197 AssertRC(rc);
2198 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2199 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
2200 {
2201 return hdaCORBCmdProcess(pThis);
2202 }
2203 return rc;
2204#else
2205 return VINF_IOM_R3_MMIO_WRITE;
2206#endif
2207}
2208
2209static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2210{
2211 uint32_t v = HDA_REG(pThis, CORBSTS);
2212 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
2213 return VINF_SUCCESS;
2214}
2215
2216static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2217{
2218#ifdef IN_RING3
2219 int rc;
2220 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2221 if (RT_FAILURE(rc))
2222 AssertRCReturn(rc, rc);
2223 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
2224 return VINF_SUCCESS;
2225 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2226 return VINF_SUCCESS;
2227 rc = hdaCORBCmdProcess(pThis);
2228 return rc;
2229#else /* !IN_RING3 */
2230 return VINF_IOM_R3_MMIO_WRITE;
2231#endif /* IN_RING3 */
2232}
2233
2234static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2235{
2236#ifdef IN_RING3
2237 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2238 return VINF_SUCCESS;
2239
2240 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
2241 if (!pStream)
2242 {
2243 LogFunc(("[SD%RU8]: Warning: Changing SDCBL on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2244 return hdaRegWriteU32(pThis, iReg, u32Value);
2245 }
2246
2247 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2248 AssertRC(rc2);
2249
2250 pStream->u32CBL = u32Value;
2251
2252 /* Reset BDLE state. */
2253 RT_ZERO(pStream->State.BDLE);
2254 pStream->State.uCurBDLE = 0;
2255
2256 rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2257 AssertRC(rc2);
2258
2259 LogFlowFunc(("[SD%RU8]: CBL=%RU32\n", pStream->u8SD, u32Value));
2260 hdaRegWriteSDUnlock(pStream);
2261
2262 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2263#else /* !IN_RING3 */
2264 return VINF_IOM_R3_MMIO_WRITE;
2265#endif /* IN_RING3 */
2266}
2267
2268static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2269{
2270 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2271 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2272 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2273 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2274
2275 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2276 return VINF_SUCCESS;
2277
2278 /* Get the stream descriptor. */
2279 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
2280
2281 /*
2282 * Extract the stream tag the guest wants to use for this specific
2283 * stream descriptor (SDn). This only can happen if the stream is in a non-running
2284 * state, so we're doing the lookup and assignment here.
2285 *
2286 * So depending on the guest OS, SD3 can use stream tag 4, for example.
2287 */
2288 uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
2289 if (uTag > HDA_MAX_TAGS)
2290 {
2291 LogFunc(("[SD%RU8]: Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
2292 return hdaRegWriteU24(pThis, iReg, u32Value);
2293 }
2294
2295#ifdef IN_RING3
2296 PHDATAG pTag = &pThis->aTags[uTag];
2297 AssertPtr(pTag);
2298
2299 LogFunc(("[SD%RU8]: Using stream tag=%RU8\n", uSD, uTag));
2300
2301 /* Assign new values. */
2302 pTag->uTag = uTag;
2303 pTag->pStrm = hdaStreamFromSD(pThis, uSD);
2304
2305 PHDASTREAM pStream = pTag->pStrm;
2306 AssertPtr(pStream);
2307
2308 /* Note: Do not use hdaRegWriteSDLock() here, as SDnCTL might change the RUN bit. */
2309 int rc2 = RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
2310 AssertRC(rc2);
2311#endif /* IN_RING3 */
2312
2313 LogFunc(("[SD%RU8]: fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
2314 uSD, fRun, fInRun, fReset, fInReset, u32Value));
2315
2316 if (fInReset)
2317 {
2318 Assert(!fReset);
2319 Assert(!fInRun && !fRun);
2320
2321 /* Report that we're done resetting this stream by clearing SRST. */
2322 HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
2323
2324 LogFunc(("[SD%RU8]: Guest initiated exit of stream reset\n", uSD));
2325 }
2326 else if (fReset)
2327 {
2328#ifdef IN_RING3
2329 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
2330 Assert(!fInRun && !fRun);
2331
2332 LogFunc(("[SD%RU8]: Guest initiated enter to stream reset\n", pStream->u8SD));
2333 hdaStreamReset(pThis, pStream);
2334#endif
2335 }
2336 else
2337 {
2338#ifdef IN_RING3
2339 /*
2340 * We enter here to change DMA states only.
2341 */
2342 if (fInRun != fRun)
2343 {
2344 Assert(!fReset && !fInReset);
2345 LogFunc(("[SD%RU8]: fRun=%RTbool\n", pStream->u8SD, fRun));
2346
2347 hdaStreamSetActive(pThis, pStream, fRun);
2348
2349 if (fRun)
2350 {
2351 /* (Re-)Fetch the current BDLE entry. */
2352 rc2 = hdaBDLEFetch(pThis, &pStream->State.BDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
2353 AssertRC(rc2);
2354 }
2355 }
2356
2357 if (!fInRun && !fRun)
2358 hdaStreamInit(pThis, pStream, pStream->u8SD);
2359#endif /* IN_RING3 */
2360 }
2361
2362 /* Make sure to handle interrupts here as well. */
2363 hdaProcessInterrupt(pThis);
2364
2365#ifdef IN_RING3
2366 rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
2367 AssertRC(rc2);
2368
2369 hdaRegWriteSDUnlock(pStream);
2370 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2371#else
2372 return VINF_IOM_R3_MMIO_WRITE;
2373#endif
2374}
2375
2376static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2377{
2378 uint32_t v = HDA_REG_IND(pThis, iReg);
2379 /* Clear (zero) FIFOE and DESE bits when writing 1 to it. */
2380 v &= ~(u32Value & v);
2381
2382 HDA_REG_IND(pThis, iReg) = v;
2383
2384 hdaProcessInterrupt(pThis);
2385 return VINF_SUCCESS;
2386}
2387
2388static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2389{
2390#ifdef IN_RING3
2391 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2392 return VINF_SUCCESS;
2393
2394 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, LVI, iReg));
2395 if (!pStream)
2396 {
2397 LogFunc(("[SD%RU8]: Warning: Changing SDLVI on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2398 return hdaRegWriteU16(pThis, iReg, u32Value);
2399 }
2400
2401 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2402 AssertRC(rc2);
2403
2404 /** @todo Validate LVI. */
2405 pStream->u16LVI = u32Value;
2406
2407 /* Reset BDLE state. */
2408 RT_ZERO(pStream->State.BDLE);
2409 pStream->State.uCurBDLE = 0;
2410
2411 rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
2412 AssertRC(rc2);
2413
2414 LogFlowFunc(("[SD%RU8]: LVI=%RU32\n", pStream->u8SD, u32Value));
2415 hdaRegWriteSDUnlock(pStream);
2416
2417 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2418#else /* !IN_RING3 */
2419 return VINF_IOM_R3_MMIO_WRITE;
2420#endif /* IN_RING3 */
2421}
2422
2423static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2424{
2425 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
2426 /** @todo Only allow updating FIFOS if RUN bit is 0? */
2427 uint32_t u32FIFOW = 0;
2428
2429 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
2430 {
2431 LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to stream #%RU8, ignoring\n", uSD));
2432 return VINF_SUCCESS;
2433 }
2434
2435 switch (u32Value)
2436 {
2437 case HDA_SDFIFOW_8B:
2438 case HDA_SDFIFOW_16B:
2439 case HDA_SDFIFOW_32B:
2440 u32FIFOW = u32Value;
2441 break;
2442 default:
2443 LogRel(("HDA: Warning: Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
2444 u32Value, uSD));
2445 u32FIFOW = HDA_SDFIFOW_32B;
2446 break;
2447 }
2448
2449 if (u32FIFOW)
2450 {
2451 LogFunc(("[SD%RU8]: Updating FIFOW to %RU32 bytes\n", uSD, hdaSDFIFOSToBytes(u32FIFOW)));
2452 /** @todo Update internal stream state with new FIFOS. */
2453
2454 return hdaRegWriteU16(pThis, iReg, u32FIFOW);
2455 }
2456
2457 return VINF_SUCCESS; /* Never reached. */
2458}
2459
2460/**
2461 * @note This method could be called for changing value on Output Streams
2462 * only (ICH6 datasheet 18.2.39).
2463 */
2464static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2465{
2466 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
2467 /** @todo Only allow updating FIFOS if RUN bit is 0? */
2468 uint32_t u32FIFOS = 0;
2469
2470 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
2471 {
2472 LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to stream #%RU8, ignoring\n", uSD));
2473 return VINF_SUCCESS;
2474 }
2475
2476 switch(u32Value)
2477 {
2478 case HDA_SDOFIFO_16B:
2479 case HDA_SDOFIFO_32B:
2480 case HDA_SDOFIFO_64B:
2481 case HDA_SDOFIFO_128B:
2482 case HDA_SDOFIFO_192B:
2483 u32FIFOS = u32Value;
2484 break;
2485
2486 case HDA_SDOFIFO_256B: /** @todo r=andy Investigate this. */
2487 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
2488 /* Fall through is intentional. */
2489 default:
2490 LogRel(("HDA: Warning: Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
2491 u32Value, uSD));
2492 u32FIFOS = HDA_SDOFIFO_192B;
2493 break;
2494 }
2495
2496 if (u32FIFOS)
2497 {
2498 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n",
2499 HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg), hdaSDFIFOSToBytes(u32FIFOS)));
2500 /** @todo Update internal stream state with new FIFOS. */
2501
2502 return hdaRegWriteU16(pThis, iReg, u32FIFOS);
2503 }
2504
2505 return VINF_SUCCESS;
2506}
2507
2508#ifdef IN_RING3
2509static int hdaSDFMTToStrmCfg(uint32_t u32SDFMT, PPDMAUDIOSTREAMCFG pStrmCfg)
2510{
2511 AssertPtrReturn(pStrmCfg, VERR_INVALID_POINTER);
2512
2513# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2514
2515 int rc = VINF_SUCCESS;
2516
2517 uint32_t u32Hz = EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BASE_RATE_MASK, HDA_SDFMT_BASE_RATE_SHIFT)
2518 ? 44100 : 48000;
2519 uint32_t u32HzMult = 1;
2520 uint32_t u32HzDiv = 1;
2521
2522 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2523 {
2524 case 0: u32HzMult = 1; break;
2525 case 1: u32HzMult = 2; break;
2526 case 2: u32HzMult = 3; break;
2527 case 3: u32HzMult = 4; break;
2528 default:
2529 LogFunc(("Unsupported multiplier %x\n",
2530 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2531 rc = VERR_NOT_SUPPORTED;
2532 break;
2533 }
2534 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2535 {
2536 case 0: u32HzDiv = 1; break;
2537 case 1: u32HzDiv = 2; break;
2538 case 2: u32HzDiv = 3; break;
2539 case 3: u32HzDiv = 4; break;
2540 case 4: u32HzDiv = 5; break;
2541 case 5: u32HzDiv = 6; break;
2542 case 6: u32HzDiv = 7; break;
2543 case 7: u32HzDiv = 8; break;
2544 default:
2545 LogFunc(("Unsupported divisor %x\n",
2546 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2547 rc = VERR_NOT_SUPPORTED;
2548 break;
2549 }
2550
2551 PDMAUDIOFMT enmFmt;
2552 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2553 {
2554 case 0:
2555 enmFmt = PDMAUDIOFMT_S8;
2556 break;
2557 case 1:
2558 enmFmt = PDMAUDIOFMT_S16;
2559 break;
2560 case 4:
2561 enmFmt = PDMAUDIOFMT_S32;
2562 break;
2563 default:
2564 AssertMsgFailed(("Unsupported bits per sample %x\n",
2565 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2566 rc = VERR_NOT_SUPPORTED;
2567 break;
2568 }
2569
2570 if (RT_SUCCESS(rc))
2571 {
2572 pStrmCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2573 pStrmCfg->cChannels = (u32SDFMT & 0xf) + 1;
2574 pStrmCfg->enmFormat = enmFmt;
2575 pStrmCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2576 }
2577
2578# undef EXTRACT_VALUE
2579 return rc;
2580}
2581
2582static int hdaAddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2583{
2584 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2585 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2586
2587 AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
2588
2589 LogFlowFunc(("Stream=%s\n", pCfg->szName));
2590
2591 int rc = VINF_SUCCESS;
2592
2593 bool fUseFront = true; /* Always use front out by default. */
2594#ifdef VBOX_WITH_HDA_51_SURROUND
2595 bool fUseRear;
2596 bool fUseCenter;
2597 bool fUseLFE;
2598
2599 fUseRear = fUseCenter = fUseLFE = false;
2600
2601 /*
2602 * Use commonly used setups for speaker configurations.
2603 */
2604
2605 /** @todo Make the following configurable through mixer API and/or CFGM? */
2606 switch (pCfg->cChannels)
2607 {
2608 case 3: /* 2.1: Front (Stereo) + LFE. */
2609 {
2610 fUseLFE = true;
2611 break;
2612 }
2613
2614 case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
2615 {
2616 fUseRear = true;
2617 break;
2618 }
2619
2620 case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
2621 {
2622 fUseRear = true;
2623 fUseLFE = true;
2624 break;
2625 }
2626
2627 case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
2628 {
2629 fUseRear = true;
2630 fUseCenter = true;
2631 fUseLFE = true;
2632 break;
2633 }
2634
2635 default: /* Unknown; fall back to 2 front channels (stereo). */
2636 {
2637 rc = VERR_NOT_SUPPORTED;
2638 break;
2639 }
2640 }
2641#else /* !VBOX_WITH_HDA_51_SURROUND */
2642 /* Only support mono or stereo channels. */
2643 if ( pCfg->cChannels != 1 /* Mono */
2644 && pCfg->cChannels != 2 /* Stereo */)
2645 {
2646 rc = VERR_NOT_SUPPORTED;
2647 }
2648#endif
2649
2650 if (rc == VERR_NOT_SUPPORTED)
2651 {
2652 LogRel(("HDA: Unsupported channel count (%RU8), falling back to stereo channels\n", pCfg->cChannels));
2653 pCfg->cChannels = 2;
2654
2655 rc = VINF_SUCCESS;
2656 }
2657
2658 do
2659 {
2660 if (RT_FAILURE(rc))
2661 break;
2662
2663 if (fUseFront)
2664 {
2665 if (!RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front"))
2666 {
2667 rc = VERR_BUFFER_OVERFLOW;
2668 break;
2669 }
2670
2671 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
2672 pCfg->cChannels = 2;
2673 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT);
2674 if (RT_SUCCESS(rc))
2675 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
2676 }
2677
2678#ifdef VBOX_WITH_HDA_51_SURROUND
2679 if ( RT_SUCCESS(rc)
2680 && (fUseCenter || fUseLFE))
2681 {
2682 if (!RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE"))
2683 {
2684 rc = VERR_BUFFER_OVERFLOW;
2685 break;
2686 }
2687
2688 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
2689 pCfg->cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
2690 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE);
2691 if (RT_SUCCESS(rc))
2692 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
2693 }
2694
2695 if ( RT_SUCCESS(rc)
2696 && fUseRear)
2697 {
2698 if (!RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear"))
2699 {
2700 rc = VERR_BUFFER_OVERFLOW;
2701 break;
2702 }
2703
2704 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
2705 pCfg->cChannels = 2;
2706 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR);
2707 if (RT_SUCCESS(rc))
2708 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
2709 }
2710#endif /* VBOX_WITH_HDA_51_SURROUND */
2711
2712 } while (0);
2713
2714 LogFlowFuncLeaveRC(rc);
2715 return rc;
2716}
2717
2718static int hdaAddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2719{
2720 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2721 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2722
2723 AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
2724
2725 LogFlowFunc(("Stream=%s\n", pCfg->szName));
2726
2727 int rc;
2728
2729 switch (pCfg->DestSource.Source)
2730 {
2731 case PDMAUDIORECSOURCE_LINE:
2732 {
2733 pCfg->DestSource.Source = PDMAUDIORECSOURCE_LINE;
2734 pCfg->cChannels = 2;
2735 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN);
2736 if (RT_SUCCESS(rc))
2737 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
2738 break;
2739 }
2740#ifdef VBOX_WITH_HDA_MIC_IN
2741 case PDMAUDIORECSOURCE_MIC:
2742 {
2743 pCfg->DestSource.Source = PDMAUDIORECSOURCE_MIC;
2744 pCfg->cChannels = 2;
2745 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN);
2746 if (RT_SUCCESS(rc))
2747 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
2748 break;
2749 }
2750#endif
2751 default:
2752 rc = VERR_NOT_SUPPORTED;
2753 break;
2754 }
2755
2756 LogFlowFuncLeaveRC(rc);
2757 return rc;
2758}
2759#endif /* IN_RING3 */
2760
2761static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2762{
2763#ifdef IN_RING3
2764 PDMAUDIOSTREAMCFG strmCfg;
2765 RT_ZERO(strmCfg);
2766
2767 int rc = hdaSDFMTToStrmCfg(u32Value, &strmCfg);
2768 if (RT_FAILURE(rc))
2769 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2770
2771 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg));
2772 if (!pStream)
2773 {
2774 LogFunc(("[SD%RU8]: Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2775 HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2776 return hdaRegWriteU16(pThis, iReg, u32Value);
2777 }
2778
2779 rc = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2780 AssertRC(rc);
2781
2782 LogFunc(("[SD%RU8]: Hz=%RU32, Channels=%RU8, enmFmt=%RU32\n",
2783 pStream->u8SD, strmCfg.uHz, strmCfg.cChannels, strmCfg.enmFormat));
2784
2785 /* Set audio direction. */
2786 strmCfg.enmDir = hdaGetDirFromSD(pStream->u8SD);
2787
2788 /*
2789 * Initialize the stream mapping in any case, regardless if
2790 * we support surround audio or not. This is needed to handle
2791 * the supported channels within a single audio stream, e.g. mono/stereo.
2792 *
2793 * In other words, the stream mapping *always* knowns the real
2794 * number of channels in a single audio stream.
2795 */
2796 rc = hdaStreamMapInit(&pStream->State.Mapping, &strmCfg);
2797 AssertRC(rc);
2798
2799 if (RT_SUCCESS(rc))
2800 {
2801 int rc2;
2802 PHDADRIVER pDrv;
2803 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2804 {
2805 switch (strmCfg.enmDir)
2806 {
2807 case PDMAUDIODIR_OUT:
2808 rc2 = hdaAddStreamOut(pThis, &strmCfg);
2809 break;
2810
2811 case PDMAUDIODIR_IN:
2812 rc2 = hdaAddStreamIn(pThis, &strmCfg);
2813 break;
2814
2815 default:
2816 rc2 = VERR_NOT_SUPPORTED;
2817 AssertFailed();
2818 break;
2819 }
2820
2821 if ( RT_FAILURE(rc2)
2822 && (pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY)) /* We only care about primary drivers here, the rest may fail. */
2823 {
2824 if (RT_SUCCESS(rc))
2825 rc = rc2;
2826 /* Keep going. */
2827 }
2828 }
2829
2830 /* If (re-)opening the stream by the codec above failed, don't write the new
2831 * format to the register so that the guest is aware it didn't work. */
2832 if (RT_SUCCESS(rc))
2833 {
2834 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2835 AssertRC(rc);
2836 }
2837 else
2838 LogFunc(("[SD%RU8]: (Re-)Opening stream failed with rc=%Rrc\n", pStream->u8SD, rc));
2839
2840 hdaRegWriteSDUnlock(pStream);
2841 }
2842
2843 return VINF_SUCCESS; /* Never return failure. */
2844#else /* !IN_RING3 */
2845 return VINF_IOM_R3_MMIO_WRITE;
2846#endif
2847}
2848
2849/* Note: Will be called for both, BDPL and BDPU, registers. */
2850DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t u8Strm)
2851{
2852#ifdef IN_RING3
2853 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2854 return VINF_SUCCESS;
2855
2856 PHDASTREAM pStream = hdaStreamFromSD(pThis, u8Strm);
2857 if (!pStream)
2858 {
2859 LogFunc(("[SD%RU8]: Warning: Changing SDBPL/SDBPU on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2860 return hdaRegWriteU32(pThis, iReg, u32Value);
2861 }
2862
2863 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2864 AssertRC(rc2);
2865
2866 rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2867 AssertRC(rc2);
2868
2869 /* Update BDL base. */
2870 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2871 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2872 /* Reset BDLE state. */
2873 RT_ZERO(pStream->State.BDLE);
2874 pStream->State.uCurBDLE = 0;
2875
2876 LogFlowFunc(("[SD%RU8]: BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2877 hdaRegWriteSDUnlock(pStream);
2878
2879 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2880#else /* !IN_RING3 */
2881 return VINF_IOM_R3_MMIO_WRITE;
2882#endif /* IN_RING3 */
2883}
2884
2885static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2886{
2887 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2888}
2889
2890static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2891{
2892 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2893}
2894
2895#ifdef IN_RING3
2896/**
2897 * XXX
2898 *
2899 * @return bool Returns @true if write is allowed, @false if not.
2900 * @param pThis Pointer to HDA state.
2901 * @param iReg Register to write.
2902 * @param u32Value Value to write.
2903 */
2904DECLINLINE(int) hdaRegWriteSDLock(PHDASTATE pThis, PHDASTREAM pStream, uint32_t iReg, uint32_t u32Value)
2905{
2906 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2907 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
2908
2909#ifdef VBOX_STRICT
2910 /* Check if the SD's RUN bit is set. */
2911 uint32_t u32SDCTL = HDA_STREAM_REG(pThis, CTL, pStream->u8SD);
2912 bool fIsRunning = RT_BOOL(u32SDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2913 if (fIsRunning)
2914 {
2915 LogFunc(("[SD%RU8]: Warning: Cannot write to register 0x%x (0x%x) when RUN bit is set (%R[sdctl])\n",
2916 pStream->u8SD, iReg, u32Value, u32SDCTL));
2917# ifdef DEBUG_andy
2918 AssertFailed();
2919# endif
2920 return VERR_ACCESS_DENIED;
2921 }
2922#endif
2923
2924 return RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
2925}
2926
2927DECLINLINE(void) hdaRegWriteSDUnlock(PHDASTREAM pStream)
2928{
2929 AssertPtrReturnVoid(pStream);
2930
2931 int rc2 = RTSemMutexRelease(pStream->State.hMtx);
2932 AssertRC(rc2);
2933}
2934#endif /* IN_RING3 */
2935
2936static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2937{
2938 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2939 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2940 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2941 {
2942 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2943 }
2944
2945 return hdaRegReadU32(pThis, iReg, pu32Value);
2946}
2947
2948static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2949{
2950 int rc = VINF_SUCCESS;
2951
2952 /*
2953 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2954 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2955 */
2956 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
2957 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
2958 {
2959#ifdef IN_RING3
2960 uint32_t uCmd = HDA_REG(pThis, IC);
2961
2962 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2963 {
2964 /*
2965 * 3.4.3: Defines behavior of immediate Command status register.
2966 */
2967 LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
2968 return rc;
2969 }
2970
2971 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2972
2973 uint64_t uResp;
2974 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
2975 HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
2976 if (RT_FAILURE(rc2))
2977 LogFunc(("Codec lookup failed with rc=%Rrc\n", rc2));
2978
2979 HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
2980 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
2981 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
2982#else /* !IN_RING3 */
2983 rc = VINF_IOM_R3_MMIO_WRITE;
2984#endif
2985 return rc;
2986 }
2987
2988 /*
2989 * Once the guest read the response, it should clean the IRV bit of the IRS register.
2990 */
2991 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
2992 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
2993 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
2994 return rc;
2995}
2996
2997static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2998{
2999 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
3000 HDA_REG(pThis, RIRBWP) = 0;
3001
3002 /* The remaining bits are O, see 6.2.22. */
3003 return VINF_SUCCESS;
3004}
3005
3006static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3007{
3008 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
3009 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
3010 if (RT_FAILURE(rc))
3011 AssertRCReturn(rc, rc);
3012
3013 switch(iReg)
3014 {
3015 case HDA_REG_CORBLBASE:
3016 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
3017 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
3018 break;
3019 case HDA_REG_CORBUBASE:
3020 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
3021 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3022 break;
3023 case HDA_REG_RIRBLBASE:
3024 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
3025 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
3026 break;
3027 case HDA_REG_RIRBUBASE:
3028 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
3029 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3030 break;
3031 case HDA_REG_DPLBASE:
3032 {
3033 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
3034 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
3035
3036 /* Also make sure to handle the DMA position enable bit. */
3037 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
3038 LogRel(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
3039 break;
3040 }
3041 case HDA_REG_DPUBASE:
3042 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
3043 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3044 break;
3045 default:
3046 AssertMsgFailed(("Invalid index\n"));
3047 break;
3048 }
3049
3050 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
3051 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
3052 return rc;
3053}
3054
3055static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3056{
3057 uint8_t v = HDA_REG(pThis, RIRBSTS);
3058 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
3059
3060 return hdaProcessInterrupt(pThis);
3061}
3062
3063#ifdef IN_RING3
3064#ifdef LOG_ENABLED
3065static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE)
3066{
3067 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
3068 if (!u64BDLBase)
3069 return;
3070
3071 uint32_t cbBDLE = 0;
3072 for (uint16_t i = 0; i < cBDLE; i++)
3073 {
3074 uint8_t bdle[16]; /** @todo Use a define. */
3075 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BDLBase + i * 16, bdle, 16); /** @todo Use a define. */
3076
3077 uint64_t addr = *(uint64_t *)bdle;
3078 uint32_t len = *(uint32_t *)&bdle[8];
3079 uint32_t ioc = *(uint32_t *)&bdle[12];
3080
3081 LogFlowFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
3082 i, addr, len, RT_BOOL(ioc & 0x1)));
3083
3084 cbBDLE += len;
3085 }
3086
3087 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
3088
3089 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
3090 return;
3091
3092 LogFlowFunc(("DMA counters:\n"));
3093
3094 for (int i = 0; i < cBDLE; i++)
3095 {
3096 uint32_t uDMACnt;
3097 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
3098 &uDMACnt, sizeof(uDMACnt));
3099
3100 LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
3101 }
3102}
3103#endif
3104
3105/**
3106 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
3107 *
3108 * @param pThis Pointer to HDA state.
3109 * @param pBDLE Where to store the fetched result.
3110 * @param u64BaseDMA Address base of DMA engine to use.
3111 * @param u16Entry BDLE entry to fetch.
3112 */
3113static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
3114{
3115 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3116 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
3117 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
3118
3119 if (!u64BaseDMA)
3120 {
3121 LogRel2(("HDA: Unable to fetch BDLE #%RU16 - no base DMA address set (yet)\n", u16Entry));
3122 return VERR_NOT_FOUND;
3123 }
3124 /** @todo Compare u16Entry with LVI. */
3125
3126 uint8_t uBundleEntry[16]; /** @todo Define a BDLE length. */
3127 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * 16, /** @todo Define a BDLE length. */
3128 uBundleEntry, RT_ELEMENTS(uBundleEntry));
3129 if (RT_FAILURE(rc))
3130 return rc;
3131
3132 RT_BZERO(pBDLE, sizeof(HDABDLE));
3133
3134 pBDLE->State.u32BDLIndex = u16Entry;
3135 pBDLE->u64BufAdr = *(uint64_t *) uBundleEntry;
3136 pBDLE->u32BufSize = *(uint32_t *)&uBundleEntry[8];
3137 if (pBDLE->u32BufSize < sizeof(uint16_t)) /* Must be at least one word. */
3138 return VERR_INVALID_STATE;
3139
3140 pBDLE->fIntOnCompletion = (*(uint32_t *)&uBundleEntry[12]) & RT_BIT(0);
3141
3142 return VINF_SUCCESS;
3143}
3144
3145/**
3146 * Returns the number of outstanding stream data bytes which need to be processed
3147 * by the DMA engine assigned to this stream.
3148 *
3149 * @return Number of bytes for the DMA engine to process.
3150 */
3151DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax)
3152{
3153 AssertPtrReturn(pThis, 0);
3154 AssertPtrReturn(pStream, 0);
3155
3156 if (!cbMax)
3157 return 0;
3158
3159 PHDABDLE pBDLE = &pStream->State.BDLE;
3160
3161 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3162 Assert(u32LPIB <= pStream->u32CBL);
3163
3164 uint32_t cbFree = pStream->u32CBL - u32LPIB;
3165 if (cbFree)
3166 {
3167 /* Limit to the available free space of the current BDLE. */
3168 cbFree = RT_MIN(cbFree, pBDLE->u32BufSize - pBDLE->State.u32BufOff);
3169
3170 /* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
3171 // cbFree = RT_MIN(cbFree, uint32_t(pStream->u16FIFOS));
3172
3173 /* Make sure we only transfer as many bytes as requested. */
3174 cbFree = RT_MIN(cbFree, cbMax);
3175
3176 if (pBDLE->State.cbBelowFIFOW)
3177 {
3178 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
3179 * No need to read data from DMA then. */
3180 if (cbFree > pBDLE->State.cbBelowFIFOW)
3181 {
3182 /* Subtract the amount of bytes that still would fit in the stream's FIFO
3183 * and therefore do not need to be processed by DMA. */
3184 cbFree -= pBDLE->State.cbBelowFIFOW;
3185 }
3186 }
3187 }
3188
3189 LogFlowFunc(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, FIFOS=%RU16, cbFree=%RU32, %R[bdle]\n", pStream->u8SD,
3190 pStream->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), pStream->u16FIFOS, cbFree, pBDLE));
3191 return cbFree;
3192}
3193
3194DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
3195{
3196 AssertPtrReturnVoid(pBDLE);
3197
3198 if (!cbData || !cbProcessed)
3199 return;
3200
3201 /* Fewer than cbBelowFIFOW bytes were copied.
3202 * Probably we need to move the buffer, but it is rather hard to imagine a situation
3203 * where it might happen. */
3204 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
3205 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
3206 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
3207
3208#if 0
3209 if ( pBDLE->State.cbBelowFIFOW
3210 && pBDLE->State.cbBelowFIFOW <= cbWritten)
3211 {
3212 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
3213 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->u32BufSize));
3214 }
3215#endif
3216
3217 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
3218 Assert(pBDLE->State.cbBelowFIFOW == 0);
3219
3220 /* We always increment the position of DMA buffer counter because we're always reading
3221 * into an intermediate buffer. */
3222 pBDLE->State.u32BufOff += cbData;
3223 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3224
3225 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
3226}
3227
3228#ifdef IN_RING3
3229/**
3230 * Initializes a stream mapping structure according to the given stream configuration.
3231 *
3232 * @return IPRT status code.
3233 * @param pMapping Pointer to mapping to initialize.
3234 * @param pCfg Pointer to stream configuration to use.
3235 */
3236static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg)
3237{
3238 AssertPtrReturn(pMapping, VERR_INVALID_POINTER);
3239 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3240
3241 AssertReturn(pCfg->cChannels, VERR_INVALID_PARAMETER);
3242
3243 hdaStreamMapReset(pMapping);
3244
3245 pMapping->paChannels = (PPDMAUDIOSTREAMCHANNEL)RTMemAlloc(sizeof(PDMAUDIOSTREAMCHANNEL) * pCfg->cChannels);
3246 if (!pMapping->paChannels)
3247 return VERR_NO_MEMORY;
3248
3249 PDMPCMPROPS Props;
3250 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &Props);
3251 if (RT_FAILURE(rc))
3252 return rc;
3253
3254 Assert(RT_IS_POWER_OF_TWO(Props.cBits));
3255
3256 /** @todo We assume all channels in a stream have the same format. */
3257 PPDMAUDIOSTREAMCHANNEL pChan = pMapping->paChannels;
3258 for (uint8_t i = 0; i < pCfg->cChannels; i++)
3259 {
3260 pChan->uChannel = i;
3261 pChan->cbStep = (Props.cBits / 2);
3262 pChan->cbFrame = pChan->cbStep * pCfg->cChannels;
3263 pChan->cbFirst = i * pChan->cbStep;
3264 pChan->cbOff = pChan->cbFirst;
3265
3266 int rc2 = hdaStreamChannelDataInit(&pChan->Data, PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE);
3267 if (RT_SUCCESS(rc))
3268 rc = rc2;
3269
3270 if (RT_FAILURE(rc))
3271 break;
3272
3273 pChan++;
3274 }
3275
3276 if ( RT_SUCCESS(rc)
3277 /* Create circular buffer if not created yet. */
3278 && !pMapping->pCircBuf)
3279 {
3280 rc = RTCircBufCreate(&pMapping->pCircBuf, _4K); /** @todo Make size configurable? */
3281 }
3282
3283 if (RT_SUCCESS(rc))
3284 {
3285 pMapping->cChannels = pCfg->cChannels;
3286#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3287 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_INTERLEAVED;
3288#else
3289 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
3290#endif
3291 }
3292
3293 return rc;
3294}
3295
3296/**
3297 * Destroys a given stream mapping.
3298 *
3299 * @param pMapping Pointer to mapping to destroy.
3300 */
3301static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping)
3302{
3303 hdaStreamMapReset(pMapping);
3304
3305 if (pMapping->pCircBuf)
3306 {
3307 RTCircBufDestroy(pMapping->pCircBuf);
3308 pMapping->pCircBuf = NULL;
3309 }
3310}
3311
3312/**
3313 * Resets a given stream mapping.
3314 *
3315 * @param pMapping Pointer to mapping to reset.
3316 */
3317static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping)
3318{
3319 AssertPtrReturnVoid(pMapping);
3320
3321 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_UNKNOWN;
3322
3323 if (pMapping->cChannels)
3324 {
3325 for (uint8_t i = 0; i < pMapping->cChannels; i++)
3326 hdaStreamChannelDataDestroy(&pMapping->paChannels[i].Data);
3327
3328 AssertPtr(pMapping->paChannels);
3329 RTMemFree(pMapping->paChannels);
3330 pMapping->paChannels = NULL;
3331
3332 pMapping->cChannels = 0;
3333 }
3334}
3335#endif /* IN_RING3 */
3336
3337DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
3338{
3339 AssertPtrReturn(pThis, false);
3340 AssertPtrReturn(pStream, false);
3341
3342 PHDABDLE pBDLE = &pStream->State.BDLE;
3343 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3344
3345 /* Did we reach the CBL (Cyclic Buffer List) limit? */
3346 bool fCBLLimitReached = u32LPIB >= pStream->u32CBL;
3347
3348 /* Do we need to use the next BDLE entry? Either because we reached
3349 * the CBL limit or our internal DMA buffer is full. */
3350 bool fNeedsNextBDLE = ( fCBLLimitReached
3351 || (pBDLE->State.u32BufOff >= pBDLE->u32BufSize));
3352
3353 Assert(u32LPIB <= pStream->u32CBL);
3354 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3355
3356 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
3357 pStream->u8SD, u32LPIB, pStream->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
3358
3359 return fNeedsNextBDLE;
3360}
3361
3362DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbInc)
3363{
3364 AssertPtrReturnVoid(pThis);
3365 AssertPtrReturnVoid(pStream);
3366
3367 LogFlowFunc(("[SD%RU8]: cbInc=%RU32\n", pStream->u8SD, cbInc));
3368
3369 //Assert(cbInc <= pStream->u16FIFOS);
3370
3371 if (!cbInc) /* Nothing to do? Bail out early. */
3372 return;
3373
3374 PHDABDLE pBDLE = &pStream->State.BDLE;
3375
3376 /*
3377 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
3378 * doesn't fetch anything via DMA, so just update LPIB.
3379 * (ICH6 datasheet 18.2.38).
3380 */
3381 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
3382 {
3383 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3384
3385 AssertMsg(((u32LPIB + cbInc) <= pStream->u32CBL),
3386 ("[SD%RU8] Increment (%RU32) exceeds CBL (%RU32): LPIB (%RU32)\n",
3387 pStream->u8SD, cbInc, pStream->u32CBL, u32LPIB));
3388
3389 u32LPIB = RT_MIN(u32LPIB + cbInc, pStream->u32CBL);
3390
3391 LogFlowFunc(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
3392 pStream->u8SD,
3393 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) + cbInc,
3394 pStream->u32CBL));
3395
3396 hdaStreamUpdateLPIB(pThis, pStream, u32LPIB);
3397 }
3398}
3399
3400static bool hdaStreamTransferIsComplete(PHDASTATE pThis, PHDASTREAM pStream, bool *pfInterrupt)
3401{
3402 AssertPtrReturn(pThis, true);
3403 AssertPtrReturn(pStream, true);
3404
3405 bool fInterrupt = false;
3406 bool fIsComplete = false;
3407
3408 PHDABDLE pBDLE = &pStream->State.BDLE;
3409 const uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3410
3411 /* Check if the current BDLE entry is complete (full). */
3412 if (pBDLE->State.u32BufOff >= pBDLE->u32BufSize)
3413 {
3414 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3415
3416 if (/* IOC (Interrupt On Completion) bit set? */
3417 pBDLE->fIntOnCompletion
3418 /* All data put into the DMA FIFO? */
3419 && pBDLE->State.cbBelowFIFOW == 0
3420 )
3421 {
3422 LogFlowFunc(("[SD%RU8]: %R[bdle] => COMPLETE\n", pStream->u8SD, pBDLE));
3423
3424 /*
3425 * If the ICE (IOCE, "Interrupt On Completion Enable") bit of the SDCTL register is set
3426 * we need to generate an interrupt.
3427 */
3428 if (HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
3429 fInterrupt = true;
3430 }
3431
3432 fIsComplete = true;
3433 }
3434
3435 if (pfInterrupt)
3436 *pfInterrupt = fInterrupt;
3437
3438 LogFlowFunc(("[SD%RU8]: u32LPIB=%RU32, CBL=%RU32, fIsComplete=%RTbool, fInterrupt=%RTbool, %R[bdle]\n",
3439 pStream->u8SD, u32LPIB, pStream->u32CBL, fIsComplete, fInterrupt, pBDLE));
3440
3441 return fIsComplete;
3442}
3443
3444/**
3445 * hdaReadAudio - copies samples from audio backend to DMA.
3446 * Note: This function writes to the DMA buffer immediately,
3447 * but "reports bytes" when all conditions are met (FIFOW).
3448 */
3449static int hdaReadAudio(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax, uint32_t *pcbRead)
3450{
3451 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3452 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
3453 /* pcbRead is optional. */
3454
3455 int rc;
3456 uint32_t cbRead = 0;
3457
3458 do
3459 {
3460 PHDABDLE pBDLE = &pStream->State.BDLE;
3461
3462 uint32_t cbBuf = hdaStreamGetTransferSize(pThis, pStream, cbMax);
3463 Log3Func(("cbBuf=%RU32, %R[bdle]\n", cbBuf, pBDLE));
3464
3465 if (!cbBuf)
3466 {
3467 rc = VINF_EOF;
3468 break;
3469 }
3470
3471 AssertPtr(pStream->pMixSink);
3472 AssertPtr(pStream->pMixSink->pMixSink);
3473 rc = AudioMixerSinkRead(pStream->pMixSink->pMixSink, AUDMIXOP_BLEND, pBDLE->State.au8FIFO, cbBuf, &cbRead);
3474 if (RT_FAILURE(rc))
3475 break;
3476
3477 if (!cbRead)
3478 {
3479 rc = VINF_EOF;
3480 break;
3481 }
3482
3483 /* Sanity checks. */
3484 Assert(cbRead <= cbBuf);
3485 Assert(cbRead <= pBDLE->u32BufSize - pBDLE->State.u32BufOff);
3486
3487 /*
3488 * Write to the BDLE's DMA buffer.
3489 */
3490 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
3491 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
3492 pBDLE->State.au8FIFO, cbRead);
3493 AssertRC(rc);
3494
3495 if (pBDLE->State.cbBelowFIFOW + cbRead > hdaStreamGetFIFOW(pThis, pStream))
3496 {
3497 Assert(pBDLE->State.u32BufOff + cbRead <= pBDLE->u32BufSize);
3498 pBDLE->State.u32BufOff += cbRead;
3499 pBDLE->State.cbBelowFIFOW = 0;
3500 //hdaBackendReadTransferReported(pBDLE, cbDMAData, cbRead, &cbRead, pcbAvail);
3501 }
3502 else
3503 {
3504 Assert(pBDLE->State.u32BufOff + cbRead <= pBDLE->u32BufSize);
3505 pBDLE->State.u32BufOff += cbRead;
3506 pBDLE->State.cbBelowFIFOW += cbRead;
3507 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStream));
3508 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbRead, pcbAvail);
3509
3510 rc = VERR_NO_DATA;
3511 }
3512
3513 } while (0);
3514
3515 if (RT_SUCCESS(rc))
3516 {
3517 if (pcbRead)
3518 *pcbRead = cbRead;
3519 }
3520
3521 Log3Func(("Returning cbRead=%RU32, rc=%Rrc\n", cbRead, rc));
3522 return rc;
3523}
3524
3525static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax, uint32_t *pcbWritten)
3526{
3527 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3528 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
3529 AssertPtrReturn(pcbWritten, VERR_INVALID_POINTER);
3530 /* pcbWritten is optional. */
3531
3532 PHDABDLE pBDLE = &pStream->State.BDLE;
3533
3534 uint32_t cbWritten = 0;
3535 uint32_t cbToWrite = hdaStreamGetTransferSize(pThis, pStream, cbMax);
3536
3537 Log3Func(("cbToWrite=%RU32, %R[bdle]\n", cbToWrite, pBDLE));
3538
3539 /*
3540 * Copy from DMA to the corresponding stream buffer (if there are any bytes from the
3541 * previous unreported transfer we write at offset 'pBDLE->State.cbUnderFifoW').
3542 */
3543 int rc;
3544 if (!cbToWrite)
3545 {
3546 rc = VINF_EOF;
3547 }
3548 else
3549 {
3550 void *pvBuf = pBDLE->State.au8FIFO + pBDLE->State.cbBelowFIFOW;
3551 Assert(cbToWrite >= pBDLE->State.cbBelowFIFOW);
3552 uint32_t cbBuf = cbToWrite - pBDLE->State.cbBelowFIFOW;
3553
3554 /*
3555 * Read from the current BDLE's DMA buffer.
3556 */
3557 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3558 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
3559 pvBuf, cbBuf);
3560 AssertRC(rc);
3561#if defined (RT_OS_LINUX) && defined(DEBUG_andy)
3562 RTFILE fh;
3563 RTFileOpen(&fh, "/tmp/hdaWriteAudio-hda.pcm",
3564 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
3565 RTFileWrite(fh, pvBuf, cbBuf, NULL);
3566 RTFileClose(fh);
3567#endif
3568
3569#ifdef VBOX_WITH_STATISTICS
3570 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBuf);
3571#endif
3572 /*
3573 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
3574 */
3575 if (cbBuf >= hdaStreamGetFIFOW(pThis, pStream))
3576 {
3577 PHDASTREAMMAPPING pMapping = &pStream->State.Mapping;
3578
3579 /** @todo Which channel is which? */
3580#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3581 PPDMAUDIOSTREAMCHANNEL pChanFront = &pMapping->paChannels[0];
3582#endif
3583#ifdef VBOX_WITH_HDA_51_SURROUND
3584 PPDMAUDIOSTREAMCHANNEL pChanCenterLFE = &pMapping->paChannels[2]; /** @todo FIX! */
3585 PPDMAUDIOSTREAMCHANNEL pChanRear = &pMapping->paChannels[4]; /** @todo FIX! */
3586#endif
3587 int rc2;
3588
3589 void *pvDataFront = NULL;
3590 size_t cbDataFront;
3591#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3592 rc2 = hdaStreamChannelExtract(pChanFront, pvBuf, cbBuf);
3593 AssertRC(rc2);
3594
3595 rc2 = hdaStreamChannelAcquireData(&pChanFront->Data, pvDataFront, &cbDataFront);
3596 AssertRC(rc2);
3597#else
3598 /* Use stuff in the whole FIFO to use for the channel data. */
3599 pvDataFront = pvBuf;
3600 cbDataFront = cbBuf;
3601#endif
3602#ifdef VBOX_WITH_HDA_51_SURROUND
3603 void *pvDataCenterLFE;
3604 size_t cbDataCenterLFE;
3605 rc2 = hdaStreamChannelExtract(pChanCenterLFE, pvBuf, cbBuf);
3606 AssertRC(rc2);
3607
3608 rc2 = hdaStreamChannelAcquireData(&pChanCenterLFE->Data, pvDataCenterLFE, &cbDataCenterLFE);
3609 AssertRC(rc2);
3610
3611 void *pvDataRear;
3612 size_t cbDataRear;
3613 rc2 = hdaStreamChannelExtract(pChanRear, pvBuf, cbBuf);
3614 AssertRC(rc2);
3615
3616 rc2 = hdaStreamChannelAcquireData(&pChanRear->Data, pvDataRear, &cbDataRear);
3617 AssertRC(rc2);
3618#endif
3619 /*
3620 * Write data to according mixer sinks.
3621 */
3622 rc2 = AudioMixerSinkWrite(pThis->SinkFront.pMixSink, AUDMIXOP_COPY, pvDataFront, cbDataFront,
3623 NULL /* pcbWritten */);
3624 AssertRC(rc2);
3625#ifdef VBOX_WITH_HDA_51_SURROUND
3626 rc2 = AudioMixerSinkWrite(pThis->SinkCenterLFE, AUDMIXOP_COPY, pvDataCenterLFE, cbDataCenterLFE,
3627 NULL /* pcbWritten */);
3628 AssertRC(rc2);
3629 rc2 = AudioMixerSinkWrite(pThis->SinkRear, AUDMIXOP_COPY, pvDataRear, cbDataRear,
3630 NULL /* pcbWritten */);
3631 AssertRC(rc2);
3632#endif
3633
3634#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3635 hdaStreamChannelReleaseData(&pChanFront->Data);
3636#endif
3637#ifdef VBOX_WITH_HDA_51_SURROUND
3638 hdaStreamChannelReleaseData(&pChanCenterLFE->Data);
3639 hdaStreamChannelReleaseData(&pChanRear->Data);
3640#endif
3641
3642 /* Always report all data as being written;
3643 * backends who were not able to catch up have to deal with it themselves. */
3644 cbWritten = cbToWrite;
3645
3646 hdaBDLEUpdate(pBDLE, cbToWrite, cbWritten);
3647 }
3648 else
3649 {
3650 Assert(pBDLE->State.u32BufOff + cbWritten <= pBDLE->u32BufSize);
3651 pBDLE->State.u32BufOff += cbWritten;
3652 pBDLE->State.cbBelowFIFOW += cbWritten;
3653 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStream));
3654
3655 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
3656 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbAvail, NULL);
3657 rc = VINF_EOF;
3658 }
3659 }
3660
3661 //Assert(cbWritten <= pStream->u16FIFOS);
3662
3663 if (RT_SUCCESS(rc))
3664 {
3665 if (pcbWritten)
3666 *pcbWritten = cbWritten;
3667 }
3668
3669 Log3Func(("Returning cbMax=%RU32, cbWritten=%RU32, rc=%Rrc\n", cbMax, cbWritten, rc));
3670 return rc;
3671}
3672
3673/**
3674 * @interface_method_impl{HDACODEC,pfnReset}
3675 */
3676static DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
3677{
3678 PHDASTATE pThis = pCodec->pHDAState;
3679 NOREF(pThis);
3680 return VINF_SUCCESS;
3681}
3682
3683/**
3684 * Retrieves a corresponding sink for a given mixer control.
3685 * Returns NULL if no sink is found.
3686 *
3687 * @return PHDAMIXERSINK
3688 * @param pThis HDA state.
3689 * @param enmMixerCtl Mixer control to get the corresponding sink for.
3690 */
3691static PHDAMIXERSINK hdaMixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3692{
3693 PHDAMIXERSINK pSink;
3694
3695 switch (enmMixerCtl)
3696 {
3697 case PDMAUDIOMIXERCTL_VOLUME:
3698 /* Fall through is intentional. */
3699 case PDMAUDIOMIXERCTL_FRONT:
3700 pSink = &pThis->SinkFront;
3701 break;
3702#ifdef VBOX_WITH_HDA_51_SURROUND
3703 case PDMAUDIOMIXERCTL_CENTER_LFE:
3704 pSink = &pThis->SinkCenterLFE;
3705 break;
3706 case PDMAUDIOMIXERCTL_REAR:
3707 pSink = &pThis->SinkRear;
3708 break;
3709#endif
3710 case PDMAUDIOMIXERCTL_LINE_IN:
3711 pSink = &pThis->SinkLineIn;
3712 break;
3713#ifdef VBOX_WITH_HDA_MIC_IN
3714 case PDMAUDIOMIXERCTL_MIC_IN:
3715 pSink = &pThis->SinkMicIn;
3716 break;
3717#endif
3718 default:
3719 pSink = NULL;
3720 AssertMsgFailed(("Unhandled mixer control\n"));
3721 break;
3722 }
3723
3724 return pSink;
3725}
3726
3727static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PHDAMIXERSINK pSink, PPDMAUDIOSTREAMCFG pCfg)
3728{
3729 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3730 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
3731 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3732
3733 LogFunc(("Sink=%s, Stream=%s\n", pSink->pMixSink->pszName, pCfg->szName));
3734
3735 /* Update the sink's format. */
3736 PDMPCMPROPS PCMProps;
3737 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &PCMProps);
3738 if (RT_SUCCESS(rc))
3739 rc = AudioMixerSinkSetFormat(pSink->pMixSink, &PCMProps);
3740
3741 if (RT_FAILURE(rc))
3742 return rc;
3743
3744 PHDADRIVER pDrv;
3745 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3746 {
3747 int rc2 = VINF_SUCCESS;
3748 PHDAMIXERSTREAM pStream;
3749
3750 if (pCfg->enmDir == PDMAUDIODIR_IN)
3751 {
3752 switch (pCfg->DestSource.Source)
3753 {
3754 case PDMAUDIORECSOURCE_LINE:
3755 pStream = &pDrv->LineIn;
3756 break;
3757#ifdef VBOX_WITH_HDA_MIC_IN
3758 case PDMAUDIORECSOURCE_MIC:
3759 pStream = &pDrv->MicIn;
3760 break;
3761#endif
3762 default:
3763 rc2 = VERR_NOT_SUPPORTED;
3764 break;
3765 }
3766 }
3767 else if (pCfg->enmDir == PDMAUDIODIR_OUT)
3768 {
3769 switch (pCfg->DestSource.Dest)
3770 {
3771 case PDMAUDIOPLAYBACKDEST_FRONT:
3772 pStream = &pDrv->Front;
3773 break;
3774#ifdef VBOX_WITH_HDA_51_SURROUND
3775 case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
3776 pStream = &pDrv->CenterLFE;
3777 break;
3778 case PDMAUDIOPLAYBACKDEST_REAR:
3779 pStream = &pDrv->Rear;
3780 break;
3781#endif
3782 default:
3783 rc2 = VERR_NOT_SUPPORTED;
3784 break;
3785 }
3786 }
3787 else
3788 rc2 = VERR_NOT_SUPPORTED;
3789
3790 if (RT_SUCCESS(rc2))
3791 {
3792 AudioMixerSinkRemoveStream(pSink->pMixSink, pStream->pMixStrm);
3793
3794 AudioMixerStreamDestroy(pStream->pMixStrm);
3795 pStream->pMixStrm = NULL;
3796
3797 PAUDMIXSTREAM pMixStrm;
3798 rc2 = AudioMixerSinkCreateStream(pSink->pMixSink, pDrv->pConnector, pCfg, 0 /* fFlags */, &pMixStrm);
3799 if (RT_SUCCESS(rc2))
3800 {
3801 rc2 = AudioMixerSinkAddStream(pSink->pMixSink, pMixStrm);
3802 LogFlowFunc(("LUN#%RU8: Added \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pCfg->szName , rc2));
3803 }
3804
3805 if (RT_SUCCESS(rc2))
3806 pStream->pMixStrm = pMixStrm;
3807 }
3808
3809 if (RT_SUCCESS(rc))
3810 rc = rc2;
3811 }
3812
3813 LogFlowFuncLeaveRC(rc);
3814 return rc;
3815}
3816
3817/**
3818 * Adds a new audio stream to a specific mixer control.
3819 * Depending on the mixer control the stream then gets assigned to one of the internal
3820 * mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
3821 *
3822 * @return IPRT status code.
3823 * @param pThis HDA state.
3824 * @param enmMixerCtl Mixer control to assign new stream to.
3825 * @param pCfg Stream configuration for the new stream.
3826 */
3827static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
3828{
3829 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3830 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3831
3832 int rc;
3833
3834 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3835 if (pSink)
3836 {
3837 rc = hdaMixerAddStream(pThis, pSink, pCfg);
3838
3839 AssertPtr(pSink->pMixSink);
3840 LogFlowFunc(("Sink=%s, enmMixerCtl=%ld\n", pSink->pMixSink->pszName, enmMixerCtl));
3841 }
3842 else
3843 rc = VERR_NOT_FOUND;
3844
3845 LogFlowFuncLeaveRC(rc);
3846 return rc;
3847}
3848
3849/**
3850 * Removes a specified mixer control from the HDA's mixer.
3851 *
3852 * @return IPRT status code.
3853 * @param pThis HDA state.
3854 * @param enmMixerCtl Mixer control to remove.
3855 */
3856static DECLCALLBACK(int) hdaMixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3857{
3858 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3859
3860 int rc;
3861
3862 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3863 if (pSink)
3864 {
3865 PHDADRIVER pDrv;
3866 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3867 {
3868 PAUDMIXSTREAM pMixStream = NULL;
3869 switch (enmMixerCtl)
3870 {
3871 /*
3872 * Input.
3873 */
3874 case PDMAUDIOMIXERCTL_LINE_IN:
3875 pMixStream = pDrv->LineIn.pMixStrm;
3876 pDrv->LineIn.pMixStrm = NULL;
3877 break;
3878#ifdef VBOX_WITH_HDA_MIC_IN
3879 case PDMAUDIOMIXERCTL_MIC_IN:
3880 pMixStream = pDrv->MicIn.pMixStrm;
3881 pDrv->MicIn.pMixStrm = NULL;
3882 break;
3883#endif
3884 /*
3885 * Output.
3886 */
3887 case PDMAUDIOMIXERCTL_FRONT:
3888 pMixStream = pDrv->Front.pMixStrm;
3889 pDrv->Front.pMixStrm = NULL;
3890 break;
3891#ifdef VBOX_WITH_HDA_51_SURROUND
3892 case PDMAUDIOMIXERCTL_CENTER_LFE:
3893 pMixStream = pDrv->CenterLFE.pMixStrm;
3894 pDrv->CenterLFE.pMixStrm = NULL;
3895 break;
3896 case PDMAUDIOMIXERCTL_REAR:
3897 pMixStream = pDrv->Rear.pMixStrm;
3898 pDrv->Rear.pMixStrm = NULL;
3899 break;
3900#endif
3901 default:
3902 AssertMsgFailed(("Mixer control %ld not implemented\n", enmMixerCtl));
3903 break;
3904 }
3905
3906 if (pMixStream)
3907 {
3908 AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
3909 AudioMixerStreamDestroy(pMixStream);
3910 }
3911 }
3912
3913 AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
3914 rc = VINF_SUCCESS;
3915 }
3916 else
3917 rc = VERR_NOT_FOUND;
3918
3919 LogFlowFunc(("enmMixerCtl=%ld, rc=%Rrc\n", enmMixerCtl, rc));
3920 return rc;
3921}
3922
3923/**
3924 * Sets a SDn stream number and channel to a particular mixer control.
3925 *
3926 * @returns IPRT status code.
3927 * @param pThis HDA State.
3928 * @param enmMixerCtl Mixer control to set SD stream number and channel for.
3929 * @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
3930 * @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
3931 */
3932static DECLCALLBACK(int) hdaMixerSetStream(PHDASTATE pThis,
3933 PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
3934{
3935 LogFlowFunc(("enmMixerCtl=%RU32, uSD=%RU8, uChannel=%RU8\n", enmMixerCtl, uSD, uChannel));
3936
3937 if (uSD == 0) /* Stream number 0 is reserved. */
3938 {
3939 LogFlowFunc(("Invalid SDn (%RU8) number for mixer control %ld, ignoring\n", uSD, enmMixerCtl));
3940 return VINF_SUCCESS;
3941 }
3942 /* uChannel is optional. */
3943
3944 /* SDn0 starts as 1. */
3945 Assert(uSD);
3946 uSD--;
3947
3948 int rc;
3949
3950 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3951 if (pSink)
3952 {
3953 if ( (uSD < HDA_MAX_SDI)
3954 && AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
3955 {
3956 uSD += HDA_MAX_SDI;
3957 }
3958
3959 LogFlowFunc(("%s: Setting to stream ID=%RU8, channel=%RU8, enmMixerCtl=%RU32\n",
3960 pSink->pMixSink->pszName, uSD, uChannel, enmMixerCtl));
3961
3962 Assert(uSD < HDA_MAX_STREAMS);
3963
3964 PHDASTREAM pStream = hdaStreamFromSD(pThis, uSD);
3965 if (pStream)
3966 {
3967 pSink->uSD = uSD;
3968 pSink->uChannel = uChannel;
3969
3970 /* Make sure that the stream also has this sink set. */
3971 hdaStreamAssignToSink(pStream, pSink);
3972
3973 rc = VINF_SUCCESS;
3974 }
3975 else
3976 {
3977 LogRel(("HDA: Guest wanted to assign invalid stream ID=%RU8 (channel %RU8) to mixer control %RU32, skipping\n",
3978 uSD, uChannel, enmMixerCtl));
3979 rc = VERR_INVALID_PARAMETER;
3980 }
3981 }
3982 else
3983 rc = VERR_NOT_FOUND;
3984
3985 LogFlowFuncLeaveRC(rc);
3986 return rc;
3987}
3988
3989/**
3990 * Sets the volume of a specified mixer control.
3991 *
3992 * @return IPRT status code.
3993 * @param pThis HDA State.
3994 * @param enmMixerCtl Mixer control to set volume for.
3995 * @param pVol Pointer to volume data to set.
3996 */
3997static DECLCALLBACK(int) hdaMixerSetVolume(PHDASTATE pThis,
3998 PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
3999{
4000 int rc;
4001
4002 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
4003 if (pSink)
4004 {
4005 /* Set the volume.
4006 * We assume that the codec already converted it to the correct range. */
4007 rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
4008 }
4009 else
4010 rc = VERR_NOT_FOUND;
4011
4012 LogFlowFuncLeaveRC(rc);
4013 return rc;
4014}
4015
4016#ifndef VBOX_WITH_AUDIO_CALLBACKS
4017
4018static void hdaTimerMaybeStart(PHDASTATE pThis)
4019{
4020 LogFlowFunc(("cStreamsActive=%RU8\n", pThis->cStreamsActive));
4021
4022 if (pThis->cStreamsActive == 0) /* Only start the timer if there are no active streams. */
4023 return;
4024
4025 if (!pThis->pTimer)
4026 return;
4027
4028 LogFlowFuncEnter();
4029
4030 /* Set timer flag. */
4031 ASMAtomicXchgBool(&pThis->fTimerActive, true);
4032
4033 /* Update current time timestamp. */
4034 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
4035
4036 /* Fire off timer. */
4037 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
4038}
4039
4040static void hdaTimerMaybeStop(PHDASTATE pThis)
4041{
4042 LogFlowFunc(("cStreamsActive=%RU8\n", pThis->cStreamsActive));
4043
4044 if (pThis->cStreamsActive) /* Some streams still active? Bail out. */
4045 return;
4046
4047 if (!pThis->pTimer)
4048 return;
4049
4050 LogFlowFuncEnter();
4051
4052 /* Set timer flag. */
4053 ASMAtomicXchgBool(&pThis->fTimerActive, false);
4054}
4055
4056static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
4057{
4058 PHDASTATE pThis = (PHDASTATE)pvUser;
4059 Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
4060 AssertPtr(pThis);
4061
4062 STAM_PROFILE_START(&pThis->StatTimer, a);
4063
4064 uint32_t cbInMax = 0;
4065 uint32_t cbOutMin = UINT32_MAX;
4066
4067 uint64_t cTicksNow = TMTimerGet(pTimer);
4068 uint64_t cTicksElapsed = cTicksNow - pThis->uTimerTS;
4069
4070 /* Update current time timestamp. */
4071 pThis->uTimerTS = cTicksNow;
4072
4073 PHDASTREAM pStreamLineIn = hdaGetStreamFromSink(pThis, &pThis->SinkLineIn);
4074#ifdef VBOX_WITH_HDA_MIC_IN
4075 PHDASTREAM pStreamMicIn = hdaGetStreamFromSink(pThis, &pThis->SinkMicIn);
4076#endif
4077 PHDASTREAM pStreamFront = hdaGetStreamFromSink(pThis, &pThis->SinkFront);
4078#ifdef VBOX_WITH_HDA_51_SURROUND
4079 /** @todo See note below. */
4080#endif
4081
4082 uint32_t cbLineIn;
4083 AudioMixerSinkTimerUpdate(pThis->SinkLineIn.pMixSink, pThis->cTimerTicks, cTicksElapsed, &cbLineIn);
4084 if (cbLineIn)
4085 hdaTransfer(pThis, pStreamLineIn, cbLineIn, NULL); /** @todo Add rc! */
4086
4087#ifdef VBOX_WITH_HDA_MIC_IN
4088 uint32_t cbMicIn;
4089 AudioMixerSinkTimerUpdate(pThis->SinkMicIn.pMixSink , pThis->cTimerTicks, cTicksElapsed, &cbMicIn);
4090#endif
4091
4092 uint32_t cbFront;
4093 AudioMixerSinkTimerUpdate(pThis->SinkFront.pMixSink, pThis->cTimerTicks, cTicksElapsed, &cbFront);
4094#ifdef VBOX_WITH_HDA_51_SURROUND
4095 uint32_t cbCenterLFE;
4096 AudioMixerSinkTimerUpdate(pThis->SinkCenterLFE.pMixSink, pThis->cTimerTicks, cTicksElapsed, &cbCenterLFE);
4097 uint32_t cbRear;
4098 AudioMixerSinkTimerUpdate(pThis->SinkRear.pMixSink, pThis->cTimerTicks, cTicksElapsed, &cbRear);
4099#endif
4100
4101 if (cbFront)
4102 hdaTransfer(pThis, pStreamFront, cbFront, NULL); /** @todo Add rc! */
4103#ifdef VBOX_WITH_HDA_51_SURROUND
4104 /*
4105 * Only call hdaTransfer if CenterLFE and/or Rear are on different SDs,
4106 * otherwise we have to use the interleaved streams support for getting the data
4107 * out of the Front sink (depending on the mapping layout).
4108 */
4109#endif
4110
4111 if ( ASMAtomicReadBool(&pThis->fTimerActive)
4112 || AudioMixerSinkHasData(pThis->SinkFront.pMixSink)
4113#ifdef VBOX_WITH_HDA_51_SURROUND
4114 || AudioMixerSinkHasData(pThis->SinkCenterLFE.pMixSink)
4115 || AudioMixerSinkHasData(pThis->SinkRear.pMixSink)
4116#endif
4117 || AudioMixerSinkHasData(pThis->SinkLineIn.pMixSink))
4118 {
4119 /* Kick the timer again. */
4120 uint64_t cTicks = pThis->cTimerTicks;
4121 /** @todo adjust cTicks down by now much cbOutMin represents. */
4122 TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
4123 }
4124
4125 STAM_PROFILE_STOP(&pThis->StatTimer, a);
4126}
4127
4128#else /* VBOX_WITH_AUDIO_CALLBACKS */
4129
4130static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4131{
4132 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
4133 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4134 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4135 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4136 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4137
4138 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4139 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4140
4141 PPDMAUDIOCALLBACKDATAIN pData = (PPDMAUDIOCALLBACKDATAIN)pvUser;
4142 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAIN), VERR_INVALID_PARAMETER);
4143
4144 return hdaTransfer(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
4145}
4146
4147static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4148{
4149 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
4150 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4151 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4152 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4153 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4154
4155 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4156 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4157
4158 PPDMAUDIOCALLBACKDATAOUT pData = (PPDMAUDIOCALLBACKDATAOUT)pvUser;
4159 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAOUT), VERR_INVALID_PARAMETER);
4160
4161 PHDASTATE pThis = pCtx->pThis;
4162
4163 int rc = hdaTransfer(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
4164 if ( RT_SUCCESS(rc)
4165 && pData->cbOutWritten)
4166 {
4167 PHDADRIVER pDrv;
4168 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4169 {
4170 uint32_t cSamplesPlayed;
4171 int rc2 = pDrv->pConnector->pfnPlay(pDrv->pConnector, &cSamplesPlayed);
4172 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
4173 }
4174 }
4175}
4176#endif /* VBOX_WITH_AUDIO_CALLBACKS */
4177
4178static int hdaTransfer(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToProcess, uint32_t *pcbProcessed)
4179{
4180 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4181 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4182 /* pcbProcessed is optional. */
4183
4184 if (ASMAtomicReadBool(&pThis->fInReset)) /* HDA controller in reset mode? Bail out. */
4185 {
4186 LogFlowFunc(("In reset mode, skipping\n"));
4187
4188 if (pcbProcessed)
4189 *pcbProcessed = 0;
4190 return VINF_SUCCESS;
4191 }
4192
4193 bool fProceed = true;
4194 int rc = RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
4195 if (RT_FAILURE(rc))
4196 return rc;
4197
4198 /* Stop request received? */
4199 if (pStream->State.fDoStop)
4200 {
4201 pStream->State.fActive = false;
4202
4203 rc = RTSemEventSignal(pStream->State.hStateChangedEvent);
4204 AssertRC(rc);
4205
4206 fProceed = false;
4207 }
4208 /* Is the stream not in a running state currently? */
4209 else if (!(HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)))
4210 fProceed = false;
4211 /* Nothing to process? */
4212 else if (!cbToProcess)
4213 fProceed = false;
4214
4215 if ((HDA_STREAM_REG(pThis, STS, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
4216 {
4217 Log3Func(("[SD%RU8]: BCIS set\n", pStream->u8SD));
4218 fProceed = false;
4219 }
4220
4221 if (!fProceed)
4222 {
4223 Log3Func(("[SD%RU8] Skipping\n", pStream->u8SD));
4224
4225 rc = RTSemMutexRelease(pStream->State.hMtx);
4226 AssertRC(rc);
4227
4228 if (pcbProcessed)
4229 *pcbProcessed = 0;
4230 return VINF_SUCCESS;
4231 }
4232
4233 /* Sanity checks. */
4234 Assert(pStream->u8SD <= HDA_MAX_STREAMS);
4235 Assert(pStream->u64BDLBase);
4236 Assert(pStream->u32CBL);
4237
4238 /* State sanity checks. */
4239 Assert(pStream->State.fInReset == false);
4240
4241 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
4242 Assert(u32LPIB <= pStream->u32CBL);
4243
4244 uint32_t cbLeft = cbToProcess;
4245 uint32_t cbTotal = 0;
4246
4247 bool fInterrupt = false;
4248
4249 Log3Func(("cbLeft=%RU32\n", cbLeft));
4250
4251#define FOO
4252
4253#ifdef FOO
4254 uint8_t u8FIFO[_16K+1];
4255 size_t u8FIFOff = 0;
4256#endif
4257
4258 /* Set the FIFORDY bit on the stream while doing the transfer. */
4259 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
4260
4261 while (cbLeft)
4262 {
4263 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
4264 if (hdaStreamNeedsNextBDLE(pThis, pStream))
4265 {
4266 rc = hdaStreamGetNextBDLE(pThis, pStream);
4267 if (RT_FAILURE(rc))
4268 break;
4269 }
4270
4271 uint32_t cbProcessed = 0;
4272 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
4273 rc = hdaReadAudio (pThis, pStream, cbLeft, &cbProcessed);
4274 else
4275 {
4276#ifndef FOO
4277 rc = hdaWriteAudio(pThis, pStream, cbLeft, &cbProcessed);
4278#else
4279 uint32_t cbToWrite = hdaStreamGetTransferSize(pThis, pStream, cbLeft);
4280
4281 void *pvBuf = u8FIFO + u8FIFOff;
4282 int32_t cbBuf = cbToWrite;
4283
4284 PHDABDLE pBDLE = &pStream->State.BDLE;
4285
4286 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
4287 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
4288 pvBuf, cbBuf);
4289
4290 hdaBDLEUpdate(pBDLE, cbToWrite, cbToWrite);
4291
4292 LogFlowFunc(("u8FIFOff=%zu, cbLeft=%RU32, cbToWrite=%RU32\n", u8FIFOff, cbLeft, cbToWrite));
4293
4294 u8FIFOff += cbToWrite;
4295 Assert(u8FIFOff <= sizeof(u8FIFO));
4296
4297 cbProcessed = cbToWrite;
4298#endif
4299 }
4300
4301 if (RT_FAILURE(rc))
4302 break;
4303
4304 hdaStreamTransferUpdate(pThis, pStream, cbProcessed);
4305
4306 Assert(cbLeft >= cbProcessed);
4307 cbLeft -= cbProcessed;
4308 cbTotal += cbProcessed;
4309
4310 LogFlowFunc(("cbProcessed=%RU32, cbLeft=%RU32, cbTotal=%RU32, rc=%Rrc\n",
4311 cbProcessed, cbLeft, cbTotal, rc));
4312
4313 if (rc == VINF_EOF)
4314 break;
4315
4316 if (hdaStreamTransferIsComplete(pThis, pStream, &fInterrupt))
4317 break;
4318 }
4319
4320 /* Remove the FIFORDY bit again. */
4321 HDA_STREAM_REG(pThis, STS, pStream->u8SD) &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
4322
4323#ifdef FOO
4324 #if defined (RT_OS_LINUX) && defined(DEBUG_andy)
4325 RTFILE fh;
4326 RTFileOpen(&fh, "/tmp/hdaWriteAudio.pcm",
4327 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4328 RTFileWrite(fh, u8FIFO, u8FIFOff, NULL);
4329 RTFileClose(fh);
4330 #endif
4331#if 1
4332 AudioMixerSinkWrite(pThis->SinkFront.pMixSink, AUDMIXOP_COPY, u8FIFO, u8FIFOff,
4333 NULL /* pcbWritten */);
4334#endif
4335#endif
4336
4337#ifdef FOO
4338 if (fInterrupt)
4339 {
4340 /**
4341 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
4342 * last byte of data for the current descriptor has been fetched
4343 * from memory and put into the DMA FIFO.
4344 *
4345 * Speech synthesis works fine on Mac Guest if this bit isn't set
4346 * but in general sound quality gets worse.
4347 *
4348 * This must be set in *any* case.
4349 */
4350 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
4351 Log3Func(("[SD%RU8]: BCIS: Set\n", pStream->u8SD));
4352
4353 hdaProcessInterrupt(pThis);
4354 }
4355#endif
4356
4357 Log3Func(("Written %RU32 / %RU32 (left: %RU32), rc=%Rrc\n", cbTotal, cbToProcess, cbLeft, rc));
4358
4359 if (RT_SUCCESS(rc))
4360 {
4361 if (pcbProcessed)
4362 *pcbProcessed = cbTotal;
4363 }
4364
4365 int rc2 = RTSemMutexRelease(pStream->State.hMtx);
4366 if (RT_SUCCESS(rc))
4367 rc = rc2;
4368
4369 return rc;
4370}
4371#endif /* IN_RING3 */
4372
4373/* MMIO callbacks */
4374
4375/**
4376 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
4377 *
4378 * @note During implementation, we discovered so-called "forgotten" or "hole"
4379 * registers whose description is not listed in the RPM, datasheet, or
4380 * spec.
4381 */
4382PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4383{
4384 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4385 int rc;
4386
4387 /*
4388 * Look up and log.
4389 */
4390 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4391 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
4392#ifdef LOG_ENABLED
4393 unsigned const cbLog = cb;
4394 uint32_t offRegLog = offReg;
4395#endif
4396
4397 Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
4398 Assert(cb == 4); Assert((offReg & 3) == 0);
4399
4400 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4401 LogFunc(("Access to registers except GCTL is blocked while reset\n"));
4402
4403 if (idxRegDsc == -1)
4404 LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
4405
4406 if (idxRegDsc != -1)
4407 {
4408 /* ASSUMES gapless DWORD at end of map. */
4409 if (g_aHdaRegMap[idxRegDsc].size == 4)
4410 {
4411 /*
4412 * Straight forward DWORD access.
4413 */
4414 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
4415 Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
4416 }
4417 else
4418 {
4419 /*
4420 * Multi register read (unless there are trailing gaps).
4421 * ASSUMES that only DWORD reads have sideeffects.
4422 */
4423 uint32_t u32Value = 0;
4424 unsigned cbLeft = 4;
4425 do
4426 {
4427 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
4428 uint32_t u32Tmp = 0;
4429
4430 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
4431 Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
4432 if (rc != VINF_SUCCESS)
4433 break;
4434 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
4435
4436 cbLeft -= cbReg;
4437 offReg += cbReg;
4438 idxRegDsc++;
4439 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
4440
4441 if (rc == VINF_SUCCESS)
4442 *(uint32_t *)pv = u32Value;
4443 else
4444 Assert(!IOM_SUCCESS(rc));
4445 }
4446 }
4447 else
4448 {
4449 rc = VINF_IOM_MMIO_UNUSED_FF;
4450 Log3Func(("\tHole at %x is accessed for read\n", offReg));
4451 }
4452
4453 /*
4454 * Log the outcome.
4455 */
4456#ifdef LOG_ENABLED
4457 if (cbLog == 4)
4458 Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
4459 else if (cbLog == 2)
4460 Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
4461 else if (cbLog == 1)
4462 Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
4463#endif
4464 return rc;
4465}
4466
4467
4468DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
4469{
4470 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4471 {
4472 LogRel2(("HDA: Warning: Access to register 0x%x is blocked while reset\n", idxRegDsc));
4473 return VINF_SUCCESS;
4474 }
4475
4476 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4477#ifdef LOG_ENABLED
4478 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
4479#endif
4480 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
4481 Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
4482 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
4483 return rc;
4484}
4485
4486
4487/**
4488 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
4489 */
4490PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
4491{
4492 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4493 int rc;
4494
4495 /*
4496 * The behavior of accesses that aren't aligned on natural boundraries is
4497 * undefined. Just reject them outright.
4498 */
4499 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
4500 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
4501 if (GCPhysAddr & (cb - 1))
4502 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
4503
4504 /*
4505 * Look up and log the access.
4506 */
4507 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4508 int idxRegDsc = hdaRegLookup(pThis, offReg);
4509 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
4510 uint64_t u64Value;
4511 if (cb == 4) u64Value = *(uint32_t const *)pv;
4512 else if (cb == 2) u64Value = *(uint16_t const *)pv;
4513 else if (cb == 1) u64Value = *(uint8_t const *)pv;
4514 else if (cb == 8) u64Value = *(uint64_t const *)pv;
4515 else
4516 {
4517 u64Value = 0; /* shut up gcc. */
4518 AssertReleaseMsgFailed(("%u\n", cb));
4519 }
4520
4521#ifdef LOG_ENABLED
4522 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
4523 if (idxRegDsc == -1)
4524 Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
4525 else if (cb == 4)
4526 Log3Func(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4527 else if (cb == 2)
4528 Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4529 else if (cb == 1)
4530 Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4531
4532 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
4533 Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
4534#endif
4535
4536 /*
4537 * Try for a direct hit first.
4538 */
4539 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
4540 {
4541 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
4542 Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
4543 }
4544 /*
4545 * Partial or multiple register access, loop thru the requested memory.
4546 */
4547 else
4548 {
4549 /*
4550 * If it's an access beyond the start of the register, shift the input
4551 * value and fill in missing bits. Natural alignment rules means we
4552 * will only see 1 or 2 byte accesses of this kind, so no risk of
4553 * shifting out input values.
4554 */
4555 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
4556 {
4557 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
4558 offReg -= cbBefore;
4559 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4560 u64Value <<= cbBefore * 8;
4561 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
4562 Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
4563 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
4564 }
4565
4566 /* Loop thru the write area, it may cover multiple registers. */
4567 rc = VINF_SUCCESS;
4568 for (;;)
4569 {
4570 uint32_t cbReg;
4571 if (idxRegDsc != -1)
4572 {
4573 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4574 cbReg = g_aHdaRegMap[idxRegDsc].size;
4575 if (cb < cbReg)
4576 {
4577 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
4578 Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
4579 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
4580 }
4581 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
4582 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
4583 Log3Func(("\t%#x -> %#x\n", u32LogOldVal, pThis->au32Regs[idxRegMem]));
4584 }
4585 else
4586 {
4587 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
4588 cbReg = 1;
4589 }
4590 if (rc != VINF_SUCCESS)
4591 break;
4592 if (cbReg >= cb)
4593 break;
4594
4595 /* Advance. */
4596 offReg += cbReg;
4597 cb -= cbReg;
4598 u64Value >>= cbReg * 8;
4599 if (idxRegDsc == -1)
4600 idxRegDsc = hdaRegLookup(pThis, offReg);
4601 else
4602 {
4603 idxRegDsc++;
4604 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
4605 || g_aHdaRegMap[idxRegDsc].offset != offReg)
4606 {
4607 idxRegDsc = -1;
4608 }
4609 }
4610 }
4611 }
4612
4613 return rc;
4614}
4615
4616
4617/* PCI callback. */
4618
4619#ifdef IN_RING3
4620/**
4621 * @callback_method_impl{FNPCIIOREGIONMAP}
4622 */
4623static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
4624 PCIADDRESSSPACE enmType)
4625{
4626 PPDMDEVINS pDevIns = pPciDev->pDevIns;
4627 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
4628 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
4629 int rc;
4630
4631 /*
4632 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
4633 *
4634 * Let IOM talk DWORDs when reading, saves a lot of complications. On
4635 * writing though, we have to do it all ourselves because of sideeffects.
4636 */
4637 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
4638 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
4639 IOMMMIO_FLAGS_READ_DWORD
4640 | IOMMMIO_FLAGS_WRITE_PASSTHRU,
4641 hdaMMIOWrite, hdaMMIORead, "HDA");
4642
4643 if (RT_FAILURE(rc))
4644 return rc;
4645
4646 if (pThis->fR0Enabled)
4647 {
4648 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
4649 "hdaMMIOWrite", "hdaMMIORead");
4650 if (RT_FAILURE(rc))
4651 return rc;
4652 }
4653
4654 if (pThis->fRCEnabled)
4655 {
4656 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
4657 "hdaMMIOWrite", "hdaMMIORead");
4658 if (RT_FAILURE(rc))
4659 return rc;
4660 }
4661
4662 pThis->MMIOBaseAddr = GCPhysAddress;
4663 return VINF_SUCCESS;
4664}
4665
4666
4667/* Saved state callbacks. */
4668
4669static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
4670{
4671 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4672
4673 LogFlowFunc(("[SD%RU8]\n", pStrm->u8SD));
4674
4675 /* Save stream ID. */
4676 int rc = SSMR3PutU8(pSSM, pStrm->u8SD);
4677 AssertRCReturn(rc, rc);
4678 Assert(pStrm->u8SD <= HDA_MAX_STREAMS);
4679
4680 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields6, NULL);
4681 AssertRCReturn(rc, rc);
4682
4683#ifdef DEBUG /* Sanity checks. */
4684 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrm->u8SD),
4685 HDA_STREAM_REG(pThis, BDPU, pStrm->u8SD));
4686 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStrm->u8SD);
4687 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStrm->u8SD);
4688
4689 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
4690
4691 Assert(u64BaseDMA == pStrm->u64BDLBase);
4692 Assert(u16LVI == pStrm->u16LVI);
4693 Assert(u32CBL == pStrm->u32CBL);
4694#endif
4695
4696 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
4697 0 /*fFlags*/, g_aSSMBDLEFields6, NULL);
4698 AssertRCReturn(rc, rc);
4699
4700 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
4701 0 /*fFlags*/, g_aSSMBDLEStateFields6, NULL);
4702 AssertRCReturn(rc, rc);
4703
4704#ifdef DEBUG /* Sanity checks. */
4705 PHDABDLE pBDLE = &pStrm->State.BDLE;
4706 if (u64BaseDMA)
4707 {
4708 Assert(pStrm->State.uCurBDLE <= u16LVI + 1);
4709
4710 HDABDLE curBDLE;
4711 rc = hdaBDLEFetch(pThis, &curBDLE, u64BaseDMA, pStrm->State.uCurBDLE);
4712 AssertRC(rc);
4713
4714 Assert(curBDLE.u32BufSize == pBDLE->u32BufSize);
4715 Assert(curBDLE.u64BufAdr == pBDLE->u64BufAdr);
4716 Assert(curBDLE.fIntOnCompletion == pBDLE->fIntOnCompletion);
4717 }
4718 else
4719 {
4720 Assert(pBDLE->u64BufAdr == 0);
4721 Assert(pBDLE->u32BufSize == 0);
4722 }
4723#endif
4724 return rc;
4725}
4726
4727/**
4728 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4729 */
4730static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4731{
4732 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4733
4734 /* Save Codec nodes states. */
4735 hdaCodecSaveState(pThis->pCodec, pSSM);
4736
4737 /* Save MMIO registers. */
4738 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
4739 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4740
4741 /* Save number of streams. */
4742 SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
4743
4744 /* Save stream states. */
4745 int rc;
4746 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4747 {
4748 rc = hdaSaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
4749 AssertRCReturn(rc, rc);
4750 }
4751
4752 return rc;
4753}
4754
4755
4756/**
4757 * @callback_method_impl{FNSSMDEVLOADEXEC}
4758 */
4759static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4760{
4761 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4762
4763 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
4764
4765 LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
4766
4767 /*
4768 * Load Codec nodes states.
4769 */
4770 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
4771 if (RT_FAILURE(rc))
4772 {
4773 LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
4774 return rc;
4775 }
4776
4777 /*
4778 * Load MMIO registers.
4779 */
4780 uint32_t cRegs;
4781 switch (uVersion)
4782 {
4783 case HDA_SSM_VERSION_1:
4784 /* Starting with r71199, we would save 112 instead of 113
4785 registers due to some code cleanups. This only affected trunk
4786 builds in the 4.1 development period. */
4787 cRegs = 113;
4788 if (SSMR3HandleRevision(pSSM) >= 71199)
4789 {
4790 uint32_t uVer = SSMR3HandleVersion(pSSM);
4791 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
4792 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
4793 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
4794 cRegs = 112;
4795 }
4796 break;
4797
4798 case HDA_SSM_VERSION_2:
4799 case HDA_SSM_VERSION_3:
4800 cRegs = 112;
4801 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
4802 break;
4803
4804 /* Since version 4 we store the register count to stay flexible. */
4805 case HDA_SSM_VERSION_4:
4806 case HDA_SSM_VERSION_5:
4807 case HDA_SSM_VERSION:
4808 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
4809 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
4810 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
4811 break;
4812
4813 default:
4814 LogRel(("HDA: Unsupported / too new saved state version (%RU32)\n", uVersion));
4815 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4816 }
4817
4818 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
4819 {
4820 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4821 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
4822 }
4823 else
4824 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
4825
4826 /*
4827 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
4828 * *every* BDLE state, whereas it only needs to be stored
4829 * *once* for every stream. Most of the BDLE state we can
4830 * get out of the registers anyway, so just ignore those values.
4831 *
4832 * Also, only the current BDLE was saved, regardless whether
4833 * there were more than one (and there are at least two entries,
4834 * according to the spec).
4835 */
4836#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
4837 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
4838 AssertRCReturn(rc, rc); \
4839 rc = SSMR3GetU64(pSSM, &x.u64BufAdr); /* u64BdleCviAddr */ \
4840 AssertRCReturn(rc, rc); \
4841 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
4842 AssertRCReturn(rc, rc); \
4843 rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
4844 AssertRCReturn(rc, rc); \
4845 rc = SSMR3GetU32(pSSM, &x.u32BufSize); /* u32BdleCviLen */ \
4846 AssertRCReturn(rc, rc); \
4847 rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
4848 AssertRCReturn(rc, rc); \
4849 rc = SSMR3GetBool(pSSM, &x.fIntOnCompletion); /* fBdleCviIoc */ \
4850 AssertRCReturn(rc, rc); \
4851 rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
4852 AssertRCReturn(rc, rc); \
4853 rc = SSMR3GetMem(pSSM, &x.State.au8FIFO, sizeof(x.State.au8FIFO)); \
4854 AssertRCReturn(rc, rc); \
4855 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
4856 AssertRCReturn(rc, rc); \
4857
4858 /*
4859 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
4860 */
4861 switch (uVersion)
4862 {
4863 case HDA_SSM_VERSION_1:
4864 case HDA_SSM_VERSION_2:
4865 case HDA_SSM_VERSION_3:
4866 case HDA_SSM_VERSION_4:
4867 {
4868 /* Only load the internal states.
4869 * The rest will be initialized from the saved registers later. */
4870
4871 /* Note 1: Only the *current* BDLE for a stream was saved! */
4872 /* Note 2: The stream's saving order is/was fixed, so don't touch! */
4873
4874 /* Output */
4875 PHDASTREAM pStream = &pThis->aStreams[4];
4876 rc = hdaStreamInit(pThis, pStream, 4 /* Stream descriptor, hardcoded */);
4877 if (RT_FAILURE(rc))
4878 break;
4879 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
4880 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
4881
4882 /* Microphone-In */
4883 pStream = &pThis->aStreams[2];
4884 rc = hdaStreamInit(pThis, pStream, 2 /* Stream descriptor, hardcoded */);
4885 if (RT_FAILURE(rc))
4886 break;
4887 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
4888 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
4889
4890 /* Line-In */
4891 pStream = &pThis->aStreams[0];
4892 rc = hdaStreamInit(pThis, pStream, 0 /* Stream descriptor, hardcoded */);
4893 if (RT_FAILURE(rc))
4894 break;
4895 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
4896 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
4897 break;
4898 }
4899
4900 /* Since v5 we support flexible stream and BDLE counts. */
4901 case HDA_SSM_VERSION_5:
4902 case HDA_SSM_VERSION:
4903 {
4904 uint32_t cStreams;
4905 rc = SSMR3GetU32(pSSM, &cStreams);
4906 if (RT_FAILURE(rc))
4907 break;
4908
4909 LogRel2(("hdaLoadExec: cStreams=%RU32\n", cStreams));
4910
4911 /* Load stream states. */
4912 for (uint32_t i = 0; i < cStreams; i++)
4913 {
4914 uint8_t uSD;
4915 rc = SSMR3GetU8(pSSM, &uSD);
4916 if (RT_FAILURE(rc))
4917 break;
4918
4919 PHDASTREAM pStrm = hdaStreamFromSD(pThis, uSD);
4920 HDASTREAM StreamDummy;
4921
4922 if (!pStrm)
4923 {
4924 RT_ZERO(StreamDummy);
4925 pStrm = &StreamDummy;
4926 LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uSD));
4927 break;
4928 }
4929
4930 rc = hdaStreamInit(pThis, pStrm, uSD);
4931 if (RT_FAILURE(rc))
4932 {
4933 LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uSD, rc));
4934 break;
4935 }
4936
4937 if (uVersion == HDA_SSM_VERSION_5)
4938 {
4939 /* Get the current BDLE entry and skip the rest. */
4940 uint16_t cBDLE;
4941
4942 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
4943 AssertRC(rc);
4944 rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
4945 AssertRC(rc);
4946 rc = SSMR3GetU16(pSSM, &pStrm->State.uCurBDLE); /* uCurBDLE */
4947 AssertRC(rc);
4948 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
4949 AssertRC(rc);
4950
4951 uint32_t u32BDLEIndex;
4952 for (uint16_t a = 0; a < cBDLE; a++)
4953 {
4954 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
4955 AssertRC(rc);
4956 rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
4957 AssertRC(rc);
4958
4959 /* Does the current BDLE index match the current BDLE to process? */
4960 if (u32BDLEIndex == pStrm->State.uCurBDLE)
4961 {
4962 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
4963 AssertRC(rc);
4964 rc = SSMR3GetMem(pSSM,
4965 &pStrm->State.BDLE.State.au8FIFO,
4966 sizeof(pStrm->State.BDLE.State.au8FIFO)); /* au8FIFO */
4967 AssertRC(rc);
4968 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.u32BufOff); /* u32BufOff */
4969 AssertRC(rc);
4970 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
4971 AssertRC(rc);
4972 }
4973 else /* Skip not current BDLEs. */
4974 {
4975 rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
4976 + sizeof(uint8_t) * 256 /* au8FIFO */
4977 + sizeof(uint32_t) /* u32BufOff */
4978 + sizeof(uint32_t)); /* End marker */
4979 AssertRC(rc);
4980 }
4981 }
4982 }
4983 else
4984 {
4985 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE),
4986 0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
4987 if (RT_FAILURE(rc))
4988 break;
4989
4990 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
4991 0 /* fFlags */, g_aSSMBDLEFields6, NULL);
4992 if (RT_FAILURE(rc))
4993 break;
4994
4995 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
4996 0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
4997 if (RT_FAILURE(rc))
4998 break;
4999 }
5000 }
5001 break;
5002 }
5003
5004 default:
5005 AssertReleaseFailed(); /* Never reached. */
5006 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5007 }
5008
5009#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
5010
5011 if (RT_SUCCESS(rc))
5012 {
5013 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
5014 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
5015 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
5016
5017 /* Also make sure to update the DMA position bit if this was enabled when saving the state. */
5018 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
5019 }
5020
5021 if (RT_SUCCESS(rc))
5022 {
5023 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5024 {
5025 PHDASTREAM pStream = hdaStreamFromSD(pThis, i);
5026 if (pStream)
5027 {
5028 bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
5029 LogFlowFunc(("[SD%RU8]: fActive=%RTbool\n", i, fActive));
5030 int rc2 = hdaStreamSetActive(pThis, pStream, fActive);
5031 AssertRC(rc2);
5032 }
5033 }
5034 }
5035
5036 if (RT_FAILURE(rc))
5037 LogRel(("HDA: Failed loading device state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5038
5039 LogFlowFuncLeaveRC(rc);
5040 return rc;
5041}
5042
5043#ifdef DEBUG
5044/* Debug and log type formatters. */
5045
5046/**
5047 * @callback_method_impl{FNRTSTRFORMATTYPE}
5048 */
5049static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5050 const char *pszType, void const *pvValue,
5051 int cchWidth, int cchPrecision, unsigned fFlags,
5052 void *pvUser)
5053{
5054 PHDABDLE pBDLE = (PHDABDLE)pvValue;
5055 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5056 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
5057 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW, pBDLE->fIntOnCompletion,
5058 pBDLE->u32BufSize, pBDLE->u64BufAdr);
5059}
5060
5061/**
5062 * @callback_method_impl{FNRTSTRFORMATTYPE}
5063 */
5064static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5065 const char *pszType, void const *pvValue,
5066 int cchWidth, int cchPrecision, unsigned fFlags,
5067 void *pvUser)
5068{
5069 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
5070 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5071 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
5072 uSDCTL,
5073 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
5074 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
5075 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
5076 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
5077 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
5078 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
5079 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
5080 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
5081}
5082
5083/**
5084 * @callback_method_impl{FNRTSTRFORMATTYPE}
5085 */
5086static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5087 const char *pszType, void const *pvValue,
5088 int cchWidth, int cchPrecision, unsigned fFlags,
5089 void *pvUser)
5090{
5091 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
5092 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, hdaSDFIFOSToBytes(uSDFIFOS));
5093}
5094
5095/**
5096 * @callback_method_impl{FNRTSTRFORMATTYPE}
5097 */
5098static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5099 const char *pszType, void const *pvValue,
5100 int cchWidth, int cchPrecision, unsigned fFlags,
5101 void *pvUser)
5102{
5103 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
5104 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
5105}
5106
5107/**
5108 * @callback_method_impl{FNRTSTRFORMATTYPE}
5109 */
5110static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5111 const char *pszType, void const *pvValue,
5112 int cchWidth, int cchPrecision, unsigned fFlags,
5113 void *pvUser)
5114{
5115 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
5116 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5117 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
5118 uSdSts,
5119 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
5120 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
5121 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
5122 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
5123}
5124
5125static int hdaDbgLookupRegByName(PHDASTATE pThis, const char *pszArgs)
5126{
5127 int iReg = 0;
5128 for (; iReg < HDA_NUM_REGS; ++iReg)
5129 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
5130 return iReg;
5131 return -1;
5132}
5133
5134
5135static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
5136{
5137 Assert( pThis
5138 && iHdaIndex >= 0
5139 && iHdaIndex < HDA_NUM_REGS);
5140 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
5141}
5142
5143/**
5144 * @callback_method_impl{FNDBGFHANDLERDEV}
5145 */
5146static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5147{
5148 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5149 int iHdaRegisterIndex = hdaDbgLookupRegByName(pThis, pszArgs);
5150 if (iHdaRegisterIndex != -1)
5151 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5152 else
5153 {
5154 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
5155 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5156 }
5157}
5158
5159static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5160{
5161 Assert( pThis
5162 && iIdx >= 0
5163 && iIdx < HDA_MAX_STREAMS);
5164
5165 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5166
5167 pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
5168 pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
5169 pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
5170 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
5171 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
5172 pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStrm->State.BDLE);
5173}
5174
5175static void hdaDbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5176{
5177 Assert( pThis
5178 && iIdx >= 0
5179 && iIdx < HDA_MAX_STREAMS);
5180
5181 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5182 const PHDABDLE pBDLE = &pStrm->State.BDLE;
5183
5184 pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
5185 pHlp->pfnPrintf(pHlp, "\t%R[bdle]\n", pBDLE);
5186
5187 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
5188 HDA_STREAM_REG(pThis, BDPU, iIdx));
5189 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
5190 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
5191
5192 if (!u64BaseDMA)
5193 return;
5194
5195 uint32_t cbBDLE = 0;
5196 for (uint16_t i = 0; i < u16LVI + 1; i++)
5197 {
5198 uint8_t bdle[16]; /** @todo Use a define. */
5199 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * 16, bdle, 16); /** @todo Use a define. */
5200
5201 uint64_t addr = *(uint64_t *)bdle;
5202 uint32_t len = *(uint32_t *)&bdle[8];
5203 uint32_t ioc = *(uint32_t *)&bdle[12];
5204
5205 pHlp->pfnPrintf(pHlp, "\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
5206 i, addr, len, RT_BOOL(ioc & 0x1));
5207
5208 cbBDLE += len;
5209 }
5210
5211 pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
5212
5213 pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", pThis->u64DPBase);
5214 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
5215 {
5216 pHlp->pfnPrintf(pHlp, "No counters found\n");
5217 return;
5218 }
5219
5220 for (int i = 0; i < u16LVI + 1; i++)
5221 {
5222 uint32_t uDMACnt;
5223 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
5224 &uDMACnt, sizeof(uDMACnt));
5225
5226 pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
5227 }
5228}
5229
5230static int hdaDbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
5231{
5232 /** @todo Add args parsing. */
5233 return -1;
5234}
5235
5236/**
5237 * @callback_method_impl{FNDBGFHANDLERDEV}
5238 */
5239static DECLCALLBACK(void) hdaDbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5240{
5241 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5242 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5243 if (iHdaStreamdex != -1)
5244 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5245 else
5246 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5247 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5248}
5249
5250/**
5251 * @callback_method_impl{FNDBGFHANDLERDEV}
5252 */
5253static DECLCALLBACK(void) hdaDbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5254{
5255 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5256 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5257 if (iHdaStreamdex != -1)
5258 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5259 else
5260 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5261 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5262}
5263
5264/**
5265 * @callback_method_impl{FNDBGFHANDLERDEV}
5266 */
5267static DECLCALLBACK(void) hdaDbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5268{
5269 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5270
5271 if (pThis->pCodec->pfnDbgListNodes)
5272 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
5273 else
5274 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5275}
5276
5277/**
5278 * @callback_method_impl{FNDBGFHANDLERDEV}
5279 */
5280static DECLCALLBACK(void) hdaDbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5281{
5282 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5283
5284 if (pThis->pCodec->pfnDbgSelector)
5285 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
5286 else
5287 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5288}
5289
5290/**
5291 * @callback_method_impl{FNDBGFHANDLERDEV}
5292 */
5293static DECLCALLBACK(void) hdaDbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5294{
5295 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5296
5297 if (pThis->pMixer)
5298 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
5299 else
5300 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
5301}
5302#endif /* DEBUG */
5303
5304/* PDMIBASE */
5305
5306/**
5307 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5308 */
5309static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
5310{
5311 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
5312 Assert(&pThis->IBase == pInterface);
5313
5314 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5315 return NULL;
5316}
5317
5318
5319/* PDMDEVREG */
5320
5321/**
5322 * Reset notification.
5323 *
5324 * @returns VBox status code.
5325 * @param pDevIns The device instance data.
5326 *
5327 * @remark The original sources didn't install a reset handler, but it seems to
5328 * make sense to me so we'll do it.
5329 */
5330static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
5331{
5332 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5333
5334 LogFlowFuncEnter();
5335
5336# ifndef VBOX_WITH_AUDIO_CALLBACKS
5337 /*
5338 * Stop the timer, if any.
5339 */
5340 hdaTimerMaybeStop(pThis);
5341# endif
5342
5343 /* See 6.2.1. */
5344 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO /* Ouput streams */,
5345 HDA_MAX_SDI /* Input streams */,
5346 0 /* Bidirectional output streams */,
5347 0 /* Serial data out signals */,
5348 1 /* 64-bit */);
5349 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
5350 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
5351 /* Announce the full 60 words output payload. */
5352 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
5353 /* Announce the full 29 words input payload. */
5354 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
5355 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
5356 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
5357 HDA_REG(pThis, CORBRP) = 0x0;
5358 HDA_REG(pThis, RIRBWP) = 0x0;
5359
5360 /*
5361 * Stop any audio currently playing and/or recording.
5362 */
5363 AudioMixerSinkCtl(pThis->SinkFront.pMixSink, AUDMIXSINKCMD_DISABLE);
5364# ifdef VBOX_WITH_HDA_MIC_IN
5365 AudioMixerSinkCtl(pThis->SinkMicIn.pMixSink, AUDMIXSINKCMD_DISABLE);
5366# endif
5367 AudioMixerSinkCtl(pThis->SinkLineIn.pMixSink, AUDMIXSINKCMD_DISABLE);
5368# ifdef VBOX_WITH_HDA_51_SURROUND
5369 AudioMixerSinkCtl(pThis->SinkCenterLFE.pMixSink, AUDMIXSINKCMD_DISABLE);
5370 AudioMixerSinkCtl(pThis->SinkRear.pMixSink, AUDMIXSINKCMD_DISABLE);
5371# endif
5372
5373 /*
5374 * Set some sensible defaults for which HDA sinks
5375 * are connected to which stream number.
5376 *
5377 * We use SD0 for input and SD4 for output by default.
5378 * These stream numbers can be changed by the guest dynamically lateron.
5379 */
5380#ifdef VBOX_WITH_HDA_MIC_IN
5381 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 */, 0 /* Channel */);
5382#endif
5383 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 */, 0 /* Channel */);
5384
5385 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 */, 0 /* Channel */);
5386#ifdef VBOX_WITH_HDA_51_SURROUND
5387 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 */, 0 /* Channel */);
5388 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 */, 0 /* Channel */);
5389#endif
5390
5391 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
5392
5393 if (pThis->pu32CorbBuf)
5394 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
5395 else
5396 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5397
5398 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
5399 if (pThis->pu64RirbBuf)
5400 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
5401 else
5402 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5403
5404 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
5405
5406 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5407 {
5408 /* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
5409 HDA_STREAM_REG(pThis, CTL, i) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN);
5410 hdaStreamReset(pThis, &pThis->aStreams[i]);
5411 }
5412
5413 /* Clear stream tags <-> objects mapping table. */
5414 RT_ZERO(pThis->aTags);
5415
5416 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
5417 HDA_REG(pThis, STATESTS) = 0x1;
5418
5419# ifndef VBOX_WITH_AUDIO_CALLBACKS
5420 hdaTimerMaybeStart(pThis);
5421# endif
5422
5423 LogFlowFuncLeave();
5424 LogRel(("HDA: Reset\n"));
5425}
5426
5427/**
5428 * @interface_method_impl{PDMDEVREG,pfnDestruct}
5429 */
5430static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
5431{
5432 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5433
5434 PHDADRIVER pDrv;
5435 while (!RTListIsEmpty(&pThis->lstDrv))
5436 {
5437 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
5438
5439 RTListNodeRemove(&pDrv->Node);
5440 RTMemFree(pDrv);
5441 }
5442
5443 if (pThis->pCodec)
5444 {
5445 hdaCodecDestruct(pThis->pCodec);
5446
5447 RTMemFree(pThis->pCodec);
5448 pThis->pCodec = NULL;
5449 }
5450
5451 RTMemFree(pThis->pu32CorbBuf);
5452 pThis->pu32CorbBuf = NULL;
5453
5454 RTMemFree(pThis->pu64RirbBuf);
5455 pThis->pu64RirbBuf = NULL;
5456
5457 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5458 hdaStreamDestroy(&pThis->aStreams[i]);
5459
5460 return VINF_SUCCESS;
5461}
5462
5463
5464/**
5465 * Attach command, internal version.
5466 *
5467 * This is called to let the device attach to a driver for a specified LUN
5468 * during runtime. This is not called during VM construction, the device
5469 * constructor has to attach to all the available drivers.
5470 *
5471 * @returns VBox status code.
5472 * @param pDevIns The device instance.
5473 * @param pDrv Driver to (re-)use for (re-)attaching to.
5474 * If NULL is specified, a new driver will be created and appended
5475 * to the driver list.
5476 * @param uLUN The logical unit which is being detached.
5477 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5478 */
5479static int hdaAttachInternal(PPDMDEVINS pDevIns, PHDADRIVER pDrv, unsigned uLUN, uint32_t fFlags)
5480{
5481 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5482
5483 /*
5484 * Attach driver.
5485 */
5486 char *pszDesc = NULL;
5487 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
5488 AssertReleaseMsgReturn(pszDesc,
5489 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
5490 VERR_NO_MEMORY);
5491
5492 PPDMIBASE pDrvBase;
5493 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
5494 &pThis->IBase, &pDrvBase, pszDesc);
5495 if (RT_SUCCESS(rc))
5496 {
5497 if (pDrv == NULL)
5498 pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
5499 if (pDrv)
5500 {
5501 pDrv->pDrvBase = pDrvBase;
5502 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
5503 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
5504 pDrv->pHDAState = pThis;
5505 pDrv->uLUN = uLUN;
5506
5507 /*
5508 * For now we always set the driver at LUN 0 as our primary
5509 * host backend. This might change in the future.
5510 */
5511 if (pDrv->uLUN == 0)
5512 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
5513
5514 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
5515
5516 /* Attach to driver list if not attached yet. */
5517 if (!pDrv->fAttached)
5518 {
5519 RTListAppend(&pThis->lstDrv, &pDrv->Node);
5520 pDrv->fAttached = true;
5521 }
5522 }
5523 else
5524 rc = VERR_NO_MEMORY;
5525 }
5526 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5527 LogFunc(("No attached driver for LUN #%u\n", uLUN));
5528
5529 if (RT_FAILURE(rc))
5530 {
5531 /* Only free this string on failure;
5532 * must remain valid for the live of the driver instance. */
5533 RTStrFree(pszDesc);
5534 }
5535
5536 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
5537 return rc;
5538}
5539
5540/**
5541 * Attach command.
5542 *
5543 * This is called to let the device attach to a driver for a specified LUN
5544 * during runtime. This is not called during VM construction, the device
5545 * constructor has to attach to all the available drivers.
5546 *
5547 * @returns VBox status code.
5548 * @param pDevIns The device instance.
5549 * @param uLUN The logical unit which is being detached.
5550 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5551 */
5552static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5553{
5554 return hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
5555}
5556
5557static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5558{
5559 LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
5560}
5561
5562/**
5563 * Powers off the device.
5564 *
5565 * @param pDevIns Device instance to power off.
5566 */
5567static DECLCALLBACK(void) hdaPowerOff(PPDMDEVINS pDevIns)
5568{
5569 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5570
5571 LogRel2(("HDA: Powering off ...\n"));
5572
5573 /* Ditto goes for the codec, which in turn uses the mixer. */
5574 hdaCodecPowerOff(pThis->pCodec);
5575
5576 /**
5577 * Note: Destroy the mixer while powering off and *not* in hdaDestruct,
5578 * giving the mixer the chance to release any references held to
5579 * PDM audio streams it maintains.
5580 */
5581 if (pThis->pMixer)
5582 {
5583 AudioMixerDestroy(pThis->pMixer);
5584 pThis->pMixer = NULL;
5585 }
5586}
5587
5588/**
5589 * Re-attaches a new driver to the device's driver chain.
5590 *
5591 * @returns VBox status code.
5592 * @param pThis Device instance to re-attach driver to.
5593 * @param pDrv Driver instance used for attaching to.
5594 * If NULL is specified, a new driver will be created and appended
5595 * to the driver list.
5596 * @param uLUN The logical unit which is being re-detached.
5597 * @param pszDriver Driver name.
5598 */
5599static int hdaReattach(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
5600{
5601 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
5602 AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
5603
5604 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
5605 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
5606 PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
5607
5608 /* Remove LUN branch. */
5609 CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
5610
5611 if (pDrv)
5612 {
5613 /* Re-use a driver instance => detach the driver before. */
5614 int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
5615 if (RT_FAILURE(rc))
5616 return rc;
5617 }
5618
5619#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
5620
5621 int rc = VINF_SUCCESS;
5622 do
5623 {
5624 PCFGMNODE pLunL0;
5625 rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
5626 rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
5627 rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
5628
5629 PCFGMNODE pLunL1, pLunL2;
5630 rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
5631 rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
5632 rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
5633
5634 rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
5635
5636 } while (0);
5637
5638 if (RT_SUCCESS(rc))
5639 rc = hdaAttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
5640
5641 LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
5642
5643#undef RC_CHECK
5644
5645 return rc;
5646}
5647
5648/**
5649 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5650 */
5651static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5652{
5653 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5654 Assert(iInstance == 0);
5655 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5656
5657 /*
5658 * Validations.
5659 */
5660 if (!CFGMR3AreValuesValid(pCfg, "R0Enabled\0"
5661 "RCEnabled\0"
5662 "TimerHz\0"))
5663 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5664 N_ ("Invalid configuration for the Intel HDA device"));
5665
5666 int rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &pThis->fRCEnabled, false);
5667 if (RT_FAILURE(rc))
5668 return PDMDEV_SET_ERROR(pDevIns, rc,
5669 N_("HDA configuration error: failed to read RCEnabled as boolean"));
5670 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
5671 if (RT_FAILURE(rc))
5672 return PDMDEV_SET_ERROR(pDevIns, rc,
5673 N_("HDA configuration error: failed to read R0Enabled as boolean"));
5674#ifndef VBOX_WITH_AUDIO_CALLBACKS
5675 uint16_t uTimerHz;
5676 rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, 100 /* Hz */);
5677 if (RT_FAILURE(rc))
5678 return PDMDEV_SET_ERROR(pDevIns, rc,
5679 N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
5680#endif
5681
5682 /*
5683 * Initialize data (most of it anyway).
5684 */
5685 pThis->pDevInsR3 = pDevIns;
5686 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5687 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5688 /* IBase */
5689 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
5690
5691 /* PCI Device */
5692 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
5693 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
5694
5695 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
5696 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
5697 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
5698 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
5699 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
5700 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
5701 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
5702 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
5703 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
5704 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
5705 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
5706
5707#if defined(HDA_AS_PCI_EXPRESS)
5708 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
5709#elif defined(VBOX_WITH_MSI_DEVICES)
5710 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
5711#else
5712 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
5713#endif
5714
5715 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
5716 /// of these values needs to be properly documented!
5717 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
5718 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
5719
5720 /* Power Management */
5721 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
5722 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
5723 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
5724
5725#ifdef HDA_AS_PCI_EXPRESS
5726 /* PCI Express */
5727 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
5728 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
5729 /* Device flags */
5730 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
5731 /* version */ 0x1 |
5732 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
5733 /* MSI */ (100) << 9 );
5734 /* Device capabilities */
5735 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
5736 /* Device control */
5737 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
5738 /* Device status */
5739 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
5740 /* Link caps */
5741 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
5742 /* Link control */
5743 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
5744 /* Link status */
5745 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
5746 /* Slot capabilities */
5747 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
5748 /* Slot control */
5749 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
5750 /* Slot status */
5751 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
5752 /* Root control */
5753 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
5754 /* Root capabilities */
5755 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
5756 /* Root status */
5757 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
5758 /* Device capabilities 2 */
5759 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
5760 /* Device control 2 */
5761 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
5762 /* Link control 2 */
5763 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
5764 /* Slot control 2 */
5765 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
5766#endif
5767
5768 /*
5769 * Register the PCI device.
5770 */
5771 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5772 if (RT_FAILURE(rc))
5773 return rc;
5774
5775 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
5776 if (RT_FAILURE(rc))
5777 return rc;
5778
5779#ifdef VBOX_WITH_MSI_DEVICES
5780 PDMMSIREG MsiReg;
5781 RT_ZERO(MsiReg);
5782 MsiReg.cMsiVectors = 1;
5783 MsiReg.iMsiCapOffset = 0x60;
5784 MsiReg.iMsiNextOffset = 0x50;
5785 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5786 if (RT_FAILURE(rc))
5787 {
5788 /* That's OK, we can work without MSI */
5789 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
5790 }
5791#endif
5792
5793 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
5794 if (RT_FAILURE(rc))
5795 return rc;
5796
5797 RTListInit(&pThis->lstDrv);
5798
5799 uint8_t uLUN;
5800 for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
5801 {
5802 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
5803 rc = hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, 0 /* fFlags */);
5804 if (RT_FAILURE(rc))
5805 {
5806 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5807 rc = VINF_SUCCESS;
5808 else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
5809 {
5810 hdaReattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
5811 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
5812 N_("No audio devices could be opened. Selecting the NULL audio backend "
5813 "with the consequence that no sound is audible"));
5814 /* attaching to the NULL audio backend will never fail */
5815 rc = VINF_SUCCESS;
5816 }
5817 break;
5818 }
5819 }
5820
5821 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
5822
5823 if (RT_SUCCESS(rc))
5824 {
5825 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
5826 if (RT_SUCCESS(rc))
5827 {
5828 /* Set a default audio format for our mixer. */
5829 PDMAUDIOSTREAMCFG streamCfg;
5830 streamCfg.uHz = 44100;
5831 streamCfg.cChannels = 2;
5832 streamCfg.enmFormat = PDMAUDIOFMT_S16;
5833 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
5834
5835 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
5836 AssertRC(rc);
5837
5838 /*
5839 * Add mixer output sinks.
5840 */
5841#ifdef VBOX_WITH_HDA_51_SURROUND
5842 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
5843 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5844 AssertRC(rc);
5845 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
5846 AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
5847 AssertRC(rc);
5848 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
5849 AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
5850 AssertRC(rc);
5851#else
5852 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
5853 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5854 AssertRC(rc);
5855#endif
5856 /*
5857 * Add mixer input sinks.
5858 */
5859 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
5860 AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
5861 AssertRC(rc);
5862#ifdef VBOX_WITH_HDA_MIC_IN
5863 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
5864 AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
5865 AssertRC(rc);
5866#endif
5867 /* There is no master volume control. Set the master to max. */
5868 PDMAUDIOVOLUME vol = { false, 255, 255 };
5869 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
5870 AssertRC(rc);
5871 }
5872 }
5873
5874 if (RT_SUCCESS(rc))
5875 {
5876 /* Construct codec. */
5877 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
5878 if (!pThis->pCodec)
5879 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
5880
5881 /* Set codec callbacks. */
5882 pThis->pCodec->pfnMixerAddStream = hdaMixerAddStream;
5883 pThis->pCodec->pfnMixerRemoveStream = hdaMixerRemoveStream;
5884 pThis->pCodec->pfnMixerSetStream = hdaMixerSetStream;
5885 pThis->pCodec->pfnMixerSetVolume = hdaMixerSetVolume;
5886 pThis->pCodec->pfnReset = hdaCodecReset;
5887
5888 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
5889
5890 /* Construct the codec. */
5891 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
5892 if (RT_FAILURE(rc))
5893 AssertRCReturn(rc, rc);
5894
5895 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
5896 verb F20 should provide device/codec recognition. */
5897 Assert(pThis->pCodec->u16VendorId);
5898 Assert(pThis->pCodec->u16DeviceId);
5899 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
5900 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
5901 }
5902
5903 if (RT_SUCCESS(rc))
5904 {
5905 /*
5906 * Create all hardware streams.
5907 */
5908 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5909 {
5910 rc = hdaStreamCreate(&pThis->aStreams[i], i /* uSD */);
5911 AssertRC(rc);
5912 }
5913
5914 /*
5915 * Initialize the driver chain.
5916 */
5917 PHDADRIVER pDrv;
5918 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
5919 {
5920 /*
5921 * Only primary drivers are critical for the VM to run. Everything else
5922 * might not worth showing an own error message box in the GUI.
5923 */
5924 if (!(pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY))
5925 continue;
5926
5927 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
5928 AssertPtr(pCon);
5929
5930 bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
5931#ifdef VBOX_WITH_HDA_MIC_IN
5932 bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
5933#endif
5934 bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
5935#ifdef VBOX_WITH_HDA_51_SURROUND
5936 /** @todo Anything to do here? */
5937#endif
5938
5939 if ( !fValidLineIn
5940#ifdef VBOX_WITH_HDA_MIC_IN
5941 && !fValidMicIn
5942#endif
5943 && !fValidOut)
5944 {
5945 LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
5946
5947 hdaReset(pDevIns);
5948 hdaReattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
5949
5950 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
5951 N_("No audio devices could be opened. Selecting the NULL audio backend "
5952 "with the consequence that no sound is audible"));
5953 }
5954 else
5955 {
5956 bool fWarn = false;
5957
5958 PDMAUDIOBACKENDCFG backendCfg;
5959 int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
5960 if (RT_SUCCESS(rc2))
5961 {
5962 if (backendCfg.cSources)
5963 {
5964#ifdef VBOX_WITH_HDA_MIC_IN
5965 /* If the audio backend supports two or more input streams at once,
5966 * warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
5967 if (backendCfg.cMaxStreamsIn >= 2)
5968 fWarn = !fValidLineIn || !fValidMicIn;
5969 /* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
5970 * *not* ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
5971 * One of the two simply is not in use then. */
5972 else if (backendCfg.cMaxStreamsIn == 1)
5973 fWarn = !fValidLineIn && !fValidMicIn;
5974 /* Don't warn if our backend is not able of supporting any input streams at all. */
5975#else
5976 /* We only have line-in as input source. */
5977 fWarn = !fValidLineIn;
5978#endif
5979 }
5980
5981 if ( !fWarn
5982 && backendCfg.cSinks)
5983 {
5984 fWarn = !fValidOut;
5985 }
5986 }
5987 else
5988 AssertReleaseMsgFailed(("Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n",
5989 pDrv->uLUN, rc2));
5990
5991 if (fWarn)
5992 {
5993 char szMissingStreams[255];
5994 size_t len = 0;
5995 if (!fValidLineIn)
5996 {
5997 LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
5998 len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
5999 }
6000#ifdef VBOX_WITH_HDA_MIC_IN
6001 if (!fValidMicIn)
6002 {
6003 LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
6004 len += RTStrPrintf(szMissingStreams + len,
6005 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
6006 }
6007#endif
6008 if (!fValidOut)
6009 {
6010 LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
6011 len += RTStrPrintf(szMissingStreams + len,
6012 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
6013 }
6014
6015 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6016 N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
6017 "output or depending on audio input may hang. Make sure your host audio device "
6018 "is working properly. Check the logfile for error messages of the audio "
6019 "subsystem"), szMissingStreams);
6020 }
6021 }
6022 }
6023 }
6024
6025 if (RT_SUCCESS(rc))
6026 {
6027 hdaReset(pDevIns);
6028
6029 /*
6030 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
6031 * hdaReset shouldn't affects these registers.
6032 */
6033 HDA_REG(pThis, WAKEEN) = 0x0;
6034 HDA_REG(pThis, STATESTS) = 0x0;
6035
6036#ifdef DEBUG
6037 /*
6038 * Debug and string formatter types.
6039 */
6040 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
6041 PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaDbgInfoBDLE);
6042 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgInfoStream);
6043 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaDbgInfoCodecNodes);
6044 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaDbgInfoCodecSelector);
6045 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaDbgInfoMixer);
6046
6047 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
6048 AssertRC(rc);
6049 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
6050 AssertRC(rc);
6051 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
6052 AssertRC(rc);
6053 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
6054 AssertRC(rc);
6055 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
6056 AssertRC(rc);
6057#endif /* DEBUG */
6058
6059 /*
6060 * Some debug assertions.
6061 */
6062 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
6063 {
6064 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
6065 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
6066
6067 /* binary search order. */
6068 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
6069 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6070 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6071
6072 /* alignment. */
6073 AssertReleaseMsg( pReg->size == 1
6074 || (pReg->size == 2 && (pReg->offset & 1) == 0)
6075 || (pReg->size == 3 && (pReg->offset & 3) == 0)
6076 || (pReg->size == 4 && (pReg->offset & 3) == 0),
6077 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6078
6079 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
6080 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
6081 if (pReg->offset & 3)
6082 {
6083 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
6084 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6085 if (pPrevReg)
6086 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
6087 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6088 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
6089 }
6090#if 0
6091 if ((pReg->offset + pReg->size) & 3)
6092 {
6093 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6094 if (pNextReg)
6095 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
6096 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6097 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6098 }
6099#endif
6100 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
6101 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
6102 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6103 }
6104 }
6105
6106# ifndef VBOX_WITH_AUDIO_CALLBACKS
6107 if (RT_SUCCESS(rc))
6108 {
6109 /* Start the emulation timer. */
6110 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
6111 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
6112 AssertRCReturn(rc, rc);
6113
6114 if (RT_SUCCESS(rc))
6115 {
6116 pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
6117 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
6118 LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
6119
6120 hdaTimerMaybeStart(pThis);
6121 }
6122 }
6123# else
6124 if (RT_SUCCESS(rc))
6125 {
6126 PHDADRIVER pDrv;
6127 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6128 {
6129 /* Only register primary driver.
6130 * The device emulation does the output multiplexing then. */
6131 if (pDrv->Flags != PDMAUDIODRVFLAG_PRIMARY)
6132 continue;
6133
6134 PDMAUDIOCALLBACK AudioCallbacks[2];
6135
6136 HDACALLBACKCTX Ctx = { pThis, pDrv };
6137
6138 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
6139 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
6140 AudioCallbacks[0].pvCtx = &Ctx;
6141 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
6142
6143 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
6144 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
6145 AudioCallbacks[1].pvCtx = &Ctx;
6146 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
6147
6148 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
6149 if (RT_FAILURE(rc))
6150 break;
6151 }
6152 }
6153# endif
6154
6155# ifdef VBOX_WITH_STATISTICS
6156 if (RT_SUCCESS(rc))
6157 {
6158 /*
6159 * Register statistics.
6160 */
6161# ifndef VBOX_WITH_AUDIO_CALLBACKS
6162 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
6163# endif
6164 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
6165 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
6166 }
6167# endif
6168
6169 LogFlowFuncLeaveRC(rc);
6170 return rc;
6171}
6172
6173/**
6174 * The device registration structure.
6175 */
6176const PDMDEVREG g_DeviceICH6_HDA =
6177{
6178 /* u32Version */
6179 PDM_DEVREG_VERSION,
6180 /* szName */
6181 "hda",
6182 /* szRCMod */
6183 "VBoxDDRC.rc",
6184 /* szR0Mod */
6185 "VBoxDDR0.r0",
6186 /* pszDescription */
6187 "Intel HD Audio Controller",
6188 /* fFlags */
6189 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
6190 /* fClass */
6191 PDM_DEVREG_CLASS_AUDIO,
6192 /* cMaxInstances */
6193 1,
6194 /* cbInstance */
6195 sizeof(HDASTATE),
6196 /* pfnConstruct */
6197 hdaConstruct,
6198 /* pfnDestruct */
6199 hdaDestruct,
6200 /* pfnRelocate */
6201 NULL,
6202 /* pfnMemSetup */
6203 NULL,
6204 /* pfnPowerOn */
6205 NULL,
6206 /* pfnReset */
6207 hdaReset,
6208 /* pfnSuspend */
6209 NULL,
6210 /* pfnResume */
6211 NULL,
6212 /* pfnAttach */
6213 hdaAttach,
6214 /* pfnDetach */
6215 hdaDetach,
6216 /* pfnQueryInterface. */
6217 NULL,
6218 /* pfnInitComplete */
6219 NULL,
6220 /* pfnPowerOff */
6221 hdaPowerOff,
6222 /* pfnSoftReset */
6223 NULL,
6224 /* u32VersionEnd */
6225 PDM_DEVREG_VERSION
6226};
6227
6228#endif /* IN_RING3 */
6229#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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