VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 63362

Last change on this file since 63362 was 63362, checked in by vboxsync, 9 years ago

Audio: PDMPCMPROPS -> PDMAUDIOPCMPROPS.
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1/* $Id: DevIchHda.cpp 63362 2016-08-12 14:21:25Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2016 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/file.h>
36#include <iprt/list.h>
37#ifdef IN_RING3
38# include <iprt/mem.h>
39# include <iprt/semaphore.h>
40# include <iprt/string.h>
41# include <iprt/uuid.h>
42#endif
43
44#include "VBoxDD.h"
45
46#include "AudioMixBuffer.h"
47#include "AudioMixer.h"
48#include "DevIchHdaCodec.h"
49#include "DevIchHdaCommon.h"
50#include "DrvAudio.h"
51
52
53/*********************************************************************************************************************************
54* Defined Constants And Macros *
55*********************************************************************************************************************************/
56//#define HDA_AS_PCI_EXPRESS
57#define VBOX_WITH_INTEL_HDA
58
59#ifdef DEBUG_andy
60/*
61 * HDA_DEBUG_DUMP_PCM_DATA enables dumping the raw PCM data
62 * to a file on the host. Be sure to adjust HDA_DEBUG_DUMP_PCM_DATA_PATH
63 * to your needs before using this!
64 */
65# define HDA_DEBUG_DUMP_PCM_DATA
66# ifdef RT_OS_WINDOWS
67# define HDA_DEBUG_DUMP_PCM_DATA_PATH "c:\\temp\\"
68# else
69# define HDA_DEBUG_DUMP_PCM_DATA_PATH "/tmp/"
70# endif
71
72/* Enables experimental support for separate mic-in handling.
73 Do not enable this yet for regular builds, as this needs more testing first! */
74//# define VBOX_WITH_HDA_MIC_IN
75#endif
76
77#if defined(VBOX_WITH_HP_HDA)
78/* HP Pavilion dv4t-1300 */
79# define HDA_PCI_VENDOR_ID 0x103c
80# define HDA_PCI_DEVICE_ID 0x30f7
81#elif defined(VBOX_WITH_INTEL_HDA)
82/* Intel HDA controller */
83# define HDA_PCI_VENDOR_ID 0x8086
84# define HDA_PCI_DEVICE_ID 0x2668
85#elif defined(VBOX_WITH_NVIDIA_HDA)
86/* nVidia HDA controller */
87# define HDA_PCI_VENDOR_ID 0x10de
88# define HDA_PCI_DEVICE_ID 0x0ac0
89#else
90# error "Please specify your HDA device vendor/device IDs"
91#endif
92
93/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
94 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
95 * is read only except for bit 15 like the HDA spec states.
96 *
97 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
98 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
99#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
100
101/* Make sure that interleaving streams support is enabled if the 5.1 code is being used. */
102#if defined (VBOX_WITH_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT)
103# define VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
104#endif
105
106/**
107 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
108 * Bidirectional streams are currently *not* supported.
109 *
110 * Note: When changing any of those values, be prepared for some saved state
111 * fixups / trouble!
112 */
113#define HDA_MAX_SDI 4
114#define HDA_MAX_SDO 4
115#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
116AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
117
118/** Number of general registers. */
119#define HDA_NUM_GENERAL_REGS 34
120/** Number of total registers in the HDA's register map. */
121#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
122/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
123#define HDA_MAX_TAGS 16
124
125/**
126 * NB: Register values stored in memory (au32Regs[]) are indexed through
127 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
128 * register descriptors in g_aHdaRegMap[] are indexed through the
129 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
130 *
131 * The au32Regs[] layout is kept unchanged for saved state
132 * compatibility.
133 */
134
135/* Registers */
136#define HDA_REG_IND_NAME(x) HDA_REG_##x
137#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
138#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
139#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
140#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
141#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
142#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
143#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
144
145
146#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
147#define HDA_RMX_GCAP 0
148/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
149 * oss (15:12) - number of output streams supported
150 * iss (11:8) - number of input streams supported
151 * bss (7:3) - number of bidirectional streams supported
152 * bds (2:1) - number of serial data out (SDO) signals supported
153 * b64sup (0) - 64 bit addressing supported.
154 */
155#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
156 ( (((oss) & 0xF) << 12) \
157 | (((iss) & 0xF) << 8) \
158 | (((bss) & 0x1F) << 3) \
159 | (((bds) & 0x3) << 1) \
160 | ((b64sup) & 1))
161
162#define HDA_REG_VMIN 1 /* 0x02 */
163#define HDA_RMX_VMIN 1
164
165#define HDA_REG_VMAJ 2 /* 0x03 */
166#define HDA_RMX_VMAJ 2
167
168#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
169#define HDA_RMX_OUTPAY 3
170
171#define HDA_REG_INPAY 4 /* 0x06-0x07 */
172#define HDA_RMX_INPAY 4
173
174#define HDA_REG_GCTL 5 /* 0x08-0x0B */
175#define HDA_RMX_GCTL 5
176#define HDA_GCTL_RST_SHIFT 0
177#define HDA_GCTL_FSH_SHIFT 1
178#define HDA_GCTL_UR_SHIFT 8
179
180#define HDA_REG_WAKEEN 6 /* 0x0C */
181#define HDA_RMX_WAKEEN 6
182
183#define HDA_REG_STATESTS 7 /* 0x0E */
184#define HDA_RMX_STATESTS 7
185#define HDA_STATES_SCSF 0x7
186
187#define HDA_REG_GSTS 8 /* 0x10-0x11*/
188#define HDA_RMX_GSTS 8
189#define HDA_GSTS_FSH_SHIFT 1
190
191#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
192#define HDA_RMX_OUTSTRMPAY 112
193
194#define HDA_REG_INSTRMPAY 10 /* 0x1a */
195#define HDA_RMX_INSTRMPAY 113
196
197#define HDA_REG_INTCTL 11 /* 0x20 */
198#define HDA_RMX_INTCTL 9
199#define HDA_INTCTL_GIE_SHIFT 31
200#define HDA_INTCTL_CIE_SHIFT 30
201#define HDA_INTCTL_S0_SHIFT 0
202#define HDA_INTCTL_S1_SHIFT 1
203#define HDA_INTCTL_S2_SHIFT 2
204#define HDA_INTCTL_S3_SHIFT 3
205#define HDA_INTCTL_S4_SHIFT 4
206#define HDA_INTCTL_S5_SHIFT 5
207#define HDA_INTCTL_S6_SHIFT 6
208#define HDA_INTCTL_S7_SHIFT 7
209#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
210
211#define HDA_REG_INTSTS 12 /* 0x24 */
212#define HDA_RMX_INTSTS 10
213#define HDA_INTSTS_GIS_SHIFT 31
214#define HDA_INTSTS_CIS_SHIFT 30
215#define HDA_INTSTS_S0_SHIFT 0
216#define HDA_INTSTS_S1_SHIFT 1
217#define HDA_INTSTS_S2_SHIFT 2
218#define HDA_INTSTS_S3_SHIFT 3
219#define HDA_INTSTS_S4_SHIFT 4
220#define HDA_INTSTS_S5_SHIFT 5
221#define HDA_INTSTS_S6_SHIFT 6
222#define HDA_INTSTS_S7_SHIFT 7
223#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
224
225#define HDA_REG_WALCLK 13 /* 0x30 */
226#define HDA_RMX_WALCLK /* Not defined! */
227
228/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
229 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
230 * the datasheet.
231 */
232#define HDA_REG_SSYNC 14 /* 0x38 */
233#define HDA_RMX_SSYNC 12
234
235#define HDA_REG_CORBLBASE 15 /* 0x40 */
236#define HDA_RMX_CORBLBASE 13
237
238#define HDA_REG_CORBUBASE 16 /* 0x44 */
239#define HDA_RMX_CORBUBASE 14
240
241#define HDA_REG_CORBWP 17 /* 0x48 */
242#define HDA_RMX_CORBWP 15
243
244#define HDA_REG_CORBRP 18 /* 0x4A */
245#define HDA_RMX_CORBRP 16
246#define HDA_CORBRP_RST_SHIFT 15
247#define HDA_CORBRP_WP_SHIFT 0
248#define HDA_CORBRP_WP_MASK 0xFF
249
250#define HDA_REG_CORBCTL 19 /* 0x4C */
251#define HDA_RMX_CORBCTL 17
252#define HDA_CORBCTL_DMA_SHIFT 1
253#define HDA_CORBCTL_CMEIE_SHIFT 0
254
255#define HDA_REG_CORBSTS 20 /* 0x4D */
256#define HDA_RMX_CORBSTS 18
257#define HDA_CORBSTS_CMEI_SHIFT 0
258
259#define HDA_REG_CORBSIZE 21 /* 0x4E */
260#define HDA_RMX_CORBSIZE 19
261#define HDA_CORBSIZE_SZ_CAP 0xF0
262#define HDA_CORBSIZE_SZ 0x3
263/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
264
265#define HDA_REG_RIRBLBASE 22 /* 0x50 */
266#define HDA_RMX_RIRBLBASE 20
267
268#define HDA_REG_RIRBUBASE 23 /* 0x54 */
269#define HDA_RMX_RIRBUBASE 21
270
271#define HDA_REG_RIRBWP 24 /* 0x58 */
272#define HDA_RMX_RIRBWP 22
273#define HDA_RIRBWP_RST_SHIFT 15
274#define HDA_RIRBWP_WP_MASK 0xFF
275
276#define HDA_REG_RINTCNT 25 /* 0x5A */
277#define HDA_RMX_RINTCNT 23
278#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
279
280#define HDA_REG_RIRBCTL 26 /* 0x5C */
281#define HDA_RMX_RIRBCTL 24
282#define HDA_RIRBCTL_RIC_SHIFT 0
283#define HDA_RIRBCTL_DMA_SHIFT 1
284#define HDA_ROI_DMA_SHIFT 2
285
286#define HDA_REG_RIRBSTS 27 /* 0x5D */
287#define HDA_RMX_RIRBSTS 25
288#define HDA_RIRBSTS_RINTFL_SHIFT 0
289#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
290
291#define HDA_REG_RIRBSIZE 28 /* 0x5E */
292#define HDA_RMX_RIRBSIZE 26
293#define HDA_RIRBSIZE_SZ_CAP 0xF0
294#define HDA_RIRBSIZE_SZ 0x3
295
296#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
297#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
298
299
300#define HDA_REG_IC 29 /* 0x60 */
301#define HDA_RMX_IC 27
302
303#define HDA_REG_IR 30 /* 0x64 */
304#define HDA_RMX_IR 28
305
306#define HDA_REG_IRS 31 /* 0x68 */
307#define HDA_RMX_IRS 29
308#define HDA_IRS_ICB_SHIFT 0
309#define HDA_IRS_IRV_SHIFT 1
310
311#define HDA_REG_DPLBASE 32 /* 0x70 */
312#define HDA_RMX_DPLBASE 30
313#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
314
315#define HDA_REG_DPUBASE 33 /* 0x74 */
316#define HDA_RMX_DPUBASE 31
317#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
318
319#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
320
321#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
322#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
323/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
324#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
325
326#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
327
328/** @todo Condense marcos! */
329
330#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80 */
331#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
332#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
333#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
334#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
335#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
336#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
337#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
338#define HDA_RMX_SD0CTL 32
339#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
340#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
341#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
342#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
343#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
344#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
345#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
346
347#define SD(func, num) SD##num##func
348
349#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
350#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
351#define HDA_SDCTL_NUM_MASK 0xF
352#define HDA_SDCTL_NUM_SHIFT 20
353#define HDA_SDCTL_DIR_SHIFT 19
354#define HDA_SDCTL_TP_SHIFT 18
355#define HDA_SDCTL_STRIPE_MASK 0x3
356#define HDA_SDCTL_STRIPE_SHIFT 16
357#define HDA_SDCTL_DEIE_SHIFT 4
358#define HDA_SDCTL_FEIE_SHIFT 3
359#define HDA_SDCTL_ICE_SHIFT 2
360#define HDA_SDCTL_RUN_SHIFT 1
361#define HDA_SDCTL_SRST_SHIFT 0
362
363#define HDA_REG_SD0STS 35 /* 0x83 */
364#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
365#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
366#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
367#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
368#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
369#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
370#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
371#define HDA_RMX_SD0STS 33
372#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
373#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
374#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
375#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
376#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
377#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
378#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
379
380#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
381#define HDA_SDSTS_FIFORDY_SHIFT 5
382#define HDA_SDSTS_DE_SHIFT 4
383#define HDA_SDSTS_FE_SHIFT 3
384#define HDA_SDSTS_BCIS_SHIFT 2
385
386#define HDA_REG_SD0LPIB 36 /* 0x84 */
387#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
388#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
389#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
390#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
391#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
392#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
393#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
394#define HDA_RMX_SD0LPIB 34
395#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
396#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
397#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
398#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
399#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
400#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
401#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
402
403#define HDA_REG_SD0CBL 37 /* 0x88 */
404#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
405#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
406#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
407#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
408#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
409#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
410#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
411#define HDA_RMX_SD0CBL 35
412#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
413#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
414#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
415#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
416#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
417#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
418#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
419
420#define HDA_REG_SD0LVI 38 /* 0x8C */
421#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
422#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
423#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
424#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
425#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
426#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
427#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
428#define HDA_RMX_SD0LVI 36
429#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
430#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
431#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
432#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
433#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
434#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
435#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
436
437#define HDA_REG_SD0FIFOW 39 /* 0x8E */
438#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
439#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
440#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
441#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
442#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
443#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
444#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
445#define HDA_RMX_SD0FIFOW 37
446#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
447#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
448#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
449#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
450#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
451#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
452#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
453
454/*
455 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
456 */
457#define HDA_SDFIFOW_8B 0x2
458#define HDA_SDFIFOW_16B 0x3
459#define HDA_SDFIFOW_32B 0x4
460
461#define HDA_REG_SD0FIFOS 40 /* 0x90 */
462#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
463#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
464#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
465#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
466#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
467#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
468#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
469#define HDA_RMX_SD0FIFOS 38
470#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
471#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
472#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
473#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
474#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
475#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
476#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
477
478/*
479 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
480 * formula: size - 1
481 * Other values not listed are not supported.
482 */
483#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
484#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
485
486#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
487#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
488#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
489#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
490#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
491#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
492#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
493
494#define HDA_REG_SD0FMT 41 /* 0x92 */
495#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
496#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
497#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
498#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
499#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
500#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
501#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
502#define HDA_RMX_SD0FMT 39
503#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
504#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
505#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
506#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
507#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
508#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
509#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
510
511#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
512#define HDA_SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
513#define HDA_SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
514#define HDA_SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
515
516#define HDA_REG_SD0BDPL 42 /* 0x98 */
517#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
518#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
519#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
520#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
521#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
522#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
523#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
524#define HDA_RMX_SD0BDPL 40
525#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
526#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
527#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
528#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
529#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
530#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
531#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
532
533#define HDA_REG_SD0BDPU 43 /* 0x9C */
534#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
535#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
536#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
537#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
538#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
539#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
540#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
541#define HDA_RMX_SD0BDPU 41
542#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
543#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
544#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
545#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
546#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
547#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
548#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
549
550#define HDA_CODEC_CAD_SHIFT 28
551/* Encodes the (required) LUN into a codec command. */
552#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
553
554
555
556/*********************************************************************************************************************************
557* Structures and Typedefs *
558*********************************************************************************************************************************/
559
560/**
561 * Internal state of a Buffer Descriptor List Entry (BDLE),
562 * needed to keep track of the data needed for the actual device
563 * emulation.
564 */
565typedef struct HDABDLESTATE
566{
567 /** Own index within the BDL (Buffer Descriptor List). */
568 uint32_t u32BDLIndex;
569 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
570 * Used to check if we need fill up the FIFO again. */
571 uint32_t cbBelowFIFOW;
572 /** The buffer descriptor's internal DMA buffer. */
573 uint8_t au8FIFO[HDA_SDOFIFO_256B + 1];
574 /** Current offset in DMA buffer (in bytes).*/
575 uint32_t u32BufOff;
576 uint32_t Padding;
577} HDABDLESTATE, *PHDABDLESTATE;
578
579/**
580 * Buffer Descriptor List Entry (BDLE) (3.6.3).
581 *
582 * Contains only register values which do *not* change until a
583 * stream reset occurs.
584 */
585typedef struct HDABDLE
586{
587 /** Starting address of the actual buffer. Must be 128-bit aligned. */
588 uint64_t u64BufAdr;
589 /** Size of the actual buffer (in bytes). */
590 uint32_t u32BufSize;
591 /** Interrupt on completion; the controller will generate
592 * an interrupt when the last byte of the buffer has been
593 * fetched by the DMA engine. */
594 bool fIntOnCompletion;
595 /** Internal state of this BDLE.
596 * Not part of the actual BDLE registers. */
597 HDABDLESTATE State;
598} HDABDLE, *PHDABDLE;
599
600/**
601 * Structure for keeping an audio stream data mapping.
602 */
603typedef struct HDASTREAMMAPPING
604{
605 /** The stream's layout. */
606 PDMAUDIOSTREAMLAYOUT enmLayout;
607 /** Number of audio channels in this stream. */
608 uint8_t cChannels;
609 /** Array audio channels. */
610 R3PTRTYPE(PPDMAUDIOSTREAMCHANNEL) paChannels;
611 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
612} HDASTREAMMAPPING, *PHDASTREAMMAPPING;
613
614/**
615 * Internal state of a HDA stream.
616 */
617typedef struct HDASTREAMSTATE
618{
619 /** Current BDLE to use. Wraps around to 0 if
620 * maximum (cBDLE) is reached. */
621 uint16_t uCurBDLE;
622 /** Stop indicator. */
623 volatile bool fDoStop;
624 /** Flag indicating whether this stream is in an
625 * active (operative) state or not. */
626 volatile bool fActive;
627 /** Flag indicating whether this stream currently is
628 * in reset mode and therefore not acccessible by the guest. */
629 volatile bool fInReset;
630 /** Unused, padding. */
631 bool fPadding;
632 /** Mutex semaphore handle to serialize access. */
633 RTSEMMUTEX hMtx;
634 /** Event signalling that the stream's state has been changed. */
635 RTSEMEVENT hStateChangedEvent;
636 /** This stream's data mapping. */
637 HDASTREAMMAPPING Mapping;
638 /** Current BDLE (Buffer Descriptor List Entry). */
639 HDABDLE BDLE;
640} HDASTREAMSTATE, *PHDASTREAMSTATE;
641
642/**
643 * Structure defining an HDA mixer sink.
644 * Its purpose is to know which audio mixer sink is bound to
645 * which SDn (SDI/SDO) device stream.
646 *
647 * This is needed in order to handle interleaved streams
648 * (that is, multiple channels in one stream) or non-interleaved
649 * streams (each channel has a dedicated stream).
650 *
651 * This is only known to the actual device emulation level.
652 */
653typedef struct HDAMIXERSINK
654{
655 /** SDn ID this sink is assigned to. 0 if not assigned. */
656 uint8_t uSD;
657 /** Channel ID of SDn ID. Only valid if SDn ID is valid. */
658 uint8_t uChannel;
659 uint8_t Padding[3];
660 /** Pointer to the actual audio mixer sink. */
661 R3PTRTYPE(PAUDMIXSINK) pMixSink;
662} HDAMIXERSINK, *PHDAMIXERSINK;
663
664/**
665 * Structure for keeping a HDA stream state.
666 *
667 * Contains only register values which do *not* change until a
668 * stream reset occurs.
669 */
670typedef struct HDASTREAM
671{
672 /** Stream descriptor number (SDn). */
673 uint8_t u8SD;
674 uint8_t Padding0[7];
675 /** DMA base address (SDnBDPU - SDnBDPL). */
676 uint64_t u64BDLBase;
677 /** Cyclic Buffer Length (SDnCBL).
678 * Represents the size of the ring buffer. */
679 uint32_t u32CBL;
680 /** Format (SDnFMT). */
681 uint16_t u16FMT;
682 /** FIFO Size (FIFOS).
683 * Maximum number of bytes that may have been DMA'd into
684 * memory but not yet transmitted on the link.
685 *
686 * Must be a power of two. */
687 uint16_t u16FIFOS;
688 /** Last Valid Index (SDnLVI). */
689 uint16_t u16LVI;
690 uint16_t Padding1[3];
691 /** Pointer to HDA sink this stream is attached to. */
692 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
693 /** Internal state of this stream. */
694 HDASTREAMSTATE State;
695} HDASTREAM, *PHDASTREAM;
696
697/**
698 * Structure for mapping a stream tag to an HDA stream.
699 */
700typedef struct HDATAG
701{
702 /** Own stream tag. */
703 uint8_t uTag;
704 uint8_t Padding[7];
705 /** Pointer to associated stream. */
706 R3PTRTYPE(PHDASTREAM) pStrm;
707} HDATAG, *PHDATAG;
708
709/**
710 * Structure defining an HDA mixer stream.
711 * This is being used together with an audio mixer instance.
712 */
713typedef struct HDAMIXERSTREAM
714{
715 union
716 {
717 /** Desired playback destination (for an output stream). */
718 PDMAUDIOPLAYBACKDEST Dest;
719 /** Desired recording source (for an input stream). */
720 PDMAUDIORECSOURCE Source;
721 } DestSource;
722 uint8_t Padding1[4];
723 /** Associated mixer handle. */
724 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
725} HDAMIXERSTREAM, *PHDAMIXERSTREAM;
726
727/**
728 * Struct for maintaining a host backend driver.
729 * This driver must be associated to one, and only one,
730 * HDA codec. The HDA controller does the actual multiplexing
731 * of HDA codec data to various host backend drivers then.
732 *
733 * This HDA device uses a timer in order to synchronize all
734 * read/write accesses across all attached LUNs / backends.
735 */
736typedef struct HDADRIVER
737{
738 /** Node for storing this driver in our device driver list of HDASTATE. */
739 RTLISTNODER3 Node;
740 /** Pointer to HDA controller (state). */
741 R3PTRTYPE(PHDASTATE) pHDAState;
742 /** Driver flags. */
743 PDMAUDIODRVFLAGS Flags;
744 uint8_t u32Padding0[2];
745 /** LUN to which this driver has been assigned. */
746 uint8_t uLUN;
747 /** Whether this driver is in an attached state or not. */
748 bool fAttached;
749 /** Pointer to attached driver base interface. */
750 R3PTRTYPE(PPDMIBASE) pDrvBase;
751 /** Audio connector interface to the underlying host backend. */
752 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
753 /** Mixer stream for line input. */
754 HDAMIXERSTREAM LineIn;
755#ifdef VBOX_WITH_HDA_MIC_IN
756 /** Mixer stream for mic input. */
757 HDAMIXERSTREAM MicIn;
758#endif
759 /** Mixer stream for front output. */
760 HDAMIXERSTREAM Front;
761#ifdef VBOX_WITH_HDA_51_SURROUND
762 /** Mixer stream for center/LFE output. */
763 HDAMIXERSTREAM CenterLFE;
764 /** Mixer stream for rear output. */
765 HDAMIXERSTREAM Rear;
766#endif
767} HDADRIVER;
768
769/**
770 * ICH Intel HD Audio Controller state.
771 */
772typedef struct HDASTATE
773{
774 /** The PCI device structure. */
775 PCIDevice PciDev;
776 /** R3 Pointer to the device instance. */
777 PPDMDEVINSR3 pDevInsR3;
778 /** R0 Pointer to the device instance. */
779 PPDMDEVINSR0 pDevInsR0;
780 /** R0 Pointer to the device instance. */
781 PPDMDEVINSRC pDevInsRC;
782 /** Padding for alignment. */
783 uint32_t u32Padding;
784 /** The base interface for LUN\#0. */
785 PDMIBASE IBase;
786 RTGCPHYS MMIOBaseAddr;
787 /** The HDA's register set. */
788 uint32_t au32Regs[HDA_NUM_REGS];
789 /** Internal stream states. */
790 HDASTREAM aStreams[HDA_MAX_STREAMS];
791 /** Mapping table between stream tags and stream states. */
792 HDATAG aTags[HDA_MAX_TAGS];
793 /** CORB buffer base address. */
794 uint64_t u64CORBBase;
795 /** RIRB buffer base address. */
796 uint64_t u64RIRBBase;
797 /** DMA base address.
798 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
799 uint64_t u64DPBase;
800 /** DMA position buffer enable bit. */
801 bool fDMAPosition;
802 /** Padding for alignment. */
803 uint8_t u8Padding0[7];
804 /** Pointer to CORB buffer. */
805 R3PTRTYPE(uint32_t *) pu32CorbBuf;
806 /** Size in bytes of CORB buffer. */
807 uint32_t cbCorbBuf;
808 /** Padding for alignment. */
809 uint32_t u32Padding1;
810 /** Pointer to RIRB buffer. */
811 R3PTRTYPE(uint64_t *) pu64RirbBuf;
812 /** Size in bytes of RIRB buffer. */
813 uint32_t cbRirbBuf;
814 /** Indicates if HDA controller is in reset mode. */
815 bool fInReset;
816 /** Flag whether the R0 part is enabled. */
817 bool fR0Enabled;
818 /** Flag whether the RC part is enabled. */
819 bool fRCEnabled;
820 /** Number of active (running) SDn streams. */
821 uint8_t cStreamsActive;
822#ifndef VBOX_WITH_AUDIO_CALLBACKS
823 /** The timer for pumping data thru the attached LUN drivers. */
824 PTMTIMERR3 pTimer;
825 /** Flag indicating whether the timer is active or not. */
826 bool fTimerActive;
827 uint8_t u8Padding1[7];
828 /** Timer ticks per Hz. */
829 uint64_t cTimerTicks;
830 /** Timestamp of the last timer callback (hdaTimer).
831 * Used to calculate the time actually elapsed between two timer callbacks. */
832 uint64_t uTimerTS;
833#endif
834#ifdef VBOX_WITH_STATISTICS
835# ifndef VBOX_WITH_AUDIO_CALLBACKS
836 STAMPROFILE StatTimer;
837# endif
838 STAMCOUNTER StatBytesRead;
839 STAMCOUNTER StatBytesWritten;
840#endif
841 /** Pointer to HDA codec to use. */
842 R3PTRTYPE(PHDACODEC) pCodec;
843 /** List of associated LUN drivers (HDADRIVER). */
844 RTLISTANCHORR3 lstDrv;
845 /** The device' software mixer. */
846 R3PTRTYPE(PAUDIOMIXER) pMixer;
847 /** HDA sink for (front) output. */
848 HDAMIXERSINK SinkFront;
849#ifdef VBOX_WITH_HDA_51_SURROUND
850 /** HDA sink for center / LFE output. */
851 HDAMIXERSINK SinkCenterLFE;
852 /** HDA sink for rear output. */
853 HDAMIXERSINK SinkRear;
854#endif
855 /** HDA mixer sink for line input. */
856 HDAMIXERSINK SinkLineIn;
857#ifdef VBOX_WITH_HDA_MIC_IN
858 /** Audio mixer sink for microphone input. */
859 HDAMIXERSINK SinkMicIn;
860#endif
861 uint64_t u64BaseTS;
862 /** Response Interrupt Count (RINTCNT). */
863 uint8_t u8RespIntCnt;
864 /** Padding for alignment. */
865 uint8_t au8Padding2[7];
866} HDASTATE;
867/** Pointer to the ICH Intel HD Audio Controller state. */
868typedef HDASTATE *PHDASTATE;
869
870#ifdef VBOX_WITH_AUDIO_CALLBACKS
871typedef struct HDACALLBACKCTX
872{
873 PHDASTATE pThis;
874 PHDADRIVER pDriver;
875} HDACALLBACKCTX, *PHDACALLBACKCTX;
876#endif
877
878
879/*********************************************************************************************************************************
880* Internal Functions *
881*********************************************************************************************************************************/
882#ifndef VBOX_DEVICE_STRUCT_TESTCASE
883#ifdef IN_RING3
884static FNPDMDEVRESET hdaReset;
885#endif
886
887/** @name Register read/write stubs.
888 * @{
889 */
890static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
891static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
892/** @} */
893
894/** @name Global register set read/write functions.
895 * @{
896 */
897static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
898static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
899static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
900static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
901//static int hdaRegReadSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value); - unused
902//static int hdaRegWriteSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value); - unused
903//static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value); - implementation not found.
904static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
905static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
906static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
907static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
908static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
909static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
910static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
911static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
912static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
913static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
914/** @} */
915
916/** @name {IOB}SDn write functions.
917 * @{
918 */
919static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
920static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
921static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
922static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
923//static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value); - unused
924//static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value); - unused
925static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
926static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
927static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
928/** @} */
929
930/* Locking + logging. */
931#ifdef IN_RING3
932DECLINLINE(int) hdaRegWriteSDLock(PHDASTATE pThis, PHDASTREAM pStream, uint32_t iReg, uint32_t u32Value);
933DECLINLINE(void) hdaRegWriteSDUnlock(PHDASTREAM pStream);
934#endif
935
936/** @name Generic register read/write functions.
937 * @{
938 */
939static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
940static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
941static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
942static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
943static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
944static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
945static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
946static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
947/** @} */
948
949#ifdef IN_RING3
950static void hdaStreamDestroy(PHDASTREAM pStream);
951static int hdaStreamSetActive(PHDASTATE pThis, PHDASTREAM pStream, bool fActive);
952//static int hdaStreamStart(PHDASTREAM pStream); - unused
953static int hdaStreamStop(PHDASTREAM pStream);
954/*static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout); - currently unused */
955static int hdaTransfer(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToProcess, uint32_t *pcbProcessed);
956#endif
957
958#ifdef IN_RING3
959static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg);
960static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping);
961static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping);
962#endif
963
964#ifdef IN_RING3
965static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
966DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB);
967# ifdef LOG_ENABLED
968static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE);
969# endif
970#endif
971static int hdaProcessInterrupt(PHDASTATE pThis);
972
973/*
974 * Timer routines.
975 */
976#if !defined(VBOX_WITH_AUDIO_CALLBACKS) && defined(IN_RING3)
977static void hdaTimerMaybeStart(PHDASTATE pThis);
978static void hdaTimerMaybeStop(PHDASTATE pThis);
979#endif
980
981
982/*********************************************************************************************************************************
983* Global Variables *
984*********************************************************************************************************************************/
985
986/** Offset of the SD0 register map. */
987#define HDA_REG_DESC_SD0_BASE 0x80
988
989/** Turn a short global register name into an memory index and a stringized name. */
990#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
991
992/** Turns a short stream register name into an memory index and a stringized name. */
993#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
994
995/** Same as above for a register *not* stored in memory. */
996#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
997
998/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
999#define HDA_REG_MAP_STRM(offset, name) \
1000 /* offset size read mask write mask read callback write callback index + abbrev description */ \
1001 /* ------- ------- ---------- ---------- -------------- ----------------- ------------------------------ ----------- */ \
1002 /* Offset 0x80 (SD0) */ \
1003 { offset, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
1004 /* Offset 0x83 (SD0) */ \
1005 { offset + 0x3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
1006 /* Offset 0x84 (SD0) */ \
1007 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
1008 /* Offset 0x88 (SD0) */ \
1009 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
1010 /* Offset 0x8C (SD0) */ \
1011 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
1012 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
1013 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteU16, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
1014 /* Offset 0x90 (SD0) */ \
1015 { offset + 0x10, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16, hdaRegWriteU16, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
1016 /* Offset 0x92 (SD0) */ \
1017 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
1018 /* Reserved: 0x94 - 0x98. */ \
1019 /* Offset 0x98 (SD0) */ \
1020 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
1021 /* Offset 0x9C (SD0) */ \
1022 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
1023
1024/** Defines a single audio stream register set (e.g. OSD0). */
1025#define HDA_REG_MAP_DEF_STREAM(index, name) \
1026 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
1027
1028/* See 302349 p 6.2. */
1029static const struct HDAREGDESC
1030{
1031 /** Register offset in the register space. */
1032 uint32_t offset;
1033 /** Size in bytes. Registers of size > 4 are in fact tables. */
1034 uint32_t size;
1035 /** Readable bits. */
1036 uint32_t readable;
1037 /** Writable bits. */
1038 uint32_t writable;
1039 /** Read callback. */
1040 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
1041 /** Write callback. */
1042 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
1043 /** Index into the register storage array. */
1044 uint32_t mem_idx;
1045 /** Abbreviated name. */
1046 const char *abbrev;
1047 /** Descripton. */
1048 const char *desc;
1049} g_aHdaRegMap[HDA_NUM_REGS] =
1050
1051{
1052 /* offset size read mask write mask read callback write callback index + abbrev */
1053 /*------- ------- ---------- ---------- ----------------------- ---------------------- ---------------- */
1054 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
1055 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
1056 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
1057 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
1058 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
1059 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
1060 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
1061 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , HDA_REG_IDX(STATESTS) }, /* State Change Status */
1062 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
1063 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
1064 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
1065 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
1066 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
1067 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
1068 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
1069 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
1070 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
1071 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
1072 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
1073 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
1074 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
1075 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
1076 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
1077 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
1078 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
1079 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
1080 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
1081 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
1082 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
1083 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
1084 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
1085 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
1086 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
1087 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
1088 /* 4 Serial Data In (SDI). */
1089 HDA_REG_MAP_DEF_STREAM(0, SD0),
1090 HDA_REG_MAP_DEF_STREAM(1, SD1),
1091 HDA_REG_MAP_DEF_STREAM(2, SD2),
1092 HDA_REG_MAP_DEF_STREAM(3, SD3),
1093 /* 4 Serial Data Out (SDO). */
1094 HDA_REG_MAP_DEF_STREAM(4, SD4),
1095 HDA_REG_MAP_DEF_STREAM(5, SD5),
1096 HDA_REG_MAP_DEF_STREAM(6, SD6),
1097 HDA_REG_MAP_DEF_STREAM(7, SD7)
1098};
1099
1100/**
1101 * HDA register aliases (HDA spec 3.3.45).
1102 * @remarks Sorted by offReg.
1103 */
1104static const struct
1105{
1106 /** The alias register offset. */
1107 uint32_t offReg;
1108 /** The register index. */
1109 int idxAlias;
1110} g_aHdaRegAliases[] =
1111{
1112 { 0x2084, HDA_REG_SD0LPIB },
1113 { 0x20a4, HDA_REG_SD1LPIB },
1114 { 0x20c4, HDA_REG_SD2LPIB },
1115 { 0x20e4, HDA_REG_SD3LPIB },
1116 { 0x2104, HDA_REG_SD4LPIB },
1117 { 0x2124, HDA_REG_SD5LPIB },
1118 { 0x2144, HDA_REG_SD6LPIB },
1119 { 0x2164, HDA_REG_SD7LPIB },
1120};
1121
1122#ifdef IN_RING3
1123/** HDABDLE field descriptors for the v6+ saved state. */
1124static SSMFIELD const g_aSSMBDLEFields6[] =
1125{
1126 SSMFIELD_ENTRY(HDABDLE, u64BufAdr),
1127 SSMFIELD_ENTRY(HDABDLE, u32BufSize),
1128 SSMFIELD_ENTRY(HDABDLE, fIntOnCompletion),
1129 SSMFIELD_ENTRY_TERM()
1130};
1131
1132/** HDABDLESTATE field descriptors for the v6+ saved state. */
1133static SSMFIELD const g_aSSMBDLEStateFields6[] =
1134{
1135 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
1136 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
1137 SSMFIELD_ENTRY(HDABDLESTATE, au8FIFO),
1138 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
1139 SSMFIELD_ENTRY_TERM()
1140};
1141
1142/** HDASTREAMSTATE field descriptors for the v6+ saved state. */
1143static SSMFIELD const g_aSSMStreamStateFields6[] =
1144{
1145 SSMFIELD_ENTRY_OLD(cBDLE, 2),
1146 SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
1147 SSMFIELD_ENTRY(HDASTREAMSTATE, fDoStop),
1148 SSMFIELD_ENTRY(HDASTREAMSTATE, fActive),
1149 SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
1150 SSMFIELD_ENTRY_TERM()
1151};
1152#endif
1153
1154/**
1155 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1156 */
1157static uint32_t const g_afMasks[5] =
1158{
1159 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1160};
1161
1162#ifdef IN_RING3
1163DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB)
1164{
1165 AssertPtrReturn(pThis, 0);
1166 AssertPtrReturn(pStream, 0);
1167
1168 Assert(u32LPIB <= pStream->u32CBL);
1169
1170 LogFlowFunc(("[SD%RU8]: LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1171 pStream->u8SD, u32LPIB, pThis->fDMAPosition));
1172
1173 /* Update LPIB in any case. */
1174 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) = u32LPIB;
1175
1176 /* Do we need to tell the current DMA position? */
1177 if (pThis->fDMAPosition)
1178 {
1179 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1180 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStream->u8SD * 2 * sizeof(uint32_t)),
1181 (void *)&u32LPIB, sizeof(uint32_t));
1182 AssertRC(rc2);
1183 }
1184
1185 return u32LPIB;
1186}
1187#endif
1188
1189/**
1190 * Retrieves the number of bytes of a FIFOS register.
1191 *
1192 * @return Number of bytes of a given FIFOS register.
1193 */
1194DECLINLINE(uint16_t) hdaSDFIFOSToBytes(uint32_t u32RegFIFOS)
1195{
1196 uint16_t cb;
1197 switch (u32RegFIFOS)
1198 {
1199 /* Input */
1200 case HDA_SDIFIFO_120B: cb = 120; break;
1201 case HDA_SDIFIFO_160B: cb = 160; break;
1202
1203 /* Output */
1204 case HDA_SDOFIFO_16B: cb = 16; break;
1205 case HDA_SDOFIFO_32B: cb = 32; break;
1206 case HDA_SDOFIFO_64B: cb = 64; break;
1207 case HDA_SDOFIFO_128B: cb = 128; break;
1208 case HDA_SDOFIFO_192B: cb = 192; break;
1209 case HDA_SDOFIFO_256B: cb = 256; break;
1210 default:
1211 {
1212 cb = 0; /* Can happen on stream reset. */
1213 break;
1214 }
1215 }
1216
1217 return cb;
1218}
1219
1220/**
1221 * Retrieves the number of bytes of a FIFOW register.
1222 *
1223 * @return Number of bytes of a given FIFOW register.
1224 */
1225DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1226{
1227 uint32_t cb;
1228 switch (u32RegFIFOW)
1229 {
1230 case HDA_SDFIFOW_8B: cb = 8; break;
1231 case HDA_SDFIFOW_16B: cb = 16; break;
1232 case HDA_SDFIFOW_32B: cb = 32; break;
1233 default: cb = 0; break;
1234 }
1235
1236#ifdef RT_STRICT
1237 Assert(RT_IS_POWER_OF_TWO(cb));
1238#endif
1239 return cb;
1240}
1241
1242#ifdef IN_RING3
1243/**
1244 * Fetches the next BDLE to use for a stream.
1245 *
1246 * @return IPRT status code.
1247 */
1248DECLINLINE(int) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
1249{
1250 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1251 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1252
1253 NOREF(pThis);
1254
1255 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1256
1257 LogFlowFuncEnter();
1258
1259#ifdef DEBUG
1260 uint32_t uOldBDLE = pStream->State.uCurBDLE;
1261#endif
1262
1263 PHDABDLE pBDLE = &pStream->State.BDLE;
1264
1265 /*
1266 * Switch to the next BDLE entry and do a wrap around
1267 * if we reached the end of the Buffer Descriptor List (BDL).
1268 */
1269 pStream->State.uCurBDLE++;
1270 if (pStream->State.uCurBDLE == pStream->u16LVI + 1)
1271 {
1272 pStream->State.uCurBDLE = 0;
1273
1274 hdaStreamUpdateLPIB(pThis, pStream, 0);
1275 }
1276
1277 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1278
1279 /* Fetch the next BDLE entry. */
1280 int rc = hdaBDLEFetch(pThis, pBDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
1281
1282#ifdef DEBUG
1283 LogFlowFunc(("[SD%RU8]: uOldBDLE=%RU16, uCurBDLE=%RU16, LVI=%RU32, rc=%Rrc, %R[bdle]\n",
1284 pStream->u8SD, uOldBDLE, pStream->State.uCurBDLE, pStream->u16LVI, rc, pBDLE));
1285#endif
1286
1287 return rc;
1288}
1289#endif /* IN_RING3 */
1290
1291/**
1292 * Returns the audio direction of a specified stream descriptor.
1293 *
1294 * The register layout specifies that input streams (SDI) come first,
1295 * followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
1296 * is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
1297 *
1298 * Note: SDnFMT register does not provide that information, so we have to judge
1299 * for ourselves.
1300 *
1301 * @return Audio direction.
1302 */
1303DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
1304{
1305 AssertReturn(uSD <= HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
1306
1307 if (uSD < HDA_MAX_SDI)
1308 return PDMAUDIODIR_IN;
1309
1310 return PDMAUDIODIR_OUT;
1311}
1312
1313/**
1314 * Returns the HDA stream of specified stream descriptor number.
1315 *
1316 * @return Pointer to HDA stream, or NULL if none found.
1317 */
1318DECLINLINE(PHDASTREAM) hdaStreamFromSD(PHDASTATE pThis, uint8_t uSD)
1319{
1320 AssertPtrReturn(pThis, NULL);
1321 AssertReturn(uSD <= HDA_MAX_STREAMS, NULL);
1322
1323 if (uSD >= HDA_MAX_STREAMS)
1324 return NULL;
1325
1326 return &pThis->aStreams[uSD];
1327}
1328
1329/**
1330 * Returns the HDA stream of specified HDA sink.
1331 *
1332 * @return Pointer to HDA stream, or NULL if none found.
1333 */
1334DECLINLINE(PHDASTREAM) hdaGetStreamFromSink(PHDASTATE pThis, PHDAMIXERSINK pSink)
1335{
1336 AssertPtrReturn(pThis, NULL);
1337 AssertPtrReturn(pSink, NULL);
1338
1339 /** @todo Do something with the channel mapping here? */
1340 return hdaStreamFromSD(pThis, pSink->uSD);
1341}
1342
1343/**
1344 * Retrieves the minimum number of bytes accumulated/free in the
1345 * FIFO before the controller will start a fetch/eviction of data.
1346 *
1347 * Uses SDFIFOW (FIFO Watermark Register).
1348 *
1349 * @return Number of bytes accumulated/free in the FIFO.
1350 */
1351DECLINLINE(uint8_t) hdaStreamGetFIFOW(PHDASTATE pThis, PHDASTREAM pStream)
1352{
1353 AssertPtrReturn(pThis, 0);
1354 AssertPtrReturn(pStream, 0);
1355
1356#ifdef VBOX_HDA_WITH_FIFO
1357 return hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, pStream->u8SD));
1358#else
1359 return 0;
1360#endif
1361}
1362
1363static int hdaProcessInterrupt(PHDASTATE pThis)
1364{
1365#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1366 ( INTCTL_SX((pThis), num) \
1367 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1368
1369 int iLevel = 0;
1370
1371 /** @todo Optimize IRQ handling. */
1372
1373 if (/* Controller Interrupt Enable (CIE). */
1374 HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1375 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1376 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1377 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1378 {
1379 iLevel = 1;
1380 }
1381
1382 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1383 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 1)
1384 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 2)
1385 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 3)
1386 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4)
1387 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 5)
1388 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 6)
1389 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 7))
1390 {
1391 iLevel = 1;
1392 }
1393
1394 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1395 {
1396 Log3Func(("Level=%d\n", iLevel));
1397 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , iLevel);
1398 }
1399
1400#undef IS_INTERRUPT_OCCURED_AND_ENABLED
1401
1402 return VINF_SUCCESS;
1403}
1404
1405/**
1406 * Looks up a register at the exact offset given by @a offReg.
1407 *
1408 * @returns Register index on success, -1 if not found.
1409 * @param offReg The register offset.
1410 */
1411static int hdaRegLookup(uint32_t offReg)
1412{
1413 /*
1414 * Aliases.
1415 */
1416 if (offReg >= g_aHdaRegAliases[0].offReg)
1417 {
1418 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1419 if (offReg == g_aHdaRegAliases[i].offReg)
1420 return g_aHdaRegAliases[i].idxAlias;
1421 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1422 return -1;
1423 }
1424
1425 /*
1426 * Binary search the
1427 */
1428 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1429 int idxLow = 0;
1430 for (;;)
1431 {
1432 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1433 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1434 {
1435 if (idxLow == idxMiddle)
1436 break;
1437 idxEnd = idxMiddle;
1438 }
1439 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1440 {
1441 idxLow = idxMiddle + 1;
1442 if (idxLow >= idxEnd)
1443 break;
1444 }
1445 else
1446 return idxMiddle;
1447 }
1448
1449#ifdef RT_STRICT
1450 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1451 Assert(g_aHdaRegMap[i].offset != offReg);
1452#endif
1453 return -1;
1454}
1455
1456/**
1457 * Looks up a register covering the offset given by @a offReg.
1458 *
1459 * @returns Register index on success, -1 if not found.
1460 * @param offReg The register offset.
1461 */
1462static int hdaRegLookupWithin(uint32_t offReg)
1463{
1464 /*
1465 * Aliases.
1466 */
1467 if (offReg >= g_aHdaRegAliases[0].offReg)
1468 {
1469 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1470 {
1471 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1472 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1473 return g_aHdaRegAliases[i].idxAlias;
1474 }
1475 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1476 return -1;
1477 }
1478
1479 /*
1480 * Binary search the register map.
1481 */
1482 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1483 int idxLow = 0;
1484 for (;;)
1485 {
1486 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1487 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1488 {
1489 if (idxLow == idxMiddle)
1490 break;
1491 idxEnd = idxMiddle;
1492 }
1493 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1494 {
1495 idxLow = idxMiddle + 1;
1496 if (idxLow >= idxEnd)
1497 break;
1498 }
1499 else
1500 return idxMiddle;
1501 }
1502
1503#ifdef RT_STRICT
1504 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1505 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1506#endif
1507 return -1;
1508}
1509
1510#ifdef IN_RING3
1511static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1512{
1513 int rc = VINF_SUCCESS;
1514 if (fLocal)
1515 {
1516 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1517 Assert(pThis->u64CORBBase);
1518 AssertPtr(pThis->pu32CorbBuf);
1519 Assert(pThis->cbCorbBuf);
1520
1521 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1522 if (RT_FAILURE(rc))
1523 AssertRCReturn(rc, rc);
1524#ifdef DEBUG_CMD_BUFFER
1525 uint8_t i = 0;
1526 do
1527 {
1528 LogFunc(("CORB%02x: ", i));
1529 uint8_t j = 0;
1530 do
1531 {
1532 const char *pszPrefix;
1533 if ((i + j) == HDA_REG(pThis, CORBRP));
1534 pszPrefix = "[R]";
1535 else if ((i + j) == HDA_REG(pThis, CORBWP));
1536 pszPrefix = "[W]";
1537 else
1538 pszPrefix = " "; /* three spaces */
1539 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1540 j++;
1541 } while (j < 8);
1542 LogFunc(("\n"));
1543 i += 8;
1544 } while(i != 0);
1545#endif
1546 }
1547 else
1548 {
1549 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1550 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1551 if (RT_FAILURE(rc))
1552 AssertRCReturn(rc, rc);
1553#ifdef DEBUG_CMD_BUFFER
1554 uint8_t i = 0;
1555 do {
1556 LogFunc(("RIRB%02x: ", i));
1557 uint8_t j = 0;
1558 do {
1559 const char *prefix;
1560 if ((i + j) == HDA_REG(pThis, RIRBWP))
1561 prefix = "[W]";
1562 else
1563 prefix = " ";
1564 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1565 } while (++j < 8);
1566 LogFunc(("\n"));
1567 i += 8;
1568 } while (i != 0);
1569#endif
1570 }
1571 return rc;
1572}
1573
1574static int hdaCORBCmdProcess(PHDASTATE pThis)
1575{
1576 int rc = hdaCmdSync(pThis, true);
1577 if (RT_FAILURE(rc))
1578 AssertRCReturn(rc, rc);
1579
1580 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1581 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1582 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1583
1584 Assert((corbWp != corbRp));
1585 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1586
1587 while (corbRp != corbWp)
1588 {
1589 uint64_t uResp;
1590 uint32_t uCmd = pThis->pu32CorbBuf[++corbRp];
1591
1592 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
1593 if (RT_FAILURE(rc2))
1594 LogFunc(("Codec lookup failed with rc=%Rrc\n", rc2));
1595
1596 (rirbWp)++;
1597
1598 if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
1599 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1600 {
1601 LogFunc(("Unexpected unsolicited response\n"));
1602 HDA_REG(pThis, CORBRP) = corbRp;
1603 return rc;
1604 }
1605
1606 pThis->pu64RirbBuf[rirbWp] = uResp;
1607
1608 pThis->u8RespIntCnt++;
1609 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1610 break;
1611 }
1612
1613 HDA_REG(pThis, CORBRP) = corbRp;
1614 HDA_REG(pThis, RIRBWP) = rirbWp;
1615
1616 rc = hdaCmdSync(pThis, false);
1617
1618 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1619
1620 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1621 {
1622 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1623
1624 pThis->u8RespIntCnt = 0;
1625 rc = hdaProcessInterrupt(pThis);
1626 }
1627
1628 if (RT_FAILURE(rc))
1629 AssertRCReturn(rc, rc);
1630 return rc;
1631}
1632
1633static int hdaStreamCreate(PHDASTREAM pStream, uint8_t uSD)
1634{
1635 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1636 AssertReturn(uSD <= HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
1637
1638 int rc = RTSemEventCreate(&pStream->State.hStateChangedEvent);
1639 if (RT_SUCCESS(rc))
1640 rc = RTSemMutexCreate(&pStream->State.hMtx);
1641
1642 if (RT_SUCCESS(rc))
1643 {
1644 pStream->u8SD = uSD;
1645 pStream->pMixSink = NULL;
1646
1647 pStream->State.fActive = false;
1648 pStream->State.fInReset = false;
1649 pStream->State.fDoStop = false;
1650 }
1651
1652 LogFlowFunc(("uSD=%RU8\n", uSD));
1653 return rc;
1654}
1655
1656static void hdaStreamDestroy(PHDASTREAM pStream)
1657{
1658 AssertPtrReturnVoid(pStream);
1659
1660 LogFlowFunc(("[SD%RU8]: Destroying ...\n", pStream->u8SD));
1661
1662 int rc2 = hdaStreamStop(pStream);
1663 AssertRC(rc2);
1664
1665 hdaStreamMapDestroy(&pStream->State.Mapping);
1666
1667 if (pStream->State.hMtx != NIL_RTSEMMUTEX)
1668 {
1669 rc2 = RTSemMutexDestroy(pStream->State.hMtx);
1670 AssertRC(rc2);
1671 pStream->State.hMtx = NIL_RTSEMMUTEX;
1672 }
1673
1674 if (pStream->State.hStateChangedEvent != NIL_RTSEMEVENT)
1675 {
1676 rc2 = RTSemEventDestroy(pStream->State.hStateChangedEvent);
1677 AssertRC(rc2);
1678 pStream->State.hStateChangedEvent = NIL_RTSEMEVENT;
1679 }
1680
1681 LogFlowFuncLeave();
1682}
1683
1684static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStream, uint8_t u8SD)
1685{
1686 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1687 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1688
1689 pStream->u8SD = u8SD;
1690 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1691 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1692 pStream->u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1693 pStream->u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1694 pStream->u16FIFOS = hdaSDFIFOSToBytes(HDA_STREAM_REG(pThis, FIFOS, pStream->u8SD));
1695
1696 RT_ZERO(pStream->State.BDLE);
1697 pStream->State.uCurBDLE = 0;
1698
1699 hdaStreamMapReset(&pStream->State.Mapping);
1700
1701 LogFlowFunc(("[SD%RU8]: DMA @ 0x%x (%RU32 bytes), LVI=%RU16, FIFOS=%RU16\n",
1702 pStream->u8SD, pStream->u64BDLBase, pStream->u32CBL, pStream->u16LVI, pStream->u16FIFOS));
1703
1704#ifdef DEBUG
1705 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1706 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1707 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1708 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1709
1710 LogFlowFunc(("\t-> DMA @ 0x%x, LVI=%RU16, CBL=%RU32\n", u64BaseDMA, u16LVI, u32CBL));
1711
1712 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
1713#endif
1714
1715 return VINF_SUCCESS;
1716}
1717
1718static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStream)
1719{
1720 AssertPtrReturnVoid(pThis);
1721 AssertPtrReturnVoid(pStream);
1722
1723 const uint8_t uSD = pStream->u8SD;
1724
1725#ifdef VBOX_STRICT
1726 AssertReleaseMsg(!RT_BOOL(HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
1727 ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
1728#endif
1729
1730 LogFunc(("[SD%RU8]: Reset\n", uSD));
1731
1732 /*
1733 * Set reset state.
1734 */
1735 Assert(ASMAtomicReadBool(&pStream->State.fInReset) == false); /* No nested calls. */
1736 ASMAtomicXchgBool(&pStream->State.fInReset, true);
1737
1738 /*
1739 * First, reset the internal stream state.
1740 */
1741 RT_ZERO(pStream->State.BDLE);
1742 pStream->State.uCurBDLE = 0;
1743
1744 /*
1745 * Second, initialize the registers.
1746 */
1747 HDA_STREAM_REG(pThis, STS, uSD) = HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1748 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1749 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1750 HDA_STREAM_REG(pThis, CTL, uSD) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1751 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39. */
1752 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
1753 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1754 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
1755 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
1756 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
1757 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
1758 HDA_STREAM_REG(pThis, FMT, uSD) = HDA_SDFMT_MAKE(HDA_SDFMT_TYPE_PCM, HDA_SDFMT_BASE_44KHZ,
1759 HDA_SDFMT_MULT_1X, HDA_SDFMT_DIV_1X, HDA_SDFMT_16_BIT,
1760 HDA_SDFMT_CHAN_STEREO);
1761 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
1762 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
1763
1764 int rc2 = hdaStreamInit(pThis, pStream, uSD);
1765 AssertRC(rc2);
1766
1767 /* Report that we're done resetting this stream. */
1768 HDA_STREAM_REG(pThis, CTL, uSD) = 0;
1769
1770 /* Exit reset state. */
1771 ASMAtomicXchgBool(&pStream->State.fInReset, false);
1772}
1773
1774#if 0 /* unused */
1775static bool hdaStreamIsActive(PHDASTATE pThis, PHDASTREAM pStream)
1776{
1777 AssertPtrReturn(pThis, false);
1778 AssertPtrReturn(pStream, false);
1779
1780 bool fActive = pStream->State.fActive;
1781
1782 LogFlowFunc(("SD=%RU8, fActive=%RTbool\n", pStream->u8SD, fActive));
1783 return fActive;
1784}
1785#endif
1786
1787static int hdaStreamSetActive(PHDASTATE pThis, PHDASTREAM pStream, bool fActive)
1788{
1789 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1790 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1791
1792 LogFlowFunc(("[SD%RU8]: fActive=%RTbool, pMixSink=%p\n", pStream->u8SD, fActive, pStream->pMixSink));
1793
1794 if (pStream->State.fActive == fActive) /* No change required? */
1795 {
1796 LogFlowFunc(("[SD%RU8]: No change\n", pStream->u8SD));
1797 return VINF_SUCCESS;
1798 }
1799
1800 int rc = VINF_SUCCESS;
1801
1802 if (pStream->pMixSink) /* Stream attached to a sink? */
1803 {
1804 AUDMIXSINKCMD enmCmd = fActive
1805 ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE;
1806
1807 /* First, enable or disable the stream and the stream's sink, if any. */
1808 if (pStream->pMixSink->pMixSink)
1809 rc = AudioMixerSinkCtl(pStream->pMixSink->pMixSink, enmCmd);
1810 }
1811 else
1812 rc = VINF_SUCCESS;
1813
1814 if (RT_FAILURE(rc))
1815 {
1816 LogFlowFunc(("Failed with rc=%Rrc\n", rc));
1817 return rc;
1818 }
1819
1820 pStream->State.fActive = fActive;
1821
1822 /* Second, see if we need to start or stop the timer. */
1823 if (!fActive)
1824 {
1825 if (pThis->cStreamsActive) /* Disable can be called mupltiple times. */
1826 pThis->cStreamsActive--;
1827
1828#ifndef VBOX_WITH_AUDIO_CALLBACKS
1829 hdaTimerMaybeStop(pThis);
1830#endif
1831 }
1832 else
1833 {
1834 pThis->cStreamsActive++;
1835#ifndef VBOX_WITH_AUDIO_CALLBACKS
1836 hdaTimerMaybeStart(pThis);
1837#endif
1838 }
1839
1840 LogFlowFunc(("u8Strm=%RU8, fActive=%RTbool, cStreamsActive=%RU8\n", pStream->u8SD, fActive, pThis->cStreamsActive));
1841 return VINF_SUCCESS;
1842}
1843
1844static void hdaStreamAssignToSink(PHDASTREAM pStream, PHDAMIXERSINK pMixSink)
1845{
1846 AssertPtrReturnVoid(pStream);
1847
1848 int rc2 = RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
1849 if (RT_SUCCESS(rc2))
1850 {
1851 pStream->pMixSink = pMixSink;
1852
1853 rc2 = RTSemMutexRelease(pStream->State.hMtx);
1854 AssertRC(rc2);
1855 }
1856}
1857
1858#if 0 /** @todo hdaStreamStart is unused */
1859static int hdaStreamStart(PHDASTREAM pStream)
1860{
1861 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1862
1863 ASMAtomicXchgBool(&pStream->State.fDoStop, false);
1864 ASMAtomicXchgBool(&pStream->State.fActive, true);
1865
1866 LogFlowFuncLeave();
1867 return VINF_SUCCESS;
1868}
1869#endif /* unused */
1870
1871static int hdaStreamStop(PHDASTREAM pStream)
1872{
1873 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1874
1875 /* Already in stopped state? */
1876 bool fActive = ASMAtomicReadBool(&pStream->State.fActive);
1877 if (!fActive)
1878 return VINF_SUCCESS;
1879
1880#if 0 /** @todo Does not work (yet), as EMT deadlocks then. */
1881 /*
1882 * Wait for the stream to stop.
1883 */
1884 ASMAtomicXchgBool(&pStream->State.fDoStop, true);
1885
1886 int rc = hdaStreamWaitForStateChange(pStream, 60 * 1000 /* ms timeout */);
1887 fActive = ASMAtomicReadBool(&pStream->State.fActive);
1888 if ( /* Waiting failed? */
1889 RT_FAILURE(rc)
1890 /* Stream is still active? */
1891 || fActive)
1892 {
1893 AssertRC(rc);
1894 LogRel(("HDA: Warning: Unable to stop stream %RU8 (state: %s), rc=%Rrc\n",
1895 pStream->u8Strm, fActive ? "active" : "stopped", rc));
1896 }
1897#else
1898 int rc = VINF_SUCCESS;
1899#endif
1900
1901 LogFlowFuncLeaveRC(rc);
1902 return rc;
1903}
1904
1905#if defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_HDA_51_SURROUND)
1906static int hdaStreamChannelExtract(PPDMAUDIOSTREAMCHANNEL pChan, const void *pvBuf, size_t cbBuf)
1907{
1908 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1909 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
1910 AssertReturn(cbBuf, VERR_INVALID_PARAMETER);
1911
1912 AssertRelease(pChan->cbOff <= cbBuf);
1913
1914 const uint8_t *pu8Buf = (const uint8_t *)pvBuf;
1915
1916 size_t cbSrc = cbBuf - pChan->cbOff;
1917 const uint8_t *pvSrc = &pu8Buf[pChan->cbOff];
1918
1919 size_t cbDst;
1920 uint8_t *pvDst;
1921 RTCircBufAcquireWriteBlock(pChan->Data.pCircBuf, cbBuf, (void **)&pvDst, &cbDst);
1922
1923 cbSrc = RT_MIN(cbSrc, cbDst);
1924
1925 while (cbSrc)
1926 {
1927 AssertBreak(cbDst >= cbSrc);
1928
1929 /* Enough data for at least one next frame? */
1930 if (cbSrc < pChan->cbFrame)
1931 break;
1932
1933 memcpy(pvDst, pvSrc, pChan->cbFrame);
1934
1935 /* Advance to next channel frame in stream. */
1936 pvSrc += pChan->cbStep;
1937 Assert(cbSrc >= pChan->cbStep);
1938 cbSrc -= pChan->cbStep;
1939
1940 /* Advance destination by one frame. */
1941 pvDst += pChan->cbFrame;
1942 Assert(cbDst >= pChan->cbFrame);
1943 cbDst -= pChan->cbFrame;
1944
1945 /* Adjust offset. */
1946 pChan->cbOff += pChan->cbFrame;
1947 }
1948
1949 RTCircBufReleaseWriteBlock(pChan->Data.pCircBuf, cbDst);
1950
1951 return VINF_SUCCESS;
1952}
1953#endif /* defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_HDA_51_SURROUND) */
1954
1955#if 0 /** @todo hdaStreamChannelAdvance is unused */
1956static int hdaStreamChannelAdvance(PPDMAUDIOSTREAMCHANNEL pChan, size_t cbAdv)
1957{
1958 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1959
1960 if (!cbAdv)
1961 return VINF_SUCCESS;
1962
1963 return VINF_SUCCESS;
1964}
1965#endif
1966
1967static int hdaStreamChannelDataInit(PPDMAUDIOSTREAMCHANNELDATA pChanData, uint32_t fFlags)
1968{
1969 int rc = RTCircBufCreate(&pChanData->pCircBuf, 256); /** @todo Make this configurable? */
1970 if (RT_SUCCESS(rc))
1971 {
1972 pChanData->fFlags = fFlags;
1973 }
1974
1975 return rc;
1976}
1977
1978/**
1979 * Frees a stream channel data block again.
1980 *
1981 * @param pChanData Pointer to channel data to free.
1982 */
1983static void hdaStreamChannelDataDestroy(PPDMAUDIOSTREAMCHANNELDATA pChanData)
1984{
1985 if (!pChanData)
1986 return;
1987
1988 if (pChanData->pCircBuf)
1989 {
1990 RTCircBufDestroy(pChanData->pCircBuf);
1991 pChanData->pCircBuf = NULL;
1992 }
1993
1994 pChanData->fFlags = PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE;
1995}
1996
1997#if defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_HDA_51_SURROUND)
1998
1999static int hdaStreamChannelAcquireData(PPDMAUDIOSTREAMCHANNELDATA pChanData, void *pvData, size_t *pcbData)
2000{
2001 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
2002 AssertPtrReturn(pvData, VERR_INVALID_POINTER);
2003 AssertPtrReturn(pcbData, VERR_INVALID_POINTER);
2004
2005 RTCircBufAcquireReadBlock(pChanData->pCircBuf, 256 /** @todo Make this configurarble? */, &pvData, &pChanData->cbAcq);
2006
2007 *pcbData = pChanData->cbAcq;
2008 return VINF_SUCCESS;
2009}
2010
2011static int hdaStreamChannelReleaseData(PPDMAUDIOSTREAMCHANNELDATA pChanData)
2012{
2013 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
2014 RTCircBufReleaseReadBlock(pChanData->pCircBuf, pChanData->cbAcq);
2015
2016 return VINF_SUCCESS;
2017}
2018
2019#endif /* defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_HDA_51_SURROUND) */
2020
2021# if 0 /* currently unused */
2022static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout)
2023{
2024 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
2025
2026 LogFlowFunc(("[SD%RU8]: msTimeout=%RU32\n", pStream->u8SD, msTimeout));
2027 return RTSemEventWait(pStream->State.hStateChangedEvent, msTimeout);
2028}
2029# endif /* currently unused */
2030
2031#endif /* IN_RING3 */
2032
2033/* Register access handlers. */
2034
2035static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2036{
2037 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg);
2038 *pu32Value = 0;
2039 return VINF_SUCCESS;
2040}
2041
2042static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2043{
2044 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2045 return VINF_SUCCESS;
2046}
2047
2048/* U8 */
2049static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2050{
2051 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
2052 return hdaRegReadU32(pThis, iReg, pu32Value);
2053}
2054
2055static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2056{
2057 Assert((u32Value & 0xffffff00) == 0);
2058 return hdaRegWriteU32(pThis, iReg, u32Value);
2059}
2060
2061/* U16 */
2062static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2063{
2064 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
2065 return hdaRegReadU32(pThis, iReg, pu32Value);
2066}
2067
2068static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2069{
2070 Assert((u32Value & 0xffff0000) == 0);
2071 return hdaRegWriteU32(pThis, iReg, u32Value);
2072}
2073
2074/* U24 */
2075static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2076{
2077 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
2078 return hdaRegReadU32(pThis, iReg, pu32Value);
2079}
2080
2081static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2082{
2083 Assert((u32Value & 0xff000000) == 0);
2084 return hdaRegWriteU32(pThis, iReg, u32Value);
2085}
2086
2087/* U32 */
2088static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2089{
2090 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2091
2092 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
2093 return VINF_SUCCESS;
2094}
2095
2096static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2097{
2098 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2099
2100 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
2101 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
2102 return VINF_SUCCESS;
2103}
2104
2105static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2106{
2107 RT_NOREF_PV(iReg);
2108
2109 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
2110 {
2111 /* Set the CRST bit to indicate that we're leaving reset mode. */
2112 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2113
2114 if (pThis->fInReset)
2115 {
2116 LogFunc(("Guest leaving HDA reset\n"));
2117 pThis->fInReset = false;
2118 }
2119 }
2120 else
2121 {
2122#ifdef IN_RING3
2123 /* Enter reset state. */
2124 LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
2125 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
2126 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
2127
2128 /* Clear the CRST bit to indicate that we're in reset state. */
2129 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2130 pThis->fInReset = true;
2131
2132 hdaReset(pThis->CTX_SUFF(pDevIns));
2133#else
2134 return VINF_IOM_R3_MMIO_WRITE;
2135#endif
2136 }
2137
2138 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
2139 {
2140 /* Flush: GSTS:1 set, see 6.2.6. */
2141 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
2142 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
2143 }
2144 return VINF_SUCCESS;
2145}
2146
2147static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2148{
2149 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2150
2151 uint32_t v = pThis->au32Regs[iRegMem];
2152 uint32_t nv = u32Value & HDA_STATES_SCSF;
2153 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
2154 return VINF_SUCCESS;
2155}
2156
2157static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2158{
2159 RT_NOREF_PV(iReg);
2160
2161 uint32_t v = 0;
2162 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
2163 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
2164 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
2165 || HDA_REG(pThis, STATESTS))
2166 {
2167 v |= RT_BIT(30); /* Touch CIS. */
2168 }
2169
2170#define HDA_MARK_STREAM(x) \
2171 if (/* Descriptor Error */ \
2172 (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
2173 /* FIFO Error */ \
2174 || (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
2175 /* Buffer Completion Interrupt Status */ \
2176 || (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))) \
2177 { \
2178 Log3Func(("[SD%RU8] BCIS: Marked\n", x)); \
2179 v |= RT_BIT(x); \
2180 }
2181
2182 HDA_MARK_STREAM(0);
2183 HDA_MARK_STREAM(1);
2184 HDA_MARK_STREAM(2);
2185 HDA_MARK_STREAM(3);
2186 HDA_MARK_STREAM(4);
2187 HDA_MARK_STREAM(5);
2188 HDA_MARK_STREAM(6);
2189 HDA_MARK_STREAM(7);
2190
2191#undef HDA_MARK_STREAM
2192
2193 /* "OR" bit of all interrupt status bits. */
2194 v |= v ? RT_BIT(31) : 0;
2195
2196 *pu32Value = v;
2197 return VINF_SUCCESS;
2198}
2199
2200static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2201{
2202 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
2203 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
2204#ifdef LOG_ENABLED
2205 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
2206 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
2207#endif
2208
2209 *pu32Value = u32LPIB;
2210 return VINF_SUCCESS;
2211}
2212
2213static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2214{
2215 RT_NOREF_PV(iReg);
2216
2217 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2218 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
2219 - pThis->u64BaseTS, 24, 1000);
2220 LogFlowFunc(("%RU32\n", *pu32Value));
2221 return VINF_SUCCESS;
2222}
2223
2224#if 0 /** @todo hdaRegReadSSYNC & hdaRegWriteSSYNC are unused */
2225
2226static int hdaRegReadSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2227{
2228 RT_NOREF_PV(iReg);
2229
2230 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2231 *pu32Value = HDA_REG(pThis, SSYNC);
2232 LogFlowFunc(("%RU32\n", *pu32Value));
2233 return VINF_SUCCESS;
2234}
2235
2236static int hdaRegWriteSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2237{
2238 LogFlowFunc(("%RU32\n", u32Value));
2239 return hdaRegWriteU32(pThis, iReg, u32Value);
2240}
2241
2242#endif /* unused */
2243
2244static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2245{
2246 RT_NOREF_PV(iReg);
2247
2248 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
2249 {
2250 HDA_REG(pThis, CORBRP) = 0;
2251 }
2252#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
2253 else
2254 return hdaRegWriteU8(pThis, iReg, u32Value);
2255#endif
2256 return VINF_SUCCESS;
2257}
2258
2259static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2260{
2261#ifdef IN_RING3
2262 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
2263 AssertRC(rc);
2264 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2265 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
2266 {
2267 return hdaCORBCmdProcess(pThis);
2268 }
2269 return rc;
2270#else
2271 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2272 return VINF_IOM_R3_MMIO_WRITE;
2273#endif
2274}
2275
2276static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2277{
2278 RT_NOREF_PV(iReg);
2279
2280 uint32_t v = HDA_REG(pThis, CORBSTS);
2281 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
2282 return VINF_SUCCESS;
2283}
2284
2285static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2286{
2287#ifdef IN_RING3
2288 int rc;
2289 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2290 if (RT_FAILURE(rc))
2291 AssertRCReturn(rc, rc);
2292 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
2293 return VINF_SUCCESS;
2294 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2295 return VINF_SUCCESS;
2296 rc = hdaCORBCmdProcess(pThis);
2297 return rc;
2298#else /* !IN_RING3 */
2299 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2300 return VINF_IOM_R3_MMIO_WRITE;
2301#endif /* IN_RING3 */
2302}
2303
2304static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2305{
2306#ifdef IN_RING3
2307 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2308 return VINF_SUCCESS;
2309
2310 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
2311 if (!pStream)
2312 {
2313 LogFunc(("[SD%RU8]: Warning: Changing SDCBL on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2314 return hdaRegWriteU32(pThis, iReg, u32Value);
2315 }
2316
2317 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2318 AssertRC(rc2);
2319
2320 pStream->u32CBL = u32Value;
2321
2322 /* Reset BDLE state. */
2323 RT_ZERO(pStream->State.BDLE);
2324 pStream->State.uCurBDLE = 0;
2325
2326 rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2327 AssertRC(rc2);
2328
2329 LogFlowFunc(("[SD%RU8]: CBL=%RU32\n", pStream->u8SD, u32Value));
2330 hdaRegWriteSDUnlock(pStream);
2331
2332 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2333#else /* !IN_RING3 */
2334 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2335 return VINF_IOM_R3_MMIO_WRITE;
2336#endif /* IN_RING3 */
2337}
2338
2339static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2340{
2341#if defined(IN_RING3) || defined(LOG_ENABLED) || defined(VBOX_STRICT)
2342 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2343 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2344#endif
2345 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2346 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2347
2348 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2349 return VINF_SUCCESS;
2350
2351 /* Get the stream descriptor. */
2352 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
2353
2354 /*
2355 * Extract the stream tag the guest wants to use for this specific
2356 * stream descriptor (SDn). This only can happen if the stream is in a non-running
2357 * state, so we're doing the lookup and assignment here.
2358 *
2359 * So depending on the guest OS, SD3 can use stream tag 4, for example.
2360 */
2361 uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
2362 if (uTag > HDA_MAX_TAGS)
2363 {
2364 LogFunc(("[SD%RU8]: Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
2365 return hdaRegWriteU24(pThis, iReg, u32Value);
2366 }
2367
2368
2369
2370/** @todo r=bird: Andy, the spotty IN_RING3 in the rest of this function makes
2371 * little sense. If you need to request a lock in ring-3, why don't
2372 * you need it in ring-0 / RC? Or, reversely, why can you do the
2373 * fInReset handling without locking and resolving pStream in R0+RC
2374 * but not in ring-3?
2375 *
2376 * What makes the least sense, is that you do fInReset +
2377 * hdaProcessInterrupt in R0/RC and then unconditionally forces a trip to
2378 * ring-3 and does the same again.
2379 *
2380 * Please, do make up your mind what you want to do here ASAP!
2381 */
2382
2383
2384#ifdef IN_RING3
2385 PHDATAG pTag = &pThis->aTags[uTag];
2386 AssertPtr(pTag);
2387
2388 LogFunc(("[SD%RU8]: Using stream tag=%RU8\n", uSD, uTag));
2389
2390 /* Assign new values. */
2391 pTag->uTag = uTag;
2392 pTag->pStrm = hdaStreamFromSD(pThis, uSD);
2393
2394 PHDASTREAM pStream = pTag->pStrm;
2395 AssertPtr(pStream);
2396
2397 /* Note: Do not use hdaRegWriteSDLock() here, as SDnCTL might change the RUN bit. */
2398 int rc2 = RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
2399 AssertRC(rc2);
2400#endif /* IN_RING3 */
2401
2402 LogFunc(("[SD%RU8]: fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
2403 uSD, fRun, fInRun, fReset, fInReset, u32Value));
2404
2405 if (fInReset)
2406 {
2407 Assert(!fReset);
2408 Assert(!fInRun && !fRun);
2409
2410 /* Report that we're done resetting this stream by clearing SRST. */
2411 HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
2412
2413 LogFunc(("[SD%RU8]: Guest initiated exit of stream reset\n", uSD));
2414 }
2415 else if (fReset)
2416 {
2417#ifdef IN_RING3
2418 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
2419 Assert(!fInRun && !fRun);
2420
2421 LogFunc(("[SD%RU8]: Guest initiated enter to stream reset\n", pStream->u8SD));
2422 hdaStreamReset(pThis, pStream);
2423#endif
2424 }
2425 else
2426 {
2427#ifdef IN_RING3
2428 /*
2429 * We enter here to change DMA states only.
2430 */
2431 if (fInRun != fRun)
2432 {
2433 Assert(!fReset && !fInReset);
2434 LogFunc(("[SD%RU8]: fRun=%RTbool\n", pStream->u8SD, fRun));
2435
2436 hdaStreamSetActive(pThis, pStream, fRun);
2437
2438 if (fRun)
2439 {
2440 /* (Re-)Fetch the current BDLE entry. */
2441 rc2 = hdaBDLEFetch(pThis, &pStream->State.BDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
2442 AssertRC(rc2);
2443 }
2444 }
2445
2446 if (!fInRun && !fRun)
2447 hdaStreamInit(pThis, pStream, pStream->u8SD);
2448#endif /* IN_RING3 */
2449 }
2450
2451 /* Make sure to handle interrupts here as well. */
2452 hdaProcessInterrupt(pThis);
2453
2454#ifdef IN_RING3
2455 rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
2456 AssertRC(rc2);
2457
2458 hdaRegWriteSDUnlock(pStream);
2459 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2460#else
2461 return VINF_IOM_R3_MMIO_WRITE;
2462#endif
2463}
2464
2465static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2466{
2467 uint32_t v = HDA_REG_IND(pThis, iReg);
2468 /* Clear (zero) FIFOE and DESE bits when writing 1 to it. */
2469 v &= ~(u32Value & v);
2470
2471 HDA_REG_IND(pThis, iReg) = v;
2472
2473 hdaProcessInterrupt(pThis);
2474 return VINF_SUCCESS;
2475}
2476
2477static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2478{
2479#ifdef IN_RING3
2480 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2481 return VINF_SUCCESS;
2482
2483 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, LVI, iReg));
2484 if (!pStream)
2485 {
2486 LogFunc(("[SD%RU8]: Warning: Changing SDLVI on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2487 return hdaRegWriteU16(pThis, iReg, u32Value);
2488 }
2489
2490 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2491 AssertRC(rc2);
2492
2493 /** @todo Validate LVI. */
2494 pStream->u16LVI = u32Value;
2495
2496 /* Reset BDLE state. */
2497 RT_ZERO(pStream->State.BDLE);
2498 pStream->State.uCurBDLE = 0;
2499
2500 rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
2501 AssertRC(rc2);
2502
2503 LogFlowFunc(("[SD%RU8]: LVI=%RU32\n", pStream->u8SD, u32Value));
2504 hdaRegWriteSDUnlock(pStream);
2505
2506 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2507
2508#else /* !IN_RING3 */
2509 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2510 return VINF_IOM_R3_MMIO_WRITE;
2511#endif /* IN_RING3 */
2512}
2513
2514#if 0 /** @todo hdaRegWriteSDFIFOW & hdaRegWriteSDFIFOS are unused */
2515static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2516{
2517 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
2518 /** @todo Only allow updating FIFOS if RUN bit is 0? */
2519 uint32_t u32FIFOW = 0;
2520
2521 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
2522 {
2523 LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to stream #%RU8, ignoring\n", uSD));
2524 return VINF_SUCCESS;
2525 }
2526
2527 switch (u32Value)
2528 {
2529 case HDA_SDFIFOW_8B:
2530 case HDA_SDFIFOW_16B:
2531 case HDA_SDFIFOW_32B:
2532 u32FIFOW = u32Value;
2533 break;
2534 default:
2535 LogRel(("HDA: Warning: Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
2536 u32Value, uSD));
2537 u32FIFOW = HDA_SDFIFOW_32B;
2538 break;
2539 }
2540
2541 if (u32FIFOW)
2542 {
2543 LogFunc(("[SD%RU8]: Updating FIFOW to %RU32 bytes\n", uSD, hdaSDFIFOSToBytes(u32FIFOW)));
2544 /** @todo Update internal stream state with new FIFOS. */
2545
2546 return hdaRegWriteU16(pThis, iReg, u32FIFOW);
2547 }
2548
2549 return VINF_SUCCESS; /* Never reached. */
2550}
2551
2552/**
2553 * @note This method could be called for changing value on Output Streams
2554 * only (ICH6 datasheet 18.2.39).
2555 */
2556static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2557{
2558 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
2559 /** @todo Only allow updating FIFOS if RUN bit is 0? */
2560 uint32_t u32FIFOS = 0;
2561
2562 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
2563 {
2564 LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to stream #%RU8, ignoring\n", uSD));
2565 return VINF_SUCCESS;
2566 }
2567
2568 switch(u32Value)
2569 {
2570 case HDA_SDOFIFO_16B:
2571 case HDA_SDOFIFO_32B:
2572 case HDA_SDOFIFO_64B:
2573 case HDA_SDOFIFO_128B:
2574 case HDA_SDOFIFO_192B:
2575 u32FIFOS = u32Value;
2576 break;
2577
2578 case HDA_SDOFIFO_256B: /** @todo r=andy Investigate this. */
2579 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
2580 /* Fall through is intentional. */
2581 default:
2582 LogRel(("HDA: Warning: Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
2583 u32Value, uSD));
2584 u32FIFOS = HDA_SDOFIFO_192B;
2585 break;
2586 }
2587
2588 if (u32FIFOS)
2589 {
2590 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n",
2591 HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg), hdaSDFIFOSToBytes(u32FIFOS)));
2592 /** @todo Update internal stream state with new FIFOS. */
2593
2594 return hdaRegWriteU16(pThis, iReg, u32FIFOS);
2595 }
2596
2597 return VINF_SUCCESS;
2598}
2599
2600#endif /* unused */
2601
2602#ifdef IN_RING3
2603static int hdaSDFMTToStrmCfg(uint32_t u32SDFMT, PPDMAUDIOSTREAMCFG pStrmCfg)
2604{
2605 AssertPtrReturn(pStrmCfg, VERR_INVALID_POINTER);
2606
2607# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2608
2609 int rc = VINF_SUCCESS;
2610
2611 uint32_t u32Hz = EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BASE_RATE_MASK, HDA_SDFMT_BASE_RATE_SHIFT)
2612 ? 44100 : 48000;
2613 uint32_t u32HzMult = 1;
2614 uint32_t u32HzDiv = 1;
2615
2616 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2617 {
2618 case 0: u32HzMult = 1; break;
2619 case 1: u32HzMult = 2; break;
2620 case 2: u32HzMult = 3; break;
2621 case 3: u32HzMult = 4; break;
2622 default:
2623 LogFunc(("Unsupported multiplier %x\n",
2624 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2625 rc = VERR_NOT_SUPPORTED;
2626 break;
2627 }
2628 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2629 {
2630 case 0: u32HzDiv = 1; break;
2631 case 1: u32HzDiv = 2; break;
2632 case 2: u32HzDiv = 3; break;
2633 case 3: u32HzDiv = 4; break;
2634 case 4: u32HzDiv = 5; break;
2635 case 5: u32HzDiv = 6; break;
2636 case 6: u32HzDiv = 7; break;
2637 case 7: u32HzDiv = 8; break;
2638 default:
2639 LogFunc(("Unsupported divisor %x\n",
2640 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2641 rc = VERR_NOT_SUPPORTED;
2642 break;
2643 }
2644
2645 PDMAUDIOFMT enmFmt;
2646 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2647 {
2648 case 0:
2649 enmFmt = PDMAUDIOFMT_S8;
2650 break;
2651 case 1:
2652 enmFmt = PDMAUDIOFMT_S16;
2653 break;
2654 case 4:
2655 enmFmt = PDMAUDIOFMT_S32;
2656 break;
2657 default:
2658 AssertMsgFailed(("Unsupported bits per sample %x\n",
2659 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2660 enmFmt = PDMAUDIOFMT_INVALID;
2661 rc = VERR_NOT_SUPPORTED;
2662 break;
2663 }
2664
2665 if (RT_SUCCESS(rc))
2666 {
2667 pStrmCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2668 pStrmCfg->cChannels = (u32SDFMT & 0xf) + 1;
2669 pStrmCfg->enmFormat = enmFmt;
2670 pStrmCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2671 }
2672
2673# undef EXTRACT_VALUE
2674 return rc;
2675}
2676
2677static int hdaAddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2678{
2679 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2680 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2681
2682 AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
2683
2684 LogFlowFunc(("Stream=%s\n", pCfg->szName));
2685
2686 int rc = VINF_SUCCESS;
2687
2688 bool fUseFront = true; /* Always use front out by default. */
2689#ifdef VBOX_WITH_HDA_51_SURROUND
2690 bool fUseRear;
2691 bool fUseCenter;
2692 bool fUseLFE;
2693
2694 fUseRear = fUseCenter = fUseLFE = false;
2695
2696 /*
2697 * Use commonly used setups for speaker configurations.
2698 */
2699
2700 /** @todo Make the following configurable through mixer API and/or CFGM? */
2701 switch (pCfg->cChannels)
2702 {
2703 case 3: /* 2.1: Front (Stereo) + LFE. */
2704 {
2705 fUseLFE = true;
2706 break;
2707 }
2708
2709 case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
2710 {
2711 fUseRear = true;
2712 break;
2713 }
2714
2715 case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
2716 {
2717 fUseRear = true;
2718 fUseLFE = true;
2719 break;
2720 }
2721
2722 case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
2723 {
2724 fUseRear = true;
2725 fUseCenter = true;
2726 fUseLFE = true;
2727 break;
2728 }
2729
2730 default: /* Unknown; fall back to 2 front channels (stereo). */
2731 {
2732 rc = VERR_NOT_SUPPORTED;
2733 break;
2734 }
2735 }
2736#else /* !VBOX_WITH_HDA_51_SURROUND */
2737 /* Only support mono or stereo channels. */
2738 if ( pCfg->cChannels != 1 /* Mono */
2739 && pCfg->cChannels != 2 /* Stereo */)
2740 {
2741 rc = VERR_NOT_SUPPORTED;
2742 }
2743#endif
2744
2745 if (rc == VERR_NOT_SUPPORTED)
2746 {
2747 LogRel(("HDA: Unsupported channel count (%RU8), falling back to stereo channels\n", pCfg->cChannels));
2748 pCfg->cChannels = 2;
2749
2750 rc = VINF_SUCCESS;
2751 }
2752
2753 do
2754 {
2755 if (RT_FAILURE(rc))
2756 break;
2757
2758 if (fUseFront)
2759 {
2760 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
2761 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
2762 pCfg->cChannels = 2;
2763
2764 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT);
2765 if (RT_SUCCESS(rc))
2766 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
2767 }
2768
2769#ifdef VBOX_WITH_HDA_51_SURROUND
2770 if ( RT_SUCCESS(rc)
2771 && (fUseCenter || fUseLFE))
2772 {
2773 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
2774 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
2775 pCfg->cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
2776
2777 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE);
2778 if (RT_SUCCESS(rc))
2779 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
2780 }
2781
2782 if ( RT_SUCCESS(rc)
2783 && fUseRear)
2784 {
2785 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
2786 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
2787 pCfg->cChannels = 2;
2788
2789 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR);
2790 if (RT_SUCCESS(rc))
2791 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
2792 }
2793#endif /* VBOX_WITH_HDA_51_SURROUND */
2794
2795 } while (0);
2796
2797 LogFlowFuncLeaveRC(rc);
2798 return rc;
2799}
2800
2801static int hdaAddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2802{
2803 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2804 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2805
2806 AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
2807
2808 LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
2809
2810 int rc;
2811
2812 switch (pCfg->DestSource.Source)
2813 {
2814 case PDMAUDIORECSOURCE_LINE:
2815 {
2816 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN);
2817 if (RT_SUCCESS(rc))
2818 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
2819 break;
2820 }
2821#ifdef VBOX_WITH_HDA_MIC_IN
2822 case PDMAUDIORECSOURCE_MIC:
2823 {
2824 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN);
2825 if (RT_SUCCESS(rc))
2826 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
2827 break;
2828 }
2829#endif
2830 default:
2831 rc = VERR_NOT_SUPPORTED;
2832 break;
2833 }
2834
2835 LogFlowFuncLeaveRC(rc);
2836 return rc;
2837}
2838#endif /* IN_RING3 */
2839
2840static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2841{
2842#ifdef IN_RING3
2843 PDMAUDIOSTREAMCFG strmCfg;
2844 RT_ZERO(strmCfg);
2845
2846 int rc = hdaSDFMTToStrmCfg(u32Value, &strmCfg);
2847 if (RT_FAILURE(rc))
2848 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2849
2850 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg));
2851 if (!pStream)
2852 {
2853 LogFunc(("[SD%RU8]: Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2854 HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2855 return hdaRegWriteU16(pThis, iReg, u32Value);
2856 }
2857
2858 int rcSem = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2859 AssertRC(rcSem);
2860
2861 LogFunc(("[SD%RU8]: Hz=%RU32, Channels=%RU8, enmFmt=%RU32\n",
2862 pStream->u8SD, strmCfg.uHz, strmCfg.cChannels, strmCfg.enmFormat));
2863
2864 /* Set audio direction. */
2865 strmCfg.enmDir = hdaGetDirFromSD(pStream->u8SD);
2866 switch (strmCfg.enmDir)
2867 {
2868 case PDMAUDIODIR_IN:
2869# ifdef VBOX_WITH_HDA_MIC_IN
2870# error "Implement me!"
2871# else
2872 strmCfg.DestSource.Source = PDMAUDIORECSOURCE_LINE;
2873 RTStrCopy(strmCfg.szName, sizeof(strmCfg.szName), "Line In");
2874# endif
2875 break;
2876
2877 case PDMAUDIODIR_OUT:
2878 /* Destination(s) will be set in hdaAddStreamOut(),
2879 * based on the channels / stream layout. */
2880 break;
2881
2882 default:
2883 rc = VERR_NOT_SUPPORTED;
2884 break;
2885 }
2886
2887 /*
2888 * Initialize the stream mapping in any case, regardless if
2889 * we support surround audio or not. This is needed to handle
2890 * the supported channels within a single audio stream, e.g. mono/stereo.
2891 *
2892 * In other words, the stream mapping *always* knowns the real
2893 * number of channels in a single audio stream.
2894 */
2895 if (RT_SUCCESS(rc))
2896 {
2897 rc = hdaStreamMapInit(&pStream->State.Mapping, &strmCfg);
2898 AssertRC(rc);
2899 }
2900
2901 if (RT_SUCCESS(rc))
2902 {
2903 PHDADRIVER pDrv;
2904 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2905 {
2906 int rc2;
2907 switch (strmCfg.enmDir)
2908 {
2909 case PDMAUDIODIR_OUT:
2910 rc2 = hdaAddStreamOut(pThis, &strmCfg);
2911 break;
2912
2913 case PDMAUDIODIR_IN:
2914 rc2 = hdaAddStreamIn(pThis, &strmCfg);
2915 break;
2916
2917 default:
2918 rc2 = VERR_NOT_SUPPORTED;
2919 AssertFailed();
2920 break;
2921 }
2922
2923 if ( RT_FAILURE(rc2)
2924 && (pDrv->Flags & PDMAUDIODRVFLAGS_PRIMARY)) /* We only care about primary drivers here, the rest may fail. */
2925 {
2926 if (RT_SUCCESS(rc))
2927 rc = rc2;
2928 /* Keep going. */
2929 }
2930 }
2931
2932 /* If (re-)opening the stream by the codec above failed, don't write the new
2933 * format to the register so that the guest is aware it didn't work. */
2934 if (RT_SUCCESS(rc))
2935 {
2936 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2937 AssertRC(rc);
2938 }
2939 else
2940 LogFunc(("[SD%RU8]: (Re-)Opening stream failed with rc=%Rrc\n", pStream->u8SD, rc));
2941 }
2942
2943 if (RT_SUCCESS(rcSem))
2944 hdaRegWriteSDUnlock(pStream);
2945
2946 return VINF_SUCCESS; /* Never return failure. */
2947#else /* !IN_RING3 */
2948 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2949 return VINF_IOM_R3_MMIO_WRITE;
2950#endif
2951}
2952
2953/* Note: Will be called for both, BDPL and BDPU, registers. */
2954DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t u8Strm)
2955{
2956#ifdef IN_RING3
2957 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2958 return VINF_SUCCESS;
2959
2960 PHDASTREAM pStream = hdaStreamFromSD(pThis, u8Strm);
2961 if (!pStream)
2962 {
2963 LogFunc(("[SD%RU8]: Warning: Changing SDBPL/SDBPU on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2964 return hdaRegWriteU32(pThis, iReg, u32Value);
2965 }
2966
2967 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2968 AssertRC(rc2);
2969
2970 rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2971 AssertRC(rc2);
2972
2973 /* Update BDL base. */
2974 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2975 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2976 /* Reset BDLE state. */
2977 RT_ZERO(pStream->State.BDLE);
2978 pStream->State.uCurBDLE = 0;
2979
2980 LogFlowFunc(("[SD%RU8]: BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2981 hdaRegWriteSDUnlock(pStream);
2982
2983 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2984#else /* !IN_RING3 */
2985 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(u8Strm);
2986 return VINF_IOM_R3_MMIO_WRITE;
2987#endif /* IN_RING3 */
2988}
2989
2990static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2991{
2992 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2993}
2994
2995static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2996{
2997 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2998}
2999
3000#ifdef IN_RING3
3001/**
3002 * XXX
3003 *
3004 * @return VBox status code. ALL THE CALLERS IGNORES THIS. DUH.
3005 *
3006 * @param pThis Pointer to HDA state.
3007 * @param iReg Register to write (logging only).
3008 * @param u32Value Value to write (logging only).
3009 */
3010DECLINLINE(int) hdaRegWriteSDLock(PHDASTATE pThis, PHDASTREAM pStream, uint32_t iReg, uint32_t u32Value)
3011{
3012 RT_NOREF(pThis, iReg, u32Value);
3013 AssertPtr(pThis); /* don't bother returning errors */
3014 AssertPtr(pStream);
3015
3016# ifdef VBOX_STRICT
3017 /* Check if the SD's RUN bit is set. */
3018 uint32_t u32SDCTL = HDA_STREAM_REG(pThis, CTL, pStream->u8SD);
3019 bool fIsRunning = RT_BOOL(u32SDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3020 if (fIsRunning)
3021 {
3022 LogFunc(("[SD%RU8]: Warning: Cannot write to register 0x%x (0x%x) when RUN bit is set (%R[sdctl])\n",
3023 pStream->u8SD, iReg, u32Value, u32SDCTL));
3024# ifdef DEBUG_andy
3025 AssertFailed();
3026# endif
3027 return VERR_ACCESS_DENIED;
3028 }
3029# endif
3030
3031 /** @todo r=bird: Why on EARTH are we using mutexes? USE CRITICAL SECTIONS!! */
3032 return RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
3033}
3034
3035DECLINLINE(void) hdaRegWriteSDUnlock(PHDASTREAM pStream)
3036{
3037 AssertPtrReturnVoid(pStream);
3038
3039 int rc2 = RTSemMutexRelease(pStream->State.hMtx);
3040 AssertRC(rc2);
3041}
3042#endif /* IN_RING3 */
3043
3044static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
3045{
3046 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
3047 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
3048 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
3049 {
3050 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
3051 }
3052
3053 return hdaRegReadU32(pThis, iReg, pu32Value);
3054}
3055
3056static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3057{
3058 RT_NOREF_PV(iReg);
3059
3060 /*
3061 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
3062 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
3063 */
3064 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
3065 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
3066 {
3067#ifdef IN_RING3
3068 uint32_t uCmd = HDA_REG(pThis, IC);
3069
3070 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
3071 {
3072 /*
3073 * 3.4.3: Defines behavior of immediate Command status register.
3074 */
3075 LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
3076 return VINF_SUCCESS;
3077 }
3078
3079 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
3080
3081 uint64_t uResp;
3082 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
3083 HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
3084 if (RT_FAILURE(rc2))
3085 LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
3086
3087 HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
3088 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
3089 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
3090 return VINF_SUCCESS;
3091#else /* !IN_RING3 */
3092 return VINF_IOM_R3_MMIO_WRITE;
3093#endif /* !IN_RING3 */
3094 }
3095
3096 /*
3097 * Once the guest read the response, it should clean the IRV bit of the IRS register.
3098 */
3099 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
3100 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
3101 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
3102 return VINF_SUCCESS;
3103}
3104
3105static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3106{
3107 RT_NOREF_PV(iReg);
3108
3109 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
3110 HDA_REG(pThis, RIRBWP) = 0;
3111
3112 /* The remaining bits are O, see 6.2.22. */
3113 return VINF_SUCCESS;
3114}
3115
3116static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3117{
3118 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
3119 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
3120 if (RT_FAILURE(rc))
3121 AssertRCReturn(rc, rc);
3122
3123 switch(iReg)
3124 {
3125 case HDA_REG_CORBLBASE:
3126 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
3127 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
3128 break;
3129 case HDA_REG_CORBUBASE:
3130 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
3131 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3132 break;
3133 case HDA_REG_RIRBLBASE:
3134 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
3135 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
3136 break;
3137 case HDA_REG_RIRBUBASE:
3138 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
3139 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3140 break;
3141 case HDA_REG_DPLBASE:
3142 {
3143 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
3144 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
3145
3146 /* Also make sure to handle the DMA position enable bit. */
3147 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
3148 LogRel2(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
3149 break;
3150 }
3151 case HDA_REG_DPUBASE:
3152 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
3153 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3154 break;
3155 default:
3156 AssertMsgFailed(("Invalid index\n"));
3157 break;
3158 }
3159
3160 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
3161 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
3162 return rc;
3163}
3164
3165static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3166{
3167 RT_NOREF_PV(iReg);
3168
3169 uint8_t v = HDA_REG(pThis, RIRBSTS);
3170 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
3171
3172 return hdaProcessInterrupt(pThis);
3173}
3174
3175#ifdef IN_RING3
3176#ifdef LOG_ENABLED
3177static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE)
3178{
3179 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
3180 if (!u64BDLBase)
3181 return;
3182
3183 uint32_t cbBDLE = 0;
3184 for (uint16_t i = 0; i < cBDLE; i++)
3185 {
3186 uint8_t bdle[16]; /** @todo Use a define. */
3187 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BDLBase + i * 16, bdle, 16); /** @todo Use a define. */
3188
3189 uint64_t addr = *(uint64_t *)bdle;
3190 uint32_t len = *(uint32_t *)&bdle[8];
3191 uint32_t ioc = *(uint32_t *)&bdle[12];
3192
3193 LogFlowFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
3194 i, addr, len, RT_BOOL(ioc & 0x1)));
3195
3196 cbBDLE += len;
3197 }
3198
3199 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
3200
3201 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
3202 return;
3203
3204 LogFlowFunc(("DMA counters:\n"));
3205
3206 for (int i = 0; i < cBDLE; i++)
3207 {
3208 uint32_t uDMACnt;
3209 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
3210 &uDMACnt, sizeof(uDMACnt));
3211
3212 LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
3213 }
3214}
3215#endif
3216
3217/**
3218 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
3219 *
3220 * @param pThis Pointer to HDA state.
3221 * @param pBDLE Where to store the fetched result.
3222 * @param u64BaseDMA Address base of DMA engine to use.
3223 * @param u16Entry BDLE entry to fetch.
3224 */
3225static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
3226{
3227 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3228 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
3229 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
3230
3231 if (!u64BaseDMA)
3232 {
3233 LogRel2(("HDA: Unable to fetch BDLE #%RU16 - no base DMA address set (yet)\n", u16Entry));
3234 return VERR_NOT_FOUND;
3235 }
3236 /** @todo Compare u16Entry with LVI. */
3237
3238 uint8_t uBundleEntry[16]; /** @todo Define a BDLE length. */
3239 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * 16, /** @todo Define a BDLE length. */
3240 uBundleEntry, RT_ELEMENTS(uBundleEntry));
3241 if (RT_FAILURE(rc))
3242 return rc;
3243
3244 RT_BZERO(pBDLE, sizeof(HDABDLE));
3245
3246 pBDLE->State.u32BDLIndex = u16Entry;
3247 pBDLE->u64BufAdr = *(uint64_t *) uBundleEntry;
3248 pBDLE->u32BufSize = *(uint32_t *)&uBundleEntry[8];
3249 if (pBDLE->u32BufSize < sizeof(uint16_t)) /* Must be at least one word. */
3250 return VERR_INVALID_STATE;
3251
3252 pBDLE->fIntOnCompletion = (*(uint32_t *)&uBundleEntry[12]) & RT_BIT(0);
3253
3254 return VINF_SUCCESS;
3255}
3256
3257/**
3258 * Returns the number of outstanding stream data bytes which need to be processed
3259 * by the DMA engine assigned to this stream.
3260 *
3261 * @return Number of bytes for the DMA engine to process.
3262 */
3263DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax)
3264{
3265 AssertPtrReturn(pThis, 0);
3266 AssertPtrReturn(pStream, 0);
3267
3268 if (!cbMax)
3269 return 0;
3270
3271 PHDABDLE pBDLE = &pStream->State.BDLE;
3272
3273 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3274 Assert(u32LPIB <= pStream->u32CBL);
3275
3276 uint32_t cbFree = pStream->u32CBL - u32LPIB;
3277 if (cbFree)
3278 {
3279 /* Limit to the available free space of the current BDLE. */
3280 cbFree = RT_MIN(cbFree, pBDLE->u32BufSize - pBDLE->State.u32BufOff);
3281
3282 /* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
3283 cbFree = RT_MIN(cbFree, uint32_t(pStream->u16FIFOS));
3284
3285 /* Make sure we only transfer as many bytes as requested. */
3286 cbFree = RT_MIN(cbFree, cbMax);
3287
3288 if (pBDLE->State.cbBelowFIFOW)
3289 {
3290 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
3291 * No need to read data from DMA then. */
3292 if (cbFree > pBDLE->State.cbBelowFIFOW)
3293 {
3294 /* Subtract the amount of bytes that still would fit in the stream's FIFO
3295 * and therefore do not need to be processed by DMA. */
3296 cbFree -= pBDLE->State.cbBelowFIFOW;
3297 }
3298 }
3299 }
3300
3301 LogFlowFunc(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, FIFOS=%RU16, cbFree=%RU32, %R[bdle]\n", pStream->u8SD,
3302 pStream->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), pStream->u16FIFOS, cbFree, pBDLE));
3303 return cbFree;
3304}
3305
3306DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
3307{
3308 AssertPtrReturnVoid(pBDLE);
3309
3310 if (!cbData || !cbProcessed)
3311 return;
3312
3313 /* Fewer than cbBelowFIFOW bytes were copied.
3314 * Probably we need to move the buffer, but it is rather hard to imagine a situation
3315 * where it might happen. */
3316 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
3317 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
3318 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
3319
3320#if 0
3321 if ( pBDLE->State.cbBelowFIFOW
3322 && pBDLE->State.cbBelowFIFOW <= cbWritten)
3323 {
3324 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
3325 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->u32BufSize));
3326 }
3327#endif
3328
3329 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
3330 Assert(pBDLE->State.cbBelowFIFOW == 0);
3331
3332 /* We always increment the position of DMA buffer counter because we're always reading
3333 * into an intermediate buffer. */
3334 pBDLE->State.u32BufOff += cbData;
3335 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3336
3337 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
3338}
3339
3340#ifdef IN_RING3
3341/**
3342 * Initializes a stream mapping structure according to the given stream configuration.
3343 *
3344 * @return IPRT status code.
3345 * @param pMapping Pointer to mapping to initialize.
3346 * @param pCfg Pointer to stream configuration to use.
3347 */
3348static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg)
3349{
3350 AssertPtrReturn(pMapping, VERR_INVALID_POINTER);
3351 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3352
3353 AssertReturn(pCfg->cChannels, VERR_INVALID_PARAMETER);
3354
3355 hdaStreamMapReset(pMapping);
3356
3357 pMapping->paChannels = (PPDMAUDIOSTREAMCHANNEL)RTMemAlloc(sizeof(PDMAUDIOSTREAMCHANNEL) * pCfg->cChannels);
3358 if (!pMapping->paChannels)
3359 return VERR_NO_MEMORY;
3360
3361 PDMAUDIOPCMPROPS Props;
3362 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &Props);
3363 if (RT_FAILURE(rc))
3364 return rc;
3365
3366 Assert(RT_IS_POWER_OF_TWO(Props.cBits));
3367
3368 /** @todo We assume all channels in a stream have the same format. */
3369 PPDMAUDIOSTREAMCHANNEL pChan = pMapping->paChannels;
3370 for (uint8_t i = 0; i < pCfg->cChannels; i++)
3371 {
3372 pChan->uChannel = i;
3373 pChan->cbStep = (Props.cBits / 2);
3374 pChan->cbFrame = pChan->cbStep * pCfg->cChannels;
3375 pChan->cbFirst = i * pChan->cbStep;
3376 pChan->cbOff = pChan->cbFirst;
3377
3378 int rc2 = hdaStreamChannelDataInit(&pChan->Data, PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE);
3379 if (RT_SUCCESS(rc))
3380 rc = rc2;
3381
3382 if (RT_FAILURE(rc))
3383 break;
3384
3385 pChan++;
3386 }
3387
3388 if ( RT_SUCCESS(rc)
3389 /* Create circular buffer if not created yet. */
3390 && !pMapping->pCircBuf)
3391 {
3392 rc = RTCircBufCreate(&pMapping->pCircBuf, _4K); /** @todo Make size configurable? */
3393 }
3394
3395 if (RT_SUCCESS(rc))
3396 {
3397 pMapping->cChannels = pCfg->cChannels;
3398#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3399 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_INTERLEAVED;
3400#else
3401 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
3402#endif
3403 }
3404
3405 return rc;
3406}
3407
3408/**
3409 * Destroys a given stream mapping.
3410 *
3411 * @param pMapping Pointer to mapping to destroy.
3412 */
3413static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping)
3414{
3415 hdaStreamMapReset(pMapping);
3416
3417 if (pMapping->pCircBuf)
3418 {
3419 RTCircBufDestroy(pMapping->pCircBuf);
3420 pMapping->pCircBuf = NULL;
3421 }
3422}
3423
3424/**
3425 * Resets a given stream mapping.
3426 *
3427 * @param pMapping Pointer to mapping to reset.
3428 */
3429static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping)
3430{
3431 AssertPtrReturnVoid(pMapping);
3432
3433 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_UNKNOWN;
3434
3435 if (pMapping->cChannels)
3436 {
3437 for (uint8_t i = 0; i < pMapping->cChannels; i++)
3438 hdaStreamChannelDataDestroy(&pMapping->paChannels[i].Data);
3439
3440 AssertPtr(pMapping->paChannels);
3441 RTMemFree(pMapping->paChannels);
3442 pMapping->paChannels = NULL;
3443
3444 pMapping->cChannels = 0;
3445 }
3446}
3447#endif /* IN_RING3 */
3448
3449DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
3450{
3451 AssertPtrReturn(pThis, false);
3452 AssertPtrReturn(pStream, false);
3453
3454 PHDABDLE pBDLE = &pStream->State.BDLE;
3455 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3456
3457 /* Did we reach the CBL (Cyclic Buffer List) limit? */
3458 bool fCBLLimitReached = u32LPIB >= pStream->u32CBL;
3459
3460 /* Do we need to use the next BDLE entry? Either because we reached
3461 * the CBL limit or our internal DMA buffer is full. */
3462 bool fNeedsNextBDLE = ( fCBLLimitReached
3463 || (pBDLE->State.u32BufOff >= pBDLE->u32BufSize));
3464
3465 Assert(u32LPIB <= pStream->u32CBL);
3466 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3467
3468 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
3469 pStream->u8SD, u32LPIB, pStream->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
3470
3471 return fNeedsNextBDLE;
3472}
3473
3474DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbInc)
3475{
3476 AssertPtrReturnVoid(pThis);
3477 AssertPtrReturnVoid(pStream);
3478
3479 LogFlowFunc(("[SD%RU8]: cbInc=%RU32\n", pStream->u8SD, cbInc));
3480
3481 //Assert(cbInc <= pStream->u16FIFOS);
3482
3483 if (!cbInc) /* Nothing to do? Bail out early. */
3484 return;
3485
3486 PHDABDLE pBDLE = &pStream->State.BDLE;
3487
3488 /*
3489 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
3490 * doesn't fetch anything via DMA, so just update LPIB.
3491 * (ICH6 datasheet 18.2.38).
3492 */
3493 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
3494 {
3495 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3496
3497 AssertMsg(((u32LPIB + cbInc) <= pStream->u32CBL),
3498 ("[SD%RU8] Increment (%RU32) exceeds CBL (%RU32): LPIB (%RU32)\n",
3499 pStream->u8SD, cbInc, pStream->u32CBL, u32LPIB));
3500
3501 u32LPIB = RT_MIN(u32LPIB + cbInc, pStream->u32CBL);
3502
3503 LogFlowFunc(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
3504 pStream->u8SD,
3505 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) + cbInc,
3506 pStream->u32CBL));
3507
3508 hdaStreamUpdateLPIB(pThis, pStream, u32LPIB);
3509 }
3510}
3511
3512static bool hdaStreamTransferIsComplete(PHDASTATE pThis, PHDASTREAM pStream, bool *pfInterrupt)
3513{
3514 AssertPtrReturn(pThis, true);
3515 AssertPtrReturn(pStream, true);
3516
3517 bool fInterrupt = false;
3518 bool fIsComplete = false;
3519
3520 PHDABDLE pBDLE = &pStream->State.BDLE;
3521#ifdef LOG_ENABLED
3522 const uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3523#endif
3524
3525 /* Check if the current BDLE entry is complete (full). */
3526 if (pBDLE->State.u32BufOff >= pBDLE->u32BufSize)
3527 {
3528 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3529
3530 if (/* IOC (Interrupt On Completion) bit set? */
3531 pBDLE->fIntOnCompletion
3532 /* All data put into the DMA FIFO? */
3533 && pBDLE->State.cbBelowFIFOW == 0
3534 )
3535 {
3536 LogFlowFunc(("[SD%RU8]: %R[bdle] => COMPLETE\n", pStream->u8SD, pBDLE));
3537
3538 /*
3539 * If the ICE (IOCE, "Interrupt On Completion Enable") bit of the SDCTL register is set
3540 * we need to generate an interrupt.
3541 */
3542 if (HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
3543 fInterrupt = true;
3544 }
3545
3546 fIsComplete = true;
3547 }
3548
3549 if (pfInterrupt)
3550 *pfInterrupt = fInterrupt;
3551
3552 LogFlowFunc(("[SD%RU8]: u32LPIB=%RU32, CBL=%RU32, fIsComplete=%RTbool, fInterrupt=%RTbool, %R[bdle]\n",
3553 pStream->u8SD, u32LPIB, pStream->u32CBL, fIsComplete, fInterrupt, pBDLE));
3554
3555 return fIsComplete;
3556}
3557
3558/**
3559 * hdaReadAudio - copies samples from audio backend to DMA.
3560 * Note: This function writes to the DMA buffer immediately,
3561 * but "reports bytes" when all conditions are met (FIFOW).
3562 */
3563static int hdaReadAudio(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToRead, uint32_t *pcbRead)
3564{
3565 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3566 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
3567 /* pcbRead is optional. */
3568
3569 int rc;
3570 uint32_t cbRead = 0;
3571
3572 do
3573 {
3574 PHDABDLE pBDLE = &pStream->State.BDLE;
3575
3576 if (!cbToRead)
3577 {
3578 rc = VINF_EOF;
3579 break;
3580 }
3581
3582 AssertPtr(pStream->pMixSink);
3583 AssertPtr(pStream->pMixSink->pMixSink);
3584 rc = AudioMixerSinkRead(pStream->pMixSink->pMixSink, AUDMIXOP_BLEND, pBDLE->State.au8FIFO, cbToRead, &cbRead);
3585 if (RT_FAILURE(rc))
3586 break;
3587
3588 if (!cbRead)
3589 {
3590 rc = VINF_EOF;
3591 break;
3592 }
3593
3594 /* Sanity checks. */
3595 Assert(cbRead <= cbToRead);
3596 Assert(cbRead <= sizeof(pBDLE->State.au8FIFO));
3597 Assert(cbRead <= pBDLE->u32BufSize - pBDLE->State.u32BufOff);
3598
3599 /*
3600 * Write to the BDLE's DMA buffer.
3601 */
3602 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
3603 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
3604 pBDLE->State.au8FIFO, cbRead);
3605 AssertRC(rc);
3606
3607 if (pBDLE->State.cbBelowFIFOW + cbRead > hdaStreamGetFIFOW(pThis, pStream))
3608 {
3609 Assert(pBDLE->State.u32BufOff + cbRead <= pBDLE->u32BufSize);
3610 pBDLE->State.u32BufOff += cbRead;
3611 pBDLE->State.cbBelowFIFOW = 0;
3612 //hdaBackendReadTransferReported(pBDLE, cbDMAData, cbRead, &cbRead, pcbAvail);
3613 }
3614 else
3615 {
3616 Assert(pBDLE->State.u32BufOff + cbRead <= pBDLE->u32BufSize);
3617 pBDLE->State.u32BufOff += cbRead;
3618 pBDLE->State.cbBelowFIFOW += cbRead;
3619 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStream));
3620 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbRead, pcbAvail);
3621
3622 rc = VERR_NO_DATA;
3623 }
3624
3625 } while (0);
3626
3627 if (RT_SUCCESS(rc))
3628 {
3629 if (pcbRead)
3630 *pcbRead = cbRead;
3631 }
3632
3633 if (RT_FAILURE(rc))
3634 LogFlowFunc(("Failed with %Rrc\n", rc));
3635
3636 return rc;
3637}
3638
3639static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToWrite, uint32_t *pcbWritten)
3640{
3641 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3642 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
3643 /* pcbWritten is optional. */
3644
3645 PHDABDLE pBDLE = &pStream->State.BDLE;
3646
3647 uint32_t cbWritten = 0;
3648
3649 /*
3650 * Copy from DMA to the corresponding stream buffer (if there are any bytes from the
3651 * previous unreported transfer we write at offset 'pBDLE->State.cbUnderFifoW').
3652 */
3653 int rc;
3654 if (!cbToWrite)
3655 {
3656 rc = VINF_EOF;
3657 }
3658 else
3659 {
3660 void *pvBuf = pBDLE->State.au8FIFO + pBDLE->State.cbBelowFIFOW;
3661 Assert(cbToWrite >= pBDLE->State.cbBelowFIFOW);
3662 uint32_t cbBuf = cbToWrite - pBDLE->State.cbBelowFIFOW;
3663
3664 /*
3665 * Read from the current BDLE's DMA buffer.
3666 */
3667 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3668 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
3669 pvBuf, cbBuf);
3670 AssertRC(rc);
3671
3672#ifdef HDA_DEBUG_DUMP_PCM_DATA
3673 RTFILE fh;
3674 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaWriteAudio-hda.pcm",
3675 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
3676 RTFileWrite(fh, pvBuf, cbBuf, NULL);
3677 RTFileClose(fh);
3678#endif
3679
3680#ifdef VBOX_WITH_STATISTICS
3681 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBuf);
3682#endif
3683 /*
3684 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
3685 */
3686 if (cbBuf >= hdaStreamGetFIFOW(pThis, pStream))
3687 {
3688#if defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_HDA_51_SURROUND)
3689 PHDASTREAMMAPPING pMapping = &pStream->State.Mapping;
3690#endif
3691
3692 /** @todo Which channel is which? */
3693#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3694 PPDMAUDIOSTREAMCHANNEL pChanFront = &pMapping->paChannels[0];
3695#endif
3696#ifdef VBOX_WITH_HDA_51_SURROUND
3697 PPDMAUDIOSTREAMCHANNEL pChanCenterLFE = &pMapping->paChannels[2]; /** @todo FIX! */
3698 PPDMAUDIOSTREAMCHANNEL pChanRear = &pMapping->paChannels[4]; /** @todo FIX! */
3699#endif
3700 int rc2;
3701
3702 void *pvDataFront = NULL;
3703 size_t cbDataFront;
3704#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3705 rc2 = hdaStreamChannelExtract(pChanFront, pvBuf, cbBuf);
3706 AssertRC(rc2);
3707
3708 rc2 = hdaStreamChannelAcquireData(&pChanFront->Data, pvDataFront, &cbDataFront);
3709 AssertRC(rc2);
3710#else
3711 /* Use stuff in the whole FIFO to use for the channel data. */
3712 pvDataFront = pvBuf;
3713 cbDataFront = cbBuf;
3714#endif
3715#ifdef VBOX_WITH_HDA_51_SURROUND
3716 void *pvDataCenterLFE;
3717 size_t cbDataCenterLFE;
3718 rc2 = hdaStreamChannelExtract(pChanCenterLFE, pvBuf, cbBuf);
3719 AssertRC(rc2);
3720
3721 rc2 = hdaStreamChannelAcquireData(&pChanCenterLFE->Data, pvDataCenterLFE, &cbDataCenterLFE);
3722 AssertRC(rc2);
3723
3724 void *pvDataRear;
3725 size_t cbDataRear;
3726 rc2 = hdaStreamChannelExtract(pChanRear, pvBuf, cbBuf);
3727 AssertRC(rc2);
3728
3729 rc2 = hdaStreamChannelAcquireData(&pChanRear->Data, pvDataRear, &cbDataRear);
3730 AssertRC(rc2);
3731#endif
3732 /*
3733 * Write data to according mixer sinks.
3734 */
3735 rc2 = AudioMixerSinkWrite(pThis->SinkFront.pMixSink, AUDMIXOP_COPY, pvDataFront, (uint32_t)cbDataFront,
3736 NULL /* pcbWritten */);
3737 AssertRC(rc2);
3738#ifdef VBOX_WITH_HDA_51_SURROUND
3739 rc2 = AudioMixerSinkWrite(pThis->SinkCenterLFE, AUDMIXOP_COPY, pvDataCenterLFE, cbDataCenterLFE,
3740 NULL /* pcbWritten */);
3741 AssertRC(rc2);
3742 rc2 = AudioMixerSinkWrite(pThis->SinkRear, AUDMIXOP_COPY, pvDataRear, cbDataRear,
3743 NULL /* pcbWritten */);
3744 AssertRC(rc2);
3745#endif
3746
3747#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3748 hdaStreamChannelReleaseData(&pChanFront->Data);
3749#endif
3750#ifdef VBOX_WITH_HDA_51_SURROUND
3751 hdaStreamChannelReleaseData(&pChanCenterLFE->Data);
3752 hdaStreamChannelReleaseData(&pChanRear->Data);
3753#endif
3754
3755 /* Always report all data as being written;
3756 * backends who were not able to catch up have to deal with it themselves. */
3757 cbWritten = cbToWrite;
3758
3759 hdaBDLEUpdate(pBDLE, cbToWrite, cbWritten);
3760 }
3761 else
3762 {
3763 Assert(pBDLE->State.u32BufOff + cbWritten <= pBDLE->u32BufSize);
3764 pBDLE->State.u32BufOff += cbWritten;
3765 pBDLE->State.cbBelowFIFOW += cbWritten;
3766 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStream));
3767
3768 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
3769 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbAvail, NULL);
3770 rc = VINF_EOF;
3771 }
3772 }
3773
3774 //Assert(cbWritten <= pStream->u16FIFOS);
3775
3776 if (RT_SUCCESS(rc))
3777 {
3778 if (pcbWritten)
3779 *pcbWritten = cbWritten;
3780 }
3781
3782 if (RT_FAILURE(rc))
3783 LogFlowFunc(("Failed with %Rrc\n", rc));
3784
3785 return rc;
3786}
3787
3788/**
3789 * @interface_method_impl{HDACODEC,pfnReset}
3790 */
3791static DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
3792{
3793 PHDASTATE pThis = pCodec->pHDAState;
3794 NOREF(pThis);
3795 return VINF_SUCCESS;
3796}
3797
3798/**
3799 * Retrieves a corresponding sink for a given mixer control.
3800 * Returns NULL if no sink is found.
3801 *
3802 * @return PHDAMIXERSINK
3803 * @param pThis HDA state.
3804 * @param enmMixerCtl Mixer control to get the corresponding sink for.
3805 */
3806static PHDAMIXERSINK hdaMixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3807{
3808 PHDAMIXERSINK pSink;
3809
3810 switch (enmMixerCtl)
3811 {
3812 case PDMAUDIOMIXERCTL_VOLUME_MASTER:
3813 /* Fall through is intentional. */
3814 case PDMAUDIOMIXERCTL_FRONT:
3815 pSink = &pThis->SinkFront;
3816 break;
3817#ifdef VBOX_WITH_HDA_51_SURROUND
3818 case PDMAUDIOMIXERCTL_CENTER_LFE:
3819 pSink = &pThis->SinkCenterLFE;
3820 break;
3821 case PDMAUDIOMIXERCTL_REAR:
3822 pSink = &pThis->SinkRear;
3823 break;
3824#endif
3825 case PDMAUDIOMIXERCTL_LINE_IN:
3826 pSink = &pThis->SinkLineIn;
3827 break;
3828#ifdef VBOX_WITH_HDA_MIC_IN
3829 case PDMAUDIOMIXERCTL_MIC_IN:
3830 pSink = &pThis->SinkMicIn;
3831 break;
3832#endif
3833 default:
3834 pSink = NULL;
3835 AssertMsgFailed(("Unhandled mixer control\n"));
3836 break;
3837 }
3838
3839 return pSink;
3840}
3841
3842static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PHDAMIXERSINK pSink, PPDMAUDIOSTREAMCFG pCfg)
3843{
3844 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3845 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
3846 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3847
3848 LogFunc(("Sink=%s, Stream=%s\n", pSink->pMixSink->pszName, pCfg->szName));
3849
3850 /* Update the sink's format. */
3851 PDMAUDIOPCMPROPS PCMProps;
3852 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &PCMProps);
3853 if (RT_SUCCESS(rc))
3854 rc = AudioMixerSinkSetFormat(pSink->pMixSink, &PCMProps);
3855
3856 if (RT_FAILURE(rc))
3857 return rc;
3858
3859 PHDADRIVER pDrv;
3860 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3861 {
3862 int rc2 = VINF_SUCCESS;
3863 PHDAMIXERSTREAM pStream = NULL;
3864
3865 PPDMAUDIOSTREAMCFG pStreamCfg = (PPDMAUDIOSTREAMCFG)RTMemDup(pCfg, sizeof(PDMAUDIOSTREAMCFG));
3866 if (!pStreamCfg)
3867 {
3868 rc = VERR_NO_MEMORY;
3869 break;
3870 }
3871
3872 /* Include the driver's LUN in the stream name for easier identification. */
3873 RTStrPrintf(pStreamCfg->szName, RT_ELEMENTS(pStreamCfg->szName), "[LUN#%RU8] %s", pDrv->uLUN, pCfg->szName);
3874
3875 if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
3876 {
3877 LogFunc(("enmRecSource=%d\n", pStreamCfg->DestSource.Source));
3878
3879 switch (pStreamCfg->DestSource.Source)
3880 {
3881 case PDMAUDIORECSOURCE_LINE:
3882 pStream = &pDrv->LineIn;
3883 break;
3884#ifdef VBOX_WITH_HDA_MIC_IN
3885 case PDMAUDIORECSOURCE_MIC:
3886 pStream = &pDrv->MicIn;
3887 break;
3888#endif
3889 default:
3890 rc2 = VERR_NOT_SUPPORTED;
3891 break;
3892 }
3893 }
3894 else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
3895 {
3896 LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->DestSource.Dest));
3897
3898 switch (pStreamCfg->DestSource.Dest)
3899 {
3900 case PDMAUDIOPLAYBACKDEST_FRONT:
3901 pStream = &pDrv->Front;
3902 break;
3903#ifdef VBOX_WITH_HDA_51_SURROUND
3904 case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
3905 pStream = &pDrv->CenterLFE;
3906 break;
3907 case PDMAUDIOPLAYBACKDEST_REAR:
3908 pStream = &pDrv->Rear;
3909 break;
3910#endif
3911 default:
3912 rc2 = VERR_NOT_SUPPORTED;
3913 break;
3914 }
3915 }
3916 else
3917 rc2 = VERR_NOT_SUPPORTED;
3918
3919 if (RT_SUCCESS(rc2))
3920 {
3921 AssertPtr(pStream);
3922
3923 AudioMixerSinkRemoveStream(pSink->pMixSink, pStream->pMixStrm);
3924
3925 AudioMixerStreamDestroy(pStream->pMixStrm);
3926 pStream->pMixStrm = NULL;
3927
3928 PAUDMIXSTREAM pMixStrm;
3929 rc2 = AudioMixerSinkCreateStream(pSink->pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
3930 if (RT_SUCCESS(rc2))
3931 {
3932 rc2 = AudioMixerSinkAddStream(pSink->pMixSink, pMixStrm);
3933 LogFlowFunc(("LUN#%RU8: Added \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName , rc2));
3934 }
3935
3936 if (RT_SUCCESS(rc2))
3937 pStream->pMixStrm = pMixStrm;
3938 }
3939
3940 if (RT_SUCCESS(rc))
3941 rc = rc2;
3942
3943 if (pStreamCfg)
3944 {
3945 RTMemFree(pStreamCfg);
3946 pStreamCfg = NULL;
3947 }
3948 }
3949
3950 LogFlowFuncLeaveRC(rc);
3951 return rc;
3952}
3953
3954/**
3955 * Adds a new audio stream to a specific mixer control.
3956 * Depending on the mixer control the stream then gets assigned to one of the internal
3957 * mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
3958 *
3959 * @return IPRT status code.
3960 * @param pThis HDA state.
3961 * @param enmMixerCtl Mixer control to assign new stream to.
3962 * @param pCfg Stream configuration for the new stream.
3963 */
3964static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
3965{
3966 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3967 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3968
3969 int rc;
3970
3971 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3972 if (pSink)
3973 {
3974 rc = hdaMixerAddStream(pThis, pSink, pCfg);
3975
3976 AssertPtr(pSink->pMixSink);
3977 LogFlowFunc(("Sink=%s, enmMixerCtl=%d\n", pSink->pMixSink->pszName, enmMixerCtl));
3978 }
3979 else
3980 rc = VERR_NOT_FOUND;
3981
3982 LogFlowFuncLeaveRC(rc);
3983 return rc;
3984}
3985
3986/**
3987 * Removes a specified mixer control from the HDA's mixer.
3988 *
3989 * @return IPRT status code.
3990 * @param pThis HDA state.
3991 * @param enmMixerCtl Mixer control to remove.
3992 */
3993static DECLCALLBACK(int) hdaMixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3994{
3995 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3996
3997 int rc;
3998
3999 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
4000 if (pSink)
4001 {
4002 PHDADRIVER pDrv;
4003 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4004 {
4005 PAUDMIXSTREAM pMixStream = NULL;
4006 switch (enmMixerCtl)
4007 {
4008 /*
4009 * Input.
4010 */
4011 case PDMAUDIOMIXERCTL_LINE_IN:
4012 pMixStream = pDrv->LineIn.pMixStrm;
4013 pDrv->LineIn.pMixStrm = NULL;
4014 break;
4015#ifdef VBOX_WITH_HDA_MIC_IN
4016 case PDMAUDIOMIXERCTL_MIC_IN:
4017 pMixStream = pDrv->MicIn.pMixStrm;
4018 pDrv->MicIn.pMixStrm = NULL;
4019 break;
4020#endif
4021 /*
4022 * Output.
4023 */
4024 case PDMAUDIOMIXERCTL_FRONT:
4025 pMixStream = pDrv->Front.pMixStrm;
4026 pDrv->Front.pMixStrm = NULL;
4027 break;
4028#ifdef VBOX_WITH_HDA_51_SURROUND
4029 case PDMAUDIOMIXERCTL_CENTER_LFE:
4030 pMixStream = pDrv->CenterLFE.pMixStrm;
4031 pDrv->CenterLFE.pMixStrm = NULL;
4032 break;
4033 case PDMAUDIOMIXERCTL_REAR:
4034 pMixStream = pDrv->Rear.pMixStrm;
4035 pDrv->Rear.pMixStrm = NULL;
4036 break;
4037#endif
4038 default:
4039 AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
4040 break;
4041 }
4042
4043 if (pMixStream)
4044 {
4045 AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
4046 AudioMixerStreamDestroy(pMixStream);
4047
4048 pMixStream = NULL;
4049 }
4050 }
4051
4052 AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
4053 rc = VINF_SUCCESS;
4054 }
4055 else
4056 rc = VERR_NOT_FOUND;
4057
4058 LogFlowFunc(("enmMixerCtl=%d, rc=%Rrc\n", enmMixerCtl, rc));
4059 return rc;
4060}
4061
4062/**
4063 * Sets a SDn stream number and channel to a particular mixer control.
4064 *
4065 * @returns IPRT status code.
4066 * @param pThis HDA State.
4067 * @param enmMixerCtl Mixer control to set SD stream number and channel for.
4068 * @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
4069 * @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
4070 */
4071static DECLCALLBACK(int) hdaMixerSetStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
4072{
4073 LogFlowFunc(("enmMixerCtl=%RU32, uSD=%RU8, uChannel=%RU8\n", enmMixerCtl, uSD, uChannel));
4074
4075 if (uSD == 0) /* Stream number 0 is reserved. */
4076 {
4077 LogFlowFunc(("Invalid SDn (%RU8) number for mixer control %d, ignoring\n", uSD, enmMixerCtl));
4078 return VINF_SUCCESS;
4079 }
4080 /* uChannel is optional. */
4081
4082 /* SDn0 starts as 1. */
4083 Assert(uSD);
4084 uSD--;
4085
4086 int rc;
4087
4088 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
4089 if (pSink)
4090 {
4091 if ( (uSD < HDA_MAX_SDI)
4092 && AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
4093 {
4094 uSD += HDA_MAX_SDI;
4095 }
4096
4097 LogFlowFunc(("%s: Setting to stream ID=%RU8, channel=%RU8, enmMixerCtl=%RU32\n",
4098 pSink->pMixSink->pszName, uSD, uChannel, enmMixerCtl));
4099
4100 Assert(uSD < HDA_MAX_STREAMS);
4101
4102 PHDASTREAM pStream = hdaStreamFromSD(pThis, uSD);
4103 if (pStream)
4104 {
4105 pSink->uSD = uSD;
4106 pSink->uChannel = uChannel;
4107
4108 /* Make sure that the stream also has this sink set. */
4109 hdaStreamAssignToSink(pStream, pSink);
4110
4111 rc = VINF_SUCCESS;
4112 }
4113 else
4114 {
4115 LogRel(("HDA: Guest wanted to assign invalid stream ID=%RU8 (channel %RU8) to mixer control %RU32, skipping\n",
4116 uSD, uChannel, enmMixerCtl));
4117 rc = VERR_INVALID_PARAMETER;
4118 }
4119 }
4120 else
4121 rc = VERR_NOT_FOUND;
4122
4123 LogFlowFuncLeaveRC(rc);
4124 return rc;
4125}
4126
4127/**
4128 * Sets the volume of a specified mixer control.
4129 *
4130 * @return IPRT status code.
4131 * @param pThis HDA State.
4132 * @param enmMixerCtl Mixer control to set volume for.
4133 * @param pVol Pointer to volume data to set.
4134 */
4135static DECLCALLBACK(int) hdaMixerSetVolume(PHDASTATE pThis,
4136 PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
4137{
4138 int rc;
4139
4140 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
4141 if (pSink)
4142 {
4143 /* Set the volume.
4144 * We assume that the codec already converted it to the correct range. */
4145 rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
4146 }
4147 else
4148 rc = VERR_NOT_FOUND;
4149
4150 LogFlowFuncLeaveRC(rc);
4151 return rc;
4152}
4153
4154#ifndef VBOX_WITH_AUDIO_CALLBACKS
4155
4156static void hdaTimerMaybeStart(PHDASTATE pThis)
4157{
4158 if (pThis->cStreamsActive == 0) /* Only start the timer if there are no active streams. */
4159 return;
4160
4161 if (!pThis->pTimer)
4162 return;
4163
4164 LogFlowFuncEnter();
4165
4166 LogFlowFunc(("Starting timer\n"));
4167
4168 /* Set timer flag. */
4169 ASMAtomicXchgBool(&pThis->fTimerActive, true);
4170
4171 /* Update current time timestamp. */
4172 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
4173
4174 /* Fire off timer. */
4175 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
4176}
4177
4178static void hdaTimerMaybeStop(PHDASTATE pThis)
4179{
4180 if (pThis->cStreamsActive) /* Some streams still active? Bail out. */
4181 return;
4182
4183 if (!pThis->pTimer)
4184 return;
4185
4186 LogFlowFunc(("Stopping timer\n"));
4187
4188 /* Set timer flag. */
4189 ASMAtomicXchgBool(&pThis->fTimerActive, false);
4190}
4191
4192static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
4193{
4194 RT_NOREF(pDevIns);
4195 PHDASTATE pThis = (PHDASTATE)pvUser;
4196 Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
4197 AssertPtr(pThis);
4198
4199 STAM_PROFILE_START(&pThis->StatTimer, a);
4200
4201 uint64_t cTicksNow = TMTimerGet(pTimer);
4202
4203 LogFlowFuncEnter();
4204
4205 /* Update current time timestamp. */
4206 pThis->uTimerTS = cTicksNow;
4207
4208 /* Flag indicating whether to kick the timer again for a
4209 * new data processing round. */
4210 bool fKickTimer = false;
4211
4212 PHDASTREAM pStreamLineIn = hdaGetStreamFromSink(pThis, &pThis->SinkLineIn);
4213#ifdef VBOX_WITH_HDA_MIC_IN
4214 PHDASTREAM pStreamMicIn = hdaGetStreamFromSink(pThis, &pThis->SinkMicIn);
4215#endif
4216 PHDASTREAM pStreamFront = hdaGetStreamFromSink(pThis, &pThis->SinkFront);
4217#ifdef VBOX_WITH_HDA_51_SURROUND
4218 /** @todo See note below. */
4219#endif
4220
4221 uint32_t cbToProcess;
4222 int rc = AudioMixerSinkUpdate(pThis->SinkLineIn.pMixSink);
4223 if (RT_SUCCESS(rc))
4224 {
4225 cbToProcess = AudioMixerSinkGetReadable(pThis->SinkLineIn.pMixSink);
4226 if (cbToProcess)
4227 {
4228 rc = hdaTransfer(pThis, pStreamLineIn, cbToProcess, NULL /* pcbProcessed */);
4229 fKickTimer |= RT_SUCCESS(rc);
4230 }
4231 }
4232
4233#ifdef VBOX_WITH_HDA_MIC_IN
4234 rc = AudioMixerSinkUpdate(pThis->SinkMicIn.pMixSink);
4235 if (RT_SUCCESS(rc))
4236 {
4237 cbToProcess = AudioMixerSinkGetReadable(pThis->SinkMicIn.pMixSink);
4238 if (cbToProcess)
4239 {
4240 rc = hdaTransfer(pThis, pStreamMicIn, cbToProcess, NULL /* pcbProcessed */);
4241 fKickTimer |= RT_SUCCESS(rc);
4242 }
4243 }
4244#endif
4245
4246#ifdef VBOX_WITH_HDA_51_SURROUND
4247 rc = AudioMixerSinkUpdate(pThis->SinkCenterLFE.pMixSink);
4248 if (RT_SUCCESS(rc))
4249 {
4250
4251 }
4252
4253 rc = AudioMixerSinkUpdate(pThis->SinkRear.pMixSink);
4254 if (RT_SUCCESS(rc))
4255 {
4256
4257 }
4258 /** @todo Check for stream interleaving and only call hdaTransfer() if required! */
4259
4260 /*
4261 * Only call hdaTransfer if CenterLFE and/or Rear are on different SDs,
4262 * otherwise we have to use the interleaved streams support for getting the data
4263 * out of the Front sink (depending on the mapping layout).
4264 */
4265#endif
4266 rc = AudioMixerSinkUpdate(pThis->SinkFront.pMixSink);
4267 if (RT_SUCCESS(rc))
4268 {
4269 cbToProcess = AudioMixerSinkGetWritable(pThis->SinkFront.pMixSink);
4270 if (cbToProcess)
4271 {
4272 rc = hdaTransfer(pThis, pStreamFront, cbToProcess, NULL /* pcbProcessed */);
4273 fKickTimer |= RT_SUCCESS(rc);
4274 }
4275 }
4276
4277 if ( ASMAtomicReadBool(&pThis->fTimerActive)
4278 || fKickTimer)
4279 {
4280 /* Kick the timer again. */
4281 uint64_t cTicks = pThis->cTimerTicks;
4282 /** @todo adjust cTicks down by now much cbOutMin represents. */
4283 TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
4284 }
4285
4286 LogFlowFuncLeave();
4287
4288 STAM_PROFILE_STOP(&pThis->StatTimer, a);
4289}
4290
4291#else /* VBOX_WITH_AUDIO_CALLBACKS */
4292
4293static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4294{
4295 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
4296 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4297 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4298 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4299 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4300
4301 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4302 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4303
4304 PPDMAUDIOCALLBACKDATAIN pData = (PPDMAUDIOCALLBACKDATAIN)pvUser;
4305 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAIN), VERR_INVALID_PARAMETER);
4306
4307 return hdaTransfer(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
4308}
4309
4310static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4311{
4312 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
4313 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4314 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4315 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4316 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4317
4318 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4319 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4320
4321 PPDMAUDIOCALLBACKDATAOUT pData = (PPDMAUDIOCALLBACKDATAOUT)pvUser;
4322 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAOUT), VERR_INVALID_PARAMETER);
4323
4324 PHDASTATE pThis = pCtx->pThis;
4325
4326 int rc = hdaTransfer(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
4327 if ( RT_SUCCESS(rc)
4328 && pData->cbOutWritten)
4329 {
4330 PHDADRIVER pDrv;
4331 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4332 {
4333 uint32_t cSamplesPlayed;
4334 int rc2 = pDrv->pConnector->pfnPlay(pDrv->pConnector, &cSamplesPlayed);
4335 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
4336 }
4337 }
4338}
4339#endif /* VBOX_WITH_AUDIO_CALLBACKS */
4340
4341static int hdaTransfer(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToProcess, uint32_t *pcbProcessed)
4342{
4343 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4344 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4345 /* pcbProcessed is optional. */
4346
4347 if (ASMAtomicReadBool(&pThis->fInReset)) /* HDA controller in reset mode? Bail out. */
4348 {
4349 LogFlowFunc(("HDA in reset mode, skipping\n"));
4350
4351 if (pcbProcessed)
4352 *pcbProcessed = 0;
4353 return VINF_SUCCESS;
4354 }
4355
4356 bool fProceed = true;
4357 int rc = RTSemMutexRequest(pStream->State.hMtx, RT_INDEFINITE_WAIT);
4358 if (RT_FAILURE(rc))
4359 return rc;
4360
4361 Log3Func(("[SD%RU8] fActive=%RTbool, cbToProcess=%RU32\n", pStream->u8SD, pStream->State.fActive, cbToProcess));
4362
4363 /* Stop request received? */
4364 if ( !pStream->State.fActive
4365 || pStream->State.fDoStop)
4366 {
4367 pStream->State.fActive = false;
4368
4369 rc = RTSemEventSignal(pStream->State.hStateChangedEvent);
4370 AssertRC(rc);
4371
4372 fProceed = false;
4373 }
4374 /* Is the stream not in a running state currently? */
4375 else if (!(HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)))
4376 fProceed = false;
4377 /* Nothing to process? */
4378 else if (!cbToProcess)
4379 fProceed = false;
4380
4381 if ((HDA_STREAM_REG(pThis, STS, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
4382 {
4383 Log3Func(("[SD%RU8]: BCIS set\n", pStream->u8SD));
4384 fProceed = false;
4385 }
4386
4387 if (!fProceed)
4388 {
4389 Log3Func(("[SD%RU8]: Skipping\n", pStream->u8SD));
4390
4391 rc = RTSemMutexRelease(pStream->State.hMtx);
4392 AssertRC(rc);
4393
4394 if (pcbProcessed)
4395 *pcbProcessed = 0;
4396 return VINF_SUCCESS;
4397 }
4398
4399 /* Sanity checks. */
4400 Assert(pStream->u8SD <= HDA_MAX_STREAMS);
4401 Assert(pStream->u64BDLBase);
4402 Assert(pStream->u32CBL);
4403
4404 /* State sanity checks. */
4405 Assert(pStream->State.fInReset == false);
4406 Assert(HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) <= pStream->u32CBL);
4407
4408 bool fInterrupt = false;
4409
4410#ifdef DEBUG_andy
4411//# define DEBUG_SIMPLE
4412#endif
4413
4414#ifdef DEBUG_SIMPLE
4415 uint8_t u8FIFO[_16K+1];
4416 size_t u8FIFOff = 0;
4417#endif
4418
4419 uint32_t cbLeft = cbToProcess;
4420 uint32_t cbTotal = 0;
4421 uint32_t cbChunk = 0;
4422 uint32_t cbChunkProcessed = 0;
4423
4424 /* Set the FIFORDY bit on the stream while doing the transfer. */
4425 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
4426
4427 while (cbLeft)
4428 {
4429 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
4430 if (hdaStreamNeedsNextBDLE(pThis, pStream))
4431 {
4432 rc = hdaStreamGetNextBDLE(pThis, pStream);
4433 if (RT_FAILURE(rc))
4434 break;
4435 }
4436
4437 cbChunk = hdaStreamGetTransferSize(pThis, pStream, cbLeft);
4438 cbChunkProcessed = 0;
4439
4440 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
4441 rc = hdaReadAudio(pThis, pStream, cbChunk, &cbChunkProcessed);
4442 else
4443 {
4444#ifndef DEBUG_SIMPLE
4445 rc = hdaWriteAudio(pThis, pStream, cbChunk, &cbChunkProcessed);
4446#else
4447 void *pvBuf = u8FIFO + u8FIFOff;
4448 int32_t cbBuf = cbChunk;
4449
4450 PHDABDLE pBDLE = &pStream->State.BDLE;
4451
4452 if (cbBuf)
4453 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
4454 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
4455 pvBuf, cbBuf);
4456
4457 cbChunkProcessed = cbChunk;
4458
4459 hdaBDLEUpdate(pBDLE, cbChunkProcessed, cbChunkProcessed);
4460
4461 u8FIFOff += cbChunkProcessed;
4462 Assert((u8FIFOff & 1) == 0);
4463 Assert(u8FIFOff <= sizeof(u8FIFO));
4464#endif
4465 }
4466
4467 if (RT_FAILURE(rc))
4468 break;
4469
4470 hdaStreamTransferUpdate(pThis, pStream, cbChunkProcessed);
4471
4472 Assert(cbLeft >= cbChunkProcessed);
4473 cbLeft -= cbChunkProcessed;
4474 cbTotal += cbChunkProcessed;
4475
4476 if (rc == VINF_EOF)
4477 break;
4478
4479 if (hdaStreamTransferIsComplete(pThis, pStream, &fInterrupt))
4480 break;
4481 }
4482
4483 /* Remove the FIFORDY bit again. */
4484 HDA_STREAM_REG(pThis, STS, pStream->u8SD) &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
4485
4486 LogFlowFunc(("[SD%RU8]: %RU32 / %RU32, rc=%Rrc\n", pStream->u8SD, cbTotal, cbToProcess, rc));
4487
4488#ifdef DEBUG_SIMPLE
4489# ifdef HDA_DEBUG_DUMP_PCM_DATA
4490 RTFILE fh;
4491 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaWriteAudio.pcm",
4492 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4493 RTFileWrite(fh, u8FIFO, u8FIFOff, NULL);
4494 RTFileClose(fh);
4495# endif
4496
4497 AudioMixerSinkWrite(pThis->SinkFront.pMixSink, AUDMIXOP_COPY, u8FIFO, u8FIFOff,
4498 NULL /* pcbWritten */);
4499#endif /* DEBUG_SIMPLE */
4500
4501 if (fInterrupt)
4502 {
4503 /**
4504 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
4505 * last byte of data for the current descriptor has been fetched
4506 * from memory and put into the DMA FIFO.
4507 *
4508 * Speech synthesis works fine on Mac Guest if this bit isn't set
4509 * but in general sound quality gets worse.
4510 *
4511 * This must be set in *any* case.
4512 */
4513 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
4514 Log3Func(("[SD%RU8]: BCIS: Set\n", pStream->u8SD));
4515
4516 hdaProcessInterrupt(pThis);
4517 }
4518
4519 if (RT_SUCCESS(rc))
4520 {
4521 if (pcbProcessed)
4522 *pcbProcessed = cbTotal;
4523 }
4524
4525 int rc2 = RTSemMutexRelease(pStream->State.hMtx);
4526 if (RT_SUCCESS(rc))
4527 rc = rc2;
4528
4529 return rc;
4530}
4531#endif /* IN_RING3 */
4532
4533/* MMIO callbacks */
4534
4535/**
4536 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
4537 *
4538 * @note During implementation, we discovered so-called "forgotten" or "hole"
4539 * registers whose description is not listed in the RPM, datasheet, or
4540 * spec.
4541 */
4542PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4543{
4544 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4545 int rc;
4546 RT_NOREF_PV(pvUser);
4547
4548 /*
4549 * Look up and log.
4550 */
4551 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4552 int idxRegDsc = hdaRegLookup(offReg); /* Register descriptor index. */
4553#ifdef LOG_ENABLED
4554 unsigned const cbLog = cb;
4555 uint32_t offRegLog = offReg;
4556#endif
4557
4558 Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
4559 Assert(cb == 4); Assert((offReg & 3) == 0);
4560
4561 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4562 LogFunc(("Access to registers except GCTL is blocked while reset\n"));
4563
4564 if (idxRegDsc == -1)
4565 LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
4566
4567 if (idxRegDsc != -1)
4568 {
4569 /* ASSUMES gapless DWORD at end of map. */
4570 if (g_aHdaRegMap[idxRegDsc].size == 4)
4571 {
4572 /*
4573 * Straight forward DWORD access.
4574 */
4575 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
4576 Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
4577 }
4578 else
4579 {
4580 /*
4581 * Multi register read (unless there are trailing gaps).
4582 * ASSUMES that only DWORD reads have sideeffects.
4583 */
4584 uint32_t u32Value = 0;
4585 unsigned cbLeft = 4;
4586 do
4587 {
4588 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
4589 uint32_t u32Tmp = 0;
4590
4591 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
4592 Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
4593 if (rc != VINF_SUCCESS)
4594 break;
4595 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
4596
4597 cbLeft -= cbReg;
4598 offReg += cbReg;
4599 idxRegDsc++;
4600 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
4601
4602 if (rc == VINF_SUCCESS)
4603 *(uint32_t *)pv = u32Value;
4604 else
4605 Assert(!IOM_SUCCESS(rc));
4606 }
4607 }
4608 else
4609 {
4610 rc = VINF_IOM_MMIO_UNUSED_FF;
4611 Log3Func(("\tHole at %x is accessed for read\n", offReg));
4612 }
4613
4614 /*
4615 * Log the outcome.
4616 */
4617#ifdef LOG_ENABLED
4618 if (cbLog == 4)
4619 Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
4620 else if (cbLog == 2)
4621 Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
4622 else if (cbLog == 1)
4623 Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
4624#endif
4625 return rc;
4626}
4627
4628
4629DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
4630{
4631 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4632 {
4633 LogRel2(("HDA: Warning: Access to register 0x%x is blocked while reset\n", idxRegDsc));
4634 return VINF_SUCCESS;
4635 }
4636
4637#ifdef LOG_ENABLED
4638 uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4639 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
4640#endif
4641 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
4642 Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
4643 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
4644 RT_NOREF1(pszLog);
4645 return rc;
4646}
4647
4648
4649/**
4650 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
4651 */
4652PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
4653{
4654 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4655 int rc;
4656 RT_NOREF_PV(pvUser);
4657
4658 /*
4659 * The behavior of accesses that aren't aligned on natural boundraries is
4660 * undefined. Just reject them outright.
4661 */
4662 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
4663 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
4664 if (GCPhysAddr & (cb - 1))
4665 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
4666
4667 /*
4668 * Look up and log the access.
4669 */
4670 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4671 int idxRegDsc = hdaRegLookup(offReg);
4672 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
4673 uint64_t u64Value;
4674 if (cb == 4) u64Value = *(uint32_t const *)pv;
4675 else if (cb == 2) u64Value = *(uint16_t const *)pv;
4676 else if (cb == 1) u64Value = *(uint8_t const *)pv;
4677 else if (cb == 8) u64Value = *(uint64_t const *)pv;
4678 else
4679 {
4680 u64Value = 0; /* shut up gcc. */
4681 AssertReleaseMsgFailed(("%u\n", cb));
4682 }
4683
4684#ifdef LOG_ENABLED
4685 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
4686 if (idxRegDsc == -1)
4687 Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
4688 else if (cb == 4)
4689 Log3Func(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4690 else if (cb == 2)
4691 Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4692 else if (cb == 1)
4693 Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4694
4695 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
4696 Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
4697#endif
4698
4699 /*
4700 * Try for a direct hit first.
4701 */
4702 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
4703 {
4704 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
4705 Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
4706 }
4707 /*
4708 * Partial or multiple register access, loop thru the requested memory.
4709 */
4710 else
4711 {
4712 /*
4713 * If it's an access beyond the start of the register, shift the input
4714 * value and fill in missing bits. Natural alignment rules means we
4715 * will only see 1 or 2 byte accesses of this kind, so no risk of
4716 * shifting out input values.
4717 */
4718 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(offReg)) != -1)
4719 {
4720 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
4721 offReg -= cbBefore;
4722 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4723 u64Value <<= cbBefore * 8;
4724 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
4725 Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
4726 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
4727 }
4728
4729 /* Loop thru the write area, it may cover multiple registers. */
4730 rc = VINF_SUCCESS;
4731 for (;;)
4732 {
4733 uint32_t cbReg;
4734 if (idxRegDsc != -1)
4735 {
4736 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4737 cbReg = g_aHdaRegMap[idxRegDsc].size;
4738 if (cb < cbReg)
4739 {
4740 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
4741 Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
4742 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
4743 }
4744#ifdef LOG_ENABLED
4745 uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
4746#endif
4747 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
4748 Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
4749 }
4750 else
4751 {
4752 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
4753 cbReg = 1;
4754 }
4755 if (rc != VINF_SUCCESS)
4756 break;
4757 if (cbReg >= cb)
4758 break;
4759
4760 /* Advance. */
4761 offReg += cbReg;
4762 cb -= cbReg;
4763 u64Value >>= cbReg * 8;
4764 if (idxRegDsc == -1)
4765 idxRegDsc = hdaRegLookup(offReg);
4766 else
4767 {
4768 idxRegDsc++;
4769 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
4770 || g_aHdaRegMap[idxRegDsc].offset != offReg)
4771 {
4772 idxRegDsc = -1;
4773 }
4774 }
4775 }
4776 }
4777
4778 return rc;
4779}
4780
4781
4782/* PCI callback. */
4783
4784#ifdef IN_RING3
4785/**
4786 * @callback_method_impl{FNPCIIOREGIONMAP}
4787 */
4788static DECLCALLBACK(int)
4789hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
4790{
4791 RT_NOREF(iRegion, enmType);
4792 PPDMDEVINS pDevIns = pPciDev->pDevIns;
4793 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
4794
4795 /*
4796 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
4797 *
4798 * Let IOM talk DWORDs when reading, saves a lot of complications. On
4799 * writing though, we have to do it all ourselves because of sideeffects.
4800 */
4801 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
4802 int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
4803 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
4804 hdaMMIOWrite, hdaMMIORead, "HDA");
4805 if (RT_FAILURE(rc))
4806 return rc;
4807
4808 if (pThis->fR0Enabled)
4809 {
4810 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
4811 "hdaMMIOWrite", "hdaMMIORead");
4812 if (RT_FAILURE(rc))
4813 return rc;
4814 }
4815
4816 if (pThis->fRCEnabled)
4817 {
4818 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
4819 "hdaMMIOWrite", "hdaMMIORead");
4820 if (RT_FAILURE(rc))
4821 return rc;
4822 }
4823
4824 pThis->MMIOBaseAddr = GCPhysAddress;
4825 return VINF_SUCCESS;
4826}
4827
4828
4829/* Saved state callbacks. */
4830
4831static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
4832{
4833 RT_NOREF(pDevIns);
4834#ifdef DEBUG
4835 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4836#endif
4837 LogFlowFunc(("[SD%RU8]\n", pStrm->u8SD));
4838
4839 /* Save stream ID. */
4840 int rc = SSMR3PutU8(pSSM, pStrm->u8SD);
4841 AssertRCReturn(rc, rc);
4842 Assert(pStrm->u8SD <= HDA_MAX_STREAMS);
4843
4844 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields6, NULL);
4845 AssertRCReturn(rc, rc);
4846
4847#ifdef DEBUG /* Sanity checks. */
4848 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrm->u8SD),
4849 HDA_STREAM_REG(pThis, BDPU, pStrm->u8SD));
4850 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStrm->u8SD);
4851 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStrm->u8SD);
4852
4853 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
4854
4855 Assert(u64BaseDMA == pStrm->u64BDLBase);
4856 Assert(u16LVI == pStrm->u16LVI);
4857 Assert(u32CBL == pStrm->u32CBL);
4858#endif
4859
4860 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
4861 0 /*fFlags*/, g_aSSMBDLEFields6, NULL);
4862 AssertRCReturn(rc, rc);
4863
4864 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
4865 0 /*fFlags*/, g_aSSMBDLEStateFields6, NULL);
4866 AssertRCReturn(rc, rc);
4867
4868#ifdef DEBUG /* Sanity checks. */
4869 PHDABDLE pBDLE = &pStrm->State.BDLE;
4870 if (u64BaseDMA)
4871 {
4872 Assert(pStrm->State.uCurBDLE <= u16LVI + 1);
4873
4874 HDABDLE curBDLE;
4875 rc = hdaBDLEFetch(pThis, &curBDLE, u64BaseDMA, pStrm->State.uCurBDLE);
4876 AssertRC(rc);
4877
4878 Assert(curBDLE.u32BufSize == pBDLE->u32BufSize);
4879 Assert(curBDLE.u64BufAdr == pBDLE->u64BufAdr);
4880 Assert(curBDLE.fIntOnCompletion == pBDLE->fIntOnCompletion);
4881 }
4882 else
4883 {
4884 Assert(pBDLE->u64BufAdr == 0);
4885 Assert(pBDLE->u32BufSize == 0);
4886 }
4887#endif
4888 return rc;
4889}
4890
4891/**
4892 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4893 */
4894static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4895{
4896 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4897
4898 /* Save Codec nodes states. */
4899 hdaCodecSaveState(pThis->pCodec, pSSM);
4900
4901 /* Save MMIO registers. */
4902 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
4903 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4904
4905 /* Save number of streams. */
4906 SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
4907
4908 /* Save stream states. */
4909 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4910 {
4911 int rc = hdaSaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
4912 AssertRCReturn(rc, rc);
4913 }
4914
4915 return VINF_SUCCESS;
4916}
4917
4918
4919/**
4920 * @callback_method_impl{FNSSMDEVLOADEXEC}
4921 */
4922static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4923{
4924 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4925
4926 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
4927
4928 LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
4929
4930 /*
4931 * Load Codec nodes states.
4932 */
4933 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
4934 if (RT_FAILURE(rc))
4935 {
4936 LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
4937 return rc;
4938 }
4939
4940 /*
4941 * Load MMIO registers.
4942 */
4943 uint32_t cRegs;
4944 switch (uVersion)
4945 {
4946 case HDA_SSM_VERSION_1:
4947 /* Starting with r71199, we would save 112 instead of 113
4948 registers due to some code cleanups. This only affected trunk
4949 builds in the 4.1 development period. */
4950 cRegs = 113;
4951 if (SSMR3HandleRevision(pSSM) >= 71199)
4952 {
4953 uint32_t uVer = SSMR3HandleVersion(pSSM);
4954 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
4955 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
4956 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
4957 cRegs = 112;
4958 }
4959 break;
4960
4961 case HDA_SSM_VERSION_2:
4962 case HDA_SSM_VERSION_3:
4963 cRegs = 112;
4964 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
4965 break;
4966
4967 /* Since version 4 we store the register count to stay flexible. */
4968 case HDA_SSM_VERSION_4:
4969 case HDA_SSM_VERSION_5:
4970 case HDA_SSM_VERSION:
4971 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
4972 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
4973 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
4974 break;
4975
4976 default:
4977 LogRel(("HDA: Unsupported / too new saved state version (%RU32)\n", uVersion));
4978 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4979 }
4980
4981 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
4982 {
4983 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4984 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
4985 }
4986 else
4987 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
4988
4989 /*
4990 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
4991 * *every* BDLE state, whereas it only needs to be stored
4992 * *once* for every stream. Most of the BDLE state we can
4993 * get out of the registers anyway, so just ignore those values.
4994 *
4995 * Also, only the current BDLE was saved, regardless whether
4996 * there were more than one (and there are at least two entries,
4997 * according to the spec).
4998 */
4999#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
5000 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
5001 AssertRCReturn(rc, rc); \
5002 rc = SSMR3GetU64(pSSM, &x.u64BufAdr); /* u64BdleCviAddr */ \
5003 AssertRCReturn(rc, rc); \
5004 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
5005 AssertRCReturn(rc, rc); \
5006 rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
5007 AssertRCReturn(rc, rc); \
5008 rc = SSMR3GetU32(pSSM, &x.u32BufSize); /* u32BdleCviLen */ \
5009 AssertRCReturn(rc, rc); \
5010 rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
5011 AssertRCReturn(rc, rc); \
5012 rc = SSMR3GetBool(pSSM, &x.fIntOnCompletion); /* fBdleCviIoc */ \
5013 AssertRCReturn(rc, rc); \
5014 rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
5015 AssertRCReturn(rc, rc); \
5016 rc = SSMR3GetMem(pSSM, &x.State.au8FIFO, sizeof(x.State.au8FIFO)); \
5017 AssertRCReturn(rc, rc); \
5018 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
5019 AssertRCReturn(rc, rc); \
5020
5021 /*
5022 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
5023 */
5024 switch (uVersion)
5025 {
5026 case HDA_SSM_VERSION_1:
5027 case HDA_SSM_VERSION_2:
5028 case HDA_SSM_VERSION_3:
5029 case HDA_SSM_VERSION_4:
5030 {
5031 /* Only load the internal states.
5032 * The rest will be initialized from the saved registers later. */
5033
5034 /* Note 1: Only the *current* BDLE for a stream was saved! */
5035 /* Note 2: The stream's saving order is/was fixed, so don't touch! */
5036
5037 /* Output */
5038 PHDASTREAM pStream = &pThis->aStreams[4];
5039 rc = hdaStreamInit(pThis, pStream, 4 /* Stream descriptor, hardcoded */);
5040 if (RT_FAILURE(rc))
5041 break;
5042 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5043 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5044
5045 /* Microphone-In */
5046 pStream = &pThis->aStreams[2];
5047 rc = hdaStreamInit(pThis, pStream, 2 /* Stream descriptor, hardcoded */);
5048 if (RT_FAILURE(rc))
5049 break;
5050 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5051 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5052
5053 /* Line-In */
5054 pStream = &pThis->aStreams[0];
5055 rc = hdaStreamInit(pThis, pStream, 0 /* Stream descriptor, hardcoded */);
5056 if (RT_FAILURE(rc))
5057 break;
5058 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5059 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5060 break;
5061 }
5062
5063 /* Since v5 we support flexible stream and BDLE counts. */
5064 case HDA_SSM_VERSION_5:
5065 case HDA_SSM_VERSION:
5066 {
5067 uint32_t cStreams;
5068 rc = SSMR3GetU32(pSSM, &cStreams);
5069 if (RT_FAILURE(rc))
5070 break;
5071
5072 LogRel2(("hdaLoadExec: cStreams=%RU32\n", cStreams));
5073
5074 /* Load stream states. */
5075 for (uint32_t i = 0; i < cStreams; i++)
5076 {
5077 uint8_t uSD;
5078 rc = SSMR3GetU8(pSSM, &uSD);
5079 if (RT_FAILURE(rc))
5080 break;
5081
5082 PHDASTREAM pStrm = hdaStreamFromSD(pThis, uSD);
5083 HDASTREAM StreamDummy;
5084
5085 if (!pStrm)
5086 {
5087 RT_ZERO(StreamDummy);
5088 pStrm = &StreamDummy;
5089 LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uSD));
5090 break;
5091 }
5092
5093 rc = hdaStreamInit(pThis, pStrm, uSD);
5094 if (RT_FAILURE(rc))
5095 {
5096 LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uSD, rc));
5097 break;
5098 }
5099
5100 if (uVersion == HDA_SSM_VERSION_5)
5101 {
5102 /* Get the current BDLE entry and skip the rest. */
5103 uint16_t cBDLE;
5104
5105 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5106 AssertRC(rc);
5107 rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
5108 AssertRC(rc);
5109 rc = SSMR3GetU16(pSSM, &pStrm->State.uCurBDLE); /* uCurBDLE */
5110 AssertRC(rc);
5111 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5112 AssertRC(rc);
5113
5114 uint32_t u32BDLEIndex;
5115 for (uint16_t a = 0; a < cBDLE; a++)
5116 {
5117 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5118 AssertRC(rc);
5119 rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
5120 AssertRC(rc);
5121
5122 /* Does the current BDLE index match the current BDLE to process? */
5123 if (u32BDLEIndex == pStrm->State.uCurBDLE)
5124 {
5125 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
5126 AssertRC(rc);
5127 rc = SSMR3GetMem(pSSM,
5128 &pStrm->State.BDLE.State.au8FIFO,
5129 sizeof(pStrm->State.BDLE.State.au8FIFO)); /* au8FIFO */
5130 AssertRC(rc);
5131 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.u32BufOff); /* u32BufOff */
5132 AssertRC(rc);
5133 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5134 AssertRC(rc);
5135 }
5136 else /* Skip not current BDLEs. */
5137 {
5138 rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
5139 + sizeof(uint8_t) * 256 /* au8FIFO */
5140 + sizeof(uint32_t) /* u32BufOff */
5141 + sizeof(uint32_t)); /* End marker */
5142 AssertRC(rc);
5143 }
5144 }
5145 }
5146 else
5147 {
5148 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE),
5149 0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
5150 if (RT_FAILURE(rc))
5151 break;
5152
5153 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
5154 0 /* fFlags */, g_aSSMBDLEFields6, NULL);
5155 if (RT_FAILURE(rc))
5156 break;
5157
5158 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
5159 0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
5160 if (RT_FAILURE(rc))
5161 break;
5162 }
5163 }
5164 break;
5165 }
5166
5167 default:
5168 AssertReleaseFailed(); /* Never reached. */
5169 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5170 }
5171
5172#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
5173
5174 if (RT_SUCCESS(rc))
5175 {
5176 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
5177 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
5178 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
5179
5180 /* Also make sure to update the DMA position bit if this was enabled when saving the state. */
5181 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
5182 }
5183
5184 if (RT_SUCCESS(rc))
5185 {
5186 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5187 {
5188 PHDASTREAM pStream = hdaStreamFromSD(pThis, i);
5189 if (pStream)
5190 {
5191 /* Deactive first. */
5192 int rc2 = hdaStreamSetActive(pThis, pStream, false);
5193 AssertRC(rc2);
5194
5195 bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
5196
5197 /* Activate, if needed. */
5198 rc2 = hdaStreamSetActive(pThis, pStream, fActive);
5199 AssertRC(rc2);
5200 }
5201 }
5202 }
5203
5204 if (RT_FAILURE(rc))
5205 LogRel(("HDA: Failed loading device state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5206
5207 LogFlowFuncLeaveRC(rc);
5208 return rc;
5209}
5210
5211#ifdef DEBUG
5212/* Debug and log type formatters. */
5213
5214/**
5215 * @callback_method_impl{FNRTSTRFORMATTYPE}
5216 */
5217static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5218 const char *pszType, void const *pvValue,
5219 int cchWidth, int cchPrecision, unsigned fFlags,
5220 void *pvUser)
5221{
5222 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5223 PHDABDLE pBDLE = (PHDABDLE)pvValue;
5224 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5225 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
5226 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW, pBDLE->fIntOnCompletion,
5227 pBDLE->u32BufSize, pBDLE->u64BufAdr);
5228}
5229
5230/**
5231 * @callback_method_impl{FNRTSTRFORMATTYPE}
5232 */
5233static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5234 const char *pszType, void const *pvValue,
5235 int cchWidth, int cchPrecision, unsigned fFlags,
5236 void *pvUser)
5237{
5238 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5239 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
5240 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5241 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
5242 uSDCTL,
5243 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
5244 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
5245 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
5246 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
5247 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
5248 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
5249 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
5250 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
5251}
5252
5253/**
5254 * @callback_method_impl{FNRTSTRFORMATTYPE}
5255 */
5256static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5257 const char *pszType, void const *pvValue,
5258 int cchWidth, int cchPrecision, unsigned fFlags,
5259 void *pvUser)
5260{
5261 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5262 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
5263 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, hdaSDFIFOSToBytes(uSDFIFOS));
5264}
5265
5266/**
5267 * @callback_method_impl{FNRTSTRFORMATTYPE}
5268 */
5269static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5270 const char *pszType, void const *pvValue,
5271 int cchWidth, int cchPrecision, unsigned fFlags,
5272 void *pvUser)
5273{
5274 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5275 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
5276 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
5277}
5278
5279/**
5280 * @callback_method_impl{FNRTSTRFORMATTYPE}
5281 */
5282static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5283 const char *pszType, void const *pvValue,
5284 int cchWidth, int cchPrecision, unsigned fFlags,
5285 void *pvUser)
5286{
5287 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5288 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
5289 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5290 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
5291 uSdSts,
5292 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
5293 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
5294 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
5295 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
5296}
5297
5298static int hdaDbgLookupRegByName(const char *pszArgs)
5299{
5300 int iReg = 0;
5301 for (; iReg < HDA_NUM_REGS; ++iReg)
5302 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
5303 return iReg;
5304 return -1;
5305}
5306
5307
5308static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
5309{
5310 Assert( pThis
5311 && iHdaIndex >= 0
5312 && iHdaIndex < HDA_NUM_REGS);
5313 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
5314}
5315
5316/**
5317 * @callback_method_impl{FNDBGFHANDLERDEV}
5318 */
5319static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5320{
5321 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5322 int iHdaRegisterIndex = hdaDbgLookupRegByName(pszArgs);
5323 if (iHdaRegisterIndex != -1)
5324 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5325 else
5326 {
5327 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
5328 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5329 }
5330}
5331
5332static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5333{
5334 Assert( pThis
5335 && iIdx >= 0
5336 && iIdx < HDA_MAX_STREAMS);
5337
5338 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5339
5340 pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
5341 pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
5342 pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
5343 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
5344 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
5345 pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStrm->State.BDLE);
5346}
5347
5348static void hdaDbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5349{
5350 Assert( pThis
5351 && iIdx >= 0
5352 && iIdx < HDA_MAX_STREAMS);
5353
5354 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5355 const PHDABDLE pBDLE = &pStrm->State.BDLE;
5356
5357 pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
5358 pHlp->pfnPrintf(pHlp, "\t%R[bdle]\n", pBDLE);
5359
5360 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
5361 HDA_STREAM_REG(pThis, BDPU, iIdx));
5362 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
5363 /*uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx); - unused */
5364
5365 if (!u64BaseDMA)
5366 return;
5367
5368 uint32_t cbBDLE = 0;
5369 for (uint16_t i = 0; i < u16LVI + 1; i++)
5370 {
5371 uint8_t bdle[16]; /** @todo Use a define. */
5372 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * 16, bdle, 16); /** @todo Use a define. */
5373
5374 uint64_t addr = *(uint64_t *)bdle;
5375 uint32_t len = *(uint32_t *)&bdle[8];
5376 uint32_t ioc = *(uint32_t *)&bdle[12];
5377
5378 pHlp->pfnPrintf(pHlp, "\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
5379 i, addr, len, RT_BOOL(ioc & 0x1));
5380
5381 cbBDLE += len;
5382 }
5383
5384 pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
5385
5386 pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", pThis->u64DPBase);
5387 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
5388 {
5389 pHlp->pfnPrintf(pHlp, "No counters found\n");
5390 return;
5391 }
5392
5393 for (int i = 0; i < u16LVI + 1; i++)
5394 {
5395 uint32_t uDMACnt;
5396 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
5397 &uDMACnt, sizeof(uDMACnt));
5398
5399 pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
5400 }
5401}
5402
5403static int hdaDbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
5404{
5405 RT_NOREF(pThis, pszArgs);
5406 /** @todo Add args parsing. */
5407 return -1;
5408}
5409
5410/**
5411 * @callback_method_impl{FNDBGFHANDLERDEV}
5412 */
5413static DECLCALLBACK(void) hdaDbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5414{
5415 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5416 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5417 if (iHdaStreamdex != -1)
5418 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5419 else
5420 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5421 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5422}
5423
5424/**
5425 * @callback_method_impl{FNDBGFHANDLERDEV}
5426 */
5427static DECLCALLBACK(void) hdaDbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5428{
5429 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5430 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5431 if (iHdaStreamdex != -1)
5432 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5433 else
5434 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5435 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5436}
5437
5438/**
5439 * @callback_method_impl{FNDBGFHANDLERDEV}
5440 */
5441static DECLCALLBACK(void) hdaDbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5442{
5443 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5444
5445 if (pThis->pCodec->pfnDbgListNodes)
5446 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
5447 else
5448 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5449}
5450
5451/**
5452 * @callback_method_impl{FNDBGFHANDLERDEV}
5453 */
5454static DECLCALLBACK(void) hdaDbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5455{
5456 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5457
5458 if (pThis->pCodec->pfnDbgSelector)
5459 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
5460 else
5461 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5462}
5463
5464/**
5465 * @callback_method_impl{FNDBGFHANDLERDEV}
5466 */
5467static DECLCALLBACK(void) hdaDbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5468{
5469 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5470
5471 if (pThis->pMixer)
5472 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
5473 else
5474 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
5475}
5476#endif /* DEBUG */
5477
5478/* PDMIBASE */
5479
5480/**
5481 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5482 */
5483static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
5484{
5485 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
5486 Assert(&pThis->IBase == pInterface);
5487
5488 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5489 return NULL;
5490}
5491
5492
5493/* PDMDEVREG */
5494
5495/**
5496 * Reset notification.
5497 *
5498 * @returns VBox status code.
5499 * @param pDevIns The device instance data.
5500 *
5501 * @remark The original sources didn't install a reset handler, but it seems to
5502 * make sense to me so we'll do it.
5503 */
5504static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
5505{
5506 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5507
5508 LogFlowFuncEnter();
5509
5510# ifndef VBOX_WITH_AUDIO_CALLBACKS
5511 /*
5512 * Stop the timer, if any.
5513 */
5514 hdaTimerMaybeStop(pThis);
5515# endif
5516
5517 /* See 6.2.1. */
5518 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO /* Ouput streams */,
5519 HDA_MAX_SDI /* Input streams */,
5520 0 /* Bidirectional output streams */,
5521 0 /* Serial data out signals */,
5522 1 /* 64-bit */);
5523 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
5524 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
5525 /* Announce the full 60 words output payload. */
5526 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
5527 /* Announce the full 29 words input payload. */
5528 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
5529 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
5530 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
5531 HDA_REG(pThis, CORBRP) = 0x0;
5532 HDA_REG(pThis, RIRBWP) = 0x0;
5533
5534 /*
5535 * Stop any audio currently playing and/or recording.
5536 */
5537 AudioMixerSinkCtl(pThis->SinkFront.pMixSink, AUDMIXSINKCMD_DISABLE);
5538# ifdef VBOX_WITH_HDA_MIC_IN
5539 AudioMixerSinkCtl(pThis->SinkMicIn.pMixSink, AUDMIXSINKCMD_DISABLE);
5540# endif
5541 AudioMixerSinkCtl(pThis->SinkLineIn.pMixSink, AUDMIXSINKCMD_DISABLE);
5542# ifdef VBOX_WITH_HDA_51_SURROUND
5543 AudioMixerSinkCtl(pThis->SinkCenterLFE.pMixSink, AUDMIXSINKCMD_DISABLE);
5544 AudioMixerSinkCtl(pThis->SinkRear.pMixSink, AUDMIXSINKCMD_DISABLE);
5545# endif
5546
5547 /*
5548 * Set some sensible defaults for which HDA sinks
5549 * are connected to which stream number.
5550 *
5551 * We use SD0 for input and SD4 for output by default.
5552 * These stream numbers can be changed by the guest dynamically lateron.
5553 */
5554#ifdef VBOX_WITH_HDA_MIC_IN
5555 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 */, 0 /* Channel */);
5556#endif
5557 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 */, 0 /* Channel */);
5558
5559 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 */, 0 /* Channel */);
5560#ifdef VBOX_WITH_HDA_51_SURROUND
5561 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 */, 0 /* Channel */);
5562 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 */, 0 /* Channel */);
5563#endif
5564
5565 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
5566
5567 if (pThis->pu32CorbBuf)
5568 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
5569 else
5570 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5571
5572 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
5573 if (pThis->pu64RirbBuf)
5574 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
5575 else
5576 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5577
5578 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
5579
5580 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5581 {
5582 /* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
5583 HDA_STREAM_REG(pThis, CTL, i) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN);
5584 hdaStreamReset(pThis, &pThis->aStreams[i]);
5585 }
5586
5587 /* Clear stream tags <-> objects mapping table. */
5588 RT_ZERO(pThis->aTags);
5589
5590 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
5591 HDA_REG(pThis, STATESTS) = 0x1;
5592
5593# ifndef VBOX_WITH_AUDIO_CALLBACKS
5594 hdaTimerMaybeStart(pThis);
5595# endif
5596
5597 LogFlowFuncLeave();
5598 LogRel(("HDA: Reset\n"));
5599}
5600
5601/**
5602 * @interface_method_impl{PDMDEVREG,pfnDestruct}
5603 */
5604static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
5605{
5606 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5607
5608 PHDADRIVER pDrv;
5609 while (!RTListIsEmpty(&pThis->lstDrv))
5610 {
5611 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
5612
5613 RTListNodeRemove(&pDrv->Node);
5614 RTMemFree(pDrv);
5615 }
5616
5617 if (pThis->pCodec)
5618 {
5619 hdaCodecDestruct(pThis->pCodec);
5620
5621 RTMemFree(pThis->pCodec);
5622 pThis->pCodec = NULL;
5623 }
5624
5625 RTMemFree(pThis->pu32CorbBuf);
5626 pThis->pu32CorbBuf = NULL;
5627
5628 RTMemFree(pThis->pu64RirbBuf);
5629 pThis->pu64RirbBuf = NULL;
5630
5631 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5632 hdaStreamDestroy(&pThis->aStreams[i]);
5633
5634 return VINF_SUCCESS;
5635}
5636
5637
5638/**
5639 * Attach command, internal version.
5640 *
5641 * This is called to let the device attach to a driver for a specified LUN
5642 * during runtime. This is not called during VM construction, the device
5643 * constructor has to attach to all the available drivers.
5644 *
5645 * @returns VBox status code.
5646 * @param pDevIns The device instance.
5647 * @param pDrv Driver to (re-)use for (re-)attaching to.
5648 * If NULL is specified, a new driver will be created and appended
5649 * to the driver list.
5650 * @param uLUN The logical unit which is being detached.
5651 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5652 */
5653static int hdaAttachInternal(PPDMDEVINS pDevIns, PHDADRIVER pDrv, unsigned uLUN, uint32_t fFlags)
5654{
5655 RT_NOREF(fFlags);
5656 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5657
5658 /*
5659 * Attach driver.
5660 */
5661 char *pszDesc = NULL;
5662 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
5663 AssertReleaseMsgReturn(pszDesc,
5664 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
5665 VERR_NO_MEMORY);
5666
5667 PPDMIBASE pDrvBase;
5668 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
5669 &pThis->IBase, &pDrvBase, pszDesc);
5670 if (RT_SUCCESS(rc))
5671 {
5672 if (pDrv == NULL)
5673 pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
5674 if (pDrv)
5675 {
5676 pDrv->pDrvBase = pDrvBase;
5677 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
5678 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
5679 pDrv->pHDAState = pThis;
5680 pDrv->uLUN = uLUN;
5681
5682 /*
5683 * For now we always set the driver at LUN 0 as our primary
5684 * host backend. This might change in the future.
5685 */
5686 if (pDrv->uLUN == 0)
5687 pDrv->Flags |= PDMAUDIODRVFLAGS_PRIMARY;
5688
5689 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
5690
5691 /* Attach to driver list if not attached yet. */
5692 if (!pDrv->fAttached)
5693 {
5694 RTListAppend(&pThis->lstDrv, &pDrv->Node);
5695 pDrv->fAttached = true;
5696 }
5697 }
5698 else
5699 rc = VERR_NO_MEMORY;
5700 }
5701 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5702 LogFunc(("No attached driver for LUN #%u\n", uLUN));
5703
5704 if (RT_FAILURE(rc))
5705 {
5706 /* Only free this string on failure;
5707 * must remain valid for the live of the driver instance. */
5708 RTStrFree(pszDesc);
5709 }
5710
5711 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
5712 return rc;
5713}
5714
5715/**
5716 * Attach command.
5717 *
5718 * This is called to let the device attach to a driver for a specified LUN
5719 * during runtime. This is not called during VM construction, the device
5720 * constructor has to attach to all the available drivers.
5721 *
5722 * @returns VBox status code.
5723 * @param pDevIns The device instance.
5724 * @param uLUN The logical unit which is being detached.
5725 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5726 */
5727static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5728{
5729 return hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
5730}
5731
5732static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5733{
5734 RT_NOREF(pDevIns, uLUN, fFlags);
5735 LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
5736}
5737
5738/**
5739 * Powers off the device.
5740 *
5741 * @param pDevIns Device instance to power off.
5742 */
5743static DECLCALLBACK(void) hdaPowerOff(PPDMDEVINS pDevIns)
5744{
5745 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5746
5747 LogRel2(("HDA: Powering off ...\n"));
5748
5749 /* Ditto goes for the codec, which in turn uses the mixer. */
5750 hdaCodecPowerOff(pThis->pCodec);
5751
5752 /**
5753 * Note: Destroy the mixer while powering off and *not* in hdaDestruct,
5754 * giving the mixer the chance to release any references held to
5755 * PDM audio streams it maintains.
5756 */
5757 if (pThis->pMixer)
5758 {
5759 AudioMixerDestroy(pThis->pMixer);
5760 pThis->pMixer = NULL;
5761 }
5762}
5763
5764/**
5765 * Re-attaches a new driver to the device's driver chain.
5766 *
5767 * @returns VBox status code.
5768 * @param pThis Device instance to re-attach driver to.
5769 * @param pDrv Driver instance used for attaching to.
5770 * If NULL is specified, a new driver will be created and appended
5771 * to the driver list.
5772 * @param uLUN The logical unit which is being re-detached.
5773 * @param pszDriver Driver name.
5774 */
5775static int hdaReattach(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
5776{
5777 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
5778 AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
5779
5780 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
5781 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
5782 PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
5783
5784 /* Remove LUN branch. */
5785 CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
5786
5787 if (pDrv)
5788 {
5789 /* Re-use a driver instance => detach the driver before. */
5790 int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
5791 if (RT_FAILURE(rc))
5792 return rc;
5793 }
5794
5795#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
5796
5797 int rc = VINF_SUCCESS;
5798 do
5799 {
5800 PCFGMNODE pLunL0;
5801 rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
5802 rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
5803 rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
5804
5805 PCFGMNODE pLunL1, pLunL2;
5806 rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
5807 rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
5808 rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
5809
5810 rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
5811
5812 } while (0);
5813
5814 if (RT_SUCCESS(rc))
5815 rc = hdaAttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
5816
5817 LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
5818
5819#undef RC_CHECK
5820
5821 return rc;
5822}
5823
5824/**
5825 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5826 */
5827static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5828{
5829 RT_NOREF(iInstance);
5830 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5831 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5832 Assert(iInstance == 0);
5833
5834 /*
5835 * Validations.
5836 */
5837 if (!CFGMR3AreValuesValid(pCfg, "R0Enabled\0"
5838 "RCEnabled\0"
5839 "TimerHz\0"))
5840 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5841 N_ ("Invalid configuration for the Intel HDA device"));
5842
5843 int rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &pThis->fRCEnabled, false);
5844 if (RT_FAILURE(rc))
5845 return PDMDEV_SET_ERROR(pDevIns, rc,
5846 N_("HDA configuration error: failed to read RCEnabled as boolean"));
5847 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
5848 if (RT_FAILURE(rc))
5849 return PDMDEV_SET_ERROR(pDevIns, rc,
5850 N_("HDA configuration error: failed to read R0Enabled as boolean"));
5851#ifndef VBOX_WITH_AUDIO_CALLBACKS
5852 uint16_t uTimerHz;
5853 rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, 200 /* Hz */);
5854 if (RT_FAILURE(rc))
5855 return PDMDEV_SET_ERROR(pDevIns, rc,
5856 N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
5857#endif
5858
5859 /*
5860 * Initialize data (most of it anyway).
5861 */
5862 pThis->pDevInsR3 = pDevIns;
5863 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5864 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5865 /* IBase */
5866 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
5867
5868 /* PCI Device */
5869 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
5870 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
5871
5872 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
5873 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
5874 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
5875 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
5876 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
5877 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
5878 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
5879 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
5880 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
5881 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
5882 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
5883
5884#if defined(HDA_AS_PCI_EXPRESS)
5885 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
5886#elif defined(VBOX_WITH_MSI_DEVICES)
5887 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
5888#else
5889 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
5890#endif
5891
5892 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
5893 /// of these values needs to be properly documented!
5894 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
5895 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
5896
5897 /* Power Management */
5898 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
5899 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
5900 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
5901
5902#ifdef HDA_AS_PCI_EXPRESS
5903 /* PCI Express */
5904 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
5905 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
5906 /* Device flags */
5907 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
5908 /* version */ 0x1 |
5909 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
5910 /* MSI */ (100) << 9 );
5911 /* Device capabilities */
5912 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
5913 /* Device control */
5914 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
5915 /* Device status */
5916 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
5917 /* Link caps */
5918 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
5919 /* Link control */
5920 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
5921 /* Link status */
5922 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
5923 /* Slot capabilities */
5924 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
5925 /* Slot control */
5926 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
5927 /* Slot status */
5928 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
5929 /* Root control */
5930 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
5931 /* Root capabilities */
5932 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
5933 /* Root status */
5934 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
5935 /* Device capabilities 2 */
5936 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
5937 /* Device control 2 */
5938 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
5939 /* Link control 2 */
5940 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
5941 /* Slot control 2 */
5942 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
5943#endif
5944
5945 /*
5946 * Register the PCI device.
5947 */
5948 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5949 if (RT_FAILURE(rc))
5950 return rc;
5951
5952 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
5953 if (RT_FAILURE(rc))
5954 return rc;
5955
5956#ifdef VBOX_WITH_MSI_DEVICES
5957 PDMMSIREG MsiReg;
5958 RT_ZERO(MsiReg);
5959 MsiReg.cMsiVectors = 1;
5960 MsiReg.iMsiCapOffset = 0x60;
5961 MsiReg.iMsiNextOffset = 0x50;
5962 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5963 if (RT_FAILURE(rc))
5964 {
5965 /* That's OK, we can work without MSI */
5966 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
5967 }
5968#endif
5969
5970 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
5971 if (RT_FAILURE(rc))
5972 return rc;
5973
5974 RTListInit(&pThis->lstDrv);
5975
5976 uint8_t uLUN;
5977 for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
5978 {
5979 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
5980 rc = hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, 0 /* fFlags */);
5981 if (RT_FAILURE(rc))
5982 {
5983 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5984 rc = VINF_SUCCESS;
5985 else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
5986 {
5987 hdaReattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
5988 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
5989 N_("No audio devices could be opened. Selecting the NULL audio backend "
5990 "with the consequence that no sound is audible"));
5991 /* attaching to the NULL audio backend will never fail */
5992 rc = VINF_SUCCESS;
5993 }
5994 break;
5995 }
5996 }
5997
5998 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
5999
6000 if (RT_SUCCESS(rc))
6001 {
6002 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
6003 if (RT_SUCCESS(rc))
6004 {
6005 /*
6006 * Add mixer output sinks.
6007 */
6008#ifdef VBOX_WITH_HDA_51_SURROUND
6009 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
6010 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
6011 AssertRC(rc);
6012 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
6013 AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
6014 AssertRC(rc);
6015 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
6016 AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
6017 AssertRC(rc);
6018#else
6019 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
6020 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
6021 AssertRC(rc);
6022#endif
6023 /*
6024 * Add mixer input sinks.
6025 */
6026 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
6027 AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
6028 AssertRC(rc);
6029#ifdef VBOX_WITH_HDA_MIC_IN
6030 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
6031 AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
6032 AssertRC(rc);
6033#endif
6034 /* There is no master volume control. Set the master to max. */
6035 PDMAUDIOVOLUME vol = { false, 255, 255 };
6036 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
6037 AssertRC(rc);
6038 }
6039 }
6040
6041 if (RT_SUCCESS(rc))
6042 {
6043 /* Construct codec. */
6044 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
6045 if (!pThis->pCodec)
6046 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
6047
6048 /* Set codec callbacks. */
6049 pThis->pCodec->pfnMixerAddStream = hdaMixerAddStream;
6050 pThis->pCodec->pfnMixerRemoveStream = hdaMixerRemoveStream;
6051 pThis->pCodec->pfnMixerSetStream = hdaMixerSetStream;
6052 pThis->pCodec->pfnMixerSetVolume = hdaMixerSetVolume;
6053 pThis->pCodec->pfnReset = hdaCodecReset;
6054
6055 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
6056
6057 /* Construct the codec. */
6058 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
6059 if (RT_FAILURE(rc))
6060 AssertRCReturn(rc, rc);
6061
6062 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
6063 verb F20 should provide device/codec recognition. */
6064 Assert(pThis->pCodec->u16VendorId);
6065 Assert(pThis->pCodec->u16DeviceId);
6066 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
6067 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
6068 }
6069
6070 if (RT_SUCCESS(rc))
6071 {
6072 /*
6073 * Create all hardware streams.
6074 */
6075 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
6076 {
6077 rc = hdaStreamCreate(&pThis->aStreams[i], i /* uSD */);
6078 AssertRC(rc);
6079 }
6080
6081 /*
6082 * Initialize the driver chain.
6083 */
6084 PHDADRIVER pDrv;
6085 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6086 {
6087 /*
6088 * Only primary drivers are critical for the VM to run. Everything else
6089 * might not worth showing an own error message box in the GUI.
6090 */
6091 if (!(pDrv->Flags & PDMAUDIODRVFLAGS_PRIMARY))
6092 continue;
6093
6094 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
6095 AssertPtr(pCon);
6096
6097 bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
6098#ifdef VBOX_WITH_HDA_MIC_IN
6099 bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
6100#endif
6101 bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
6102#ifdef VBOX_WITH_HDA_51_SURROUND
6103 /** @todo Anything to do here? */
6104#endif
6105
6106 if ( !fValidLineIn
6107#ifdef VBOX_WITH_HDA_MIC_IN
6108 && !fValidMicIn
6109#endif
6110 && !fValidOut)
6111 {
6112 LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
6113
6114 hdaReset(pDevIns);
6115 hdaReattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
6116
6117 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6118 N_("No audio devices could be opened. Selecting the NULL audio backend "
6119 "with the consequence that no sound is audible"));
6120 }
6121 else
6122 {
6123 bool fWarn = false;
6124
6125 PDMAUDIOBACKENDCFG backendCfg;
6126 int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
6127 if (RT_SUCCESS(rc2))
6128 {
6129 if (backendCfg.cSources)
6130 {
6131#ifdef VBOX_WITH_HDA_MIC_IN
6132 /* If the audio backend supports two or more input streams at once,
6133 * warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
6134 if (backendCfg.cMaxStreamsIn >= 2)
6135 fWarn = !fValidLineIn || !fValidMicIn;
6136 /* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
6137 * *not* ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
6138 * One of the two simply is not in use then. */
6139 else if (backendCfg.cMaxStreamsIn == 1)
6140 fWarn = !fValidLineIn && !fValidMicIn;
6141 /* Don't warn if our backend is not able of supporting any input streams at all. */
6142#else
6143 /* We only have line-in as input source. */
6144 fWarn = !fValidLineIn;
6145#endif
6146 }
6147
6148 if ( !fWarn
6149 && backendCfg.cSinks)
6150 {
6151 fWarn = !fValidOut;
6152 }
6153 }
6154 else
6155 {
6156 LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
6157 fWarn = true;
6158 }
6159
6160 if (fWarn)
6161 {
6162 char szMissingStreams[255];
6163 size_t len = 0;
6164 if (!fValidLineIn)
6165 {
6166 LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
6167 len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
6168 }
6169#ifdef VBOX_WITH_HDA_MIC_IN
6170 if (!fValidMicIn)
6171 {
6172 LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
6173 len += RTStrPrintf(szMissingStreams + len,
6174 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
6175 }
6176#endif
6177 if (!fValidOut)
6178 {
6179 LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
6180 len += RTStrPrintf(szMissingStreams + len,
6181 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
6182 }
6183
6184 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6185 N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
6186 "output or depending on audio input may hang. Make sure your host audio device "
6187 "is working properly. Check the logfile for error messages of the audio "
6188 "subsystem"), szMissingStreams);
6189 }
6190 }
6191 }
6192 }
6193
6194 if (RT_SUCCESS(rc))
6195 {
6196 hdaReset(pDevIns);
6197
6198 /*
6199 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
6200 * hdaReset shouldn't affects these registers.
6201 */
6202 HDA_REG(pThis, WAKEEN) = 0x0;
6203 HDA_REG(pThis, STATESTS) = 0x0;
6204
6205#ifdef DEBUG
6206 /*
6207 * Debug and string formatter types.
6208 */
6209 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
6210 PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaDbgInfoBDLE);
6211 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgInfoStream);
6212 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaDbgInfoCodecNodes);
6213 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaDbgInfoCodecSelector);
6214 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaDbgInfoMixer);
6215
6216 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
6217 AssertRC(rc);
6218 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
6219 AssertRC(rc);
6220 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
6221 AssertRC(rc);
6222 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
6223 AssertRC(rc);
6224 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
6225 AssertRC(rc);
6226#endif /* DEBUG */
6227
6228 /*
6229 * Some debug assertions.
6230 */
6231 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
6232 {
6233 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
6234 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
6235
6236 /* binary search order. */
6237 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
6238 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6239 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6240
6241 /* alignment. */
6242 AssertReleaseMsg( pReg->size == 1
6243 || (pReg->size == 2 && (pReg->offset & 1) == 0)
6244 || (pReg->size == 3 && (pReg->offset & 3) == 0)
6245 || (pReg->size == 4 && (pReg->offset & 3) == 0),
6246 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6247
6248 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
6249 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
6250 if (pReg->offset & 3)
6251 {
6252 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
6253 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6254 if (pPrevReg)
6255 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
6256 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6257 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
6258 }
6259#if 0
6260 if ((pReg->offset + pReg->size) & 3)
6261 {
6262 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6263 if (pNextReg)
6264 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
6265 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6266 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6267 }
6268#endif
6269 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
6270 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
6271 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6272 }
6273 }
6274
6275# ifndef VBOX_WITH_AUDIO_CALLBACKS
6276 if (RT_SUCCESS(rc))
6277 {
6278 /* Start the emulation timer. */
6279 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
6280 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
6281 AssertRCReturn(rc, rc);
6282
6283 if (RT_SUCCESS(rc))
6284 {
6285 pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
6286 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
6287 LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
6288
6289 hdaTimerMaybeStart(pThis);
6290 }
6291 }
6292# else
6293 if (RT_SUCCESS(rc))
6294 {
6295 PHDADRIVER pDrv;
6296 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6297 {
6298 /* Only register primary driver.
6299 * The device emulation does the output multiplexing then. */
6300 if (pDrv->Flags != PDMAUDIODRVFLAGS_PRIMARY)
6301 continue;
6302
6303 PDMAUDIOCALLBACK AudioCallbacks[2];
6304
6305 HDACALLBACKCTX Ctx = { pThis, pDrv };
6306
6307 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
6308 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
6309 AudioCallbacks[0].pvCtx = &Ctx;
6310 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
6311
6312 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
6313 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
6314 AudioCallbacks[1].pvCtx = &Ctx;
6315 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
6316
6317 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
6318 if (RT_FAILURE(rc))
6319 break;
6320 }
6321 }
6322# endif
6323
6324# ifdef VBOX_WITH_STATISTICS
6325 if (RT_SUCCESS(rc))
6326 {
6327 /*
6328 * Register statistics.
6329 */
6330# ifndef VBOX_WITH_AUDIO_CALLBACKS
6331 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
6332# endif
6333 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
6334 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
6335 }
6336# endif
6337
6338 LogFlowFuncLeaveRC(rc);
6339 return rc;
6340}
6341
6342/**
6343 * The device registration structure.
6344 */
6345const PDMDEVREG g_DeviceICH6_HDA =
6346{
6347 /* u32Version */
6348 PDM_DEVREG_VERSION,
6349 /* szName */
6350 "hda",
6351 /* szRCMod */
6352 "VBoxDDRC.rc",
6353 /* szR0Mod */
6354 "VBoxDDR0.r0",
6355 /* pszDescription */
6356 "Intel HD Audio Controller",
6357 /* fFlags */
6358 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
6359 /* fClass */
6360 PDM_DEVREG_CLASS_AUDIO,
6361 /* cMaxInstances */
6362 1,
6363 /* cbInstance */
6364 sizeof(HDASTATE),
6365 /* pfnConstruct */
6366 hdaConstruct,
6367 /* pfnDestruct */
6368 hdaDestruct,
6369 /* pfnRelocate */
6370 NULL,
6371 /* pfnMemSetup */
6372 NULL,
6373 /* pfnPowerOn */
6374 NULL,
6375 /* pfnReset */
6376 hdaReset,
6377 /* pfnSuspend */
6378 NULL,
6379 /* pfnResume */
6380 NULL,
6381 /* pfnAttach */
6382 hdaAttach,
6383 /* pfnDetach */
6384 hdaDetach,
6385 /* pfnQueryInterface. */
6386 NULL,
6387 /* pfnInitComplete */
6388 NULL,
6389 /* pfnPowerOff */
6390 hdaPowerOff,
6391 /* pfnSoftReset */
6392 NULL,
6393 /* u32VersionEnd */
6394 PDM_DEVREG_VERSION
6395};
6396
6397#endif /* IN_RING3 */
6398#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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