VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 63373

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1/* $Id: DevIchHda.cpp 63373 2016-08-12 17:03:50Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2016 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/file.h>
36#include <iprt/list.h>
37#ifdef IN_RING3
38# include <iprt/mem.h>
39# include <iprt/semaphore.h>
40# include <iprt/string.h>
41# include <iprt/uuid.h>
42#endif
43
44#include "VBoxDD.h"
45
46#include "AudioMixBuffer.h"
47#include "AudioMixer.h"
48#include "DevIchHdaCodec.h"
49#include "DevIchHdaCommon.h"
50#include "DrvAudio.h"
51
52
53/*********************************************************************************************************************************
54* Defined Constants And Macros *
55*********************************************************************************************************************************/
56//#define HDA_AS_PCI_EXPRESS
57#define VBOX_WITH_INTEL_HDA
58
59#ifdef DEBUG_andy
60/*
61 * HDA_DEBUG_DUMP_PCM_DATA enables dumping the raw PCM data
62 * to a file on the host. Be sure to adjust HDA_DEBUG_DUMP_PCM_DATA_PATH
63 * to your needs before using this!
64 */
65# define HDA_DEBUG_DUMP_PCM_DATA
66# ifdef RT_OS_WINDOWS
67# define HDA_DEBUG_DUMP_PCM_DATA_PATH "c:\\temp\\"
68# else
69# define HDA_DEBUG_DUMP_PCM_DATA_PATH "/tmp/"
70# endif
71
72/* Enables experimental support for separate mic-in handling.
73 Do not enable this yet for regular builds, as this needs more testing first! */
74//# define VBOX_WITH_HDA_MIC_IN
75#endif
76
77#if defined(VBOX_WITH_HP_HDA)
78/* HP Pavilion dv4t-1300 */
79# define HDA_PCI_VENDOR_ID 0x103c
80# define HDA_PCI_DEVICE_ID 0x30f7
81#elif defined(VBOX_WITH_INTEL_HDA)
82/* Intel HDA controller */
83# define HDA_PCI_VENDOR_ID 0x8086
84# define HDA_PCI_DEVICE_ID 0x2668
85#elif defined(VBOX_WITH_NVIDIA_HDA)
86/* nVidia HDA controller */
87# define HDA_PCI_VENDOR_ID 0x10de
88# define HDA_PCI_DEVICE_ID 0x0ac0
89#else
90# error "Please specify your HDA device vendor/device IDs"
91#endif
92
93/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
94 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
95 * is read only except for bit 15 like the HDA spec states.
96 *
97 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
98 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
99#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
100
101/* Make sure that interleaving streams support is enabled if the 5.1 code is being used. */
102#if defined (VBOX_WITH_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT)
103# define VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
104#endif
105
106/**
107 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
108 * Bidirectional streams are currently *not* supported.
109 *
110 * Note: When changing any of those values, be prepared for some saved state
111 * fixups / trouble!
112 */
113#define HDA_MAX_SDI 4
114#define HDA_MAX_SDO 4
115#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
116AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
117
118/** Number of general registers. */
119#define HDA_NUM_GENERAL_REGS 34
120/** Number of total registers in the HDA's register map. */
121#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
122/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
123#define HDA_MAX_TAGS 16
124
125/**
126 * NB: Register values stored in memory (au32Regs[]) are indexed through
127 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
128 * register descriptors in g_aHdaRegMap[] are indexed through the
129 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
130 *
131 * The au32Regs[] layout is kept unchanged for saved state
132 * compatibility.
133 */
134
135/* Registers */
136#define HDA_REG_IND_NAME(x) HDA_REG_##x
137#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
138#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
139#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
140#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
141#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
142#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
143#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
144
145
146#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
147#define HDA_RMX_GCAP 0
148/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
149 * oss (15:12) - number of output streams supported
150 * iss (11:8) - number of input streams supported
151 * bss (7:3) - number of bidirectional streams supported
152 * bds (2:1) - number of serial data out (SDO) signals supported
153 * b64sup (0) - 64 bit addressing supported.
154 */
155#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
156 ( (((oss) & 0xF) << 12) \
157 | (((iss) & 0xF) << 8) \
158 | (((bss) & 0x1F) << 3) \
159 | (((bds) & 0x3) << 1) \
160 | ((b64sup) & 1))
161
162#define HDA_REG_VMIN 1 /* 0x02 */
163#define HDA_RMX_VMIN 1
164
165#define HDA_REG_VMAJ 2 /* 0x03 */
166#define HDA_RMX_VMAJ 2
167
168#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
169#define HDA_RMX_OUTPAY 3
170
171#define HDA_REG_INPAY 4 /* 0x06-0x07 */
172#define HDA_RMX_INPAY 4
173
174#define HDA_REG_GCTL 5 /* 0x08-0x0B */
175#define HDA_RMX_GCTL 5
176#define HDA_GCTL_RST_SHIFT 0
177#define HDA_GCTL_FSH_SHIFT 1
178#define HDA_GCTL_UR_SHIFT 8
179
180#define HDA_REG_WAKEEN 6 /* 0x0C */
181#define HDA_RMX_WAKEEN 6
182
183#define HDA_REG_STATESTS 7 /* 0x0E */
184#define HDA_RMX_STATESTS 7
185#define HDA_STATES_SCSF 0x7
186
187#define HDA_REG_GSTS 8 /* 0x10-0x11*/
188#define HDA_RMX_GSTS 8
189#define HDA_GSTS_FSH_SHIFT 1
190
191#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
192#define HDA_RMX_OUTSTRMPAY 112
193
194#define HDA_REG_INSTRMPAY 10 /* 0x1a */
195#define HDA_RMX_INSTRMPAY 113
196
197#define HDA_REG_INTCTL 11 /* 0x20 */
198#define HDA_RMX_INTCTL 9
199#define HDA_INTCTL_GIE_SHIFT 31
200#define HDA_INTCTL_CIE_SHIFT 30
201#define HDA_INTCTL_S0_SHIFT 0
202#define HDA_INTCTL_S1_SHIFT 1
203#define HDA_INTCTL_S2_SHIFT 2
204#define HDA_INTCTL_S3_SHIFT 3
205#define HDA_INTCTL_S4_SHIFT 4
206#define HDA_INTCTL_S5_SHIFT 5
207#define HDA_INTCTL_S6_SHIFT 6
208#define HDA_INTCTL_S7_SHIFT 7
209#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
210
211#define HDA_REG_INTSTS 12 /* 0x24 */
212#define HDA_RMX_INTSTS 10
213#define HDA_INTSTS_GIS_SHIFT 31
214#define HDA_INTSTS_CIS_SHIFT 30
215#define HDA_INTSTS_S0_SHIFT 0
216#define HDA_INTSTS_S1_SHIFT 1
217#define HDA_INTSTS_S2_SHIFT 2
218#define HDA_INTSTS_S3_SHIFT 3
219#define HDA_INTSTS_S4_SHIFT 4
220#define HDA_INTSTS_S5_SHIFT 5
221#define HDA_INTSTS_S6_SHIFT 6
222#define HDA_INTSTS_S7_SHIFT 7
223#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
224
225#define HDA_REG_WALCLK 13 /* 0x30 */
226#define HDA_RMX_WALCLK /* Not defined! */
227
228/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
229 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
230 * the datasheet.
231 */
232#define HDA_REG_SSYNC 14 /* 0x38 */
233#define HDA_RMX_SSYNC 12
234
235#define HDA_REG_CORBLBASE 15 /* 0x40 */
236#define HDA_RMX_CORBLBASE 13
237
238#define HDA_REG_CORBUBASE 16 /* 0x44 */
239#define HDA_RMX_CORBUBASE 14
240
241#define HDA_REG_CORBWP 17 /* 0x48 */
242#define HDA_RMX_CORBWP 15
243
244#define HDA_REG_CORBRP 18 /* 0x4A */
245#define HDA_RMX_CORBRP 16
246#define HDA_CORBRP_RST_SHIFT 15
247#define HDA_CORBRP_WP_SHIFT 0
248#define HDA_CORBRP_WP_MASK 0xFF
249
250#define HDA_REG_CORBCTL 19 /* 0x4C */
251#define HDA_RMX_CORBCTL 17
252#define HDA_CORBCTL_DMA_SHIFT 1
253#define HDA_CORBCTL_CMEIE_SHIFT 0
254
255#define HDA_REG_CORBSTS 20 /* 0x4D */
256#define HDA_RMX_CORBSTS 18
257#define HDA_CORBSTS_CMEI_SHIFT 0
258
259#define HDA_REG_CORBSIZE 21 /* 0x4E */
260#define HDA_RMX_CORBSIZE 19
261#define HDA_CORBSIZE_SZ_CAP 0xF0
262#define HDA_CORBSIZE_SZ 0x3
263/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
264
265#define HDA_REG_RIRBLBASE 22 /* 0x50 */
266#define HDA_RMX_RIRBLBASE 20
267
268#define HDA_REG_RIRBUBASE 23 /* 0x54 */
269#define HDA_RMX_RIRBUBASE 21
270
271#define HDA_REG_RIRBWP 24 /* 0x58 */
272#define HDA_RMX_RIRBWP 22
273#define HDA_RIRBWP_RST_SHIFT 15
274#define HDA_RIRBWP_WP_MASK 0xFF
275
276#define HDA_REG_RINTCNT 25 /* 0x5A */
277#define HDA_RMX_RINTCNT 23
278#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
279
280#define HDA_REG_RIRBCTL 26 /* 0x5C */
281#define HDA_RMX_RIRBCTL 24
282#define HDA_RIRBCTL_RIC_SHIFT 0
283#define HDA_RIRBCTL_DMA_SHIFT 1
284#define HDA_ROI_DMA_SHIFT 2
285
286#define HDA_REG_RIRBSTS 27 /* 0x5D */
287#define HDA_RMX_RIRBSTS 25
288#define HDA_RIRBSTS_RINTFL_SHIFT 0
289#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
290
291#define HDA_REG_RIRBSIZE 28 /* 0x5E */
292#define HDA_RMX_RIRBSIZE 26
293#define HDA_RIRBSIZE_SZ_CAP 0xF0
294#define HDA_RIRBSIZE_SZ 0x3
295
296#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
297#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
298
299
300#define HDA_REG_IC 29 /* 0x60 */
301#define HDA_RMX_IC 27
302
303#define HDA_REG_IR 30 /* 0x64 */
304#define HDA_RMX_IR 28
305
306#define HDA_REG_IRS 31 /* 0x68 */
307#define HDA_RMX_IRS 29
308#define HDA_IRS_ICB_SHIFT 0
309#define HDA_IRS_IRV_SHIFT 1
310
311#define HDA_REG_DPLBASE 32 /* 0x70 */
312#define HDA_RMX_DPLBASE 30
313#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
314
315#define HDA_REG_DPUBASE 33 /* 0x74 */
316#define HDA_RMX_DPUBASE 31
317#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
318
319#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
320
321#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
322#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
323/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
324#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
325
326#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
327
328/** @todo Condense marcos! */
329
330#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80 */
331#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
332#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
333#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
334#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
335#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
336#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
337#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
338#define HDA_RMX_SD0CTL 32
339#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
340#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
341#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
342#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
343#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
344#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
345#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
346
347#define SD(func, num) SD##num##func
348
349#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
350#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
351#define HDA_SDCTL_NUM_MASK 0xF
352#define HDA_SDCTL_NUM_SHIFT 20
353#define HDA_SDCTL_DIR_SHIFT 19
354#define HDA_SDCTL_TP_SHIFT 18
355#define HDA_SDCTL_STRIPE_MASK 0x3
356#define HDA_SDCTL_STRIPE_SHIFT 16
357#define HDA_SDCTL_DEIE_SHIFT 4
358#define HDA_SDCTL_FEIE_SHIFT 3
359#define HDA_SDCTL_ICE_SHIFT 2
360#define HDA_SDCTL_RUN_SHIFT 1
361#define HDA_SDCTL_SRST_SHIFT 0
362
363#define HDA_REG_SD0STS 35 /* 0x83 */
364#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
365#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
366#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
367#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
368#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
369#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
370#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
371#define HDA_RMX_SD0STS 33
372#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
373#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
374#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
375#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
376#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
377#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
378#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
379
380#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
381#define HDA_SDSTS_FIFORDY_SHIFT 5
382#define HDA_SDSTS_DE_SHIFT 4
383#define HDA_SDSTS_FE_SHIFT 3
384#define HDA_SDSTS_BCIS_SHIFT 2
385
386#define HDA_REG_SD0LPIB 36 /* 0x84 */
387#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
388#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
389#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
390#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
391#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
392#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
393#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
394#define HDA_RMX_SD0LPIB 34
395#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
396#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
397#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
398#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
399#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
400#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
401#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
402
403#define HDA_REG_SD0CBL 37 /* 0x88 */
404#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
405#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
406#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
407#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
408#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
409#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
410#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
411#define HDA_RMX_SD0CBL 35
412#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
413#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
414#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
415#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
416#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
417#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
418#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
419
420#define HDA_REG_SD0LVI 38 /* 0x8C */
421#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
422#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
423#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
424#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
425#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
426#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
427#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
428#define HDA_RMX_SD0LVI 36
429#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
430#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
431#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
432#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
433#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
434#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
435#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
436
437#define HDA_REG_SD0FIFOW 39 /* 0x8E */
438#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
439#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
440#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
441#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
442#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
443#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
444#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
445#define HDA_RMX_SD0FIFOW 37
446#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
447#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
448#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
449#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
450#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
451#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
452#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
453
454/*
455 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
456 */
457#define HDA_SDFIFOW_8B 0x2
458#define HDA_SDFIFOW_16B 0x3
459#define HDA_SDFIFOW_32B 0x4
460
461#define HDA_REG_SD0FIFOS 40 /* 0x90 */
462#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
463#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
464#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
465#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
466#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
467#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
468#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
469#define HDA_RMX_SD0FIFOS 38
470#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
471#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
472#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
473#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
474#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
475#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
476#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
477
478/*
479 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
480 * formula: size - 1
481 * Other values not listed are not supported.
482 */
483#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
484#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
485
486#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
487#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
488#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
489#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
490#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
491#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
492#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
493
494#define HDA_REG_SD0FMT 41 /* 0x92 */
495#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
496#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
497#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
498#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
499#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
500#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
501#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
502#define HDA_RMX_SD0FMT 39
503#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
504#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
505#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
506#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
507#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
508#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
509#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
510
511#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
512#define HDA_SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
513#define HDA_SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
514#define HDA_SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
515
516#define HDA_REG_SD0BDPL 42 /* 0x98 */
517#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
518#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
519#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
520#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
521#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
522#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
523#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
524#define HDA_RMX_SD0BDPL 40
525#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
526#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
527#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
528#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
529#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
530#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
531#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
532
533#define HDA_REG_SD0BDPU 43 /* 0x9C */
534#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
535#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
536#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
537#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
538#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
539#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
540#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
541#define HDA_RMX_SD0BDPU 41
542#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
543#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
544#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
545#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
546#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
547#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
548#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
549
550#define HDA_CODEC_CAD_SHIFT 28
551/* Encodes the (required) LUN into a codec command. */
552#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
553
554
555
556/*********************************************************************************************************************************
557* Structures and Typedefs *
558*********************************************************************************************************************************/
559
560/**
561 * Internal state of a Buffer Descriptor List Entry (BDLE),
562 * needed to keep track of the data needed for the actual device
563 * emulation.
564 */
565typedef struct HDABDLESTATE
566{
567 /** Own index within the BDL (Buffer Descriptor List). */
568 uint32_t u32BDLIndex;
569 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
570 * Used to check if we need fill up the FIFO again. */
571 uint32_t cbBelowFIFOW;
572 /** The buffer descriptor's internal DMA buffer. */
573 uint8_t au8FIFO[HDA_SDOFIFO_256B + 1];
574 /** Current offset in DMA buffer (in bytes).*/
575 uint32_t u32BufOff;
576 uint32_t Padding;
577} HDABDLESTATE, *PHDABDLESTATE;
578
579/**
580 * Buffer Descriptor List Entry (BDLE) (3.6.3).
581 *
582 * Contains only register values which do *not* change until a
583 * stream reset occurs.
584 */
585typedef struct HDABDLE
586{
587 /** Starting address of the actual buffer. Must be 128-bit aligned. */
588 uint64_t u64BufAdr;
589 /** Size of the actual buffer (in bytes). */
590 uint32_t u32BufSize;
591 /** Interrupt on completion; the controller will generate
592 * an interrupt when the last byte of the buffer has been
593 * fetched by the DMA engine. */
594 bool fIntOnCompletion;
595 /** Internal state of this BDLE.
596 * Not part of the actual BDLE registers. */
597 HDABDLESTATE State;
598} HDABDLE, *PHDABDLE;
599
600/**
601 * Structure for keeping an audio stream data mapping.
602 */
603typedef struct HDASTREAMMAPPING
604{
605 /** The stream's layout. */
606 PDMAUDIOSTREAMLAYOUT enmLayout;
607 /** Number of audio channels in this stream. */
608 uint8_t cChannels;
609 /** Array audio channels. */
610 R3PTRTYPE(PPDMAUDIOSTREAMCHANNEL) paChannels;
611 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
612} HDASTREAMMAPPING, *PHDASTREAMMAPPING;
613
614/**
615 * Internal state of a HDA stream.
616 */
617typedef struct HDASTREAMSTATE
618{
619 /** Current BDLE to use. Wraps around to 0 if
620 * maximum (cBDLE) is reached. */
621 uint16_t uCurBDLE;
622 /** Stop indicator. */
623 volatile bool fDoStop;
624 /** Flag indicating whether this stream is in an
625 * active (operative) state or not. */
626 volatile bool fActive;
627 /** Flag indicating whether this stream currently is
628 * in reset mode and therefore not acccessible by the guest. */
629 volatile bool fInReset;
630 /** Unused, padding. */
631 bool fPadding;
632 /** Critical section to serialize access. */
633 RTCRITSECT CritSect;
634 /** Event signalling that the stream's state has been changed. */
635 RTSEMEVENT hStateChangedEvent;
636 /** This stream's data mapping. */
637 HDASTREAMMAPPING Mapping;
638 /** Current BDLE (Buffer Descriptor List Entry). */
639 HDABDLE BDLE;
640} HDASTREAMSTATE, *PHDASTREAMSTATE;
641
642/**
643 * Structure defining an HDA mixer sink.
644 * Its purpose is to know which audio mixer sink is bound to
645 * which SDn (SDI/SDO) device stream.
646 *
647 * This is needed in order to handle interleaved streams
648 * (that is, multiple channels in one stream) or non-interleaved
649 * streams (each channel has a dedicated stream).
650 *
651 * This is only known to the actual device emulation level.
652 */
653typedef struct HDAMIXERSINK
654{
655 /** SDn ID this sink is assigned to. 0 if not assigned. */
656 uint8_t uSD;
657 /** Channel ID of SDn ID. Only valid if SDn ID is valid. */
658 uint8_t uChannel;
659 uint8_t Padding[3];
660 /** Pointer to the actual audio mixer sink. */
661 R3PTRTYPE(PAUDMIXSINK) pMixSink;
662} HDAMIXERSINK, *PHDAMIXERSINK;
663
664/**
665 * Structure for keeping a HDA stream state.
666 *
667 * Contains only register values which do *not* change until a
668 * stream reset occurs.
669 */
670typedef struct HDASTREAM
671{
672 /** Stream descriptor number (SDn). */
673 uint8_t u8SD;
674 uint8_t Padding0[7];
675 /** DMA base address (SDnBDPU - SDnBDPL). */
676 uint64_t u64BDLBase;
677 /** Cyclic Buffer Length (SDnCBL).
678 * Represents the size of the ring buffer. */
679 uint32_t u32CBL;
680 /** Format (SDnFMT). */
681 uint16_t u16FMT;
682 /** FIFO Size (FIFOS).
683 * Maximum number of bytes that may have been DMA'd into
684 * memory but not yet transmitted on the link.
685 *
686 * Must be a power of two. */
687 uint16_t u16FIFOS;
688 /** Last Valid Index (SDnLVI). */
689 uint16_t u16LVI;
690 uint16_t Padding1[3];
691 /** Pointer to HDA sink this stream is attached to. */
692 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
693 /** Internal state of this stream. */
694 HDASTREAMSTATE State;
695} HDASTREAM, *PHDASTREAM;
696
697/**
698 * Structure for mapping a stream tag to an HDA stream.
699 */
700typedef struct HDATAG
701{
702 /** Own stream tag. */
703 uint8_t uTag;
704 uint8_t Padding[7];
705 /** Pointer to associated stream. */
706 R3PTRTYPE(PHDASTREAM) pStrm;
707} HDATAG, *PHDATAG;
708
709/**
710 * Structure defining an HDA mixer stream.
711 * This is being used together with an audio mixer instance.
712 */
713typedef struct HDAMIXERSTREAM
714{
715 union
716 {
717 /** Desired playback destination (for an output stream). */
718 PDMAUDIOPLAYBACKDEST Dest;
719 /** Desired recording source (for an input stream). */
720 PDMAUDIORECSOURCE Source;
721 } DestSource;
722 uint8_t Padding1[4];
723 /** Associated mixer handle. */
724 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
725} HDAMIXERSTREAM, *PHDAMIXERSTREAM;
726
727/**
728 * Struct for maintaining a host backend driver.
729 * This driver must be associated to one, and only one,
730 * HDA codec. The HDA controller does the actual multiplexing
731 * of HDA codec data to various host backend drivers then.
732 *
733 * This HDA device uses a timer in order to synchronize all
734 * read/write accesses across all attached LUNs / backends.
735 */
736typedef struct HDADRIVER
737{
738 /** Node for storing this driver in our device driver list of HDASTATE. */
739 RTLISTNODER3 Node;
740 /** Pointer to HDA controller (state). */
741 R3PTRTYPE(PHDASTATE) pHDAState;
742 /** Driver flags. */
743 PDMAUDIODRVFLAGS Flags;
744 uint8_t u32Padding0[2];
745 /** LUN to which this driver has been assigned. */
746 uint8_t uLUN;
747 /** Whether this driver is in an attached state or not. */
748 bool fAttached;
749 /** Pointer to attached driver base interface. */
750 R3PTRTYPE(PPDMIBASE) pDrvBase;
751 /** Audio connector interface to the underlying host backend. */
752 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
753 /** Mixer stream for line input. */
754 HDAMIXERSTREAM LineIn;
755#ifdef VBOX_WITH_HDA_MIC_IN
756 /** Mixer stream for mic input. */
757 HDAMIXERSTREAM MicIn;
758#endif
759 /** Mixer stream for front output. */
760 HDAMIXERSTREAM Front;
761#ifdef VBOX_WITH_HDA_51_SURROUND
762 /** Mixer stream for center/LFE output. */
763 HDAMIXERSTREAM CenterLFE;
764 /** Mixer stream for rear output. */
765 HDAMIXERSTREAM Rear;
766#endif
767} HDADRIVER;
768
769/**
770 * ICH Intel HD Audio Controller state.
771 */
772typedef struct HDASTATE
773{
774 /** The PCI device structure. */
775 PCIDevice PciDev;
776 /** R3 Pointer to the device instance. */
777 PPDMDEVINSR3 pDevInsR3;
778 /** R0 Pointer to the device instance. */
779 PPDMDEVINSR0 pDevInsR0;
780 /** R0 Pointer to the device instance. */
781 PPDMDEVINSRC pDevInsRC;
782 /** Padding for alignment. */
783 uint32_t u32Padding;
784 /** The base interface for LUN\#0. */
785 PDMIBASE IBase;
786 RTGCPHYS MMIOBaseAddr;
787 /** The HDA's register set. */
788 uint32_t au32Regs[HDA_NUM_REGS];
789 /** Internal stream states. */
790 HDASTREAM aStreams[HDA_MAX_STREAMS];
791 /** Mapping table between stream tags and stream states. */
792 HDATAG aTags[HDA_MAX_TAGS];
793 /** CORB buffer base address. */
794 uint64_t u64CORBBase;
795 /** RIRB buffer base address. */
796 uint64_t u64RIRBBase;
797 /** DMA base address.
798 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
799 uint64_t u64DPBase;
800 /** DMA position buffer enable bit. */
801 bool fDMAPosition;
802 /** Padding for alignment. */
803 uint8_t u8Padding0[7];
804 /** Pointer to CORB buffer. */
805 R3PTRTYPE(uint32_t *) pu32CorbBuf;
806 /** Size in bytes of CORB buffer. */
807 uint32_t cbCorbBuf;
808 /** Padding for alignment. */
809 uint32_t u32Padding1;
810 /** Pointer to RIRB buffer. */
811 R3PTRTYPE(uint64_t *) pu64RirbBuf;
812 /** Size in bytes of RIRB buffer. */
813 uint32_t cbRirbBuf;
814 /** Indicates if HDA controller is in reset mode. */
815 bool fInReset;
816 /** Flag whether the R0 part is enabled. */
817 bool fR0Enabled;
818 /** Flag whether the RC part is enabled. */
819 bool fRCEnabled;
820 /** Number of active (running) SDn streams. */
821 uint8_t cStreamsActive;
822#ifndef VBOX_WITH_AUDIO_CALLBACKS
823 /** The timer for pumping data thru the attached LUN drivers. */
824 PTMTIMERR3 pTimer;
825 /** Flag indicating whether the timer is active or not. */
826 bool fTimerActive;
827 uint8_t u8Padding1[7];
828 /** Timer ticks per Hz. */
829 uint64_t cTimerTicks;
830 /** Timestamp of the last timer callback (hdaTimer).
831 * Used to calculate the time actually elapsed between two timer callbacks. */
832 uint64_t uTimerTS;
833#endif
834#ifdef VBOX_WITH_STATISTICS
835# ifndef VBOX_WITH_AUDIO_CALLBACKS
836 STAMPROFILE StatTimer;
837# endif
838 STAMCOUNTER StatBytesRead;
839 STAMCOUNTER StatBytesWritten;
840#endif
841 /** Pointer to HDA codec to use. */
842 R3PTRTYPE(PHDACODEC) pCodec;
843 /** List of associated LUN drivers (HDADRIVER). */
844 RTLISTANCHORR3 lstDrv;
845 /** The device' software mixer. */
846 R3PTRTYPE(PAUDIOMIXER) pMixer;
847 /** HDA sink for (front) output. */
848 HDAMIXERSINK SinkFront;
849#ifdef VBOX_WITH_HDA_51_SURROUND
850 /** HDA sink for center / LFE output. */
851 HDAMIXERSINK SinkCenterLFE;
852 /** HDA sink for rear output. */
853 HDAMIXERSINK SinkRear;
854#endif
855 /** HDA mixer sink for line input. */
856 HDAMIXERSINK SinkLineIn;
857#ifdef VBOX_WITH_HDA_MIC_IN
858 /** Audio mixer sink for microphone input. */
859 HDAMIXERSINK SinkMicIn;
860#endif
861 uint64_t u64BaseTS;
862 /** Response Interrupt Count (RINTCNT). */
863 uint8_t u8RespIntCnt;
864 /** Padding for alignment. */
865 uint8_t au8Padding2[7];
866} HDASTATE;
867/** Pointer to the ICH Intel HD Audio Controller state. */
868typedef HDASTATE *PHDASTATE;
869
870#ifdef VBOX_WITH_AUDIO_CALLBACKS
871typedef struct HDACALLBACKCTX
872{
873 PHDASTATE pThis;
874 PHDADRIVER pDriver;
875} HDACALLBACKCTX, *PHDACALLBACKCTX;
876#endif
877
878
879/*********************************************************************************************************************************
880* Internal Functions *
881*********************************************************************************************************************************/
882#ifndef VBOX_DEVICE_STRUCT_TESTCASE
883#ifdef IN_RING3
884static FNPDMDEVRESET hdaReset;
885#endif
886
887/** @name Register read/write stubs.
888 * @{
889 */
890static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
891static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
892/** @} */
893
894/** @name Global register set read/write functions.
895 * @{
896 */
897static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
898static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
899static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
900static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
901//static int hdaRegReadSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value); - unused
902//static int hdaRegWriteSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value); - unused
903//static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value); - implementation not found.
904static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
905static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
906static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
907static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
908static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
909static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
910static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
911static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
912static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
913static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
914/** @} */
915
916/** @name {IOB}SDn write functions.
917 * @{
918 */
919static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
920static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
921static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
922static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
923//static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value); - unused
924//static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value); - unused
925static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
926static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
927static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
928/** @} */
929
930/* Locking + logging. */
931#ifdef IN_RING3
932DECLINLINE(int) hdaRegWriteSDLock(PHDASTATE pThis, PHDASTREAM pStream, uint32_t iReg, uint32_t u32Value);
933DECLINLINE(void) hdaRegWriteSDUnlock(PHDASTREAM pStream);
934#endif
935
936/** @name Generic register read/write functions.
937 * @{
938 */
939static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
940static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
941static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
942#ifdef IN_RING3
943static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
944#endif
945static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
946static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
947static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
948static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
949/** @} */
950
951#ifdef IN_RING3
952static void hdaStreamDestroy(PHDASTREAM pStream);
953static int hdaStreamSetActive(PHDASTATE pThis, PHDASTREAM pStream, bool fActive);
954//static int hdaStreamStart(PHDASTREAM pStream); - unused
955static int hdaStreamStop(PHDASTREAM pStream);
956/*static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout); - currently unused */
957static int hdaTransfer(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToProcess, uint32_t *pcbProcessed);
958#endif
959
960#ifdef IN_RING3
961static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg);
962static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping);
963static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping);
964#endif
965
966#ifdef IN_RING3
967static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
968DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB);
969# ifdef LOG_ENABLED
970static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE);
971# endif
972#endif
973static int hdaProcessInterrupt(PHDASTATE pThis);
974
975/*
976 * Timer routines.
977 */
978#if !defined(VBOX_WITH_AUDIO_CALLBACKS) && defined(IN_RING3)
979static void hdaTimerMaybeStart(PHDASTATE pThis);
980static void hdaTimerMaybeStop(PHDASTATE pThis);
981#endif
982
983
984/*********************************************************************************************************************************
985* Global Variables *
986*********************************************************************************************************************************/
987
988/** Offset of the SD0 register map. */
989#define HDA_REG_DESC_SD0_BASE 0x80
990
991/** Turn a short global register name into an memory index and a stringized name. */
992#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
993
994/** Turns a short stream register name into an memory index and a stringized name. */
995#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
996
997/** Same as above for a register *not* stored in memory. */
998#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
999
1000/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
1001#define HDA_REG_MAP_STRM(offset, name) \
1002 /* offset size read mask write mask read callback write callback index + abbrev description */ \
1003 /* ------- ------- ---------- ---------- -------------- ----------------- ------------------------------ ----------- */ \
1004 /* Offset 0x80 (SD0) */ \
1005 { offset, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
1006 /* Offset 0x83 (SD0) */ \
1007 { offset + 0x3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
1008 /* Offset 0x84 (SD0) */ \
1009 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
1010 /* Offset 0x88 (SD0) */ \
1011 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
1012 /* Offset 0x8C (SD0) */ \
1013 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
1014 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
1015 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteU16, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
1016 /* Offset 0x90 (SD0) */ \
1017 { offset + 0x10, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16, hdaRegWriteU16, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
1018 /* Offset 0x92 (SD0) */ \
1019 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
1020 /* Reserved: 0x94 - 0x98. */ \
1021 /* Offset 0x98 (SD0) */ \
1022 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
1023 /* Offset 0x9C (SD0) */ \
1024 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
1025
1026/** Defines a single audio stream register set (e.g. OSD0). */
1027#define HDA_REG_MAP_DEF_STREAM(index, name) \
1028 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
1029
1030/* See 302349 p 6.2. */
1031static const struct HDAREGDESC
1032{
1033 /** Register offset in the register space. */
1034 uint32_t offset;
1035 /** Size in bytes. Registers of size > 4 are in fact tables. */
1036 uint32_t size;
1037 /** Readable bits. */
1038 uint32_t readable;
1039 /** Writable bits. */
1040 uint32_t writable;
1041 /** Read callback. */
1042 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
1043 /** Write callback. */
1044 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
1045 /** Index into the register storage array. */
1046 uint32_t mem_idx;
1047 /** Abbreviated name. */
1048 const char *abbrev;
1049 /** Descripton. */
1050 const char *desc;
1051} g_aHdaRegMap[HDA_NUM_REGS] =
1052
1053{
1054 /* offset size read mask write mask read callback write callback index + abbrev */
1055 /*------- ------- ---------- ---------- ----------------------- ---------------------- ---------------- */
1056 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
1057 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
1058 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
1059 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
1060 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
1061 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
1062 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
1063 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , HDA_REG_IDX(STATESTS) }, /* State Change Status */
1064 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
1065 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
1066 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
1067 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
1068 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
1069 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
1070 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
1071 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
1072 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
1073 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
1074 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
1075 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
1076 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
1077 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
1078 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
1079 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
1080 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
1081 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
1082 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
1083 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
1084 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
1085 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
1086 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
1087 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
1088 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
1089 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
1090 /* 4 Serial Data In (SDI). */
1091 HDA_REG_MAP_DEF_STREAM(0, SD0),
1092 HDA_REG_MAP_DEF_STREAM(1, SD1),
1093 HDA_REG_MAP_DEF_STREAM(2, SD2),
1094 HDA_REG_MAP_DEF_STREAM(3, SD3),
1095 /* 4 Serial Data Out (SDO). */
1096 HDA_REG_MAP_DEF_STREAM(4, SD4),
1097 HDA_REG_MAP_DEF_STREAM(5, SD5),
1098 HDA_REG_MAP_DEF_STREAM(6, SD6),
1099 HDA_REG_MAP_DEF_STREAM(7, SD7)
1100};
1101
1102/**
1103 * HDA register aliases (HDA spec 3.3.45).
1104 * @remarks Sorted by offReg.
1105 */
1106static const struct
1107{
1108 /** The alias register offset. */
1109 uint32_t offReg;
1110 /** The register index. */
1111 int idxAlias;
1112} g_aHdaRegAliases[] =
1113{
1114 { 0x2084, HDA_REG_SD0LPIB },
1115 { 0x20a4, HDA_REG_SD1LPIB },
1116 { 0x20c4, HDA_REG_SD2LPIB },
1117 { 0x20e4, HDA_REG_SD3LPIB },
1118 { 0x2104, HDA_REG_SD4LPIB },
1119 { 0x2124, HDA_REG_SD5LPIB },
1120 { 0x2144, HDA_REG_SD6LPIB },
1121 { 0x2164, HDA_REG_SD7LPIB },
1122};
1123
1124#ifdef IN_RING3
1125/** HDABDLE field descriptors for the v6+ saved state. */
1126static SSMFIELD const g_aSSMBDLEFields6[] =
1127{
1128 SSMFIELD_ENTRY(HDABDLE, u64BufAdr),
1129 SSMFIELD_ENTRY(HDABDLE, u32BufSize),
1130 SSMFIELD_ENTRY(HDABDLE, fIntOnCompletion),
1131 SSMFIELD_ENTRY_TERM()
1132};
1133
1134/** HDABDLESTATE field descriptors for the v6+ saved state. */
1135static SSMFIELD const g_aSSMBDLEStateFields6[] =
1136{
1137 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
1138 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
1139 SSMFIELD_ENTRY(HDABDLESTATE, au8FIFO),
1140 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
1141 SSMFIELD_ENTRY_TERM()
1142};
1143
1144/** HDASTREAMSTATE field descriptors for the v6+ saved state. */
1145static SSMFIELD const g_aSSMStreamStateFields6[] =
1146{
1147 SSMFIELD_ENTRY_OLD(cBDLE, 2),
1148 SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
1149 SSMFIELD_ENTRY(HDASTREAMSTATE, fDoStop),
1150 SSMFIELD_ENTRY(HDASTREAMSTATE, fActive),
1151 SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
1152 SSMFIELD_ENTRY_TERM()
1153};
1154#endif
1155
1156/**
1157 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1158 */
1159static uint32_t const g_afMasks[5] =
1160{
1161 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1162};
1163
1164#ifdef IN_RING3
1165DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB)
1166{
1167 AssertPtrReturn(pThis, 0);
1168 AssertPtrReturn(pStream, 0);
1169
1170 Assert(u32LPIB <= pStream->u32CBL);
1171
1172 LogFlowFunc(("[SD%RU8]: LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1173 pStream->u8SD, u32LPIB, pThis->fDMAPosition));
1174
1175 /* Update LPIB in any case. */
1176 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) = u32LPIB;
1177
1178 /* Do we need to tell the current DMA position? */
1179 if (pThis->fDMAPosition)
1180 {
1181 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1182 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStream->u8SD * 2 * sizeof(uint32_t)),
1183 (void *)&u32LPIB, sizeof(uint32_t));
1184 AssertRC(rc2);
1185 }
1186
1187 return u32LPIB;
1188}
1189#endif
1190
1191/**
1192 * Retrieves the number of bytes of a FIFOS register.
1193 *
1194 * @return Number of bytes of a given FIFOS register.
1195 */
1196DECLINLINE(uint16_t) hdaSDFIFOSToBytes(uint32_t u32RegFIFOS)
1197{
1198 uint16_t cb;
1199 switch (u32RegFIFOS)
1200 {
1201 /* Input */
1202 case HDA_SDIFIFO_120B: cb = 120; break;
1203 case HDA_SDIFIFO_160B: cb = 160; break;
1204
1205 /* Output */
1206 case HDA_SDOFIFO_16B: cb = 16; break;
1207 case HDA_SDOFIFO_32B: cb = 32; break;
1208 case HDA_SDOFIFO_64B: cb = 64; break;
1209 case HDA_SDOFIFO_128B: cb = 128; break;
1210 case HDA_SDOFIFO_192B: cb = 192; break;
1211 case HDA_SDOFIFO_256B: cb = 256; break;
1212 default:
1213 {
1214 cb = 0; /* Can happen on stream reset. */
1215 break;
1216 }
1217 }
1218
1219 return cb;
1220}
1221
1222/**
1223 * Retrieves the number of bytes of a FIFOW register.
1224 *
1225 * @return Number of bytes of a given FIFOW register.
1226 */
1227DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1228{
1229 uint32_t cb;
1230 switch (u32RegFIFOW)
1231 {
1232 case HDA_SDFIFOW_8B: cb = 8; break;
1233 case HDA_SDFIFOW_16B: cb = 16; break;
1234 case HDA_SDFIFOW_32B: cb = 32; break;
1235 default: cb = 0; break;
1236 }
1237
1238#ifdef RT_STRICT
1239 Assert(RT_IS_POWER_OF_TWO(cb));
1240#endif
1241 return cb;
1242}
1243
1244#ifdef IN_RING3
1245/**
1246 * Fetches the next BDLE to use for a stream.
1247 *
1248 * @return IPRT status code.
1249 */
1250DECLINLINE(int) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
1251{
1252 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1253 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1254
1255 NOREF(pThis);
1256
1257 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1258
1259 LogFlowFuncEnter();
1260
1261#ifdef DEBUG
1262 uint32_t uOldBDLE = pStream->State.uCurBDLE;
1263#endif
1264
1265 PHDABDLE pBDLE = &pStream->State.BDLE;
1266
1267 /*
1268 * Switch to the next BDLE entry and do a wrap around
1269 * if we reached the end of the Buffer Descriptor List (BDL).
1270 */
1271 pStream->State.uCurBDLE++;
1272 if (pStream->State.uCurBDLE == pStream->u16LVI + 1)
1273 {
1274 pStream->State.uCurBDLE = 0;
1275
1276 hdaStreamUpdateLPIB(pThis, pStream, 0);
1277 }
1278
1279 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1280
1281 /* Fetch the next BDLE entry. */
1282 int rc = hdaBDLEFetch(pThis, pBDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
1283
1284#ifdef DEBUG
1285 LogFlowFunc(("[SD%RU8]: uOldBDLE=%RU16, uCurBDLE=%RU16, LVI=%RU32, rc=%Rrc, %R[bdle]\n",
1286 pStream->u8SD, uOldBDLE, pStream->State.uCurBDLE, pStream->u16LVI, rc, pBDLE));
1287#endif
1288
1289 return rc;
1290}
1291#endif /* IN_RING3 */
1292
1293/**
1294 * Returns the audio direction of a specified stream descriptor.
1295 *
1296 * The register layout specifies that input streams (SDI) come first,
1297 * followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
1298 * is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
1299 *
1300 * Note: SDnFMT register does not provide that information, so we have to judge
1301 * for ourselves.
1302 *
1303 * @return Audio direction.
1304 */
1305DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
1306{
1307 AssertReturn(uSD <= HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
1308
1309 if (uSD < HDA_MAX_SDI)
1310 return PDMAUDIODIR_IN;
1311
1312 return PDMAUDIODIR_OUT;
1313}
1314
1315/**
1316 * Returns the HDA stream of specified stream descriptor number.
1317 *
1318 * @return Pointer to HDA stream, or NULL if none found.
1319 */
1320DECLINLINE(PHDASTREAM) hdaStreamFromSD(PHDASTATE pThis, uint8_t uSD)
1321{
1322 AssertPtrReturn(pThis, NULL);
1323 AssertReturn(uSD <= HDA_MAX_STREAMS, NULL);
1324
1325 if (uSD >= HDA_MAX_STREAMS)
1326 return NULL;
1327
1328 return &pThis->aStreams[uSD];
1329}
1330
1331/**
1332 * Returns the HDA stream of specified HDA sink.
1333 *
1334 * @return Pointer to HDA stream, or NULL if none found.
1335 */
1336DECLINLINE(PHDASTREAM) hdaGetStreamFromSink(PHDASTATE pThis, PHDAMIXERSINK pSink)
1337{
1338 AssertPtrReturn(pThis, NULL);
1339 AssertPtrReturn(pSink, NULL);
1340
1341 /** @todo Do something with the channel mapping here? */
1342 return hdaStreamFromSD(pThis, pSink->uSD);
1343}
1344
1345/**
1346 * Retrieves the minimum number of bytes accumulated/free in the
1347 * FIFO before the controller will start a fetch/eviction of data.
1348 *
1349 * Uses SDFIFOW (FIFO Watermark Register).
1350 *
1351 * @return Number of bytes accumulated/free in the FIFO.
1352 */
1353DECLINLINE(uint8_t) hdaStreamGetFIFOW(PHDASTATE pThis, PHDASTREAM pStream)
1354{
1355 AssertPtrReturn(pThis, 0);
1356 AssertPtrReturn(pStream, 0);
1357
1358#ifdef VBOX_HDA_WITH_FIFO
1359 return hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, pStream->u8SD));
1360#else
1361 return 0;
1362#endif
1363}
1364
1365static int hdaProcessInterrupt(PHDASTATE pThis)
1366{
1367#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1368 ( INTCTL_SX((pThis), num) \
1369 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1370
1371 int iLevel = 0;
1372
1373 /** @todo Optimize IRQ handling. */
1374
1375 if (/* Controller Interrupt Enable (CIE). */
1376 HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1377 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1378 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1379 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1380 {
1381 iLevel = 1;
1382 }
1383
1384 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1385 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 1)
1386 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 2)
1387 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 3)
1388 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4)
1389 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 5)
1390 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 6)
1391 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 7))
1392 {
1393 iLevel = 1;
1394 }
1395
1396 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1397 {
1398 Log3Func(("Level=%d\n", iLevel));
1399 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , iLevel);
1400 }
1401
1402#undef IS_INTERRUPT_OCCURED_AND_ENABLED
1403
1404 return VINF_SUCCESS;
1405}
1406
1407/**
1408 * Looks up a register at the exact offset given by @a offReg.
1409 *
1410 * @returns Register index on success, -1 if not found.
1411 * @param offReg The register offset.
1412 */
1413static int hdaRegLookup(uint32_t offReg)
1414{
1415 /*
1416 * Aliases.
1417 */
1418 if (offReg >= g_aHdaRegAliases[0].offReg)
1419 {
1420 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1421 if (offReg == g_aHdaRegAliases[i].offReg)
1422 return g_aHdaRegAliases[i].idxAlias;
1423 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1424 return -1;
1425 }
1426
1427 /*
1428 * Binary search the
1429 */
1430 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1431 int idxLow = 0;
1432 for (;;)
1433 {
1434 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1435 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1436 {
1437 if (idxLow == idxMiddle)
1438 break;
1439 idxEnd = idxMiddle;
1440 }
1441 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1442 {
1443 idxLow = idxMiddle + 1;
1444 if (idxLow >= idxEnd)
1445 break;
1446 }
1447 else
1448 return idxMiddle;
1449 }
1450
1451#ifdef RT_STRICT
1452 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1453 Assert(g_aHdaRegMap[i].offset != offReg);
1454#endif
1455 return -1;
1456}
1457
1458/**
1459 * Looks up a register covering the offset given by @a offReg.
1460 *
1461 * @returns Register index on success, -1 if not found.
1462 * @param offReg The register offset.
1463 */
1464static int hdaRegLookupWithin(uint32_t offReg)
1465{
1466 /*
1467 * Aliases.
1468 */
1469 if (offReg >= g_aHdaRegAliases[0].offReg)
1470 {
1471 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1472 {
1473 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1474 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1475 return g_aHdaRegAliases[i].idxAlias;
1476 }
1477 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1478 return -1;
1479 }
1480
1481 /*
1482 * Binary search the register map.
1483 */
1484 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1485 int idxLow = 0;
1486 for (;;)
1487 {
1488 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1489 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1490 {
1491 if (idxLow == idxMiddle)
1492 break;
1493 idxEnd = idxMiddle;
1494 }
1495 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1496 {
1497 idxLow = idxMiddle + 1;
1498 if (idxLow >= idxEnd)
1499 break;
1500 }
1501 else
1502 return idxMiddle;
1503 }
1504
1505#ifdef RT_STRICT
1506 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1507 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1508#endif
1509 return -1;
1510}
1511
1512#ifdef IN_RING3
1513static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1514{
1515 int rc = VINF_SUCCESS;
1516 if (fLocal)
1517 {
1518 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1519 Assert(pThis->u64CORBBase);
1520 AssertPtr(pThis->pu32CorbBuf);
1521 Assert(pThis->cbCorbBuf);
1522
1523 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1524 if (RT_FAILURE(rc))
1525 AssertRCReturn(rc, rc);
1526#ifdef DEBUG_CMD_BUFFER
1527 uint8_t i = 0;
1528 do
1529 {
1530 LogFunc(("CORB%02x: ", i));
1531 uint8_t j = 0;
1532 do
1533 {
1534 const char *pszPrefix;
1535 if ((i + j) == HDA_REG(pThis, CORBRP));
1536 pszPrefix = "[R]";
1537 else if ((i + j) == HDA_REG(pThis, CORBWP));
1538 pszPrefix = "[W]";
1539 else
1540 pszPrefix = " "; /* three spaces */
1541 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1542 j++;
1543 } while (j < 8);
1544 LogFunc(("\n"));
1545 i += 8;
1546 } while(i != 0);
1547#endif
1548 }
1549 else
1550 {
1551 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1552 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1553 if (RT_FAILURE(rc))
1554 AssertRCReturn(rc, rc);
1555#ifdef DEBUG_CMD_BUFFER
1556 uint8_t i = 0;
1557 do {
1558 LogFunc(("RIRB%02x: ", i));
1559 uint8_t j = 0;
1560 do {
1561 const char *prefix;
1562 if ((i + j) == HDA_REG(pThis, RIRBWP))
1563 prefix = "[W]";
1564 else
1565 prefix = " ";
1566 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1567 } while (++j < 8);
1568 LogFunc(("\n"));
1569 i += 8;
1570 } while (i != 0);
1571#endif
1572 }
1573 return rc;
1574}
1575
1576static int hdaCORBCmdProcess(PHDASTATE pThis)
1577{
1578 int rc = hdaCmdSync(pThis, true);
1579 if (RT_FAILURE(rc))
1580 AssertRCReturn(rc, rc);
1581
1582 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1583 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1584 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1585
1586 Assert((corbWp != corbRp));
1587 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1588
1589 while (corbRp != corbWp)
1590 {
1591 uint64_t uResp;
1592 uint32_t uCmd = pThis->pu32CorbBuf[++corbRp];
1593
1594 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
1595 if (RT_FAILURE(rc2))
1596 LogFunc(("Codec lookup failed with rc=%Rrc\n", rc2));
1597
1598 (rirbWp)++;
1599
1600 if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
1601 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1602 {
1603 LogFunc(("Unexpected unsolicited response\n"));
1604 HDA_REG(pThis, CORBRP) = corbRp;
1605 return rc;
1606 }
1607
1608 pThis->pu64RirbBuf[rirbWp] = uResp;
1609
1610 pThis->u8RespIntCnt++;
1611 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1612 break;
1613 }
1614
1615 HDA_REG(pThis, CORBRP) = corbRp;
1616 HDA_REG(pThis, RIRBWP) = rirbWp;
1617
1618 rc = hdaCmdSync(pThis, false);
1619
1620 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1621
1622 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1623 {
1624 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1625
1626 pThis->u8RespIntCnt = 0;
1627 rc = hdaProcessInterrupt(pThis);
1628 }
1629
1630 if (RT_FAILURE(rc))
1631 AssertRCReturn(rc, rc);
1632 return rc;
1633}
1634
1635static int hdaStreamCreate(PHDASTREAM pStream, uint8_t uSD)
1636{
1637 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1638 AssertReturn(uSD <= HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
1639
1640 int rc = RTSemEventCreate(&pStream->State.hStateChangedEvent);
1641 if (RT_SUCCESS(rc))
1642 rc = RTCritSectInit(&pStream->State.CritSect);
1643
1644 if (RT_SUCCESS(rc))
1645 {
1646 pStream->u8SD = uSD;
1647 pStream->pMixSink = NULL;
1648
1649 pStream->State.fActive = false;
1650 pStream->State.fInReset = false;
1651 pStream->State.fDoStop = false;
1652 }
1653
1654 LogFlowFunc(("uSD=%RU8\n", uSD));
1655 return rc;
1656}
1657
1658static void hdaStreamDestroy(PHDASTREAM pStream)
1659{
1660 AssertPtrReturnVoid(pStream);
1661
1662 LogFlowFunc(("[SD%RU8]: Destroying ...\n", pStream->u8SD));
1663
1664 int rc2 = hdaStreamStop(pStream);
1665 AssertRC(rc2);
1666
1667 hdaStreamMapDestroy(&pStream->State.Mapping);
1668
1669 rc2 = RTCritSectDelete(&pStream->State.CritSect);
1670 AssertRC(rc2);
1671
1672 if (pStream->State.hStateChangedEvent != NIL_RTSEMEVENT)
1673 {
1674 rc2 = RTSemEventDestroy(pStream->State.hStateChangedEvent);
1675 AssertRC(rc2);
1676 pStream->State.hStateChangedEvent = NIL_RTSEMEVENT;
1677 }
1678
1679 LogFlowFuncLeave();
1680}
1681
1682static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStream, uint8_t u8SD)
1683{
1684 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1685 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1686
1687 pStream->u8SD = u8SD;
1688 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1689 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1690 pStream->u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1691 pStream->u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1692 pStream->u16FIFOS = hdaSDFIFOSToBytes(HDA_STREAM_REG(pThis, FIFOS, pStream->u8SD));
1693
1694 RT_ZERO(pStream->State.BDLE);
1695 pStream->State.uCurBDLE = 0;
1696
1697 hdaStreamMapReset(&pStream->State.Mapping);
1698
1699 LogFlowFunc(("[SD%RU8]: DMA @ 0x%x (%RU32 bytes), LVI=%RU16, FIFOS=%RU16\n",
1700 pStream->u8SD, pStream->u64BDLBase, pStream->u32CBL, pStream->u16LVI, pStream->u16FIFOS));
1701
1702#ifdef DEBUG
1703 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1704 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1705 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1706 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1707
1708 LogFlowFunc(("\t-> DMA @ 0x%x, LVI=%RU16, CBL=%RU32\n", u64BaseDMA, u16LVI, u32CBL));
1709
1710 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
1711#endif
1712
1713 return VINF_SUCCESS;
1714}
1715
1716static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStream)
1717{
1718 AssertPtrReturnVoid(pThis);
1719 AssertPtrReturnVoid(pStream);
1720
1721 const uint8_t uSD = pStream->u8SD;
1722
1723#ifdef VBOX_STRICT
1724 AssertReleaseMsg(!RT_BOOL(HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
1725 ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
1726#endif
1727
1728 LogFunc(("[SD%RU8]: Reset\n", uSD));
1729
1730 /*
1731 * Set reset state.
1732 */
1733 Assert(ASMAtomicReadBool(&pStream->State.fInReset) == false); /* No nested calls. */
1734 ASMAtomicXchgBool(&pStream->State.fInReset, true);
1735
1736 /*
1737 * First, reset the internal stream state.
1738 */
1739 RT_ZERO(pStream->State.BDLE);
1740 pStream->State.uCurBDLE = 0;
1741
1742 /*
1743 * Second, initialize the registers.
1744 */
1745 HDA_STREAM_REG(pThis, STS, uSD) = HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1746 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1747 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1748 HDA_STREAM_REG(pThis, CTL, uSD) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1749 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39. */
1750 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
1751 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1752 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
1753 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
1754 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
1755 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
1756 HDA_STREAM_REG(pThis, FMT, uSD) = HDA_SDFMT_MAKE(HDA_SDFMT_TYPE_PCM, HDA_SDFMT_BASE_44KHZ,
1757 HDA_SDFMT_MULT_1X, HDA_SDFMT_DIV_1X, HDA_SDFMT_16_BIT,
1758 HDA_SDFMT_CHAN_STEREO);
1759 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
1760 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
1761
1762 int rc2 = hdaStreamInit(pThis, pStream, uSD);
1763 AssertRC(rc2);
1764
1765 /* Report that we're done resetting this stream. */
1766 HDA_STREAM_REG(pThis, CTL, uSD) = 0;
1767
1768 /* Exit reset state. */
1769 ASMAtomicXchgBool(&pStream->State.fInReset, false);
1770}
1771
1772#if 0 /* unused */
1773static bool hdaStreamIsActive(PHDASTATE pThis, PHDASTREAM pStream)
1774{
1775 AssertPtrReturn(pThis, false);
1776 AssertPtrReturn(pStream, false);
1777
1778 bool fActive = pStream->State.fActive;
1779
1780 LogFlowFunc(("SD=%RU8, fActive=%RTbool\n", pStream->u8SD, fActive));
1781 return fActive;
1782}
1783#endif
1784
1785static int hdaStreamSetActive(PHDASTATE pThis, PHDASTREAM pStream, bool fActive)
1786{
1787 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1788 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1789
1790 LogFlowFunc(("[SD%RU8]: fActive=%RTbool, pMixSink=%p\n", pStream->u8SD, fActive, pStream->pMixSink));
1791
1792 if (pStream->State.fActive == fActive) /* No change required? */
1793 {
1794 LogFlowFunc(("[SD%RU8]: No change\n", pStream->u8SD));
1795 return VINF_SUCCESS;
1796 }
1797
1798 int rc = VINF_SUCCESS;
1799
1800 if (pStream->pMixSink) /* Stream attached to a sink? */
1801 {
1802 AUDMIXSINKCMD enmCmd = fActive
1803 ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE;
1804
1805 /* First, enable or disable the stream and the stream's sink, if any. */
1806 if (pStream->pMixSink->pMixSink)
1807 rc = AudioMixerSinkCtl(pStream->pMixSink->pMixSink, enmCmd);
1808 }
1809 else
1810 rc = VINF_SUCCESS;
1811
1812 if (RT_FAILURE(rc))
1813 {
1814 LogFlowFunc(("Failed with rc=%Rrc\n", rc));
1815 return rc;
1816 }
1817
1818 pStream->State.fActive = fActive;
1819
1820 /* Second, see if we need to start or stop the timer. */
1821 if (!fActive)
1822 {
1823 if (pThis->cStreamsActive) /* Disable can be called mupltiple times. */
1824 pThis->cStreamsActive--;
1825
1826#ifndef VBOX_WITH_AUDIO_CALLBACKS
1827 hdaTimerMaybeStop(pThis);
1828#endif
1829 }
1830 else
1831 {
1832 pThis->cStreamsActive++;
1833#ifndef VBOX_WITH_AUDIO_CALLBACKS
1834 hdaTimerMaybeStart(pThis);
1835#endif
1836 }
1837
1838 LogFlowFunc(("u8Strm=%RU8, fActive=%RTbool, cStreamsActive=%RU8\n", pStream->u8SD, fActive, pThis->cStreamsActive));
1839 return VINF_SUCCESS;
1840}
1841
1842static void hdaStreamAssignToSink(PHDASTREAM pStream, PHDAMIXERSINK pMixSink)
1843{
1844 AssertPtrReturnVoid(pStream);
1845
1846 int rc2 = RTCritSectEnter(&pStream->State.CritSect);
1847 if (RT_SUCCESS(rc2))
1848 {
1849 pStream->pMixSink = pMixSink;
1850
1851 rc2 = RTCritSectLeave(&pStream->State.CritSect);
1852 AssertRC(rc2);
1853 }
1854}
1855
1856#if 0 /** @todo hdaStreamStart is unused */
1857static int hdaStreamStart(PHDASTREAM pStream)
1858{
1859 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1860
1861 ASMAtomicXchgBool(&pStream->State.fDoStop, false);
1862 ASMAtomicXchgBool(&pStream->State.fActive, true);
1863
1864 LogFlowFuncLeave();
1865 return VINF_SUCCESS;
1866}
1867#endif /* unused */
1868
1869static int hdaStreamStop(PHDASTREAM pStream)
1870{
1871 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1872
1873 /* Already in stopped state? */
1874 bool fActive = ASMAtomicReadBool(&pStream->State.fActive);
1875 if (!fActive)
1876 return VINF_SUCCESS;
1877
1878#if 0 /** @todo Does not work (yet), as EMT deadlocks then. */
1879 /*
1880 * Wait for the stream to stop.
1881 */
1882 ASMAtomicXchgBool(&pStream->State.fDoStop, true);
1883
1884 int rc = hdaStreamWaitForStateChange(pStream, 60 * 1000 /* ms timeout */);
1885 fActive = ASMAtomicReadBool(&pStream->State.fActive);
1886 if ( /* Waiting failed? */
1887 RT_FAILURE(rc)
1888 /* Stream is still active? */
1889 || fActive)
1890 {
1891 AssertRC(rc);
1892 LogRel(("HDA: Warning: Unable to stop stream %RU8 (state: %s), rc=%Rrc\n",
1893 pStream->u8Strm, fActive ? "active" : "stopped", rc));
1894 }
1895#else
1896 int rc = VINF_SUCCESS;
1897#endif
1898
1899 LogFlowFuncLeaveRC(rc);
1900 return rc;
1901}
1902
1903#if defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_HDA_51_SURROUND)
1904static int hdaStreamChannelExtract(PPDMAUDIOSTREAMCHANNEL pChan, const void *pvBuf, size_t cbBuf)
1905{
1906 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1907 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
1908 AssertReturn(cbBuf, VERR_INVALID_PARAMETER);
1909
1910 AssertRelease(pChan->cbOff <= cbBuf);
1911
1912 const uint8_t *pu8Buf = (const uint8_t *)pvBuf;
1913
1914 size_t cbSrc = cbBuf - pChan->cbOff;
1915 const uint8_t *pvSrc = &pu8Buf[pChan->cbOff];
1916
1917 size_t cbDst;
1918 uint8_t *pvDst;
1919 RTCircBufAcquireWriteBlock(pChan->Data.pCircBuf, cbBuf, (void **)&pvDst, &cbDst);
1920
1921 cbSrc = RT_MIN(cbSrc, cbDst);
1922
1923 while (cbSrc)
1924 {
1925 AssertBreak(cbDst >= cbSrc);
1926
1927 /* Enough data for at least one next frame? */
1928 if (cbSrc < pChan->cbFrame)
1929 break;
1930
1931 memcpy(pvDst, pvSrc, pChan->cbFrame);
1932
1933 /* Advance to next channel frame in stream. */
1934 pvSrc += pChan->cbStep;
1935 Assert(cbSrc >= pChan->cbStep);
1936 cbSrc -= pChan->cbStep;
1937
1938 /* Advance destination by one frame. */
1939 pvDst += pChan->cbFrame;
1940 Assert(cbDst >= pChan->cbFrame);
1941 cbDst -= pChan->cbFrame;
1942
1943 /* Adjust offset. */
1944 pChan->cbOff += pChan->cbFrame;
1945 }
1946
1947 RTCircBufReleaseWriteBlock(pChan->Data.pCircBuf, cbDst);
1948
1949 return VINF_SUCCESS;
1950}
1951#endif /* defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_HDA_51_SURROUND) */
1952
1953#if 0 /** @todo hdaStreamChannelAdvance is unused */
1954static int hdaStreamChannelAdvance(PPDMAUDIOSTREAMCHANNEL pChan, size_t cbAdv)
1955{
1956 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1957
1958 if (!cbAdv)
1959 return VINF_SUCCESS;
1960
1961 return VINF_SUCCESS;
1962}
1963#endif
1964
1965static int hdaStreamChannelDataInit(PPDMAUDIOSTREAMCHANNELDATA pChanData, uint32_t fFlags)
1966{
1967 int rc = RTCircBufCreate(&pChanData->pCircBuf, 256); /** @todo Make this configurable? */
1968 if (RT_SUCCESS(rc))
1969 {
1970 pChanData->fFlags = fFlags;
1971 }
1972
1973 return rc;
1974}
1975
1976/**
1977 * Frees a stream channel data block again.
1978 *
1979 * @param pChanData Pointer to channel data to free.
1980 */
1981static void hdaStreamChannelDataDestroy(PPDMAUDIOSTREAMCHANNELDATA pChanData)
1982{
1983 if (!pChanData)
1984 return;
1985
1986 if (pChanData->pCircBuf)
1987 {
1988 RTCircBufDestroy(pChanData->pCircBuf);
1989 pChanData->pCircBuf = NULL;
1990 }
1991
1992 pChanData->fFlags = PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE;
1993}
1994
1995#if defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_HDA_51_SURROUND)
1996
1997static int hdaStreamChannelAcquireData(PPDMAUDIOSTREAMCHANNELDATA pChanData, void *pvData, size_t *pcbData)
1998{
1999 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
2000 AssertPtrReturn(pvData, VERR_INVALID_POINTER);
2001 AssertPtrReturn(pcbData, VERR_INVALID_POINTER);
2002
2003 RTCircBufAcquireReadBlock(pChanData->pCircBuf, 256 /** @todo Make this configurarble? */, &pvData, &pChanData->cbAcq);
2004
2005 *pcbData = pChanData->cbAcq;
2006 return VINF_SUCCESS;
2007}
2008
2009static int hdaStreamChannelReleaseData(PPDMAUDIOSTREAMCHANNELDATA pChanData)
2010{
2011 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
2012 RTCircBufReleaseReadBlock(pChanData->pCircBuf, pChanData->cbAcq);
2013
2014 return VINF_SUCCESS;
2015}
2016
2017#endif /* defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_HDA_51_SURROUND) */
2018
2019# if 0 /* currently unused */
2020static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout)
2021{
2022 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
2023
2024 LogFlowFunc(("[SD%RU8]: msTimeout=%RU32\n", pStream->u8SD, msTimeout));
2025 return RTSemEventWait(pStream->State.hStateChangedEvent, msTimeout);
2026}
2027# endif /* currently unused */
2028
2029#endif /* IN_RING3 */
2030
2031/* Register access handlers. */
2032
2033static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2034{
2035 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg);
2036 *pu32Value = 0;
2037 return VINF_SUCCESS;
2038}
2039
2040static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2041{
2042 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2043 return VINF_SUCCESS;
2044}
2045
2046/* U8 */
2047static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2048{
2049 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
2050 return hdaRegReadU32(pThis, iReg, pu32Value);
2051}
2052
2053static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2054{
2055 Assert((u32Value & 0xffffff00) == 0);
2056 return hdaRegWriteU32(pThis, iReg, u32Value);
2057}
2058
2059/* U16 */
2060static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2061{
2062 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
2063 return hdaRegReadU32(pThis, iReg, pu32Value);
2064}
2065
2066static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2067{
2068 Assert((u32Value & 0xffff0000) == 0);
2069 return hdaRegWriteU32(pThis, iReg, u32Value);
2070}
2071
2072/* U24 */
2073static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2074{
2075 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
2076 return hdaRegReadU32(pThis, iReg, pu32Value);
2077}
2078
2079#ifdef IN_RING3
2080static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2081{
2082 Assert((u32Value & 0xff000000) == 0);
2083 return hdaRegWriteU32(pThis, iReg, u32Value);
2084}
2085#endif
2086
2087/* U32 */
2088static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2089{
2090 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2091
2092 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
2093 return VINF_SUCCESS;
2094}
2095
2096static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2097{
2098 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2099
2100 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
2101 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
2102 return VINF_SUCCESS;
2103}
2104
2105static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2106{
2107 RT_NOREF_PV(iReg);
2108
2109 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
2110 {
2111 /* Set the CRST bit to indicate that we're leaving reset mode. */
2112 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2113
2114 if (pThis->fInReset)
2115 {
2116 LogFunc(("Guest leaving HDA reset\n"));
2117 pThis->fInReset = false;
2118 }
2119 }
2120 else
2121 {
2122#ifdef IN_RING3
2123 /* Enter reset state. */
2124 LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
2125 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
2126 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
2127
2128 /* Clear the CRST bit to indicate that we're in reset state. */
2129 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2130 pThis->fInReset = true;
2131
2132 hdaReset(pThis->CTX_SUFF(pDevIns));
2133#else
2134 return VINF_IOM_R3_MMIO_WRITE;
2135#endif
2136 }
2137
2138 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
2139 {
2140 /* Flush: GSTS:1 set, see 6.2.6. */
2141 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
2142 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
2143 }
2144 return VINF_SUCCESS;
2145}
2146
2147static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2148{
2149 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2150
2151 uint32_t v = pThis->au32Regs[iRegMem];
2152 uint32_t nv = u32Value & HDA_STATES_SCSF;
2153 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
2154 return VINF_SUCCESS;
2155}
2156
2157static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2158{
2159 RT_NOREF_PV(iReg);
2160
2161 uint32_t v = 0;
2162 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
2163 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
2164 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
2165 || HDA_REG(pThis, STATESTS))
2166 {
2167 v |= RT_BIT(30); /* Touch CIS. */
2168 }
2169
2170#define HDA_MARK_STREAM(x) \
2171 if (/* Descriptor Error */ \
2172 (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
2173 /* FIFO Error */ \
2174 || (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
2175 /* Buffer Completion Interrupt Status */ \
2176 || (SDSTS((pThis), x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))) \
2177 { \
2178 Log3Func(("[SD%RU8] BCIS: Marked\n", x)); \
2179 v |= RT_BIT(x); \
2180 }
2181
2182 HDA_MARK_STREAM(0);
2183 HDA_MARK_STREAM(1);
2184 HDA_MARK_STREAM(2);
2185 HDA_MARK_STREAM(3);
2186 HDA_MARK_STREAM(4);
2187 HDA_MARK_STREAM(5);
2188 HDA_MARK_STREAM(6);
2189 HDA_MARK_STREAM(7);
2190
2191#undef HDA_MARK_STREAM
2192
2193 /* "OR" bit of all interrupt status bits. */
2194 v |= v ? RT_BIT(31) : 0;
2195
2196 *pu32Value = v;
2197 return VINF_SUCCESS;
2198}
2199
2200static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2201{
2202 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
2203 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
2204#ifdef LOG_ENABLED
2205 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
2206 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
2207#endif
2208
2209 *pu32Value = u32LPIB;
2210 return VINF_SUCCESS;
2211}
2212
2213static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2214{
2215 RT_NOREF_PV(iReg);
2216
2217 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2218 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
2219 - pThis->u64BaseTS, 24, 1000);
2220 LogFlowFunc(("%RU32\n", *pu32Value));
2221 return VINF_SUCCESS;
2222}
2223
2224#if 0 /** @todo hdaRegReadSSYNC & hdaRegWriteSSYNC are unused */
2225
2226static int hdaRegReadSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2227{
2228 RT_NOREF_PV(iReg);
2229
2230 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2231 *pu32Value = HDA_REG(pThis, SSYNC);
2232 LogFlowFunc(("%RU32\n", *pu32Value));
2233 return VINF_SUCCESS;
2234}
2235
2236static int hdaRegWriteSSYNC(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2237{
2238 LogFlowFunc(("%RU32\n", u32Value));
2239 return hdaRegWriteU32(pThis, iReg, u32Value);
2240}
2241
2242#endif /* unused */
2243
2244static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2245{
2246 RT_NOREF_PV(iReg);
2247
2248 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
2249 {
2250 HDA_REG(pThis, CORBRP) = 0;
2251 }
2252#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
2253 else
2254 return hdaRegWriteU8(pThis, iReg, u32Value);
2255#endif
2256 return VINF_SUCCESS;
2257}
2258
2259static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2260{
2261#ifdef IN_RING3
2262 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
2263 AssertRC(rc);
2264 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2265 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
2266 {
2267 return hdaCORBCmdProcess(pThis);
2268 }
2269 return rc;
2270#else
2271 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2272 return VINF_IOM_R3_MMIO_WRITE;
2273#endif
2274}
2275
2276static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2277{
2278 RT_NOREF_PV(iReg);
2279
2280 uint32_t v = HDA_REG(pThis, CORBSTS);
2281 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
2282 return VINF_SUCCESS;
2283}
2284
2285static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2286{
2287#ifdef IN_RING3
2288 int rc;
2289 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2290 if (RT_FAILURE(rc))
2291 AssertRCReturn(rc, rc);
2292 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
2293 return VINF_SUCCESS;
2294 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2295 return VINF_SUCCESS;
2296 rc = hdaCORBCmdProcess(pThis);
2297 return rc;
2298#else /* !IN_RING3 */
2299 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2300 return VINF_IOM_R3_MMIO_WRITE;
2301#endif /* IN_RING3 */
2302}
2303
2304static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2305{
2306#ifdef IN_RING3
2307 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2308 return VINF_SUCCESS;
2309
2310 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
2311 if (!pStream)
2312 {
2313 LogFunc(("[SD%RU8]: Warning: Changing SDCBL on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2314 return hdaRegWriteU32(pThis, iReg, u32Value);
2315 }
2316
2317 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2318 AssertRC(rc2);
2319
2320 pStream->u32CBL = u32Value;
2321
2322 /* Reset BDLE state. */
2323 RT_ZERO(pStream->State.BDLE);
2324 pStream->State.uCurBDLE = 0;
2325
2326 rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2327 AssertRC(rc2);
2328
2329 LogFlowFunc(("[SD%RU8]: CBL=%RU32\n", pStream->u8SD, u32Value));
2330 hdaRegWriteSDUnlock(pStream);
2331
2332 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2333#else /* !IN_RING3 */
2334 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2335 return VINF_IOM_R3_MMIO_WRITE;
2336#endif /* IN_RING3 */
2337}
2338
2339static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2340{
2341#ifdef IN_RING3
2342 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2343 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2344
2345 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2346 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2347
2348 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2349 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2350
2351 /* Get the stream descriptor. */
2352 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
2353
2354 /*
2355 * Extract the stream tag the guest wants to use for this specific
2356 * stream descriptor (SDn). This only can happen if the stream is in a non-running
2357 * state, so we're doing the lookup and assignment here.
2358 *
2359 * So depending on the guest OS, SD3 can use stream tag 4, for example.
2360 */
2361 uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
2362 if (uTag > HDA_MAX_TAGS)
2363 {
2364 LogFunc(("[SD%RU8]: Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
2365 return hdaRegWriteU24(pThis, iReg, u32Value);
2366 }
2367
2368 PHDATAG pTag = &pThis->aTags[uTag];
2369 AssertPtr(pTag);
2370
2371 LogFunc(("[SD%RU8]: Using stream tag=%RU8\n", uSD, uTag));
2372
2373 /* Assign new values. */
2374 pTag->uTag = uTag;
2375 pTag->pStrm = hdaStreamFromSD(pThis, uSD);
2376
2377 PHDASTREAM pStream = pTag->pStrm;
2378 AssertPtr(pStream);
2379
2380 /* Note: Do not use hdaRegWriteSDLock() here, as SDnCTL might change the RUN bit. */
2381 int rc2 = RTCritSectEnter(&pStream->State.CritSect);
2382 AssertRC(rc2);
2383
2384 LogFunc(("[SD%RU8]: fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
2385 uSD, fRun, fInRun, fReset, fInReset, u32Value));
2386
2387 if (fInReset)
2388 {
2389 Assert(!fReset);
2390 Assert(!fInRun && !fRun);
2391
2392 /* Report that we're done resetting this stream by clearing SRST. */
2393 HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
2394
2395 LogFunc(("[SD%RU8]: Guest initiated exit of stream reset\n", uSD));
2396 }
2397 else if (fReset)
2398 {
2399 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
2400 Assert(!fInRun && !fRun);
2401
2402 LogFunc(("[SD%RU8]: Guest initiated enter to stream reset\n", pStream->u8SD));
2403 hdaStreamReset(pThis, pStream);
2404 }
2405 else
2406 {
2407 /*
2408 * We enter here to change DMA states only.
2409 */
2410 if (fInRun != fRun)
2411 {
2412 Assert(!fReset && !fInReset);
2413 LogFunc(("[SD%RU8]: fRun=%RTbool\n", pStream->u8SD, fRun));
2414
2415 hdaStreamSetActive(pThis, pStream, fRun);
2416
2417 if (fRun)
2418 {
2419 /* (Re-)Fetch the current BDLE entry. */
2420 rc2 = hdaBDLEFetch(pThis, &pStream->State.BDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
2421 AssertRC(rc2);
2422 }
2423 }
2424
2425 if (!fInRun && !fRun)
2426 hdaStreamInit(pThis, pStream, pStream->u8SD);
2427 }
2428
2429 /* Make sure to handle interrupts here as well. */
2430 hdaProcessInterrupt(pThis);
2431
2432 rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
2433 AssertRC(rc2);
2434
2435 hdaRegWriteSDUnlock(pStream);
2436 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2437#else /* !IN_RING3 */
2438 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2439 return VINF_IOM_R3_MMIO_WRITE;
2440#endif /* IN_RING3 */
2441}
2442
2443static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2444{
2445 uint32_t v = HDA_REG_IND(pThis, iReg);
2446 /* Clear (zero) FIFOE and DESE bits when writing 1 to it. */
2447 v &= ~(u32Value & v);
2448
2449 HDA_REG_IND(pThis, iReg) = v;
2450
2451 hdaProcessInterrupt(pThis);
2452 return VINF_SUCCESS;
2453}
2454
2455static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2456{
2457#ifdef IN_RING3
2458 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2459 return VINF_SUCCESS;
2460
2461 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, LVI, iReg));
2462 if (!pStream)
2463 {
2464 LogFunc(("[SD%RU8]: Warning: Changing SDLVI on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2465 return hdaRegWriteU16(pThis, iReg, u32Value);
2466 }
2467
2468 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2469 AssertRC(rc2);
2470
2471 /** @todo Validate LVI. */
2472 pStream->u16LVI = u32Value;
2473
2474 /* Reset BDLE state. */
2475 RT_ZERO(pStream->State.BDLE);
2476 pStream->State.uCurBDLE = 0;
2477
2478 rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
2479 AssertRC(rc2);
2480
2481 LogFlowFunc(("[SD%RU8]: LVI=%RU32\n", pStream->u8SD, u32Value));
2482 hdaRegWriteSDUnlock(pStream);
2483
2484 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2485
2486#else /* !IN_RING3 */
2487 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2488 return VINF_IOM_R3_MMIO_WRITE;
2489#endif /* IN_RING3 */
2490}
2491
2492#if 0 /** @todo hdaRegWriteSDFIFOW & hdaRegWriteSDFIFOS are unused */
2493static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2494{
2495 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
2496 /** @todo Only allow updating FIFOS if RUN bit is 0? */
2497 uint32_t u32FIFOW = 0;
2498
2499 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
2500 {
2501 LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to stream #%RU8, ignoring\n", uSD));
2502 return VINF_SUCCESS;
2503 }
2504
2505 switch (u32Value)
2506 {
2507 case HDA_SDFIFOW_8B:
2508 case HDA_SDFIFOW_16B:
2509 case HDA_SDFIFOW_32B:
2510 u32FIFOW = u32Value;
2511 break;
2512 default:
2513 LogRel(("HDA: Warning: Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
2514 u32Value, uSD));
2515 u32FIFOW = HDA_SDFIFOW_32B;
2516 break;
2517 }
2518
2519 if (u32FIFOW)
2520 {
2521 LogFunc(("[SD%RU8]: Updating FIFOW to %RU32 bytes\n", uSD, hdaSDFIFOSToBytes(u32FIFOW)));
2522 /** @todo Update internal stream state with new FIFOS. */
2523
2524 return hdaRegWriteU16(pThis, iReg, u32FIFOW);
2525 }
2526
2527 return VINF_SUCCESS; /* Never reached. */
2528}
2529
2530/**
2531 * @note This method could be called for changing value on Output Streams
2532 * only (ICH6 datasheet 18.2.39).
2533 */
2534static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2535{
2536 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
2537 /** @todo Only allow updating FIFOS if RUN bit is 0? */
2538 uint32_t u32FIFOS = 0;
2539
2540 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
2541 {
2542 LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to stream #%RU8, ignoring\n", uSD));
2543 return VINF_SUCCESS;
2544 }
2545
2546 switch(u32Value)
2547 {
2548 case HDA_SDOFIFO_16B:
2549 case HDA_SDOFIFO_32B:
2550 case HDA_SDOFIFO_64B:
2551 case HDA_SDOFIFO_128B:
2552 case HDA_SDOFIFO_192B:
2553 u32FIFOS = u32Value;
2554 break;
2555
2556 case HDA_SDOFIFO_256B: /** @todo r=andy Investigate this. */
2557 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
2558 /* Fall through is intentional. */
2559 default:
2560 LogRel(("HDA: Warning: Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
2561 u32Value, uSD));
2562 u32FIFOS = HDA_SDOFIFO_192B;
2563 break;
2564 }
2565
2566 if (u32FIFOS)
2567 {
2568 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n",
2569 HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg), hdaSDFIFOSToBytes(u32FIFOS)));
2570 /** @todo Update internal stream state with new FIFOS. */
2571
2572 return hdaRegWriteU16(pThis, iReg, u32FIFOS);
2573 }
2574
2575 return VINF_SUCCESS;
2576}
2577
2578#endif /* unused */
2579
2580#ifdef IN_RING3
2581static int hdaSDFMTToStrmCfg(uint32_t u32SDFMT, PPDMAUDIOSTREAMCFG pStrmCfg)
2582{
2583 AssertPtrReturn(pStrmCfg, VERR_INVALID_POINTER);
2584
2585# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2586
2587 int rc = VINF_SUCCESS;
2588
2589 uint32_t u32Hz = EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BASE_RATE_MASK, HDA_SDFMT_BASE_RATE_SHIFT)
2590 ? 44100 : 48000;
2591 uint32_t u32HzMult = 1;
2592 uint32_t u32HzDiv = 1;
2593
2594 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2595 {
2596 case 0: u32HzMult = 1; break;
2597 case 1: u32HzMult = 2; break;
2598 case 2: u32HzMult = 3; break;
2599 case 3: u32HzMult = 4; break;
2600 default:
2601 LogFunc(("Unsupported multiplier %x\n",
2602 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2603 rc = VERR_NOT_SUPPORTED;
2604 break;
2605 }
2606 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2607 {
2608 case 0: u32HzDiv = 1; break;
2609 case 1: u32HzDiv = 2; break;
2610 case 2: u32HzDiv = 3; break;
2611 case 3: u32HzDiv = 4; break;
2612 case 4: u32HzDiv = 5; break;
2613 case 5: u32HzDiv = 6; break;
2614 case 6: u32HzDiv = 7; break;
2615 case 7: u32HzDiv = 8; break;
2616 default:
2617 LogFunc(("Unsupported divisor %x\n",
2618 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2619 rc = VERR_NOT_SUPPORTED;
2620 break;
2621 }
2622
2623 PDMAUDIOFMT enmFmt;
2624 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2625 {
2626 case 0:
2627 enmFmt = PDMAUDIOFMT_S8;
2628 break;
2629 case 1:
2630 enmFmt = PDMAUDIOFMT_S16;
2631 break;
2632 case 4:
2633 enmFmt = PDMAUDIOFMT_S32;
2634 break;
2635 default:
2636 AssertMsgFailed(("Unsupported bits per sample %x\n",
2637 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2638 enmFmt = PDMAUDIOFMT_INVALID;
2639 rc = VERR_NOT_SUPPORTED;
2640 break;
2641 }
2642
2643 if (RT_SUCCESS(rc))
2644 {
2645 pStrmCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2646 pStrmCfg->cChannels = (u32SDFMT & 0xf) + 1;
2647 pStrmCfg->enmFormat = enmFmt;
2648 pStrmCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2649 }
2650
2651# undef EXTRACT_VALUE
2652 return rc;
2653}
2654
2655static int hdaAddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2656{
2657 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2658 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2659
2660 AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
2661
2662 LogFlowFunc(("Stream=%s\n", pCfg->szName));
2663
2664 int rc = VINF_SUCCESS;
2665
2666 bool fUseFront = true; /* Always use front out by default. */
2667#ifdef VBOX_WITH_HDA_51_SURROUND
2668 bool fUseRear;
2669 bool fUseCenter;
2670 bool fUseLFE;
2671
2672 fUseRear = fUseCenter = fUseLFE = false;
2673
2674 /*
2675 * Use commonly used setups for speaker configurations.
2676 */
2677
2678 /** @todo Make the following configurable through mixer API and/or CFGM? */
2679 switch (pCfg->cChannels)
2680 {
2681 case 3: /* 2.1: Front (Stereo) + LFE. */
2682 {
2683 fUseLFE = true;
2684 break;
2685 }
2686
2687 case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
2688 {
2689 fUseRear = true;
2690 break;
2691 }
2692
2693 case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
2694 {
2695 fUseRear = true;
2696 fUseLFE = true;
2697 break;
2698 }
2699
2700 case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
2701 {
2702 fUseRear = true;
2703 fUseCenter = true;
2704 fUseLFE = true;
2705 break;
2706 }
2707
2708 default: /* Unknown; fall back to 2 front channels (stereo). */
2709 {
2710 rc = VERR_NOT_SUPPORTED;
2711 break;
2712 }
2713 }
2714#else /* !VBOX_WITH_HDA_51_SURROUND */
2715 /* Only support mono or stereo channels. */
2716 if ( pCfg->cChannels != 1 /* Mono */
2717 && pCfg->cChannels != 2 /* Stereo */)
2718 {
2719 rc = VERR_NOT_SUPPORTED;
2720 }
2721#endif
2722
2723 if (rc == VERR_NOT_SUPPORTED)
2724 {
2725 LogRel(("HDA: Unsupported channel count (%RU8), falling back to stereo channels\n", pCfg->cChannels));
2726 pCfg->cChannels = 2;
2727
2728 rc = VINF_SUCCESS;
2729 }
2730
2731 do
2732 {
2733 if (RT_FAILURE(rc))
2734 break;
2735
2736 if (fUseFront)
2737 {
2738 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
2739 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
2740 pCfg->cChannels = 2;
2741
2742 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT);
2743 if (RT_SUCCESS(rc))
2744 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
2745 }
2746
2747#ifdef VBOX_WITH_HDA_51_SURROUND
2748 if ( RT_SUCCESS(rc)
2749 && (fUseCenter || fUseLFE))
2750 {
2751 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
2752 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
2753 pCfg->cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
2754
2755 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE);
2756 if (RT_SUCCESS(rc))
2757 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
2758 }
2759
2760 if ( RT_SUCCESS(rc)
2761 && fUseRear)
2762 {
2763 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
2764 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
2765 pCfg->cChannels = 2;
2766
2767 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR);
2768 if (RT_SUCCESS(rc))
2769 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
2770 }
2771#endif /* VBOX_WITH_HDA_51_SURROUND */
2772
2773 } while (0);
2774
2775 LogFlowFuncLeaveRC(rc);
2776 return rc;
2777}
2778
2779static int hdaAddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2780{
2781 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2782 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2783
2784 AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
2785
2786 LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
2787
2788 int rc;
2789
2790 switch (pCfg->DestSource.Source)
2791 {
2792 case PDMAUDIORECSOURCE_LINE:
2793 {
2794 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN);
2795 if (RT_SUCCESS(rc))
2796 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
2797 break;
2798 }
2799#ifdef VBOX_WITH_HDA_MIC_IN
2800 case PDMAUDIORECSOURCE_MIC:
2801 {
2802 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN);
2803 if (RT_SUCCESS(rc))
2804 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
2805 break;
2806 }
2807#endif
2808 default:
2809 rc = VERR_NOT_SUPPORTED;
2810 break;
2811 }
2812
2813 LogFlowFuncLeaveRC(rc);
2814 return rc;
2815}
2816#endif /* IN_RING3 */
2817
2818static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2819{
2820#ifdef IN_RING3
2821 PDMAUDIOSTREAMCFG strmCfg;
2822 RT_ZERO(strmCfg);
2823
2824 int rc = hdaSDFMTToStrmCfg(u32Value, &strmCfg);
2825 if (RT_FAILURE(rc))
2826 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2827
2828 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg));
2829 if (!pStream)
2830 {
2831 LogFunc(("[SD%RU8]: Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2832 HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2833 return hdaRegWriteU16(pThis, iReg, u32Value);
2834 }
2835
2836 int rcSem = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2837 AssertRC(rcSem);
2838
2839 LogFunc(("[SD%RU8]: Hz=%RU32, Channels=%RU8, enmFmt=%RU32\n",
2840 pStream->u8SD, strmCfg.uHz, strmCfg.cChannels, strmCfg.enmFormat));
2841
2842 /* Set audio direction. */
2843 strmCfg.enmDir = hdaGetDirFromSD(pStream->u8SD);
2844 switch (strmCfg.enmDir)
2845 {
2846 case PDMAUDIODIR_IN:
2847# ifdef VBOX_WITH_HDA_MIC_IN
2848# error "Implement me!"
2849# else
2850 strmCfg.DestSource.Source = PDMAUDIORECSOURCE_LINE;
2851 RTStrCopy(strmCfg.szName, sizeof(strmCfg.szName), "Line In");
2852# endif
2853 break;
2854
2855 case PDMAUDIODIR_OUT:
2856 /* Destination(s) will be set in hdaAddStreamOut(),
2857 * based on the channels / stream layout. */
2858 break;
2859
2860 default:
2861 rc = VERR_NOT_SUPPORTED;
2862 break;
2863 }
2864
2865 /*
2866 * Initialize the stream mapping in any case, regardless if
2867 * we support surround audio or not. This is needed to handle
2868 * the supported channels within a single audio stream, e.g. mono/stereo.
2869 *
2870 * In other words, the stream mapping *always* knowns the real
2871 * number of channels in a single audio stream.
2872 */
2873 if (RT_SUCCESS(rc))
2874 {
2875 rc = hdaStreamMapInit(&pStream->State.Mapping, &strmCfg);
2876 AssertRC(rc);
2877 }
2878
2879 if (RT_SUCCESS(rc))
2880 {
2881 PHDADRIVER pDrv;
2882 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2883 {
2884 int rc2;
2885 switch (strmCfg.enmDir)
2886 {
2887 case PDMAUDIODIR_OUT:
2888 rc2 = hdaAddStreamOut(pThis, &strmCfg);
2889 break;
2890
2891 case PDMAUDIODIR_IN:
2892 rc2 = hdaAddStreamIn(pThis, &strmCfg);
2893 break;
2894
2895 default:
2896 rc2 = VERR_NOT_SUPPORTED;
2897 AssertFailed();
2898 break;
2899 }
2900
2901 if ( RT_FAILURE(rc2)
2902 && (pDrv->Flags & PDMAUDIODRVFLAGS_PRIMARY)) /* We only care about primary drivers here, the rest may fail. */
2903 {
2904 if (RT_SUCCESS(rc))
2905 rc = rc2;
2906 /* Keep going. */
2907 }
2908 }
2909
2910 /* If (re-)opening the stream by the codec above failed, don't write the new
2911 * format to the register so that the guest is aware it didn't work. */
2912 if (RT_SUCCESS(rc))
2913 {
2914 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2915 AssertRC(rc);
2916 }
2917 else
2918 LogFunc(("[SD%RU8]: (Re-)Opening stream failed with rc=%Rrc\n", pStream->u8SD, rc));
2919 }
2920
2921 if (RT_SUCCESS(rcSem))
2922 hdaRegWriteSDUnlock(pStream);
2923
2924 return VINF_SUCCESS; /* Never return failure. */
2925#else /* !IN_RING3 */
2926 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2927 return VINF_IOM_R3_MMIO_WRITE;
2928#endif
2929}
2930
2931/* Note: Will be called for both, BDPL and BDPU, registers. */
2932DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t u8Strm)
2933{
2934#ifdef IN_RING3
2935 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2936 return VINF_SUCCESS;
2937
2938 PHDASTREAM pStream = hdaStreamFromSD(pThis, u8Strm);
2939 if (!pStream)
2940 {
2941 LogFunc(("[SD%RU8]: Warning: Changing SDBPL/SDBPU on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2942 return hdaRegWriteU32(pThis, iReg, u32Value);
2943 }
2944
2945 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2946 AssertRC(rc2);
2947
2948 rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2949 AssertRC(rc2);
2950
2951 /* Update BDL base. */
2952 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2953 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2954 /* Reset BDLE state. */
2955 RT_ZERO(pStream->State.BDLE);
2956 pStream->State.uCurBDLE = 0;
2957
2958 LogFlowFunc(("[SD%RU8]: BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2959 hdaRegWriteSDUnlock(pStream);
2960
2961 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2962#else /* !IN_RING3 */
2963 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(u8Strm);
2964 return VINF_IOM_R3_MMIO_WRITE;
2965#endif /* IN_RING3 */
2966}
2967
2968static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2969{
2970 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2971}
2972
2973static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2974{
2975 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2976}
2977
2978#ifdef IN_RING3
2979/**
2980 * XXX
2981 *
2982 * @return VBox status code. ALL THE CALLERS IGNORES THIS. DUH.
2983 *
2984 * @param pThis Pointer to HDA state.
2985 * @param iReg Register to write (logging only).
2986 * @param u32Value Value to write (logging only).
2987 */
2988DECLINLINE(int) hdaRegWriteSDLock(PHDASTATE pThis, PHDASTREAM pStream, uint32_t iReg, uint32_t u32Value)
2989{
2990 RT_NOREF(pThis, iReg, u32Value);
2991 AssertPtr(pThis); /* don't bother returning errors */
2992 AssertPtr(pStream);
2993
2994# ifdef VBOX_STRICT
2995 /* Check if the SD's RUN bit is set. */
2996 uint32_t u32SDCTL = HDA_STREAM_REG(pThis, CTL, pStream->u8SD);
2997 bool fIsRunning = RT_BOOL(u32SDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2998 if (fIsRunning)
2999 {
3000 LogFunc(("[SD%RU8]: Warning: Cannot write to register 0x%x (0x%x) when RUN bit is set (%R[sdctl])\n",
3001 pStream->u8SD, iReg, u32Value, u32SDCTL));
3002# ifdef DEBUG_andy
3003 AssertFailed();
3004# endif
3005 return VERR_ACCESS_DENIED;
3006 }
3007# endif
3008
3009 return RTCritSectEnter(&pStream->State.CritSect);
3010}
3011
3012DECLINLINE(void) hdaRegWriteSDUnlock(PHDASTREAM pStream)
3013{
3014 AssertPtrReturnVoid(pStream);
3015
3016 int rc2 = RTCritSectLeave(&pStream->State.CritSect);
3017 AssertRC(rc2);
3018}
3019#endif /* IN_RING3 */
3020
3021static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
3022{
3023 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
3024 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
3025 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
3026 {
3027 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
3028 }
3029
3030 return hdaRegReadU32(pThis, iReg, pu32Value);
3031}
3032
3033static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3034{
3035 RT_NOREF_PV(iReg);
3036
3037 /*
3038 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
3039 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
3040 */
3041 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
3042 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
3043 {
3044#ifdef IN_RING3
3045 uint32_t uCmd = HDA_REG(pThis, IC);
3046
3047 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
3048 {
3049 /*
3050 * 3.4.3: Defines behavior of immediate Command status register.
3051 */
3052 LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
3053 return VINF_SUCCESS;
3054 }
3055
3056 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
3057
3058 uint64_t uResp;
3059 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
3060 HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
3061 if (RT_FAILURE(rc2))
3062 LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
3063
3064 HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
3065 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
3066 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
3067 return VINF_SUCCESS;
3068#else /* !IN_RING3 */
3069 return VINF_IOM_R3_MMIO_WRITE;
3070#endif /* !IN_RING3 */
3071 }
3072
3073 /*
3074 * Once the guest read the response, it should clean the IRV bit of the IRS register.
3075 */
3076 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
3077 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
3078 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
3079 return VINF_SUCCESS;
3080}
3081
3082static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3083{
3084 RT_NOREF_PV(iReg);
3085
3086 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
3087 HDA_REG(pThis, RIRBWP) = 0;
3088
3089 /* The remaining bits are O, see 6.2.22. */
3090 return VINF_SUCCESS;
3091}
3092
3093static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3094{
3095 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
3096 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
3097 if (RT_FAILURE(rc))
3098 AssertRCReturn(rc, rc);
3099
3100 switch(iReg)
3101 {
3102 case HDA_REG_CORBLBASE:
3103 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
3104 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
3105 break;
3106 case HDA_REG_CORBUBASE:
3107 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
3108 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3109 break;
3110 case HDA_REG_RIRBLBASE:
3111 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
3112 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
3113 break;
3114 case HDA_REG_RIRBUBASE:
3115 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
3116 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3117 break;
3118 case HDA_REG_DPLBASE:
3119 {
3120 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
3121 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
3122
3123 /* Also make sure to handle the DMA position enable bit. */
3124 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
3125 LogRel2(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
3126 break;
3127 }
3128 case HDA_REG_DPUBASE:
3129 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
3130 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3131 break;
3132 default:
3133 AssertMsgFailed(("Invalid index\n"));
3134 break;
3135 }
3136
3137 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
3138 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
3139 return rc;
3140}
3141
3142static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3143{
3144 RT_NOREF_PV(iReg);
3145
3146 uint8_t v = HDA_REG(pThis, RIRBSTS);
3147 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
3148
3149 return hdaProcessInterrupt(pThis);
3150}
3151
3152#ifdef IN_RING3
3153#ifdef LOG_ENABLED
3154static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE)
3155{
3156 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
3157 if (!u64BDLBase)
3158 return;
3159
3160 uint32_t cbBDLE = 0;
3161 for (uint16_t i = 0; i < cBDLE; i++)
3162 {
3163 uint8_t bdle[16]; /** @todo Use a define. */
3164 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BDLBase + i * 16, bdle, 16); /** @todo Use a define. */
3165
3166 uint64_t addr = *(uint64_t *)bdle;
3167 uint32_t len = *(uint32_t *)&bdle[8];
3168 uint32_t ioc = *(uint32_t *)&bdle[12];
3169
3170 LogFlowFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
3171 i, addr, len, RT_BOOL(ioc & 0x1)));
3172
3173 cbBDLE += len;
3174 }
3175
3176 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
3177
3178 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
3179 return;
3180
3181 LogFlowFunc(("DMA counters:\n"));
3182
3183 for (int i = 0; i < cBDLE; i++)
3184 {
3185 uint32_t uDMACnt;
3186 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
3187 &uDMACnt, sizeof(uDMACnt));
3188
3189 LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
3190 }
3191}
3192#endif
3193
3194/**
3195 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
3196 *
3197 * @param pThis Pointer to HDA state.
3198 * @param pBDLE Where to store the fetched result.
3199 * @param u64BaseDMA Address base of DMA engine to use.
3200 * @param u16Entry BDLE entry to fetch.
3201 */
3202static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
3203{
3204 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3205 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
3206 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
3207
3208 if (!u64BaseDMA)
3209 {
3210 LogRel2(("HDA: Unable to fetch BDLE #%RU16 - no base DMA address set (yet)\n", u16Entry));
3211 return VERR_NOT_FOUND;
3212 }
3213 /** @todo Compare u16Entry with LVI. */
3214
3215 uint8_t uBundleEntry[16]; /** @todo Define a BDLE length. */
3216 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * 16, /** @todo Define a BDLE length. */
3217 uBundleEntry, RT_ELEMENTS(uBundleEntry));
3218 if (RT_FAILURE(rc))
3219 return rc;
3220
3221 RT_BZERO(pBDLE, sizeof(HDABDLE));
3222
3223 pBDLE->State.u32BDLIndex = u16Entry;
3224 pBDLE->u64BufAdr = *(uint64_t *) uBundleEntry;
3225 pBDLE->u32BufSize = *(uint32_t *)&uBundleEntry[8];
3226 if (pBDLE->u32BufSize < sizeof(uint16_t)) /* Must be at least one word. */
3227 return VERR_INVALID_STATE;
3228
3229 pBDLE->fIntOnCompletion = (*(uint32_t *)&uBundleEntry[12]) & RT_BIT(0);
3230
3231 return VINF_SUCCESS;
3232}
3233
3234/**
3235 * Returns the number of outstanding stream data bytes which need to be processed
3236 * by the DMA engine assigned to this stream.
3237 *
3238 * @return Number of bytes for the DMA engine to process.
3239 */
3240DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax)
3241{
3242 AssertPtrReturn(pThis, 0);
3243 AssertPtrReturn(pStream, 0);
3244
3245 if (!cbMax)
3246 return 0;
3247
3248 PHDABDLE pBDLE = &pStream->State.BDLE;
3249
3250 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3251 Assert(u32LPIB <= pStream->u32CBL);
3252
3253 uint32_t cbFree = pStream->u32CBL - u32LPIB;
3254 if (cbFree)
3255 {
3256 /* Limit to the available free space of the current BDLE. */
3257 cbFree = RT_MIN(cbFree, pBDLE->u32BufSize - pBDLE->State.u32BufOff);
3258
3259 /* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
3260 cbFree = RT_MIN(cbFree, uint32_t(pStream->u16FIFOS));
3261
3262 /* Make sure we only transfer as many bytes as requested. */
3263 cbFree = RT_MIN(cbFree, cbMax);
3264
3265 if (pBDLE->State.cbBelowFIFOW)
3266 {
3267 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
3268 * No need to read data from DMA then. */
3269 if (cbFree > pBDLE->State.cbBelowFIFOW)
3270 {
3271 /* Subtract the amount of bytes that still would fit in the stream's FIFO
3272 * and therefore do not need to be processed by DMA. */
3273 cbFree -= pBDLE->State.cbBelowFIFOW;
3274 }
3275 }
3276 }
3277
3278 LogFlowFunc(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, FIFOS=%RU16, cbFree=%RU32, %R[bdle]\n", pStream->u8SD,
3279 pStream->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), pStream->u16FIFOS, cbFree, pBDLE));
3280 return cbFree;
3281}
3282
3283DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
3284{
3285 AssertPtrReturnVoid(pBDLE);
3286
3287 if (!cbData || !cbProcessed)
3288 return;
3289
3290 /* Fewer than cbBelowFIFOW bytes were copied.
3291 * Probably we need to move the buffer, but it is rather hard to imagine a situation
3292 * where it might happen. */
3293 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
3294 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
3295 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
3296
3297#if 0
3298 if ( pBDLE->State.cbBelowFIFOW
3299 && pBDLE->State.cbBelowFIFOW <= cbWritten)
3300 {
3301 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
3302 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->u32BufSize));
3303 }
3304#endif
3305
3306 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
3307 Assert(pBDLE->State.cbBelowFIFOW == 0);
3308
3309 /* We always increment the position of DMA buffer counter because we're always reading
3310 * into an intermediate buffer. */
3311 pBDLE->State.u32BufOff += cbData;
3312 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3313
3314 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
3315}
3316
3317#ifdef IN_RING3
3318/**
3319 * Initializes a stream mapping structure according to the given stream configuration.
3320 *
3321 * @return IPRT status code.
3322 * @param pMapping Pointer to mapping to initialize.
3323 * @param pCfg Pointer to stream configuration to use.
3324 */
3325static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg)
3326{
3327 AssertPtrReturn(pMapping, VERR_INVALID_POINTER);
3328 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3329
3330 AssertReturn(pCfg->cChannels, VERR_INVALID_PARAMETER);
3331
3332 hdaStreamMapReset(pMapping);
3333
3334 pMapping->paChannels = (PPDMAUDIOSTREAMCHANNEL)RTMemAlloc(sizeof(PDMAUDIOSTREAMCHANNEL) * pCfg->cChannels);
3335 if (!pMapping->paChannels)
3336 return VERR_NO_MEMORY;
3337
3338 PDMAUDIOPCMPROPS Props;
3339 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &Props);
3340 if (RT_FAILURE(rc))
3341 return rc;
3342
3343 Assert(RT_IS_POWER_OF_TWO(Props.cBits));
3344
3345 /** @todo We assume all channels in a stream have the same format. */
3346 PPDMAUDIOSTREAMCHANNEL pChan = pMapping->paChannels;
3347 for (uint8_t i = 0; i < pCfg->cChannels; i++)
3348 {
3349 pChan->uChannel = i;
3350 pChan->cbStep = (Props.cBits / 2);
3351 pChan->cbFrame = pChan->cbStep * pCfg->cChannels;
3352 pChan->cbFirst = i * pChan->cbStep;
3353 pChan->cbOff = pChan->cbFirst;
3354
3355 int rc2 = hdaStreamChannelDataInit(&pChan->Data, PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE);
3356 if (RT_SUCCESS(rc))
3357 rc = rc2;
3358
3359 if (RT_FAILURE(rc))
3360 break;
3361
3362 pChan++;
3363 }
3364
3365 if ( RT_SUCCESS(rc)
3366 /* Create circular buffer if not created yet. */
3367 && !pMapping->pCircBuf)
3368 {
3369 rc = RTCircBufCreate(&pMapping->pCircBuf, _4K); /** @todo Make size configurable? */
3370 }
3371
3372 if (RT_SUCCESS(rc))
3373 {
3374 pMapping->cChannels = pCfg->cChannels;
3375#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3376 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_INTERLEAVED;
3377#else
3378 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
3379#endif
3380 }
3381
3382 return rc;
3383}
3384
3385/**
3386 * Destroys a given stream mapping.
3387 *
3388 * @param pMapping Pointer to mapping to destroy.
3389 */
3390static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping)
3391{
3392 hdaStreamMapReset(pMapping);
3393
3394 if (pMapping->pCircBuf)
3395 {
3396 RTCircBufDestroy(pMapping->pCircBuf);
3397 pMapping->pCircBuf = NULL;
3398 }
3399}
3400
3401/**
3402 * Resets a given stream mapping.
3403 *
3404 * @param pMapping Pointer to mapping to reset.
3405 */
3406static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping)
3407{
3408 AssertPtrReturnVoid(pMapping);
3409
3410 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_UNKNOWN;
3411
3412 if (pMapping->cChannels)
3413 {
3414 for (uint8_t i = 0; i < pMapping->cChannels; i++)
3415 hdaStreamChannelDataDestroy(&pMapping->paChannels[i].Data);
3416
3417 AssertPtr(pMapping->paChannels);
3418 RTMemFree(pMapping->paChannels);
3419 pMapping->paChannels = NULL;
3420
3421 pMapping->cChannels = 0;
3422 }
3423}
3424#endif /* IN_RING3 */
3425
3426DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
3427{
3428 AssertPtrReturn(pThis, false);
3429 AssertPtrReturn(pStream, false);
3430
3431 PHDABDLE pBDLE = &pStream->State.BDLE;
3432 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3433
3434 /* Did we reach the CBL (Cyclic Buffer List) limit? */
3435 bool fCBLLimitReached = u32LPIB >= pStream->u32CBL;
3436
3437 /* Do we need to use the next BDLE entry? Either because we reached
3438 * the CBL limit or our internal DMA buffer is full. */
3439 bool fNeedsNextBDLE = ( fCBLLimitReached
3440 || (pBDLE->State.u32BufOff >= pBDLE->u32BufSize));
3441
3442 Assert(u32LPIB <= pStream->u32CBL);
3443 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3444
3445 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
3446 pStream->u8SD, u32LPIB, pStream->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
3447
3448 return fNeedsNextBDLE;
3449}
3450
3451DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbInc)
3452{
3453 AssertPtrReturnVoid(pThis);
3454 AssertPtrReturnVoid(pStream);
3455
3456 LogFlowFunc(("[SD%RU8]: cbInc=%RU32\n", pStream->u8SD, cbInc));
3457
3458 //Assert(cbInc <= pStream->u16FIFOS);
3459
3460 if (!cbInc) /* Nothing to do? Bail out early. */
3461 return;
3462
3463 PHDABDLE pBDLE = &pStream->State.BDLE;
3464
3465 /*
3466 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
3467 * doesn't fetch anything via DMA, so just update LPIB.
3468 * (ICH6 datasheet 18.2.38).
3469 */
3470 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
3471 {
3472 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3473
3474 AssertMsg(((u32LPIB + cbInc) <= pStream->u32CBL),
3475 ("[SD%RU8] Increment (%RU32) exceeds CBL (%RU32): LPIB (%RU32)\n",
3476 pStream->u8SD, cbInc, pStream->u32CBL, u32LPIB));
3477
3478 u32LPIB = RT_MIN(u32LPIB + cbInc, pStream->u32CBL);
3479
3480 LogFlowFunc(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
3481 pStream->u8SD,
3482 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) + cbInc,
3483 pStream->u32CBL));
3484
3485 hdaStreamUpdateLPIB(pThis, pStream, u32LPIB);
3486 }
3487}
3488
3489static bool hdaStreamTransferIsComplete(PHDASTATE pThis, PHDASTREAM pStream, bool *pfInterrupt)
3490{
3491 AssertPtrReturn(pThis, true);
3492 AssertPtrReturn(pStream, true);
3493
3494 bool fInterrupt = false;
3495 bool fIsComplete = false;
3496
3497 PHDABDLE pBDLE = &pStream->State.BDLE;
3498#ifdef LOG_ENABLED
3499 const uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3500#endif
3501
3502 /* Check if the current BDLE entry is complete (full). */
3503 if (pBDLE->State.u32BufOff >= pBDLE->u32BufSize)
3504 {
3505 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
3506
3507 if (/* IOC (Interrupt On Completion) bit set? */
3508 pBDLE->fIntOnCompletion
3509 /* All data put into the DMA FIFO? */
3510 && pBDLE->State.cbBelowFIFOW == 0
3511 )
3512 {
3513 LogFlowFunc(("[SD%RU8]: %R[bdle] => COMPLETE\n", pStream->u8SD, pBDLE));
3514
3515 /*
3516 * If the ICE (IOCE, "Interrupt On Completion Enable") bit of the SDCTL register is set
3517 * we need to generate an interrupt.
3518 */
3519 if (HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
3520 fInterrupt = true;
3521 }
3522
3523 fIsComplete = true;
3524 }
3525
3526 if (pfInterrupt)
3527 *pfInterrupt = fInterrupt;
3528
3529 LogFlowFunc(("[SD%RU8]: u32LPIB=%RU32, CBL=%RU32, fIsComplete=%RTbool, fInterrupt=%RTbool, %R[bdle]\n",
3530 pStream->u8SD, u32LPIB, pStream->u32CBL, fIsComplete, fInterrupt, pBDLE));
3531
3532 return fIsComplete;
3533}
3534
3535/**
3536 * hdaReadAudio - copies samples from audio backend to DMA.
3537 * Note: This function writes to the DMA buffer immediately,
3538 * but "reports bytes" when all conditions are met (FIFOW).
3539 */
3540static int hdaReadAudio(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToRead, uint32_t *pcbRead)
3541{
3542 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3543 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
3544 /* pcbRead is optional. */
3545
3546 int rc;
3547 uint32_t cbRead = 0;
3548
3549 do
3550 {
3551 PHDABDLE pBDLE = &pStream->State.BDLE;
3552
3553 if (!cbToRead)
3554 {
3555 rc = VINF_EOF;
3556 break;
3557 }
3558
3559 AssertPtr(pStream->pMixSink);
3560 AssertPtr(pStream->pMixSink->pMixSink);
3561 rc = AudioMixerSinkRead(pStream->pMixSink->pMixSink, AUDMIXOP_BLEND, pBDLE->State.au8FIFO, cbToRead, &cbRead);
3562 if (RT_FAILURE(rc))
3563 break;
3564
3565 if (!cbRead)
3566 {
3567 rc = VINF_EOF;
3568 break;
3569 }
3570
3571 /* Sanity checks. */
3572 Assert(cbRead <= cbToRead);
3573 Assert(cbRead <= sizeof(pBDLE->State.au8FIFO));
3574 Assert(cbRead <= pBDLE->u32BufSize - pBDLE->State.u32BufOff);
3575
3576 /*
3577 * Write to the BDLE's DMA buffer.
3578 */
3579 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
3580 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
3581 pBDLE->State.au8FIFO, cbRead);
3582 AssertRC(rc);
3583
3584 if (pBDLE->State.cbBelowFIFOW + cbRead > hdaStreamGetFIFOW(pThis, pStream))
3585 {
3586 Assert(pBDLE->State.u32BufOff + cbRead <= pBDLE->u32BufSize);
3587 pBDLE->State.u32BufOff += cbRead;
3588 pBDLE->State.cbBelowFIFOW = 0;
3589 //hdaBackendReadTransferReported(pBDLE, cbDMAData, cbRead, &cbRead, pcbAvail);
3590 }
3591 else
3592 {
3593 Assert(pBDLE->State.u32BufOff + cbRead <= pBDLE->u32BufSize);
3594 pBDLE->State.u32BufOff += cbRead;
3595 pBDLE->State.cbBelowFIFOW += cbRead;
3596 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStream));
3597 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbRead, pcbAvail);
3598
3599 rc = VERR_NO_DATA;
3600 }
3601
3602 } while (0);
3603
3604 if (RT_SUCCESS(rc))
3605 {
3606 if (pcbRead)
3607 *pcbRead = cbRead;
3608 }
3609
3610 if (RT_FAILURE(rc))
3611 LogFlowFunc(("Failed with %Rrc\n", rc));
3612
3613 return rc;
3614}
3615
3616static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToWrite, uint32_t *pcbWritten)
3617{
3618 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3619 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
3620 /* pcbWritten is optional. */
3621
3622 PHDABDLE pBDLE = &pStream->State.BDLE;
3623
3624 uint32_t cbWritten = 0;
3625
3626 /*
3627 * Copy from DMA to the corresponding stream buffer (if there are any bytes from the
3628 * previous unreported transfer we write at offset 'pBDLE->State.cbUnderFifoW').
3629 */
3630 int rc;
3631 if (!cbToWrite)
3632 {
3633 rc = VINF_EOF;
3634 }
3635 else
3636 {
3637 void *pvBuf = pBDLE->State.au8FIFO + pBDLE->State.cbBelowFIFOW;
3638 Assert(cbToWrite >= pBDLE->State.cbBelowFIFOW);
3639 uint32_t cbBuf = cbToWrite - pBDLE->State.cbBelowFIFOW;
3640
3641 /*
3642 * Read from the current BDLE's DMA buffer.
3643 */
3644 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3645 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
3646 pvBuf, cbBuf);
3647 AssertRC(rc);
3648
3649#ifdef HDA_DEBUG_DUMP_PCM_DATA
3650 RTFILE fh;
3651 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaWriteAudio-hda.pcm",
3652 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
3653 RTFileWrite(fh, pvBuf, cbBuf, NULL);
3654 RTFileClose(fh);
3655#endif
3656
3657#ifdef VBOX_WITH_STATISTICS
3658 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBuf);
3659#endif
3660 /*
3661 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
3662 */
3663 if (cbBuf >= hdaStreamGetFIFOW(pThis, pStream))
3664 {
3665#if defined(VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_HDA_51_SURROUND)
3666 PHDASTREAMMAPPING pMapping = &pStream->State.Mapping;
3667#endif
3668
3669 /** @todo Which channel is which? */
3670#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3671 PPDMAUDIOSTREAMCHANNEL pChanFront = &pMapping->paChannels[0];
3672#endif
3673#ifdef VBOX_WITH_HDA_51_SURROUND
3674 PPDMAUDIOSTREAMCHANNEL pChanCenterLFE = &pMapping->paChannels[2]; /** @todo FIX! */
3675 PPDMAUDIOSTREAMCHANNEL pChanRear = &pMapping->paChannels[4]; /** @todo FIX! */
3676#endif
3677 int rc2;
3678
3679 void *pvDataFront = NULL;
3680 size_t cbDataFront;
3681#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3682 rc2 = hdaStreamChannelExtract(pChanFront, pvBuf, cbBuf);
3683 AssertRC(rc2);
3684
3685 rc2 = hdaStreamChannelAcquireData(&pChanFront->Data, pvDataFront, &cbDataFront);
3686 AssertRC(rc2);
3687#else
3688 /* Use stuff in the whole FIFO to use for the channel data. */
3689 pvDataFront = pvBuf;
3690 cbDataFront = cbBuf;
3691#endif
3692#ifdef VBOX_WITH_HDA_51_SURROUND
3693 void *pvDataCenterLFE;
3694 size_t cbDataCenterLFE;
3695 rc2 = hdaStreamChannelExtract(pChanCenterLFE, pvBuf, cbBuf);
3696 AssertRC(rc2);
3697
3698 rc2 = hdaStreamChannelAcquireData(&pChanCenterLFE->Data, pvDataCenterLFE, &cbDataCenterLFE);
3699 AssertRC(rc2);
3700
3701 void *pvDataRear;
3702 size_t cbDataRear;
3703 rc2 = hdaStreamChannelExtract(pChanRear, pvBuf, cbBuf);
3704 AssertRC(rc2);
3705
3706 rc2 = hdaStreamChannelAcquireData(&pChanRear->Data, pvDataRear, &cbDataRear);
3707 AssertRC(rc2);
3708#endif
3709 /*
3710 * Write data to according mixer sinks.
3711 */
3712 rc2 = AudioMixerSinkWrite(pThis->SinkFront.pMixSink, AUDMIXOP_COPY, pvDataFront, (uint32_t)cbDataFront,
3713 NULL /* pcbWritten */);
3714 AssertRC(rc2);
3715#ifdef VBOX_WITH_HDA_51_SURROUND
3716 rc2 = AudioMixerSinkWrite(pThis->SinkCenterLFE, AUDMIXOP_COPY, pvDataCenterLFE, cbDataCenterLFE,
3717 NULL /* pcbWritten */);
3718 AssertRC(rc2);
3719 rc2 = AudioMixerSinkWrite(pThis->SinkRear, AUDMIXOP_COPY, pvDataRear, cbDataRear,
3720 NULL /* pcbWritten */);
3721 AssertRC(rc2);
3722#endif
3723
3724#ifdef VBOX_WITH_HDA_INTERLEAVING_STREAMS_SUPPORT
3725 hdaStreamChannelReleaseData(&pChanFront->Data);
3726#endif
3727#ifdef VBOX_WITH_HDA_51_SURROUND
3728 hdaStreamChannelReleaseData(&pChanCenterLFE->Data);
3729 hdaStreamChannelReleaseData(&pChanRear->Data);
3730#endif
3731
3732 /* Always report all data as being written;
3733 * backends who were not able to catch up have to deal with it themselves. */
3734 cbWritten = cbToWrite;
3735
3736 hdaBDLEUpdate(pBDLE, cbToWrite, cbWritten);
3737 }
3738 else
3739 {
3740 Assert(pBDLE->State.u32BufOff + cbWritten <= pBDLE->u32BufSize);
3741 pBDLE->State.u32BufOff += cbWritten;
3742 pBDLE->State.cbBelowFIFOW += cbWritten;
3743 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStream));
3744
3745 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
3746 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbAvail, NULL);
3747 rc = VINF_EOF;
3748 }
3749 }
3750
3751 //Assert(cbWritten <= pStream->u16FIFOS);
3752
3753 if (RT_SUCCESS(rc))
3754 {
3755 if (pcbWritten)
3756 *pcbWritten = cbWritten;
3757 }
3758
3759 if (RT_FAILURE(rc))
3760 LogFlowFunc(("Failed with %Rrc\n", rc));
3761
3762 return rc;
3763}
3764
3765/**
3766 * @interface_method_impl{HDACODEC,pfnReset}
3767 */
3768static DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
3769{
3770 PHDASTATE pThis = pCodec->pHDAState;
3771 NOREF(pThis);
3772 return VINF_SUCCESS;
3773}
3774
3775/**
3776 * Retrieves a corresponding sink for a given mixer control.
3777 * Returns NULL if no sink is found.
3778 *
3779 * @return PHDAMIXERSINK
3780 * @param pThis HDA state.
3781 * @param enmMixerCtl Mixer control to get the corresponding sink for.
3782 */
3783static PHDAMIXERSINK hdaMixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3784{
3785 PHDAMIXERSINK pSink;
3786
3787 switch (enmMixerCtl)
3788 {
3789 case PDMAUDIOMIXERCTL_VOLUME_MASTER:
3790 /* Fall through is intentional. */
3791 case PDMAUDIOMIXERCTL_FRONT:
3792 pSink = &pThis->SinkFront;
3793 break;
3794#ifdef VBOX_WITH_HDA_51_SURROUND
3795 case PDMAUDIOMIXERCTL_CENTER_LFE:
3796 pSink = &pThis->SinkCenterLFE;
3797 break;
3798 case PDMAUDIOMIXERCTL_REAR:
3799 pSink = &pThis->SinkRear;
3800 break;
3801#endif
3802 case PDMAUDIOMIXERCTL_LINE_IN:
3803 pSink = &pThis->SinkLineIn;
3804 break;
3805#ifdef VBOX_WITH_HDA_MIC_IN
3806 case PDMAUDIOMIXERCTL_MIC_IN:
3807 pSink = &pThis->SinkMicIn;
3808 break;
3809#endif
3810 default:
3811 pSink = NULL;
3812 AssertMsgFailed(("Unhandled mixer control\n"));
3813 break;
3814 }
3815
3816 return pSink;
3817}
3818
3819static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PHDAMIXERSINK pSink, PPDMAUDIOSTREAMCFG pCfg)
3820{
3821 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3822 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
3823 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3824
3825 LogFunc(("Sink=%s, Stream=%s\n", pSink->pMixSink->pszName, pCfg->szName));
3826
3827 /* Update the sink's format. */
3828 PDMAUDIOPCMPROPS PCMProps;
3829 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &PCMProps);
3830 if (RT_SUCCESS(rc))
3831 rc = AudioMixerSinkSetFormat(pSink->pMixSink, &PCMProps);
3832
3833 if (RT_FAILURE(rc))
3834 return rc;
3835
3836 PHDADRIVER pDrv;
3837 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3838 {
3839 int rc2 = VINF_SUCCESS;
3840 PHDAMIXERSTREAM pStream = NULL;
3841
3842 PPDMAUDIOSTREAMCFG pStreamCfg = (PPDMAUDIOSTREAMCFG)RTMemDup(pCfg, sizeof(PDMAUDIOSTREAMCFG));
3843 if (!pStreamCfg)
3844 {
3845 rc = VERR_NO_MEMORY;
3846 break;
3847 }
3848
3849 /* Include the driver's LUN in the stream name for easier identification. */
3850 RTStrPrintf(pStreamCfg->szName, RT_ELEMENTS(pStreamCfg->szName), "[LUN#%RU8] %s", pDrv->uLUN, pCfg->szName);
3851
3852 if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
3853 {
3854 LogFunc(("enmRecSource=%d\n", pStreamCfg->DestSource.Source));
3855
3856 switch (pStreamCfg->DestSource.Source)
3857 {
3858 case PDMAUDIORECSOURCE_LINE:
3859 pStream = &pDrv->LineIn;
3860 break;
3861#ifdef VBOX_WITH_HDA_MIC_IN
3862 case PDMAUDIORECSOURCE_MIC:
3863 pStream = &pDrv->MicIn;
3864 break;
3865#endif
3866 default:
3867 rc2 = VERR_NOT_SUPPORTED;
3868 break;
3869 }
3870 }
3871 else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
3872 {
3873 LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->DestSource.Dest));
3874
3875 switch (pStreamCfg->DestSource.Dest)
3876 {
3877 case PDMAUDIOPLAYBACKDEST_FRONT:
3878 pStream = &pDrv->Front;
3879 break;
3880#ifdef VBOX_WITH_HDA_51_SURROUND
3881 case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
3882 pStream = &pDrv->CenterLFE;
3883 break;
3884 case PDMAUDIOPLAYBACKDEST_REAR:
3885 pStream = &pDrv->Rear;
3886 break;
3887#endif
3888 default:
3889 rc2 = VERR_NOT_SUPPORTED;
3890 break;
3891 }
3892 }
3893 else
3894 rc2 = VERR_NOT_SUPPORTED;
3895
3896 if (RT_SUCCESS(rc2))
3897 {
3898 AssertPtr(pStream);
3899
3900 AudioMixerSinkRemoveStream(pSink->pMixSink, pStream->pMixStrm);
3901
3902 AudioMixerStreamDestroy(pStream->pMixStrm);
3903 pStream->pMixStrm = NULL;
3904
3905 PAUDMIXSTREAM pMixStrm;
3906 rc2 = AudioMixerSinkCreateStream(pSink->pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
3907 if (RT_SUCCESS(rc2))
3908 {
3909 rc2 = AudioMixerSinkAddStream(pSink->pMixSink, pMixStrm);
3910 LogFlowFunc(("LUN#%RU8: Added \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName , rc2));
3911 }
3912
3913 if (RT_SUCCESS(rc2))
3914 pStream->pMixStrm = pMixStrm;
3915 }
3916
3917 if (RT_SUCCESS(rc))
3918 rc = rc2;
3919
3920 if (pStreamCfg)
3921 {
3922 RTMemFree(pStreamCfg);
3923 pStreamCfg = NULL;
3924 }
3925 }
3926
3927 LogFlowFuncLeaveRC(rc);
3928 return rc;
3929}
3930
3931/**
3932 * Adds a new audio stream to a specific mixer control.
3933 * Depending on the mixer control the stream then gets assigned to one of the internal
3934 * mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
3935 *
3936 * @return IPRT status code.
3937 * @param pThis HDA state.
3938 * @param enmMixerCtl Mixer control to assign new stream to.
3939 * @param pCfg Stream configuration for the new stream.
3940 */
3941static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
3942{
3943 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3944 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3945
3946 int rc;
3947
3948 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3949 if (pSink)
3950 {
3951 rc = hdaMixerAddStream(pThis, pSink, pCfg);
3952
3953 AssertPtr(pSink->pMixSink);
3954 LogFlowFunc(("Sink=%s, enmMixerCtl=%d\n", pSink->pMixSink->pszName, enmMixerCtl));
3955 }
3956 else
3957 rc = VERR_NOT_FOUND;
3958
3959 LogFlowFuncLeaveRC(rc);
3960 return rc;
3961}
3962
3963/**
3964 * Removes a specified mixer control from the HDA's mixer.
3965 *
3966 * @return IPRT status code.
3967 * @param pThis HDA state.
3968 * @param enmMixerCtl Mixer control to remove.
3969 */
3970static DECLCALLBACK(int) hdaMixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3971{
3972 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3973
3974 int rc;
3975
3976 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3977 if (pSink)
3978 {
3979 PHDADRIVER pDrv;
3980 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3981 {
3982 PAUDMIXSTREAM pMixStream = NULL;
3983 switch (enmMixerCtl)
3984 {
3985 /*
3986 * Input.
3987 */
3988 case PDMAUDIOMIXERCTL_LINE_IN:
3989 pMixStream = pDrv->LineIn.pMixStrm;
3990 pDrv->LineIn.pMixStrm = NULL;
3991 break;
3992#ifdef VBOX_WITH_HDA_MIC_IN
3993 case PDMAUDIOMIXERCTL_MIC_IN:
3994 pMixStream = pDrv->MicIn.pMixStrm;
3995 pDrv->MicIn.pMixStrm = NULL;
3996 break;
3997#endif
3998 /*
3999 * Output.
4000 */
4001 case PDMAUDIOMIXERCTL_FRONT:
4002 pMixStream = pDrv->Front.pMixStrm;
4003 pDrv->Front.pMixStrm = NULL;
4004 break;
4005#ifdef VBOX_WITH_HDA_51_SURROUND
4006 case PDMAUDIOMIXERCTL_CENTER_LFE:
4007 pMixStream = pDrv->CenterLFE.pMixStrm;
4008 pDrv->CenterLFE.pMixStrm = NULL;
4009 break;
4010 case PDMAUDIOMIXERCTL_REAR:
4011 pMixStream = pDrv->Rear.pMixStrm;
4012 pDrv->Rear.pMixStrm = NULL;
4013 break;
4014#endif
4015 default:
4016 AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
4017 break;
4018 }
4019
4020 if (pMixStream)
4021 {
4022 AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
4023 AudioMixerStreamDestroy(pMixStream);
4024
4025 pMixStream = NULL;
4026 }
4027 }
4028
4029 AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
4030 rc = VINF_SUCCESS;
4031 }
4032 else
4033 rc = VERR_NOT_FOUND;
4034
4035 LogFlowFunc(("enmMixerCtl=%d, rc=%Rrc\n", enmMixerCtl, rc));
4036 return rc;
4037}
4038
4039/**
4040 * Sets a SDn stream number and channel to a particular mixer control.
4041 *
4042 * @returns IPRT status code.
4043 * @param pThis HDA State.
4044 * @param enmMixerCtl Mixer control to set SD stream number and channel for.
4045 * @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
4046 * @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
4047 */
4048static DECLCALLBACK(int) hdaMixerSetStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
4049{
4050 LogFlowFunc(("enmMixerCtl=%RU32, uSD=%RU8, uChannel=%RU8\n", enmMixerCtl, uSD, uChannel));
4051
4052 if (uSD == 0) /* Stream number 0 is reserved. */
4053 {
4054 LogFlowFunc(("Invalid SDn (%RU8) number for mixer control %d, ignoring\n", uSD, enmMixerCtl));
4055 return VINF_SUCCESS;
4056 }
4057 /* uChannel is optional. */
4058
4059 /* SDn0 starts as 1. */
4060 Assert(uSD);
4061 uSD--;
4062
4063 int rc;
4064
4065 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
4066 if (pSink)
4067 {
4068 if ( (uSD < HDA_MAX_SDI)
4069 && AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
4070 {
4071 uSD += HDA_MAX_SDI;
4072 }
4073
4074 LogFlowFunc(("%s: Setting to stream ID=%RU8, channel=%RU8, enmMixerCtl=%RU32\n",
4075 pSink->pMixSink->pszName, uSD, uChannel, enmMixerCtl));
4076
4077 Assert(uSD < HDA_MAX_STREAMS);
4078
4079 PHDASTREAM pStream = hdaStreamFromSD(pThis, uSD);
4080 if (pStream)
4081 {
4082 pSink->uSD = uSD;
4083 pSink->uChannel = uChannel;
4084
4085 /* Make sure that the stream also has this sink set. */
4086 hdaStreamAssignToSink(pStream, pSink);
4087
4088 rc = VINF_SUCCESS;
4089 }
4090 else
4091 {
4092 LogRel(("HDA: Guest wanted to assign invalid stream ID=%RU8 (channel %RU8) to mixer control %RU32, skipping\n",
4093 uSD, uChannel, enmMixerCtl));
4094 rc = VERR_INVALID_PARAMETER;
4095 }
4096 }
4097 else
4098 rc = VERR_NOT_FOUND;
4099
4100 LogFlowFuncLeaveRC(rc);
4101 return rc;
4102}
4103
4104/**
4105 * Sets the volume of a specified mixer control.
4106 *
4107 * @return IPRT status code.
4108 * @param pThis HDA State.
4109 * @param enmMixerCtl Mixer control to set volume for.
4110 * @param pVol Pointer to volume data to set.
4111 */
4112static DECLCALLBACK(int) hdaMixerSetVolume(PHDASTATE pThis,
4113 PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
4114{
4115 int rc;
4116
4117 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
4118 if (pSink)
4119 {
4120 /* Set the volume.
4121 * We assume that the codec already converted it to the correct range. */
4122 rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
4123 }
4124 else
4125 rc = VERR_NOT_FOUND;
4126
4127 LogFlowFuncLeaveRC(rc);
4128 return rc;
4129}
4130
4131#ifndef VBOX_WITH_AUDIO_CALLBACKS
4132
4133static void hdaTimerMaybeStart(PHDASTATE pThis)
4134{
4135 if (pThis->cStreamsActive == 0) /* Only start the timer if there are no active streams. */
4136 return;
4137
4138 if (!pThis->pTimer)
4139 return;
4140
4141 LogFlowFuncEnter();
4142
4143 LogFlowFunc(("Starting timer\n"));
4144
4145 /* Set timer flag. */
4146 ASMAtomicXchgBool(&pThis->fTimerActive, true);
4147
4148 /* Update current time timestamp. */
4149 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
4150
4151 /* Fire off timer. */
4152 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
4153}
4154
4155static void hdaTimerMaybeStop(PHDASTATE pThis)
4156{
4157 if (pThis->cStreamsActive) /* Some streams still active? Bail out. */
4158 return;
4159
4160 if (!pThis->pTimer)
4161 return;
4162
4163 LogFlowFunc(("Stopping timer\n"));
4164
4165 /* Set timer flag. */
4166 ASMAtomicXchgBool(&pThis->fTimerActive, false);
4167}
4168
4169static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
4170{
4171 RT_NOREF(pDevIns);
4172 PHDASTATE pThis = (PHDASTATE)pvUser;
4173 Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
4174 AssertPtr(pThis);
4175
4176 STAM_PROFILE_START(&pThis->StatTimer, a);
4177
4178 uint64_t cTicksNow = TMTimerGet(pTimer);
4179
4180 LogFlowFuncEnter();
4181
4182 /* Update current time timestamp. */
4183 pThis->uTimerTS = cTicksNow;
4184
4185 /* Flag indicating whether to kick the timer again for a
4186 * new data processing round. */
4187 bool fKickTimer = false;
4188
4189 PHDASTREAM pStreamLineIn = hdaGetStreamFromSink(pThis, &pThis->SinkLineIn);
4190#ifdef VBOX_WITH_HDA_MIC_IN
4191 PHDASTREAM pStreamMicIn = hdaGetStreamFromSink(pThis, &pThis->SinkMicIn);
4192#endif
4193 PHDASTREAM pStreamFront = hdaGetStreamFromSink(pThis, &pThis->SinkFront);
4194#ifdef VBOX_WITH_HDA_51_SURROUND
4195 /** @todo See note below. */
4196#endif
4197
4198 uint32_t cbToProcess;
4199 int rc = AudioMixerSinkUpdate(pThis->SinkLineIn.pMixSink);
4200 if (RT_SUCCESS(rc))
4201 {
4202 cbToProcess = AudioMixerSinkGetReadable(pThis->SinkLineIn.pMixSink);
4203 if (cbToProcess)
4204 {
4205 rc = hdaTransfer(pThis, pStreamLineIn, cbToProcess, NULL /* pcbProcessed */);
4206 fKickTimer |= RT_SUCCESS(rc);
4207 }
4208 }
4209
4210#ifdef VBOX_WITH_HDA_MIC_IN
4211 rc = AudioMixerSinkUpdate(pThis->SinkMicIn.pMixSink);
4212 if (RT_SUCCESS(rc))
4213 {
4214 cbToProcess = AudioMixerSinkGetReadable(pThis->SinkMicIn.pMixSink);
4215 if (cbToProcess)
4216 {
4217 rc = hdaTransfer(pThis, pStreamMicIn, cbToProcess, NULL /* pcbProcessed */);
4218 fKickTimer |= RT_SUCCESS(rc);
4219 }
4220 }
4221#endif
4222
4223#ifdef VBOX_WITH_HDA_51_SURROUND
4224 rc = AudioMixerSinkUpdate(pThis->SinkCenterLFE.pMixSink);
4225 if (RT_SUCCESS(rc))
4226 {
4227
4228 }
4229
4230 rc = AudioMixerSinkUpdate(pThis->SinkRear.pMixSink);
4231 if (RT_SUCCESS(rc))
4232 {
4233
4234 }
4235 /** @todo Check for stream interleaving and only call hdaTransfer() if required! */
4236
4237 /*
4238 * Only call hdaTransfer if CenterLFE and/or Rear are on different SDs,
4239 * otherwise we have to use the interleaved streams support for getting the data
4240 * out of the Front sink (depending on the mapping layout).
4241 */
4242#endif
4243 rc = AudioMixerSinkUpdate(pThis->SinkFront.pMixSink);
4244 if (RT_SUCCESS(rc))
4245 {
4246 cbToProcess = AudioMixerSinkGetWritable(pThis->SinkFront.pMixSink);
4247 if (cbToProcess)
4248 {
4249 rc = hdaTransfer(pThis, pStreamFront, cbToProcess, NULL /* pcbProcessed */);
4250 fKickTimer |= RT_SUCCESS(rc);
4251 }
4252 }
4253
4254 if ( ASMAtomicReadBool(&pThis->fTimerActive)
4255 || fKickTimer)
4256 {
4257 /* Kick the timer again. */
4258 uint64_t cTicks = pThis->cTimerTicks;
4259 /** @todo adjust cTicks down by now much cbOutMin represents. */
4260 TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
4261 }
4262
4263 LogFlowFuncLeave();
4264
4265 STAM_PROFILE_STOP(&pThis->StatTimer, a);
4266}
4267
4268#else /* VBOX_WITH_AUDIO_CALLBACKS */
4269
4270static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4271{
4272 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
4273 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4274 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4275 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4276 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4277
4278 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4279 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4280
4281 PPDMAUDIOCALLBACKDATAIN pData = (PPDMAUDIOCALLBACKDATAIN)pvUser;
4282 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAIN), VERR_INVALID_PARAMETER);
4283
4284 return hdaTransfer(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
4285}
4286
4287static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4288{
4289 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
4290 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4291 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4292 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4293 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4294
4295 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4296 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4297
4298 PPDMAUDIOCALLBACKDATAOUT pData = (PPDMAUDIOCALLBACKDATAOUT)pvUser;
4299 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAOUT), VERR_INVALID_PARAMETER);
4300
4301 PHDASTATE pThis = pCtx->pThis;
4302
4303 int rc = hdaTransfer(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
4304 if ( RT_SUCCESS(rc)
4305 && pData->cbOutWritten)
4306 {
4307 PHDADRIVER pDrv;
4308 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4309 {
4310 uint32_t cSamplesPlayed;
4311 int rc2 = pDrv->pConnector->pfnPlay(pDrv->pConnector, &cSamplesPlayed);
4312 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
4313 }
4314 }
4315}
4316#endif /* VBOX_WITH_AUDIO_CALLBACKS */
4317
4318static int hdaTransfer(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToProcess, uint32_t *pcbProcessed)
4319{
4320 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4321 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4322 /* pcbProcessed is optional. */
4323
4324 if (ASMAtomicReadBool(&pThis->fInReset)) /* HDA controller in reset mode? Bail out. */
4325 {
4326 LogFlowFunc(("HDA in reset mode, skipping\n"));
4327
4328 if (pcbProcessed)
4329 *pcbProcessed = 0;
4330 return VINF_SUCCESS;
4331 }
4332
4333 bool fProceed = true;
4334 int rc = RTCritSectEnter(&pStream->State.CritSect);
4335 if (RT_FAILURE(rc))
4336 return rc;
4337
4338 Log3Func(("[SD%RU8] fActive=%RTbool, cbToProcess=%RU32\n", pStream->u8SD, pStream->State.fActive, cbToProcess));
4339
4340 /* Stop request received? */
4341 if ( !pStream->State.fActive
4342 || pStream->State.fDoStop)
4343 {
4344 pStream->State.fActive = false;
4345
4346 rc = RTSemEventSignal(pStream->State.hStateChangedEvent);
4347 AssertRC(rc);
4348
4349 fProceed = false;
4350 }
4351 /* Is the stream not in a running state currently? */
4352 else if (!(HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)))
4353 fProceed = false;
4354 /* Nothing to process? */
4355 else if (!cbToProcess)
4356 fProceed = false;
4357
4358 if ((HDA_STREAM_REG(pThis, STS, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
4359 {
4360 Log3Func(("[SD%RU8]: BCIS set\n", pStream->u8SD));
4361 fProceed = false;
4362 }
4363
4364 if (!fProceed)
4365 {
4366 Log3Func(("[SD%RU8]: Skipping\n", pStream->u8SD));
4367
4368 rc = RTCritSectLeave(&pStream->State.CritSect);
4369 AssertRC(rc);
4370
4371 if (pcbProcessed)
4372 *pcbProcessed = 0;
4373 return VINF_SUCCESS;
4374 }
4375
4376 /* Sanity checks. */
4377 Assert(pStream->u8SD <= HDA_MAX_STREAMS);
4378 Assert(pStream->u64BDLBase);
4379 Assert(pStream->u32CBL);
4380
4381 /* State sanity checks. */
4382 Assert(pStream->State.fInReset == false);
4383 Assert(HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) <= pStream->u32CBL);
4384
4385 bool fInterrupt = false;
4386
4387#ifdef DEBUG_andy
4388//# define DEBUG_SIMPLE
4389#endif
4390
4391#ifdef DEBUG_SIMPLE
4392 uint8_t u8FIFO[_16K+1];
4393 size_t u8FIFOff = 0;
4394#endif
4395
4396 uint32_t cbLeft = cbToProcess;
4397 uint32_t cbTotal = 0;
4398 uint32_t cbChunk = 0;
4399 uint32_t cbChunkProcessed = 0;
4400
4401 /* Set the FIFORDY bit on the stream while doing the transfer. */
4402 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
4403
4404 while (cbLeft)
4405 {
4406 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
4407 if (hdaStreamNeedsNextBDLE(pThis, pStream))
4408 {
4409 rc = hdaStreamGetNextBDLE(pThis, pStream);
4410 if (RT_FAILURE(rc))
4411 break;
4412 }
4413
4414 cbChunk = hdaStreamGetTransferSize(pThis, pStream, cbLeft);
4415 cbChunkProcessed = 0;
4416
4417 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN)
4418 rc = hdaReadAudio(pThis, pStream, cbChunk, &cbChunkProcessed);
4419 else
4420 {
4421#ifndef DEBUG_SIMPLE
4422 rc = hdaWriteAudio(pThis, pStream, cbChunk, &cbChunkProcessed);
4423#else
4424 void *pvBuf = u8FIFO + u8FIFOff;
4425 int32_t cbBuf = cbChunk;
4426
4427 PHDABDLE pBDLE = &pStream->State.BDLE;
4428
4429 if (cbBuf)
4430 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
4431 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
4432 pvBuf, cbBuf);
4433
4434 cbChunkProcessed = cbChunk;
4435
4436 hdaBDLEUpdate(pBDLE, cbChunkProcessed, cbChunkProcessed);
4437
4438 u8FIFOff += cbChunkProcessed;
4439 Assert((u8FIFOff & 1) == 0);
4440 Assert(u8FIFOff <= sizeof(u8FIFO));
4441#endif
4442 }
4443
4444 if (RT_FAILURE(rc))
4445 break;
4446
4447 hdaStreamTransferUpdate(pThis, pStream, cbChunkProcessed);
4448
4449 Assert(cbLeft >= cbChunkProcessed);
4450 cbLeft -= cbChunkProcessed;
4451 cbTotal += cbChunkProcessed;
4452
4453 if (rc == VINF_EOF)
4454 break;
4455
4456 if (hdaStreamTransferIsComplete(pThis, pStream, &fInterrupt))
4457 break;
4458 }
4459
4460 /* Remove the FIFORDY bit again. */
4461 HDA_STREAM_REG(pThis, STS, pStream->u8SD) &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
4462
4463 LogFlowFunc(("[SD%RU8]: %RU32 / %RU32, rc=%Rrc\n", pStream->u8SD, cbTotal, cbToProcess, rc));
4464
4465#ifdef DEBUG_SIMPLE
4466# ifdef HDA_DEBUG_DUMP_PCM_DATA
4467 RTFILE fh;
4468 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaWriteAudio.pcm",
4469 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4470 RTFileWrite(fh, u8FIFO, u8FIFOff, NULL);
4471 RTFileClose(fh);
4472# endif
4473
4474 AudioMixerSinkWrite(pThis->SinkFront.pMixSink, AUDMIXOP_COPY, u8FIFO, u8FIFOff,
4475 NULL /* pcbWritten */);
4476#endif /* DEBUG_SIMPLE */
4477
4478 if (fInterrupt)
4479 {
4480 /**
4481 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
4482 * last byte of data for the current descriptor has been fetched
4483 * from memory and put into the DMA FIFO.
4484 *
4485 * Speech synthesis works fine on Mac Guest if this bit isn't set
4486 * but in general sound quality gets worse.
4487 *
4488 * This must be set in *any* case.
4489 */
4490 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
4491 Log3Func(("[SD%RU8]: BCIS: Set\n", pStream->u8SD));
4492
4493 hdaProcessInterrupt(pThis);
4494 }
4495
4496 if (RT_SUCCESS(rc))
4497 {
4498 if (pcbProcessed)
4499 *pcbProcessed = cbTotal;
4500 }
4501
4502 int rc2 = RTCritSectLeave(&pStream->State.CritSect);
4503 if (RT_SUCCESS(rc))
4504 rc = rc2;
4505
4506 return rc;
4507}
4508#endif /* IN_RING3 */
4509
4510/* MMIO callbacks */
4511
4512/**
4513 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
4514 *
4515 * @note During implementation, we discovered so-called "forgotten" or "hole"
4516 * registers whose description is not listed in the RPM, datasheet, or
4517 * spec.
4518 */
4519PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4520{
4521 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4522 int rc;
4523 RT_NOREF_PV(pvUser);
4524
4525 /*
4526 * Look up and log.
4527 */
4528 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4529 int idxRegDsc = hdaRegLookup(offReg); /* Register descriptor index. */
4530#ifdef LOG_ENABLED
4531 unsigned const cbLog = cb;
4532 uint32_t offRegLog = offReg;
4533#endif
4534
4535 Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
4536 Assert(cb == 4); Assert((offReg & 3) == 0);
4537
4538 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4539 LogFunc(("Access to registers except GCTL is blocked while reset\n"));
4540
4541 if (idxRegDsc == -1)
4542 LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
4543
4544 if (idxRegDsc != -1)
4545 {
4546 /* ASSUMES gapless DWORD at end of map. */
4547 if (g_aHdaRegMap[idxRegDsc].size == 4)
4548 {
4549 /*
4550 * Straight forward DWORD access.
4551 */
4552 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
4553 Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
4554 }
4555 else
4556 {
4557 /*
4558 * Multi register read (unless there are trailing gaps).
4559 * ASSUMES that only DWORD reads have sideeffects.
4560 */
4561 uint32_t u32Value = 0;
4562 unsigned cbLeft = 4;
4563 do
4564 {
4565 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
4566 uint32_t u32Tmp = 0;
4567
4568 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
4569 Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
4570 if (rc != VINF_SUCCESS)
4571 break;
4572 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
4573
4574 cbLeft -= cbReg;
4575 offReg += cbReg;
4576 idxRegDsc++;
4577 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
4578
4579 if (rc == VINF_SUCCESS)
4580 *(uint32_t *)pv = u32Value;
4581 else
4582 Assert(!IOM_SUCCESS(rc));
4583 }
4584 }
4585 else
4586 {
4587 rc = VINF_IOM_MMIO_UNUSED_FF;
4588 Log3Func(("\tHole at %x is accessed for read\n", offReg));
4589 }
4590
4591 /*
4592 * Log the outcome.
4593 */
4594#ifdef LOG_ENABLED
4595 if (cbLog == 4)
4596 Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
4597 else if (cbLog == 2)
4598 Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
4599 else if (cbLog == 1)
4600 Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
4601#endif
4602 return rc;
4603}
4604
4605
4606DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
4607{
4608 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4609 {
4610 LogRel2(("HDA: Warning: Access to register 0x%x is blocked while reset\n", idxRegDsc));
4611 return VINF_SUCCESS;
4612 }
4613
4614#ifdef LOG_ENABLED
4615 uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4616 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
4617#endif
4618 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
4619 Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
4620 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
4621 RT_NOREF1(pszLog);
4622 return rc;
4623}
4624
4625
4626/**
4627 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
4628 */
4629PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
4630{
4631 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4632 int rc;
4633 RT_NOREF_PV(pvUser);
4634
4635 /*
4636 * The behavior of accesses that aren't aligned on natural boundraries is
4637 * undefined. Just reject them outright.
4638 */
4639 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
4640 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
4641 if (GCPhysAddr & (cb - 1))
4642 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
4643
4644 /*
4645 * Look up and log the access.
4646 */
4647 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4648 int idxRegDsc = hdaRegLookup(offReg);
4649 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
4650 uint64_t u64Value;
4651 if (cb == 4) u64Value = *(uint32_t const *)pv;
4652 else if (cb == 2) u64Value = *(uint16_t const *)pv;
4653 else if (cb == 1) u64Value = *(uint8_t const *)pv;
4654 else if (cb == 8) u64Value = *(uint64_t const *)pv;
4655 else
4656 {
4657 u64Value = 0; /* shut up gcc. */
4658 AssertReleaseMsgFailed(("%u\n", cb));
4659 }
4660
4661#ifdef LOG_ENABLED
4662 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
4663 if (idxRegDsc == -1)
4664 Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
4665 else if (cb == 4)
4666 Log3Func(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4667 else if (cb == 2)
4668 Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4669 else if (cb == 1)
4670 Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4671
4672 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
4673 Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
4674#endif
4675
4676 /*
4677 * Try for a direct hit first.
4678 */
4679 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
4680 {
4681 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
4682 Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
4683 }
4684 /*
4685 * Partial or multiple register access, loop thru the requested memory.
4686 */
4687 else
4688 {
4689 /*
4690 * If it's an access beyond the start of the register, shift the input
4691 * value and fill in missing bits. Natural alignment rules means we
4692 * will only see 1 or 2 byte accesses of this kind, so no risk of
4693 * shifting out input values.
4694 */
4695 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(offReg)) != -1)
4696 {
4697 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
4698 offReg -= cbBefore;
4699 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4700 u64Value <<= cbBefore * 8;
4701 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
4702 Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
4703 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
4704 }
4705
4706 /* Loop thru the write area, it may cover multiple registers. */
4707 rc = VINF_SUCCESS;
4708 for (;;)
4709 {
4710 uint32_t cbReg;
4711 if (idxRegDsc != -1)
4712 {
4713 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4714 cbReg = g_aHdaRegMap[idxRegDsc].size;
4715 if (cb < cbReg)
4716 {
4717 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
4718 Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
4719 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
4720 }
4721#ifdef LOG_ENABLED
4722 uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
4723#endif
4724 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
4725 Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
4726 }
4727 else
4728 {
4729 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
4730 cbReg = 1;
4731 }
4732 if (rc != VINF_SUCCESS)
4733 break;
4734 if (cbReg >= cb)
4735 break;
4736
4737 /* Advance. */
4738 offReg += cbReg;
4739 cb -= cbReg;
4740 u64Value >>= cbReg * 8;
4741 if (idxRegDsc == -1)
4742 idxRegDsc = hdaRegLookup(offReg);
4743 else
4744 {
4745 idxRegDsc++;
4746 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
4747 || g_aHdaRegMap[idxRegDsc].offset != offReg)
4748 {
4749 idxRegDsc = -1;
4750 }
4751 }
4752 }
4753 }
4754
4755 return rc;
4756}
4757
4758
4759/* PCI callback. */
4760
4761#ifdef IN_RING3
4762/**
4763 * @callback_method_impl{FNPCIIOREGIONMAP}
4764 */
4765static DECLCALLBACK(int)
4766hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
4767{
4768 RT_NOREF(iRegion, enmType);
4769 PPDMDEVINS pDevIns = pPciDev->pDevIns;
4770 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
4771
4772 /*
4773 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
4774 *
4775 * Let IOM talk DWORDs when reading, saves a lot of complications. On
4776 * writing though, we have to do it all ourselves because of sideeffects.
4777 */
4778 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
4779 int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
4780 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
4781 hdaMMIOWrite, hdaMMIORead, "HDA");
4782 if (RT_FAILURE(rc))
4783 return rc;
4784
4785 if (pThis->fR0Enabled)
4786 {
4787 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
4788 "hdaMMIOWrite", "hdaMMIORead");
4789 if (RT_FAILURE(rc))
4790 return rc;
4791 }
4792
4793 if (pThis->fRCEnabled)
4794 {
4795 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
4796 "hdaMMIOWrite", "hdaMMIORead");
4797 if (RT_FAILURE(rc))
4798 return rc;
4799 }
4800
4801 pThis->MMIOBaseAddr = GCPhysAddress;
4802 return VINF_SUCCESS;
4803}
4804
4805
4806/* Saved state callbacks. */
4807
4808static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
4809{
4810 RT_NOREF(pDevIns);
4811#ifdef DEBUG
4812 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4813#endif
4814 LogFlowFunc(("[SD%RU8]\n", pStrm->u8SD));
4815
4816 /* Save stream ID. */
4817 int rc = SSMR3PutU8(pSSM, pStrm->u8SD);
4818 AssertRCReturn(rc, rc);
4819 Assert(pStrm->u8SD <= HDA_MAX_STREAMS);
4820
4821 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields6, NULL);
4822 AssertRCReturn(rc, rc);
4823
4824#ifdef DEBUG /* Sanity checks. */
4825 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrm->u8SD),
4826 HDA_STREAM_REG(pThis, BDPU, pStrm->u8SD));
4827 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStrm->u8SD);
4828 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStrm->u8SD);
4829
4830 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
4831
4832 Assert(u64BaseDMA == pStrm->u64BDLBase);
4833 Assert(u16LVI == pStrm->u16LVI);
4834 Assert(u32CBL == pStrm->u32CBL);
4835#endif
4836
4837 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
4838 0 /*fFlags*/, g_aSSMBDLEFields6, NULL);
4839 AssertRCReturn(rc, rc);
4840
4841 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
4842 0 /*fFlags*/, g_aSSMBDLEStateFields6, NULL);
4843 AssertRCReturn(rc, rc);
4844
4845#ifdef DEBUG /* Sanity checks. */
4846 PHDABDLE pBDLE = &pStrm->State.BDLE;
4847 if (u64BaseDMA)
4848 {
4849 Assert(pStrm->State.uCurBDLE <= u16LVI + 1);
4850
4851 HDABDLE curBDLE;
4852 rc = hdaBDLEFetch(pThis, &curBDLE, u64BaseDMA, pStrm->State.uCurBDLE);
4853 AssertRC(rc);
4854
4855 Assert(curBDLE.u32BufSize == pBDLE->u32BufSize);
4856 Assert(curBDLE.u64BufAdr == pBDLE->u64BufAdr);
4857 Assert(curBDLE.fIntOnCompletion == pBDLE->fIntOnCompletion);
4858 }
4859 else
4860 {
4861 Assert(pBDLE->u64BufAdr == 0);
4862 Assert(pBDLE->u32BufSize == 0);
4863 }
4864#endif
4865 return rc;
4866}
4867
4868/**
4869 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4870 */
4871static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4872{
4873 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4874
4875 /* Save Codec nodes states. */
4876 hdaCodecSaveState(pThis->pCodec, pSSM);
4877
4878 /* Save MMIO registers. */
4879 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
4880 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4881
4882 /* Save number of streams. */
4883 SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
4884
4885 /* Save stream states. */
4886 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4887 {
4888 int rc = hdaSaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
4889 AssertRCReturn(rc, rc);
4890 }
4891
4892 return VINF_SUCCESS;
4893}
4894
4895
4896/**
4897 * @callback_method_impl{FNSSMDEVLOADEXEC}
4898 */
4899static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4900{
4901 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4902
4903 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
4904
4905 LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
4906
4907 /*
4908 * Load Codec nodes states.
4909 */
4910 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
4911 if (RT_FAILURE(rc))
4912 {
4913 LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
4914 return rc;
4915 }
4916
4917 /*
4918 * Load MMIO registers.
4919 */
4920 uint32_t cRegs;
4921 switch (uVersion)
4922 {
4923 case HDA_SSM_VERSION_1:
4924 /* Starting with r71199, we would save 112 instead of 113
4925 registers due to some code cleanups. This only affected trunk
4926 builds in the 4.1 development period. */
4927 cRegs = 113;
4928 if (SSMR3HandleRevision(pSSM) >= 71199)
4929 {
4930 uint32_t uVer = SSMR3HandleVersion(pSSM);
4931 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
4932 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
4933 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
4934 cRegs = 112;
4935 }
4936 break;
4937
4938 case HDA_SSM_VERSION_2:
4939 case HDA_SSM_VERSION_3:
4940 cRegs = 112;
4941 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
4942 break;
4943
4944 /* Since version 4 we store the register count to stay flexible. */
4945 case HDA_SSM_VERSION_4:
4946 case HDA_SSM_VERSION_5:
4947 case HDA_SSM_VERSION:
4948 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
4949 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
4950 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
4951 break;
4952
4953 default:
4954 LogRel(("HDA: Unsupported / too new saved state version (%RU32)\n", uVersion));
4955 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4956 }
4957
4958 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
4959 {
4960 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4961 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
4962 }
4963 else
4964 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
4965
4966 /*
4967 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
4968 * *every* BDLE state, whereas it only needs to be stored
4969 * *once* for every stream. Most of the BDLE state we can
4970 * get out of the registers anyway, so just ignore those values.
4971 *
4972 * Also, only the current BDLE was saved, regardless whether
4973 * there were more than one (and there are at least two entries,
4974 * according to the spec).
4975 */
4976#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
4977 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
4978 AssertRCReturn(rc, rc); \
4979 rc = SSMR3GetU64(pSSM, &x.u64BufAdr); /* u64BdleCviAddr */ \
4980 AssertRCReturn(rc, rc); \
4981 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
4982 AssertRCReturn(rc, rc); \
4983 rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
4984 AssertRCReturn(rc, rc); \
4985 rc = SSMR3GetU32(pSSM, &x.u32BufSize); /* u32BdleCviLen */ \
4986 AssertRCReturn(rc, rc); \
4987 rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
4988 AssertRCReturn(rc, rc); \
4989 rc = SSMR3GetBool(pSSM, &x.fIntOnCompletion); /* fBdleCviIoc */ \
4990 AssertRCReturn(rc, rc); \
4991 rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
4992 AssertRCReturn(rc, rc); \
4993 rc = SSMR3GetMem(pSSM, &x.State.au8FIFO, sizeof(x.State.au8FIFO)); \
4994 AssertRCReturn(rc, rc); \
4995 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
4996 AssertRCReturn(rc, rc); \
4997
4998 /*
4999 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
5000 */
5001 switch (uVersion)
5002 {
5003 case HDA_SSM_VERSION_1:
5004 case HDA_SSM_VERSION_2:
5005 case HDA_SSM_VERSION_3:
5006 case HDA_SSM_VERSION_4:
5007 {
5008 /* Only load the internal states.
5009 * The rest will be initialized from the saved registers later. */
5010
5011 /* Note 1: Only the *current* BDLE for a stream was saved! */
5012 /* Note 2: The stream's saving order is/was fixed, so don't touch! */
5013
5014 /* Output */
5015 PHDASTREAM pStream = &pThis->aStreams[4];
5016 rc = hdaStreamInit(pThis, pStream, 4 /* Stream descriptor, hardcoded */);
5017 if (RT_FAILURE(rc))
5018 break;
5019 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5020 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5021
5022 /* Microphone-In */
5023 pStream = &pThis->aStreams[2];
5024 rc = hdaStreamInit(pThis, pStream, 2 /* Stream descriptor, hardcoded */);
5025 if (RT_FAILURE(rc))
5026 break;
5027 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5028 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5029
5030 /* Line-In */
5031 pStream = &pThis->aStreams[0];
5032 rc = hdaStreamInit(pThis, pStream, 0 /* Stream descriptor, hardcoded */);
5033 if (RT_FAILURE(rc))
5034 break;
5035 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5036 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5037 break;
5038 }
5039
5040 /* Since v5 we support flexible stream and BDLE counts. */
5041 case HDA_SSM_VERSION_5:
5042 case HDA_SSM_VERSION:
5043 {
5044 uint32_t cStreams;
5045 rc = SSMR3GetU32(pSSM, &cStreams);
5046 if (RT_FAILURE(rc))
5047 break;
5048
5049 LogRel2(("hdaLoadExec: cStreams=%RU32\n", cStreams));
5050
5051 /* Load stream states. */
5052 for (uint32_t i = 0; i < cStreams; i++)
5053 {
5054 uint8_t uSD;
5055 rc = SSMR3GetU8(pSSM, &uSD);
5056 if (RT_FAILURE(rc))
5057 break;
5058
5059 PHDASTREAM pStrm = hdaStreamFromSD(pThis, uSD);
5060 HDASTREAM StreamDummy;
5061
5062 if (!pStrm)
5063 {
5064 RT_ZERO(StreamDummy);
5065 pStrm = &StreamDummy;
5066 LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uSD));
5067 break;
5068 }
5069
5070 rc = hdaStreamInit(pThis, pStrm, uSD);
5071 if (RT_FAILURE(rc))
5072 {
5073 LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uSD, rc));
5074 break;
5075 }
5076
5077 if (uVersion == HDA_SSM_VERSION_5)
5078 {
5079 /* Get the current BDLE entry and skip the rest. */
5080 uint16_t cBDLE;
5081
5082 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5083 AssertRC(rc);
5084 rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
5085 AssertRC(rc);
5086 rc = SSMR3GetU16(pSSM, &pStrm->State.uCurBDLE); /* uCurBDLE */
5087 AssertRC(rc);
5088 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5089 AssertRC(rc);
5090
5091 uint32_t u32BDLEIndex;
5092 for (uint16_t a = 0; a < cBDLE; a++)
5093 {
5094 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5095 AssertRC(rc);
5096 rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
5097 AssertRC(rc);
5098
5099 /* Does the current BDLE index match the current BDLE to process? */
5100 if (u32BDLEIndex == pStrm->State.uCurBDLE)
5101 {
5102 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
5103 AssertRC(rc);
5104 rc = SSMR3GetMem(pSSM,
5105 &pStrm->State.BDLE.State.au8FIFO,
5106 sizeof(pStrm->State.BDLE.State.au8FIFO)); /* au8FIFO */
5107 AssertRC(rc);
5108 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.u32BufOff); /* u32BufOff */
5109 AssertRC(rc);
5110 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5111 AssertRC(rc);
5112 }
5113 else /* Skip not current BDLEs. */
5114 {
5115 rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
5116 + sizeof(uint8_t) * 256 /* au8FIFO */
5117 + sizeof(uint32_t) /* u32BufOff */
5118 + sizeof(uint32_t)); /* End marker */
5119 AssertRC(rc);
5120 }
5121 }
5122 }
5123 else
5124 {
5125 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE),
5126 0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
5127 if (RT_FAILURE(rc))
5128 break;
5129
5130 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
5131 0 /* fFlags */, g_aSSMBDLEFields6, NULL);
5132 if (RT_FAILURE(rc))
5133 break;
5134
5135 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
5136 0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
5137 if (RT_FAILURE(rc))
5138 break;
5139 }
5140 }
5141 break;
5142 }
5143
5144 default:
5145 AssertReleaseFailed(); /* Never reached. */
5146 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5147 }
5148
5149#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
5150
5151 if (RT_SUCCESS(rc))
5152 {
5153 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
5154 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
5155 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
5156
5157 /* Also make sure to update the DMA position bit if this was enabled when saving the state. */
5158 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
5159 }
5160
5161 if (RT_SUCCESS(rc))
5162 {
5163 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5164 {
5165 PHDASTREAM pStream = hdaStreamFromSD(pThis, i);
5166 if (pStream)
5167 {
5168 /* Deactive first. */
5169 int rc2 = hdaStreamSetActive(pThis, pStream, false);
5170 AssertRC(rc2);
5171
5172 bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
5173
5174 /* Activate, if needed. */
5175 rc2 = hdaStreamSetActive(pThis, pStream, fActive);
5176 AssertRC(rc2);
5177 }
5178 }
5179 }
5180
5181 if (RT_FAILURE(rc))
5182 LogRel(("HDA: Failed loading device state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5183
5184 LogFlowFuncLeaveRC(rc);
5185 return rc;
5186}
5187
5188#ifdef DEBUG
5189/* Debug and log type formatters. */
5190
5191/**
5192 * @callback_method_impl{FNRTSTRFORMATTYPE}
5193 */
5194static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5195 const char *pszType, void const *pvValue,
5196 int cchWidth, int cchPrecision, unsigned fFlags,
5197 void *pvUser)
5198{
5199 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5200 PHDABDLE pBDLE = (PHDABDLE)pvValue;
5201 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5202 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
5203 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW, pBDLE->fIntOnCompletion,
5204 pBDLE->u32BufSize, pBDLE->u64BufAdr);
5205}
5206
5207/**
5208 * @callback_method_impl{FNRTSTRFORMATTYPE}
5209 */
5210static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5211 const char *pszType, void const *pvValue,
5212 int cchWidth, int cchPrecision, unsigned fFlags,
5213 void *pvUser)
5214{
5215 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5216 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
5217 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5218 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
5219 uSDCTL,
5220 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
5221 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
5222 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
5223 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
5224 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
5225 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
5226 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
5227 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
5228}
5229
5230/**
5231 * @callback_method_impl{FNRTSTRFORMATTYPE}
5232 */
5233static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5234 const char *pszType, void const *pvValue,
5235 int cchWidth, int cchPrecision, unsigned fFlags,
5236 void *pvUser)
5237{
5238 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5239 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
5240 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, hdaSDFIFOSToBytes(uSDFIFOS));
5241}
5242
5243/**
5244 * @callback_method_impl{FNRTSTRFORMATTYPE}
5245 */
5246static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5247 const char *pszType, void const *pvValue,
5248 int cchWidth, int cchPrecision, unsigned fFlags,
5249 void *pvUser)
5250{
5251 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5252 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
5253 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
5254}
5255
5256/**
5257 * @callback_method_impl{FNRTSTRFORMATTYPE}
5258 */
5259static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5260 const char *pszType, void const *pvValue,
5261 int cchWidth, int cchPrecision, unsigned fFlags,
5262 void *pvUser)
5263{
5264 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5265 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
5266 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5267 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
5268 uSdSts,
5269 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
5270 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
5271 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
5272 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
5273}
5274
5275static int hdaDbgLookupRegByName(const char *pszArgs)
5276{
5277 int iReg = 0;
5278 for (; iReg < HDA_NUM_REGS; ++iReg)
5279 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
5280 return iReg;
5281 return -1;
5282}
5283
5284
5285static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
5286{
5287 Assert( pThis
5288 && iHdaIndex >= 0
5289 && iHdaIndex < HDA_NUM_REGS);
5290 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
5291}
5292
5293/**
5294 * @callback_method_impl{FNDBGFHANDLERDEV}
5295 */
5296static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5297{
5298 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5299 int iHdaRegisterIndex = hdaDbgLookupRegByName(pszArgs);
5300 if (iHdaRegisterIndex != -1)
5301 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5302 else
5303 {
5304 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
5305 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5306 }
5307}
5308
5309static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5310{
5311 Assert( pThis
5312 && iIdx >= 0
5313 && iIdx < HDA_MAX_STREAMS);
5314
5315 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5316
5317 pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
5318 pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
5319 pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
5320 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
5321 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
5322 pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStrm->State.BDLE);
5323}
5324
5325static void hdaDbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5326{
5327 Assert( pThis
5328 && iIdx >= 0
5329 && iIdx < HDA_MAX_STREAMS);
5330
5331 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5332 const PHDABDLE pBDLE = &pStrm->State.BDLE;
5333
5334 pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
5335 pHlp->pfnPrintf(pHlp, "\t%R[bdle]\n", pBDLE);
5336
5337 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
5338 HDA_STREAM_REG(pThis, BDPU, iIdx));
5339 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
5340 /*uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx); - unused */
5341
5342 if (!u64BaseDMA)
5343 return;
5344
5345 uint32_t cbBDLE = 0;
5346 for (uint16_t i = 0; i < u16LVI + 1; i++)
5347 {
5348 uint8_t bdle[16]; /** @todo Use a define. */
5349 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * 16, bdle, 16); /** @todo Use a define. */
5350
5351 uint64_t addr = *(uint64_t *)bdle;
5352 uint32_t len = *(uint32_t *)&bdle[8];
5353 uint32_t ioc = *(uint32_t *)&bdle[12];
5354
5355 pHlp->pfnPrintf(pHlp, "\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
5356 i, addr, len, RT_BOOL(ioc & 0x1));
5357
5358 cbBDLE += len;
5359 }
5360
5361 pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
5362
5363 pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", pThis->u64DPBase);
5364 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
5365 {
5366 pHlp->pfnPrintf(pHlp, "No counters found\n");
5367 return;
5368 }
5369
5370 for (int i = 0; i < u16LVI + 1; i++)
5371 {
5372 uint32_t uDMACnt;
5373 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
5374 &uDMACnt, sizeof(uDMACnt));
5375
5376 pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
5377 }
5378}
5379
5380static int hdaDbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
5381{
5382 RT_NOREF(pThis, pszArgs);
5383 /** @todo Add args parsing. */
5384 return -1;
5385}
5386
5387/**
5388 * @callback_method_impl{FNDBGFHANDLERDEV}
5389 */
5390static DECLCALLBACK(void) hdaDbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5391{
5392 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5393 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5394 if (iHdaStreamdex != -1)
5395 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5396 else
5397 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5398 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5399}
5400
5401/**
5402 * @callback_method_impl{FNDBGFHANDLERDEV}
5403 */
5404static DECLCALLBACK(void) hdaDbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5405{
5406 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5407 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5408 if (iHdaStreamdex != -1)
5409 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5410 else
5411 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5412 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5413}
5414
5415/**
5416 * @callback_method_impl{FNDBGFHANDLERDEV}
5417 */
5418static DECLCALLBACK(void) hdaDbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5419{
5420 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5421
5422 if (pThis->pCodec->pfnDbgListNodes)
5423 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
5424 else
5425 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5426}
5427
5428/**
5429 * @callback_method_impl{FNDBGFHANDLERDEV}
5430 */
5431static DECLCALLBACK(void) hdaDbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5432{
5433 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5434
5435 if (pThis->pCodec->pfnDbgSelector)
5436 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
5437 else
5438 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5439}
5440
5441/**
5442 * @callback_method_impl{FNDBGFHANDLERDEV}
5443 */
5444static DECLCALLBACK(void) hdaDbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5445{
5446 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5447
5448 if (pThis->pMixer)
5449 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
5450 else
5451 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
5452}
5453#endif /* DEBUG */
5454
5455/* PDMIBASE */
5456
5457/**
5458 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5459 */
5460static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
5461{
5462 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
5463 Assert(&pThis->IBase == pInterface);
5464
5465 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5466 return NULL;
5467}
5468
5469
5470/* PDMDEVREG */
5471
5472/**
5473 * Reset notification.
5474 *
5475 * @returns VBox status code.
5476 * @param pDevIns The device instance data.
5477 *
5478 * @remark The original sources didn't install a reset handler, but it seems to
5479 * make sense to me so we'll do it.
5480 */
5481static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
5482{
5483 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5484
5485 LogFlowFuncEnter();
5486
5487# ifndef VBOX_WITH_AUDIO_CALLBACKS
5488 /*
5489 * Stop the timer, if any.
5490 */
5491 hdaTimerMaybeStop(pThis);
5492# endif
5493
5494 /* See 6.2.1. */
5495 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO /* Ouput streams */,
5496 HDA_MAX_SDI /* Input streams */,
5497 0 /* Bidirectional output streams */,
5498 0 /* Serial data out signals */,
5499 1 /* 64-bit */);
5500 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
5501 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
5502 /* Announce the full 60 words output payload. */
5503 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
5504 /* Announce the full 29 words input payload. */
5505 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
5506 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
5507 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
5508 HDA_REG(pThis, CORBRP) = 0x0;
5509 HDA_REG(pThis, RIRBWP) = 0x0;
5510
5511 /*
5512 * Stop any audio currently playing and/or recording.
5513 */
5514 AudioMixerSinkCtl(pThis->SinkFront.pMixSink, AUDMIXSINKCMD_DISABLE);
5515# ifdef VBOX_WITH_HDA_MIC_IN
5516 AudioMixerSinkCtl(pThis->SinkMicIn.pMixSink, AUDMIXSINKCMD_DISABLE);
5517# endif
5518 AudioMixerSinkCtl(pThis->SinkLineIn.pMixSink, AUDMIXSINKCMD_DISABLE);
5519# ifdef VBOX_WITH_HDA_51_SURROUND
5520 AudioMixerSinkCtl(pThis->SinkCenterLFE.pMixSink, AUDMIXSINKCMD_DISABLE);
5521 AudioMixerSinkCtl(pThis->SinkRear.pMixSink, AUDMIXSINKCMD_DISABLE);
5522# endif
5523
5524 /*
5525 * Set some sensible defaults for which HDA sinks
5526 * are connected to which stream number.
5527 *
5528 * We use SD0 for input and SD4 for output by default.
5529 * These stream numbers can be changed by the guest dynamically lateron.
5530 */
5531#ifdef VBOX_WITH_HDA_MIC_IN
5532 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 */, 0 /* Channel */);
5533#endif
5534 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 */, 0 /* Channel */);
5535
5536 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 */, 0 /* Channel */);
5537#ifdef VBOX_WITH_HDA_51_SURROUND
5538 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 */, 0 /* Channel */);
5539 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 */, 0 /* Channel */);
5540#endif
5541
5542 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
5543
5544 if (pThis->pu32CorbBuf)
5545 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
5546 else
5547 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5548
5549 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
5550 if (pThis->pu64RirbBuf)
5551 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
5552 else
5553 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5554
5555 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
5556
5557 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5558 {
5559 /* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
5560 HDA_STREAM_REG(pThis, CTL, i) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN);
5561 hdaStreamReset(pThis, &pThis->aStreams[i]);
5562 }
5563
5564 /* Clear stream tags <-> objects mapping table. */
5565 RT_ZERO(pThis->aTags);
5566
5567 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
5568 HDA_REG(pThis, STATESTS) = 0x1;
5569
5570# ifndef VBOX_WITH_AUDIO_CALLBACKS
5571 hdaTimerMaybeStart(pThis);
5572# endif
5573
5574 LogFlowFuncLeave();
5575 LogRel(("HDA: Reset\n"));
5576}
5577
5578/**
5579 * @interface_method_impl{PDMDEVREG,pfnDestruct}
5580 */
5581static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
5582{
5583 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5584
5585 PHDADRIVER pDrv;
5586 while (!RTListIsEmpty(&pThis->lstDrv))
5587 {
5588 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
5589
5590 RTListNodeRemove(&pDrv->Node);
5591 RTMemFree(pDrv);
5592 }
5593
5594 if (pThis->pCodec)
5595 {
5596 hdaCodecDestruct(pThis->pCodec);
5597
5598 RTMemFree(pThis->pCodec);
5599 pThis->pCodec = NULL;
5600 }
5601
5602 RTMemFree(pThis->pu32CorbBuf);
5603 pThis->pu32CorbBuf = NULL;
5604
5605 RTMemFree(pThis->pu64RirbBuf);
5606 pThis->pu64RirbBuf = NULL;
5607
5608 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5609 hdaStreamDestroy(&pThis->aStreams[i]);
5610
5611 return VINF_SUCCESS;
5612}
5613
5614
5615/**
5616 * Attach command, internal version.
5617 *
5618 * This is called to let the device attach to a driver for a specified LUN
5619 * during runtime. This is not called during VM construction, the device
5620 * constructor has to attach to all the available drivers.
5621 *
5622 * @returns VBox status code.
5623 * @param pDevIns The device instance.
5624 * @param pDrv Driver to (re-)use for (re-)attaching to.
5625 * If NULL is specified, a new driver will be created and appended
5626 * to the driver list.
5627 * @param uLUN The logical unit which is being detached.
5628 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5629 */
5630static int hdaAttachInternal(PPDMDEVINS pDevIns, PHDADRIVER pDrv, unsigned uLUN, uint32_t fFlags)
5631{
5632 RT_NOREF(fFlags);
5633 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5634
5635 /*
5636 * Attach driver.
5637 */
5638 char *pszDesc = NULL;
5639 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
5640 AssertReleaseMsgReturn(pszDesc,
5641 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
5642 VERR_NO_MEMORY);
5643
5644 PPDMIBASE pDrvBase;
5645 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
5646 &pThis->IBase, &pDrvBase, pszDesc);
5647 if (RT_SUCCESS(rc))
5648 {
5649 if (pDrv == NULL)
5650 pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
5651 if (pDrv)
5652 {
5653 pDrv->pDrvBase = pDrvBase;
5654 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
5655 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
5656 pDrv->pHDAState = pThis;
5657 pDrv->uLUN = uLUN;
5658
5659 /*
5660 * For now we always set the driver at LUN 0 as our primary
5661 * host backend. This might change in the future.
5662 */
5663 if (pDrv->uLUN == 0)
5664 pDrv->Flags |= PDMAUDIODRVFLAGS_PRIMARY;
5665
5666 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
5667
5668 /* Attach to driver list if not attached yet. */
5669 if (!pDrv->fAttached)
5670 {
5671 RTListAppend(&pThis->lstDrv, &pDrv->Node);
5672 pDrv->fAttached = true;
5673 }
5674 }
5675 else
5676 rc = VERR_NO_MEMORY;
5677 }
5678 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5679 LogFunc(("No attached driver for LUN #%u\n", uLUN));
5680
5681 if (RT_FAILURE(rc))
5682 {
5683 /* Only free this string on failure;
5684 * must remain valid for the live of the driver instance. */
5685 RTStrFree(pszDesc);
5686 }
5687
5688 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
5689 return rc;
5690}
5691
5692/**
5693 * Attach command.
5694 *
5695 * This is called to let the device attach to a driver for a specified LUN
5696 * during runtime. This is not called during VM construction, the device
5697 * constructor has to attach to all the available drivers.
5698 *
5699 * @returns VBox status code.
5700 * @param pDevIns The device instance.
5701 * @param uLUN The logical unit which is being detached.
5702 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5703 */
5704static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5705{
5706 return hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
5707}
5708
5709static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5710{
5711 RT_NOREF(pDevIns, uLUN, fFlags);
5712 LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
5713}
5714
5715/**
5716 * Powers off the device.
5717 *
5718 * @param pDevIns Device instance to power off.
5719 */
5720static DECLCALLBACK(void) hdaPowerOff(PPDMDEVINS pDevIns)
5721{
5722 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5723
5724 LogRel2(("HDA: Powering off ...\n"));
5725
5726 /* Ditto goes for the codec, which in turn uses the mixer. */
5727 hdaCodecPowerOff(pThis->pCodec);
5728
5729 /**
5730 * Note: Destroy the mixer while powering off and *not* in hdaDestruct,
5731 * giving the mixer the chance to release any references held to
5732 * PDM audio streams it maintains.
5733 */
5734 if (pThis->pMixer)
5735 {
5736 AudioMixerDestroy(pThis->pMixer);
5737 pThis->pMixer = NULL;
5738 }
5739}
5740
5741/**
5742 * Re-attaches a new driver to the device's driver chain.
5743 *
5744 * @returns VBox status code.
5745 * @param pThis Device instance to re-attach driver to.
5746 * @param pDrv Driver instance used for attaching to.
5747 * If NULL is specified, a new driver will be created and appended
5748 * to the driver list.
5749 * @param uLUN The logical unit which is being re-detached.
5750 * @param pszDriver Driver name.
5751 */
5752static int hdaReattach(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
5753{
5754 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
5755 AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
5756
5757 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
5758 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
5759 PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
5760
5761 /* Remove LUN branch. */
5762 CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
5763
5764 if (pDrv)
5765 {
5766 /* Re-use a driver instance => detach the driver before. */
5767 int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
5768 if (RT_FAILURE(rc))
5769 return rc;
5770 }
5771
5772#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
5773
5774 int rc = VINF_SUCCESS;
5775 do
5776 {
5777 PCFGMNODE pLunL0;
5778 rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
5779 rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
5780 rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
5781
5782 PCFGMNODE pLunL1, pLunL2;
5783 rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
5784 rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
5785 rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
5786
5787 rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
5788
5789 } while (0);
5790
5791 if (RT_SUCCESS(rc))
5792 rc = hdaAttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
5793
5794 LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
5795
5796#undef RC_CHECK
5797
5798 return rc;
5799}
5800
5801/**
5802 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5803 */
5804static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5805{
5806 RT_NOREF(iInstance);
5807 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5808 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5809 Assert(iInstance == 0);
5810
5811 /*
5812 * Validations.
5813 */
5814 if (!CFGMR3AreValuesValid(pCfg, "R0Enabled\0"
5815 "RCEnabled\0"
5816 "TimerHz\0"))
5817 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5818 N_ ("Invalid configuration for the Intel HDA device"));
5819
5820 int rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &pThis->fRCEnabled, false);
5821 if (RT_FAILURE(rc))
5822 return PDMDEV_SET_ERROR(pDevIns, rc,
5823 N_("HDA configuration error: failed to read RCEnabled as boolean"));
5824 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
5825 if (RT_FAILURE(rc))
5826 return PDMDEV_SET_ERROR(pDevIns, rc,
5827 N_("HDA configuration error: failed to read R0Enabled as boolean"));
5828#ifndef VBOX_WITH_AUDIO_CALLBACKS
5829 uint16_t uTimerHz;
5830 rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, 200 /* Hz */);
5831 if (RT_FAILURE(rc))
5832 return PDMDEV_SET_ERROR(pDevIns, rc,
5833 N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
5834#endif
5835
5836 /*
5837 * Initialize data (most of it anyway).
5838 */
5839 pThis->pDevInsR3 = pDevIns;
5840 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5841 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5842 /* IBase */
5843 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
5844
5845 /* PCI Device */
5846 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
5847 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
5848
5849 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
5850 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
5851 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
5852 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
5853 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
5854 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
5855 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
5856 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
5857 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
5858 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
5859 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
5860
5861#if defined(HDA_AS_PCI_EXPRESS)
5862 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
5863#elif defined(VBOX_WITH_MSI_DEVICES)
5864 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
5865#else
5866 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
5867#endif
5868
5869 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
5870 /// of these values needs to be properly documented!
5871 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
5872 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
5873
5874 /* Power Management */
5875 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
5876 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
5877 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
5878
5879#ifdef HDA_AS_PCI_EXPRESS
5880 /* PCI Express */
5881 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
5882 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
5883 /* Device flags */
5884 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
5885 /* version */ 0x1 |
5886 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
5887 /* MSI */ (100) << 9 );
5888 /* Device capabilities */
5889 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
5890 /* Device control */
5891 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
5892 /* Device status */
5893 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
5894 /* Link caps */
5895 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
5896 /* Link control */
5897 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
5898 /* Link status */
5899 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
5900 /* Slot capabilities */
5901 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
5902 /* Slot control */
5903 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
5904 /* Slot status */
5905 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
5906 /* Root control */
5907 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
5908 /* Root capabilities */
5909 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
5910 /* Root status */
5911 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
5912 /* Device capabilities 2 */
5913 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
5914 /* Device control 2 */
5915 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
5916 /* Link control 2 */
5917 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
5918 /* Slot control 2 */
5919 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
5920#endif
5921
5922 /*
5923 * Register the PCI device.
5924 */
5925 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5926 if (RT_FAILURE(rc))
5927 return rc;
5928
5929 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
5930 if (RT_FAILURE(rc))
5931 return rc;
5932
5933#ifdef VBOX_WITH_MSI_DEVICES
5934 PDMMSIREG MsiReg;
5935 RT_ZERO(MsiReg);
5936 MsiReg.cMsiVectors = 1;
5937 MsiReg.iMsiCapOffset = 0x60;
5938 MsiReg.iMsiNextOffset = 0x50;
5939 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5940 if (RT_FAILURE(rc))
5941 {
5942 /* That's OK, we can work without MSI */
5943 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
5944 }
5945#endif
5946
5947 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
5948 if (RT_FAILURE(rc))
5949 return rc;
5950
5951 RTListInit(&pThis->lstDrv);
5952
5953 uint8_t uLUN;
5954 for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
5955 {
5956 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
5957 rc = hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, 0 /* fFlags */);
5958 if (RT_FAILURE(rc))
5959 {
5960 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5961 rc = VINF_SUCCESS;
5962 else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
5963 {
5964 hdaReattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
5965 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
5966 N_("No audio devices could be opened. Selecting the NULL audio backend "
5967 "with the consequence that no sound is audible"));
5968 /* attaching to the NULL audio backend will never fail */
5969 rc = VINF_SUCCESS;
5970 }
5971 break;
5972 }
5973 }
5974
5975 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
5976
5977 if (RT_SUCCESS(rc))
5978 {
5979 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
5980 if (RT_SUCCESS(rc))
5981 {
5982 /*
5983 * Add mixer output sinks.
5984 */
5985#ifdef VBOX_WITH_HDA_51_SURROUND
5986 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
5987 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5988 AssertRC(rc);
5989 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
5990 AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
5991 AssertRC(rc);
5992 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
5993 AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
5994 AssertRC(rc);
5995#else
5996 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
5997 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5998 AssertRC(rc);
5999#endif
6000 /*
6001 * Add mixer input sinks.
6002 */
6003 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
6004 AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
6005 AssertRC(rc);
6006#ifdef VBOX_WITH_HDA_MIC_IN
6007 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
6008 AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
6009 AssertRC(rc);
6010#endif
6011 /* There is no master volume control. Set the master to max. */
6012 PDMAUDIOVOLUME vol = { false, 255, 255 };
6013 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
6014 AssertRC(rc);
6015 }
6016 }
6017
6018 if (RT_SUCCESS(rc))
6019 {
6020 /* Construct codec. */
6021 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
6022 if (!pThis->pCodec)
6023 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
6024
6025 /* Set codec callbacks. */
6026 pThis->pCodec->pfnMixerAddStream = hdaMixerAddStream;
6027 pThis->pCodec->pfnMixerRemoveStream = hdaMixerRemoveStream;
6028 pThis->pCodec->pfnMixerSetStream = hdaMixerSetStream;
6029 pThis->pCodec->pfnMixerSetVolume = hdaMixerSetVolume;
6030 pThis->pCodec->pfnReset = hdaCodecReset;
6031
6032 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
6033
6034 /* Construct the codec. */
6035 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
6036 if (RT_FAILURE(rc))
6037 AssertRCReturn(rc, rc);
6038
6039 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
6040 verb F20 should provide device/codec recognition. */
6041 Assert(pThis->pCodec->u16VendorId);
6042 Assert(pThis->pCodec->u16DeviceId);
6043 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
6044 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
6045 }
6046
6047 if (RT_SUCCESS(rc))
6048 {
6049 /*
6050 * Create all hardware streams.
6051 */
6052 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
6053 {
6054 rc = hdaStreamCreate(&pThis->aStreams[i], i /* uSD */);
6055 AssertRC(rc);
6056 }
6057
6058 /*
6059 * Initialize the driver chain.
6060 */
6061 PHDADRIVER pDrv;
6062 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6063 {
6064 /*
6065 * Only primary drivers are critical for the VM to run. Everything else
6066 * might not worth showing an own error message box in the GUI.
6067 */
6068 if (!(pDrv->Flags & PDMAUDIODRVFLAGS_PRIMARY))
6069 continue;
6070
6071 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
6072 AssertPtr(pCon);
6073
6074 bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
6075#ifdef VBOX_WITH_HDA_MIC_IN
6076 bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
6077#endif
6078 bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
6079#ifdef VBOX_WITH_HDA_51_SURROUND
6080 /** @todo Anything to do here? */
6081#endif
6082
6083 if ( !fValidLineIn
6084#ifdef VBOX_WITH_HDA_MIC_IN
6085 && !fValidMicIn
6086#endif
6087 && !fValidOut)
6088 {
6089 LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
6090
6091 hdaReset(pDevIns);
6092 hdaReattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
6093
6094 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6095 N_("No audio devices could be opened. Selecting the NULL audio backend "
6096 "with the consequence that no sound is audible"));
6097 }
6098 else
6099 {
6100 bool fWarn = false;
6101
6102 PDMAUDIOBACKENDCFG backendCfg;
6103 int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
6104 if (RT_SUCCESS(rc2))
6105 {
6106 if (backendCfg.cSources)
6107 {
6108#ifdef VBOX_WITH_HDA_MIC_IN
6109 /* If the audio backend supports two or more input streams at once,
6110 * warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
6111 if (backendCfg.cMaxStreamsIn >= 2)
6112 fWarn = !fValidLineIn || !fValidMicIn;
6113 /* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
6114 * *not* ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
6115 * One of the two simply is not in use then. */
6116 else if (backendCfg.cMaxStreamsIn == 1)
6117 fWarn = !fValidLineIn && !fValidMicIn;
6118 /* Don't warn if our backend is not able of supporting any input streams at all. */
6119#else
6120 /* We only have line-in as input source. */
6121 fWarn = !fValidLineIn;
6122#endif
6123 }
6124
6125 if ( !fWarn
6126 && backendCfg.cSinks)
6127 {
6128 fWarn = !fValidOut;
6129 }
6130 }
6131 else
6132 {
6133 LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
6134 fWarn = true;
6135 }
6136
6137 if (fWarn)
6138 {
6139 char szMissingStreams[255];
6140 size_t len = 0;
6141 if (!fValidLineIn)
6142 {
6143 LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
6144 len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
6145 }
6146#ifdef VBOX_WITH_HDA_MIC_IN
6147 if (!fValidMicIn)
6148 {
6149 LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
6150 len += RTStrPrintf(szMissingStreams + len,
6151 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
6152 }
6153#endif
6154 if (!fValidOut)
6155 {
6156 LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
6157 len += RTStrPrintf(szMissingStreams + len,
6158 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
6159 }
6160
6161 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6162 N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
6163 "output or depending on audio input may hang. Make sure your host audio device "
6164 "is working properly. Check the logfile for error messages of the audio "
6165 "subsystem"), szMissingStreams);
6166 }
6167 }
6168 }
6169 }
6170
6171 if (RT_SUCCESS(rc))
6172 {
6173 hdaReset(pDevIns);
6174
6175 /*
6176 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
6177 * hdaReset shouldn't affects these registers.
6178 */
6179 HDA_REG(pThis, WAKEEN) = 0x0;
6180 HDA_REG(pThis, STATESTS) = 0x0;
6181
6182#ifdef DEBUG
6183 /*
6184 * Debug and string formatter types.
6185 */
6186 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
6187 PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaDbgInfoBDLE);
6188 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgInfoStream);
6189 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaDbgInfoCodecNodes);
6190 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaDbgInfoCodecSelector);
6191 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaDbgInfoMixer);
6192
6193 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
6194 AssertRC(rc);
6195 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
6196 AssertRC(rc);
6197 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
6198 AssertRC(rc);
6199 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
6200 AssertRC(rc);
6201 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
6202 AssertRC(rc);
6203#endif /* DEBUG */
6204
6205 /*
6206 * Some debug assertions.
6207 */
6208 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
6209 {
6210 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
6211 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
6212
6213 /* binary search order. */
6214 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
6215 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6216 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6217
6218 /* alignment. */
6219 AssertReleaseMsg( pReg->size == 1
6220 || (pReg->size == 2 && (pReg->offset & 1) == 0)
6221 || (pReg->size == 3 && (pReg->offset & 3) == 0)
6222 || (pReg->size == 4 && (pReg->offset & 3) == 0),
6223 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6224
6225 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
6226 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
6227 if (pReg->offset & 3)
6228 {
6229 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
6230 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6231 if (pPrevReg)
6232 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
6233 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6234 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
6235 }
6236#if 0
6237 if ((pReg->offset + pReg->size) & 3)
6238 {
6239 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6240 if (pNextReg)
6241 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
6242 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6243 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6244 }
6245#endif
6246 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
6247 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
6248 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6249 }
6250 }
6251
6252# ifndef VBOX_WITH_AUDIO_CALLBACKS
6253 if (RT_SUCCESS(rc))
6254 {
6255 /* Start the emulation timer. */
6256 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
6257 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
6258 AssertRCReturn(rc, rc);
6259
6260 if (RT_SUCCESS(rc))
6261 {
6262 pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
6263 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
6264 LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
6265
6266 hdaTimerMaybeStart(pThis);
6267 }
6268 }
6269# else
6270 if (RT_SUCCESS(rc))
6271 {
6272 PHDADRIVER pDrv;
6273 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6274 {
6275 /* Only register primary driver.
6276 * The device emulation does the output multiplexing then. */
6277 if (pDrv->Flags != PDMAUDIODRVFLAGS_PRIMARY)
6278 continue;
6279
6280 PDMAUDIOCALLBACK AudioCallbacks[2];
6281
6282 HDACALLBACKCTX Ctx = { pThis, pDrv };
6283
6284 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
6285 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
6286 AudioCallbacks[0].pvCtx = &Ctx;
6287 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
6288
6289 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
6290 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
6291 AudioCallbacks[1].pvCtx = &Ctx;
6292 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
6293
6294 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
6295 if (RT_FAILURE(rc))
6296 break;
6297 }
6298 }
6299# endif
6300
6301# ifdef VBOX_WITH_STATISTICS
6302 if (RT_SUCCESS(rc))
6303 {
6304 /*
6305 * Register statistics.
6306 */
6307# ifndef VBOX_WITH_AUDIO_CALLBACKS
6308 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
6309# endif
6310 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
6311 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
6312 }
6313# endif
6314
6315 LogFlowFuncLeaveRC(rc);
6316 return rc;
6317}
6318
6319/**
6320 * The device registration structure.
6321 */
6322const PDMDEVREG g_DeviceICH6_HDA =
6323{
6324 /* u32Version */
6325 PDM_DEVREG_VERSION,
6326 /* szName */
6327 "hda",
6328 /* szRCMod */
6329 "VBoxDDRC.rc",
6330 /* szR0Mod */
6331 "VBoxDDR0.r0",
6332 /* pszDescription */
6333 "Intel HD Audio Controller",
6334 /* fFlags */
6335 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
6336 /* fClass */
6337 PDM_DEVREG_CLASS_AUDIO,
6338 /* cMaxInstances */
6339 1,
6340 /* cbInstance */
6341 sizeof(HDASTATE),
6342 /* pfnConstruct */
6343 hdaConstruct,
6344 /* pfnDestruct */
6345 hdaDestruct,
6346 /* pfnRelocate */
6347 NULL,
6348 /* pfnMemSetup */
6349 NULL,
6350 /* pfnPowerOn */
6351 NULL,
6352 /* pfnReset */
6353 hdaReset,
6354 /* pfnSuspend */
6355 NULL,
6356 /* pfnResume */
6357 NULL,
6358 /* pfnAttach */
6359 hdaAttach,
6360 /* pfnDetach */
6361 hdaDetach,
6362 /* pfnQueryInterface. */
6363 NULL,
6364 /* pfnInitComplete */
6365 NULL,
6366 /* pfnPowerOff */
6367 hdaPowerOff,
6368 /* pfnSoftReset */
6369 NULL,
6370 /* u32VersionEnd */
6371 PDM_DEVREG_VERSION
6372};
6373
6374#endif /* IN_RING3 */
6375#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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