VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 37209

Last change on this file since 37209 was 37190, checked in by vboxsync, 14 years ago

Audio/HDA: loading V1 saved state. (xTracker/5704).
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1/* $Id: DevIchIntelHDA.cpp 37190 2011-05-24 03:23:48Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/vmm/pdmdev.h>
23#include <iprt/assert.h>
24#include <iprt/uuid.h>
25#include <iprt/string.h>
26#include <iprt/mem.h>
27#include <iprt/asm.h>
28#include <iprt/asm-math.h>
29
30#include "VBoxDD.h"
31
32extern "C" {
33#include "audio.h"
34}
35#include "DevCodec.h"
36
37#define VBOX_WITH_INTEL_HDA
38
39#if defined(VBOX_WITH_HP_HDA)
40/* HP Pavilion dv4t-1300 */
41# define HDA_PCI_VENDOR_ID 0x103c
42# define HDA_PCI_DEICE_ID 0x30f7
43#elif defined(VBOX_WITH_INTEL_HDA)
44/* Intel HDA controller */
45# define HDA_PCI_VENDOR_ID 0x8086
46# define HDA_PCI_DEICE_ID 0x2668
47#elif defined(VBOX_WITH_NVIDIA_HDA)
48/* nVidia HDA controller */
49# define HDA_PCI_VENDOR_ID 0x10de
50# define HDA_PCI_DEICE_ID 0x0ac0
51#else
52# error "Please specify your HDA device vendor/device IDs"
53#endif
54
55PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
56PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
57static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
58
59#define HDA_NREGS 112
60/* Registers */
61#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
62#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
63#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
64#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
65#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
66#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
67#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
68#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
69#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
70#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
71
72#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
73#define GCAP(pState) (HDA_REG((pState), GCAP))
74/* GCAP HDASpec 3.3.2 This macro compact following information about HDA
75 * oss (15:12) - number of output streams supported
76 * iss (11:8) - number of input streams supported
77 * bss (7:3) - number of bidirection streams suppoted
78 * bds (2:1) - number of serial data out signals supported
79 * b64sup (0) - 64 bit addressing supported.
80 */
81#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
82 ( (((oss) & 0xF) << 12) \
83 | (((iss) & 0xF) << 8) \
84 | (((bss) & 0x1F) << 3) \
85 | (((bds) & 0x3) << 2) \
86 | ((b64sup) & 1))
87#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
88#define VMIN(pState) (HDA_REG((pState), VMIN))
89
90#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
91#define VMAJ(pState) (HDA_REG((pState), VMAJ))
92
93#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
94#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
95
96#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
97#define INPAY(pState) (HDA_REG((pState), INPAY))
98
99#define ICH6_HDA_REG_GCTL (5)
100#define ICH6_HDA_GCTL_RST_SHIFT (0)
101#define ICH6_HDA_GCTL_FSH_SHIFT (1)
102#define ICH6_HDA_GCTL_UR_SHIFT (8)
103#define GCTL(pState) (HDA_REG((pState), GCTL))
104
105#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
106#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
107
108#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
109#define STATESTS(pState) (HDA_REG((pState), STATESTS))
110#define ICH6_HDA_STATES_SCSF 0x7
111
112#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
113#define ICH6_HDA_GSTS_FSH_SHIFT (1)
114#define GSTS(pState) (HDA_REG(pState, GSTS))
115
116#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
117#define ICH6_HDA_INTCTL_GIE_SHIFT 31
118#define ICH6_HDA_INTCTL_CIE_SHIFT 30
119#define ICH6_HDA_INTCTL_S0_SHIFT (0)
120#define ICH6_HDA_INTCTL_S1_SHIFT (1)
121#define ICH6_HDA_INTCTL_S2_SHIFT (2)
122#define ICH6_HDA_INTCTL_S3_SHIFT (3)
123#define ICH6_HDA_INTCTL_S4_SHIFT (4)
124#define ICH6_HDA_INTCTL_S5_SHIFT (5)
125#define ICH6_HDA_INTCTL_S6_SHIFT (6)
126#define ICH6_HDA_INTCTL_S7_SHIFT (7)
127#define INTCTL(pState) (HDA_REG((pState), INTCTL))
128#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
129#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
130#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
131#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
132
133/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
134 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
135 * the datasheet.
136 */
137#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
138#define SSYNC(pState) (HDA_REG((pState), SSYNC))
139
140#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
141#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
142#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
143#define ICH6_HDA_INTSTS_S0_SHIFT (0)
144#define ICH6_HDA_INTSTS_S1_SHIFT (1)
145#define ICH6_HDA_INTSTS_S2_SHIFT (2)
146#define ICH6_HDA_INTSTS_S3_SHIFT (3)
147#define ICH6_HDA_INTSTS_S4_SHIFT (4)
148#define ICH6_HDA_INTSTS_S5_SHIFT (5)
149#define ICH6_HDA_INTSTS_S6_SHIFT (6)
150#define ICH6_HDA_INTSTS_S7_SHIFT (7)
151#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
152#define INTSTS(pState) (HDA_REG((pState), INTSTS))
153#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
154#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
155#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
156#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
157
158#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
159#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
160#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
161#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
162#define ICH6_HDA_REG_CORBWP 15 /* 48 */
163#define ICH6_HDA_REG_CORBRP 16 /* 4A */
164#define ICH6_HDA_CORBRP_RST_SHIFT 15
165#define ICH6_HDA_CORBRP_WP_SHIFT 0
166#define ICH6_HDA_CORBRP_WP_MASK 0xFF
167
168#define CORBRP(pState) (HDA_REG(pState, CORBRP))
169#define CORBWP(pState) (HDA_REG(pState, CORBWP))
170
171#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
172#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
173#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
174
175#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
176
177
178#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
179#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
180#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
181
182#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
183#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
184#define ICH6_HDA_CORBSIZE_SZ 0x3
185#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
186#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
187/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
188
189#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
190#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
191
192#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
193#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
194
195#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
196#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
197#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
198#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
199
200#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
201#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
202#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
203
204#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
205#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
206#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
207#define ICH6_HDA_ROI_DMA_SHIFT (2)
208#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
209#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
210#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
211#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
212
213#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
214#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
215#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
216#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
217#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
218#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
219
220#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
221#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
222#define ICH6_HDA_RIRBSIZE_SZ 0x3
223
224#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
225#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
226
227
228#define ICH6_HDA_REG_IC 27 /* 0x60 */
229#define IC(pState) (HDA_REG(pState, IC))
230#define ICH6_HDA_REG_IR 28 /* 0x64 */
231#define IR(pState) (HDA_REG(pState, IR))
232#define ICH6_HDA_REG_IRS 29 /* 0x68 */
233#define ICH6_HDA_IRS_ICB_SHIFT (0)
234#define ICH6_HDA_IRS_IRV_SHIFT (1)
235#define IRS(pState) (HDA_REG(pState, IRS))
236#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
237#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
238
239#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
240#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
241#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
242#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
243#define DPBASE_ENABLED 1
244#define DPBASE_ADDR_MASK (~0x7f)
245
246#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
247#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
248/* Note: sdnum here _MUST_ be stream reg number [0,7] */
249#define HDA_STREAM_REG2(pState, name, sdnum) (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
250
251#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
252#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
253#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
254#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
255#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
256#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
257#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
258#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
259
260#define SD(func, num) SD##num##func
261#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
262#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
263#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
264#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
265#define ICH6_HDA_SDCTL_DIR_SHIFT (19)
266#define ICH6_HDA_SDCTL_TP_SHIFT (18)
267#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)
268#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)
269#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
270#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
271#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
272#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
273#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
274
275#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
276#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
277#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
278#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
279#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
280#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
281#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
282#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
283
284#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
285#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
286#define ICH6_HDA_SDSTS_DE_SHIFT (4)
287#define ICH6_HDA_SDSTS_FE_SHIFT (3)
288#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
289
290#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
291#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
292#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
293#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
294#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
295#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
296#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
297#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
298
299#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
300
301#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
302#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
303#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
304#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
305#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
306#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
307#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
308#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
309
310#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
311
312#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
313#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
314#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
315#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
316#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
317#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
318#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
319#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
320
321#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
322
323#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
324#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
325#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
326#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
327#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
328#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
329#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
330#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
331
332/*
333 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
334 */
335#define HDA_SDFIFOW_8B (0x2)
336#define HDA_SDFIFOW_16B (0x3)
337#define HDA_SDFIFOW_32B (0x4)
338#define SDFIFOW(pState, num) HDA_REG((pState), SD(FIFOW, num))
339
340#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
341#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
342#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
343#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
344#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
345#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
346#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
347#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
348
349/*
350 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
351 * formula: size - 1
352 * Other values not listed are not supported.
353 */
354#define HDA_SDONFIFO_16B (0xF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
355#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
356#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
357#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
358#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
359#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
360#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
361#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
362#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
363
364#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
365#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
366#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
367#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
368#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
369#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
370#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
371#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
372
373#define SDFMT(pState, num) (HDA_REG((pState), SD(FMT, num)))
374#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
375#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
376#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
377#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
378#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
379#define ICH6_HDA_SDFMT_BITS_SHIFT (4)
380#define ICH6_HDA_SDFMT_BITS_MASK (0x7)
381#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
382#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
383#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
384
385#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
386#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
387#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
388#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
389#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
390#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
391#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
392#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
393
394#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
395
396#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
397#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
398#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
399#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
400#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
401#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
402#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
403#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
404
405#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
406
407/* Predicates */
408
409typedef struct HDABDLEDESC
410{
411 uint64_t u64BdleCviAddr;
412 uint32_t u32BdleMaxCvi;
413 uint32_t u32BdleCvi;
414 uint32_t u32BdleCviLen;
415 uint32_t u32BdleCviPos;
416 bool fBdleCviIoc;
417 uint32_t cbUnderFifoW;
418 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
419} HDABDLEDESC, *PHDABDLEDESC;
420
421typedef struct HDASTREAMTRANSFERDESC
422{
423 uint64_t u64BaseDMA;
424 uint32_t u32Ctl;
425 uint32_t *pu32Sts;
426 uint8_t u8Strm;
427 uint32_t *pu32Lpib;
428 uint32_t u32Cbl;
429 uint32_t u32Fifos;
430} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
431
432typedef struct INTELHDLinkState
433{
434 /** Pointer to the device instance. */
435 PPDMDEVINSR3 pDevIns;
436 /** Pointer to the connector of the attached audio driver. */
437 PPDMIAUDIOCONNECTOR pDrv;
438 /** Pointer to the attached audio driver. */
439 PPDMIBASE pDrvBase;
440 /** The base interface for LUN\#0. */
441 PDMIBASE IBase;
442 RTGCPHYS addrMMReg;
443 uint32_t au32Regs[HDA_NREGS];
444 HDABDLEDESC stInBdle;
445 HDABDLEDESC stOutBdle;
446 HDABDLEDESC stMicBdle;
447 /* Interrupt on completion */
448 bool fCviIoc;
449 uint64_t u64CORBBase;
450 uint64_t u64RIRBBase;
451 uint64_t u64DPBase;
452 /* pointer on CORB buf */
453 uint32_t *pu32CorbBuf;
454 /* size in bytes of CORB buf */
455 uint32_t cbCorbBuf;
456 /* pointer on RIRB buf */
457 uint64_t *pu64RirbBuf;
458 /* size in bytes of RIRB buf */
459 uint32_t cbRirbBuf;
460 /* indicates if HDA in reset. */
461 bool fInReset;
462 CODECState Codec;
463 uint8_t u8Counter;
464 uint64_t u64BaseTS;
465} INTELHDLinkState, *PINTELHDLinkState;
466
467#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
468#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
469
470#define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In, \
471 SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
472#define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out, \
473 SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
474
475
476
477
478typedef struct PCIINTELHDLinkState
479{
480 PCIDevice dev;
481 INTELHDLinkState hda;
482} PCIINTELHDLinkState;
483
484
485DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
486DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
487DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
488DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
489DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
490DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
491DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
492DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
493DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
494DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
495DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
496DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
497DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
498DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
499DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
500DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
501DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
502DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
503DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
504DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
505
506DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
507DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
508DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
509DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
510DECLCALLBACK(int)hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
511DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
512DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
513DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
514DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
515DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
516DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
517DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
518DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
519DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
520DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
521DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
522
523static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc);
524static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
525static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
526#ifdef LOG_ENABLED
527static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
528#endif
529
530
531/* see 302349 p 6.2*/
532const static struct stIchIntelHDRegMap
533{
534 /** Register offset in the register space. */
535 uint32_t offset;
536 /** Size in bytes. Registers of size > 4 are in fact tables. */
537 uint32_t size;
538 /** Readable bits. */
539 uint32_t readable;
540 /** Writable bits. */
541 uint32_t writable;
542 /** Read callback. */
543 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
544 /** Write callback. */
545 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
546 /** Abbreviated name. */
547 const char *abbrev;
548 /** Full name. */
549 const char *name;
550} s_ichIntelHDRegMap[HDA_NREGS] =
551{
552 /* offset size read mask write mask read callback write callback abbrev full name */
553 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
554 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
555 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
556 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
557 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
558 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
559 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
560 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
561 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
562 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
563 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
564 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
565 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
566 //** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
567 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
568 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
569 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
570 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
571 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
572 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
573 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
574 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
575 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
576 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
577 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
578 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
579 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
580 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
581 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
582 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
583 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
584 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
585 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
586 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
587
588 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
589 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
590 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
591 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
592 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
593 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
594 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
595 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
596 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
597 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
598
599 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
600 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
601 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
602 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
603 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
604 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
605 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
606 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
607 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
608 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
609
610 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
611 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
612 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
613 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
614 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
615 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
616 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
617 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
618 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
619 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
620
621 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
622 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
623 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
624 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
625 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
626 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
627 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
628 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
629 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
630 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
631
632 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
633 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
634 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
635 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
636 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
637 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
638 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
639 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
640 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
641 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
642
643 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
644 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
645 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
646 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
647 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
648 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
649 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
650 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
651 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
652 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
653
654 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
655 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
656 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
657 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
658 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
659 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
660 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
661 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
662 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
663 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
664
665 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
666 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
667 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
668 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
669 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
670 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
671 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
672 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
673 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
674 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
675};
676
677static void inline hdaUpdatePosBuf(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
678{
679 if (pState->u64DPBase & DPBASE_ENABLED)
680 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
681 (pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
682}
683static uint32_t inline hdaFifoWToSz(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
684{
685#if 0
686 switch(HDA_STREAM_REG2(pState, FIFOW, pStreamDesc->u8Strm))
687 {
688 case HDA_SDFIFOW_8B: return 8;
689 case HDA_SDFIFOW_16B: return 16;
690 case HDA_SDFIFOW_32B: return 32;
691 default:
692 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
693 }
694#endif
695 return 0;
696}
697
698static int hdaProcessInterrupt(INTELHDLinkState* pState)
699{
700#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
701 ( INTCTL_SX((pState), num) \
702 && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
703 bool fIrq = false;
704 if ( INTCTL_CIE(pState)
705 && ( RIRBSTS_RINTFL(pState)
706 || RIRBSTS_RIRBOIS(pState)
707 || (STATESTS(pState) & WAKEEN(pState))))
708 fIrq = true;
709
710 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
711 || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
712 fIrq = true;
713
714 if (INTCTL_GIE(pState))
715 {
716 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
717 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
718 }
719 return VINF_SUCCESS;
720}
721
722static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
723{
724 int index = 0;
725 //** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
726 for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
727 {
728 if ( u32Offset >= s_ichIntelHDRegMap[index].offset
729 && u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
730 {
731 return index;
732 }
733 }
734 /* Aliases HDA spec 3.3.45 */
735 switch(u32Offset)
736 {
737 case 0x2084:
738 return HDA_REG_IND_NAME(SD0LPIB);
739 case 0x20A4:
740 return HDA_REG_IND_NAME(SD1LPIB);
741 case 0x20C4:
742 return HDA_REG_IND_NAME(SD2LPIB);
743 case 0x20E4:
744 return HDA_REG_IND_NAME(SD3LPIB);
745 case 0x2104:
746 return HDA_REG_IND_NAME(SD4LPIB);
747 case 0x2124:
748 return HDA_REG_IND_NAME(SD5LPIB);
749 case 0x2144:
750 return HDA_REG_IND_NAME(SD6LPIB);
751 case 0x2164:
752 return HDA_REG_IND_NAME(SD7LPIB);
753 }
754 return -1;
755}
756
757static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
758{
759 int rc = VINF_SUCCESS;
760 if (fLocal)
761 {
762 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
763 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
764 if (RT_FAILURE(rc))
765 AssertRCReturn(rc, rc);
766#ifdef DEBUG_CMD_BUFFER
767 uint8_t i = 0;
768 do
769 {
770 Log(("hda: corb%02x: ", i));
771 uint8_t j = 0;
772 do
773 {
774 const char *prefix;
775 if ((i + j) == CORBRP(pState))
776 prefix = "[R]";
777 else if ((i + j) == CORBWP(pState))
778 prefix = "[W]";
779 else
780 prefix = " "; /* three spaces */
781 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
782 j++;
783 } while (j < 8);
784 Log(("\n"));
785 i += 8;
786 } while(i != 0);
787#endif
788 }
789 else
790 {
791 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
792 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
793 if (RT_FAILURE(rc))
794 AssertRCReturn(rc, rc);
795#ifdef DEBUG_CMD_BUFFER
796 uint8_t i = 0;
797 do {
798 Log(("hda: rirb%02x: ", i));
799 uint8_t j = 0;
800 do {
801 const char *prefix;
802 if ((i + j) == RIRBWP(pState))
803 prefix = "[W]";
804 else
805 prefix = " ";
806 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
807 } while (++j < 8);
808 Log(("\n"));
809 i += 8;
810 } while (i != 0);
811#endif
812 }
813 return rc;
814}
815
816static int hdaCORBCmdProcess(INTELHDLinkState *pState)
817{
818 int rc;
819 uint8_t corbRp;
820 uint8_t corbWp;
821 uint8_t rirbWp;
822
823 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
824
825 rc = hdaCmdSync(pState, true);
826 if (RT_FAILURE(rc))
827 AssertRCReturn(rc, rc);
828 corbRp = CORBRP(pState);
829 corbWp = CORBWP(pState);
830 rirbWp = RIRBWP(pState);
831 Assert((corbWp != corbRp));
832 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
833 while (corbRp != corbWp)
834 {
835 uint32_t cmd;
836 uint64_t resp;
837 corbRp++;
838 cmd = pState->pu32CorbBuf[corbRp];
839 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
840 if (RT_FAILURE(rc))
841 AssertRCReturn(rc, rc);
842 Assert(pfn);
843 (rirbWp)++;
844 rc = pfn(&pState->Codec, cmd, &resp);
845 if (RT_FAILURE(rc))
846 AssertRCReturn(rc, rc);
847 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
848 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
849 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
850 {
851 Log(("hda: unexpected unsolicited response.\n"));
852 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
853 return rc;
854 }
855 pState->pu64RirbBuf[rirbWp] = resp;
856 pState->u8Counter++;
857 if (pState->u8Counter == RINTCNT_N(pState))
858 break;
859 }
860 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
861 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
862 rc = hdaCmdSync(pState, false);
863 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
864 if (RIRBCTL_RIRB_RIC(pState))
865 {
866 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
867 pState->u8Counter = 0;
868 rc = hdaProcessInterrupt(pState);
869 }
870 if (RT_FAILURE(rc))
871 AssertRCReturn(rc, rc);
872 return rc;
873}
874
875static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
876{
877 Log(("hda: reset of stream (%d) started\n", u8Strm));
878 Assert(( pState
879 && pBdle
880 && pStreamDesc
881 && u8Strm <= 7));
882 memset(pBdle, 0, sizeof(HDABDLEDESC));
883 *pStreamDesc->pu32Lpib = 0;
884 *pStreamDesc->pu32Sts = 0;
885 /* According to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
886 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
887 HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
888
889 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
890 HDA_STREAM_REG2(pState, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
891 HDA_STREAM_REG2(pState, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
892 HDA_STREAM_REG2(pState, CBL, u8Strm) = 0;
893 HDA_STREAM_REG2(pState, LVI, u8Strm) = 0;
894 HDA_STREAM_REG2(pState, FMT, u8Strm) = 0;
895 HDA_STREAM_REG2(pState, BDPU, u8Strm) = 0;
896 HDA_STREAM_REG2(pState, BDPL, u8Strm) = 0;
897 Log(("hda: reset of stream (%d) finished\n", u8Strm));
898}
899
900
901DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
902{
903 *pu32Value = 0;
904 return VINF_SUCCESS;
905}
906DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
907{
908 return VINF_SUCCESS;
909}
910/* U8 */
911DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
912{
913 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
914 return hdaRegReadU32(pState, offset, index, pu32Value);
915}
916
917DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
918{
919 Assert(((u32Value & 0xffffff00) == 0));
920 return hdaRegWriteU32(pState, offset, index, u32Value);
921}
922/* U16 */
923DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
924{
925 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
926 return hdaRegReadU32(pState, offset, index, pu32Value);
927}
928
929DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
930{
931 Assert(((u32Value & 0xffff0000) == 0));
932 return hdaRegWriteU32(pState, offset, index, u32Value);
933}
934
935/* U24 */
936DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
937{
938 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
939 return hdaRegReadU32(pState, offset, index, pu32Value);
940}
941
942DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
943{
944 Assert(((u32Value & 0xff000000) == 0));
945 return hdaRegWriteU32(pState, offset, index, u32Value);
946}
947/* U32 */
948DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
949{
950 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
951 return VINF_SUCCESS;
952}
953
954DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
955{
956 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
957 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
958 return VINF_SUCCESS;
959}
960
961DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
962{
963 return hdaRegReadU32(pState, offset, index, pu32Value);
964}
965
966DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
967{
968 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
969 {
970 /* exit reset state */
971 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
972 pState->fInReset = false;
973 }
974 else
975 {
976 /* enter reset state*/
977 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
978 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
979 {
980 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
981 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
982 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
983 }
984 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
985 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
986 pState->fInReset = true;
987 }
988 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
989 {
990 /* Flush: GSTS:1 set, see 6.2.6*/
991 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
992 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
993 }
994 return VINF_SUCCESS;
995}
996
997DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
998{
999 uint32_t v = pState->au32Regs[index];
1000 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
1001 pState->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
1002 return VINF_SUCCESS;
1003}
1004
1005DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1006{
1007 uint32_t v = 0;
1008 if ( RIRBSTS_RIRBOIS(pState)
1009 || RIRBSTS_RINTFL(pState)
1010 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
1011 || STATESTS(pState))
1012 v |= RT_BIT(30);
1013#define HDA_IS_STREAM_EVENT(pState, stream) \
1014 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1015 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1016 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1017#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
1018 MARK_STREAM(pState, 0, v);
1019 MARK_STREAM(pState, 1, v);
1020 MARK_STREAM(pState, 2, v);
1021 MARK_STREAM(pState, 3, v);
1022 MARK_STREAM(pState, 4, v);
1023 MARK_STREAM(pState, 5, v);
1024 MARK_STREAM(pState, 6, v);
1025 MARK_STREAM(pState, 7, v);
1026 v |= v ? RT_BIT(31) : 0;
1027 *pu32Value = v;
1028 return VINF_SUCCESS;
1029}
1030
1031DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1032{
1033 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1034 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pState)) - pState->u64BaseTS, 24, 1000);
1035 return VINF_SUCCESS;
1036}
1037
1038DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1039{
1040 return hdaRegReadU16(pState, offset, index, pu32Value);
1041}
1042
1043DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1044{
1045 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1046 CORBRP(pState) = 0;
1047 else
1048 return hdaRegWriteU8(pState, offset, index, u32Value);
1049 return VINF_SUCCESS;
1050}
1051
1052DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1053{
1054 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
1055 AssertRC(rc);
1056 if ( CORBWP(pState) != CORBRP(pState)
1057 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
1058 return hdaCORBCmdProcess(pState);
1059 return rc;
1060}
1061
1062DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1063{
1064 uint32_t v = CORBSTS(pState);
1065 CORBSTS(pState) &= ~(v & u32Value);
1066 return VINF_SUCCESS;
1067}
1068
1069DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1070{
1071 int rc;
1072 rc = hdaRegWriteU16(pState, offset, index, u32Value);
1073 if (RT_FAILURE(rc))
1074 AssertRCReturn(rc, rc);
1075 if (CORBWP(pState) == CORBRP(pState))
1076 return VINF_SUCCESS;
1077 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1078 return VINF_SUCCESS;
1079 rc = hdaCORBCmdProcess(pState);
1080 return rc;
1081}
1082
1083DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1084{
1085 return hdaRegReadU24(pState, offset, index, pu32Value);
1086}
1087
1088DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1089{
1090 bool fRun = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1091 bool fInRun = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1092 bool fReset = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1093 bool fInReset = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1094 int rc = VINF_SUCCESS;
1095 if (fInReset)
1096 {
1097 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1098 * from reset
1099 */
1100 Assert((!fReset));
1101 Log(("hda: guest initiate exit of stream reset.\n"));
1102 goto done;
1103 }
1104 else if (fReset)
1105 {
1106 /*
1107 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1108 */
1109 uint8_t u8Strm = 0;
1110 PHDABDLEDESC pBdle = NULL;
1111 HDASTREAMTRANSFERDESC stStreamDesc;
1112 Assert((!fInRun && !fRun));
1113 switch (index)
1114 {
1115 case ICH6_HDA_REG_SD0CTL:
1116 u8Strm = 0;
1117 pBdle = &pState->stInBdle;
1118 break;
1119 case ICH6_HDA_REG_SD4CTL:
1120 u8Strm = 4;
1121 pBdle = &pState->stOutBdle;
1122 break;
1123 default:
1124 Log(("hda: changing SRST bit on non-attached stream\n"));
1125 goto done;
1126 }
1127 Log(("hda: guest initiate enter to stream reset.\n"));
1128 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1129 hdaStreamReset(pState, pBdle, &stStreamDesc, u8Strm);
1130 goto done;
1131 }
1132
1133 /* we enter here to change DMA states only */
1134 if ( (fInRun && !fRun)
1135 || (fRun && !fInRun))
1136 {
1137 Assert((!fReset && !fInReset));
1138 switch (index)
1139 {
1140 case ICH6_HDA_REG_SD0CTL:
1141 AUD_set_active_in(pState->Codec.SwVoiceIn, fRun);
1142 break;
1143 case ICH6_HDA_REG_SD4CTL:
1144 AUD_set_active_out(pState->Codec.SwVoiceOut, fRun);
1145 break;
1146 default:
1147 Log(("hda: changing RUN bit on non-attached stream\n"));
1148 goto done;
1149 }
1150 }
1151
1152 done:
1153 rc = hdaRegWriteU24(pState, offset, index, u32Value);
1154 if (RT_FAILURE(rc))
1155 AssertRCReturn(rc, VINF_SUCCESS);
1156 return rc;
1157}
1158
1159DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1160{
1161 uint32_t v = HDA_REG_IND(pState, index);
1162 v &= ~(u32Value & v);
1163 HDA_REG_IND(pState, index) = v;
1164 hdaProcessInterrupt(pState);
1165 return VINF_SUCCESS;
1166}
1167
1168DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1169{
1170 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1171 if (RT_FAILURE(rc))
1172 AssertRCReturn(rc, VINF_SUCCESS);
1173 return rc;
1174}
1175
1176DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1177{
1178 switch (u32Value)
1179 {
1180 case HDA_SDFIFOW_8B:
1181 case HDA_SDFIFOW_16B:
1182 case HDA_SDFIFOW_32B:
1183 return hdaRegWriteU16(pState, offset, index, u32Value);
1184 default:
1185 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1186 return hdaRegWriteU16(pState, offset, index, HDA_SDFIFOW_32B);
1187 }
1188 return VINF_SUCCESS;
1189}
1190/*
1191 * Note this method could be called for changing value on Output Streams only (ICH6 datacheet 18.2.39)
1192 *
1193 */
1194DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1195{
1196 switch (index)
1197 {
1198 /* SDInFIFOS is RO, n=0-3 */
1199 case ICH6_HDA_REG_SD0FIFOS:
1200 case ICH6_HDA_REG_SD1FIFOS:
1201 case ICH6_HDA_REG_SD2FIFOS:
1202 case ICH6_HDA_REG_SD3FIFOS:
1203 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1204 return VINF_SUCCESS;
1205 case ICH6_HDA_REG_SD4FIFOS:
1206 case ICH6_HDA_REG_SD5FIFOS:
1207 case ICH6_HDA_REG_SD6FIFOS:
1208 case ICH6_HDA_REG_SD7FIFOS:
1209 switch(u32Value)
1210 {
1211 case HDA_SDONFIFO_16B:
1212 case HDA_SDONFIFO_32B:
1213 case HDA_SDONFIFO_64B:
1214 case HDA_SDONFIFO_128B:
1215 case HDA_SDONFIFO_192B:
1216 return hdaRegWriteU16(pState, offset, index, u32Value);
1217
1218 case HDA_SDONFIFO_256B:
1219 Log(("hda: 256 bit is unsupported, HDA is switched into 192B mode\n"));
1220 default:
1221 return hdaRegWriteU16(pState, offset, index, HDA_SDONFIFO_192B);
1222 }
1223 return VINF_SUCCESS;
1224 default:
1225 AssertMsgFailed(("Something wierd happens with register lookup routine"));
1226 }
1227 return VINF_SUCCESS;
1228}
1229
1230static void inline hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1231{
1232 Assert((pAudSetting));
1233#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1234 uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1235 uint32_t u32HzMult = 1;
1236 uint32_t u32HzDiv = 1;
1237 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))
1238 {
1239 case 0: u32HzMult = 1; break;
1240 case 1: u32HzMult = 2; break;
1241 case 2: u32HzMult = 3; break;
1242 case 3: u32HzMult = 4; break;
1243 default:
1244 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1245 }
1246 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))
1247 {
1248 case 0: u32HzDiv = 1; break;
1249 case 1: u32HzDiv = 2; break;
1250 case 2: u32HzDiv = 3; break;
1251 case 3: u32HzDiv = 4; break;
1252 case 4: u32HzDiv = 5; break;
1253 case 5: u32HzDiv = 6; break;
1254 case 6: u32HzDiv = 7; break;
1255 case 7: u32HzDiv = 8; break;
1256 }
1257 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1258
1259 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_BITS_MASK, ICH6_HDA_SDFMT_BITS_SHIFT))
1260 {
1261 case 0:
1262 Log(("hda: %s requested 8 bit\n", __FUNCTION__));
1263 pAudSetting->fmt = AUD_FMT_S8;
1264 break;
1265 case 1:
1266 Log(("hda: %s requested 16 bit\n", __FUNCTION__));
1267 pAudSetting->fmt = AUD_FMT_S16;
1268 break;
1269 case 2:
1270 Log(("hda: %s requested 20 bit\n", __FUNCTION__));
1271 break;
1272 case 3:
1273 Log(("hda: %s requested 24 bit\n", __FUNCTION__));
1274 break;
1275 case 4:
1276 Log(("hda: %s requested 32 bit\n", __FUNCTION__));
1277 pAudSetting->fmt = AUD_FMT_S32;
1278 break;
1279 default:
1280 AssertMsgFailed(("Unsupported"));
1281 }
1282 pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;
1283 pAudSetting->fmt = AUD_FMT_S16;
1284 pAudSetting->endianness = 0;
1285#undef EXTRACT_VALUE
1286}
1287
1288DECLCALLBACK(int)hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1289{
1290#ifdef VBOX_WITH_HDA_CODEC_EMU
1291 /* @todo here some more investigations are required. */
1292 int rc = 0;
1293 audsettings_t as;
1294 /* no reason to reopen voice with same settings */
1295 if (u32Value == HDA_REG_IND(pState, index))
1296 return VINF_SUCCESS;
1297 hdaSdFmtToAudSettings(u32Value, &as);
1298 switch (index)
1299 {
1300 case ICH6_HDA_REG_SD0FMT:
1301 rc = codecOpenVoice(&pState->Codec, PI_INDEX, &as);
1302 break;
1303 case ICH6_HDA_REG_SD4FMT:
1304 rc = codecOpenVoice(&pState->Codec, PO_INDEX, &as);
1305 break;
1306 default:
1307 Log(("HDA: attempt to change format on %d\n", index));
1308 rc = 0;
1309 }
1310 return hdaRegWriteU16(pState, offset, index, u32Value);
1311#else
1312 return hdaRegWriteU16(pState, offset, index, u32Value);
1313#endif
1314}
1315
1316DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1317{
1318 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1319 if (RT_FAILURE(rc))
1320 AssertRCReturn(rc, VINF_SUCCESS);
1321 return rc;
1322}
1323
1324DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1325{
1326 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1327 if (RT_FAILURE(rc))
1328 AssertRCReturn(rc, VINF_SUCCESS);
1329 return rc;
1330}
1331
1332DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1333{
1334 int rc = VINF_SUCCESS;
1335 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1336 if ( CORBWP(pState) != CORBRP(pState)
1337 || HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1338 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1339
1340 rc = hdaRegReadU32(pState, offset, index, pu32Value);
1341 return rc;
1342}
1343
1344DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1345{
1346 int rc = VINF_SUCCESS;
1347 uint64_t resp;
1348 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1349 /*
1350 * if guest set ICB bit of IRS register HDA should process verb in IC register and
1351 * writes response in IR register and set IRV (valid in case of success) bit of IRS register.
1352 */
1353 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1354 && !IRS_ICB(pState))
1355 {
1356 uint32_t cmd = IC(pState);
1357 if (CORBWP(pState) != CORBRP(pState))
1358 {
1359 /*
1360 * 3.4.3 defines behaviour of immediate Command status register.
1361 */
1362 LogRel(("hda: guest has tried process immediate verb (%x) with active CORB\n", cmd));
1363 return rc;
1364 }
1365 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1366 Log(("hda: IC:%x\n", cmd));
1367 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1368 if (RT_FAILURE(rc))
1369 AssertRCReturn(rc, rc);
1370 rc = pfn(&pState->Codec, cmd, &resp);
1371 if (RT_FAILURE(rc))
1372 AssertRCReturn(rc, rc);
1373 IR(pState) = (uint32_t)resp;
1374 Log(("hda: IR:%x\n", IR(pState)));
1375 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1376 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1377 return rc;
1378 }
1379 /*
1380 * when guest's read the response it should clean the IRV bit of the IRS register.
1381 */
1382 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1383 && IRS_IRV(pState))
1384 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1385 return rc;
1386}
1387
1388DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1389{
1390 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1391 {
1392 RIRBWP(pState) = 0;
1393 }
1394 /*The rest of bits are O, see 6.2.22 */
1395 return VINF_SUCCESS;
1396}
1397
1398DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1399{
1400 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1401 if (RT_FAILURE(rc))
1402 AssertRCReturn(rc, rc);
1403 switch(index)
1404 {
1405 case ICH6_HDA_REG_CORBLBASE:
1406 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1407 pState->u64CORBBase |= pState->au32Regs[index];
1408 break;
1409 case ICH6_HDA_REG_CORBUBASE:
1410 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1411 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1412 break;
1413 case ICH6_HDA_REG_RIRLBASE:
1414 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1415 pState->u64RIRBBase |= pState->au32Regs[index];
1416 break;
1417 case ICH6_HDA_REG_RIRUBASE:
1418 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1419 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1420 break;
1421 case ICH6_HDA_REG_DPLBASE:
1422 /* @todo: first bit has special meaning */
1423 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1424 pState->u64DPBase |= pState->au32Regs[index];
1425 break;
1426 case ICH6_HDA_REG_DPUBASE:
1427 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1428 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1429 break;
1430 default:
1431 AssertMsgFailed(("Invalid index"));
1432 }
1433 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1434 return rc;
1435}
1436
1437DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1438{
1439 uint8_t v = RIRBSTS(pState);
1440 RIRBSTS(pState) &= ~(v & u32Value);
1441
1442 return hdaProcessInterrupt(pState);
1443}
1444
1445#ifdef LOG_ENABLED
1446static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1447{
1448#if 0
1449 uint64_t addr;
1450 uint32_t len;
1451 uint32_t ioc;
1452 uint8_t bdle[16];
1453 uint32_t counter;
1454 uint32_t i;
1455 uint32_t sum = 0;
1456 Assert(pBdle && pBdle->u32BdleMaxCvi);
1457 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1458 {
1459 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1460 addr = *(uint64_t *)bdle;
1461 len = *(uint32_t *)&bdle[8];
1462 ioc = *(uint32_t *)&bdle[12];
1463 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1464 sum += len;
1465 }
1466 Log(("hda: sum: %d\n", sum));
1467 for (i = 0; i < 8; ++i)
1468 {
1469 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1470 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
1471 i , counter));
1472 }
1473#endif
1474}
1475#endif
1476
1477static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1478{
1479 uint8_t bdle[16];
1480 Assert(( pStreamDesc->u64BaseDMA
1481 && pBdle
1482 && pBdle->u32BdleMaxCvi));
1483 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1484 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1485 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1486 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1487#ifdef LOG_ENABLED
1488 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1489#endif
1490}
1491
1492static inline uint32_t hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1493{
1494 uint32_t cb2Copy;
1495 /*
1496 * Amounts of bytes depends on current position in buffer (u32BdleCviLen-u32BdleCviPos)
1497 */
1498 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1499 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1500 /*
1501 * we may increase the counter in range of [0, FIFOS + 1]
1502 */
1503 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1504 Assert((u32SoundBackendBufferBytesAvail > 0));
1505
1506 /* sanity check to avoid overriding sound backend buffer */
1507 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1508 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1509
1510 if (cb2Copy <= pBdle->cbUnderFifoW)
1511 return 0;
1512 cb2Copy -= pBdle->cbUnderFifoW; /* forcely reserve amount of ureported bytes to copy */
1513 return cb2Copy;
1514}
1515
1516static inline void hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1517{
1518 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1519 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1520 Assert((cbCopied));
1521 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1522 /* Assertion!!! It was copied less than cbUnderFifoW
1523 * Probably we need to move the buffer, but it rather hard to imagine situation
1524 * why it may happen.
1525 */
1526 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write whole buffer including not reported bytes */
1527 if ( pBdle->cbUnderFifoW
1528 && pBdle->cbUnderFifoW <= cbCopied)
1529 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1530
1531 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1532 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Assumption failed */
1533
1534 /* We always increment position on DMA buffer counter because we're always reading to intermediate buffer */
1535 pBdle->u32BdleCviPos += cbArranged2Copy;
1536
1537 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1538 /* We reports all bytes (including unreported previously) */
1539 *pu32DMACursor += cbCopied;
1540 /* reducing backend counter on amount of bytes we copied to backend */
1541 *pu32BackendBufferCapacity -= cbCopied;
1542 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1543 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1544}
1545
1546static inline void hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1547{
1548 Assert((cbCopied, cbArranged2Copy));
1549 *pu32BackendBufferCapacity -= cbCopied;
1550 pBdle->u32BdleCviPos += cbCopied;
1551 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1552 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1553 pBdle->cbUnderFifoW = 0;
1554 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1555 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1556}
1557
1558static inline void hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1559{
1560 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1561 pBdle->u32BdleCviPos += cbCopied;
1562 pBdle->cbUnderFifoW += cbCopied;
1563 /* In case of read transaction we're always coping from backend buffer */
1564 if (pu32BackendBufferCapacity)
1565 *pu32BackendBufferCapacity -= cbCopied;
1566 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1567 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pState, pStreamDesc)));
1568}
1569static inline bool hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1570{
1571 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1572 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1573
1574 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1575
1576 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1577 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1578 hdaUpdatePosBuf(pState, pStreamDesc);
1579
1580 /* don't touch BdleCvi counter on uninitialized descriptor */
1581 if ( pBdle->u32BdleCviPos
1582 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1583 {
1584 pBdle->u32BdleCviPos = 0;
1585 pBdle->u32BdleCvi++;
1586 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1587 pBdle->u32BdleCvi = 0;
1588 }
1589 return fOnBufferEdge;
1590}
1591
1592static inline void hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbInc)
1593{
1594 /*
1595 * if we're under FIFO Watermark it's expected that HDA doesn't fetch anything.
1596 * (ICH6 datasheet 18.2.38)
1597 */
1598 if (!pBdle->cbUnderFifoW)
1599 {
1600 *pStreamDesc->pu32Lpib += cbInc;
1601
1602 /*
1603 * Assert. Overlapping of buffer counter shouldn't happen.
1604 */
1605 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1606
1607 hdaUpdatePosBuf(pState, pStreamDesc);
1608
1609 }
1610}
1611
1612static inline bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1613{
1614 bool fDoNextTransferLoop = true;
1615 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1616 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1617 {
1618 if ( !pBdle->cbUnderFifoW
1619 && pBdle->fBdleCviIoc)
1620 {
1621 /*
1622 * @todo - more carefully investigate BCIS flag.
1623 * Speech synthesis works fine on Mac Guest if this bit isn't set
1624 * but in general sound quality becomes lesser.
1625 */
1626 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1627
1628 /*
1629 * we should generate the interrupt if ICE bit of SDCTL register is set.
1630 */
1631 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1632 hdaProcessInterrupt(pState);
1633 }
1634 fDoNextTransferLoop = false;
1635 }
1636 return fDoNextTransferLoop;
1637}
1638
1639/*
1640 * hdaReadAudio - copies samples from Qemu Sound back-end to DMA.
1641 * Note: this function writes immediately to DMA buffer, but "reports bytes" when all conditions meet (FIFOW)
1642 */
1643static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1644{
1645 PHDABDLEDESC pBdle = &pState->stInBdle;
1646 uint32_t cbTransfered = 0;
1647 uint32_t cb2Copy = 0;
1648 uint32_t cbBackendCopy = 0;
1649
1650 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1651
1652 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1653 if (!cb2Copy)
1654 {
1655 /* if we enter here we can't report "unreported bits" */
1656 *fStop = true;
1657 goto done;
1658 }
1659
1660
1661 /*
1662 * read from backend input line to last ureported position or at the begining.
1663 */
1664 cbBackendCopy = AUD_read (pState->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1665 /*
1666 * write on the HDA DMA
1667 */
1668 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1669
1670 /* Don't see reasons why cb2Copy could differ from cbBackendCopy */
1671 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1672
1673 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pState, 0))
1674 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1675 else
1676 {
1677 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1678 *fStop = true;
1679 }
1680 done:
1681 Assert((cbTransfered <= (SDFIFOS(pState, 0) + 1)));
1682 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransfered: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1683 return cbTransfered;
1684}
1685
1686static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1687{
1688 PHDABDLEDESC pBdle = &pState->stOutBdle;
1689 uint32_t cbTransfered = 0;
1690 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1691 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1692
1693 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1694
1695 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1696
1697 /*
1698 * Copy from DMA to the corresponding hdaBuffer (if there exists some bytes from the previous not reported transfer we write to ''pBdle->cbUnderFifoW'' offset)
1699 */
1700 if (!cb2Copy)
1701 {
1702 *fStop = true;
1703 goto done;
1704 }
1705
1706 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1707 /*
1708 * Write to audio backend. we should be sure whether we have enought bytes to copy to Audio backend.
1709 */
1710 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, pStreamDesc))
1711 {
1712 /*
1713 * We feed backend with new portion of fetched samples including not reported.
1714 */
1715 cbBackendCopy = AUD_write (pState->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1716 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1717 }
1718 else
1719 {
1720 /* Not enough bytes to be processed and reported, check luck on next enterence */
1721 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cb2Copy, NULL);
1722 *fStop = true;
1723 }
1724
1725 done:
1726 Assert((cbTransfered <= (SDFIFOS(pState, 4) + 1)));
1727 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransfered:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1728 return cbTransfered;
1729}
1730
1731DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1732{
1733 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1734 return VINF_SUCCESS;
1735}
1736
1737static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc)
1738{
1739 Assert(( pState
1740 && pBdle
1741 && pStreamDesc
1742 && u8Strm <= 7));
1743 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1744 pStreamDesc->u8Strm = u8Strm;
1745 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pState, CTL, u8Strm);
1746 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pState, BDPL, u8Strm),
1747 HDA_STREAM_REG2(pState, BDPU, u8Strm));
1748 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pState, LPIB, u8Strm);
1749 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pState, STS, u8Strm);
1750 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pState, CBL, u8Strm);
1751 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pState, FIFOS, u8Strm);
1752
1753 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pState, LVI, u8Strm);
1754#ifdef LOG_ENABLED
1755 if ( pBdle
1756 && pBdle->u32BdleMaxCvi)
1757 {
1758 Log(("Initialization of transfer descriptor:\n"));
1759 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1760 }
1761#endif
1762}
1763
1764DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1765{
1766 bool fStop = false;
1767 uint8_t u8Strm = 0;
1768 PHDABDLEDESC pBdle = NULL;
1769 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1770 HDASTREAMTRANSFERDESC stStreamDesc;
1771 uint32_t nBytes;
1772 switch (src)
1773 {
1774 case PO_INDEX:
1775 {
1776 u8Strm = 4;
1777 pBdle = &pState->stOutBdle;
1778 break;
1779 }
1780 case PI_INDEX:
1781 {
1782 u8Strm = 0;
1783 pBdle = &pState->stInBdle;
1784 break;
1785 }
1786 default:
1787 return;
1788 }
1789 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1790 while( avail && !fStop)
1791 {
1792 Assert ( (stStreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1793 && avail
1794 && stStreamDesc.u64BaseDMA);
1795
1796 /* Fetch the Buffer Descriptor Entry (BDE). */
1797
1798 if (hdaIsTransferCountersOverlapped(pState, pBdle, &stStreamDesc))
1799 hdaFetchBdle(pState, pBdle, &stStreamDesc);
1800 *stStreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1801 Assert((avail >= 0 && (stStreamDesc.u32Cbl >= (*stStreamDesc.pu32Lpib)))); /* sanity */
1802 uint32_t u32CblLimit = stStreamDesc.u32Cbl - (*stStreamDesc.pu32Lpib);
1803 Assert((u32CblLimit > hdaFifoWToSz(pState, &stStreamDesc)));
1804 Log(("hda: CBL=%d, LPIB=%d\n", stStreamDesc.u32Cbl, *stStreamDesc.pu32Lpib));
1805 switch (src)
1806 {
1807 case PO_INDEX:
1808 nBytes = hdaWriteAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1809 break;
1810 case PI_INDEX:
1811 nBytes = hdaReadAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1812 break;
1813 default:
1814 nBytes = 0;
1815 fStop = true;
1816 AssertMsgFailed(("Unsupported"));
1817 }
1818 Assert(nBytes <= (stStreamDesc.u32Fifos + 1));
1819 *stStreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1820
1821 /* Process end of buffer condition. */
1822 hdaStreamCounterUpdate(pState, pBdle, &stStreamDesc, nBytes);
1823 fStop = !fStop ? !hdaDoNextTransferCycle(pState, pBdle, &stStreamDesc) : fStop;
1824 }
1825}
1826
1827/**
1828 * Handle register read operation.
1829 *
1830 * Looks up and calls appropriate handler.
1831 *
1832 * @note: while implementation was detected so called "forgotten" or "hole" registers
1833 * which description is missed in RPM, datasheet or spec.
1834 *
1835 * @returns VBox status code.
1836 *
1837 * @param pState The device state structure.
1838 * @param uOffset Register offset in memory-mapped frame.
1839 * @param pv Where to fetch the value.
1840 * @param cb Number of bytes to write.
1841 * @thread EMT
1842 */
1843PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1844{
1845 int rc = VINF_SUCCESS;
1846 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1847 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1848 int index = hdaLookup(&pThis->hda, u32Offset);
1849 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1850 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1851
1852 if ( index == -1
1853 || cb > 4)
1854 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", u32Offset, cb));
1855
1856 if (index != -1)
1857 {
1858 uint32_t mask = 0;
1859 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1860 uint32_t v = 0;
1861 switch(cb)
1862 {
1863 case 1: mask = 0x000000ff; break;
1864 case 2: mask = 0x0000ffff; break;
1865 case 3: mask = 0x00ffffff; break;
1866 case 4: mask = 0xffffffff; break;
1867 }
1868 mask <<= shift;
1869 rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1870 *(uint32_t *)pv = (v & mask) >> shift;
1871 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
1872 return rc;
1873 }
1874 *(uint32_t *)pv = 0xFF;
1875 Log(("hda: hole at %X is accessed for read\n", u32Offset));
1876 return rc;
1877}
1878
1879/**
1880 * Handle register write operation.
1881 *
1882 * Looks up and calls appropriate handler.
1883 *
1884 * @returns VBox status code.
1885 *
1886 * @param pState The device state structure.
1887 * @param uOffset Register offset in memory-mapped frame.
1888 * @param pv Where to fetch the value.
1889 * @param cb Number of bytes to write.
1890 * @thread EMT
1891 */
1892PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1893{
1894 int rc = VINF_SUCCESS;
1895 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1896 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1897 int index = hdaLookup(&pThis->hda, u32Offset);
1898
1899 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1900 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1901
1902 if ( index == -1
1903 || cb > 4)
1904 LogRel(("hda: Invalid write access @0x%x(of bytes:%d)\n", u32Offset, cb));
1905
1906 if (index != -1)
1907 {
1908 uint32_t v = pThis->hda.au32Regs[index];
1909 uint32_t mask = 0;
1910 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1911 switch(cb)
1912 {
1913 case 1: mask = 0xffffff00; break;
1914 case 2: mask = 0xffff0000; break;
1915 case 3: mask = 0xff000000; break;
1916 case 4: mask = 0x00000000; break;
1917 }
1918 mask <<= shift;
1919 *(uint32_t *)pv = ((v & mask) | (*(uint32_t *)pv & ~mask)) >> shift;
1920 rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
1921 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
1922 return rc;
1923 }
1924 Log(("hda: hole at %X is accessed for write\n", u32Offset));
1925 return rc;
1926}
1927
1928/**
1929 * Callback function for mapping a PCI I/O region.
1930 *
1931 * @return VBox status code.
1932 * @param pPciDev Pointer to PCI device.
1933 * Use pPciDev->pDevIns to get the device instance.
1934 * @param iRegion The region number.
1935 * @param GCPhysAddress Physical address of the region.
1936 * If iType is PCI_ADDRESS_SPACE_IO, this is an
1937 * I/O port, else it's a physical address.
1938 * This address is *NOT* relative
1939 * to pci_mem_base like earlier!
1940 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
1941 */
1942static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
1943 RTGCPHYS GCPhysAddress, uint32_t cb,
1944 PCIADDRESSSPACE enmType)
1945{
1946 int rc;
1947 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1948 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1949 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1950
1951 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1952 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
1953 hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
1954
1955 if (RT_FAILURE(rc))
1956 return rc;
1957
1958 pThis->hda.addrMMReg = GCPhysAddress;
1959 return VINF_SUCCESS;
1960}
1961
1962/**
1963 * Saves a state of the HDA device.
1964 *
1965 * @returns VBox status code.
1966 * @param pDevIns The device instance.
1967 * @param pSSMHandle The handle to save the state to.
1968 */
1969static DECLCALLBACK(int) hdaSaveExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1970{
1971 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1972 /* Save Codec nodes states */
1973 codecSaveState(&pThis->hda.Codec, pSSMHandle);
1974 /* Save MMIO registers */
1975 SSMR3PutMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1976 /* Save HDA dma counters */
1977 SSMR3PutMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
1978 SSMR3PutMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
1979 SSMR3PutMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
1980 return VINF_SUCCESS;
1981}
1982
1983/**
1984 * Loads a saved HDA device state.
1985 *
1986 * @returns VBox status code.
1987 * @param pDevIns The device instance.
1988 * @param pSSMHandle The handle to the saved state.
1989 * @param uVersion The data unit version number.
1990 * @param uPass The data pass.
1991 */
1992static DECLCALLBACK(int) hdaLoadExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1993 uint32_t uVersion, uint32_t uPass)
1994{
1995 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1996 /* Load Codec nodes states */
1997 if (uVersion > HDA_SSM_VERSION)
1998 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1999 Assert (uPass == SSM_PASS_FINAL); NOREF(uPass);
2000
2001 codecLoadState(&pThis->hda.Codec, pSSMHandle, uVersion);
2002 /* Load MMIO registers */
2003 SSMR3GetMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
2004 /* Load HDA dma counters */
2005 SSMR3GetMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
2006 SSMR3GetMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
2007 SSMR3GetMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
2008
2009 AUD_set_active_in(pThis->hda.Codec.SwVoiceIn, SDCTL(&pThis->hda, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2010 AUD_set_active_out(pThis->hda.Codec.SwVoiceOut, SDCTL(&pThis->hda, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2011
2012 pThis->hda.u64CORBBase = CORBLBASE(&pThis->hda);
2013 pThis->hda.u64CORBBase |= ((uint64_t)CORBUBASE(&pThis->hda)) << 32;
2014 pThis->hda.u64RIRBBase = RIRLBASE(&pThis->hda);
2015 pThis->hda.u64RIRBBase |= ((uint64_t)RIRUBASE(&pThis->hda)) << 32;
2016 pThis->hda.u64DPBase = DPLBASE(&pThis->hda);
2017 pThis->hda.u64DPBase |= ((uint64_t)DPUBASE(&pThis->hda)) << 32;
2018 return VINF_SUCCESS;
2019}
2020
2021/**
2022 * Reset notification.
2023 *
2024 * @returns VBox status.
2025 * @param pDevIns The device instance data.
2026 *
2027 * @remark The original sources didn't install a reset handler, but it seems to
2028 * make sense to me so we'll do it.
2029 */
2030static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
2031{
2032 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2033 GCAP(&pThis->hda) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
2034 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
2035 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2036 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2037 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
2038 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
2039 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
2040 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
2041 CORBRP(&pThis->hda) = 0x0;
2042 RIRBWP(&pThis->hda) = 0x0;
2043
2044 Log(("hda: inter HDA reset.\n"));
2045 pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
2046
2047 if (pThis->hda.pu32CorbBuf)
2048 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
2049 else
2050 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
2051
2052 pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
2053 if (pThis->hda.pu64RirbBuf)
2054 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
2055 else
2056 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
2057
2058 pThis->hda.u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2059
2060 HDABDLEDESC stEmptyBdle;
2061 for(uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2062 {
2063 HDASTREAMTRANSFERDESC stStreamDesc;
2064 PHDABDLEDESC pBdle = NULL;
2065 if (u8Strm == 0)
2066 pBdle = &pThis->hda.stInBdle;
2067 else if(u8Strm == 4)
2068 pBdle = &pThis->hda.stOutBdle;
2069 else
2070 {
2071 memset(&stEmptyBdle, 0, sizeof(HDABDLEDESC));
2072 pBdle = &stEmptyBdle;
2073 }
2074 hdaInitTransferDescriptor(&pThis->hda, pBdle, u8Strm, &stStreamDesc);
2075 /* hdaStreamReset prevents changing SRST bit, so we zerro it here forcely. */
2076 HDA_STREAM_REG2(&pThis->hda, CTL, u8Strm) = 0;
2077 hdaStreamReset(&pThis->hda, pBdle, &stStreamDesc, u8Strm);
2078 }
2079
2080 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
2081 STATESTS(&pThis->hda) = 0x1;
2082
2083 Log(("hda: reset finished\n"));
2084}
2085
2086/**
2087 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2088 */
2089static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
2090 const char *pszIID)
2091{
2092 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
2093 Assert(&pThis->hda.IBase == pInterface);
2094
2095 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
2096 return NULL;
2097}
2098
2099static inline int hdaLookUpRegisterByName(INTELHDLinkState *pState, const char *pszArgs)
2100{
2101 int iReg = 0;
2102 for (; iReg < HDA_NREGS; ++iReg)
2103 if (!RTStrICmp(s_ichIntelHDRegMap[iReg].abbrev, pszArgs))
2104 return iReg;
2105 return -1;
2106}
2107static inline void hdaDbgPrintRegister(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaIndex)
2108{
2109 Assert( pState
2110 && iHdaIndex >= 0
2111 && iHdaIndex < HDA_NREGS);
2112 pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", s_ichIntelHDRegMap[iHdaIndex].abbrev, pState->au32Regs[iHdaIndex]);
2113}
2114static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2115{
2116 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2117 INTELHDLinkState *hda = &pThis->hda;
2118 int iHdaRegisterIndex = hdaLookUpRegisterByName(hda, pszArgs);
2119 if (iHdaRegisterIndex != -1)
2120 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2121 else
2122 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
2123 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2124}
2125
2126static inline void hdaDbgPrintStream(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
2127{
2128 Assert( pState
2129 && iHdaStrmIndex >= 0
2130 && iHdaStrmIndex < 7);
2131 pHlp->pfnPrintf(pHlp, "Dump of %d Hda Stream:\n", iHdaStrmIndex);
2132 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, CTL, iHdaStrmIndex));
2133 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, STS, iHdaStrmIndex));
2134 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOS, iHdaStrmIndex));
2135 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOW, iHdaStrmIndex));
2136}
2137
2138static inline int hdaLookUpStreamIndex(INTELHDLinkState *pState, const char *pszArgs)
2139{
2140 /* todo: add args parsing */
2141 return -1;
2142}
2143static DECLCALLBACK(void) hdaDbgStreamInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2144{
2145 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2146 INTELHDLinkState *hda = &pThis->hda;
2147 int iHdaStrmIndex = hdaLookUpStreamIndex(hda, pszArgs);
2148 if (iHdaStrmIndex != -1)
2149 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2150 else
2151 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
2152 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2153}
2154
2155/* Codec debugger interface */
2156static DECLCALLBACK(void) hdaCodecDbgNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2157{
2158 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2159 INTELHDLinkState *hda = &pThis->hda;
2160 if (hda->Codec.pfnCodecDbgListNodes)
2161 hda->Codec.pfnCodecDbgListNodes(&hda->Codec, pHlp, pszArgs);
2162 else
2163 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2164}
2165
2166static DECLCALLBACK(void) hdaCodecDbgSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2167{
2168 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2169 INTELHDLinkState *hda = &pThis->hda;
2170 if (hda->Codec.pfnCodecDbgSelector)
2171 hda->Codec.pfnCodecDbgSelector(&hda->Codec, pHlp, pszArgs);
2172 else
2173 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2174}
2175
2176//#define HDA_AS_PCI_EXPRESS
2177/* Misc routines */
2178static inline bool printHdaIsValid(const char *pszType, const char *pszExpectedFlag)
2179{
2180 return (RTStrCmp(pszType, pszExpectedFlag) == 0);
2181}
2182static const char *printHdaYesNo(bool fFlag)
2183{
2184 return fFlag ? "yes" : "no";
2185}
2186static DECLCALLBACK(size_t)
2187printHdaStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2188 const char *pszType, void const *pvValue,
2189 int cchWidth, int cchPrecision, unsigned fFlags,
2190 void *pvUser)
2191{
2192 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
2193 size_t cb = 0;
2194 if (!printHdaIsValid(pszType, "sdctl"))
2195 return cb;
2196 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2197 "SDCTL(raw: %#0x, strm:0x%x, dir:%s, tp:%s strip:%x, deie:%s, ioce:%s, run:%s, srst:%s)",
2198 sdCtl,
2199 ((sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> ICH6_HDA_SDCTL_NUM_SHIFT),
2200 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR))),
2201 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP))),
2202 ((sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> ICH6_HDA_SDCTL_STRIPE_SHIFT),
2203 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE))),
2204 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))),
2205 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))),
2206 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST))));
2207 return cb;
2208}
2209
2210static DECLCALLBACK(size_t)
2211printHdaStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2212 const char *pszType, void const *pvValue,
2213 int cchWidth, int cchPrecision, unsigned fFlags,
2214 void *pvUser)
2215{
2216 uint32_t sdFifos = (uint32_t)(uintptr_t)pvValue;
2217 uint32_t u32Bytes = 0;
2218 size_t cb = 0;
2219 if (!printHdaIsValid(pszType, "sdfifos"))
2220 return cb;
2221 switch(sdFifos)
2222 {
2223 case HDA_SDONFIFO_16B: u32Bytes = 16; break;
2224 case HDA_SDONFIFO_32B: u32Bytes = 32; break;
2225 case HDA_SDONFIFO_64B: u32Bytes = 64; break;
2226 case HDA_SDONFIFO_128B: u32Bytes = 128; break;
2227 case HDA_SDONFIFO_192B: u32Bytes = 192; break;
2228 case HDA_SDONFIFO_256B: u32Bytes = 256; break;
2229 case HDA_SDINFIFO_120B: u32Bytes = 120; break;
2230 case HDA_SDINFIFO_160B: u32Bytes = 160; break;
2231 default:;
2232 }
2233 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2234 "SDFIFOS(raw: %#0x, sdfifos:%d B)",
2235 sdFifos,
2236 u32Bytes);
2237 return cb;
2238}
2239
2240static DECLCALLBACK(size_t)
2241printHdaStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2242 const char *pszType, void const *pvValue,
2243 int cchWidth, int cchPrecision, unsigned fFlags,
2244 void *pvUser)
2245{
2246 uint32_t sdFifow = (uint32_t)(uintptr_t)pvValue;
2247 uint32_t u32Bytes = 0;
2248 size_t cb = 0;
2249 if (!printHdaIsValid(pszType, "sdfifow"))
2250 return cb;
2251 switch(sdFifow)
2252 {
2253 case HDA_SDFIFOW_8B: u32Bytes = 8; break;
2254 case HDA_SDFIFOW_16B: u32Bytes = 16; break;
2255 case HDA_SDFIFOW_32B: u32Bytes = 32; break;
2256 }
2257 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2258 "SDFIFOW(raw: %#0x, sdfifow:%d B)",
2259 sdFifow,
2260 u32Bytes);
2261 return cb;
2262}
2263
2264static DECLCALLBACK(size_t)
2265printHdaStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2266 const char *pszType, void const *pvValue,
2267 int cchWidth, int cchPrecision, unsigned fFlags,
2268 void *pvUser)
2269{
2270 uint32_t sdSts = (uint32_t)(uintptr_t)pvValue;
2271 size_t cb = 0;
2272 if (!printHdaIsValid(pszType, "sdsts"))
2273 return cb;
2274 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2275 "SDSTS(raw: %#0x, fifordy:%s, dese:%s, fifoe:%s, bcis:%s)",
2276 sdSts,
2277 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY))),
2278 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE))),
2279 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE))),
2280 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))));
2281 return cb;
2282}
2283/**
2284 * This routine registers debugger info extensions and custom printf formatters
2285 */
2286static inline int hdaInitMisc(PPDMDEVINS pDevIns)
2287{
2288 int rc;
2289 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
2290 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgStreamInfo);
2291 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaCodecDbgNodes);
2292 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaCodecDbgSelector);
2293 rc = RTStrFormatTypeRegister("sdctl", printHdaStrmCtl, NULL);
2294 AssertRC(rc);
2295 rc = RTStrFormatTypeRegister("sdsts", printHdaStrmSts, NULL);
2296 AssertRC(rc);
2297 rc = RTStrFormatTypeRegister("sdfifos", printHdaStrmFifos, NULL);
2298 AssertRC(rc);
2299 rc = RTStrFormatTypeRegister("sdfifow", printHdaStrmFifow, NULL);
2300 AssertRC(rc);
2301#if 0
2302 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
2303 AssertRC(rc);
2304#endif
2305 return rc;
2306}
2307
2308/**
2309 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2310 */
2311static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
2312 PCFGMNODE pCfgHandle)
2313{
2314 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2315 INTELHDLinkState *s = &pThis->hda;
2316 int rc;
2317
2318 Assert(iInstance == 0);
2319 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2320
2321 /*
2322 * Validations.
2323 */
2324 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
2325 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2326 N_ ("Invalid configuration for the INTELHD device"));
2327
2328 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
2329 // poll some register(s).
2330
2331 /*
2332 * Initialize data (most of it anyway).
2333 */
2334 s->pDevIns = pDevIns;
2335 /* IBase */
2336 s->IBase.pfnQueryInterface = hdaQueryInterface;
2337
2338 /* PCI Device (the assertions will be removed later) */
2339 PCIDevSetVendorId (&pThis->dev, HDA_PCI_VENDOR_ID); /* nVidia */
2340 PCIDevSetDeviceId (&pThis->dev, HDA_PCI_DEICE_ID); /* HDA */
2341
2342 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
2343 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2344 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
2345 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
2346 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
2347 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2348 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
2349 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
2350 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2351 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
2352 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */
2353
2354#if defined(HDA_AS_PCI_EXPRESS)
2355 PCIDevSetCapabilityList (&pThis->dev, 0x80);
2356#elif defined(VBOX_WITH_MSI_DEVICES)
2357 PCIDevSetCapabilityList (&pThis->dev, 0x60);
2358#else
2359 PCIDevSetCapabilityList (&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
2360#endif
2361
2362 //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2363 // of these values needs to be properly documented!
2364 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2365 PCIDevSetByte(&pThis->dev, 0x40, 0x01);
2366
2367 /* Power Management */
2368 PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2369 PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
2370 PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2371
2372#ifdef HDA_AS_PCI_EXPRESS
2373 /* PCI Express */
2374 PCIDevSetByte (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2375 PCIDevSetByte (&pThis->dev, 0x80 + 1, 0x60); /* next */
2376 /* Device flags */
2377 PCIDevSetWord (&pThis->dev, 0x80 + 2,
2378 /* version */ 0x1 |
2379 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2380 /* MSI */ (100) << 9
2381 );
2382 /* Device capabilities */
2383 PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2384 /* Device control */
2385 PCIDevSetWord (&pThis->dev, 0x80 + 8, 0);
2386 /* Device status */
2387 PCIDevSetWord (&pThis->dev, 0x80 + 10, 0);
2388 /* Link caps */
2389 PCIDevSetDWord (&pThis->dev, 0x80 + 12, 0);
2390 /* Link control */
2391 PCIDevSetWord (&pThis->dev, 0x80 + 16, 0);
2392 /* Link status */
2393 PCIDevSetWord (&pThis->dev, 0x80 + 18, 0);
2394 /* Slot capabilities */
2395 PCIDevSetDWord (&pThis->dev, 0x80 + 20, 0);
2396 /* Slot control */
2397 PCIDevSetWord (&pThis->dev, 0x80 + 24, 0);
2398 /* Slot status */
2399 PCIDevSetWord (&pThis->dev, 0x80 + 26, 0);
2400 /* Root control */
2401 PCIDevSetWord (&pThis->dev, 0x80 + 28, 0);
2402 /* Root capabilities */
2403 PCIDevSetWord (&pThis->dev, 0x80 + 30, 0);
2404 /* Root status */
2405 PCIDevSetDWord (&pThis->dev, 0x80 + 32, 0);
2406 /* Device capabilities 2 */
2407 PCIDevSetDWord (&pThis->dev, 0x80 + 36, 0);
2408 /* Device control 2 */
2409 PCIDevSetQWord (&pThis->dev, 0x80 + 40, 0);
2410 /* Link control 2 */
2411 PCIDevSetQWord (&pThis->dev, 0x80 + 48, 0);
2412 /* Slot control 2 */
2413 PCIDevSetWord (&pThis->dev, 0x80 + 56, 0);
2414#endif
2415
2416 /*
2417 * Register the PCI device.
2418 */
2419 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
2420 if (RT_FAILURE (rc))
2421 return rc;
2422
2423 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
2424 hdaMap);
2425 if (RT_FAILURE (rc))
2426 return rc;
2427
2428#ifdef VBOX_WITH_MSI_DEVICES
2429 PDMMSIREG aMsiReg;
2430
2431 RT_ZERO(aMsiReg);
2432 aMsiReg.cMsiVectors = 1;
2433 aMsiReg.iMsiCapOffset = 0x60;
2434 aMsiReg.iMsiNextOffset = 0x50;
2435 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
2436 if (RT_FAILURE (rc))
2437 {
2438 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2439 PCIDevSetCapabilityList (&pThis->dev, 0x50);
2440 }
2441#endif
2442
2443 rc = PDMDevHlpSSMRegister (pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2444 if (RT_FAILURE (rc))
2445 return rc;
2446
2447 /*
2448 * Attach driver.
2449 */
2450 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
2451 &s->pDrvBase, "Audio Driver Port");
2452 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2453 Log (("hda: No attached driver!\n"));
2454 else if (RT_FAILURE (rc))
2455 {
2456 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
2457 return rc;
2458 }
2459
2460
2461
2462 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
2463 rc = codecConstruct(pDevIns, &pThis->hda.Codec, pCfgHandle);
2464 if (RT_FAILURE(rc))
2465 AssertRCReturn(rc, rc);
2466
2467 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2468 verb F20 should provide device/codec recognition. */
2469 Assert(pThis->hda.Codec.u16VendorId);
2470 Assert(pThis->hda.Codec.u16DeviceId);
2471 PCIDevSetSubSystemVendorId (&pThis->dev, pThis->hda.Codec.u16VendorId); /* 2c ro - intel.) */
2472 PCIDevSetSubSystemId (&pThis->dev, pThis->hda.Codec.u16DeviceId); /* 2e ro. */
2473
2474 hdaReset (pDevIns);
2475 pThis->hda.Codec.id = 0;
2476 pThis->hda.Codec.pfnTransfer = hdaTransfer;
2477 pThis->hda.Codec.pfnReset = hdaCodecReset;
2478 /*
2479 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2480 * hdaReset shouldn't affects these registers.
2481 */
2482 WAKEEN(&pThis->hda) = 0x0;
2483 STATESTS(&pThis->hda) = 0x0;
2484 hdaInitMisc(pDevIns);
2485
2486 return VINF_SUCCESS;
2487}
2488
2489/**
2490 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2491 */
2492static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
2493{
2494 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2495
2496 int rc = codecDestruct(&pThis->hda.Codec);
2497 AssertRC(rc);
2498 if (pThis->hda.pu32CorbBuf)
2499 RTMemFree(pThis->hda.pu32CorbBuf);
2500 if (pThis->hda.pu64RirbBuf)
2501 RTMemFree(pThis->hda.pu64RirbBuf);
2502 return VINF_SUCCESS;
2503}
2504
2505/**
2506 * The device registration structure.
2507 */
2508const PDMDEVREG g_DeviceICH6_HDA =
2509{
2510 /* u32Version */
2511 PDM_DEVREG_VERSION,
2512 /* szName */
2513 "hda",
2514 /* szRCMod */
2515 "",
2516 /* szR0Mod */
2517 "",
2518 /* pszDescription */
2519 "ICH IntelHD Audio Controller",
2520 /* fFlags */
2521 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2522 /* fClass */
2523 PDM_DEVREG_CLASS_AUDIO,
2524 /* cMaxInstances */
2525 1,
2526 /* cbInstance */
2527 sizeof(PCIINTELHDLinkState),
2528 /* pfnConstruct */
2529 hdaConstruct,
2530 /* pfnDestruct */
2531 hdaDestruct,
2532 /* pfnRelocate */
2533 NULL,
2534 /* pfnIOCtl */
2535 NULL,
2536 /* pfnPowerOn */
2537 NULL,
2538 /* pfnReset */
2539 hdaReset,
2540 /* pfnSuspend */
2541 NULL,
2542 /* pfnResume */
2543 NULL,
2544 /* pfnAttach */
2545 NULL,
2546 /* pfnDetach */
2547 NULL,
2548 /* pfnQueryInterface. */
2549 NULL,
2550 /* pfnInitComplete */
2551 NULL,
2552 /* pfnPowerOff */
2553 NULL,
2554 /* pfnSoftReset */
2555 NULL,
2556 /* u32VersionEnd */
2557 PDM_DEVREG_VERSION
2558};
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