VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 37642

Last change on this file since 37642 was 37642, checked in by vboxsync, 14 years ago

Audio/HDA: some todo (binary search).
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1/* $Id: DevIchIntelHDA.cpp 37642 2011-06-27 04:51:13Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/vmm/pdmdev.h>
23#include <iprt/assert.h>
24#include <iprt/uuid.h>
25#include <iprt/string.h>
26#include <iprt/mem.h>
27#include <iprt/asm.h>
28#include <iprt/asm-math.h>
29
30#include "VBoxDD.h"
31
32extern "C" {
33#include "audio.h"
34}
35#include "DevCodec.h"
36
37#define VBOX_WITH_INTEL_HDA
38
39#if defined(VBOX_WITH_HP_HDA)
40/* HP Pavilion dv4t-1300 */
41# define HDA_PCI_VENDOR_ID 0x103c
42# define HDA_PCI_DEICE_ID 0x30f7
43#elif defined(VBOX_WITH_INTEL_HDA)
44/* Intel HDA controller */
45# define HDA_PCI_VENDOR_ID 0x8086
46# define HDA_PCI_DEICE_ID 0x2668
47#elif defined(VBOX_WITH_NVIDIA_HDA)
48/* nVidia HDA controller */
49# define HDA_PCI_VENDOR_ID 0x10de
50# define HDA_PCI_DEICE_ID 0x0ac0
51#else
52# error "Please specify your HDA device vendor/device IDs"
53#endif
54
55PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
56PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
57static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
58
59#define HDA_NREGS 112
60/* Registers */
61#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
62#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
63#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
64#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
65#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
66#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
67#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
68#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
69#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
70#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
71
72#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
73#define GCAP(pState) (HDA_REG((pState), GCAP))
74/* GCAP HDASpec 3.3.2 This macro compact following information about HDA
75 * oss (15:12) - number of output streams supported
76 * iss (11:8) - number of input streams supported
77 * bss (7:3) - number of bidirection streams suppoted
78 * bds (2:1) - number of serial data out signals supported
79 * b64sup (0) - 64 bit addressing supported.
80 */
81#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
82 ( (((oss) & 0xF) << 12) \
83 | (((iss) & 0xF) << 8) \
84 | (((bss) & 0x1F) << 3) \
85 | (((bds) & 0x3) << 2) \
86 | ((b64sup) & 1))
87#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
88#define VMIN(pState) (HDA_REG((pState), VMIN))
89
90#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
91#define VMAJ(pState) (HDA_REG((pState), VMAJ))
92
93#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
94#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
95
96#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
97#define INPAY(pState) (HDA_REG((pState), INPAY))
98
99#define ICH6_HDA_REG_GCTL (5)
100#define ICH6_HDA_GCTL_RST_SHIFT (0)
101#define ICH6_HDA_GCTL_FSH_SHIFT (1)
102#define ICH6_HDA_GCTL_UR_SHIFT (8)
103#define GCTL(pState) (HDA_REG((pState), GCTL))
104
105#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
106#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
107
108#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
109#define STATESTS(pState) (HDA_REG((pState), STATESTS))
110#define ICH6_HDA_STATES_SCSF 0x7
111
112#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
113#define ICH6_HDA_GSTS_FSH_SHIFT (1)
114#define GSTS(pState) (HDA_REG(pState, GSTS))
115
116#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
117#define ICH6_HDA_INTCTL_GIE_SHIFT 31
118#define ICH6_HDA_INTCTL_CIE_SHIFT 30
119#define ICH6_HDA_INTCTL_S0_SHIFT (0)
120#define ICH6_HDA_INTCTL_S1_SHIFT (1)
121#define ICH6_HDA_INTCTL_S2_SHIFT (2)
122#define ICH6_HDA_INTCTL_S3_SHIFT (3)
123#define ICH6_HDA_INTCTL_S4_SHIFT (4)
124#define ICH6_HDA_INTCTL_S5_SHIFT (5)
125#define ICH6_HDA_INTCTL_S6_SHIFT (6)
126#define ICH6_HDA_INTCTL_S7_SHIFT (7)
127#define INTCTL(pState) (HDA_REG((pState), INTCTL))
128#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
129#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
130#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
131#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
132
133/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
134 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
135 * the datasheet.
136 */
137#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
138#define SSYNC(pState) (HDA_REG((pState), SSYNC))
139
140#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
141#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
142#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
143#define ICH6_HDA_INTSTS_S0_SHIFT (0)
144#define ICH6_HDA_INTSTS_S1_SHIFT (1)
145#define ICH6_HDA_INTSTS_S2_SHIFT (2)
146#define ICH6_HDA_INTSTS_S3_SHIFT (3)
147#define ICH6_HDA_INTSTS_S4_SHIFT (4)
148#define ICH6_HDA_INTSTS_S5_SHIFT (5)
149#define ICH6_HDA_INTSTS_S6_SHIFT (6)
150#define ICH6_HDA_INTSTS_S7_SHIFT (7)
151#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
152#define INTSTS(pState) (HDA_REG((pState), INTSTS))
153#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
154#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
155#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
156#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
157
158#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
159#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
160#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
161#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
162#define ICH6_HDA_REG_CORBWP 15 /* 48 */
163#define ICH6_HDA_REG_CORBRP 16 /* 4A */
164#define ICH6_HDA_CORBRP_RST_SHIFT 15
165#define ICH6_HDA_CORBRP_WP_SHIFT 0
166#define ICH6_HDA_CORBRP_WP_MASK 0xFF
167
168#define CORBRP(pState) (HDA_REG(pState, CORBRP))
169#define CORBWP(pState) (HDA_REG(pState, CORBWP))
170
171#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
172#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
173#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
174
175#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
176
177
178#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
179#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
180#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
181
182#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
183#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
184#define ICH6_HDA_CORBSIZE_SZ 0x3
185#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
186#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
187/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
188
189#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
190#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
191
192#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
193#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
194
195#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
196#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
197#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
198#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
199
200#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
201#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
202#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
203
204#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
205#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
206#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
207#define ICH6_HDA_ROI_DMA_SHIFT (2)
208#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
209#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
210#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
211#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
212
213#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
214#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
215#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
216#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
217#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
218#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
219
220#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
221#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
222#define ICH6_HDA_RIRBSIZE_SZ 0x3
223
224#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
225#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
226
227
228#define ICH6_HDA_REG_IC 27 /* 0x60 */
229#define IC(pState) (HDA_REG(pState, IC))
230#define ICH6_HDA_REG_IR 28 /* 0x64 */
231#define IR(pState) (HDA_REG(pState, IR))
232#define ICH6_HDA_REG_IRS 29 /* 0x68 */
233#define ICH6_HDA_IRS_ICB_SHIFT (0)
234#define ICH6_HDA_IRS_IRV_SHIFT (1)
235#define IRS(pState) (HDA_REG(pState, IRS))
236#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
237#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
238
239#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
240#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
241#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
242#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
243#define DPBASE_ENABLED 1
244#define DPBASE_ADDR_MASK (~0x7f)
245
246#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
247#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
248/* Note: sdnum here _MUST_ be stream reg number [0,7] */
249#define HDA_STREAM_REG2(pState, name, sdnum) (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
250
251#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
252#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
253#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
254#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
255#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
256#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
257#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
258#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
259
260#define SD(func, num) SD##num##func
261#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
262#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
263#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
264#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
265#define ICH6_HDA_SDCTL_DIR_SHIFT (19)
266#define ICH6_HDA_SDCTL_TP_SHIFT (18)
267#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)
268#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)
269#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
270#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
271#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
272#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
273#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
274
275#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
276#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
277#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
278#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
279#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
280#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
281#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
282#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
283
284#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
285#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
286#define ICH6_HDA_SDSTS_DE_SHIFT (4)
287#define ICH6_HDA_SDSTS_FE_SHIFT (3)
288#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
289
290#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
291#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
292#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
293#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
294#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
295#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
296#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
297#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
298
299#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
300
301#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
302#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
303#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
304#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
305#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
306#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
307#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
308#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
309
310#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
311
312#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
313#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
314#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
315#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
316#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
317#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
318#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
319#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
320
321#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
322
323#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
324#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
325#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
326#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
327#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
328#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
329#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
330#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
331
332/*
333 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
334 */
335#define HDA_SDFIFOW_8B (0x2)
336#define HDA_SDFIFOW_16B (0x3)
337#define HDA_SDFIFOW_32B (0x4)
338#define SDFIFOW(pState, num) HDA_REG((pState), SD(FIFOW, num))
339
340#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
341#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
342#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
343#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
344#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
345#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
346#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
347#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
348
349/*
350 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
351 * formula: size - 1
352 * Other values not listed are not supported.
353 */
354#define HDA_SDONFIFO_16B (0xF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
355#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
356#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
357#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
358#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
359#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
360#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
361#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
362#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
363
364#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
365#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
366#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
367#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
368#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
369#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
370#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
371#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
372
373#define SDFMT(pState, num) (HDA_REG((pState), SD(FMT, num)))
374#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
375#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
376#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
377#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
378#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
379#define ICH6_HDA_SDFMT_BITS_SHIFT (4)
380#define ICH6_HDA_SDFMT_BITS_MASK (0x7)
381#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
382#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
383#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
384
385#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
386#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
387#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
388#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
389#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
390#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
391#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
392#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
393
394#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
395
396#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
397#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
398#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
399#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
400#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
401#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
402#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
403#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
404
405#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
406
407/* Predicates */
408
409typedef struct HDABDLEDESC
410{
411 uint64_t u64BdleCviAddr;
412 uint32_t u32BdleMaxCvi;
413 uint32_t u32BdleCvi;
414 uint32_t u32BdleCviLen;
415 uint32_t u32BdleCviPos;
416 bool fBdleCviIoc;
417 uint32_t cbUnderFifoW;
418 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
419} HDABDLEDESC, *PHDABDLEDESC;
420
421static SSMFIELD const g_aHdaBDLEDescFields[] =
422{
423 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
424 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
425 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
426 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
427 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
428 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
429 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
430 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
431 SSMFIELD_ENTRY_TERM()
432};
433
434typedef struct HDASTREAMTRANSFERDESC
435{
436 uint64_t u64BaseDMA;
437 uint32_t u32Ctl;
438 uint32_t *pu32Sts;
439 uint8_t u8Strm;
440 uint32_t *pu32Lpib;
441 uint32_t u32Cbl;
442 uint32_t u32Fifos;
443} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
444
445typedef struct INTELHDLinkState
446{
447 /** Pointer to the device instance. */
448 PPDMDEVINSR3 pDevIns;
449 /** Pointer to the connector of the attached audio driver. */
450 PPDMIAUDIOCONNECTOR pDrv;
451 /** Pointer to the attached audio driver. */
452 PPDMIBASE pDrvBase;
453 /** The base interface for LUN\#0. */
454 PDMIBASE IBase;
455 RTGCPHYS addrMMReg;
456 uint32_t au32Regs[HDA_NREGS];
457 HDABDLEDESC stInBdle;
458 HDABDLEDESC stOutBdle;
459 HDABDLEDESC stMicBdle;
460 /* Interrupt on completion */
461 bool fCviIoc;
462 uint64_t u64CORBBase;
463 uint64_t u64RIRBBase;
464 uint64_t u64DPBase;
465 /* pointer on CORB buf */
466 uint32_t *pu32CorbBuf;
467 /* size in bytes of CORB buf */
468 uint32_t cbCorbBuf;
469 /* pointer on RIRB buf */
470 uint64_t *pu64RirbBuf;
471 /* size in bytes of RIRB buf */
472 uint32_t cbRirbBuf;
473 /* indicates if HDA in reset. */
474 bool fInReset;
475 CODECState Codec;
476 uint8_t u8Counter;
477 uint64_t u64BaseTS;
478} INTELHDLinkState, *PINTELHDLinkState;
479
480#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
481#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
482
483#define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In, \
484 SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
485#define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out, \
486 SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
487
488
489
490
491typedef struct PCIINTELHDLinkState
492{
493 PCIDevice dev;
494 INTELHDLinkState hda;
495} PCIINTELHDLinkState;
496
497
498DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
499DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
500DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
501DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
502DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
503DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
504DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
505DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
506DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
507DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
508DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
509DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
510DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
511DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
512DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
513DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
514DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
515DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
516DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
517DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
518
519DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
520DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
521DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
522DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
523DECLCALLBACK(int)hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
524DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
525DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
526DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
527DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
528DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
529DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
530DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
531DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
532DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
533DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
534DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
535
536static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc);
537static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
538static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
539#ifdef LOG_ENABLED
540static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
541#endif
542
543
544/* see 302349 p 6.2*/
545const static struct stIchIntelHDRegMap
546{
547 /** Register offset in the register space. */
548 uint32_t offset;
549 /** Size in bytes. Registers of size > 4 are in fact tables. */
550 uint32_t size;
551 /** Readable bits. */
552 uint32_t readable;
553 /** Writable bits. */
554 uint32_t writable;
555 /** Read callback. */
556 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
557 /** Write callback. */
558 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
559 /** Abbreviated name. */
560 const char *abbrev;
561 /** Full name. */
562 const char *name;
563} s_ichIntelHDRegMap[HDA_NREGS] =
564{
565 /* offset size read mask write mask read callback write callback abbrev full name */
566 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
567 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
568 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
569 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
570 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
571 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
572 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
573 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
574 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
575 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
576 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
577 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
578 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
579 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
580 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
581 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
582 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
583 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
584 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
585 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
586 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
587 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
588 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
589 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
590 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
591 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
592 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
593 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
594 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
595 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
596 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
597 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
598 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
599 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
600
601 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
602 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
603 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
604 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
605 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
606 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
607 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
608 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
609 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
610 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
611
612 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
613 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
614 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
615 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
616 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
617 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
618 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
619 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
620 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
621 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
622
623 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
624 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
625 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
626 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
627 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
628 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
629 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
630 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
631 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
632 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
633
634 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
635 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
636 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
637 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
638 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
639 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
640 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
641 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
642 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
643 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
644
645 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
646 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
647 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
648 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
649 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
650 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
651 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
652 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
653 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
654 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
655
656 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
657 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
658 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
659 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
660 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
661 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
662 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
663 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
664 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
665 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
666
667 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
668 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
669 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
670 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
671 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
672 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
673 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
674 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
675 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
676 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
677
678 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
679 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
680 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
681 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
682 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
683 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
684 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
685 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
686 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
687 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
688};
689
690static void inline hdaUpdatePosBuf(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
691{
692 if (pState->u64DPBase & DPBASE_ENABLED)
693 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
694 (pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
695}
696static uint32_t inline hdaFifoWToSz(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
697{
698#if 0
699 switch(HDA_STREAM_REG2(pState, FIFOW, pStreamDesc->u8Strm))
700 {
701 case HDA_SDFIFOW_8B: return 8;
702 case HDA_SDFIFOW_16B: return 16;
703 case HDA_SDFIFOW_32B: return 32;
704 default:
705 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
706 }
707#endif
708 return 0;
709}
710
711static int hdaProcessInterrupt(INTELHDLinkState* pState)
712{
713#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
714 ( INTCTL_SX((pState), num) \
715 && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
716 bool fIrq = false;
717 if ( INTCTL_CIE(pState)
718 && ( RIRBSTS_RINTFL(pState)
719 || RIRBSTS_RIRBOIS(pState)
720 || (STATESTS(pState) & WAKEEN(pState))))
721 fIrq = true;
722
723 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
724 || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
725 fIrq = true;
726
727 if (INTCTL_GIE(pState))
728 {
729 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
730 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
731 }
732 return VINF_SUCCESS;
733}
734
735static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
736{
737 int idxMiddle;
738 int idxHigh = RT_ELEMENTS(s_ichIntelHDRegMap);
739 int idxLow = 0;
740 while (1)
741 {
742 if (idxHigh < idxLow)
743 break;
744 idxMiddle = idxLow + (idxHigh - idxLow)/2;
745 if (u32Offset < s_ichIntelHDRegMap[idxMiddle].offset)
746 {
747 idxHigh = idxMiddle - 1;
748 continue;
749 }
750 if (u32Offset >= s_ichIntelHDRegMap[idxMiddle].offset + s_ichIntelHDRegMap[idxMiddle].size)
751 {
752 idxLow = idxMiddle + 1;
753 continue;
754 }
755 if (u32Offset >= s_ichIntelHDRegMap[idxMiddle].offset
756 && u32Offset < s_ichIntelHDRegMap[idxMiddle].offset + s_ichIntelHDRegMap[idxMiddle].size)
757 return idxMiddle;
758 }
759 /* Aliases HDA spec 3.3.45 */
760 switch(u32Offset)
761 {
762 case 0x2084:
763 return HDA_REG_IND_NAME(SD0LPIB);
764 case 0x20A4:
765 return HDA_REG_IND_NAME(SD1LPIB);
766 case 0x20C4:
767 return HDA_REG_IND_NAME(SD2LPIB);
768 case 0x20E4:
769 return HDA_REG_IND_NAME(SD3LPIB);
770 case 0x2104:
771 return HDA_REG_IND_NAME(SD4LPIB);
772 case 0x2124:
773 return HDA_REG_IND_NAME(SD5LPIB);
774 case 0x2144:
775 return HDA_REG_IND_NAME(SD6LPIB);
776 case 0x2164:
777 return HDA_REG_IND_NAME(SD7LPIB);
778 }
779 return -1;
780}
781
782static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
783{
784 int rc = VINF_SUCCESS;
785 if (fLocal)
786 {
787 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
788 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
789 if (RT_FAILURE(rc))
790 AssertRCReturn(rc, rc);
791#ifdef DEBUG_CMD_BUFFER
792 uint8_t i = 0;
793 do
794 {
795 Log(("hda: corb%02x: ", i));
796 uint8_t j = 0;
797 do
798 {
799 const char *prefix;
800 if ((i + j) == CORBRP(pState))
801 prefix = "[R]";
802 else if ((i + j) == CORBWP(pState))
803 prefix = "[W]";
804 else
805 prefix = " "; /* three spaces */
806 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
807 j++;
808 } while (j < 8);
809 Log(("\n"));
810 i += 8;
811 } while(i != 0);
812#endif
813 }
814 else
815 {
816 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
817 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
818 if (RT_FAILURE(rc))
819 AssertRCReturn(rc, rc);
820#ifdef DEBUG_CMD_BUFFER
821 uint8_t i = 0;
822 do {
823 Log(("hda: rirb%02x: ", i));
824 uint8_t j = 0;
825 do {
826 const char *prefix;
827 if ((i + j) == RIRBWP(pState))
828 prefix = "[W]";
829 else
830 prefix = " ";
831 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
832 } while (++j < 8);
833 Log(("\n"));
834 i += 8;
835 } while (i != 0);
836#endif
837 }
838 return rc;
839}
840
841static int hdaCORBCmdProcess(INTELHDLinkState *pState)
842{
843 int rc;
844 uint8_t corbRp;
845 uint8_t corbWp;
846 uint8_t rirbWp;
847
848 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
849
850 rc = hdaCmdSync(pState, true);
851 if (RT_FAILURE(rc))
852 AssertRCReturn(rc, rc);
853 corbRp = CORBRP(pState);
854 corbWp = CORBWP(pState);
855 rirbWp = RIRBWP(pState);
856 Assert((corbWp != corbRp));
857 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
858 while (corbRp != corbWp)
859 {
860 uint32_t cmd;
861 uint64_t resp;
862 corbRp++;
863 cmd = pState->pu32CorbBuf[corbRp];
864 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
865 if (RT_FAILURE(rc))
866 AssertRCReturn(rc, rc);
867 Assert(pfn);
868 (rirbWp)++;
869 rc = pfn(&pState->Codec, cmd, &resp);
870 if (RT_FAILURE(rc))
871 AssertRCReturn(rc, rc);
872 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
873 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
874 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
875 {
876 Log(("hda: unexpected unsolicited response.\n"));
877 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
878 return rc;
879 }
880 pState->pu64RirbBuf[rirbWp] = resp;
881 pState->u8Counter++;
882 if (pState->u8Counter == RINTCNT_N(pState))
883 break;
884 }
885 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
886 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
887 rc = hdaCmdSync(pState, false);
888 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
889 if (RIRBCTL_RIRB_RIC(pState))
890 {
891 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
892 pState->u8Counter = 0;
893 rc = hdaProcessInterrupt(pState);
894 }
895 if (RT_FAILURE(rc))
896 AssertRCReturn(rc, rc);
897 return rc;
898}
899
900static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
901{
902 Log(("hda: reset of stream (%d) started\n", u8Strm));
903 Assert(( pState
904 && pBdle
905 && pStreamDesc
906 && u8Strm <= 7));
907 memset(pBdle, 0, sizeof(HDABDLEDESC));
908 *pStreamDesc->pu32Lpib = 0;
909 *pStreamDesc->pu32Sts = 0;
910 /* According to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
911 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
912 HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
913
914 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
915 HDA_STREAM_REG2(pState, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
916 HDA_STREAM_REG2(pState, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
917 HDA_STREAM_REG2(pState, CBL, u8Strm) = 0;
918 HDA_STREAM_REG2(pState, LVI, u8Strm) = 0;
919 HDA_STREAM_REG2(pState, FMT, u8Strm) = 0;
920 HDA_STREAM_REG2(pState, BDPU, u8Strm) = 0;
921 HDA_STREAM_REG2(pState, BDPL, u8Strm) = 0;
922 Log(("hda: reset of stream (%d) finished\n", u8Strm));
923}
924
925
926DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
927{
928 *pu32Value = 0;
929 return VINF_SUCCESS;
930}
931DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
932{
933 return VINF_SUCCESS;
934}
935/* U8 */
936DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
937{
938 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
939 return hdaRegReadU32(pState, offset, index, pu32Value);
940}
941
942DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
943{
944 Assert(((u32Value & 0xffffff00) == 0));
945 return hdaRegWriteU32(pState, offset, index, u32Value);
946}
947/* U16 */
948DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
949{
950 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
951 return hdaRegReadU32(pState, offset, index, pu32Value);
952}
953
954DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
955{
956 Assert(((u32Value & 0xffff0000) == 0));
957 return hdaRegWriteU32(pState, offset, index, u32Value);
958}
959
960/* U24 */
961DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
962{
963 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
964 return hdaRegReadU32(pState, offset, index, pu32Value);
965}
966
967DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
968{
969 Assert(((u32Value & 0xff000000) == 0));
970 return hdaRegWriteU32(pState, offset, index, u32Value);
971}
972/* U32 */
973DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
974{
975 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
976 return VINF_SUCCESS;
977}
978
979DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
980{
981 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
982 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
983 return VINF_SUCCESS;
984}
985
986DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
987{
988 return hdaRegReadU32(pState, offset, index, pu32Value);
989}
990
991DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
992{
993 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
994 {
995 /* exit reset state */
996 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
997 pState->fInReset = false;
998 }
999 else
1000 {
1001 /* enter reset state*/
1002 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
1003 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
1004 {
1005 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1006 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
1007 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
1008 }
1009 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
1010 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1011 pState->fInReset = true;
1012 }
1013 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1014 {
1015 /* Flush: GSTS:1 set, see 6.2.6*/
1016 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1017 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
1018 }
1019 return VINF_SUCCESS;
1020}
1021
1022DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1023{
1024 uint32_t v = pState->au32Regs[index];
1025 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
1026 pState->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
1027 return VINF_SUCCESS;
1028}
1029
1030DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1031{
1032 uint32_t v = 0;
1033 if ( RIRBSTS_RIRBOIS(pState)
1034 || RIRBSTS_RINTFL(pState)
1035 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
1036 || STATESTS(pState))
1037 v |= RT_BIT(30);
1038#define HDA_IS_STREAM_EVENT(pState, stream) \
1039 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1040 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1041 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1042#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
1043 MARK_STREAM(pState, 0, v);
1044 MARK_STREAM(pState, 1, v);
1045 MARK_STREAM(pState, 2, v);
1046 MARK_STREAM(pState, 3, v);
1047 MARK_STREAM(pState, 4, v);
1048 MARK_STREAM(pState, 5, v);
1049 MARK_STREAM(pState, 6, v);
1050 MARK_STREAM(pState, 7, v);
1051 v |= v ? RT_BIT(31) : 0;
1052 *pu32Value = v;
1053 return VINF_SUCCESS;
1054}
1055
1056DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1057{
1058 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1059 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pState)) - pState->u64BaseTS, 24, 1000);
1060 return VINF_SUCCESS;
1061}
1062
1063DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1064{
1065 return hdaRegReadU16(pState, offset, index, pu32Value);
1066}
1067
1068DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1069{
1070 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1071 CORBRP(pState) = 0;
1072 else
1073 return hdaRegWriteU8(pState, offset, index, u32Value);
1074 return VINF_SUCCESS;
1075}
1076
1077DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1078{
1079 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
1080 AssertRC(rc);
1081 if ( CORBWP(pState) != CORBRP(pState)
1082 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
1083 return hdaCORBCmdProcess(pState);
1084 return rc;
1085}
1086
1087DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1088{
1089 uint32_t v = CORBSTS(pState);
1090 CORBSTS(pState) &= ~(v & u32Value);
1091 return VINF_SUCCESS;
1092}
1093
1094DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1095{
1096 int rc;
1097 rc = hdaRegWriteU16(pState, offset, index, u32Value);
1098 if (RT_FAILURE(rc))
1099 AssertRCReturn(rc, rc);
1100 if (CORBWP(pState) == CORBRP(pState))
1101 return VINF_SUCCESS;
1102 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1103 return VINF_SUCCESS;
1104 rc = hdaCORBCmdProcess(pState);
1105 return rc;
1106}
1107
1108DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1109{
1110 return hdaRegReadU24(pState, offset, index, pu32Value);
1111}
1112
1113DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1114{
1115 bool fRun = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1116 bool fInRun = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1117 bool fReset = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1118 bool fInReset = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1119 int rc = VINF_SUCCESS;
1120 if (fInReset)
1121 {
1122 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1123 * from reset
1124 */
1125 Assert((!fReset));
1126 Log(("hda: guest initiate exit of stream reset.\n"));
1127 goto done;
1128 }
1129 else if (fReset)
1130 {
1131 /*
1132 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1133 */
1134 uint8_t u8Strm = 0;
1135 PHDABDLEDESC pBdle = NULL;
1136 HDASTREAMTRANSFERDESC stStreamDesc;
1137 Assert((!fInRun && !fRun));
1138 switch (index)
1139 {
1140 case ICH6_HDA_REG_SD0CTL:
1141 u8Strm = 0;
1142 pBdle = &pState->stInBdle;
1143 break;
1144 case ICH6_HDA_REG_SD4CTL:
1145 u8Strm = 4;
1146 pBdle = &pState->stOutBdle;
1147 break;
1148 default:
1149 Log(("hda: changing SRST bit on non-attached stream\n"));
1150 goto done;
1151 }
1152 Log(("hda: guest initiate enter to stream reset.\n"));
1153 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1154 hdaStreamReset(pState, pBdle, &stStreamDesc, u8Strm);
1155 goto done;
1156 }
1157
1158 /* we enter here to change DMA states only */
1159 if ( (fInRun && !fRun)
1160 || (fRun && !fInRun))
1161 {
1162 Assert((!fReset && !fInReset));
1163 switch (index)
1164 {
1165 case ICH6_HDA_REG_SD0CTL:
1166 AUD_set_active_in(pState->Codec.SwVoiceIn, fRun);
1167 break;
1168 case ICH6_HDA_REG_SD4CTL:
1169 AUD_set_active_out(pState->Codec.SwVoiceOut, fRun);
1170 break;
1171 default:
1172 Log(("hda: changing RUN bit on non-attached stream\n"));
1173 goto done;
1174 }
1175 }
1176
1177 done:
1178 rc = hdaRegWriteU24(pState, offset, index, u32Value);
1179 if (RT_FAILURE(rc))
1180 AssertRCReturn(rc, VINF_SUCCESS);
1181 return rc;
1182}
1183
1184DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1185{
1186 uint32_t v = HDA_REG_IND(pState, index);
1187 v &= ~(u32Value & v);
1188 HDA_REG_IND(pState, index) = v;
1189 hdaProcessInterrupt(pState);
1190 return VINF_SUCCESS;
1191}
1192
1193DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1194{
1195 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1196 if (RT_FAILURE(rc))
1197 AssertRCReturn(rc, VINF_SUCCESS);
1198 return rc;
1199}
1200
1201DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1202{
1203 switch (u32Value)
1204 {
1205 case HDA_SDFIFOW_8B:
1206 case HDA_SDFIFOW_16B:
1207 case HDA_SDFIFOW_32B:
1208 return hdaRegWriteU16(pState, offset, index, u32Value);
1209 default:
1210 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1211 return hdaRegWriteU16(pState, offset, index, HDA_SDFIFOW_32B);
1212 }
1213 return VINF_SUCCESS;
1214}
1215/*
1216 * Note this method could be called for changing value on Output Streams only (ICH6 datacheet 18.2.39)
1217 *
1218 */
1219DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1220{
1221 switch (index)
1222 {
1223 /* SDInFIFOS is RO, n=0-3 */
1224 case ICH6_HDA_REG_SD0FIFOS:
1225 case ICH6_HDA_REG_SD1FIFOS:
1226 case ICH6_HDA_REG_SD2FIFOS:
1227 case ICH6_HDA_REG_SD3FIFOS:
1228 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1229 return VINF_SUCCESS;
1230 case ICH6_HDA_REG_SD4FIFOS:
1231 case ICH6_HDA_REG_SD5FIFOS:
1232 case ICH6_HDA_REG_SD6FIFOS:
1233 case ICH6_HDA_REG_SD7FIFOS:
1234 switch(u32Value)
1235 {
1236 case HDA_SDONFIFO_16B:
1237 case HDA_SDONFIFO_32B:
1238 case HDA_SDONFIFO_64B:
1239 case HDA_SDONFIFO_128B:
1240 case HDA_SDONFIFO_192B:
1241 return hdaRegWriteU16(pState, offset, index, u32Value);
1242
1243 case HDA_SDONFIFO_256B:
1244 Log(("hda: 256 bit is unsupported, HDA is switched into 192B mode\n"));
1245 default:
1246 return hdaRegWriteU16(pState, offset, index, HDA_SDONFIFO_192B);
1247 }
1248 return VINF_SUCCESS;
1249 default:
1250 AssertMsgFailed(("Something wierd happens with register lookup routine"));
1251 }
1252 return VINF_SUCCESS;
1253}
1254
1255static void inline hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1256{
1257 Assert((pAudSetting));
1258#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1259 uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1260 uint32_t u32HzMult = 1;
1261 uint32_t u32HzDiv = 1;
1262 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))
1263 {
1264 case 0: u32HzMult = 1; break;
1265 case 1: u32HzMult = 2; break;
1266 case 2: u32HzMult = 3; break;
1267 case 3: u32HzMult = 4; break;
1268 default:
1269 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1270 }
1271 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))
1272 {
1273 case 0: u32HzDiv = 1; break;
1274 case 1: u32HzDiv = 2; break;
1275 case 2: u32HzDiv = 3; break;
1276 case 3: u32HzDiv = 4; break;
1277 case 4: u32HzDiv = 5; break;
1278 case 5: u32HzDiv = 6; break;
1279 case 6: u32HzDiv = 7; break;
1280 case 7: u32HzDiv = 8; break;
1281 }
1282 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1283
1284 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_BITS_MASK, ICH6_HDA_SDFMT_BITS_SHIFT))
1285 {
1286 case 0:
1287 Log(("hda: %s requested 8 bit\n", __FUNCTION__));
1288 pAudSetting->fmt = AUD_FMT_S8;
1289 break;
1290 case 1:
1291 Log(("hda: %s requested 16 bit\n", __FUNCTION__));
1292 pAudSetting->fmt = AUD_FMT_S16;
1293 break;
1294 case 2:
1295 Log(("hda: %s requested 20 bit\n", __FUNCTION__));
1296 break;
1297 case 3:
1298 Log(("hda: %s requested 24 bit\n", __FUNCTION__));
1299 break;
1300 case 4:
1301 Log(("hda: %s requested 32 bit\n", __FUNCTION__));
1302 pAudSetting->fmt = AUD_FMT_S32;
1303 break;
1304 default:
1305 AssertMsgFailed(("Unsupported"));
1306 }
1307 pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;
1308 pAudSetting->fmt = AUD_FMT_S16;
1309 pAudSetting->endianness = 0;
1310#undef EXTRACT_VALUE
1311}
1312
1313DECLCALLBACK(int)hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1314{
1315#ifdef VBOX_WITH_HDA_CODEC_EMU
1316 /* @todo here some more investigations are required. */
1317 int rc = 0;
1318 audsettings_t as;
1319 /* no reason to reopen voice with same settings */
1320 if (u32Value == HDA_REG_IND(pState, index))
1321 return VINF_SUCCESS;
1322 hdaSdFmtToAudSettings(u32Value, &as);
1323 switch (index)
1324 {
1325 case ICH6_HDA_REG_SD0FMT:
1326 rc = codecOpenVoice(&pState->Codec, PI_INDEX, &as);
1327 break;
1328 case ICH6_HDA_REG_SD4FMT:
1329 rc = codecOpenVoice(&pState->Codec, PO_INDEX, &as);
1330 break;
1331 default:
1332 Log(("HDA: attempt to change format on %d\n", index));
1333 rc = 0;
1334 }
1335 return hdaRegWriteU16(pState, offset, index, u32Value);
1336#else
1337 return hdaRegWriteU16(pState, offset, index, u32Value);
1338#endif
1339}
1340
1341DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1342{
1343 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1344 if (RT_FAILURE(rc))
1345 AssertRCReturn(rc, VINF_SUCCESS);
1346 return rc;
1347}
1348
1349DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1350{
1351 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1352 if (RT_FAILURE(rc))
1353 AssertRCReturn(rc, VINF_SUCCESS);
1354 return rc;
1355}
1356
1357DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1358{
1359 int rc = VINF_SUCCESS;
1360 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1361 if ( CORBWP(pState) != CORBRP(pState)
1362 || HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1363 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1364
1365 rc = hdaRegReadU32(pState, offset, index, pu32Value);
1366 return rc;
1367}
1368
1369DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1370{
1371 int rc = VINF_SUCCESS;
1372 uint64_t resp;
1373 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1374 /*
1375 * if guest set ICB bit of IRS register HDA should process verb in IC register and
1376 * writes response in IR register and set IRV (valid in case of success) bit of IRS register.
1377 */
1378 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1379 && !IRS_ICB(pState))
1380 {
1381 uint32_t cmd = IC(pState);
1382 if (CORBWP(pState) != CORBRP(pState))
1383 {
1384 /*
1385 * 3.4.3 defines behaviour of immediate Command status register.
1386 */
1387 LogRel(("hda: guest has tried process immediate verb (%x) with active CORB\n", cmd));
1388 return rc;
1389 }
1390 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1391 Log(("hda: IC:%x\n", cmd));
1392 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1393 if (RT_FAILURE(rc))
1394 AssertRCReturn(rc, rc);
1395 rc = pfn(&pState->Codec, cmd, &resp);
1396 if (RT_FAILURE(rc))
1397 AssertRCReturn(rc, rc);
1398 IR(pState) = (uint32_t)resp;
1399 Log(("hda: IR:%x\n", IR(pState)));
1400 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1401 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1402 return rc;
1403 }
1404 /*
1405 * when guest's read the response it should clean the IRV bit of the IRS register.
1406 */
1407 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1408 && IRS_IRV(pState))
1409 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1410 return rc;
1411}
1412
1413DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1414{
1415 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1416 {
1417 RIRBWP(pState) = 0;
1418 }
1419 /*The rest of bits are O, see 6.2.22 */
1420 return VINF_SUCCESS;
1421}
1422
1423DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1424{
1425 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1426 if (RT_FAILURE(rc))
1427 AssertRCReturn(rc, rc);
1428 switch(index)
1429 {
1430 case ICH6_HDA_REG_CORBLBASE:
1431 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1432 pState->u64CORBBase |= pState->au32Regs[index];
1433 break;
1434 case ICH6_HDA_REG_CORBUBASE:
1435 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1436 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1437 break;
1438 case ICH6_HDA_REG_RIRLBASE:
1439 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1440 pState->u64RIRBBase |= pState->au32Regs[index];
1441 break;
1442 case ICH6_HDA_REG_RIRUBASE:
1443 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1444 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1445 break;
1446 case ICH6_HDA_REG_DPLBASE:
1447 /* @todo: first bit has special meaning */
1448 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1449 pState->u64DPBase |= pState->au32Regs[index];
1450 break;
1451 case ICH6_HDA_REG_DPUBASE:
1452 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1453 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1454 break;
1455 default:
1456 AssertMsgFailed(("Invalid index"));
1457 }
1458 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1459 return rc;
1460}
1461
1462DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1463{
1464 uint8_t v = RIRBSTS(pState);
1465 RIRBSTS(pState) &= ~(v & u32Value);
1466
1467 return hdaProcessInterrupt(pState);
1468}
1469
1470#ifdef LOG_ENABLED
1471static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1472{
1473#if 0
1474 uint64_t addr;
1475 uint32_t len;
1476 uint32_t ioc;
1477 uint8_t bdle[16];
1478 uint32_t counter;
1479 uint32_t i;
1480 uint32_t sum = 0;
1481 Assert(pBdle && pBdle->u32BdleMaxCvi);
1482 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1483 {
1484 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1485 addr = *(uint64_t *)bdle;
1486 len = *(uint32_t *)&bdle[8];
1487 ioc = *(uint32_t *)&bdle[12];
1488 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1489 sum += len;
1490 }
1491 Log(("hda: sum: %d\n", sum));
1492 for (i = 0; i < 8; ++i)
1493 {
1494 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1495 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
1496 i , counter));
1497 }
1498#endif
1499}
1500#endif
1501
1502static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1503{
1504 uint8_t bdle[16];
1505 Assert(( pStreamDesc->u64BaseDMA
1506 && pBdle
1507 && pBdle->u32BdleMaxCvi));
1508 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1509 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1510 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1511 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1512#ifdef LOG_ENABLED
1513 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1514#endif
1515}
1516
1517static inline uint32_t hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1518{
1519 uint32_t cb2Copy;
1520 /*
1521 * Amounts of bytes depends on current position in buffer (u32BdleCviLen-u32BdleCviPos)
1522 */
1523 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1524 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1525 /*
1526 * we may increase the counter in range of [0, FIFOS + 1]
1527 */
1528 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1529 Assert((u32SoundBackendBufferBytesAvail > 0));
1530
1531 /* sanity check to avoid overriding sound backend buffer */
1532 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1533 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1534
1535 if (cb2Copy <= pBdle->cbUnderFifoW)
1536 return 0;
1537 cb2Copy -= pBdle->cbUnderFifoW; /* forcely reserve amount of ureported bytes to copy */
1538 return cb2Copy;
1539}
1540
1541static inline void hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1542{
1543 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1544 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1545 Assert((cbCopied));
1546 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1547 /* Assertion!!! It was copied less than cbUnderFifoW
1548 * Probably we need to move the buffer, but it rather hard to imagine situation
1549 * why it may happen.
1550 */
1551 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write whole buffer including not reported bytes */
1552 if ( pBdle->cbUnderFifoW
1553 && pBdle->cbUnderFifoW <= cbCopied)
1554 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1555
1556 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1557 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Assumption failed */
1558
1559 /* We always increment position on DMA buffer counter because we're always reading to intermediate buffer */
1560 pBdle->u32BdleCviPos += cbArranged2Copy;
1561
1562 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1563 /* We reports all bytes (including unreported previously) */
1564 *pu32DMACursor += cbCopied;
1565 /* reducing backend counter on amount of bytes we copied to backend */
1566 *pu32BackendBufferCapacity -= cbCopied;
1567 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1568 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1569}
1570
1571static inline void hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1572{
1573 Assert((cbCopied, cbArranged2Copy));
1574 *pu32BackendBufferCapacity -= cbCopied;
1575 pBdle->u32BdleCviPos += cbCopied;
1576 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1577 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1578 pBdle->cbUnderFifoW = 0;
1579 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1580 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1581}
1582
1583static inline void hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1584{
1585 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1586 pBdle->u32BdleCviPos += cbCopied;
1587 pBdle->cbUnderFifoW += cbCopied;
1588 /* In case of read transaction we're always coping from backend buffer */
1589 if (pu32BackendBufferCapacity)
1590 *pu32BackendBufferCapacity -= cbCopied;
1591 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1592 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pState, pStreamDesc)));
1593}
1594static inline bool hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1595{
1596 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1597 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1598
1599 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1600
1601 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1602 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1603 hdaUpdatePosBuf(pState, pStreamDesc);
1604
1605 /* don't touch BdleCvi counter on uninitialized descriptor */
1606 if ( pBdle->u32BdleCviPos
1607 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1608 {
1609 pBdle->u32BdleCviPos = 0;
1610 pBdle->u32BdleCvi++;
1611 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1612 pBdle->u32BdleCvi = 0;
1613 }
1614 return fOnBufferEdge;
1615}
1616
1617static inline void hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbInc)
1618{
1619 /*
1620 * if we're under FIFO Watermark it's expected that HDA doesn't fetch anything.
1621 * (ICH6 datasheet 18.2.38)
1622 */
1623 if (!pBdle->cbUnderFifoW)
1624 {
1625 *pStreamDesc->pu32Lpib += cbInc;
1626
1627 /*
1628 * Assert. Overlapping of buffer counter shouldn't happen.
1629 */
1630 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1631
1632 hdaUpdatePosBuf(pState, pStreamDesc);
1633
1634 }
1635}
1636
1637static inline bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1638{
1639 bool fDoNextTransferLoop = true;
1640 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1641 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1642 {
1643 if ( !pBdle->cbUnderFifoW
1644 && pBdle->fBdleCviIoc)
1645 {
1646 /*
1647 * @todo - more carefully investigate BCIS flag.
1648 * Speech synthesis works fine on Mac Guest if this bit isn't set
1649 * but in general sound quality becomes lesser.
1650 */
1651 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1652
1653 /*
1654 * we should generate the interrupt if ICE bit of SDCTL register is set.
1655 */
1656 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1657 hdaProcessInterrupt(pState);
1658 }
1659 fDoNextTransferLoop = false;
1660 }
1661 return fDoNextTransferLoop;
1662}
1663
1664/*
1665 * hdaReadAudio - copies samples from Qemu Sound back-end to DMA.
1666 * Note: this function writes immediately to DMA buffer, but "reports bytes" when all conditions meet (FIFOW)
1667 */
1668static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1669{
1670 PHDABDLEDESC pBdle = &pState->stInBdle;
1671 uint32_t cbTransfered = 0;
1672 uint32_t cb2Copy = 0;
1673 uint32_t cbBackendCopy = 0;
1674
1675 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1676
1677 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1678 if (!cb2Copy)
1679 {
1680 /* if we enter here we can't report "unreported bits" */
1681 *fStop = true;
1682 goto done;
1683 }
1684
1685
1686 /*
1687 * read from backend input line to last ureported position or at the begining.
1688 */
1689 cbBackendCopy = AUD_read (pState->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1690 /*
1691 * write on the HDA DMA
1692 */
1693 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1694
1695 /* Don't see reasons why cb2Copy could differ from cbBackendCopy */
1696 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1697
1698 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pState, 0))
1699 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1700 else
1701 {
1702 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1703 *fStop = true;
1704 }
1705 done:
1706 Assert((cbTransfered <= (SDFIFOS(pState, 0) + 1)));
1707 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransfered: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1708 return cbTransfered;
1709}
1710
1711static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1712{
1713 PHDABDLEDESC pBdle = &pState->stOutBdle;
1714 uint32_t cbTransfered = 0;
1715 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1716 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1717
1718 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1719
1720 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1721
1722 /*
1723 * Copy from DMA to the corresponding hdaBuffer (if there exists some bytes from the previous not reported transfer we write to ''pBdle->cbUnderFifoW'' offset)
1724 */
1725 if (!cb2Copy)
1726 {
1727 *fStop = true;
1728 goto done;
1729 }
1730
1731 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1732 /*
1733 * Write to audio backend. we should be sure whether we have enought bytes to copy to Audio backend.
1734 */
1735 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, pStreamDesc))
1736 {
1737 /*
1738 * We feed backend with new portion of fetched samples including not reported.
1739 */
1740 cbBackendCopy = AUD_write (pState->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1741 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1742 }
1743 else
1744 {
1745 /* Not enough bytes to be processed and reported, check luck on next enterence */
1746 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cb2Copy, NULL);
1747 *fStop = true;
1748 }
1749
1750 done:
1751 Assert((cbTransfered <= (SDFIFOS(pState, 4) + 1)));
1752 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransfered:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1753 return cbTransfered;
1754}
1755
1756DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1757{
1758 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1759 return VINF_SUCCESS;
1760}
1761
1762static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc)
1763{
1764 Assert(( pState
1765 && pBdle
1766 && pStreamDesc
1767 && u8Strm <= 7));
1768 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1769 pStreamDesc->u8Strm = u8Strm;
1770 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pState, CTL, u8Strm);
1771 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pState, BDPL, u8Strm),
1772 HDA_STREAM_REG2(pState, BDPU, u8Strm));
1773 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pState, LPIB, u8Strm);
1774 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pState, STS, u8Strm);
1775 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pState, CBL, u8Strm);
1776 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pState, FIFOS, u8Strm);
1777
1778 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pState, LVI, u8Strm);
1779#ifdef LOG_ENABLED
1780 if ( pBdle
1781 && pBdle->u32BdleMaxCvi)
1782 {
1783 Log(("Initialization of transfer descriptor:\n"));
1784 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1785 }
1786#endif
1787}
1788
1789DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1790{
1791 bool fStop = false;
1792 uint8_t u8Strm = 0;
1793 PHDABDLEDESC pBdle = NULL;
1794 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1795 HDASTREAMTRANSFERDESC stStreamDesc;
1796 uint32_t nBytes;
1797 switch (src)
1798 {
1799 case PO_INDEX:
1800 {
1801 u8Strm = 4;
1802 pBdle = &pState->stOutBdle;
1803 break;
1804 }
1805 case PI_INDEX:
1806 {
1807 u8Strm = 0;
1808 pBdle = &pState->stInBdle;
1809 break;
1810 }
1811 default:
1812 return;
1813 }
1814 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1815 while( avail && !fStop)
1816 {
1817 Assert ( (stStreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1818 && avail
1819 && stStreamDesc.u64BaseDMA);
1820
1821 /* Fetch the Buffer Descriptor Entry (BDE). */
1822
1823 if (hdaIsTransferCountersOverlapped(pState, pBdle, &stStreamDesc))
1824 hdaFetchBdle(pState, pBdle, &stStreamDesc);
1825 *stStreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1826 Assert((avail >= 0 && (stStreamDesc.u32Cbl >= (*stStreamDesc.pu32Lpib)))); /* sanity */
1827 uint32_t u32CblLimit = stStreamDesc.u32Cbl - (*stStreamDesc.pu32Lpib);
1828 Assert((u32CblLimit > hdaFifoWToSz(pState, &stStreamDesc)));
1829 Log(("hda: CBL=%d, LPIB=%d\n", stStreamDesc.u32Cbl, *stStreamDesc.pu32Lpib));
1830 switch (src)
1831 {
1832 case PO_INDEX:
1833 nBytes = hdaWriteAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1834 break;
1835 case PI_INDEX:
1836 nBytes = hdaReadAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1837 break;
1838 default:
1839 nBytes = 0;
1840 fStop = true;
1841 AssertMsgFailed(("Unsupported"));
1842 }
1843 Assert(nBytes <= (stStreamDesc.u32Fifos + 1));
1844 *stStreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1845
1846 /* Process end of buffer condition. */
1847 hdaStreamCounterUpdate(pState, pBdle, &stStreamDesc, nBytes);
1848 fStop = !fStop ? !hdaDoNextTransferCycle(pState, pBdle, &stStreamDesc) : fStop;
1849 }
1850}
1851
1852/**
1853 * Handle register read operation.
1854 *
1855 * Looks up and calls appropriate handler.
1856 *
1857 * @note: while implementation was detected so called "forgotten" or "hole" registers
1858 * which description is missed in RPM, datasheet or spec.
1859 *
1860 * @returns VBox status code.
1861 *
1862 * @param pState The device state structure.
1863 * @param uOffset Register offset in memory-mapped frame.
1864 * @param pv Where to fetch the value.
1865 * @param cb Number of bytes to write.
1866 * @thread EMT
1867 */
1868PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1869{
1870 int rc = VINF_SUCCESS;
1871 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1872 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1873 int index = hdaLookup(&pThis->hda, u32Offset);
1874 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1875 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1876
1877 if ( index == -1
1878 || cb > 4)
1879 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", u32Offset, cb));
1880
1881 if (index != -1)
1882 {
1883 /** @todo r=bird: Accesses crossing register boundraries aren't handled
1884 * right from what I can tell? If they are, please explain
1885 * what the rules are. */
1886 uint32_t mask = 0;
1887 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1888 uint32_t v = 0;
1889 switch(cb)
1890 {
1891 case 1: mask = 0x000000ff; break;
1892 case 2: mask = 0x0000ffff; break;
1893 case 3: mask = 0x00ffffff; break;
1894 case 4: mask = 0xffffffff; break;
1895 }
1896 mask <<= shift;
1897 rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1898 *(uint32_t *)pv = (v & mask) >> shift;
1899 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
1900 return rc;
1901 }
1902 *(uint32_t *)pv = 0xFF;
1903 Log(("hda: hole at %x is accessed for read\n", u32Offset));
1904 return rc;
1905}
1906
1907/**
1908 * Handle register write operation.
1909 *
1910 * Looks up and calls appropriate handler.
1911 *
1912 * @returns VBox status code.
1913 *
1914 * @param pState The device state structure.
1915 * @param uOffset Register offset in memory-mapped frame.
1916 * @param pv Where to fetch the value.
1917 * @param cb Number of bytes to write.
1918 * @thread EMT
1919 */
1920PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1921{
1922 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1923 uint32_t offReg = GCPhysAddr - pThis->hda.addrMMReg;
1924 int idxReg = hdaLookup(&pThis->hda, offReg);
1925 int rc = VINF_SUCCESS;
1926
1927 if (pThis->hda.fInReset && idxReg != ICH6_HDA_REG_GCTL)
1928 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1929
1930 if ( idxReg == -1
1931 || cb > 4)
1932 LogRel(("hda: Invalid write access @0x%x(of bytes:%d)\n", offReg, cb));
1933
1934 if (idxReg != -1)
1935 {
1936 /** @todo r=bird: This looks like code for handling unalinged register
1937 * accesses. If it isn't then, add a comment explaing what you're
1938 * trying to do here. OTOH, if it is then it has the following
1939 * issues:
1940 * -# You're calculating the wrong new value for the register.
1941 * -# You're not handling cross register accesses. Imagine a
1942 * 4-byte write starting at CORBCTL, or a 8-byte write.
1943 *
1944 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
1945 * nobody seems to be using it and it just add complexity when reading
1946 * the code.
1947 *
1948 * PPS. 'v' is not a very good variable name.
1949 * PPPS. We don't do 3 byte writes, only 1, 2, 4 and 8.
1950 */
1951 uint32_t u32CurValue = pThis->hda.au32Regs[idxReg];
1952 uint32_t u32NewValue;
1953 uint32_t mask;
1954 switch (cb)
1955 {
1956 case 1:
1957 u32NewValue = *(uint8_t const *)pv;
1958 mask = 0xffffff00;
1959 break;
1960 case 2:
1961 u32NewValue = *(uint16_t const *)pv;
1962 mask = 0xffff0000;
1963 break;
1964 case 4:
1965 case 8: /** @todo r=bird: Add a line about why 8-byte accesses are handled like 4-byte ones. */
1966 u32NewValue = *(uint32_t const *)pv;
1967 mask = 0;
1968 break;
1969 default:
1970 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
1971 }
1972 uint32_t shift = (offReg - s_ichIntelHDRegMap[idxReg].offset) % sizeof(uint32_t) * 8;
1973 mask <<= shift;
1974 u32NewValue = ((u32CurValue & mask) | (u32NewValue & ~mask)) >> shift;
1975
1976 rc = s_ichIntelHDRegMap[idxReg].pfnWrite(&pThis->hda, offReg, idxReg, u32NewValue);
1977 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[idxReg].abbrev, u32NewValue,
1978 u32CurValue, pThis->hda.au32Regs[idxReg]));
1979 return rc;
1980 }
1981
1982 Log(("hda: hole at %x is accessed for write\n", offReg));
1983 return rc;
1984}
1985
1986/**
1987 * Callback function for mapping a PCI I/O region.
1988 *
1989 * @return VBox status code.
1990 * @param pPciDev Pointer to PCI device.
1991 * Use pPciDev->pDevIns to get the device instance.
1992 * @param iRegion The region number.
1993 * @param GCPhysAddress Physical address of the region.
1994 * If iType is PCI_ADDRESS_SPACE_IO, this is an
1995 * I/O port, else it's a physical address.
1996 * This address is *NOT* relative
1997 * to pci_mem_base like earlier!
1998 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
1999 */
2000static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
2001 RTGCPHYS GCPhysAddress, uint32_t cb,
2002 PCIADDRESSSPACE enmType)
2003{
2004 int rc;
2005 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2006 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
2007 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
2008
2009 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2010 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
2011 hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
2012
2013 if (RT_FAILURE(rc))
2014 return rc;
2015
2016 pThis->hda.addrMMReg = GCPhysAddress;
2017 return VINF_SUCCESS;
2018}
2019
2020/**
2021 * Saves a state of the HDA device.
2022 *
2023 * @returns VBox status code.
2024 * @param pDevIns The device instance.
2025 * @param pSSMHandle The handle to save the state to.
2026 */
2027static DECLCALLBACK(int) hdaSaveExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2028{
2029 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2030 /* Save Codec nodes states */
2031 codecSaveState(&pThis->hda.Codec, pSSMHandle);
2032 /* Save MMIO registers */
2033 SSMR3PutMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
2034 /* Save HDA dma counters */
2035 SSMR3PutStruct (pSSMHandle, &pThis->hda.stOutBdle, g_aHdaBDLEDescFields);
2036 SSMR3PutStruct (pSSMHandle, &pThis->hda.stMicBdle, g_aHdaBDLEDescFields);
2037 SSMR3PutStruct (pSSMHandle, &pThis->hda.stInBdle, g_aHdaBDLEDescFields);
2038 return VINF_SUCCESS;
2039}
2040
2041/**
2042 * Loads a saved HDA device state.
2043 *
2044 * @returns VBox status code.
2045 * @param pDevIns The device instance.
2046 * @param pSSMHandle The handle to the saved state.
2047 * @param uVersion The data unit version number.
2048 * @param uPass The data pass.
2049 */
2050static DECLCALLBACK(int) hdaLoadExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
2051 uint32_t uVersion, uint32_t uPass)
2052{
2053 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2054 /* Load Codec nodes states */
2055 Assert (uPass == SSM_PASS_FINAL); NOREF(uPass);
2056
2057 codecLoadState(&pThis->hda.Codec, pSSMHandle, uVersion);
2058 /* Load MMIO registers */
2059 SSMR3GetMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
2060 /* Load HDA dma counters */
2061 if ( uVersion == HDA_SSM_VERSION_1
2062 || uVersion == HDA_SSM_VERSION_2)
2063 {
2064 SSMR3GetMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
2065 SSMR3GetMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
2066 SSMR3GetMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
2067 }
2068 else
2069 {
2070 SSMR3GetStruct (pSSMHandle, &pThis->hda.stOutBdle, g_aHdaBDLEDescFields);
2071 SSMR3GetStruct (pSSMHandle, &pThis->hda.stMicBdle, g_aHdaBDLEDescFields);
2072 SSMR3GetStruct (pSSMHandle, &pThis->hda.stInBdle, g_aHdaBDLEDescFields);
2073 }
2074
2075
2076 AUD_set_active_in(pThis->hda.Codec.SwVoiceIn, SDCTL(&pThis->hda, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2077 AUD_set_active_out(pThis->hda.Codec.SwVoiceOut, SDCTL(&pThis->hda, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2078
2079 pThis->hda.u64CORBBase = CORBLBASE(&pThis->hda);
2080 pThis->hda.u64CORBBase |= ((uint64_t)CORBUBASE(&pThis->hda)) << 32;
2081 pThis->hda.u64RIRBBase = RIRLBASE(&pThis->hda);
2082 pThis->hda.u64RIRBBase |= ((uint64_t)RIRUBASE(&pThis->hda)) << 32;
2083 pThis->hda.u64DPBase = DPLBASE(&pThis->hda);
2084 pThis->hda.u64DPBase |= ((uint64_t)DPUBASE(&pThis->hda)) << 32;
2085 return VINF_SUCCESS;
2086}
2087
2088/**
2089 * Reset notification.
2090 *
2091 * @returns VBox status.
2092 * @param pDevIns The device instance data.
2093 *
2094 * @remark The original sources didn't install a reset handler, but it seems to
2095 * make sense to me so we'll do it.
2096 */
2097static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
2098{
2099 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2100 GCAP(&pThis->hda) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
2101 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
2102 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2103 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2104 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
2105 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
2106 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
2107 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
2108 CORBRP(&pThis->hda) = 0x0;
2109 RIRBWP(&pThis->hda) = 0x0;
2110
2111 Log(("hda: inter HDA reset.\n"));
2112 pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
2113
2114 if (pThis->hda.pu32CorbBuf)
2115 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
2116 else
2117 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
2118
2119 pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
2120 if (pThis->hda.pu64RirbBuf)
2121 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
2122 else
2123 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
2124
2125 pThis->hda.u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2126
2127 HDABDLEDESC stEmptyBdle;
2128 for(uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2129 {
2130 HDASTREAMTRANSFERDESC stStreamDesc;
2131 PHDABDLEDESC pBdle = NULL;
2132 if (u8Strm == 0)
2133 pBdle = &pThis->hda.stInBdle;
2134 else if(u8Strm == 4)
2135 pBdle = &pThis->hda.stOutBdle;
2136 else
2137 {
2138 memset(&stEmptyBdle, 0, sizeof(HDABDLEDESC));
2139 pBdle = &stEmptyBdle;
2140 }
2141 hdaInitTransferDescriptor(&pThis->hda, pBdle, u8Strm, &stStreamDesc);
2142 /* hdaStreamReset prevents changing SRST bit, so we zerro it here forcely. */
2143 HDA_STREAM_REG2(&pThis->hda, CTL, u8Strm) = 0;
2144 hdaStreamReset(&pThis->hda, pBdle, &stStreamDesc, u8Strm);
2145 }
2146
2147 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
2148 STATESTS(&pThis->hda) = 0x1;
2149
2150 Log(("hda: reset finished\n"));
2151}
2152
2153/**
2154 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2155 */
2156static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
2157 const char *pszIID)
2158{
2159 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
2160 Assert(&pThis->hda.IBase == pInterface);
2161
2162 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
2163 return NULL;
2164}
2165
2166static inline int hdaLookUpRegisterByName(INTELHDLinkState *pState, const char *pszArgs)
2167{
2168 int iReg = 0;
2169 for (; iReg < HDA_NREGS; ++iReg)
2170 if (!RTStrICmp(s_ichIntelHDRegMap[iReg].abbrev, pszArgs))
2171 return iReg;
2172 return -1;
2173}
2174static inline void hdaDbgPrintRegister(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaIndex)
2175{
2176 Assert( pState
2177 && iHdaIndex >= 0
2178 && iHdaIndex < HDA_NREGS);
2179 pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", s_ichIntelHDRegMap[iHdaIndex].abbrev, pState->au32Regs[iHdaIndex]);
2180}
2181static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2182{
2183 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2184 INTELHDLinkState *hda = &pThis->hda;
2185 int iHdaRegisterIndex = hdaLookUpRegisterByName(hda, pszArgs);
2186 if (iHdaRegisterIndex != -1)
2187 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2188 else
2189 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
2190 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2191}
2192
2193static inline void hdaDbgPrintStream(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
2194{
2195 Assert( pState
2196 && iHdaStrmIndex >= 0
2197 && iHdaStrmIndex < 7);
2198 pHlp->pfnPrintf(pHlp, "Dump of %d Hda Stream:\n", iHdaStrmIndex);
2199 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, CTL, iHdaStrmIndex));
2200 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, STS, iHdaStrmIndex));
2201 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOS, iHdaStrmIndex));
2202 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOW, iHdaStrmIndex));
2203}
2204
2205static inline int hdaLookUpStreamIndex(INTELHDLinkState *pState, const char *pszArgs)
2206{
2207 /* todo: add args parsing */
2208 return -1;
2209}
2210static DECLCALLBACK(void) hdaDbgStreamInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2211{
2212 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2213 INTELHDLinkState *hda = &pThis->hda;
2214 int iHdaStrmIndex = hdaLookUpStreamIndex(hda, pszArgs);
2215 if (iHdaStrmIndex != -1)
2216 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2217 else
2218 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
2219 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2220}
2221
2222/* Codec debugger interface */
2223static DECLCALLBACK(void) hdaCodecDbgNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2224{
2225 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2226 INTELHDLinkState *hda = &pThis->hda;
2227 if (hda->Codec.pfnCodecDbgListNodes)
2228 hda->Codec.pfnCodecDbgListNodes(&hda->Codec, pHlp, pszArgs);
2229 else
2230 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2231}
2232
2233static DECLCALLBACK(void) hdaCodecDbgSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2234{
2235 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2236 INTELHDLinkState *hda = &pThis->hda;
2237 if (hda->Codec.pfnCodecDbgSelector)
2238 hda->Codec.pfnCodecDbgSelector(&hda->Codec, pHlp, pszArgs);
2239 else
2240 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2241}
2242
2243//#define HDA_AS_PCI_EXPRESS
2244/* Misc routines */
2245static inline bool printHdaIsValid(const char *pszType, const char *pszExpectedFlag)
2246{
2247 return (RTStrCmp(pszType, pszExpectedFlag) == 0);
2248}
2249static const char *printHdaYesNo(bool fFlag)
2250{
2251 return fFlag ? "yes" : "no";
2252}
2253static DECLCALLBACK(size_t)
2254printHdaStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2255 const char *pszType, void const *pvValue,
2256 int cchWidth, int cchPrecision, unsigned fFlags,
2257 void *pvUser)
2258{
2259 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
2260 size_t cb = 0;
2261 if (!printHdaIsValid(pszType, "sdctl"))
2262 return cb;
2263 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2264 "SDCTL(raw: %#0x, strm:0x%x, dir:%s, tp:%s strip:%x, deie:%s, ioce:%s, run:%s, srst:%s)",
2265 sdCtl,
2266 ((sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> ICH6_HDA_SDCTL_NUM_SHIFT),
2267 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR))),
2268 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP))),
2269 ((sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> ICH6_HDA_SDCTL_STRIPE_SHIFT),
2270 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE))),
2271 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))),
2272 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))),
2273 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST))));
2274 return cb;
2275}
2276
2277static DECLCALLBACK(size_t)
2278printHdaStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2279 const char *pszType, void const *pvValue,
2280 int cchWidth, int cchPrecision, unsigned fFlags,
2281 void *pvUser)
2282{
2283 uint32_t sdFifos = (uint32_t)(uintptr_t)pvValue;
2284 uint32_t u32Bytes = 0;
2285 size_t cb = 0;
2286 if (!printHdaIsValid(pszType, "sdfifos"))
2287 return cb;
2288 switch(sdFifos)
2289 {
2290 case HDA_SDONFIFO_16B: u32Bytes = 16; break;
2291 case HDA_SDONFIFO_32B: u32Bytes = 32; break;
2292 case HDA_SDONFIFO_64B: u32Bytes = 64; break;
2293 case HDA_SDONFIFO_128B: u32Bytes = 128; break;
2294 case HDA_SDONFIFO_192B: u32Bytes = 192; break;
2295 case HDA_SDONFIFO_256B: u32Bytes = 256; break;
2296 case HDA_SDINFIFO_120B: u32Bytes = 120; break;
2297 case HDA_SDINFIFO_160B: u32Bytes = 160; break;
2298 default:;
2299 }
2300 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2301 "SDFIFOS(raw: %#0x, sdfifos:%d B)",
2302 sdFifos,
2303 u32Bytes);
2304 return cb;
2305}
2306
2307static DECLCALLBACK(size_t)
2308printHdaStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2309 const char *pszType, void const *pvValue,
2310 int cchWidth, int cchPrecision, unsigned fFlags,
2311 void *pvUser)
2312{
2313 uint32_t sdFifow = (uint32_t)(uintptr_t)pvValue;
2314 uint32_t u32Bytes = 0;
2315 size_t cb = 0;
2316 if (!printHdaIsValid(pszType, "sdfifow"))
2317 return cb;
2318 switch(sdFifow)
2319 {
2320 case HDA_SDFIFOW_8B: u32Bytes = 8; break;
2321 case HDA_SDFIFOW_16B: u32Bytes = 16; break;
2322 case HDA_SDFIFOW_32B: u32Bytes = 32; break;
2323 }
2324 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2325 "SDFIFOW(raw: %#0x, sdfifow:%d B)",
2326 sdFifow,
2327 u32Bytes);
2328 return cb;
2329}
2330
2331static DECLCALLBACK(size_t)
2332printHdaStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2333 const char *pszType, void const *pvValue,
2334 int cchWidth, int cchPrecision, unsigned fFlags,
2335 void *pvUser)
2336{
2337 uint32_t sdSts = (uint32_t)(uintptr_t)pvValue;
2338 size_t cb = 0;
2339 if (!printHdaIsValid(pszType, "sdsts"))
2340 return cb;
2341 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2342 "SDSTS(raw: %#0x, fifordy:%s, dese:%s, fifoe:%s, bcis:%s)",
2343 sdSts,
2344 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY))),
2345 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE))),
2346 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE))),
2347 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))));
2348 return cb;
2349}
2350/**
2351 * This routine registers debugger info extensions and custom printf formatters
2352 */
2353static inline int hdaInitMisc(PPDMDEVINS pDevIns)
2354{
2355 int rc;
2356 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
2357 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgStreamInfo);
2358 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaCodecDbgNodes);
2359 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaCodecDbgSelector);
2360 rc = RTStrFormatTypeRegister("sdctl", printHdaStrmCtl, NULL);
2361 AssertRC(rc);
2362 rc = RTStrFormatTypeRegister("sdsts", printHdaStrmSts, NULL);
2363 AssertRC(rc);
2364 rc = RTStrFormatTypeRegister("sdfifos", printHdaStrmFifos, NULL);
2365 AssertRC(rc);
2366 rc = RTStrFormatTypeRegister("sdfifow", printHdaStrmFifow, NULL);
2367 AssertRC(rc);
2368#if 0
2369 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
2370 AssertRC(rc);
2371#endif
2372 return rc;
2373}
2374
2375/**
2376 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2377 */
2378static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
2379 PCFGMNODE pCfgHandle)
2380{
2381 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2382 INTELHDLinkState *s = &pThis->hda;
2383 int rc;
2384
2385 Assert(iInstance == 0);
2386 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2387
2388 /*
2389 * Validations.
2390 */
2391 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
2392 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2393 N_ ("Invalid configuration for the INTELHD device"));
2394
2395 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
2396 // poll some register(s).
2397
2398 /*
2399 * Initialize data (most of it anyway).
2400 */
2401 s->pDevIns = pDevIns;
2402 /* IBase */
2403 s->IBase.pfnQueryInterface = hdaQueryInterface;
2404
2405 /* PCI Device (the assertions will be removed later) */
2406 PCIDevSetVendorId (&pThis->dev, HDA_PCI_VENDOR_ID); /* nVidia */
2407 PCIDevSetDeviceId (&pThis->dev, HDA_PCI_DEICE_ID); /* HDA */
2408
2409 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
2410 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2411 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
2412 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
2413 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
2414 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2415 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
2416 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
2417 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2418 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
2419 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */
2420
2421#if defined(HDA_AS_PCI_EXPRESS)
2422 PCIDevSetCapabilityList (&pThis->dev, 0x80);
2423#elif defined(VBOX_WITH_MSI_DEVICES)
2424 PCIDevSetCapabilityList (&pThis->dev, 0x60);
2425#else
2426 PCIDevSetCapabilityList (&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
2427#endif
2428
2429 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2430 // of these values needs to be properly documented!
2431 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2432 PCIDevSetByte(&pThis->dev, 0x40, 0x01);
2433
2434 /* Power Management */
2435 PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2436 PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
2437 PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2438
2439#ifdef HDA_AS_PCI_EXPRESS
2440 /* PCI Express */
2441 PCIDevSetByte (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2442 PCIDevSetByte (&pThis->dev, 0x80 + 1, 0x60); /* next */
2443 /* Device flags */
2444 PCIDevSetWord (&pThis->dev, 0x80 + 2,
2445 /* version */ 0x1 |
2446 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2447 /* MSI */ (100) << 9
2448 );
2449 /* Device capabilities */
2450 PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2451 /* Device control */
2452 PCIDevSetWord (&pThis->dev, 0x80 + 8, 0);
2453 /* Device status */
2454 PCIDevSetWord (&pThis->dev, 0x80 + 10, 0);
2455 /* Link caps */
2456 PCIDevSetDWord (&pThis->dev, 0x80 + 12, 0);
2457 /* Link control */
2458 PCIDevSetWord (&pThis->dev, 0x80 + 16, 0);
2459 /* Link status */
2460 PCIDevSetWord (&pThis->dev, 0x80 + 18, 0);
2461 /* Slot capabilities */
2462 PCIDevSetDWord (&pThis->dev, 0x80 + 20, 0);
2463 /* Slot control */
2464 PCIDevSetWord (&pThis->dev, 0x80 + 24, 0);
2465 /* Slot status */
2466 PCIDevSetWord (&pThis->dev, 0x80 + 26, 0);
2467 /* Root control */
2468 PCIDevSetWord (&pThis->dev, 0x80 + 28, 0);
2469 /* Root capabilities */
2470 PCIDevSetWord (&pThis->dev, 0x80 + 30, 0);
2471 /* Root status */
2472 PCIDevSetDWord (&pThis->dev, 0x80 + 32, 0);
2473 /* Device capabilities 2 */
2474 PCIDevSetDWord (&pThis->dev, 0x80 + 36, 0);
2475 /* Device control 2 */
2476 PCIDevSetQWord (&pThis->dev, 0x80 + 40, 0);
2477 /* Link control 2 */
2478 PCIDevSetQWord (&pThis->dev, 0x80 + 48, 0);
2479 /* Slot control 2 */
2480 PCIDevSetWord (&pThis->dev, 0x80 + 56, 0);
2481#endif
2482
2483 /*
2484 * Register the PCI device.
2485 */
2486 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
2487 if (RT_FAILURE (rc))
2488 return rc;
2489
2490 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
2491 hdaMap);
2492 if (RT_FAILURE (rc))
2493 return rc;
2494
2495#ifdef VBOX_WITH_MSI_DEVICES
2496 PDMMSIREG aMsiReg;
2497
2498 RT_ZERO(aMsiReg);
2499 aMsiReg.cMsiVectors = 1;
2500 aMsiReg.iMsiCapOffset = 0x60;
2501 aMsiReg.iMsiNextOffset = 0x50;
2502 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
2503 if (RT_FAILURE (rc))
2504 {
2505 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2506 PCIDevSetCapabilityList (&pThis->dev, 0x50);
2507 }
2508#endif
2509
2510 rc = PDMDevHlpSSMRegister (pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2511 if (RT_FAILURE (rc))
2512 return rc;
2513
2514 /*
2515 * Attach driver.
2516 */
2517 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
2518 &s->pDrvBase, "Audio Driver Port");
2519 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2520 Log (("hda: No attached driver!\n"));
2521 else if (RT_FAILURE (rc))
2522 {
2523 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
2524 return rc;
2525 }
2526
2527
2528
2529 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
2530 rc = codecConstruct(pDevIns, &pThis->hda.Codec, pCfgHandle);
2531 if (RT_FAILURE(rc))
2532 AssertRCReturn(rc, rc);
2533
2534 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2535 verb F20 should provide device/codec recognition. */
2536 Assert(pThis->hda.Codec.u16VendorId);
2537 Assert(pThis->hda.Codec.u16DeviceId);
2538 PCIDevSetSubSystemVendorId (&pThis->dev, pThis->hda.Codec.u16VendorId); /* 2c ro - intel.) */
2539 PCIDevSetSubSystemId (&pThis->dev, pThis->hda.Codec.u16DeviceId); /* 2e ro. */
2540
2541 hdaReset (pDevIns);
2542 pThis->hda.Codec.id = 0;
2543 pThis->hda.Codec.pfnTransfer = hdaTransfer;
2544 pThis->hda.Codec.pfnReset = hdaCodecReset;
2545 /*
2546 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2547 * hdaReset shouldn't affects these registers.
2548 */
2549 WAKEEN(&pThis->hda) = 0x0;
2550 STATESTS(&pThis->hda) = 0x0;
2551 hdaInitMisc(pDevIns);
2552
2553 return VINF_SUCCESS;
2554}
2555
2556/**
2557 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2558 */
2559static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
2560{
2561 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2562
2563 int rc = codecDestruct(&pThis->hda.Codec);
2564 AssertRC(rc);
2565 if (pThis->hda.pu32CorbBuf)
2566 RTMemFree(pThis->hda.pu32CorbBuf);
2567 if (pThis->hda.pu64RirbBuf)
2568 RTMemFree(pThis->hda.pu64RirbBuf);
2569 return VINF_SUCCESS;
2570}
2571
2572/**
2573 * The device registration structure.
2574 */
2575const PDMDEVREG g_DeviceICH6_HDA =
2576{
2577 /* u32Version */
2578 PDM_DEVREG_VERSION,
2579 /* szName */
2580 "hda",
2581 /* szRCMod */
2582 "",
2583 /* szR0Mod */
2584 "",
2585 /* pszDescription */
2586 "ICH IntelHD Audio Controller",
2587 /* fFlags */
2588 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2589 /* fClass */
2590 PDM_DEVREG_CLASS_AUDIO,
2591 /* cMaxInstances */
2592 1,
2593 /* cbInstance */
2594 sizeof(PCIINTELHDLinkState),
2595 /* pfnConstruct */
2596 hdaConstruct,
2597 /* pfnDestruct */
2598 hdaDestruct,
2599 /* pfnRelocate */
2600 NULL,
2601 /* pfnIOCtl */
2602 NULL,
2603 /* pfnPowerOn */
2604 NULL,
2605 /* pfnReset */
2606 hdaReset,
2607 /* pfnSuspend */
2608 NULL,
2609 /* pfnResume */
2610 NULL,
2611 /* pfnAttach */
2612 NULL,
2613 /* pfnDetach */
2614 NULL,
2615 /* pfnQueryInterface. */
2616 NULL,
2617 /* pfnInitComplete */
2618 NULL,
2619 /* pfnPowerOff */
2620 NULL,
2621 /* pfnSoftReset */
2622 NULL,
2623 /* u32VersionEnd */
2624 PDM_DEVREG_VERSION
2625};
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