VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 40532

Last change on this file since 40532 was 40112, checked in by vboxsync, 13 years ago

Audio/HDA: reinitialize pointer to verb routine before every lookup and don't try process verb vith NULL verb routine.
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1/* $Id: DevIchIntelHDA.cpp 40112 2012-02-14 02:05:25Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/vmm/pdmdev.h>
23#include <VBox/version.h>
24
25#include <iprt/assert.h>
26#include <iprt/uuid.h>
27#include <iprt/string.h>
28#include <iprt/mem.h>
29#include <iprt/asm.h>
30#include <iprt/asm-math.h>
31
32#include "VBoxDD.h"
33
34extern "C" {
35#include "audio.h"
36}
37#include "DevCodec.h"
38
39#define VBOX_WITH_INTEL_HDA
40
41#if defined(VBOX_WITH_HP_HDA)
42/* HP Pavilion dv4t-1300 */
43# define HDA_PCI_VENDOR_ID 0x103c
44# define HDA_PCI_DEICE_ID 0x30f7
45#elif defined(VBOX_WITH_INTEL_HDA)
46/* Intel HDA controller */
47# define HDA_PCI_VENDOR_ID 0x8086
48# define HDA_PCI_DEICE_ID 0x2668
49#elif defined(VBOX_WITH_NVIDIA_HDA)
50/* nVidia HDA controller */
51# define HDA_PCI_VENDOR_ID 0x10de
52# define HDA_PCI_DEICE_ID 0x0ac0
53#else
54# error "Please specify your HDA device vendor/device IDs"
55#endif
56
57PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
58PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb);
59static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
60
61#define HDA_NREGS 112
62/* Registers */
63#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
64#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
65#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
66#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
67#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
68#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
69#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
70#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
71#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
72#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
73
74#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
75#define GCAP(pState) (HDA_REG((pState), GCAP))
76/* GCAP HDASpec 3.3.2 This macro compact following information about HDA
77 * oss (15:12) - number of output streams supported
78 * iss (11:8) - number of input streams supported
79 * bss (7:3) - number of bidirection streams suppoted
80 * bds (2:1) - number of serial data out signals supported
81 * b64sup (0) - 64 bit addressing supported.
82 */
83#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
84 ( (((oss) & 0xF) << 12) \
85 | (((iss) & 0xF) << 8) \
86 | (((bss) & 0x1F) << 3) \
87 | (((bds) & 0x3) << 2) \
88 | ((b64sup) & 1))
89#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
90#define VMIN(pState) (HDA_REG((pState), VMIN))
91
92#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
93#define VMAJ(pState) (HDA_REG((pState), VMAJ))
94
95#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
96#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
97
98#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
99#define INPAY(pState) (HDA_REG((pState), INPAY))
100
101#define ICH6_HDA_REG_GCTL (5)
102#define ICH6_HDA_GCTL_RST_SHIFT (0)
103#define ICH6_HDA_GCTL_FSH_SHIFT (1)
104#define ICH6_HDA_GCTL_UR_SHIFT (8)
105#define GCTL(pState) (HDA_REG((pState), GCTL))
106
107#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
108#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
109
110#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
111#define STATESTS(pState) (HDA_REG((pState), STATESTS))
112#define ICH6_HDA_STATES_SCSF 0x7
113
114#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
115#define ICH6_HDA_GSTS_FSH_SHIFT (1)
116#define GSTS(pState) (HDA_REG(pState, GSTS))
117
118#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
119#define ICH6_HDA_INTCTL_GIE_SHIFT 31
120#define ICH6_HDA_INTCTL_CIE_SHIFT 30
121#define ICH6_HDA_INTCTL_S0_SHIFT (0)
122#define ICH6_HDA_INTCTL_S1_SHIFT (1)
123#define ICH6_HDA_INTCTL_S2_SHIFT (2)
124#define ICH6_HDA_INTCTL_S3_SHIFT (3)
125#define ICH6_HDA_INTCTL_S4_SHIFT (4)
126#define ICH6_HDA_INTCTL_S5_SHIFT (5)
127#define ICH6_HDA_INTCTL_S6_SHIFT (6)
128#define ICH6_HDA_INTCTL_S7_SHIFT (7)
129#define INTCTL(pState) (HDA_REG((pState), INTCTL))
130#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
131#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
132#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
133#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
134
135/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
136 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
137 * the datasheet.
138 */
139#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
140#define SSYNC(pState) (HDA_REG((pState), SSYNC))
141
142#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
143#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
144#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
145#define ICH6_HDA_INTSTS_S0_SHIFT (0)
146#define ICH6_HDA_INTSTS_S1_SHIFT (1)
147#define ICH6_HDA_INTSTS_S2_SHIFT (2)
148#define ICH6_HDA_INTSTS_S3_SHIFT (3)
149#define ICH6_HDA_INTSTS_S4_SHIFT (4)
150#define ICH6_HDA_INTSTS_S5_SHIFT (5)
151#define ICH6_HDA_INTSTS_S6_SHIFT (6)
152#define ICH6_HDA_INTSTS_S7_SHIFT (7)
153#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
154#define INTSTS(pState) (HDA_REG((pState), INTSTS))
155#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
156#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
157#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
158#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
159
160#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
161#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
162#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
163#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
164#define ICH6_HDA_REG_CORBWP 15 /* 48 */
165#define ICH6_HDA_REG_CORBRP 16 /* 4A */
166#define ICH6_HDA_CORBRP_RST_SHIFT 15
167#define ICH6_HDA_CORBRP_WP_SHIFT 0
168#define ICH6_HDA_CORBRP_WP_MASK 0xFF
169
170#define CORBRP(pState) (HDA_REG(pState, CORBRP))
171#define CORBWP(pState) (HDA_REG(pState, CORBWP))
172
173#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
174#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
175#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
176
177#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
178
179
180#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
181#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
182#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
183
184#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
185#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
186#define ICH6_HDA_CORBSIZE_SZ 0x3
187#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
188#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
189/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
190
191#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
192#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
193
194#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
195#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
196
197#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
198#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
199#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
200#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
201
202#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
203#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
204#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
205
206#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
207#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
208#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
209#define ICH6_HDA_ROI_DMA_SHIFT (2)
210#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
211#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
212#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
213#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
214
215#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
216#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
217#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
218#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
219#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
220#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
221
222#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
223#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
224#define ICH6_HDA_RIRBSIZE_SZ 0x3
225
226#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
227#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
228
229
230#define ICH6_HDA_REG_IC 27 /* 0x60 */
231#define IC(pState) (HDA_REG(pState, IC))
232#define ICH6_HDA_REG_IR 28 /* 0x64 */
233#define IR(pState) (HDA_REG(pState, IR))
234#define ICH6_HDA_REG_IRS 29 /* 0x68 */
235#define ICH6_HDA_IRS_ICB_SHIFT (0)
236#define ICH6_HDA_IRS_IRV_SHIFT (1)
237#define IRS(pState) (HDA_REG(pState, IRS))
238#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
239#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
240
241#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
242#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
243#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
244#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
245#define DPBASE_ENABLED 1
246#define DPBASE_ADDR_MASK (~0x7f)
247
248#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
249#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
250/* Note: sdnum here _MUST_ be stream reg number [0,7] */
251#define HDA_STREAM_REG2(pState, name, sdnum) (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
252
253#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
254#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
255#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
256#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
257#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
258#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
259#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
260#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
261
262#define SD(func, num) SD##num##func
263#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
264#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
265#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
266#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
267#define ICH6_HDA_SDCTL_DIR_SHIFT (19)
268#define ICH6_HDA_SDCTL_TP_SHIFT (18)
269#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)
270#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)
271#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
272#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
273#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
274#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
275#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
276
277#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
278#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
279#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
280#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
281#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
282#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
283#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
284#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
285
286#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
287#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
288#define ICH6_HDA_SDSTS_DE_SHIFT (4)
289#define ICH6_HDA_SDSTS_FE_SHIFT (3)
290#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
291
292#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
293#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
294#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
295#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
296#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
297#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
298#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
299#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
300
301#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
302
303#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
304#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
305#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
306#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
307#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
308#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
309#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
310#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
311
312#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
313
314#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
315#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
316#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
317#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
318#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
319#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
320#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
321#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
322
323#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
324
325#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
326#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
327#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
328#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
329#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
330#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
331#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
332#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
333
334/*
335 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
336 */
337#define HDA_SDFIFOW_8B (0x2)
338#define HDA_SDFIFOW_16B (0x3)
339#define HDA_SDFIFOW_32B (0x4)
340#define SDFIFOW(pState, num) HDA_REG((pState), SD(FIFOW, num))
341
342#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
343#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
344#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
345#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
346#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
347#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
348#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
349#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
350
351/*
352 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
353 * formula: size - 1
354 * Other values not listed are not supported.
355 */
356#define HDA_SDONFIFO_16B (0xF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
357#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
358#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
359#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
360#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
361#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
362#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
363#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
364#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
365
366#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
367#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
368#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
369#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
370#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
371#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
372#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
373#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
374
375#define SDFMT(pState, num) (HDA_REG((pState), SD(FMT, num)))
376#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
377#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
378#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
379#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
380#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
381#define ICH6_HDA_SDFMT_BITS_SHIFT (4)
382#define ICH6_HDA_SDFMT_BITS_MASK (0x7)
383#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
384#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
385#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
386
387#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
388#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
389#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
390#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
391#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
392#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
393#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
394#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
395
396#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
397
398#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
399#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
400#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
401#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
402#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
403#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
404#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
405#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
406
407#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
408
409
410typedef struct HDABDLEDESC
411{
412 uint64_t u64BdleCviAddr;
413 uint32_t u32BdleMaxCvi;
414 uint32_t u32BdleCvi;
415 uint32_t u32BdleCviLen;
416 uint32_t u32BdleCviPos;
417 bool fBdleCviIoc;
418 uint32_t cbUnderFifoW;
419 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
420} HDABDLEDESC, *PHDABDLEDESC;
421
422
423/** HDABDLEDESC field descriptors the v3+ saved state. */
424static SSMFIELD const g_aHdaBDLEDescFields[] =
425{
426 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
427 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
428 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
429 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
430 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
431 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
432 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
433 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
434 SSMFIELD_ENTRY_TERM()
435};
436
437/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
438static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
439{
440 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
441 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
442 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
443 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
444 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
445 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
446 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
447 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
448 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
449 SSMFIELD_ENTRY_TERM()
450};
451
452typedef struct HDASTREAMTRANSFERDESC
453{
454 uint64_t u64BaseDMA;
455 uint32_t u32Ctl;
456 uint32_t *pu32Sts;
457 uint8_t u8Strm;
458 uint32_t *pu32Lpib;
459 uint32_t u32Cbl;
460 uint32_t u32Fifos;
461} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
462
463typedef struct INTELHDLinkState
464{
465 /** Pointer to the device instance. */
466 PPDMDEVINSR3 pDevIns;
467 /** Pointer to the connector of the attached audio driver. */
468 PPDMIAUDIOCONNECTOR pDrv;
469 /** Pointer to the attached audio driver. */
470 PPDMIBASE pDrvBase;
471 /** The base interface for LUN\#0. */
472 PDMIBASE IBase;
473 RTGCPHYS addrMMReg;
474 uint32_t au32Regs[HDA_NREGS];
475 HDABDLEDESC stInBdle;
476 HDABDLEDESC stOutBdle;
477 HDABDLEDESC stMicBdle;
478 /* Interrupt on completion */
479 bool fCviIoc;
480 uint64_t u64CORBBase;
481 uint64_t u64RIRBBase;
482 uint64_t u64DPBase;
483 /* pointer on CORB buf */
484 uint32_t *pu32CorbBuf;
485 /* size in bytes of CORB buf */
486 uint32_t cbCorbBuf;
487 /* pointer on RIRB buf */
488 uint64_t *pu64RirbBuf;
489 /* size in bytes of RIRB buf */
490 uint32_t cbRirbBuf;
491 /* indicates if HDA in reset. */
492 bool fInReset;
493 CODECState Codec;
494 uint8_t u8Counter;
495 uint64_t u64BaseTS;
496} INTELHDLinkState, *PINTELHDLinkState;
497
498#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
499#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
500
501#define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In, \
502 SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
503#define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out, \
504 SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
505
506
507
508
509typedef struct PCIINTELHDLinkState
510{
511 PCIDevice dev;
512 INTELHDLinkState hda;
513} PCIINTELHDLinkState;
514
515
516DECLCALLBACK(int) hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
517DECLCALLBACK(int) hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
518DECLCALLBACK(int) hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
519DECLCALLBACK(int) hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
520DECLCALLBACK(int) hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
521DECLCALLBACK(int) hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
522DECLCALLBACK(int) hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
523DECLCALLBACK(int) hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
524DECLCALLBACK(int) hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
525DECLCALLBACK(int) hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
526DECLCALLBACK(int) hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
527DECLCALLBACK(int) hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
528DECLCALLBACK(int) hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
529DECLCALLBACK(int) hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
530DECLCALLBACK(int) hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
531DECLCALLBACK(int) hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
532DECLCALLBACK(int) hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
533DECLCALLBACK(int) hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
534DECLCALLBACK(int) hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
535DECLCALLBACK(int) hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
536
537DECLCALLBACK(int) hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
538DECLCALLBACK(int) hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
539DECLCALLBACK(int) hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
540DECLCALLBACK(int) hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
541DECLCALLBACK(int) hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
542DECLCALLBACK(int) hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
543DECLCALLBACK(int) hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
544DECLCALLBACK(int) hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
545DECLCALLBACK(int) hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
546DECLCALLBACK(int) hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
547DECLCALLBACK(int) hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
548DECLCALLBACK(int) hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
549DECLCALLBACK(int) hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
550DECLCALLBACK(int) hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
551DECLCALLBACK(int) hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
552DECLCALLBACK(int) hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
553
554static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc);
555static int hdaMMIORegLookup(INTELHDLinkState* pState, uint32_t u32Offset);
556static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
557#ifdef LOG_ENABLED
558static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
559#endif
560
561
562/* see 302349 p 6.2*/
563const static struct stIchIntelHDRegMap
564{
565 /** Register offset in the register space. */
566 uint32_t offset;
567 /** Size in bytes. Registers of size > 4 are in fact tables. */
568 uint32_t size;
569 /** Readable bits. */
570 uint32_t readable;
571 /** Writable bits. */
572 uint32_t writable;
573 /** Read callback. */
574 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
575 /** Write callback. */
576 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
577 /** Abbreviated name. */
578 const char *abbrev;
579 /** Full name. */
580 const char *name;
581} s_ichIntelHDRegMap[HDA_NREGS] =
582{
583 /* offset size read mask write mask read callback write callback abbrev full name */
584 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
585 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
586 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
587 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
588 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
589 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
590 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
591 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
592 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
593 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
594 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
595 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
596 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
597 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
598 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
599 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
600 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
601 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
602 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
603 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
604 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
605 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
606 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
607 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
608 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
609 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
610 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
611 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
612 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
613 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
614 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
615 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
616 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
617 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
618
619 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
620 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
621 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
622 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
623 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
624 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
625 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
626 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
627 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
628 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
629
630 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
631 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
632 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
633 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
634 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
635 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
636 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
637 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
638 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
639 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
640
641 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
642 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
643 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
644 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
645 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
646 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
647 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
648 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
649 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
650 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
651
652 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
653 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
654 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
655 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
656 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
657 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
658 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
659 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
660 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
661 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
662
663 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
664 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
665 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
666 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
667 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
668 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
669 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
670 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
671 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
672 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
673
674 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
675 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
676 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
677 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
678 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
679 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
680 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
681 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
682 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
683 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
684
685 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
686 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
687 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
688 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
689 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
690 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
691 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
692 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
693 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
694 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
695
696 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
697 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
698 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
699 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
700 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
701 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
702 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
703 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
704 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
705 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
706};
707
708static void inline hdaUpdatePosBuf(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
709{
710 if (pState->u64DPBase & DPBASE_ENABLED)
711 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
712 (pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
713}
714static uint32_t inline hdaFifoWToSz(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
715{
716#if 0
717 switch(HDA_STREAM_REG2(pState, FIFOW, pStreamDesc->u8Strm))
718 {
719 case HDA_SDFIFOW_8B: return 8;
720 case HDA_SDFIFOW_16B: return 16;
721 case HDA_SDFIFOW_32B: return 32;
722 default:
723 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
724 }
725#endif
726 return 0;
727}
728
729static int hdaProcessInterrupt(INTELHDLinkState* pState)
730{
731#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
732 ( INTCTL_SX((pState), num) \
733 && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
734 bool fIrq = false;
735 if ( INTCTL_CIE(pState)
736 && ( RIRBSTS_RINTFL(pState)
737 || RIRBSTS_RIRBOIS(pState)
738 || (STATESTS(pState) & WAKEEN(pState))))
739 fIrq = true;
740
741 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
742 || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
743 fIrq = true;
744
745 if (INTCTL_GIE(pState))
746 {
747 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
748 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
749 }
750 return VINF_SUCCESS;
751}
752
753static int hdaMMIORegLookup(INTELHDLinkState* pState, uint32_t u32Offset)
754{
755 int idxMiddle;
756 int idxHigh = RT_ELEMENTS(s_ichIntelHDRegMap);
757 int idxLow = 0;
758 /* Aliases HDA spec 3.3.45 */
759 switch(u32Offset)
760 {
761 case 0x2084:
762 return HDA_REG_IND_NAME(SD0LPIB);
763 case 0x20A4:
764 return HDA_REG_IND_NAME(SD1LPIB);
765 case 0x20C4:
766 return HDA_REG_IND_NAME(SD2LPIB);
767 case 0x20E4:
768 return HDA_REG_IND_NAME(SD3LPIB);
769 case 0x2104:
770 return HDA_REG_IND_NAME(SD4LPIB);
771 case 0x2124:
772 return HDA_REG_IND_NAME(SD5LPIB);
773 case 0x2144:
774 return HDA_REG_IND_NAME(SD6LPIB);
775 case 0x2164:
776 return HDA_REG_IND_NAME(SD7LPIB);
777 }
778 while (1)
779 {
780#ifdef DEBUG_vvl
781 Assert(( idxHigh >= 0
782 && idxLow >= 0));
783#endif
784 if ( idxHigh < idxLow
785 || idxHigh < 0)
786 break;
787 idxMiddle = idxLow + (idxHigh - idxLow)/2;
788 if (u32Offset < s_ichIntelHDRegMap[idxMiddle].offset)
789 {
790 idxHigh = idxMiddle - 1;
791 continue;
792 }
793 if (u32Offset >= s_ichIntelHDRegMap[idxMiddle].offset + s_ichIntelHDRegMap[idxMiddle].size)
794 {
795 idxLow = idxMiddle + 1;
796 continue;
797 }
798 if ( u32Offset >= s_ichIntelHDRegMap[idxMiddle].offset
799 && u32Offset < s_ichIntelHDRegMap[idxMiddle].offset + s_ichIntelHDRegMap[idxMiddle].size)
800 return idxMiddle;
801 }
802 return -1;
803}
804
805static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
806{
807 int rc = VINF_SUCCESS;
808 if (fLocal)
809 {
810 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
811 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
812 if (RT_FAILURE(rc))
813 AssertRCReturn(rc, rc);
814#ifdef DEBUG_CMD_BUFFER
815 uint8_t i = 0;
816 do
817 {
818 Log(("hda: corb%02x: ", i));
819 uint8_t j = 0;
820 do
821 {
822 const char *prefix;
823 if ((i + j) == CORBRP(pState))
824 prefix = "[R]";
825 else if ((i + j) == CORBWP(pState))
826 prefix = "[W]";
827 else
828 prefix = " "; /* three spaces */
829 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
830 j++;
831 } while (j < 8);
832 Log(("\n"));
833 i += 8;
834 } while(i != 0);
835#endif
836 }
837 else
838 {
839 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
840 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
841 if (RT_FAILURE(rc))
842 AssertRCReturn(rc, rc);
843#ifdef DEBUG_CMD_BUFFER
844 uint8_t i = 0;
845 do {
846 Log(("hda: rirb%02x: ", i));
847 uint8_t j = 0;
848 do {
849 const char *prefix;
850 if ((i + j) == RIRBWP(pState))
851 prefix = "[W]";
852 else
853 prefix = " ";
854 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
855 } while (++j < 8);
856 Log(("\n"));
857 i += 8;
858 } while (i != 0);
859#endif
860 }
861 return rc;
862}
863
864static int hdaCORBCmdProcess(INTELHDLinkState *pState)
865{
866 int rc;
867 uint8_t corbRp;
868 uint8_t corbWp;
869 uint8_t rirbWp;
870
871 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
872
873 rc = hdaCmdSync(pState, true);
874 if (RT_FAILURE(rc))
875 AssertRCReturn(rc, rc);
876 corbRp = CORBRP(pState);
877 corbWp = CORBWP(pState);
878 rirbWp = RIRBWP(pState);
879 Assert((corbWp != corbRp));
880 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
881 while (corbRp != corbWp)
882 {
883 uint32_t cmd;
884 uint64_t resp;
885 pfn = (PFNCODECVERBPROCESSOR)NULL;
886 corbRp++;
887 cmd = pState->pu32CorbBuf[corbRp];
888 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
889 if (RT_FAILURE(rc))
890 AssertRCReturn(rc, rc);
891 Assert(pfn);
892 (rirbWp)++;
893
894 if (RT_LIKELY(pfn))
895 rc = pfn(&pState->Codec, cmd, &resp);
896 else
897 rc = VERR_INVALID_FUNCTION;
898
899 if (RT_FAILURE(rc))
900 AssertRCReturn(rc, rc);
901 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
902 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
903 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
904 {
905 Log(("hda: unexpected unsolicited response.\n"));
906 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
907 return rc;
908 }
909 pState->pu64RirbBuf[rirbWp] = resp;
910 pState->u8Counter++;
911 if (pState->u8Counter == RINTCNT_N(pState))
912 break;
913 }
914 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
915 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
916 rc = hdaCmdSync(pState, false);
917 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
918 if (RIRBCTL_RIRB_RIC(pState))
919 {
920 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
921 pState->u8Counter = 0;
922 rc = hdaProcessInterrupt(pState);
923 }
924 if (RT_FAILURE(rc))
925 AssertRCReturn(rc, rc);
926 return rc;
927}
928
929static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
930{
931 Log(("hda: reset of stream (%d) started\n", u8Strm));
932 Assert(( pState
933 && pBdle
934 && pStreamDesc
935 && u8Strm <= 7));
936 memset(pBdle, 0, sizeof(HDABDLEDESC));
937 *pStreamDesc->pu32Lpib = 0;
938 *pStreamDesc->pu32Sts = 0;
939 /* According to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
940 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
941 HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
942
943 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
944 HDA_STREAM_REG2(pState, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
945 HDA_STREAM_REG2(pState, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
946 HDA_STREAM_REG2(pState, CBL, u8Strm) = 0;
947 HDA_STREAM_REG2(pState, LVI, u8Strm) = 0;
948 HDA_STREAM_REG2(pState, FMT, u8Strm) = 0;
949 HDA_STREAM_REG2(pState, BDPU, u8Strm) = 0;
950 HDA_STREAM_REG2(pState, BDPL, u8Strm) = 0;
951 Log(("hda: reset of stream (%d) finished\n", u8Strm));
952}
953
954
955DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
956{
957 *pu32Value = 0;
958 return VINF_SUCCESS;
959}
960DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
961{
962 return VINF_SUCCESS;
963}
964/* U8 */
965DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
966{
967 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
968 return hdaRegReadU32(pState, offset, index, pu32Value);
969}
970
971DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
972{
973 Assert(((u32Value & 0xffffff00) == 0));
974 return hdaRegWriteU32(pState, offset, index, u32Value);
975}
976/* U16 */
977DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
978{
979 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
980 return hdaRegReadU32(pState, offset, index, pu32Value);
981}
982
983DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
984{
985 Assert(((u32Value & 0xffff0000) == 0));
986 return hdaRegWriteU32(pState, offset, index, u32Value);
987}
988
989/* U24 */
990DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
991{
992 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
993 return hdaRegReadU32(pState, offset, index, pu32Value);
994}
995
996DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
997{
998 Assert(((u32Value & 0xff000000) == 0));
999 return hdaRegWriteU32(pState, offset, index, u32Value);
1000}
1001/* U32 */
1002DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1003{
1004 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
1005 return VINF_SUCCESS;
1006}
1007
1008DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1009{
1010 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
1011 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
1012 return VINF_SUCCESS;
1013}
1014
1015DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1016{
1017 return hdaRegReadU32(pState, offset, index, pu32Value);
1018}
1019
1020DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1021{
1022 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1023 {
1024 /* exit reset state */
1025 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1026 pState->fInReset = false;
1027 }
1028 else
1029 {
1030 /* enter reset state*/
1031 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
1032 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
1033 {
1034 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1035 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
1036 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
1037 }
1038 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
1039 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1040 pState->fInReset = true;
1041 }
1042 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1043 {
1044 /* Flush: GSTS:1 set, see 6.2.6*/
1045 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1046 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
1047 }
1048 return VINF_SUCCESS;
1049}
1050
1051DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1052{
1053 uint32_t v = pState->au32Regs[index];
1054 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
1055 pState->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
1056 return VINF_SUCCESS;
1057}
1058
1059DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1060{
1061 uint32_t v = 0;
1062 if ( RIRBSTS_RIRBOIS(pState)
1063 || RIRBSTS_RINTFL(pState)
1064 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
1065 || STATESTS(pState))
1066 v |= RT_BIT(30);
1067#define HDA_IS_STREAM_EVENT(pState, stream) \
1068 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1069 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1070 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1071#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
1072 MARK_STREAM(pState, 0, v);
1073 MARK_STREAM(pState, 1, v);
1074 MARK_STREAM(pState, 2, v);
1075 MARK_STREAM(pState, 3, v);
1076 MARK_STREAM(pState, 4, v);
1077 MARK_STREAM(pState, 5, v);
1078 MARK_STREAM(pState, 6, v);
1079 MARK_STREAM(pState, 7, v);
1080 v |= v ? RT_BIT(31) : 0;
1081 *pu32Value = v;
1082 return VINF_SUCCESS;
1083}
1084
1085DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1086{
1087 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1088 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pState)) - pState->u64BaseTS, 24, 1000);
1089 return VINF_SUCCESS;
1090}
1091
1092DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1093{
1094 return hdaRegReadU16(pState, offset, index, pu32Value);
1095}
1096
1097DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1098{
1099 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1100 CORBRP(pState) = 0;
1101 else
1102 return hdaRegWriteU8(pState, offset, index, u32Value);
1103 return VINF_SUCCESS;
1104}
1105
1106DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1107{
1108 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
1109 AssertRC(rc);
1110 if ( CORBWP(pState) != CORBRP(pState)
1111 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
1112 return hdaCORBCmdProcess(pState);
1113 return rc;
1114}
1115
1116DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1117{
1118 uint32_t v = CORBSTS(pState);
1119 CORBSTS(pState) &= ~(v & u32Value);
1120 return VINF_SUCCESS;
1121}
1122
1123DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1124{
1125 int rc;
1126 rc = hdaRegWriteU16(pState, offset, index, u32Value);
1127 if (RT_FAILURE(rc))
1128 AssertRCReturn(rc, rc);
1129 if (CORBWP(pState) == CORBRP(pState))
1130 return VINF_SUCCESS;
1131 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1132 return VINF_SUCCESS;
1133 rc = hdaCORBCmdProcess(pState);
1134 return rc;
1135}
1136
1137DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1138{
1139 return hdaRegReadU24(pState, offset, index, pu32Value);
1140}
1141
1142DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1143{
1144 bool fRun = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1145 bool fInRun = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1146 bool fReset = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1147 bool fInReset = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1148 int rc = VINF_SUCCESS;
1149 if (fInReset)
1150 {
1151 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1152 * from reset
1153 */
1154 Assert((!fReset));
1155 Log(("hda: guest initiate exit of stream reset.\n"));
1156 goto done;
1157 }
1158 else if (fReset)
1159 {
1160 /*
1161 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1162 */
1163 uint8_t u8Strm = 0;
1164 PHDABDLEDESC pBdle = NULL;
1165 HDASTREAMTRANSFERDESC stStreamDesc;
1166 Assert((!fInRun && !fRun));
1167 switch (index)
1168 {
1169 case ICH6_HDA_REG_SD0CTL:
1170 u8Strm = 0;
1171 pBdle = &pState->stInBdle;
1172 break;
1173 case ICH6_HDA_REG_SD4CTL:
1174 u8Strm = 4;
1175 pBdle = &pState->stOutBdle;
1176 break;
1177 default:
1178 Log(("hda: changing SRST bit on non-attached stream\n"));
1179 goto done;
1180 }
1181 Log(("hda: guest initiate enter to stream reset.\n"));
1182 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1183 hdaStreamReset(pState, pBdle, &stStreamDesc, u8Strm);
1184 goto done;
1185 }
1186
1187 /* we enter here to change DMA states only */
1188 if ( (fInRun && !fRun)
1189 || (fRun && !fInRun))
1190 {
1191 Assert((!fReset && !fInReset));
1192 switch (index)
1193 {
1194 case ICH6_HDA_REG_SD0CTL:
1195 AUD_set_active_in(pState->Codec.SwVoiceIn, fRun);
1196 break;
1197 case ICH6_HDA_REG_SD4CTL:
1198 AUD_set_active_out(pState->Codec.SwVoiceOut, fRun);
1199 break;
1200 default:
1201 Log(("hda: changing RUN bit on non-attached stream\n"));
1202 goto done;
1203 }
1204 }
1205
1206 done:
1207 rc = hdaRegWriteU24(pState, offset, index, u32Value);
1208 if (RT_FAILURE(rc))
1209 AssertRCReturn(rc, VINF_SUCCESS);
1210 return rc;
1211}
1212
1213DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1214{
1215 uint32_t v = HDA_REG_IND(pState, index);
1216 v &= ~(u32Value & v);
1217 HDA_REG_IND(pState, index) = v;
1218 hdaProcessInterrupt(pState);
1219 return VINF_SUCCESS;
1220}
1221
1222DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1223{
1224 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1225 if (RT_FAILURE(rc))
1226 AssertRCReturn(rc, VINF_SUCCESS);
1227 return rc;
1228}
1229
1230DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1231{
1232 switch (u32Value)
1233 {
1234 case HDA_SDFIFOW_8B:
1235 case HDA_SDFIFOW_16B:
1236 case HDA_SDFIFOW_32B:
1237 return hdaRegWriteU16(pState, offset, index, u32Value);
1238 default:
1239 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1240 return hdaRegWriteU16(pState, offset, index, HDA_SDFIFOW_32B);
1241 }
1242 return VINF_SUCCESS;
1243}
1244/*
1245 * Note this method could be called for changing value on Output Streams only (ICH6 datacheet 18.2.39)
1246 *
1247 */
1248DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1249{
1250 switch (index)
1251 {
1252 /* SDInFIFOS is RO, n=0-3 */
1253 case ICH6_HDA_REG_SD0FIFOS:
1254 case ICH6_HDA_REG_SD1FIFOS:
1255 case ICH6_HDA_REG_SD2FIFOS:
1256 case ICH6_HDA_REG_SD3FIFOS:
1257 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1258 return VINF_SUCCESS;
1259 case ICH6_HDA_REG_SD4FIFOS:
1260 case ICH6_HDA_REG_SD5FIFOS:
1261 case ICH6_HDA_REG_SD6FIFOS:
1262 case ICH6_HDA_REG_SD7FIFOS:
1263 switch(u32Value)
1264 {
1265 case HDA_SDONFIFO_16B:
1266 case HDA_SDONFIFO_32B:
1267 case HDA_SDONFIFO_64B:
1268 case HDA_SDONFIFO_128B:
1269 case HDA_SDONFIFO_192B:
1270 return hdaRegWriteU16(pState, offset, index, u32Value);
1271
1272 case HDA_SDONFIFO_256B:
1273 Log(("hda: 256 bit is unsupported, HDA is switched into 192B mode\n"));
1274 default:
1275 return hdaRegWriteU16(pState, offset, index, HDA_SDONFIFO_192B);
1276 }
1277 return VINF_SUCCESS;
1278 default:
1279 AssertMsgFailed(("Something wierd happens with register lookup routine"));
1280 }
1281 return VINF_SUCCESS;
1282}
1283
1284static void inline hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1285{
1286 Assert((pAudSetting));
1287#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1288 uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1289 uint32_t u32HzMult = 1;
1290 uint32_t u32HzDiv = 1;
1291 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))
1292 {
1293 case 0: u32HzMult = 1; break;
1294 case 1: u32HzMult = 2; break;
1295 case 2: u32HzMult = 3; break;
1296 case 3: u32HzMult = 4; break;
1297 default:
1298 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1299 }
1300 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))
1301 {
1302 case 0: u32HzDiv = 1; break;
1303 case 1: u32HzDiv = 2; break;
1304 case 2: u32HzDiv = 3; break;
1305 case 3: u32HzDiv = 4; break;
1306 case 4: u32HzDiv = 5; break;
1307 case 5: u32HzDiv = 6; break;
1308 case 6: u32HzDiv = 7; break;
1309 case 7: u32HzDiv = 8; break;
1310 }
1311 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1312
1313 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_BITS_MASK, ICH6_HDA_SDFMT_BITS_SHIFT))
1314 {
1315 case 0:
1316 Log(("hda: %s requested 8 bit\n", __FUNCTION__));
1317 pAudSetting->fmt = AUD_FMT_S8;
1318 break;
1319 case 1:
1320 Log(("hda: %s requested 16 bit\n", __FUNCTION__));
1321 pAudSetting->fmt = AUD_FMT_S16;
1322 break;
1323 case 2:
1324 Log(("hda: %s requested 20 bit\n", __FUNCTION__));
1325 break;
1326 case 3:
1327 Log(("hda: %s requested 24 bit\n", __FUNCTION__));
1328 break;
1329 case 4:
1330 Log(("hda: %s requested 32 bit\n", __FUNCTION__));
1331 pAudSetting->fmt = AUD_FMT_S32;
1332 break;
1333 default:
1334 AssertMsgFailed(("Unsupported"));
1335 }
1336 pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;
1337 pAudSetting->fmt = AUD_FMT_S16;
1338 pAudSetting->endianness = 0;
1339#undef EXTRACT_VALUE
1340}
1341
1342DECLCALLBACK(int)hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1343{
1344#ifdef VBOX_WITH_HDA_CODEC_EMU
1345 /* @todo here some more investigations are required. */
1346 int rc = 0;
1347 audsettings_t as;
1348 /* no reason to reopen voice with same settings */
1349 if (u32Value == HDA_REG_IND(pState, index))
1350 return VINF_SUCCESS;
1351 hdaSdFmtToAudSettings(u32Value, &as);
1352 switch (index)
1353 {
1354 case ICH6_HDA_REG_SD0FMT:
1355 rc = codecOpenVoice(&pState->Codec, PI_INDEX, &as);
1356 break;
1357 case ICH6_HDA_REG_SD4FMT:
1358 rc = codecOpenVoice(&pState->Codec, PO_INDEX, &as);
1359 break;
1360 default:
1361 Log(("HDA: attempt to change format on %d\n", index));
1362 rc = 0;
1363 }
1364 return hdaRegWriteU16(pState, offset, index, u32Value);
1365#else
1366 return hdaRegWriteU16(pState, offset, index, u32Value);
1367#endif
1368}
1369
1370DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1371{
1372 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1373 if (RT_FAILURE(rc))
1374 AssertRCReturn(rc, VINF_SUCCESS);
1375 return rc;
1376}
1377
1378DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1379{
1380 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1381 if (RT_FAILURE(rc))
1382 AssertRCReturn(rc, VINF_SUCCESS);
1383 return rc;
1384}
1385
1386DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1387{
1388 int rc = VINF_SUCCESS;
1389 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1390 if ( CORBWP(pState) != CORBRP(pState)
1391 || HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1392 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1393
1394 rc = hdaRegReadU32(pState, offset, index, pu32Value);
1395 return rc;
1396}
1397
1398DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1399{
1400 int rc = VINF_SUCCESS;
1401 uint64_t resp;
1402 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1403 /*
1404 * if guest set ICB bit of IRS register HDA should process verb in IC register and
1405 * writes response in IR register and set IRV (valid in case of success) bit of IRS register.
1406 */
1407 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1408 && !IRS_ICB(pState))
1409 {
1410 uint32_t cmd = IC(pState);
1411 if (CORBWP(pState) != CORBRP(pState))
1412 {
1413 /*
1414 * 3.4.3 defines behaviour of immediate Command status register.
1415 */
1416 LogRel(("hda: guest has tried process immediate verb (%x) with active CORB\n", cmd));
1417 return rc;
1418 }
1419 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1420 Log(("hda: IC:%x\n", cmd));
1421 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1422 if (RT_FAILURE(rc))
1423 AssertRCReturn(rc, rc);
1424 rc = pfn(&pState->Codec, cmd, &resp);
1425 if (RT_FAILURE(rc))
1426 AssertRCReturn(rc, rc);
1427 IR(pState) = (uint32_t)resp;
1428 Log(("hda: IR:%x\n", IR(pState)));
1429 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1430 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1431 return rc;
1432 }
1433 /*
1434 * when guest's read the response it should clean the IRV bit of the IRS register.
1435 */
1436 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1437 && IRS_IRV(pState))
1438 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1439 return rc;
1440}
1441
1442DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1443{
1444 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1445 {
1446 RIRBWP(pState) = 0;
1447 }
1448 /*The rest of bits are O, see 6.2.22 */
1449 return VINF_SUCCESS;
1450}
1451
1452DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1453{
1454 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1455 if (RT_FAILURE(rc))
1456 AssertRCReturn(rc, rc);
1457 switch(index)
1458 {
1459 case ICH6_HDA_REG_CORBLBASE:
1460 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1461 pState->u64CORBBase |= pState->au32Regs[index];
1462 break;
1463 case ICH6_HDA_REG_CORBUBASE:
1464 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1465 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1466 break;
1467 case ICH6_HDA_REG_RIRLBASE:
1468 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1469 pState->u64RIRBBase |= pState->au32Regs[index];
1470 break;
1471 case ICH6_HDA_REG_RIRUBASE:
1472 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1473 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1474 break;
1475 case ICH6_HDA_REG_DPLBASE:
1476 /* @todo: first bit has special meaning */
1477 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1478 pState->u64DPBase |= pState->au32Regs[index];
1479 break;
1480 case ICH6_HDA_REG_DPUBASE:
1481 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1482 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1483 break;
1484 default:
1485 AssertMsgFailed(("Invalid index"));
1486 }
1487 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1488 return rc;
1489}
1490
1491DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1492{
1493 uint8_t v = RIRBSTS(pState);
1494 RIRBSTS(pState) &= ~(v & u32Value);
1495
1496 return hdaProcessInterrupt(pState);
1497}
1498
1499#ifdef LOG_ENABLED
1500static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1501{
1502#if 0
1503 uint64_t addr;
1504 uint32_t len;
1505 uint32_t ioc;
1506 uint8_t bdle[16];
1507 uint32_t counter;
1508 uint32_t i;
1509 uint32_t sum = 0;
1510 Assert(pBdle && pBdle->u32BdleMaxCvi);
1511 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1512 {
1513 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1514 addr = *(uint64_t *)bdle;
1515 len = *(uint32_t *)&bdle[8];
1516 ioc = *(uint32_t *)&bdle[12];
1517 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1518 sum += len;
1519 }
1520 Log(("hda: sum: %d\n", sum));
1521 for (i = 0; i < 8; ++i)
1522 {
1523 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1524 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
1525 i , counter));
1526 }
1527#endif
1528}
1529#endif
1530
1531static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1532{
1533 uint8_t bdle[16];
1534 Assert(( pStreamDesc->u64BaseDMA
1535 && pBdle
1536 && pBdle->u32BdleMaxCvi));
1537 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1538 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1539 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1540 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1541#ifdef LOG_ENABLED
1542 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1543#endif
1544}
1545
1546static inline uint32_t hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1547{
1548 uint32_t cb2Copy;
1549 /*
1550 * Amounts of bytes depends on current position in buffer (u32BdleCviLen-u32BdleCviPos)
1551 */
1552 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1553 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1554 /*
1555 * we may increase the counter in range of [0, FIFOS + 1]
1556 */
1557 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1558 Assert((u32SoundBackendBufferBytesAvail > 0));
1559
1560 /* sanity check to avoid overriding sound backend buffer */
1561 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1562 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1563
1564 if (cb2Copy <= pBdle->cbUnderFifoW)
1565 return 0;
1566 cb2Copy -= pBdle->cbUnderFifoW; /* forcely reserve amount of ureported bytes to copy */
1567 return cb2Copy;
1568}
1569
1570static inline void hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1571{
1572 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1573 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1574 Assert((cbCopied));
1575 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1576 /* Assertion!!! It was copied less than cbUnderFifoW
1577 * Probably we need to move the buffer, but it rather hard to imagine situation
1578 * why it may happen.
1579 */
1580 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write whole buffer including not reported bytes */
1581 if ( pBdle->cbUnderFifoW
1582 && pBdle->cbUnderFifoW <= cbCopied)
1583 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1584
1585 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1586 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Assumption failed */
1587
1588 /* We always increment position on DMA buffer counter because we're always reading to intermediate buffer */
1589 pBdle->u32BdleCviPos += cbArranged2Copy;
1590
1591 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1592 /* We reports all bytes (including unreported previously) */
1593 *pu32DMACursor += cbCopied;
1594 /* reducing backend counter on amount of bytes we copied to backend */
1595 *pu32BackendBufferCapacity -= cbCopied;
1596 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1597 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1598}
1599
1600static inline void hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1601{
1602 Assert((cbCopied, cbArranged2Copy));
1603 *pu32BackendBufferCapacity -= cbCopied;
1604 pBdle->u32BdleCviPos += cbCopied;
1605 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1606 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1607 pBdle->cbUnderFifoW = 0;
1608 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1609 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1610}
1611
1612static inline void hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1613{
1614 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1615 pBdle->u32BdleCviPos += cbCopied;
1616 pBdle->cbUnderFifoW += cbCopied;
1617 /* In case of read transaction we're always coping from backend buffer */
1618 if (pu32BackendBufferCapacity)
1619 *pu32BackendBufferCapacity -= cbCopied;
1620 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1621 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pState, pStreamDesc)));
1622}
1623static inline bool hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1624{
1625 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1626 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1627
1628 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1629
1630 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1631 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1632 hdaUpdatePosBuf(pState, pStreamDesc);
1633
1634 /* don't touch BdleCvi counter on uninitialized descriptor */
1635 if ( pBdle->u32BdleCviPos
1636 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1637 {
1638 pBdle->u32BdleCviPos = 0;
1639 pBdle->u32BdleCvi++;
1640 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1641 pBdle->u32BdleCvi = 0;
1642 }
1643 return fOnBufferEdge;
1644}
1645
1646static inline void hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbInc)
1647{
1648 /*
1649 * if we're under FIFO Watermark it's expected that HDA doesn't fetch anything.
1650 * (ICH6 datasheet 18.2.38)
1651 */
1652 if (!pBdle->cbUnderFifoW)
1653 {
1654 *pStreamDesc->pu32Lpib += cbInc;
1655
1656 /*
1657 * Assert. Overlapping of buffer counter shouldn't happen.
1658 */
1659 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1660
1661 hdaUpdatePosBuf(pState, pStreamDesc);
1662
1663 }
1664}
1665
1666static inline bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1667{
1668 bool fDoNextTransferLoop = true;
1669 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1670 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1671 {
1672 if ( !pBdle->cbUnderFifoW
1673 && pBdle->fBdleCviIoc)
1674 {
1675 /*
1676 * @todo - more carefully investigate BCIS flag.
1677 * Speech synthesis works fine on Mac Guest if this bit isn't set
1678 * but in general sound quality becomes lesser.
1679 */
1680 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1681
1682 /*
1683 * we should generate the interrupt if ICE bit of SDCTL register is set.
1684 */
1685 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1686 hdaProcessInterrupt(pState);
1687 }
1688 fDoNextTransferLoop = false;
1689 }
1690 return fDoNextTransferLoop;
1691}
1692
1693/*
1694 * hdaReadAudio - copies samples from Qemu Sound back-end to DMA.
1695 * Note: this function writes immediately to DMA buffer, but "reports bytes" when all conditions meet (FIFOW)
1696 */
1697static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1698{
1699 PHDABDLEDESC pBdle = &pState->stInBdle;
1700 uint32_t cbTransfered = 0;
1701 uint32_t cb2Copy = 0;
1702 uint32_t cbBackendCopy = 0;
1703
1704 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1705
1706 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1707 if (!cb2Copy)
1708 {
1709 /* if we enter here we can't report "unreported bits" */
1710 *fStop = true;
1711 goto done;
1712 }
1713
1714
1715 /*
1716 * read from backend input line to last ureported position or at the begining.
1717 */
1718 cbBackendCopy = AUD_read (pState->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1719 /*
1720 * write on the HDA DMA
1721 */
1722 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1723
1724 /* Don't see reasons why cb2Copy could differ from cbBackendCopy */
1725 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1726
1727 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pState, 0))
1728 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1729 else
1730 {
1731 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1732 *fStop = true;
1733 }
1734 done:
1735 Assert((cbTransfered <= (SDFIFOS(pState, 0) + 1)));
1736 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransfered: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1737 return cbTransfered;
1738}
1739
1740static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1741{
1742 PHDABDLEDESC pBdle = &pState->stOutBdle;
1743 uint32_t cbTransfered = 0;
1744 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1745 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1746
1747 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1748
1749 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1750
1751 /*
1752 * Copy from DMA to the corresponding hdaBuffer (if there exists some bytes from the previous not reported transfer we write to ''pBdle->cbUnderFifoW'' offset)
1753 */
1754 if (!cb2Copy)
1755 {
1756 *fStop = true;
1757 goto done;
1758 }
1759
1760 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1761 /*
1762 * Write to audio backend. we should be sure whether we have enought bytes to copy to Audio backend.
1763 */
1764 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, pStreamDesc))
1765 {
1766 /*
1767 * We feed backend with new portion of fetched samples including not reported.
1768 */
1769 cbBackendCopy = AUD_write (pState->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1770 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1771 }
1772 else
1773 {
1774 /* Not enough bytes to be processed and reported, check luck on next enterence */
1775 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cb2Copy, NULL);
1776 *fStop = true;
1777 }
1778
1779 done:
1780 Assert((cbTransfered <= (SDFIFOS(pState, 4) + 1)));
1781 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransfered:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1782 return cbTransfered;
1783}
1784
1785DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1786{
1787 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1788 return VINF_SUCCESS;
1789}
1790
1791static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc)
1792{
1793 Assert(( pState
1794 && pBdle
1795 && pStreamDesc
1796 && u8Strm <= 7));
1797 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1798 pStreamDesc->u8Strm = u8Strm;
1799 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pState, CTL, u8Strm);
1800 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pState, BDPL, u8Strm),
1801 HDA_STREAM_REG2(pState, BDPU, u8Strm));
1802 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pState, LPIB, u8Strm);
1803 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pState, STS, u8Strm);
1804 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pState, CBL, u8Strm);
1805 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pState, FIFOS, u8Strm);
1806
1807 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pState, LVI, u8Strm);
1808#ifdef LOG_ENABLED
1809 if ( pBdle
1810 && pBdle->u32BdleMaxCvi)
1811 {
1812 Log(("Initialization of transfer descriptor:\n"));
1813 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1814 }
1815#endif
1816}
1817
1818DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1819{
1820 bool fStop = false;
1821 uint8_t u8Strm = 0;
1822 PHDABDLEDESC pBdle = NULL;
1823 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1824 HDASTREAMTRANSFERDESC stStreamDesc;
1825 uint32_t nBytes;
1826 switch (src)
1827 {
1828 case PO_INDEX:
1829 {
1830 u8Strm = 4;
1831 pBdle = &pState->stOutBdle;
1832 break;
1833 }
1834 case PI_INDEX:
1835 {
1836 u8Strm = 0;
1837 pBdle = &pState->stInBdle;
1838 break;
1839 }
1840 default:
1841 return;
1842 }
1843 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1844 while( avail && !fStop)
1845 {
1846 Assert ( (stStreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1847 && avail
1848 && stStreamDesc.u64BaseDMA);
1849
1850 /* Fetch the Buffer Descriptor Entry (BDE). */
1851
1852 if (hdaIsTransferCountersOverlapped(pState, pBdle, &stStreamDesc))
1853 hdaFetchBdle(pState, pBdle, &stStreamDesc);
1854 *stStreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1855 Assert((avail >= 0 && (stStreamDesc.u32Cbl >= (*stStreamDesc.pu32Lpib)))); /* sanity */
1856 uint32_t u32CblLimit = stStreamDesc.u32Cbl - (*stStreamDesc.pu32Lpib);
1857 Assert((u32CblLimit > hdaFifoWToSz(pState, &stStreamDesc)));
1858 Log(("hda: CBL=%d, LPIB=%d\n", stStreamDesc.u32Cbl, *stStreamDesc.pu32Lpib));
1859 switch (src)
1860 {
1861 case PO_INDEX:
1862 nBytes = hdaWriteAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1863 break;
1864 case PI_INDEX:
1865 nBytes = hdaReadAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1866 break;
1867 default:
1868 nBytes = 0;
1869 fStop = true;
1870 AssertMsgFailed(("Unsupported"));
1871 }
1872 Assert(nBytes <= (stStreamDesc.u32Fifos + 1));
1873 *stStreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1874
1875 /* Process end of buffer condition. */
1876 hdaStreamCounterUpdate(pState, pBdle, &stStreamDesc, nBytes);
1877 fStop = !fStop ? !hdaDoNextTransferCycle(pState, pBdle, &stStreamDesc) : fStop;
1878 }
1879}
1880
1881/**
1882 * Handle register read operation.
1883 *
1884 * Looks up and calls appropriate handler.
1885 *
1886 * @note: while implementation was detected so called "forgotten" or "hole" registers
1887 * which description is missed in RPM, datasheet or spec.
1888 *
1889 * @returns VBox status code.
1890 *
1891 * @param pState The device state structure.
1892 * @param uOffset Register offset in memory-mapped frame.
1893 * @param pv Where to fetch the value.
1894 * @param cb Number of bytes to write.
1895 * @thread EMT
1896 */
1897PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1898{
1899 int rc = VINF_SUCCESS;
1900 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1901 uint32_t offReg = GCPhysAddr - pThis->hda.addrMMReg;
1902 int idxReg = hdaMMIORegLookup(&pThis->hda, offReg);
1903 if (pThis->hda.fInReset && idxReg != ICH6_HDA_REG_GCTL)
1904 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1905
1906 if (idxReg == -1)
1907 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
1908
1909 if (idxReg != -1)
1910 {
1911 /** @todo r=bird: Accesses crossing register boundraries aren't handled
1912 * right from what I can tell? If they are, please explain
1913 * what the rules are. */
1914 uint32_t mask = 0;
1915 uint32_t shift = (s_ichIntelHDRegMap[idxReg].offset - offReg) % sizeof(uint32_t) * 8;
1916 uint32_t u32Value = 0;
1917 switch(cb)
1918 {
1919 case 1: mask = 0x000000ff; break;
1920 case 2: mask = 0x0000ffff; break;
1921 case 4:
1922 /* 18.2 of ICH6 datasheet defines wideness of the accesses byte, word and double word */
1923 case 8:
1924 mask = 0xffffffff;
1925 cb = 4;
1926 break;
1927 }
1928#if 0
1929 /* cross register access. Mac guest hit this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
1930 */
1931 //Assert((cb <= s_ichIntelHDRegMap[idxReg].size - (offReg - s_ichIntelHDRegMap[idxReg].offset)));
1932 if (cb > s_ichIntelHDRegMap[idxReg].size - (offReg - s_ichIntelHDRegMap[idxReg].offset))
1933 {
1934 int off = cb - (s_ichIntelHDRegMap[idxReg].size - (offReg - s_ichIntelHDRegMap[idxReg].offset));
1935 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
1936 if (RT_FAILURE(rc))
1937 AssertRCReturn (rc, rc);
1938 }
1939 //Assert(((offReg - s_ichIntelHDRegMap[idxReg].offset) == 0));
1940#endif
1941 mask <<= shift;
1942 rc = s_ichIntelHDRegMap[idxReg].pfnRead(&pThis->hda, offReg, idxReg, &u32Value);
1943 *(uint32_t *)pv |= (u32Value & mask);
1944 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[idxReg].abbrev, u32Value, *(uint32_t *)pv));
1945 return rc;
1946 }
1947 *(uint32_t *)pv = 0xFF;
1948 Log(("hda: hole at %x is accessed for read\n", offReg));
1949 return rc;
1950}
1951
1952/**
1953 * Handle register write operation.
1954 *
1955 * Looks up and calls appropriate handler.
1956 *
1957 * @returns VBox status code.
1958 *
1959 * @param pState The device state structure.
1960 * @param uOffset Register offset in memory-mapped frame.
1961 * @param pv Where to fetch the value.
1962 * @param cb Number of bytes to write.
1963 * @thread EMT
1964 */
1965PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1966{
1967 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1968 uint32_t offReg = GCPhysAddr - pThis->hda.addrMMReg;
1969 int idxReg = hdaMMIORegLookup(&pThis->hda, offReg);
1970 int rc = VINF_SUCCESS;
1971
1972 if (pThis->hda.fInReset && idxReg != ICH6_HDA_REG_GCTL)
1973 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1974
1975 if ( idxReg == -1
1976 || cb > 4)
1977 LogRel(("hda: Invalid write access @0x%x(of bytes:%d)\n", offReg, cb));
1978
1979 if (idxReg != -1)
1980 {
1981 /** @todo r=bird: This looks like code for handling unalinged register
1982 * accesses. If it isn't then, add a comment explaing what you're
1983 * trying to do here. OTOH, if it is then it has the following
1984 * issues:
1985 * -# You're calculating the wrong new value for the register.
1986 * -# You're not handling cross register accesses. Imagine a
1987 * 4-byte write starting at CORBCTL, or a 8-byte write.
1988 *
1989 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
1990 * nobody seems to be using it and it just add complexity when reading
1991 * the code.
1992 *
1993 */
1994 uint32_t u32CurValue = pThis->hda.au32Regs[idxReg];
1995 uint32_t u32NewValue;
1996 uint32_t mask;
1997 switch (cb)
1998 {
1999 case 1:
2000 u32NewValue = *(uint8_t const *)pv;
2001 mask = 0xff;
2002 break;
2003 case 2:
2004 u32NewValue = *(uint16_t const *)pv;
2005 mask = 0xffff;
2006 break;
2007 case 4:
2008 case 8:
2009 /* 18.2 of ICH6 datasheet defines wideness of the accesses byte, word and double word */
2010 u32NewValue = *(uint32_t const *)pv;
2011 mask = 0xffffffff;
2012 cb = 4;
2013 break;
2014 default:
2015 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
2016 }
2017 /* cross register access, see corresponding comment in hdaMMIORead */
2018#if 0
2019 if (cb > s_ichIntelHDRegMap[idxReg].size - (offReg - s_ichIntelHDRegMap[idxReg].offset))
2020 {
2021 int off = cb - (s_ichIntelHDRegMap[idxReg].size - (offReg - s_ichIntelHDRegMap[idxReg].offset));
2022 rc = hdaMMIOWrite(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2023 if (RT_FAILURE(rc))
2024 AssertRCReturn (rc, rc);
2025 }
2026#endif
2027 uint32_t shift = (s_ichIntelHDRegMap[idxReg].offset - offReg) % sizeof(uint32_t) * 8;
2028 mask <<= shift;
2029 u32NewValue <<= shift;
2030 u32NewValue &= mask;
2031 u32NewValue |= (u32CurValue & ~mask);
2032
2033 rc = s_ichIntelHDRegMap[idxReg].pfnWrite(&pThis->hda, offReg, idxReg, u32NewValue);
2034 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[idxReg].abbrev, u32NewValue,
2035 u32CurValue, pThis->hda.au32Regs[idxReg]));
2036 return rc;
2037 }
2038
2039 Log(("hda: hole at %x is accessed for write\n", offReg));
2040 return rc;
2041}
2042
2043/**
2044 * Callback function for mapping a PCI I/O region.
2045 *
2046 * @return VBox status code.
2047 * @param pPciDev Pointer to PCI device.
2048 * Use pPciDev->pDevIns to get the device instance.
2049 * @param iRegion The region number.
2050 * @param GCPhysAddress Physical address of the region.
2051 * If iType is PCI_ADDRESS_SPACE_IO, this is an
2052 * I/O port, else it's a physical address.
2053 * This address is *NOT* relative
2054 * to pci_mem_base like earlier!
2055 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
2056 */
2057static DECLCALLBACK(int) hdaMap(PPCIDEVICE pPciDev, int iRegion,
2058 RTGCPHYS GCPhysAddress, uint32_t cb,
2059 PCIADDRESSSPACE enmType)
2060{
2061 int rc;
2062 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2063 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
2064 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
2065
2066 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2067 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2068 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
2069 hdaMMIOWrite, hdaMMIORead, "ICH6_HDA");
2070
2071 if (RT_FAILURE(rc))
2072 return rc;
2073
2074 pThis->hda.addrMMReg = GCPhysAddress;
2075 return VINF_SUCCESS;
2076}
2077
2078/**
2079 * Saves a state of the HDA device.
2080 *
2081 * @returns VBox status code.
2082 * @param pDevIns The device instance.
2083 * @param pSSM The handle to save the state to.
2084 */
2085static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2086{
2087 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2088 /* Save Codec nodes states */
2089 codecSaveState(&pThis->hda.Codec, pSSM);
2090
2091 /* Save MMIO registers */
2092 AssertCompile(RT_ELEMENTS(pThis->hda.au32Regs) == 112);
2093 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->hda.au32Regs));
2094 SSMR3PutMem(pSSM, pThis->hda.au32Regs, sizeof(pThis->hda.au32Regs));
2095
2096 /* Save HDA dma counters */
2097 SSMR3PutStructEx(pSSM, &pThis->hda.stOutBdle, sizeof(pThis->hda.stOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2098 SSMR3PutStructEx(pSSM, &pThis->hda.stMicBdle, sizeof(pThis->hda.stMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2099 SSMR3PutStructEx(pSSM, &pThis->hda.stInBdle, sizeof(pThis->hda.stInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2100 return VINF_SUCCESS;
2101}
2102
2103/**
2104 * Loads a saved HDA device state.
2105 *
2106 * @returns VBox status code.
2107 * @param pDevIns The device instance.
2108 * @param pSSM The handle to the saved state.
2109 * @param uVersion The data unit version number.
2110 * @param uPass The data pass.
2111 */
2112static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2113{
2114 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2115
2116 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2117
2118 /*
2119 * Load Codec nodes states.
2120 */
2121 int rc = codecLoadState(&pThis->hda.Codec, pSSM, uVersion);
2122 if (RT_FAILURE(rc))
2123 return rc;
2124
2125 /*
2126 * Load MMIO registers.
2127 */
2128 uint32_t cRegs;
2129 switch (uVersion)
2130 {
2131 case HDA_SSM_VERSION_1:
2132 /* Starting with r71199, we would save 112 instead of 113
2133 registers due to some code cleanups. This only affects trunk
2134 builds in the 4.1 development period. */
2135 cRegs = 113;
2136 if (SSMR3HandleRevision(pSSM) >= 71199)
2137 {
2138 uint32_t uVer = SSMR3HandleVersion(pSSM);
2139 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
2140 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
2141 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
2142 cRegs = 112;
2143 }
2144 break;
2145
2146 case HDA_SSM_VERSION_2:
2147 case HDA_SSM_VERSION_3:
2148 cRegs = 112;
2149 AssertCompile(RT_ELEMENTS(pThis->hda.au32Regs) == 112);
2150 break;
2151
2152 case HDA_SSM_VERSION:
2153 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
2154 AssertLogRelMsgReturn(cRegs == RT_ELEMENTS(pThis->hda.au32Regs),
2155 ("cRegs is %d, expected %d\n", cRegs, RT_ELEMENTS(pThis->hda.au32Regs)),
2156 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2157 break;
2158
2159 default:
2160 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2161 }
2162
2163 if (cRegs >= RT_ELEMENTS(pThis->hda.au32Regs))
2164 {
2165 SSMR3GetMem(pSSM, pThis->hda.au32Regs, sizeof(pThis->hda.au32Regs));
2166 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->hda.au32Regs)));
2167 }
2168 else
2169 {
2170 RT_ZERO(pThis->hda.au32Regs);
2171 SSMR3GetMem(pSSM, pThis->hda.au32Regs, sizeof(uint32_t) * cRegs);
2172 }
2173
2174 /*
2175 * Load HDA dma counters.
2176 */
2177 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
2178 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
2179 SSMR3GetStructEx(pSSM, &pThis->hda.stOutBdle, sizeof(pThis->hda.stOutBdle), fFlags, paFields, NULL);
2180 SSMR3GetStructEx(pSSM, &pThis->hda.stMicBdle, sizeof(pThis->hda.stMicBdle), fFlags, paFields, NULL);
2181 rc = SSMR3GetStructEx(pSSM, &pThis->hda.stInBdle, sizeof(pThis->hda.stInBdle), fFlags, paFields, NULL);
2182 AssertRCReturn(rc, rc);
2183
2184 /*
2185 * Update stuff after the state changes.
2186 */
2187 AUD_set_active_in(pThis->hda.Codec.SwVoiceIn, SDCTL(&pThis->hda, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2188 AUD_set_active_out(pThis->hda.Codec.SwVoiceOut, SDCTL(&pThis->hda, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2189
2190 pThis->hda.u64CORBBase = RT_MAKE_U64(CORBLBASE(&pThis->hda), CORBUBASE(&pThis->hda));
2191 pThis->hda.u64RIRBBase = RT_MAKE_U64(RIRLBASE(&pThis->hda), RIRUBASE(&pThis->hda));
2192 pThis->hda.u64DPBase = RT_MAKE_U64(DPLBASE(&pThis->hda), DPUBASE(&pThis->hda));
2193 return VINF_SUCCESS;
2194}
2195
2196/**
2197 * Reset notification.
2198 *
2199 * @returns VBox status.
2200 * @param pDevIns The device instance data.
2201 *
2202 * @remark The original sources didn't install a reset handler, but it seems to
2203 * make sense to me so we'll do it.
2204 */
2205static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
2206{
2207 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2208 GCAP(&pThis->hda) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
2209 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
2210 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2211 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2212 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
2213 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
2214 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
2215 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
2216 CORBRP(&pThis->hda) = 0x0;
2217 RIRBWP(&pThis->hda) = 0x0;
2218
2219 Log(("hda: inter HDA reset.\n"));
2220 pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
2221
2222 if (pThis->hda.pu32CorbBuf)
2223 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
2224 else
2225 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
2226
2227 pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
2228 if (pThis->hda.pu64RirbBuf)
2229 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
2230 else
2231 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
2232
2233 pThis->hda.u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2234
2235 HDABDLEDESC stEmptyBdle;
2236 for(uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2237 {
2238 HDASTREAMTRANSFERDESC stStreamDesc;
2239 PHDABDLEDESC pBdle = NULL;
2240 if (u8Strm == 0)
2241 pBdle = &pThis->hda.stInBdle;
2242 else if(u8Strm == 4)
2243 pBdle = &pThis->hda.stOutBdle;
2244 else
2245 {
2246 memset(&stEmptyBdle, 0, sizeof(HDABDLEDESC));
2247 pBdle = &stEmptyBdle;
2248 }
2249 hdaInitTransferDescriptor(&pThis->hda, pBdle, u8Strm, &stStreamDesc);
2250 /* hdaStreamReset prevents changing SRST bit, so we zerro it here forcely. */
2251 HDA_STREAM_REG2(&pThis->hda, CTL, u8Strm) = 0;
2252 hdaStreamReset(&pThis->hda, pBdle, &stStreamDesc, u8Strm);
2253 }
2254
2255 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
2256 STATESTS(&pThis->hda) = 0x1;
2257
2258 Log(("hda: reset finished\n"));
2259}
2260
2261/**
2262 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2263 */
2264static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
2265 const char *pszIID)
2266{
2267 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
2268 Assert(&pThis->hda.IBase == pInterface);
2269
2270 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
2271 return NULL;
2272}
2273
2274static inline int hdaLookUpRegisterByName(INTELHDLinkState *pState, const char *pszArgs)
2275{
2276 int iReg = 0;
2277 for (; iReg < HDA_NREGS; ++iReg)
2278 if (!RTStrICmp(s_ichIntelHDRegMap[iReg].abbrev, pszArgs))
2279 return iReg;
2280 return -1;
2281}
2282static inline void hdaDbgPrintRegister(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaIndex)
2283{
2284 Assert( pState
2285 && iHdaIndex >= 0
2286 && iHdaIndex < HDA_NREGS);
2287 pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", s_ichIntelHDRegMap[iHdaIndex].abbrev, pState->au32Regs[iHdaIndex]);
2288}
2289static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2290{
2291 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2292 INTELHDLinkState *hda = &pThis->hda;
2293 int iHdaRegisterIndex = hdaLookUpRegisterByName(hda, pszArgs);
2294 if (iHdaRegisterIndex != -1)
2295 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2296 else
2297 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
2298 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2299}
2300
2301static inline void hdaDbgPrintStream(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
2302{
2303 Assert( pState
2304 && iHdaStrmIndex >= 0
2305 && iHdaStrmIndex < 7);
2306 pHlp->pfnPrintf(pHlp, "Dump of %d Hda Stream:\n", iHdaStrmIndex);
2307 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, CTL, iHdaStrmIndex));
2308 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, STS, iHdaStrmIndex));
2309 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOS, iHdaStrmIndex));
2310 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOW, iHdaStrmIndex));
2311}
2312
2313static inline int hdaLookUpStreamIndex(INTELHDLinkState *pState, const char *pszArgs)
2314{
2315 /* todo: add args parsing */
2316 return -1;
2317}
2318static DECLCALLBACK(void) hdaDbgStreamInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2319{
2320 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2321 INTELHDLinkState *hda = &pThis->hda;
2322 int iHdaStrmIndex = hdaLookUpStreamIndex(hda, pszArgs);
2323 if (iHdaStrmIndex != -1)
2324 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2325 else
2326 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
2327 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2328}
2329
2330/* Codec debugger interface */
2331static DECLCALLBACK(void) hdaCodecDbgNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2332{
2333 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2334 INTELHDLinkState *hda = &pThis->hda;
2335 if (hda->Codec.pfnCodecDbgListNodes)
2336 hda->Codec.pfnCodecDbgListNodes(&hda->Codec, pHlp, pszArgs);
2337 else
2338 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2339}
2340
2341static DECLCALLBACK(void) hdaCodecDbgSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2342{
2343 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2344 INTELHDLinkState *hda = &pThis->hda;
2345 if (hda->Codec.pfnCodecDbgSelector)
2346 hda->Codec.pfnCodecDbgSelector(&hda->Codec, pHlp, pszArgs);
2347 else
2348 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2349}
2350
2351//#define HDA_AS_PCI_EXPRESS
2352/* Misc routines */
2353static inline bool printHdaIsValid(const char *pszType, const char *pszExpectedFlag)
2354{
2355 return (RTStrCmp(pszType, pszExpectedFlag) == 0);
2356}
2357static const char *printHdaYesNo(bool fFlag)
2358{
2359 return fFlag ? "yes" : "no";
2360}
2361static DECLCALLBACK(size_t)
2362printHdaStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2363 const char *pszType, void const *pvValue,
2364 int cchWidth, int cchPrecision, unsigned fFlags,
2365 void *pvUser)
2366{
2367 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
2368 size_t cb = 0;
2369 if (!printHdaIsValid(pszType, "sdctl"))
2370 return cb;
2371 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2372 "SDCTL(raw: %#0x, strm:0x%x, dir:%s, tp:%s strip:%x, deie:%s, ioce:%s, run:%s, srst:%s)",
2373 sdCtl,
2374 ((sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> ICH6_HDA_SDCTL_NUM_SHIFT),
2375 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR))),
2376 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP))),
2377 ((sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> ICH6_HDA_SDCTL_STRIPE_SHIFT),
2378 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE))),
2379 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))),
2380 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))),
2381 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST))));
2382 return cb;
2383}
2384
2385static DECLCALLBACK(size_t)
2386printHdaStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2387 const char *pszType, void const *pvValue,
2388 int cchWidth, int cchPrecision, unsigned fFlags,
2389 void *pvUser)
2390{
2391 uint32_t sdFifos = (uint32_t)(uintptr_t)pvValue;
2392 uint32_t u32Bytes = 0;
2393 size_t cb = 0;
2394 if (!printHdaIsValid(pszType, "sdfifos"))
2395 return cb;
2396 switch(sdFifos)
2397 {
2398 case HDA_SDONFIFO_16B: u32Bytes = 16; break;
2399 case HDA_SDONFIFO_32B: u32Bytes = 32; break;
2400 case HDA_SDONFIFO_64B: u32Bytes = 64; break;
2401 case HDA_SDONFIFO_128B: u32Bytes = 128; break;
2402 case HDA_SDONFIFO_192B: u32Bytes = 192; break;
2403 case HDA_SDONFIFO_256B: u32Bytes = 256; break;
2404 case HDA_SDINFIFO_120B: u32Bytes = 120; break;
2405 case HDA_SDINFIFO_160B: u32Bytes = 160; break;
2406 default:;
2407 }
2408 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2409 "SDFIFOS(raw: %#0x, sdfifos:%d B)",
2410 sdFifos,
2411 u32Bytes);
2412 return cb;
2413}
2414
2415static DECLCALLBACK(size_t)
2416printHdaStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2417 const char *pszType, void const *pvValue,
2418 int cchWidth, int cchPrecision, unsigned fFlags,
2419 void *pvUser)
2420{
2421 uint32_t sdFifow = (uint32_t)(uintptr_t)pvValue;
2422 uint32_t u32Bytes = 0;
2423 size_t cb = 0;
2424 if (!printHdaIsValid(pszType, "sdfifow"))
2425 return cb;
2426 switch(sdFifow)
2427 {
2428 case HDA_SDFIFOW_8B: u32Bytes = 8; break;
2429 case HDA_SDFIFOW_16B: u32Bytes = 16; break;
2430 case HDA_SDFIFOW_32B: u32Bytes = 32; break;
2431 }
2432 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2433 "SDFIFOW(raw: %#0x, sdfifow:%d B)",
2434 sdFifow,
2435 u32Bytes);
2436 return cb;
2437}
2438
2439static DECLCALLBACK(size_t)
2440printHdaStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2441 const char *pszType, void const *pvValue,
2442 int cchWidth, int cchPrecision, unsigned fFlags,
2443 void *pvUser)
2444{
2445 uint32_t sdSts = (uint32_t)(uintptr_t)pvValue;
2446 size_t cb = 0;
2447 if (!printHdaIsValid(pszType, "sdsts"))
2448 return cb;
2449 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2450 "SDSTS(raw: %#0x, fifordy:%s, dese:%s, fifoe:%s, bcis:%s)",
2451 sdSts,
2452 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY))),
2453 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE))),
2454 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE))),
2455 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))));
2456 return cb;
2457}
2458/**
2459 * This routine registers debugger info extensions and custom printf formatters
2460 */
2461static inline int hdaInitMisc(PPDMDEVINS pDevIns)
2462{
2463 int rc;
2464 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
2465 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgStreamInfo);
2466 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaCodecDbgNodes);
2467 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaCodecDbgSelector);
2468 rc = RTStrFormatTypeRegister("sdctl", printHdaStrmCtl, NULL);
2469 AssertRC(rc);
2470 rc = RTStrFormatTypeRegister("sdsts", printHdaStrmSts, NULL);
2471 AssertRC(rc);
2472 rc = RTStrFormatTypeRegister("sdfifos", printHdaStrmFifos, NULL);
2473 AssertRC(rc);
2474 rc = RTStrFormatTypeRegister("sdfifow", printHdaStrmFifow, NULL);
2475 AssertRC(rc);
2476#if 0
2477 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
2478 AssertRC(rc);
2479#endif
2480 return rc;
2481}
2482
2483/**
2484 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2485 */
2486static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
2487 PCFGMNODE pCfgHandle)
2488{
2489 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2490 INTELHDLinkState *s = &pThis->hda;
2491 int rc;
2492
2493 Assert(iInstance == 0);
2494 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2495
2496 /*
2497 * Validations.
2498 */
2499 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
2500 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2501 N_ ("Invalid configuration for the INTELHD device"));
2502
2503 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
2504 // poll some register(s).
2505
2506 /*
2507 * Initialize data (most of it anyway).
2508 */
2509 s->pDevIns = pDevIns;
2510 /* IBase */
2511 s->IBase.pfnQueryInterface = hdaQueryInterface;
2512
2513 /* PCI Device (the assertions will be removed later) */
2514 PCIDevSetVendorId (&pThis->dev, HDA_PCI_VENDOR_ID); /* nVidia */
2515 PCIDevSetDeviceId (&pThis->dev, HDA_PCI_DEICE_ID); /* HDA */
2516
2517 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
2518 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2519 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
2520 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
2521 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
2522 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2523 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
2524 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
2525 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2526 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
2527 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */
2528
2529#if defined(HDA_AS_PCI_EXPRESS)
2530 PCIDevSetCapabilityList (&pThis->dev, 0x80);
2531#elif defined(VBOX_WITH_MSI_DEVICES)
2532 PCIDevSetCapabilityList (&pThis->dev, 0x60);
2533#else
2534 PCIDevSetCapabilityList (&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
2535#endif
2536
2537 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2538 // of these values needs to be properly documented!
2539 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2540 PCIDevSetByte(&pThis->dev, 0x40, 0x01);
2541
2542 /* Power Management */
2543 PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2544 PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
2545 PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2546
2547#ifdef HDA_AS_PCI_EXPRESS
2548 /* PCI Express */
2549 PCIDevSetByte (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2550 PCIDevSetByte (&pThis->dev, 0x80 + 1, 0x60); /* next */
2551 /* Device flags */
2552 PCIDevSetWord (&pThis->dev, 0x80 + 2,
2553 /* version */ 0x1 |
2554 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2555 /* MSI */ (100) << 9
2556 );
2557 /* Device capabilities */
2558 PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2559 /* Device control */
2560 PCIDevSetWord (&pThis->dev, 0x80 + 8, 0);
2561 /* Device status */
2562 PCIDevSetWord (&pThis->dev, 0x80 + 10, 0);
2563 /* Link caps */
2564 PCIDevSetDWord (&pThis->dev, 0x80 + 12, 0);
2565 /* Link control */
2566 PCIDevSetWord (&pThis->dev, 0x80 + 16, 0);
2567 /* Link status */
2568 PCIDevSetWord (&pThis->dev, 0x80 + 18, 0);
2569 /* Slot capabilities */
2570 PCIDevSetDWord (&pThis->dev, 0x80 + 20, 0);
2571 /* Slot control */
2572 PCIDevSetWord (&pThis->dev, 0x80 + 24, 0);
2573 /* Slot status */
2574 PCIDevSetWord (&pThis->dev, 0x80 + 26, 0);
2575 /* Root control */
2576 PCIDevSetWord (&pThis->dev, 0x80 + 28, 0);
2577 /* Root capabilities */
2578 PCIDevSetWord (&pThis->dev, 0x80 + 30, 0);
2579 /* Root status */
2580 PCIDevSetDWord (&pThis->dev, 0x80 + 32, 0);
2581 /* Device capabilities 2 */
2582 PCIDevSetDWord (&pThis->dev, 0x80 + 36, 0);
2583 /* Device control 2 */
2584 PCIDevSetQWord (&pThis->dev, 0x80 + 40, 0);
2585 /* Link control 2 */
2586 PCIDevSetQWord (&pThis->dev, 0x80 + 48, 0);
2587 /* Slot control 2 */
2588 PCIDevSetWord (&pThis->dev, 0x80 + 56, 0);
2589#endif
2590
2591 /*
2592 * Register the PCI device.
2593 */
2594 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
2595 if (RT_FAILURE (rc))
2596 return rc;
2597
2598 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
2599 hdaMap);
2600 if (RT_FAILURE (rc))
2601 return rc;
2602
2603#ifdef VBOX_WITH_MSI_DEVICES
2604 PDMMSIREG aMsiReg;
2605
2606 RT_ZERO(aMsiReg);
2607 aMsiReg.cMsiVectors = 1;
2608 aMsiReg.iMsiCapOffset = 0x60;
2609 aMsiReg.iMsiNextOffset = 0x50;
2610 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
2611 if (RT_FAILURE (rc))
2612 {
2613 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2614 PCIDevSetCapabilityList (&pThis->dev, 0x50);
2615 }
2616#endif
2617
2618 rc = PDMDevHlpSSMRegister (pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2619 if (RT_FAILURE (rc))
2620 return rc;
2621
2622 /*
2623 * Attach driver.
2624 */
2625 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
2626 &s->pDrvBase, "Audio Driver Port");
2627 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2628 Log (("hda: No attached driver!\n"));
2629 else if (RT_FAILURE (rc))
2630 {
2631 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
2632 return rc;
2633 }
2634
2635
2636
2637 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
2638 rc = codecConstruct(pDevIns, &pThis->hda.Codec, pCfgHandle);
2639 if (RT_FAILURE(rc))
2640 AssertRCReturn(rc, rc);
2641
2642 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2643 verb F20 should provide device/codec recognition. */
2644 Assert(pThis->hda.Codec.u16VendorId);
2645 Assert(pThis->hda.Codec.u16DeviceId);
2646 PCIDevSetSubSystemVendorId (&pThis->dev, pThis->hda.Codec.u16VendorId); /* 2c ro - intel.) */
2647 PCIDevSetSubSystemId (&pThis->dev, pThis->hda.Codec.u16DeviceId); /* 2e ro. */
2648
2649 hdaReset (pDevIns);
2650 pThis->hda.Codec.id = 0;
2651 pThis->hda.Codec.pfnTransfer = hdaTransfer;
2652 pThis->hda.Codec.pfnReset = hdaCodecReset;
2653 /*
2654 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2655 * hdaReset shouldn't affects these registers.
2656 */
2657 WAKEEN(&pThis->hda) = 0x0;
2658 STATESTS(&pThis->hda) = 0x0;
2659 hdaInitMisc(pDevIns);
2660
2661 return VINF_SUCCESS;
2662}
2663
2664/**
2665 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2666 */
2667static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
2668{
2669 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2670
2671 int rc = codecDestruct(&pThis->hda.Codec);
2672 AssertRC(rc);
2673 if (pThis->hda.pu32CorbBuf)
2674 RTMemFree(pThis->hda.pu32CorbBuf);
2675 if (pThis->hda.pu64RirbBuf)
2676 RTMemFree(pThis->hda.pu64RirbBuf);
2677 return VINF_SUCCESS;
2678}
2679
2680/**
2681 * The device registration structure.
2682 */
2683const PDMDEVREG g_DeviceICH6_HDA =
2684{
2685 /* u32Version */
2686 PDM_DEVREG_VERSION,
2687 /* szName */
2688 "hda",
2689 /* szRCMod */
2690 "",
2691 /* szR0Mod */
2692 "",
2693 /* pszDescription */
2694 "ICH IntelHD Audio Controller",
2695 /* fFlags */
2696 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2697 /* fClass */
2698 PDM_DEVREG_CLASS_AUDIO,
2699 /* cMaxInstances */
2700 1,
2701 /* cbInstance */
2702 sizeof(PCIINTELHDLinkState),
2703 /* pfnConstruct */
2704 hdaConstruct,
2705 /* pfnDestruct */
2706 hdaDestruct,
2707 /* pfnRelocate */
2708 NULL,
2709 /* pfnIOCtl */
2710 NULL,
2711 /* pfnPowerOn */
2712 NULL,
2713 /* pfnReset */
2714 hdaReset,
2715 /* pfnSuspend */
2716 NULL,
2717 /* pfnResume */
2718 NULL,
2719 /* pfnAttach */
2720 NULL,
2721 /* pfnDetach */
2722 NULL,
2723 /* pfnQueryInterface. */
2724 NULL,
2725 /* pfnInitComplete */
2726 NULL,
2727 /* pfnPowerOff */
2728 NULL,
2729 /* pfnSoftReset */
2730 NULL,
2731 /* u32VersionEnd */
2732 PDM_DEVREG_VERSION
2733};
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