VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 31085

Last change on this file since 31085 was 31085, checked in by vboxsync, 15 years ago

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1/* $Id: DevIchIntelHDA.cpp 31085 2010-07-25 04:10:21Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/pdmdev.h>
23#include <iprt/assert.h>
24#include <iprt/uuid.h>
25#include <iprt/string.h>
26#include <iprt/mem.h>
27#include <iprt/asm.h>
28
29#include "../Builtins.h"
30
31extern "C" {
32#include "audio.h"
33}
34#include "DevCodec.h"
35
36#undef LOG_VOICES
37#ifndef VBOX
38//#define USE_MIXER
39#else
40#define USE_MIXER
41#endif
42
43#define INTELHD_SSM_VERSION 1
44PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
45PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
46static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
47
48/* Registers */
49#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
50#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
51#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
52#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
53#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
54#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
55#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
56#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
57#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
58#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
59
60#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
61#define GCAP(pState) (HDA_REG((pState), GCAP))
62
63#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
64#define VMIN(pState) (HDA_REG((pState), VMIN))
65
66#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
67#define VMAJ(pState) (HDA_REG((pState), VMAJ))
68
69#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
70#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
71
72#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
73#define INPAY(pState) (HDA_REG((pState), INPAY))
74
75#define ICH6_HDA_REG_GCTL (5)
76#define ICH6_HDA_GCTL_RST_SHIFT (0)
77#define ICH6_HDA_GCTL_FSH_SHIFT (1)
78#define GCTL(pState) (HDA_REG((pState), GCTL))
79
80#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
81#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
82
83#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
84#define STATESTS(pState) (HDA_REG((pState), STATESTS))
85#define ICH6_HDA_STATES_SCSF 0x7
86
87#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
88#define ICH6_HDA_GSTS_FSH_SHIFT (1)
89#define GSTS(pState) (HDA_REG(pState, GSTS))
90
91#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
92#define ICH6_HDA_INTCTL_GIE_SHIFT 31
93#define ICH6_HDA_INTCTL_CIE_SHIFT 30
94#define ICH6_HDA_INTCTL_S0_SHIFT (0)
95#define ICH6_HDA_INTCTL_S1_SHIFT (1)
96#define ICH6_HDA_INTCTL_S2_SHIFT (2)
97#define ICH6_HDA_INTCTL_S3_SHIFT (3)
98#define ICH6_HDA_INTCTL_S4_SHIFT (4)
99#define ICH6_HDA_INTCTL_S5_SHIFT (5)
100#define ICH6_HDA_INTCTL_S6_SHIFT (6)
101#define ICH6_HDA_INTCTL_S7_SHIFT (7)
102#define INTCTL(pState) (HDA_REG((pState), INTCTL))
103#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
104#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
105#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
106#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
107
108/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
109 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
110 * the datasheet.
111 */
112#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
113#define SSYNC(pState) (HDA_REG((pState), SSYNC))
114
115#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
116#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
117#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
118#define ICH6_HDA_INTSTS_S0_SHIFT (0)
119#define ICH6_HDA_INTSTS_S1_SHIFT (1)
120#define ICH6_HDA_INTSTS_S2_SHIFT (2)
121#define ICH6_HDA_INTSTS_S3_SHIFT (3)
122#define ICH6_HDA_INTSTS_S4_SHIFT (4)
123#define ICH6_HDA_INTSTS_S5_SHIFT (5)
124#define ICH6_HDA_INTSTS_S6_SHIFT (6)
125#define ICH6_HDA_INTSTS_S7_SHIFT (7)
126#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
127#define INTSTS(pState) (HDA_REG((pState), INTSTS))
128#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
129#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
130#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
131#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
132
133#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
134#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
135#define ICH6_HDA_REG_CORBWP 15 /* 48 */
136#define ICH6_HDA_REG_CORBRP 16 /* 4A */
137#define ICH6_HDA_CORBRP_RST_SHIFT 15
138#define ICH6_HDA_CORBRP_WP_SHIFT 0
139#define ICH6_HDA_CORBRP_WP_MASK 0xFF
140
141#define CORBRP(pState) (HDA_REG(pState, CORBRP))
142#define CORBWP(pState) (HDA_REG(pState, CORBWP))
143
144#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
145#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
146#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
147
148#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
149
150
151#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
152#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
153#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
154
155#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
156#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
157#define ICH6_HDA_CORBSIZE_SZ 0x3
158#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
159#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
160/* till ich 10 sizes of CORB and RIRB are harcoded to 256 in real hw */
161#define CORBSIZE(pState) (255)
162
163#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
164#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
165
166#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
167#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
168#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
169#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
170
171#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
172#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
173#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
174
175#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
176#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
177#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
178#define ICH6_HDA_ROI_DMA_SHIFT (2)
179#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
180#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
181#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
182#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
183
184#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
185#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
186#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
187#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
188#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
189#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
190
191#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
192#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
193#define ICH6_HDA_RIRBSIZE_SZ 0x3
194
195#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
196#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
197#define RIRBSIZE(pState) (255)
198
199
200#define ICH6_HDA_REG_IC 27 /* 0x60 */
201#define IC(pState) (HDA_REG(pState, IC))
202#define ICH6_HDA_REG_IR 28 /* 0x64 */
203#define IR(pState) (HDA_REG(pState, IR))
204#define ICH6_HDA_REG_IRS 29 /* 0x68 */
205#define ICH6_HDA_IRS_ICB_SHIFT (0)
206#define ICH6_HDA_IRS_IRV_SHIFT (1)
207#define IRS(pState) (HDA_REG(pState, IRS))
208#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
209#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
210
211#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
212#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
213#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
214#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
215
216#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
217#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
218
219#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
220#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
221#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
222#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
223#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
224#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
225#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
226#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
227
228#define SD(func, num) SD##num##func
229#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
230#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
231#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
232#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
233#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
234#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
235#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
236#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
237#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
238
239#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
240#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
241#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
242#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
243#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
244#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
245#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
246#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
247
248#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
249#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
250#define ICH6_HDA_SDSTS_DE_SHIFT (4)
251#define ICH6_HDA_SDSTS_FE_SHIFT (3)
252#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
253
254#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
255#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
256#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
257#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
258#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
259#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
260#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
261#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
262
263#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
264
265#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
266#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
267#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
268#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
269#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
270#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
271#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
272#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
273
274#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
275
276#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
277#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
278#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
279#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
280#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
281#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
282#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
283#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
284
285#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
286
287#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
288#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
289#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
290#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
291#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
292#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
293#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
294#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
295
296#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
297#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
298#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
299#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
300#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
301#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
302#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
303#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
304
305#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
306
307#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
308#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
309#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
310#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
311#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
312#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
313#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
314#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
315
316#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
317#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
318#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
319#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
320#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
321#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
322#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
323#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
324
325#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
326
327#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
328#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
329#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
330#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
331#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
332#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
333#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
334#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
335
336#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
337
338/* Predicates */
339
340
341typedef struct INTELHDLinkState
342{
343 /** Pointer to the device instance. */
344 PPDMDEVINSR3 pDevIns;
345 /** Pointer to the connector of the attached audio driver. */
346 PPDMIAUDIOCONNECTOR pDrv;
347 /** Pointer to the attached audio driver. */
348 PPDMIBASE pDrvBase;
349 /** The base interface for LUN\#0. */
350 PDMIBASE IBase;
351 RTGCPHYS addrMMReg;
352 uint32_t au32Regs[113];
353 /* Current BD index */
354 uint32_t u32Cvi;
355 uint64_t u64CviAddr;
356 /* Length of current BD entry */
357 uint32_t u32CviLen;
358 uint32_t u32CviPos;
359 uint32_t u32Cbp;
360 /* Interrupt on completition */
361 bool fCviIoc;
362 uint64_t u64CORBBase;
363 uint64_t u64RIRBBase;
364 uint64_t u64DPBase;
365 uint8_t u8CORBRP;
366 /* pointer on CORB buf */
367 uint32_t *pu32CorbBuf;
368 /* size in bytes of CORB buf */
369 uint32_t cbCorbBuf;
370 /* size in double words of CORB buf */
371 uint8_t cdwCorbBuf;
372 /* pointer on RIRB buf */
373 uint64_t *pu64RirbBuf;
374 /* size in bytes of RIRB buf */
375 uint32_t cbRirbBuf;
376 /* size in quad words of RIRB buf */
377 uint8_t cdqRirbBuf;
378 /* indicates if HDA in reset. */
379 bool fInReset;
380 CODECState Codec;
381} INTELHDLinkState;
382
383#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
384#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
385
386
387
388
389typedef struct PCIINTELHDLinkState
390{
391 PCIDevice dev;
392 INTELHDLinkState hda;
393} PCIINTELHDLinkState;
394
395DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
396DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
397DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
398DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
399DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
400DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
401DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
402DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
403DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
404DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
405DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
406DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
407DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
408DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
409DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
410DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
411DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
412DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
413
414DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
415DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
416DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
417DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
418DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
419DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
420DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
421DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
422DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
423DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
424DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
425DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
426DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
427static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
428
429/* see 302349 p 6.2*/
430const static struct stIchIntelHDRegMap
431{
432 /** Register offset in the register space. */
433 uint32_t offset;
434 /** Size in bytes. Registers of size > 4 are in fact tables. */
435 uint32_t size;
436 /** Readable bits. */
437 uint32_t readable;
438 /** Writable bits. */
439 uint32_t writable;
440 /** Read callback. */
441 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
442 /** Write callback. */
443 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
444 /** Abbreviated name. */
445 const char *abbrev;
446 /** Full name. */
447 const char *name;
448} s_ichIntelHDRegMap[] =
449{
450 /* offset size read mask write mask read callback write callback abbrev full name */
451 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
452 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
453 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
454 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
455 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
456 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
457 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
458 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
459 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
460 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
461 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
462 { 0x00024, 0x00004, 0xC00000FF, 0x400000FF, hdaRegReadINTSTS , hdaRegWriteINTSTS , "INTSTS" , "Interrupt Status" },
463 //** @todo r=michaln: Are guests really not reading the WALCLK register at all?
464 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
465 //** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
466 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
467 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
468 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
469 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
470 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
471 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
472 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
473 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
474 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
475 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
476 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
477 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
478 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
479 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
480 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
481 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
482 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
483 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadU16 , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
484 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
485 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
486
487 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
488 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
489 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
490 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
491 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
492 { 0x0008E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOW", "ISD0 FIFO Watermark" },
493 { 0x00090, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
494 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FMT" , "ISD0 Format" },
495 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
496 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
497
498 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
499 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
500 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
501 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
502 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
503 { 0x000AE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOW", "ISD1 FIFO Watermark" },
504 { 0x000B0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
505 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FMT" , "ISD1 Format" },
506 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
507 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
508
509 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
510 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
511 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
512 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
513 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
514 { 0x000CE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOW", "ISD2 FIFO Watermark" },
515 { 0x000D0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
516 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FMT" , "ISD2 Format" },
517 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
518 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
519
520 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
521 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
522 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
523 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
524 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
525 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
526 { 0x000F0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
527 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FMT" , "ISD3 Format" },
528 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
529 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
530
531 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
532 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
533 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
534 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
535 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
536 { 0x0010E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOW", "OSD0 FIFO Watermark" },
537 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOS", "OSD0 FIFO Size" },
538 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FMT" , "OSD0 Format" },
539 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
540 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
541
542 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
543 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
544 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
545 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
546 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
547 { 0x0012E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOW", "OSD1 FIFO Watermark" },
548 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOS", "OSD1 FIFO Size" },
549 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FMT" , "OSD1 Format" },
550 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
551 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
552
553 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
554 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
555 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
556 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
557 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
558 { 0x0014E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOW", "OSD2 FIFO Watermark" },
559 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOS", "OSD2 FIFO Size" },
560 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FMT" , "OSD2 Format" },
561 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
562 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
563
564 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
565 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
566 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
567 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
568 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
569 { 0x0016E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOW", "OSD3 FIFO Watermark" },
570 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOS", "OSD3 FIFO Size" },
571 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FMT" , "OSD3 Format" },
572 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
573 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
574};
575
576static int hdaProcessInterrupt(INTELHDLinkState* pState)
577{
578 bool fIrq = false;
579 /* @todo add state change */
580 if( INTCTL_CIE(pState)
581 && ( RIRBSTS_RINTFL(pState)
582 || RIRBSTS_RIRBOIS(pState)))
583 {
584 INTSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(INTSTS, CIS);
585 fIrq = true;
586 }
587 if ( INTCTL_SX(pState, 4)
588 && SDSTS(pState, 4) && HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))
589 {
590 INTSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(INTSTS, S4);
591 fIrq = true;
592 }
593 if (INTCTL_GIE(pState))
594 {
595 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
596 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
597 }
598 return VINF_SUCCESS;
599}
600
601static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
602{
603 int index = 0;
604 //** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
605 for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
606 {
607 if ( u32Offset >= s_ichIntelHDRegMap[index].offset
608 && u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
609 {
610 return index;
611 }
612 }
613 return -1;
614}
615
616static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
617{
618 int rc = VINF_SUCCESS;
619 if (fLocal)
620 {
621 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
622 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
623 if (RT_FAILURE(rc))
624 AssertRCReturn(rc, rc);
625 uint8_t i = 0;
626 do
627 {
628 Log(("hda: corb%02x: ", i));
629 uint8_t j = 0;
630 do
631 {
632 const char *prefix;
633 if ((i + j) == CORBRP(pState))
634 prefix = "[R]";
635 else if ((i + j) == CORBWP(pState))
636 prefix = "[W]";
637 else
638 prefix = " "; /* three spaces */
639 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
640 j++;
641 } while (j < 8);
642 Log(("\n"));
643 i += 8;
644 } while(i != 0);
645 }
646 else
647 {
648 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
649 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
650 if (RT_FAILURE(rc))
651 AssertRCReturn(rc, rc);
652 uint8_t i = 0;
653 do {
654 Log(("hda: rirb%02x: ", i));
655 uint8_t j = 0;
656 do {
657 const char *prefix;
658 if ((i + j) == RIRBWP(pState))
659 prefix = "[W]";
660 else
661 prefix = " ";
662 Log((" %s%016x", prefix, pState->pu64RirbBuf[i + j]));
663 } while (++j < 8);
664 Log(("\n"));
665 i += 8;
666 } while (i != 0);
667 }
668 return rc;
669}
670static int hdaCORBCmdProcess(INTELHDLinkState *pState)
671{
672 int rc;
673 uint8_t corbRp;
674 uint8_t corbWp;
675 uint8_t rirbWp;
676 uint8_t u8Counter = 0;
677
678 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
679
680 rc = hdaCmdSync(pState, true);
681 if (RT_FAILURE(rc))
682 AssertRCReturn(rc, rc);
683 corbRp = CORBRP(pState);
684 corbWp = CORBWP(pState);
685 rirbWp = RIRBWP(pState);
686 Assert((corbWp != corbRp));
687 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
688 while (corbRp != corbWp)
689 {
690 uint32_t cmd;
691 corbRp++;
692 cmd = pState->pu32CorbBuf[corbRp];
693 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
694 if (RT_FAILURE(rc))
695 AssertRCReturn(rc, rc);
696 Assert(pfn);
697 (rirbWp)++;
698 rc = pfn(&pState->Codec, cmd, &pState->pu64RirbBuf[rirbWp]);
699 if (RT_FAILURE(rc))
700 AssertRCReturn(rc, rc);
701 u8Counter++;
702 if (u8Counter == RINTCNT_N(pState))
703 break;
704 }
705 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
706 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
707 rc = hdaCmdSync(pState, false);
708 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
709 if (RIRBCTL_RIRB_RIC(pState))
710 {
711 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
712 rc = hdaProcessInterrupt(pState);
713 }
714 if (RT_FAILURE(rc))
715 AssertRCReturn(rc, rc);
716 return rc;
717}
718
719static void hdaStreamReset(INTELHDLinkState *pState, uint32_t u32Offset)
720{
721 Log(("hda: reset of stream (%x) started\n", u32Offset));
722 Log(("hda: reset of stream (%x) finished\n", u32Offset));
723}
724
725
726DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
727{
728 *pu32Value = 0;
729 return VINF_SUCCESS;
730}
731DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
732{
733 return VINF_SUCCESS;
734}
735/* U8 */
736DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
737{
738 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
739 return hdaRegReadU32(pState, offset, index, pu32Value);
740}
741
742DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
743{
744 Assert(((u32Value & 0xffffff00) == 0));
745 return hdaRegWriteU32(pState, offset, index, u32Value);
746}
747/* U16 */
748DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
749{
750 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
751 return hdaRegReadU32(pState, offset, index, pu32Value);
752}
753
754DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
755{
756 Assert(((u32Value & 0xffff0000) == 0));
757 return hdaRegWriteU32(pState, offset, index, u32Value);
758}
759
760/* U24 */
761DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
762{
763 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
764 return hdaRegReadU32(pState, offset, index, pu32Value);
765}
766
767DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
768{
769 Assert(((u32Value & 0xff000000) == 0));
770 return hdaRegWriteU32(pState, offset, index, u32Value);
771}
772/* U32 */
773DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
774{
775 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
776 return VINF_SUCCESS;
777}
778
779DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
780{
781 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
782 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
783 return VINF_SUCCESS;
784}
785
786DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
787{
788 return hdaRegReadU32(pState, offset, index, pu32Value);
789}
790
791DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
792{
793 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
794 {
795 /* exit reset state */
796 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
797 pState->fInReset = false;
798 }
799 else
800 {
801 /* enter reset state*/
802 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
803 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
804 {
805 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
806 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
807 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
808 }
809 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
810 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
811 pState->fInReset = true;
812 }
813 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
814 {
815 /* Flush: GSTS:1 set, see 6.2.6*/
816 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
817 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
818 }
819 return VINF_SUCCESS;
820}
821
822DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
823{
824 uint32_t v = pState->au32Regs[index];
825 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
826 pState->au32Regs[index] = (v ^ nv) & v; /* write of 1 clears corresponding bit */
827 return VINF_SUCCESS;
828}
829
830DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
831{
832 uint32_t v = INTSTS(pState);
833 v &= ~HDA_REG_FIELD_FLAG_MASK(INTSTS, GIS);
834 v |= (v ? HDA_REG_FIELD_FLAG_MASK(INTSTS, GIS) : 0);
835 *pu32Value = v;
836 return VINF_SUCCESS;
837}
838
839DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
840{
841 uint32_t v = INTSTS(pState);
842 INTSTS(pState) = (v ^ u32Value) & v;
843 return hdaProcessInterrupt(pState);
844}
845
846DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
847{
848 return hdaRegReadU16(pState, offset, index, pu32Value);
849}
850
851DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
852{
853 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
854 {
855 pState->u8CORBRP = 0;
856 CORBRP(pState) = 0;
857 }
858 else
859 return hdaRegWriteU8(pState, offset, index, u32Value);
860 return VINF_SUCCESS;
861}
862
863DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
864{
865 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
866 AssertRC(rc);
867 if ( CORBWP(pState) != CORBRP(pState)
868 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
869 return hdaCORBCmdProcess(pState);
870 return rc;
871}
872
873DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
874{
875 uint32_t v = CORBSTS(pState);
876 v = (v ^ u32Value) & v;
877 CORBSTS(pState) = v;
878 return VINF_SUCCESS;
879}
880
881DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
882{
883 int rc;
884 rc = hdaRegWriteU16(pState, offset, index, u32Value);
885 if (RT_FAILURE(rc))
886 AssertRCReturn(rc, rc);
887 if (CORBWP(pState) == CORBRP(pState))
888 return VINF_SUCCESS;
889 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
890 return VINF_SUCCESS;
891 rc = hdaCORBCmdProcess(pState);
892 return rc;
893}
894
895DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
896{
897 return hdaRegReadU24(pState, offset, index, pu32Value);
898}
899
900DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
901{
902 if((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)))
903 {
904 hdaStreamReset(pState, offset);
905 }
906 /* @todo: use right offsets for right streams */
907 if (u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
908 {
909 Log(("hda: DMA(%x) switched on\n", offset));
910 AUD_set_active_in(pState->Codec.voice_pi, 1);
911 AUD_set_active_in(pState->Codec.voice_mc, 1);
912 if (offset == 0x100)
913 {
914 AUD_set_active_out(pState->Codec.voice_po, 1);
915 //SDSTS(pState, 4) |= (1<<5);
916 }
917 }
918 else
919 {
920 Log(("hda: DMA(%x) switched off\n", offset));
921 AUD_set_active_in(pState->Codec.voice_pi, 0);
922 AUD_set_active_in(pState->Codec.voice_mc, 0);
923 if (offset == 0x100)
924 {
925 SDSTS(pState, 4) &= ~(1<<5);
926 AUD_set_active_out(pState->Codec.voice_po, 0);
927 }
928 SSYNC(pState) &= ~(1<< (offset - 0x80));
929 }
930 int rc = hdaRegWriteU24(pState, offset, index, u32Value);
931 if (RT_FAILURE(rc))
932 AssertRCReturn(rc, VINF_SUCCESS);
933 return rc;
934}
935
936DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
937{
938 uint32_t v = HDA_REG_IND(pState, index);
939 //int rc = hdaRegWriteU8(pState, offset, index, u32Value);
940 switch (offset)
941 {
942 case 0x83:
943 SDSTS(pState, 0) ^= u32Value;
944 break;
945 case 0xA3:
946 SDSTS(pState, 1) ^= u32Value;
947 break;
948 case 0xC3:
949 SDSTS(pState, 2) ^= u32Value;
950 break;
951 case 0xE3:
952 SDSTS(pState, 3) ^= u32Value;
953 break;
954 case 0x103:
955 SDSTS(pState, 4) ^= u32Value;
956 break;
957 case 0x123:
958 SDSTS(pState, 5) ^= u32Value;
959 break;
960 case 0x143:
961 SDSTS(pState, 6) ^= u32Value;
962 break;
963 case 0x163:
964 SDSTS(pState, 7) ^= u32Value;
965 break;
966 }
967 hdaProcessInterrupt(pState);
968#if 0
969 if ( v != u32Value
970 && (INTCTL_SALL(pState) & (1 << ((offset - 0x83) >> 5))))
971 {
972 int rc;
973 rc = hdaProcessInterrupt(pState);
974 if (RT_FAILURE(rc))
975 AssertRCReturn(rc, rc);
976 }
977#endif
978 return VINF_SUCCESS;
979}
980DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
981{
982 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
983 if (RT_FAILURE(rc))
984 AssertRCReturn(rc, VINF_SUCCESS);
985 return rc;
986}
987
988DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
989{
990 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
991 if (RT_FAILURE(rc))
992 AssertRCReturn(rc, VINF_SUCCESS);
993 return rc;
994}
995
996DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
997{
998 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
999 if (RT_FAILURE(rc))
1000 AssertRCReturn(rc, VINF_SUCCESS);
1001 return rc;
1002}
1003
1004DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1005{
1006 int rc = VINF_SUCCESS;
1007 uint64_t resp;
1008 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1009 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1010 && !IRS_ICB(pState))
1011 {
1012 uint32_t cmd = IC(pState);
1013 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1014 Log(("hda: IC:%x\n", cmd));
1015 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1016 if (RT_FAILURE(rc))
1017 AssertRCReturn(rc, rc);
1018 rc = pfn(&pState->Codec, cmd, &resp);
1019 if (RT_FAILURE(rc))
1020 AssertRCReturn(rc, rc);
1021 IR(pState) = (uint32_t)resp;
1022 Log(("hda: IR:%x\n", IR(pState)));
1023 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* clear busy, result is ready */
1024 return rc;
1025 }
1026 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1027 && IRS_IRV(pState))
1028 IRS(pState) ^= HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1029 return rc;
1030}
1031
1032DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1033{
1034 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1035 {
1036 RIRBWP(pState) = 0;
1037 }
1038 /*The rest of bits are O, see 6.2.22 */
1039 return VINF_SUCCESS;
1040}
1041
1042DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1043{
1044 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1045 if (RT_FAILURE(rc))
1046 AssertRCReturn(rc, rc);
1047 switch(index)
1048 {
1049 case ICH6_HDA_REG_CORBLBASE:
1050 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1051 pState->u64CORBBase |= pState->au32Regs[index];
1052 break;
1053 case ICH6_HDA_REG_CORBUBASE:
1054 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1055 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1056 break;
1057 case ICH6_HDA_REG_RIRLBASE:
1058 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1059 pState->u64RIRBBase |= pState->au32Regs[index];
1060 break;
1061 case ICH6_HDA_REG_RIRUBASE:
1062 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1063 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1064 break;
1065 case ICH6_HDA_REG_DPLBASE:
1066 /* @todo: first bit has special meaning */
1067 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1068 pState->u64DPBase |= pState->au32Regs[index];
1069 break;
1070 case ICH6_HDA_REG_DPUBASE:
1071 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1072 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1073 break;
1074 default:
1075 AssertMsgFailed(("Invalid index"));
1076 }
1077 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1078 return rc;
1079}
1080
1081DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1082{
1083 uint8_t nv = u32Value;
1084 uint8_t v = RIRBSTS(pState);
1085 RIRBSTS(pState) = (v ^ nv) & v;
1086
1087 return hdaProcessInterrupt(pState);
1088}
1089
1090static void dump_bd(INTELHDLinkState *pState)
1091{
1092 uint64_t addr;
1093 uint32_t len;
1094 uint32_t ioc;
1095 uint8_t bdle[16];
1096 uint32_t counter;
1097 uint32_t i;
1098 uint32_t sum = 0;
1099 for (i = 0; i <= SDLVI(pState, 4); ++i)
1100 {
1101 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), SDBDPL(pState, 4) + i*16, bdle, 16);
1102 addr = *(uint64_t *)bdle;
1103 len = *(uint32_t *)&bdle[8];
1104 ioc = *(uint32_t *)&bdle[12];
1105 Log(("hda: %s bdle[%d] a:%x, len:%x, ios:%d\n", (i == pState->u32Cvi? "[C]": " "), i, addr, len, ioc));
1106 sum += len;
1107 }
1108 Log(("hda: sum: %d\n", sum));
1109 for (i = 0; i < 8; ++i)
1110 {
1111 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64DPBase + i*8, &counter, 4);
1112 Log(("hda: %s stream[%d] counter=%x\n", (i) == SDCTL_NUM(pState, 4)? "[C]": " ", i , counter));
1113 }
1114}
1115static void fetch_bd(INTELHDLinkState *pState)
1116{
1117 dump_bd(pState);
1118 pState->u32Cvi;
1119 uint8_t bdle[16];
1120 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), SDBDPL(pState, 4) + pState->u32Cvi*16, bdle, 16);
1121 pState->u64CviAddr = *(uint64_t *)bdle;
1122 pState->u32CviLen = *(uint32_t *)&bdle[8];
1123 pState->fCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1124}
1125
1126static uint32_t write_audio(INTELHDLinkState *pState, int avail, bool *fStop)
1127{
1128 uint8_t tmpbuf[4096];
1129 uint32_t temp;
1130 uint32_t u32Rest;
1131 uint32_t written = 0;
1132 int to_copy = 0;
1133 u32Rest = pState->u32CviLen - pState->u32CviPos;
1134 temp = audio_MIN(u32Rest, (uint32_t)avail);
1135 if (!temp)
1136 {
1137 *fStop = true;
1138 return written;
1139 }
1140 while (temp)
1141 {
1142 int copied;
1143 to_copy = audio_MIN(temp, 4096U);
1144 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CviAddr + pState->u32CviPos, tmpbuf, to_copy);
1145 copied = AUD_write (pState->Codec.voice_po, tmpbuf, to_copy);
1146 Log (("hda: write_audio max=%x to_copy=%x copied=%x\n",
1147 avail, to_copy, copied));
1148 Assert((copied));
1149 if (!copied)
1150 {
1151 *fStop = true;
1152 break;
1153 }
1154 temp -= copied;
1155 written += copied;
1156 pState->u32CviPos += written;
1157 }
1158 return written;
1159}
1160
1161DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1162{
1163 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1164 STATESTS(pState) |= 1 << (pCodecState->id);
1165 INTSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(INTSTS, CIS);
1166 return VINF_SUCCESS;
1167}
1168DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1169{
1170 bool fStop = false;
1171 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1172 switch(src)
1173 {
1174 case PO_INDEX:
1175 {
1176 uint32_t written;
1177 uint32_t u32Counter;
1178 if ( !(SDCTL(pState, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1179 || avail == 0)
1180 return;
1181 SDCTL(pState, 4) |= ((pState->Codec.pNodes[2].adc.u32F06_param & (0x5 << 4)) >> 4) << 20;
1182 fetch_bd(pState);
1183 while( avail
1184 && !fStop)
1185 {
1186 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + 4*8, &u32Counter, 4);
1187 written = write_audio(pState, avail, &fStop);
1188 if (fStop)
1189 break;
1190 SDLPIB(pState, 4) += written; /* bytes ? */
1191 avail -= written;
1192 u32Counter += written;
1193 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + 4*8, &u32Counter, 4);
1194 if (pState->u32CviPos == pState->u32CviLen
1195 || SDLPIB(pState, 4) == SDLCBL(pState, 4))
1196 {
1197 if ( SDCTL(pState, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)
1198 && ( pState->u32CviPos == pState->u32CviLen
1199 || SDLPIB(pState, 4) == SDLCBL(pState, 4)))
1200 {
1201 SDSTS(pState,4) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1202 INTSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(INTSTS, S4);
1203 hdaProcessInterrupt(pState);
1204 if (SDLPIB(pState, 4) == SDLCBL(pState, 4))
1205 {
1206 SDLPIB(pState, 4) = 0;
1207 u32Counter = 0;
1208 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + 4*8, &u32Counter, 4);
1209 }
1210 if (pState->u32CviPos == pState->u32CviLen)
1211 {
1212 pState->u32CviPos = 0;
1213 pState->u32Cvi++;
1214 if (pState->u32Cvi == SDLVI(pState, 4) + 1)
1215 pState->u32Cvi = 0;
1216 }
1217 }
1218 }
1219 fetch_bd(pState);
1220 }
1221 }
1222 break;
1223 AssertMsgFailed(("Unexpected index: %x\n", src));
1224 default:
1225 break;
1226 }
1227}
1228
1229/**
1230 * Handle register read operation.
1231 *
1232 * Looks up and calls appropriate handler.
1233 *
1234 * @note: while implementation was detected so called "forgotten" or "hole" registers
1235 * which description is missed in RPM, datasheet or spec.
1236 *
1237 * @returns VBox status code.
1238 *
1239 * @param pState The device state structure.
1240 * @param uOffset Register offset in memory-mapped frame.
1241 * @param pv Where to fetch the value.
1242 * @param cb Number of bytes to write.
1243 * @thread EMT
1244 */
1245PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1246{
1247 int rc = VINF_SUCCESS;
1248 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1249 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1250 int index = hdaLookup(&pThis->hda, u32Offset);
1251 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1252 {
1253 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1254 }
1255 Assert( index != -1
1256 && u32Offset == s_ichIntelHDRegMap[index].offset
1257 && cb <= 4);
1258 if (index != -1)
1259 {
1260 uint32_t mask = 0;
1261 uint32_t v = 0;
1262 switch(cb)
1263 {
1264 case 1: mask = 0x000000ff; break;
1265 case 2: mask = 0x0000ffff; break;
1266 case 3: mask = 0x00ffffff; break;
1267 case 4: mask = 0xffffffff; break;
1268 }
1269 Assert(u32Offset == s_ichIntelHDRegMap[index].offset);
1270 rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1271 *(uint32_t *)pv = v & mask;
1272 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
1273 return rc;
1274 }
1275 *(uint32_t *)pv = 0xFF;
1276 Log(("hda: hole at %X is accessed for read\n", u32Offset));
1277 return rc;
1278}
1279
1280/**
1281 * Handle register write operation.
1282 *
1283 * Looks up and calls appropriate handler.
1284 *
1285 * @returns VBox status code.
1286 *
1287 * @param pState The device state structure.
1288 * @param uOffset Register offset in memory-mapped frame.
1289 * @param pv Where to fetch the value.
1290 * @param cb Number of bytes to write.
1291 * @thread EMT
1292 */
1293PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1294{
1295 int rc = VINF_SUCCESS;
1296 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1297 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1298 int index = hdaLookup(&pThis->hda, u32Offset);
1299 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1300 {
1301 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1302 }
1303 Assert( index != -1
1304 && u32Offset == s_ichIntelHDRegMap[index].offset
1305 && cb <= 4);
1306 if (index != -1)
1307 {
1308 Assert(u32Offset == s_ichIntelHDRegMap[index].offset);
1309 uint32_t v = pThis->hda.au32Regs[index];
1310 uint32_t mask = 0;
1311 switch(cb)
1312 {
1313 case 1: mask = 0xffffff00; break;
1314 case 2: mask = 0xffff0000; break;
1315 case 3: mask = 0xff000000; break;
1316 case 4: mask = 0x00000000; break;
1317 }
1318 *(uint32_t *)pv = (v & mask) | (*(uint32_t *)pv & ~mask);
1319 rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
1320 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
1321 return rc;
1322 }
1323 Log(("hda: hole at %X is accessed for write\n", u32Offset));
1324 return rc;
1325}
1326
1327/**
1328 * Callback function for mapping a PCI I/O region.
1329 *
1330 * @return VBox status code.
1331 * @param pPciDev Pointer to PCI device.
1332 * Use pPciDev->pDevIns to get the device instance.
1333 * @param iRegion The region number.
1334 * @param GCPhysAddress Physical address of the region.
1335 * If iType is PCI_ADDRESS_SPACE_IO, this is an
1336 * I/O port, else it's a physical address.
1337 * This address is *NOT* relative
1338 * to pci_mem_base like earlier!
1339 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
1340 */
1341static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
1342 RTGCPHYS GCPhysAddress, uint32_t cb,
1343 PCIADDRESSSPACE enmType)
1344{
1345 int rc;
1346 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1347 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1348 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1349
1350 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1351 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
1352 hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
1353
1354 if (RT_FAILURE(rc))
1355 return rc;
1356
1357 pThis->hda.addrMMReg = GCPhysAddress;
1358 return VINF_SUCCESS;
1359}
1360
1361
1362/**
1363 * Reset notification.
1364 *
1365 * @returns VBox status.
1366 * @param pDevIns The device instance data.
1367 *
1368 * @remark The original sources didn't install a reset handler, but it seems to
1369 * make sense to me so we'll do it.
1370 */
1371static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns)
1372{
1373 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1374 GCAP(&pThis->hda) = 0x4401; /* see 6.2.1 */
1375 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
1376 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1377 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1378 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
1379 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
1380 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
1381 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
1382 CORBRP(&pThis->hda) = 0x0;
1383 RIRBWP(&pThis->hda) = 0x0;
1384
1385 LogRel(("hda: inter HDA reset.\n"));
1386 //** @todo r=michaln: There should be LogRel statements when the guest initializes
1387 // or resets the HDA chip, and possibly also when opening the PCM streams.
1388 pThis->hda.cdwCorbBuf = CORBSIZE(&pThis->hda);
1389 pThis->hda.cbCorbBuf = CORBSIZE(&pThis->hda) * sizeof(uint32_t);
1390
1391 if (pThis->hda.pu32CorbBuf)
1392 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
1393 else
1394 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
1395
1396 pThis->hda.cdqRirbBuf = RIRBSIZE(&pThis->hda);
1397 pThis->hda.cbRirbBuf = RIRBSIZE(&pThis->hda) * sizeof(uint64_t);
1398 if (pThis->hda.pu64RirbBuf)
1399 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
1400 else
1401 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
1402
1403 /* Accoding to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
1404 * bits are reserved for stream number 18.2.33 */
1405 SDCTL(&pThis->hda, 0) = 0x40000;
1406 SDCTL(&pThis->hda, 1) = 0x40000;
1407 SDCTL(&pThis->hda, 2) = 0x40000;
1408 SDCTL(&pThis->hda, 3) = 0x40000;
1409 SDCTL(&pThis->hda, 4) = 0x40000;
1410 SDCTL(&pThis->hda, 5) = 0x40000;
1411 SDCTL(&pThis->hda, 6) = 0x40000;
1412 SDCTL(&pThis->hda, 7) = 0x40000;
1413
1414 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1415 SDFIFOS(&pThis->hda, 0) = 0x77;
1416 SDFIFOS(&pThis->hda, 1) = 0x77;
1417 SDFIFOS(&pThis->hda, 2) = 0x77;
1418 SDFIFOS(&pThis->hda, 3) = 0x77;
1419 SDFIFOS(&pThis->hda, 4) = 0xBF;
1420 SDFIFOS(&pThis->hda, 5) = 0xBF;
1421 SDFIFOS(&pThis->hda, 6) = 0xBF;
1422 SDFIFOS(&pThis->hda, 7) = 0xBF;
1423
1424 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
1425 STATESTS(&pThis->hda) = 0x1;
1426
1427 Log(("hda: reset finished\n"));
1428}
1429
1430/**
1431 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1432 */
1433static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
1434 const char *pszIID)
1435{
1436 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
1437 Assert(&pThis->hda.IBase == pInterface);
1438
1439 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
1440 return NULL;
1441}
1442
1443/**
1444 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1445 */
1446static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
1447 PCFGMNODE pCfgHandle)
1448{
1449 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1450 INTELHDLinkState *s = &pThis->hda;
1451 int rc;
1452
1453 Assert(iInstance == 0);
1454 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1455
1456 /*
1457 * Validations.
1458 */
1459 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
1460 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1461 N_ ("Invalid configuration for the INTELHD device"));
1462
1463 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
1464 // poll some register(s).
1465
1466 /*
1467 * Initialize data (most of it anyway).
1468 */
1469 s->pDevIns = pDevIns;
1470 /* IBase */
1471 s->IBase.pfnQueryInterface = hdaQueryInterface;
1472
1473 /* PCI Device (the assertions will be removed later) */
1474 PCIDevSetVendorId (&pThis->dev, 0x8086); /* 00 ro - intel. */
1475 PCIDevSetDeviceId (&pThis->dev, 0x2668); /* 02 ro - 82801 / 82801aa(?). */
1476 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
1477 PCIDevSetStatus (&pThis->dev, 0x0010); /* 06 rwc?,ro? - pcists. */
1478 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
1479 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
1480 PCIDevSetClassSub (&pThis->dev, 0x02); /* 0a ro - scc; 02 == HDA. */
1481 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
1482 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
1483 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
1484 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
1485 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
1486 verb F20 should provide device/codec recognition. */
1487 PCIDevSetSubSystemVendorId (&pThis->dev, 0x0000); /* 2c ro - intel.) */
1488 PCIDevSetSubSystemId (&pThis->dev, 0x0000); /* 2e ro. */
1489 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
1490 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */ Assert (pThis->dev.config[0x3d] == 0x01);
1491 PCIDevSetCapabilityList(&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
1492
1493 //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
1494 // of these values needs to be properly documented!
1495 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1496 pThis->dev.config[0x40] = 0x01;
1497
1498 pThis->dev.config[0x50] = 0x01;
1499 pThis->dev.config[0x51] = 0x60; /* next */
1500 pThis->dev.config[0x52] = 0x22;
1501 pThis->dev.config[0x53] = 0x00; /* PM - disabled, */
1502
1503 pThis->dev.config[0x60] = 0x05;
1504 pThis->dev.config[0x61] = 0x70; /* next */
1505 pThis->dev.config[0x62] = 0x00;
1506 pThis->dev.config[0x63] = 0x80;
1507
1508 /*
1509 * Register the PCI device.
1510 */
1511 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
1512 if (RT_FAILURE (rc))
1513 return rc;
1514
1515 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
1516 hdaMap);
1517 if (RT_FAILURE (rc))
1518 return rc;
1519
1520 /*
1521 * Attach driver.
1522 */
1523 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
1524 &s->pDrvBase, "Audio Driver Port");
1525 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1526 Log (("hda: No attached driver!\n"));
1527 else if (RT_FAILURE (rc))
1528 {
1529 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
1530 return rc;
1531 }
1532
1533
1534
1535 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
1536 rc = stac9220Construct(&pThis->hda.Codec);
1537 if (RT_FAILURE(rc))
1538 AssertRCReturn(rc, rc);
1539 hdaReset (pDevIns);
1540 pThis->hda.Codec.id = 0;
1541 pThis->hda.Codec.pfnTransfer = hdaTransfer;
1542 pThis->hda.Codec.pfnReset = hdaCodecReset;
1543 /*
1544 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
1545 * hdaReset shouldn't affects these registers.
1546 */
1547 WAKEEN(&pThis->hda) = 0x0;
1548 STATESTS(&pThis->hda) = 0x0;
1549
1550 return VINF_SUCCESS;
1551}
1552
1553/**
1554 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1555 */
1556static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
1557{
1558 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1559
1560 int rc = stac9220Destruct(&pThis->hda.Codec);
1561 AssertRC(rc);
1562 if (pThis->hda.pu32CorbBuf)
1563 RTMemFree(pThis->hda.pu32CorbBuf);
1564 if (pThis->hda.pu64RirbBuf)
1565 RTMemFree(pThis->hda.pu64RirbBuf);
1566 return VINF_SUCCESS;
1567}
1568
1569/**
1570 * The device registration structure.
1571 */
1572const PDMDEVREG g_DeviceICH6_HDA =
1573{
1574 /* u32Version */
1575 PDM_DEVREG_VERSION,
1576 /* szName */
1577 "hda",
1578 /* szRCMod */
1579 "",
1580 /* szR0Mod */
1581 "",
1582 /* pszDescription */
1583 "ICH IntelHD Audio Controller",
1584 /* fFlags */
1585 PDM_DEVREG_FLAGS_DEFAULT_BITS,
1586 /* fClass */
1587 PDM_DEVREG_CLASS_AUDIO,
1588 /* cMaxInstances */
1589 1,
1590 /* cbInstance */
1591 sizeof(PCIINTELHDLinkState),
1592 /* pfnConstruct */
1593 hdaConstruct,
1594 /* pfnDestruct */
1595 hdaDestruct,
1596 /* pfnRelocate */
1597 NULL,
1598 /* pfnIOCtl */
1599 NULL,
1600 /* pfnPowerOn */
1601 NULL,
1602 /* pfnReset */
1603 hdaReset,
1604 /* pfnSuspend */
1605 NULL,
1606 /* pfnResume */
1607 NULL,
1608 /* pfnAttach */
1609 NULL,
1610 /* pfnDetach */
1611 NULL,
1612 /* pfnQueryInterface. */
1613 NULL,
1614 /* pfnInitComplete */
1615 NULL,
1616 /* pfnPowerOff */
1617 NULL,
1618 /* pfnSoftReset */
1619 NULL,
1620 /* u32VersionEnd */
1621 PDM_DEVREG_VERSION
1622};
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