VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 31215

Last change on this file since 31215 was 31172, checked in by vboxsync, 15 years ago

HDA: Fixed spelling.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 73.3 KB
Line 
1/* $Id: DevIchIntelHDA.cpp 31172 2010-07-28 16:02:38Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/pdmdev.h>
23#include <iprt/assert.h>
24#include <iprt/uuid.h>
25#include <iprt/string.h>
26#include <iprt/mem.h>
27#include <iprt/asm.h>
28
29#include "../Builtins.h"
30
31extern "C" {
32#include "audio.h"
33}
34#include "DevCodec.h"
35
36#undef LOG_VOICES
37#ifndef VBOX
38//#define USE_MIXER
39#else
40#define USE_MIXER
41#endif
42
43#define INTELHD_SSM_VERSION 1
44PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
45PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
46static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
47
48/* Registers */
49#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
50#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
51#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
52#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
53#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
54#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
55#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
56#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
57#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
58#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
59
60#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
61#define GCAP(pState) (HDA_REG((pState), GCAP))
62
63#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
64#define VMIN(pState) (HDA_REG((pState), VMIN))
65
66#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
67#define VMAJ(pState) (HDA_REG((pState), VMAJ))
68
69#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
70#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
71
72#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
73#define INPAY(pState) (HDA_REG((pState), INPAY))
74
75#define ICH6_HDA_REG_GCTL (5)
76#define ICH6_HDA_GCTL_RST_SHIFT (0)
77#define ICH6_HDA_GCTL_FSH_SHIFT (1)
78#define ICH6_HDA_GCTL_UR_SHIFT (8)
79#define GCTL(pState) (HDA_REG((pState), GCTL))
80
81#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
82#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
83
84#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
85#define STATESTS(pState) (HDA_REG((pState), STATESTS))
86#define ICH6_HDA_STATES_SCSF 0x7
87
88#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
89#define ICH6_HDA_GSTS_FSH_SHIFT (1)
90#define GSTS(pState) (HDA_REG(pState, GSTS))
91
92#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
93#define ICH6_HDA_INTCTL_GIE_SHIFT 31
94#define ICH6_HDA_INTCTL_CIE_SHIFT 30
95#define ICH6_HDA_INTCTL_S0_SHIFT (0)
96#define ICH6_HDA_INTCTL_S1_SHIFT (1)
97#define ICH6_HDA_INTCTL_S2_SHIFT (2)
98#define ICH6_HDA_INTCTL_S3_SHIFT (3)
99#define ICH6_HDA_INTCTL_S4_SHIFT (4)
100#define ICH6_HDA_INTCTL_S5_SHIFT (5)
101#define ICH6_HDA_INTCTL_S6_SHIFT (6)
102#define ICH6_HDA_INTCTL_S7_SHIFT (7)
103#define INTCTL(pState) (HDA_REG((pState), INTCTL))
104#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
105#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
106#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
107#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
108
109/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
110 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
111 * the datasheet.
112 */
113#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
114#define SSYNC(pState) (HDA_REG((pState), SSYNC))
115
116#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
117#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
118#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
119#define ICH6_HDA_INTSTS_S0_SHIFT (0)
120#define ICH6_HDA_INTSTS_S1_SHIFT (1)
121#define ICH6_HDA_INTSTS_S2_SHIFT (2)
122#define ICH6_HDA_INTSTS_S3_SHIFT (3)
123#define ICH6_HDA_INTSTS_S4_SHIFT (4)
124#define ICH6_HDA_INTSTS_S5_SHIFT (5)
125#define ICH6_HDA_INTSTS_S6_SHIFT (6)
126#define ICH6_HDA_INTSTS_S7_SHIFT (7)
127#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
128#define INTSTS(pState) (HDA_REG((pState), INTSTS))
129#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
130#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
131#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
132#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
133
134#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
135#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
136#define ICH6_HDA_REG_CORBWP 15 /* 48 */
137#define ICH6_HDA_REG_CORBRP 16 /* 4A */
138#define ICH6_HDA_CORBRP_RST_SHIFT 15
139#define ICH6_HDA_CORBRP_WP_SHIFT 0
140#define ICH6_HDA_CORBRP_WP_MASK 0xFF
141
142#define CORBRP(pState) (HDA_REG(pState, CORBRP))
143#define CORBWP(pState) (HDA_REG(pState, CORBWP))
144
145#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
146#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
147#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
148
149#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
150
151
152#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
153#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
154#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
155
156#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
157#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
158#define ICH6_HDA_CORBSIZE_SZ 0x3
159#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
160#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
161/* till ich 10 sizes of CORB and RIRB are harcoded to 256 in real hw */
162#define CORBSIZE(pState) (255)
163
164#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
165#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
166
167#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
168#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
169#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
170#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
171
172#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
173#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
174#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
175
176#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
177#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
178#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
179#define ICH6_HDA_ROI_DMA_SHIFT (2)
180#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
181#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
182#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
183#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
184
185#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
186#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
187#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
188#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
189#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
190#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
191
192#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
193#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
194#define ICH6_HDA_RIRBSIZE_SZ 0x3
195
196#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
197#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
198#define RIRBSIZE(pState) (255)
199
200
201#define ICH6_HDA_REG_IC 27 /* 0x60 */
202#define IC(pState) (HDA_REG(pState, IC))
203#define ICH6_HDA_REG_IR 28 /* 0x64 */
204#define IR(pState) (HDA_REG(pState, IR))
205#define ICH6_HDA_REG_IRS 29 /* 0x68 */
206#define ICH6_HDA_IRS_ICB_SHIFT (0)
207#define ICH6_HDA_IRS_IRV_SHIFT (1)
208#define IRS(pState) (HDA_REG(pState, IRS))
209#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
210#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
211
212#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
213#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
214#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
215#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
216
217#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
218#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
219
220#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
221#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
222#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
223#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
224#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
225#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
226#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
227#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
228
229#define SD(func, num) SD##num##func
230#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
231#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
232#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
233#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
234#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
235#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
236#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
237#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
238#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
239
240#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
241#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
242#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
243#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
244#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
245#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
246#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
247#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
248
249#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
250#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
251#define ICH6_HDA_SDSTS_DE_SHIFT (4)
252#define ICH6_HDA_SDSTS_FE_SHIFT (3)
253#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
254
255#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
256#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
257#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
258#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
259#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
260#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
261#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
262#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
263
264#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
265
266#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
267#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
268#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
269#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
270#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
271#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
272#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
273#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
274
275#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
276
277#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
278#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
279#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
280#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
281#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
282#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
283#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
284#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
285
286#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
287
288#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
289#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
290#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
291#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
292#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
293#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
294#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
295#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
296
297#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
298#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
299#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
300#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
301#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
302#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
303#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
304#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
305
306#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
307
308#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
309#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
310#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
311#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
312#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
313#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
314#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
315#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
316
317#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
318#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
319#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
320#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
321#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
322#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
323#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
324#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
325
326#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
327
328#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
329#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
330#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
331#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
332#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
333#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
334#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
335#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
336
337#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
338
339/* Predicates */
340
341
342typedef struct INTELHDLinkState
343{
344 /** Pointer to the device instance. */
345 PPDMDEVINSR3 pDevIns;
346 /** Pointer to the connector of the attached audio driver. */
347 PPDMIAUDIOCONNECTOR pDrv;
348 /** Pointer to the attached audio driver. */
349 PPDMIBASE pDrvBase;
350 /** The base interface for LUN\#0. */
351 PDMIBASE IBase;
352 RTGCPHYS addrMMReg;
353 uint32_t au32Regs[113];
354 /* Current BD index */
355 uint32_t u32Cvi;
356 uint64_t u64CviAddr;
357 /* Length of current BD entry */
358 uint32_t u32CviLen;
359 uint32_t u32CviPos;
360 uint32_t u32Cbp;
361 /* Interrupt on completition */
362 bool fCviIoc;
363 uint64_t u64CORBBase;
364 uint64_t u64RIRBBase;
365 uint64_t u64DPBase;
366 uint8_t u8CORBRP;
367 /* pointer on CORB buf */
368 uint32_t *pu32CorbBuf;
369 /* size in bytes of CORB buf */
370 uint32_t cbCorbBuf;
371 /* size in double words of CORB buf */
372 uint8_t cdwCorbBuf;
373 /* pointer on RIRB buf */
374 uint64_t *pu64RirbBuf;
375 /* size in bytes of RIRB buf */
376 uint32_t cbRirbBuf;
377 /* size in quad words of RIRB buf */
378 uint8_t cdqRirbBuf;
379 /* indicates if HDA in reset. */
380 bool fInReset;
381 CODECState Codec;
382 uint8_t u8Counter;
383} INTELHDLinkState;
384
385#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
386#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
387
388
389
390
391typedef struct PCIINTELHDLinkState
392{
393 PCIDevice dev;
394 INTELHDLinkState hda;
395} PCIINTELHDLinkState;
396
397DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
398DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
399DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
400DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
401DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
402DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
403DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
404DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
405DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
406DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
407DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
408DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
409DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
410DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
411DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
412DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
413DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
414DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
415
416DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
417DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
418DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
419DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
420DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
421DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
422DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
423DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
424DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
425DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
426DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
427DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
428DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
429static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
430
431/* see 302349 p 6.2*/
432const static struct stIchIntelHDRegMap
433{
434 /** Register offset in the register space. */
435 uint32_t offset;
436 /** Size in bytes. Registers of size > 4 are in fact tables. */
437 uint32_t size;
438 /** Readable bits. */
439 uint32_t readable;
440 /** Writable bits. */
441 uint32_t writable;
442 /** Read callback. */
443 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
444 /** Write callback. */
445 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
446 /** Abbreviated name. */
447 const char *abbrev;
448 /** Full name. */
449 const char *name;
450} s_ichIntelHDRegMap[] =
451{
452 /* offset size read mask write mask read callback write callback abbrev full name */
453 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
454 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
455 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
456 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
457 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
458 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
459 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
460 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
461 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
462 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
463 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
464 { 0x00024, 0x00004, 0xC00000FF, 0x400000FF, hdaRegReadINTSTS , hdaRegWriteINTSTS , "INTSTS" , "Interrupt Status" },
465 //** @todo r=michaln: Are guests really not reading the WALCLK register at all?
466 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
467 //** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
468 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
469 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
470 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
471 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
472 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
473 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
474 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
475 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
476 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
477 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
478 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
479 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
480 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
481 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
482 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
483 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
484 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
485 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadU16 , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
486 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
487 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
488
489 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
490 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
491 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
492 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
493 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
494 { 0x0008E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOW", "ISD0 FIFO Watermark" },
495 { 0x00090, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
496 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FMT" , "ISD0 Format" },
497 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
498 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
499
500 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
501 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
502 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
503 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
504 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
505 { 0x000AE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOW", "ISD1 FIFO Watermark" },
506 { 0x000B0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
507 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FMT" , "ISD1 Format" },
508 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
509 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
510
511 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
512 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
513 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
514 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
515 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
516 { 0x000CE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOW", "ISD2 FIFO Watermark" },
517 { 0x000D0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
518 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FMT" , "ISD2 Format" },
519 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
520 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
521
522 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
523 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
524 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
525 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
526 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
527 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
528 { 0x000F0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
529 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FMT" , "ISD3 Format" },
530 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
531 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
532
533 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
534 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
535 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
536 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
537 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
538 { 0x0010E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOW", "OSD0 FIFO Watermark" },
539 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOS", "OSD0 FIFO Size" },
540 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FMT" , "OSD0 Format" },
541 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
542 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
543
544 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
545 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
546 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
547 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
548 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
549 { 0x0012E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOW", "OSD1 FIFO Watermark" },
550 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOS", "OSD1 FIFO Size" },
551 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FMT" , "OSD1 Format" },
552 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
553 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
554
555 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
556 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
557 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
558 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
559 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
560 { 0x0014E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOW", "OSD2 FIFO Watermark" },
561 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOS", "OSD2 FIFO Size" },
562 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FMT" , "OSD2 Format" },
563 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
564 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
565
566 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
567 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
568 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
569 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
570 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
571 { 0x0016E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOW", "OSD3 FIFO Watermark" },
572 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOS", "OSD3 FIFO Size" },
573 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FMT" , "OSD3 Format" },
574 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
575 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
576};
577
578static int hdaProcessInterrupt(INTELHDLinkState* pState)
579{
580 bool fIrq = false;
581 /* @todo add state change */
582 if( INTCTL_CIE(pState)
583 && ( RIRBSTS_RINTFL(pState)
584 || RIRBSTS_RIRBOIS(pState)))
585 {
586 INTSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(INTSTS, CIS);
587 fIrq = true;
588 }
589 if ( INTCTL_SX(pState, 4)
590 && SDSTS(pState, 4) && HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))
591 {
592 INTSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(INTSTS, S4);
593 fIrq = true;
594 }
595 if (INTCTL_GIE(pState))
596 {
597 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
598 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
599 }
600 return VINF_SUCCESS;
601}
602
603static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
604{
605 int index = 0;
606 //** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
607 for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
608 {
609 if ( u32Offset >= s_ichIntelHDRegMap[index].offset
610 && u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
611 {
612 return index;
613 }
614 }
615 return -1;
616}
617
618static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
619{
620 int rc = VINF_SUCCESS;
621 if (fLocal)
622 {
623 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
624 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
625 if (RT_FAILURE(rc))
626 AssertRCReturn(rc, rc);
627 uint8_t i = 0;
628 do
629 {
630 Log(("hda: corb%02x: ", i));
631 uint8_t j = 0;
632 do
633 {
634 const char *prefix;
635 if ((i + j) == CORBRP(pState))
636 prefix = "[R]";
637 else if ((i + j) == CORBWP(pState))
638 prefix = "[W]";
639 else
640 prefix = " "; /* three spaces */
641 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
642 j++;
643 } while (j < 8);
644 Log(("\n"));
645 i += 8;
646 } while(i != 0);
647 }
648 else
649 {
650 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
651 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
652 if (RT_FAILURE(rc))
653 AssertRCReturn(rc, rc);
654 uint8_t i = 0;
655 do {
656 Log(("hda: rirb%02x: ", i));
657 uint8_t j = 0;
658 do {
659 const char *prefix;
660 if ((i + j) == RIRBWP(pState))
661 prefix = "[W]";
662 else
663 prefix = " ";
664 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
665 } while (++j < 8);
666 Log(("\n"));
667 i += 8;
668 } while (i != 0);
669 }
670 return rc;
671}
672
673#if 0
674static int hdaUnsolictedResponse(INTELHDLinkState *pState, uint64_t pu64UnsolictedResponse)
675{
676 uint8_t rirbWp;
677 if (!HDA_REG_FLAG_VALUE(pState, GCTL, UR))
678 {
679 Log(("hda: unsolicited response %016lx is ignored\n"));
680 return VINF_SUCCESS;
681 }
682}
683#endif
684
685static int hdaCORBCmdProcess(INTELHDLinkState *pState)
686{
687 int rc;
688 uint8_t corbRp;
689 uint8_t corbWp;
690 uint8_t rirbWp;
691
692 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
693
694 rc = hdaCmdSync(pState, true);
695 if (RT_FAILURE(rc))
696 AssertRCReturn(rc, rc);
697 corbRp = CORBRP(pState);
698 corbWp = CORBWP(pState);
699 rirbWp = RIRBWP(pState);
700 Assert((corbWp != corbRp));
701 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
702 while (corbRp != corbWp)
703 {
704 uint32_t cmd;
705 uint64_t resp;
706 corbRp++;
707 cmd = pState->pu32CorbBuf[corbRp];
708 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
709 if (RT_FAILURE(rc))
710 AssertRCReturn(rc, rc);
711 Assert(pfn);
712 (rirbWp)++;
713 rc = pfn(&pState->Codec, cmd, &resp);
714 if (RT_FAILURE(rc))
715 AssertRCReturn(rc, rc);
716 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
717 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
718 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
719 {
720 Log(("hda: unexpected unsolicited response.\n"));
721 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
722 return rc;
723 }
724 pState->pu64RirbBuf[rirbWp] = resp;
725 pState->u8Counter++;
726 if (pState->u8Counter == RINTCNT_N(pState))
727 break;
728 }
729 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
730 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
731 rc = hdaCmdSync(pState, false);
732 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
733 if (RIRBCTL_RIRB_RIC(pState))
734 {
735 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
736 pState->u8Counter = 0;
737 rc = hdaProcessInterrupt(pState);
738 }
739 if (RT_FAILURE(rc))
740 AssertRCReturn(rc, rc);
741 return rc;
742}
743
744static void hdaStreamReset(INTELHDLinkState *pState, uint32_t u32Offset)
745{
746 Log(("hda: reset of stream (%x) started\n", u32Offset));
747 Log(("hda: reset of stream (%x) finished\n", u32Offset));
748}
749
750
751DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
752{
753 *pu32Value = 0;
754 return VINF_SUCCESS;
755}
756DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
757{
758 return VINF_SUCCESS;
759}
760/* U8 */
761DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
762{
763 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
764 return hdaRegReadU32(pState, offset, index, pu32Value);
765}
766
767DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
768{
769 Assert(((u32Value & 0xffffff00) == 0));
770 return hdaRegWriteU32(pState, offset, index, u32Value);
771}
772/* U16 */
773DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
774{
775 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
776 return hdaRegReadU32(pState, offset, index, pu32Value);
777}
778
779DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
780{
781 Assert(((u32Value & 0xffff0000) == 0));
782 return hdaRegWriteU32(pState, offset, index, u32Value);
783}
784
785/* U24 */
786DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
787{
788 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
789 return hdaRegReadU32(pState, offset, index, pu32Value);
790}
791
792DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
793{
794 Assert(((u32Value & 0xff000000) == 0));
795 return hdaRegWriteU32(pState, offset, index, u32Value);
796}
797/* U32 */
798DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
799{
800 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
801 return VINF_SUCCESS;
802}
803
804DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
805{
806 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
807 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
808 return VINF_SUCCESS;
809}
810
811DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
812{
813 return hdaRegReadU32(pState, offset, index, pu32Value);
814}
815
816DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
817{
818 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
819 {
820 /* exit reset state */
821 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
822 pState->fInReset = false;
823 }
824 else
825 {
826 /* enter reset state*/
827 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
828 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
829 {
830 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
831 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
832 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
833 }
834 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
835 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
836 pState->fInReset = true;
837 }
838 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
839 {
840 /* Flush: GSTS:1 set, see 6.2.6*/
841 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
842 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
843 }
844 return VINF_SUCCESS;
845}
846
847DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
848{
849 uint32_t v = pState->au32Regs[index];
850 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
851 pState->au32Regs[index] = (v ^ nv) & v; /* write of 1 clears corresponding bit */
852 return VINF_SUCCESS;
853}
854
855DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
856{
857 uint32_t v = INTSTS(pState);
858 v &= ~HDA_REG_FIELD_FLAG_MASK(INTSTS, GIS);
859 v |= (v ? HDA_REG_FIELD_FLAG_MASK(INTSTS, GIS) : 0);
860 *pu32Value = v;
861 return VINF_SUCCESS;
862}
863
864DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
865{
866 uint32_t v = INTSTS(pState);
867 INTSTS(pState) = (v ^ u32Value) & v;
868 return hdaProcessInterrupt(pState);
869}
870
871DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
872{
873 return hdaRegReadU16(pState, offset, index, pu32Value);
874}
875
876DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
877{
878 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
879 {
880 pState->u8CORBRP = 0;
881 CORBRP(pState) = 0;
882 }
883 else
884 return hdaRegWriteU8(pState, offset, index, u32Value);
885 return VINF_SUCCESS;
886}
887
888DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
889{
890 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
891 AssertRC(rc);
892 if ( CORBWP(pState) != CORBRP(pState)
893 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
894 return hdaCORBCmdProcess(pState);
895 return rc;
896}
897
898DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
899{
900 uint32_t v = CORBSTS(pState);
901 v = (v ^ u32Value) & v;
902 CORBSTS(pState) = v;
903 return VINF_SUCCESS;
904}
905
906DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
907{
908 int rc;
909 rc = hdaRegWriteU16(pState, offset, index, u32Value);
910 if (RT_FAILURE(rc))
911 AssertRCReturn(rc, rc);
912 if (CORBWP(pState) == CORBRP(pState))
913 return VINF_SUCCESS;
914 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
915 return VINF_SUCCESS;
916 rc = hdaCORBCmdProcess(pState);
917 return rc;
918}
919
920DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
921{
922 return hdaRegReadU24(pState, offset, index, pu32Value);
923}
924
925DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
926{
927 if((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)))
928 {
929 hdaStreamReset(pState, offset);
930 }
931 /* @todo: use right offsets for right streams */
932 if (u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
933 {
934 Log(("hda: DMA(%x) switched on\n", offset));
935 AUD_set_active_in(pState->Codec.voice_pi, 1);
936 AUD_set_active_in(pState->Codec.voice_mc, 1);
937 if (offset == 0x100)
938 {
939 AUD_set_active_out(pState->Codec.voice_po, 1);
940 //SDSTS(pState, 4) |= (1<<5);
941 }
942 }
943 else
944 {
945 Log(("hda: DMA(%x) switched off\n", offset));
946 AUD_set_active_in(pState->Codec.voice_pi, 0);
947 AUD_set_active_in(pState->Codec.voice_mc, 0);
948 if (offset == 0x100)
949 {
950 SDSTS(pState, 4) &= ~(1<<5);
951 AUD_set_active_out(pState->Codec.voice_po, 0);
952 }
953 SSYNC(pState) &= ~(1<< (offset - 0x80));
954 }
955 int rc = hdaRegWriteU24(pState, offset, index, u32Value);
956 if (RT_FAILURE(rc))
957 AssertRCReturn(rc, VINF_SUCCESS);
958 return rc;
959}
960
961DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
962{
963 uint32_t v = HDA_REG_IND(pState, index);
964 //int rc = hdaRegWriteU8(pState, offset, index, u32Value);
965 switch (offset)
966 {
967 case 0x83:
968 SDSTS(pState, 0) ^= u32Value;
969 break;
970 case 0xA3:
971 SDSTS(pState, 1) ^= u32Value;
972 break;
973 case 0xC3:
974 SDSTS(pState, 2) ^= u32Value;
975 break;
976 case 0xE3:
977 SDSTS(pState, 3) ^= u32Value;
978 break;
979 case 0x103:
980 SDSTS(pState, 4) ^= u32Value;
981 break;
982 case 0x123:
983 SDSTS(pState, 5) ^= u32Value;
984 break;
985 case 0x143:
986 SDSTS(pState, 6) ^= u32Value;
987 break;
988 case 0x163:
989 SDSTS(pState, 7) ^= u32Value;
990 break;
991 }
992 hdaProcessInterrupt(pState);
993#if 0
994 if ( v != u32Value
995 && (INTCTL_SALL(pState) & (1 << ((offset - 0x83) >> 5))))
996 {
997 int rc;
998 rc = hdaProcessInterrupt(pState);
999 if (RT_FAILURE(rc))
1000 AssertRCReturn(rc, rc);
1001 }
1002#endif
1003 return VINF_SUCCESS;
1004}
1005DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1006{
1007 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1008 if (RT_FAILURE(rc))
1009 AssertRCReturn(rc, VINF_SUCCESS);
1010 return rc;
1011}
1012
1013DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1014{
1015 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1016 if (RT_FAILURE(rc))
1017 AssertRCReturn(rc, VINF_SUCCESS);
1018 return rc;
1019}
1020
1021DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1022{
1023 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1024 if (RT_FAILURE(rc))
1025 AssertRCReturn(rc, VINF_SUCCESS);
1026 return rc;
1027}
1028
1029DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1030{
1031 int rc = VINF_SUCCESS;
1032 uint64_t resp;
1033 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1034 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1035 && !IRS_ICB(pState))
1036 {
1037 uint32_t cmd = IC(pState);
1038 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1039 Log(("hda: IC:%x\n", cmd));
1040 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1041 if (RT_FAILURE(rc))
1042 AssertRCReturn(rc, rc);
1043 rc = pfn(&pState->Codec, cmd, &resp);
1044 if (RT_FAILURE(rc))
1045 AssertRCReturn(rc, rc);
1046 IR(pState) = (uint32_t)resp;
1047 Log(("hda: IR:%x\n", IR(pState)));
1048 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* clear busy, result is ready */
1049 return rc;
1050 }
1051 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1052 && IRS_IRV(pState))
1053 IRS(pState) ^= HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1054 return rc;
1055}
1056
1057DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1058{
1059 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1060 {
1061 RIRBWP(pState) = 0;
1062 }
1063 /*The rest of bits are O, see 6.2.22 */
1064 return VINF_SUCCESS;
1065}
1066
1067DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1068{
1069 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1070 if (RT_FAILURE(rc))
1071 AssertRCReturn(rc, rc);
1072 switch(index)
1073 {
1074 case ICH6_HDA_REG_CORBLBASE:
1075 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1076 pState->u64CORBBase |= pState->au32Regs[index];
1077 break;
1078 case ICH6_HDA_REG_CORBUBASE:
1079 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1080 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1081 break;
1082 case ICH6_HDA_REG_RIRLBASE:
1083 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1084 pState->u64RIRBBase |= pState->au32Regs[index];
1085 break;
1086 case ICH6_HDA_REG_RIRUBASE:
1087 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1088 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1089 break;
1090 case ICH6_HDA_REG_DPLBASE:
1091 /* @todo: first bit has special meaning */
1092 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1093 pState->u64DPBase |= pState->au32Regs[index];
1094 break;
1095 case ICH6_HDA_REG_DPUBASE:
1096 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1097 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1098 break;
1099 default:
1100 AssertMsgFailed(("Invalid index"));
1101 }
1102 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1103 return rc;
1104}
1105
1106DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1107{
1108 uint8_t nv = u32Value;
1109 uint8_t v = RIRBSTS(pState);
1110 RIRBSTS(pState) = (v ^ nv) & v;
1111
1112 return hdaProcessInterrupt(pState);
1113}
1114
1115static void dump_bd(INTELHDLinkState *pState)
1116{
1117 uint64_t addr;
1118 uint32_t len;
1119 uint32_t ioc;
1120 uint8_t bdle[16];
1121 uint32_t counter;
1122 uint32_t i;
1123 uint32_t sum = 0;
1124 for (i = 0; i <= SDLVI(pState, 4); ++i)
1125 {
1126 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), SDBDPL(pState, 4) + i*16, bdle, 16);
1127 addr = *(uint64_t *)bdle;
1128 len = *(uint32_t *)&bdle[8];
1129 ioc = *(uint32_t *)&bdle[12];
1130 Log(("hda: %s bdle[%d] a:%x, len:%x, ios:%d\n", (i == pState->u32Cvi? "[C]": " "), i, addr, len, ioc));
1131 sum += len;
1132 }
1133 Log(("hda: sum: %d\n", sum));
1134 for (i = 0; i < 8; ++i)
1135 {
1136 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64DPBase + i*8, &counter, 4);
1137 Log(("hda: %s stream[%d] counter=%x\n", (i) == SDCTL_NUM(pState, 4)? "[C]": " ", i , counter));
1138 }
1139}
1140static void fetch_bd(INTELHDLinkState *pState)
1141{
1142 dump_bd(pState);
1143 pState->u32Cvi;
1144 uint8_t bdle[16];
1145 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), SDBDPL(pState, 4) + pState->u32Cvi*16, bdle, 16);
1146 pState->u64CviAddr = *(uint64_t *)bdle;
1147 pState->u32CviLen = *(uint32_t *)&bdle[8];
1148 pState->fCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1149}
1150
1151static uint32_t write_audio(INTELHDLinkState *pState, int avail, bool *fStop)
1152{
1153 uint8_t tmpbuf[4096];
1154 uint32_t temp;
1155 uint32_t u32Rest;
1156 uint32_t written = 0;
1157 int to_copy = 0;
1158 u32Rest = pState->u32CviLen - pState->u32CviPos;
1159 temp = audio_MIN(u32Rest, (uint32_t)avail);
1160 if (!temp)
1161 {
1162 *fStop = true;
1163 return written;
1164 }
1165 while (temp)
1166 {
1167 int copied;
1168 to_copy = audio_MIN(temp, 4096U);
1169 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CviAddr + pState->u32CviPos, tmpbuf, to_copy);
1170 copied = AUD_write (pState->Codec.voice_po, tmpbuf, to_copy);
1171 Log (("hda: write_audio max=%x to_copy=%x copied=%x\n",
1172 avail, to_copy, copied));
1173 Assert((copied));
1174 if (!copied)
1175 {
1176 *fStop = true;
1177 break;
1178 }
1179 temp -= copied;
1180 written += copied;
1181 pState->u32CviPos += written;
1182 }
1183 return written;
1184}
1185
1186DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1187{
1188 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1189 STATESTS(pState) |= 1 << (pCodecState->id);
1190 INTSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(INTSTS, CIS);
1191 return VINF_SUCCESS;
1192}
1193
1194DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1195{
1196 bool fStop = false;
1197 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1198 switch(src)
1199 {
1200 case PO_INDEX:
1201 {
1202 uint32_t written;
1203 uint32_t u32Counter;
1204 if ( !(SDCTL(pState, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1205 || avail == 0)
1206 return;
1207 SDCTL(pState, 4) |= ((pState->Codec.pNodes[2].adc.u32F06_param & (0x5 << 4)) >> 4) << 20;
1208 fetch_bd(pState);
1209 while( avail
1210 && !fStop)
1211 {
1212 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + 4*8, &u32Counter, 4);
1213 written = write_audio(pState, avail, &fStop);
1214 if (fStop)
1215 break;
1216 SDLPIB(pState, 4) += written; /* bytes ? */
1217 avail -= written;
1218 u32Counter += written;
1219 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + 4*8, &u32Counter, 4);
1220 if (pState->u32CviPos == pState->u32CviLen
1221 || SDLPIB(pState, 4) == SDLCBL(pState, 4))
1222 {
1223 if ( SDCTL(pState, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)
1224 && ( pState->u32CviPos == pState->u32CviLen
1225 || SDLPIB(pState, 4) == SDLCBL(pState, 4)))
1226 {
1227 SDSTS(pState,4) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1228 INTSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(INTSTS, S4);
1229 hdaProcessInterrupt(pState);
1230 if (SDLPIB(pState, 4) == SDLCBL(pState, 4))
1231 {
1232 SDLPIB(pState, 4) = 0;
1233 u32Counter = 0;
1234 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + 4*8, &u32Counter, 4);
1235 }
1236 if (pState->u32CviPos == pState->u32CviLen)
1237 {
1238 pState->u32CviPos = 0;
1239 pState->u32Cvi++;
1240 if (pState->u32Cvi == SDLVI(pState, 4) + 1)
1241 pState->u32Cvi = 0;
1242 }
1243 }
1244 }
1245 fetch_bd(pState);
1246 }
1247 }
1248 break;
1249 AssertMsgFailed(("Unexpected index: %x\n", src));
1250 default:
1251 break;
1252 }
1253}
1254
1255/**
1256 * Handle register read operation.
1257 *
1258 * Looks up and calls appropriate handler.
1259 *
1260 * @note: while implementation was detected so called "forgotten" or "hole" registers
1261 * which description is missed in RPM, datasheet or spec.
1262 *
1263 * @returns VBox status code.
1264 *
1265 * @param pState The device state structure.
1266 * @param uOffset Register offset in memory-mapped frame.
1267 * @param pv Where to fetch the value.
1268 * @param cb Number of bytes to write.
1269 * @thread EMT
1270 */
1271PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1272{
1273 int rc = VINF_SUCCESS;
1274 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1275 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1276 int index = hdaLookup(&pThis->hda, u32Offset);
1277 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1278 {
1279 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1280 }
1281 Assert( index != -1
1282 && u32Offset == s_ichIntelHDRegMap[index].offset
1283 && cb <= 4);
1284 if (index != -1)
1285 {
1286 uint32_t mask = 0;
1287 uint32_t v = 0;
1288 switch(cb)
1289 {
1290 case 1: mask = 0x000000ff; break;
1291 case 2: mask = 0x0000ffff; break;
1292 case 3: mask = 0x00ffffff; break;
1293 case 4: mask = 0xffffffff; break;
1294 }
1295 Assert(u32Offset == s_ichIntelHDRegMap[index].offset);
1296 rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1297 *(uint32_t *)pv = v & mask;
1298 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
1299 return rc;
1300 }
1301 *(uint32_t *)pv = 0xFF;
1302 Log(("hda: hole at %X is accessed for read\n", u32Offset));
1303 return rc;
1304}
1305
1306/**
1307 * Handle register write operation.
1308 *
1309 * Looks up and calls appropriate handler.
1310 *
1311 * @returns VBox status code.
1312 *
1313 * @param pState The device state structure.
1314 * @param uOffset Register offset in memory-mapped frame.
1315 * @param pv Where to fetch the value.
1316 * @param cb Number of bytes to write.
1317 * @thread EMT
1318 */
1319PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1320{
1321 int rc = VINF_SUCCESS;
1322 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1323 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1324 int index = hdaLookup(&pThis->hda, u32Offset);
1325 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1326 {
1327 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1328 }
1329 Assert( index != -1
1330 && u32Offset == s_ichIntelHDRegMap[index].offset
1331 && cb <= 4);
1332 if (index != -1)
1333 {
1334 Assert(u32Offset == s_ichIntelHDRegMap[index].offset);
1335 uint32_t v = pThis->hda.au32Regs[index];
1336 uint32_t mask = 0;
1337 switch(cb)
1338 {
1339 case 1: mask = 0xffffff00; break;
1340 case 2: mask = 0xffff0000; break;
1341 case 3: mask = 0xff000000; break;
1342 case 4: mask = 0x00000000; break;
1343 }
1344 *(uint32_t *)pv = (v & mask) | (*(uint32_t *)pv & ~mask);
1345 rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
1346 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
1347 return rc;
1348 }
1349 Log(("hda: hole at %X is accessed for write\n", u32Offset));
1350 return rc;
1351}
1352
1353/**
1354 * Callback function for mapping a PCI I/O region.
1355 *
1356 * @return VBox status code.
1357 * @param pPciDev Pointer to PCI device.
1358 * Use pPciDev->pDevIns to get the device instance.
1359 * @param iRegion The region number.
1360 * @param GCPhysAddress Physical address of the region.
1361 * If iType is PCI_ADDRESS_SPACE_IO, this is an
1362 * I/O port, else it's a physical address.
1363 * This address is *NOT* relative
1364 * to pci_mem_base like earlier!
1365 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
1366 */
1367static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
1368 RTGCPHYS GCPhysAddress, uint32_t cb,
1369 PCIADDRESSSPACE enmType)
1370{
1371 int rc;
1372 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1373 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1374 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1375
1376 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1377 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
1378 hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
1379
1380 if (RT_FAILURE(rc))
1381 return rc;
1382
1383 pThis->hda.addrMMReg = GCPhysAddress;
1384 return VINF_SUCCESS;
1385}
1386
1387
1388/**
1389 * Reset notification.
1390 *
1391 * @returns VBox status.
1392 * @param pDevIns The device instance data.
1393 *
1394 * @remark The original sources didn't install a reset handler, but it seems to
1395 * make sense to me so we'll do it.
1396 */
1397static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns)
1398{
1399 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1400 GCAP(&pThis->hda) = 0x4401; /* see 6.2.1 */
1401 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
1402 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1403 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1404 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
1405 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
1406 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
1407 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
1408 CORBRP(&pThis->hda) = 0x0;
1409 RIRBWP(&pThis->hda) = 0x0;
1410
1411 LogRel(("hda: inter HDA reset.\n"));
1412 //** @todo r=michaln: There should be LogRel statements when the guest initializes
1413 // or resets the HDA chip, and possibly also when opening the PCM streams.
1414 pThis->hda.cdwCorbBuf = CORBSIZE(&pThis->hda);
1415 pThis->hda.cbCorbBuf = CORBSIZE(&pThis->hda) * sizeof(uint32_t);
1416
1417 if (pThis->hda.pu32CorbBuf)
1418 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
1419 else
1420 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
1421
1422 pThis->hda.cdqRirbBuf = RIRBSIZE(&pThis->hda);
1423 pThis->hda.cbRirbBuf = RIRBSIZE(&pThis->hda) * sizeof(uint64_t);
1424 if (pThis->hda.pu64RirbBuf)
1425 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
1426 else
1427 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
1428
1429 /* Accoding to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
1430 * bits are reserved for stream number 18.2.33 */
1431 SDCTL(&pThis->hda, 0) = 0x40000;
1432 SDCTL(&pThis->hda, 1) = 0x40000;
1433 SDCTL(&pThis->hda, 2) = 0x40000;
1434 SDCTL(&pThis->hda, 3) = 0x40000;
1435 SDCTL(&pThis->hda, 4) = 0x40000;
1436 SDCTL(&pThis->hda, 5) = 0x40000;
1437 SDCTL(&pThis->hda, 6) = 0x40000;
1438 SDCTL(&pThis->hda, 7) = 0x40000;
1439
1440 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1441 SDFIFOS(&pThis->hda, 0) = 0x77;
1442 SDFIFOS(&pThis->hda, 1) = 0x77;
1443 SDFIFOS(&pThis->hda, 2) = 0x77;
1444 SDFIFOS(&pThis->hda, 3) = 0x77;
1445 SDFIFOS(&pThis->hda, 4) = 0xBF;
1446 SDFIFOS(&pThis->hda, 5) = 0xBF;
1447 SDFIFOS(&pThis->hda, 6) = 0xBF;
1448 SDFIFOS(&pThis->hda, 7) = 0xBF;
1449
1450 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
1451 STATESTS(&pThis->hda) = 0x1;
1452
1453 Log(("hda: reset finished\n"));
1454}
1455
1456/**
1457 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1458 */
1459static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
1460 const char *pszIID)
1461{
1462 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
1463 Assert(&pThis->hda.IBase == pInterface);
1464
1465 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
1466 return NULL;
1467}
1468
1469/**
1470 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1471 */
1472static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
1473 PCFGMNODE pCfgHandle)
1474{
1475 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1476 INTELHDLinkState *s = &pThis->hda;
1477 int rc;
1478
1479 Assert(iInstance == 0);
1480 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1481
1482 /*
1483 * Validations.
1484 */
1485 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
1486 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1487 N_ ("Invalid configuration for the INTELHD device"));
1488
1489 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
1490 // poll some register(s).
1491
1492 /*
1493 * Initialize data (most of it anyway).
1494 */
1495 s->pDevIns = pDevIns;
1496 /* IBase */
1497 s->IBase.pfnQueryInterface = hdaQueryInterface;
1498
1499 /* PCI Device (the assertions will be removed later) */
1500 PCIDevSetVendorId (&pThis->dev, 0x8086); /* 00 ro - intel. */
1501 PCIDevSetDeviceId (&pThis->dev, 0x2668); /* 02 ro - 82801 / 82801aa(?). */
1502 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
1503 PCIDevSetStatus (&pThis->dev, 0x0010); /* 06 rwc?,ro? - pcists. */
1504 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
1505 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
1506 PCIDevSetClassSub (&pThis->dev, 0x02); /* 0a ro - scc; 02 == HDA. */
1507 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
1508 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
1509 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
1510 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
1511 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
1512 verb F20 should provide device/codec recognition. */
1513 PCIDevSetSubSystemVendorId (&pThis->dev, 0x0000); /* 2c ro - intel.) */
1514 PCIDevSetSubSystemId (&pThis->dev, 0x0000); /* 2e ro. */
1515 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
1516 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */ Assert (pThis->dev.config[0x3d] == 0x01);
1517 PCIDevSetCapabilityList(&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
1518
1519 //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
1520 // of these values needs to be properly documented!
1521 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1522 pThis->dev.config[0x40] = 0x01;
1523
1524 pThis->dev.config[0x50] = 0x01;
1525 pThis->dev.config[0x51] = 0x60; /* next */
1526 pThis->dev.config[0x52] = 0x22;
1527 pThis->dev.config[0x53] = 0x00; /* PM - disabled, */
1528
1529#if 0
1530 pThis->dev.config[0x60] = 0x05;
1531 pThis->dev.config[0x61] = 0x70; /* next */
1532 pThis->dev.config[0x62] = 0x00;
1533 pThis->dev.config[0x63] = 0x80;
1534#endif
1535
1536 /*
1537 * Register the PCI device.
1538 */
1539 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
1540 if (RT_FAILURE (rc))
1541 return rc;
1542
1543 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
1544 hdaMap);
1545 if (RT_FAILURE (rc))
1546 return rc;
1547
1548 /*
1549 * Attach driver.
1550 */
1551 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
1552 &s->pDrvBase, "Audio Driver Port");
1553 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1554 Log (("hda: No attached driver!\n"));
1555 else if (RT_FAILURE (rc))
1556 {
1557 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
1558 return rc;
1559 }
1560
1561
1562
1563 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
1564 rc = stac9220Construct(&pThis->hda.Codec);
1565 if (RT_FAILURE(rc))
1566 AssertRCReturn(rc, rc);
1567 hdaReset (pDevIns);
1568 pThis->hda.Codec.id = 0;
1569 pThis->hda.Codec.pfnTransfer = hdaTransfer;
1570 pThis->hda.Codec.pfnReset = hdaCodecReset;
1571 /*
1572 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
1573 * hdaReset shouldn't affects these registers.
1574 */
1575 WAKEEN(&pThis->hda) = 0x0;
1576 STATESTS(&pThis->hda) = 0x0;
1577
1578 return VINF_SUCCESS;
1579}
1580
1581/**
1582 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1583 */
1584static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
1585{
1586 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1587
1588 int rc = stac9220Destruct(&pThis->hda.Codec);
1589 AssertRC(rc);
1590 if (pThis->hda.pu32CorbBuf)
1591 RTMemFree(pThis->hda.pu32CorbBuf);
1592 if (pThis->hda.pu64RirbBuf)
1593 RTMemFree(pThis->hda.pu64RirbBuf);
1594 return VINF_SUCCESS;
1595}
1596
1597/**
1598 * The device registration structure.
1599 */
1600const PDMDEVREG g_DeviceICH6_HDA =
1601{
1602 /* u32Version */
1603 PDM_DEVREG_VERSION,
1604 /* szName */
1605 "hda",
1606 /* szRCMod */
1607 "",
1608 /* szR0Mod */
1609 "",
1610 /* pszDescription */
1611 "ICH IntelHD Audio Controller",
1612 /* fFlags */
1613 PDM_DEVREG_FLAGS_DEFAULT_BITS,
1614 /* fClass */
1615 PDM_DEVREG_CLASS_AUDIO,
1616 /* cMaxInstances */
1617 1,
1618 /* cbInstance */
1619 sizeof(PCIINTELHDLinkState),
1620 /* pfnConstruct */
1621 hdaConstruct,
1622 /* pfnDestruct */
1623 hdaDestruct,
1624 /* pfnRelocate */
1625 NULL,
1626 /* pfnIOCtl */
1627 NULL,
1628 /* pfnPowerOn */
1629 NULL,
1630 /* pfnReset */
1631 hdaReset,
1632 /* pfnSuspend */
1633 NULL,
1634 /* pfnResume */
1635 NULL,
1636 /* pfnAttach */
1637 NULL,
1638 /* pfnDetach */
1639 NULL,
1640 /* pfnQueryInterface. */
1641 NULL,
1642 /* pfnInitComplete */
1643 NULL,
1644 /* pfnPowerOff */
1645 NULL,
1646 /* pfnSoftReset */
1647 NULL,
1648 /* u32VersionEnd */
1649 PDM_DEVREG_VERSION
1650};
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette