VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 31713

Last change on this file since 31713 was 31507, checked in by vboxsync, 14 years ago

Audio/HDA: STAC9220 doesn't support EPSS, so "Double reset" detection isn't required. Old style reset should prevent reseting Default Configuration controls.

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File size: 74.2 KB
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1/* $Id: DevIchIntelHDA.cpp 31507 2010-08-10 06:52:49Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/pdmdev.h>
23#include <iprt/assert.h>
24#include <iprt/uuid.h>
25#include <iprt/string.h>
26#include <iprt/mem.h>
27#include <iprt/asm.h>
28
29#include "../Builtins.h"
30
31extern "C" {
32#include "audio.h"
33}
34#include "DevCodec.h"
35
36#undef LOG_VOICES
37#ifndef VBOX
38//#define USE_MIXER
39#else
40#define USE_MIXER
41#endif
42
43#define INTELHD_SSM_VERSION 1
44PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
45PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
46static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
47
48/* Registers */
49#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
50#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
51#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
52#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
53#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
54#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
55#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
56#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
57#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
58#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
59
60#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
61#define GCAP(pState) (HDA_REG((pState), GCAP))
62
63#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
64#define VMIN(pState) (HDA_REG((pState), VMIN))
65
66#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
67#define VMAJ(pState) (HDA_REG((pState), VMAJ))
68
69#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
70#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
71
72#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
73#define INPAY(pState) (HDA_REG((pState), INPAY))
74
75#define ICH6_HDA_REG_GCTL (5)
76#define ICH6_HDA_GCTL_RST_SHIFT (0)
77#define ICH6_HDA_GCTL_FSH_SHIFT (1)
78#define ICH6_HDA_GCTL_UR_SHIFT (8)
79#define GCTL(pState) (HDA_REG((pState), GCTL))
80
81#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
82#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
83
84#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
85#define STATESTS(pState) (HDA_REG((pState), STATESTS))
86#define ICH6_HDA_STATES_SCSF 0x7
87
88#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
89#define ICH6_HDA_GSTS_FSH_SHIFT (1)
90#define GSTS(pState) (HDA_REG(pState, GSTS))
91
92#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
93#define ICH6_HDA_INTCTL_GIE_SHIFT 31
94#define ICH6_HDA_INTCTL_CIE_SHIFT 30
95#define ICH6_HDA_INTCTL_S0_SHIFT (0)
96#define ICH6_HDA_INTCTL_S1_SHIFT (1)
97#define ICH6_HDA_INTCTL_S2_SHIFT (2)
98#define ICH6_HDA_INTCTL_S3_SHIFT (3)
99#define ICH6_HDA_INTCTL_S4_SHIFT (4)
100#define ICH6_HDA_INTCTL_S5_SHIFT (5)
101#define ICH6_HDA_INTCTL_S6_SHIFT (6)
102#define ICH6_HDA_INTCTL_S7_SHIFT (7)
103#define INTCTL(pState) (HDA_REG((pState), INTCTL))
104#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
105#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
106#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
107#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
108
109/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
110 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
111 * the datasheet.
112 */
113#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
114#define SSYNC(pState) (HDA_REG((pState), SSYNC))
115
116#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
117#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
118#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
119#define ICH6_HDA_INTSTS_S0_SHIFT (0)
120#define ICH6_HDA_INTSTS_S1_SHIFT (1)
121#define ICH6_HDA_INTSTS_S2_SHIFT (2)
122#define ICH6_HDA_INTSTS_S3_SHIFT (3)
123#define ICH6_HDA_INTSTS_S4_SHIFT (4)
124#define ICH6_HDA_INTSTS_S5_SHIFT (5)
125#define ICH6_HDA_INTSTS_S6_SHIFT (6)
126#define ICH6_HDA_INTSTS_S7_SHIFT (7)
127#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
128#define INTSTS(pState) (HDA_REG((pState), INTSTS))
129#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
130#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
131#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
132#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
133
134#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
135#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
136#define ICH6_HDA_REG_CORBWP 15 /* 48 */
137#define ICH6_HDA_REG_CORBRP 16 /* 4A */
138#define ICH6_HDA_CORBRP_RST_SHIFT 15
139#define ICH6_HDA_CORBRP_WP_SHIFT 0
140#define ICH6_HDA_CORBRP_WP_MASK 0xFF
141
142#define CORBRP(pState) (HDA_REG(pState, CORBRP))
143#define CORBWP(pState) (HDA_REG(pState, CORBWP))
144
145#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
146#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
147#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
148
149#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
150
151
152#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
153#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
154#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
155
156#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
157#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
158#define ICH6_HDA_CORBSIZE_SZ 0x3
159#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
160#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
161/* till ich 10 sizes of CORB and RIRB are harcoded to 256 in real hw */
162#define CORBSIZE(pState) (255)
163
164#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
165#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
166
167#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
168#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
169#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
170#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
171
172#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
173#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
174#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
175
176#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
177#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
178#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
179#define ICH6_HDA_ROI_DMA_SHIFT (2)
180#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
181#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
182#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
183#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
184
185#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
186#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
187#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
188#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
189#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
190#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
191
192#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
193#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
194#define ICH6_HDA_RIRBSIZE_SZ 0x3
195
196#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
197#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
198#define RIRBSIZE(pState) (255)
199
200
201#define ICH6_HDA_REG_IC 27 /* 0x60 */
202#define IC(pState) (HDA_REG(pState, IC))
203#define ICH6_HDA_REG_IR 28 /* 0x64 */
204#define IR(pState) (HDA_REG(pState, IR))
205#define ICH6_HDA_REG_IRS 29 /* 0x68 */
206#define ICH6_HDA_IRS_ICB_SHIFT (0)
207#define ICH6_HDA_IRS_IRV_SHIFT (1)
208#define IRS(pState) (HDA_REG(pState, IRS))
209#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
210#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
211
212#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
213#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
214#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
215#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
216
217#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
218#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
219
220#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
221#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
222#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
223#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
224#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
225#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
226#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
227#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
228
229#define SD(func, num) SD##num##func
230#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
231#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
232#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
233#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
234#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
235#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
236#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
237#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
238#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
239
240#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
241#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
242#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
243#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
244#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
245#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
246#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
247#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
248
249#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
250#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
251#define ICH6_HDA_SDSTS_DE_SHIFT (4)
252#define ICH6_HDA_SDSTS_FE_SHIFT (3)
253#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
254
255#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
256#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
257#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
258#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
259#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
260#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
261#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
262#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
263
264#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
265
266#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
267#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
268#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
269#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
270#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
271#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
272#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
273#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
274
275#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
276
277#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
278#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
279#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
280#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
281#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
282#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
283#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
284#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
285
286#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
287
288#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
289#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
290#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
291#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
292#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
293#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
294#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
295#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
296
297#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
298#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
299#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
300#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
301#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
302#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
303#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
304#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
305
306#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
307
308#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
309#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
310#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
311#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
312#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
313#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
314#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
315#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
316
317#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
318#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
319#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
320#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
321#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
322#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
323#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
324#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
325
326#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
327
328#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
329#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
330#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
331#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
332#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
333#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
334#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
335#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
336
337#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
338
339/* Predicates */
340
341
342typedef struct INTELHDLinkState
343{
344 /** Pointer to the device instance. */
345 PPDMDEVINSR3 pDevIns;
346 /** Pointer to the connector of the attached audio driver. */
347 PPDMIAUDIOCONNECTOR pDrv;
348 /** Pointer to the attached audio driver. */
349 PPDMIBASE pDrvBase;
350 /** The base interface for LUN\#0. */
351 PDMIBASE IBase;
352 RTGCPHYS addrMMReg;
353 uint32_t au32Regs[113];
354 /* Current BD index */
355 uint32_t u32Cvi;
356 uint64_t u64CviAddr;
357 /* Length of current BD entry */
358 uint32_t u32CviLen;
359 uint32_t u32CviPos;
360 uint32_t u32Cbp;
361 /* Interrupt on completition */
362 bool fCviIoc;
363 uint64_t u64CORBBase;
364 uint64_t u64RIRBBase;
365 uint64_t u64DPBase;
366 uint8_t u8CORBRP;
367 /* pointer on CORB buf */
368 uint32_t *pu32CorbBuf;
369 /* size in bytes of CORB buf */
370 uint32_t cbCorbBuf;
371 /* size in double words of CORB buf */
372 uint8_t cdwCorbBuf;
373 /* pointer on RIRB buf */
374 uint64_t *pu64RirbBuf;
375 /* size in bytes of RIRB buf */
376 uint32_t cbRirbBuf;
377 /* size in quad words of RIRB buf */
378 uint8_t cdqRirbBuf;
379 /* indicates if HDA in reset. */
380 bool fInReset;
381 CODECState Codec;
382 uint8_t u8Counter;
383 uint8_t u8StreamsInReset;
384} INTELHDLinkState;
385
386#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
387#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
388
389
390
391
392typedef struct PCIINTELHDLinkState
393{
394 PCIDevice dev;
395 INTELHDLinkState hda;
396} PCIINTELHDLinkState;
397
398DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
399DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
400DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
401DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
402DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
403DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
404DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
405DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
406DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
407DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
408DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
409DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
410DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
411DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
412DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
413DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
414DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
415DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
416
417DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
418DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
419DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
420DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
421DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
422DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
423DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
424DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
425DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
426DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
427DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
428DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
429DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
430static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
431static void fetch_bd(INTELHDLinkState *pState);
432
433/* see 302349 p 6.2*/
434const static struct stIchIntelHDRegMap
435{
436 /** Register offset in the register space. */
437 uint32_t offset;
438 /** Size in bytes. Registers of size > 4 are in fact tables. */
439 uint32_t size;
440 /** Readable bits. */
441 uint32_t readable;
442 /** Writable bits. */
443 uint32_t writable;
444 /** Read callback. */
445 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
446 /** Write callback. */
447 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
448 /** Abbreviated name. */
449 const char *abbrev;
450 /** Full name. */
451 const char *name;
452} s_ichIntelHDRegMap[] =
453{
454 /* offset size read mask write mask read callback write callback abbrev full name */
455 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
456 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
457 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
458 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
459 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
460 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
461 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
462 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
463 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
464 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
465 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
466 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
467 //** @todo r=michaln: Are guests really not reading the WALCLK register at all?
468 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
469 //** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
470 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
471 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
472 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
473 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
474 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
475 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
476 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
477 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
478 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
479 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
480 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
481 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
482 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
483 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
484 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
485 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
486 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
487 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadU16 , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
488 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
489 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
490
491 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
492 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
493 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
494 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
495 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
496 { 0x0008E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOW", "ISD0 FIFO Watermark" },
497 { 0x00090, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
498 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FMT" , "ISD0 Format" },
499 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
500 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
501
502 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
503 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
504 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
505 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
506 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
507 { 0x000AE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOW", "ISD1 FIFO Watermark" },
508 { 0x000B0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
509 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FMT" , "ISD1 Format" },
510 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
511 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
512
513 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
514 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
515 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
516 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
517 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
518 { 0x000CE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOW", "ISD2 FIFO Watermark" },
519 { 0x000D0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
520 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FMT" , "ISD2 Format" },
521 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
522 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
523
524 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
525 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
526 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
527 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
528 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
529 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
530 { 0x000F0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
531 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FMT" , "ISD3 Format" },
532 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
533 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
534
535 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
536 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
537 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
538 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
539 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
540 { 0x0010E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOW", "OSD0 FIFO Watermark" },
541 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOS", "OSD0 FIFO Size" },
542 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FMT" , "OSD0 Format" },
543 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
544 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
545
546 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
547 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
548 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
549 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
550 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
551 { 0x0012E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOW", "OSD1 FIFO Watermark" },
552 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOS", "OSD1 FIFO Size" },
553 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FMT" , "OSD1 Format" },
554 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
555 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
556
557 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
558 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
559 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
560 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
561 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
562 { 0x0014E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOW", "OSD2 FIFO Watermark" },
563 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOS", "OSD2 FIFO Size" },
564 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FMT" , "OSD2 Format" },
565 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
566 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
567
568 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
569 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
570 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
571 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
572 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
573 { 0x0016E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOW", "OSD3 FIFO Watermark" },
574 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOS", "OSD3 FIFO Size" },
575 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FMT" , "OSD3 Format" },
576 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
577 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
578};
579
580static int hdaProcessInterrupt(INTELHDLinkState* pState)
581{
582 bool fIrq = false;
583 if( INTCTL_CIE(pState)
584 && ( RIRBSTS_RINTFL(pState)
585 || RIRBSTS_RIRBOIS(pState)
586 || STATESTS(pState)))
587 {
588 fIrq = true;
589 }
590 if ( INTCTL_SX(pState, 4)
591 && SDSTS(pState, 4) && HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))
592 {
593 fIrq = true;
594 }
595 if (INTCTL_GIE(pState))
596 {
597 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
598 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
599 }
600 return VINF_SUCCESS;
601}
602
603static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
604{
605 int index = 0;
606 //** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
607 for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
608 {
609 if ( u32Offset >= s_ichIntelHDRegMap[index].offset
610 && u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
611 {
612 return index;
613 }
614 }
615 /* Aliases HDA spec 3.3.45 */
616 switch(u32Offset)
617 {
618 case 0x2084:
619 return HDA_REG_IND_NAME(SD0LPIB);
620 case 0x20A4:
621 return HDA_REG_IND_NAME(SD1LPIB);
622 case 0x20C4:
623 return HDA_REG_IND_NAME(SD2LPIB);
624 case 0x20E4:
625 return HDA_REG_IND_NAME(SD3LPIB);
626 case 0x2104:
627 return HDA_REG_IND_NAME(SD4LPIB);
628 case 0x2124:
629 return HDA_REG_IND_NAME(SD5LPIB);
630 case 0x2144:
631 return HDA_REG_IND_NAME(SD6LPIB);
632 case 0x2164:
633 return HDA_REG_IND_NAME(SD7LPIB);
634 }
635 return -1;
636}
637
638static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
639{
640 int rc = VINF_SUCCESS;
641 if (fLocal)
642 {
643 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
644 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
645 if (RT_FAILURE(rc))
646 AssertRCReturn(rc, rc);
647 uint8_t i = 0;
648 do
649 {
650 Log(("hda: corb%02x: ", i));
651 uint8_t j = 0;
652 do
653 {
654 const char *prefix;
655 if ((i + j) == CORBRP(pState))
656 prefix = "[R]";
657 else if ((i + j) == CORBWP(pState))
658 prefix = "[W]";
659 else
660 prefix = " "; /* three spaces */
661 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
662 j++;
663 } while (j < 8);
664 Log(("\n"));
665 i += 8;
666 } while(i != 0);
667 }
668 else
669 {
670 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
671 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
672 if (RT_FAILURE(rc))
673 AssertRCReturn(rc, rc);
674 uint8_t i = 0;
675 do {
676 Log(("hda: rirb%02x: ", i));
677 uint8_t j = 0;
678 do {
679 const char *prefix;
680 if ((i + j) == RIRBWP(pState))
681 prefix = "[W]";
682 else
683 prefix = " ";
684 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
685 } while (++j < 8);
686 Log(("\n"));
687 i += 8;
688 } while (i != 0);
689 }
690 return rc;
691}
692
693#if 0
694static int hdaUnsolictedResponse(INTELHDLinkState *pState, uint64_t pu64UnsolictedResponse)
695{
696 uint8_t rirbWp;
697 if (!HDA_REG_FLAG_VALUE(pState, GCTL, UR))
698 {
699 Log(("hda: unsolicited response %016lx is ignored\n"));
700 return VINF_SUCCESS;
701 }
702}
703#endif
704
705static int hdaCORBCmdProcess(INTELHDLinkState *pState)
706{
707 int rc;
708 uint8_t corbRp;
709 uint8_t corbWp;
710 uint8_t rirbWp;
711
712 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
713
714 rc = hdaCmdSync(pState, true);
715 if (RT_FAILURE(rc))
716 AssertRCReturn(rc, rc);
717 corbRp = CORBRP(pState);
718 corbWp = CORBWP(pState);
719 rirbWp = RIRBWP(pState);
720 Assert((corbWp != corbRp));
721 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
722 while (corbRp != corbWp)
723 {
724 uint32_t cmd;
725 uint64_t resp;
726 corbRp++;
727 cmd = pState->pu32CorbBuf[corbRp];
728 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
729 if (RT_FAILURE(rc))
730 AssertRCReturn(rc, rc);
731 Assert(pfn);
732 (rirbWp)++;
733 rc = pfn(&pState->Codec, cmd, &resp);
734 if (RT_FAILURE(rc))
735 AssertRCReturn(rc, rc);
736 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
737 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
738 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
739 {
740 Log(("hda: unexpected unsolicited response.\n"));
741 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
742 return rc;
743 }
744 pState->pu64RirbBuf[rirbWp] = resp;
745 pState->u8Counter++;
746 if (pState->u8Counter == RINTCNT_N(pState))
747 break;
748 }
749 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
750 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
751 rc = hdaCmdSync(pState, false);
752 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
753 if (RIRBCTL_RIRB_RIC(pState))
754 {
755 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
756 pState->u8Counter = 0;
757 rc = hdaProcessInterrupt(pState);
758 }
759 if (RT_FAILURE(rc))
760 AssertRCReturn(rc, rc);
761 return rc;
762}
763
764static void hdaStreamReset(INTELHDLinkState *pState, uint32_t u32Offset)
765{
766 Log(("hda: reset of stream (%x) started\n", u32Offset));
767 Log(("hda: reset of stream (%x) finished\n", u32Offset));
768}
769
770
771DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
772{
773 *pu32Value = 0;
774 return VINF_SUCCESS;
775}
776DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
777{
778 return VINF_SUCCESS;
779}
780/* U8 */
781DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
782{
783 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
784 return hdaRegReadU32(pState, offset, index, pu32Value);
785}
786
787DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
788{
789 Assert(((u32Value & 0xffffff00) == 0));
790 return hdaRegWriteU32(pState, offset, index, u32Value);
791}
792/* U16 */
793DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
794{
795 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
796 return hdaRegReadU32(pState, offset, index, pu32Value);
797}
798
799DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
800{
801 Assert(((u32Value & 0xffff0000) == 0));
802 return hdaRegWriteU32(pState, offset, index, u32Value);
803}
804
805/* U24 */
806DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
807{
808 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
809 return hdaRegReadU32(pState, offset, index, pu32Value);
810}
811
812DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
813{
814 Assert(((u32Value & 0xff000000) == 0));
815 return hdaRegWriteU32(pState, offset, index, u32Value);
816}
817/* U32 */
818DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
819{
820 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
821 return VINF_SUCCESS;
822}
823
824DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
825{
826 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
827 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
828 return VINF_SUCCESS;
829}
830
831DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
832{
833 return hdaRegReadU32(pState, offset, index, pu32Value);
834}
835
836DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
837{
838 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
839 {
840 /* exit reset state */
841 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
842 pState->fInReset = false;
843 }
844 else
845 {
846 /* enter reset state*/
847 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
848 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
849 {
850 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
851 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
852 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
853 }
854 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
855 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
856 pState->fInReset = true;
857 }
858 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
859 {
860 /* Flush: GSTS:1 set, see 6.2.6*/
861 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
862 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
863 }
864 return VINF_SUCCESS;
865}
866
867DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
868{
869 uint32_t v = pState->au32Regs[index];
870 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
871 pState->au32Regs[index] = (v ^ nv) & v; /* write of 1 clears corresponding bit */
872 return VINF_SUCCESS;
873}
874
875DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
876{
877 uint32_t v = 0;
878 if ( RIRBSTS_RIRBOIS(pState)
879 || RIRBSTS_RINTFL(pState)
880 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
881 || STATESTS(pState))
882 v |= RT_BIT(30);
883#define HDA_IS_STREAM_EVENT(pState, stream) \
884 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
885 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
886 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
887#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
888 MARK_STREAM(pState, 0, v);
889 MARK_STREAM(pState, 1, v);
890 MARK_STREAM(pState, 2, v);
891 MARK_STREAM(pState, 3, v);
892 MARK_STREAM(pState, 4, v);
893 MARK_STREAM(pState, 5, v);
894 MARK_STREAM(pState, 6, v);
895 MARK_STREAM(pState, 7, v);
896 v |= v ? RT_BIT(31) : 0;
897 *pu32Value = v;
898 return VINF_SUCCESS;
899}
900
901DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
902{
903 return hdaRegReadU16(pState, offset, index, pu32Value);
904}
905
906DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
907{
908 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
909 {
910 pState->u8CORBRP = 0;
911 CORBRP(pState) = 0;
912 }
913 else
914 return hdaRegWriteU8(pState, offset, index, u32Value);
915 return VINF_SUCCESS;
916}
917
918DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
919{
920 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
921 AssertRC(rc);
922 if ( CORBWP(pState) != CORBRP(pState)
923 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
924 return hdaCORBCmdProcess(pState);
925 return rc;
926}
927
928DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
929{
930 uint32_t v = CORBSTS(pState);
931 v = (v ^ u32Value) & v;
932 CORBSTS(pState) = v;
933 return VINF_SUCCESS;
934}
935
936DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
937{
938 int rc;
939 rc = hdaRegWriteU16(pState, offset, index, u32Value);
940 if (RT_FAILURE(rc))
941 AssertRCReturn(rc, rc);
942 if (CORBWP(pState) == CORBRP(pState))
943 return VINF_SUCCESS;
944 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
945 return VINF_SUCCESS;
946 rc = hdaCORBCmdProcess(pState);
947 return rc;
948}
949
950DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
951{
952 return hdaRegReadU24(pState, offset, index, pu32Value);
953}
954#define HDA_STREAM_BITMASK(offset) (1 << (((offset) - 0x80) >> 5))
955#define HDA_IS_STREAM_IN_RESET(pState, offset) ((pState)->u8StreamsInReset & HDA_STREAM_BITMASK((offset)))
956DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
957{
958 if(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST))
959 {
960 LogRel(("hda: guest has iniated hw stream reset\n"));
961 pState->u8StreamsInReset |= HDA_STREAM_BITMASK(offset);
962 hdaStreamReset(pState, offset);
963 HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
964 }
965 else if (HDA_IS_STREAM_IN_RESET(pState, offset))
966 {
967 LogRel(("hda: guest has iniated exit of stream reset\n"));
968 pState->u8StreamsInReset &= ~HDA_STREAM_BITMASK(offset);
969 HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
970 }
971 /* @todo: use right offsets for right streams */
972 if (u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
973 {
974 Log(("hda: DMA(%x) switched on\n", offset));
975 AUD_set_active_in(pState->Codec.voice_pi, 1);
976 AUD_set_active_in(pState->Codec.voice_mc, 1);
977 if (offset == 0x100)
978 {
979 fetch_bd(pState);
980 AUD_set_active_out(pState->Codec.voice_po, 1);
981 //SDSTS(pState, 4) |= (1<<5);
982 }
983 }
984 else
985 {
986 Log(("hda: DMA(%x) switched off\n", offset));
987 AUD_set_active_in(pState->Codec.voice_pi, 0);
988 AUD_set_active_in(pState->Codec.voice_mc, 0);
989 if (offset == 0x100)
990 {
991 SDSTS(pState, 4) &= ~(1<<5);
992 AUD_set_active_out(pState->Codec.voice_po, 0);
993 }
994 //SSYNC(pState) &= ~(1<< (offset - 0x80));
995 }
996 int rc = hdaRegWriteU24(pState, offset, index, u32Value);
997 if (RT_FAILURE(rc))
998 AssertRCReturn(rc, VINF_SUCCESS);
999 return rc;
1000}
1001
1002DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1003{
1004 uint32_t v = HDA_REG_IND(pState, index);
1005 v ^= (u32Value & v);
1006 HDA_REG_IND(pState, index) = v;
1007 hdaProcessInterrupt(pState);
1008#if 0
1009 if ( v != u32Value
1010 && (INTCTL_SALL(pState) & (1 << ((offset - 0x83) >> 5))))
1011 {
1012 int rc;
1013 rc = hdaProcessInterrupt(pState);
1014 if (RT_FAILURE(rc))
1015 AssertRCReturn(rc, rc);
1016 }
1017#endif
1018 return VINF_SUCCESS;
1019}
1020DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1021{
1022 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1023 if (RT_FAILURE(rc))
1024 AssertRCReturn(rc, VINF_SUCCESS);
1025 return rc;
1026}
1027
1028DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1029{
1030 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1031 if (RT_FAILURE(rc))
1032 AssertRCReturn(rc, VINF_SUCCESS);
1033 return rc;
1034}
1035
1036DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1037{
1038 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1039 if (RT_FAILURE(rc))
1040 AssertRCReturn(rc, VINF_SUCCESS);
1041 return rc;
1042}
1043
1044DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1045{
1046 int rc = VINF_SUCCESS;
1047 uint64_t resp;
1048 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1049 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1050 && !IRS_ICB(pState))
1051 {
1052 uint32_t cmd = IC(pState);
1053 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1054 Log(("hda: IC:%x\n", cmd));
1055 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1056 if (RT_FAILURE(rc))
1057 AssertRCReturn(rc, rc);
1058 rc = pfn(&pState->Codec, cmd, &resp);
1059 if (RT_FAILURE(rc))
1060 AssertRCReturn(rc, rc);
1061 IR(pState) = (uint32_t)resp;
1062 Log(("hda: IR:%x\n", IR(pState)));
1063 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* clear busy, result is ready */
1064 return rc;
1065 }
1066 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1067 && IRS_IRV(pState))
1068 IRS(pState) ^= HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1069 return rc;
1070}
1071
1072DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1073{
1074 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1075 {
1076 RIRBWP(pState) = 0;
1077 }
1078 /*The rest of bits are O, see 6.2.22 */
1079 return VINF_SUCCESS;
1080}
1081
1082DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1083{
1084 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1085 if (RT_FAILURE(rc))
1086 AssertRCReturn(rc, rc);
1087 switch(index)
1088 {
1089 case ICH6_HDA_REG_CORBLBASE:
1090 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1091 pState->u64CORBBase |= pState->au32Regs[index];
1092 break;
1093 case ICH6_HDA_REG_CORBUBASE:
1094 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1095 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1096 break;
1097 case ICH6_HDA_REG_RIRLBASE:
1098 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1099 pState->u64RIRBBase |= pState->au32Regs[index];
1100 break;
1101 case ICH6_HDA_REG_RIRUBASE:
1102 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1103 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1104 break;
1105 case ICH6_HDA_REG_DPLBASE:
1106 /* @todo: first bit has special meaning */
1107 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1108 pState->u64DPBase |= pState->au32Regs[index];
1109 break;
1110 case ICH6_HDA_REG_DPUBASE:
1111 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1112 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1113 break;
1114 default:
1115 AssertMsgFailed(("Invalid index"));
1116 }
1117 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1118 return rc;
1119}
1120
1121DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1122{
1123 uint8_t nv = u32Value;
1124 uint8_t v = RIRBSTS(pState);
1125 RIRBSTS(pState) = (v ^ nv) & v;
1126
1127 return hdaProcessInterrupt(pState);
1128}
1129
1130static void dump_bd(INTELHDLinkState *pState)
1131{
1132 uint64_t addr;
1133 uint32_t len;
1134 uint32_t ioc;
1135 uint8_t bdle[16];
1136 uint32_t counter;
1137 uint32_t i;
1138 uint32_t sum = 0;
1139 for (i = 0; i <= SDLVI(pState, 4); ++i)
1140 {
1141 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), SDBDPL(pState, 4) + i*16, bdle, 16);
1142 addr = *(uint64_t *)bdle;
1143 len = *(uint32_t *)&bdle[8];
1144 ioc = *(uint32_t *)&bdle[12];
1145 Log(("hda: %s bdle[%d] a:%x, len:%x, ios:%d\n", (i == pState->u32Cvi? "[C]": " "), i, addr, len, ioc));
1146 sum += len;
1147 }
1148 Log(("hda: sum: %d\n", sum));
1149 for (i = 0; i < 8; ++i)
1150 {
1151 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64DPBase + i*8, &counter, 4);
1152 Log(("hda: %s stream[%d] counter=%x\n", (i) == SDCTL_NUM(pState, 4)? "[C]": " ", i , counter));
1153 }
1154}
1155static void fetch_bd(INTELHDLinkState *pState)
1156{
1157 dump_bd(pState);
1158 uint8_t bdle[16];
1159 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), SDBDPL(pState, 4) + pState->u32Cvi*16, bdle, 16);
1160 pState->u64CviAddr = *(uint64_t *)bdle;
1161 pState->u32CviLen = *(uint32_t *)&bdle[8];
1162 pState->fCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1163}
1164
1165static uint32_t write_audio(INTELHDLinkState *pState, int avail, bool *fStop)
1166{
1167 uint8_t tmpbuf[4096];
1168 uint32_t temp;
1169 uint32_t u32Rest;
1170 uint32_t written = 0;
1171 int to_copy = 0;
1172 u32Rest = pState->u32CviLen - pState->u32CviPos;
1173 temp = audio_MIN(u32Rest, (uint32_t)avail);
1174 if (!temp)
1175 {
1176 *fStop = true;
1177 return written;
1178 }
1179 while (temp)
1180 {
1181 int copied;
1182 to_copy = audio_MIN(temp, 4096U);
1183 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CviAddr + pState->u32CviPos, tmpbuf, to_copy);
1184 copied = AUD_write (pState->Codec.voice_po, tmpbuf, to_copy);
1185 Log (("hda: write_audio max=%x to_copy=%x copied=%x\n",
1186 avail, to_copy, copied));
1187 Assert((copied));
1188 if (!copied)
1189 {
1190 *fStop = true;
1191 break;
1192 }
1193 temp -= copied;
1194 written += copied;
1195 pState->u32CviPos += copied;
1196 }
1197 return written;
1198}
1199
1200DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1201{
1202 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1203 return VINF_SUCCESS;
1204}
1205
1206DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1207{
1208 bool fStop = false;
1209 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1210 switch(src)
1211 {
1212 case PO_INDEX:
1213 {
1214 uint32_t written;
1215 uint32_t u32Counter;
1216 if ( !(SDCTL(pState, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1217 || avail == 0)
1218 return;
1219 SDCTL(pState, 4) |= ((pState->Codec.pNodes[2].dac.u32F06_param & (0xf << 4)) >> 4) << 20;
1220 //fetch_bd(pState);
1221 while( avail
1222 && !fStop)
1223 {
1224 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + 4*8, &u32Counter, 4);
1225 written = write_audio(pState, avail, &fStop);
1226 if ( fStop
1227 && pState->u32CviLen != pState->u32CviPos)
1228 break;
1229 SDLPIB(pState, 4) += written; /* bytes ? */
1230 avail -= written;
1231 u32Counter += written;
1232 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + 4*8, &u32Counter, 4);
1233 if ( pState->u32CviPos == pState->u32CviLen
1234 || SDLPIB(pState, 4) == SDLCBL(pState, 4))
1235 {
1236 if ( SDCTL(pState, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)
1237 && ( ( pState->u32CviPos == pState->u32CviLen
1238 && pState->fCviIoc )
1239 || SDLPIB(pState, 4) == SDLCBL(pState, 4)))
1240 {
1241 SDSTS(pState,4) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1242 hdaProcessInterrupt(pState);
1243 if (SDLPIB(pState, 4) == SDLCBL(pState, 4))
1244 {
1245 SDLPIB(pState, 4) = 0;
1246 u32Counter = 0;
1247 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + 4*8, &u32Counter, 4);
1248 }
1249 }
1250 if (pState->u32CviPos == pState->u32CviLen)
1251 {
1252 pState->u32CviPos = 0;
1253 pState->u32Cvi++;
1254 if (pState->u32Cvi == SDLVI(pState, 4) + 1)
1255 pState->u32Cvi = 0;
1256 }
1257 fStop = false;
1258 fetch_bd(pState);
1259 }
1260 }
1261 }
1262 break;
1263 AssertMsgFailed(("Unexpected index: %x\n", src));
1264 default:
1265 break;
1266 }
1267}
1268
1269/**
1270 * Handle register read operation.
1271 *
1272 * Looks up and calls appropriate handler.
1273 *
1274 * @note: while implementation was detected so called "forgotten" or "hole" registers
1275 * which description is missed in RPM, datasheet or spec.
1276 *
1277 * @returns VBox status code.
1278 *
1279 * @param pState The device state structure.
1280 * @param uOffset Register offset in memory-mapped frame.
1281 * @param pv Where to fetch the value.
1282 * @param cb Number of bytes to write.
1283 * @thread EMT
1284 */
1285PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1286{
1287 int rc = VINF_SUCCESS;
1288 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1289 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1290 int index = hdaLookup(&pThis->hda, u32Offset);
1291 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1292 {
1293 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1294 }
1295 Assert( index != -1
1296 && cb <= 4);
1297 if (index != -1)
1298 {
1299 uint32_t mask = 0;
1300 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1301 uint32_t v = 0;
1302 switch(cb)
1303 {
1304 case 1: mask = 0x000000ff; break;
1305 case 2: mask = 0x0000ffff; break;
1306 case 3: mask = 0x00ffffff; break;
1307 case 4: mask = 0xffffffff; break;
1308 }
1309 mask <<= shift;
1310 rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1311 *(uint32_t *)pv = (v & mask) >> shift;
1312 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
1313 return rc;
1314 }
1315 *(uint32_t *)pv = 0xFF;
1316 Log(("hda: hole at %X is accessed for read\n", u32Offset));
1317 return rc;
1318}
1319
1320/**
1321 * Handle register write operation.
1322 *
1323 * Looks up and calls appropriate handler.
1324 *
1325 * @returns VBox status code.
1326 *
1327 * @param pState The device state structure.
1328 * @param uOffset Register offset in memory-mapped frame.
1329 * @param pv Where to fetch the value.
1330 * @param cb Number of bytes to write.
1331 * @thread EMT
1332 */
1333PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1334{
1335 int rc = VINF_SUCCESS;
1336 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1337 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1338 int index = hdaLookup(&pThis->hda, u32Offset);
1339 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1340 {
1341 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1342 }
1343 Assert( index != -1
1344 && cb <= 4);
1345 if (index != -1)
1346 {
1347 uint32_t v = pThis->hda.au32Regs[index];
1348 uint32_t mask = 0;
1349 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1350 switch(cb)
1351 {
1352 case 1: mask = 0xffffff00; break;
1353 case 2: mask = 0xffff0000; break;
1354 case 3: mask = 0xff000000; break;
1355 case 4: mask = 0x00000000; break;
1356 }
1357 mask <<= shift;
1358 *(uint32_t *)pv = ((v & mask) | (*(uint32_t *)pv & ~mask)) >> shift;
1359 rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
1360 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
1361 return rc;
1362 }
1363 Log(("hda: hole at %X is accessed for write\n", u32Offset));
1364 return rc;
1365}
1366
1367/**
1368 * Callback function for mapping a PCI I/O region.
1369 *
1370 * @return VBox status code.
1371 * @param pPciDev Pointer to PCI device.
1372 * Use pPciDev->pDevIns to get the device instance.
1373 * @param iRegion The region number.
1374 * @param GCPhysAddress Physical address of the region.
1375 * If iType is PCI_ADDRESS_SPACE_IO, this is an
1376 * I/O port, else it's a physical address.
1377 * This address is *NOT* relative
1378 * to pci_mem_base like earlier!
1379 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
1380 */
1381static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
1382 RTGCPHYS GCPhysAddress, uint32_t cb,
1383 PCIADDRESSSPACE enmType)
1384{
1385 int rc;
1386 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1387 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1388 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1389
1390 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1391 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
1392 hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
1393
1394 if (RT_FAILURE(rc))
1395 return rc;
1396
1397 pThis->hda.addrMMReg = GCPhysAddress;
1398 return VINF_SUCCESS;
1399}
1400
1401
1402/**
1403 * Reset notification.
1404 *
1405 * @returns VBox status.
1406 * @param pDevIns The device instance data.
1407 *
1408 * @remark The original sources didn't install a reset handler, but it seems to
1409 * make sense to me so we'll do it.
1410 */
1411static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns)
1412{
1413 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1414 GCAP(&pThis->hda) = 0x4401; /* see 6.2.1 */
1415 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
1416 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1417 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1418 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
1419 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
1420 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
1421 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
1422 CORBRP(&pThis->hda) = 0x0;
1423 RIRBWP(&pThis->hda) = 0x0;
1424
1425 LogRel(("hda: inter HDA reset.\n"));
1426 //** @todo r=michaln: There should be LogRel statements when the guest initializes
1427 // or resets the HDA chip, and possibly also when opening the PCM streams.
1428 pThis->hda.cdwCorbBuf = CORBSIZE(&pThis->hda);
1429 pThis->hda.cbCorbBuf = CORBSIZE(&pThis->hda) * sizeof(uint32_t);
1430
1431 if (pThis->hda.pu32CorbBuf)
1432 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
1433 else
1434 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
1435
1436 pThis->hda.cdqRirbBuf = RIRBSIZE(&pThis->hda);
1437 pThis->hda.cbRirbBuf = RIRBSIZE(&pThis->hda) * sizeof(uint64_t);
1438 if (pThis->hda.pu64RirbBuf)
1439 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
1440 else
1441 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
1442
1443 /* Accoding to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
1444 * bits are reserved for stream number 18.2.33 */
1445 SDCTL(&pThis->hda, 0) = 0x40000;
1446 SDCTL(&pThis->hda, 1) = 0x40000;
1447 SDCTL(&pThis->hda, 2) = 0x40000;
1448 SDCTL(&pThis->hda, 3) = 0x40000;
1449 SDCTL(&pThis->hda, 4) = 0x40000;
1450 SDCTL(&pThis->hda, 5) = 0x40000;
1451 SDCTL(&pThis->hda, 6) = 0x40000;
1452 SDCTL(&pThis->hda, 7) = 0x40000;
1453
1454 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1455 SDFIFOS(&pThis->hda, 0) = 0x77;
1456 SDFIFOS(&pThis->hda, 1) = 0x77;
1457 SDFIFOS(&pThis->hda, 2) = 0x77;
1458 SDFIFOS(&pThis->hda, 3) = 0x77;
1459 SDFIFOS(&pThis->hda, 4) = 0xBF;
1460 SDFIFOS(&pThis->hda, 5) = 0xBF;
1461 SDFIFOS(&pThis->hda, 6) = 0xBF;
1462 SDFIFOS(&pThis->hda, 7) = 0xBF;
1463
1464 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
1465 STATESTS(&pThis->hda) = 0x1;
1466
1467 Log(("hda: reset finished\n"));
1468}
1469
1470/**
1471 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1472 */
1473static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
1474 const char *pszIID)
1475{
1476 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
1477 Assert(&pThis->hda.IBase == pInterface);
1478
1479 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
1480 return NULL;
1481}
1482
1483/**
1484 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1485 */
1486static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
1487 PCFGMNODE pCfgHandle)
1488{
1489 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1490 INTELHDLinkState *s = &pThis->hda;
1491 int rc;
1492
1493 Assert(iInstance == 0);
1494 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1495
1496 /*
1497 * Validations.
1498 */
1499 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
1500 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1501 N_ ("Invalid configuration for the INTELHD device"));
1502
1503 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
1504 // poll some register(s).
1505
1506 /*
1507 * Initialize data (most of it anyway).
1508 */
1509 s->pDevIns = pDevIns;
1510 /* IBase */
1511 s->IBase.pfnQueryInterface = hdaQueryInterface;
1512
1513 /* PCI Device (the assertions will be removed later) */
1514 PCIDevSetVendorId (&pThis->dev, 0x8086); /* 00 ro - intel. */
1515 PCIDevSetDeviceId (&pThis->dev, 0x2668); /* 02 ro - 82801 / 82801aa(?). */
1516 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
1517 PCIDevSetStatus (&pThis->dev, 0x0010); /* 06 rwc?,ro? - pcists. */
1518 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
1519 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
1520 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
1521 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
1522 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
1523 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
1524 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
1525 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
1526 verb F20 should provide device/codec recognition. */
1527 PCIDevSetSubSystemVendorId (&pThis->dev, 0x0000); /* 2c ro - intel.) */
1528 PCIDevSetSubSystemId (&pThis->dev, 0x0000); /* 2e ro. */
1529 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
1530 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */ Assert (pThis->dev.config[0x3d] == 0x01);
1531 PCIDevSetCapabilityList(&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
1532
1533 //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
1534 // of these values needs to be properly documented!
1535 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1536 pThis->dev.config[0x40] = 0x01;
1537
1538 pThis->dev.config[0x50] = 0x01;
1539 pThis->dev.config[0x51] = 0x60; /* next */
1540 pThis->dev.config[0x52] = 0x22;
1541 pThis->dev.config[0x53] = 0x00; /* PM - disabled, */
1542
1543#if 0
1544 pThis->dev.config[0x60] = 0x05;
1545 pThis->dev.config[0x61] = 0x70; /* next */
1546 pThis->dev.config[0x62] = 0x00;
1547 pThis->dev.config[0x63] = 0x80;
1548#endif
1549
1550 /*
1551 * Register the PCI device.
1552 */
1553 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
1554 if (RT_FAILURE (rc))
1555 return rc;
1556
1557 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
1558 hdaMap);
1559 if (RT_FAILURE (rc))
1560 return rc;
1561
1562 /*
1563 * Attach driver.
1564 */
1565 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
1566 &s->pDrvBase, "Audio Driver Port");
1567 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1568 Log (("hda: No attached driver!\n"));
1569 else if (RT_FAILURE (rc))
1570 {
1571 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
1572 return rc;
1573 }
1574
1575
1576
1577 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
1578 rc = stac9220Construct(&pThis->hda.Codec);
1579 if (RT_FAILURE(rc))
1580 AssertRCReturn(rc, rc);
1581 hdaReset (pDevIns);
1582 pThis->hda.Codec.id = 0;
1583 pThis->hda.Codec.pfnTransfer = hdaTransfer;
1584 pThis->hda.Codec.pfnReset = hdaCodecReset;
1585 /*
1586 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
1587 * hdaReset shouldn't affects these registers.
1588 */
1589 WAKEEN(&pThis->hda) = 0x0;
1590 STATESTS(&pThis->hda) = 0x0;
1591
1592 return VINF_SUCCESS;
1593}
1594
1595/**
1596 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1597 */
1598static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
1599{
1600 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1601
1602 int rc = stac9220Destruct(&pThis->hda.Codec);
1603 AssertRC(rc);
1604 if (pThis->hda.pu32CorbBuf)
1605 RTMemFree(pThis->hda.pu32CorbBuf);
1606 if (pThis->hda.pu64RirbBuf)
1607 RTMemFree(pThis->hda.pu64RirbBuf);
1608 return VINF_SUCCESS;
1609}
1610
1611/**
1612 * The device registration structure.
1613 */
1614const PDMDEVREG g_DeviceICH6_HDA =
1615{
1616 /* u32Version */
1617 PDM_DEVREG_VERSION,
1618 /* szName */
1619 "hda",
1620 /* szRCMod */
1621 "",
1622 /* szR0Mod */
1623 "",
1624 /* pszDescription */
1625 "ICH IntelHD Audio Controller",
1626 /* fFlags */
1627 PDM_DEVREG_FLAGS_DEFAULT_BITS,
1628 /* fClass */
1629 PDM_DEVREG_CLASS_AUDIO,
1630 /* cMaxInstances */
1631 1,
1632 /* cbInstance */
1633 sizeof(PCIINTELHDLinkState),
1634 /* pfnConstruct */
1635 hdaConstruct,
1636 /* pfnDestruct */
1637 hdaDestruct,
1638 /* pfnRelocate */
1639 NULL,
1640 /* pfnIOCtl */
1641 NULL,
1642 /* pfnPowerOn */
1643 NULL,
1644 /* pfnReset */
1645 hdaReset,
1646 /* pfnSuspend */
1647 NULL,
1648 /* pfnResume */
1649 NULL,
1650 /* pfnAttach */
1651 NULL,
1652 /* pfnDetach */
1653 NULL,
1654 /* pfnQueryInterface. */
1655 NULL,
1656 /* pfnInitComplete */
1657 NULL,
1658 /* pfnPowerOff */
1659 NULL,
1660 /* pfnSoftReset */
1661 NULL,
1662 /* u32VersionEnd */
1663 PDM_DEVREG_VERSION
1664};
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