VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 31741

Last change on this file since 31741 was 31741, checked in by vboxsync, 14 years ago

Audio/HDA: corrects capasity of CORB and RIRB.
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  • Property svn:keywords set to Author Date Id Revision
File size: 73.9 KB
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1/* $Id: DevIchIntelHDA.cpp 31741 2010-08-18 02:59:21Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/pdmdev.h>
23#include <iprt/assert.h>
24#include <iprt/uuid.h>
25#include <iprt/string.h>
26#include <iprt/mem.h>
27#include <iprt/asm.h>
28
29#include "../Builtins.h"
30
31extern "C" {
32#include "audio.h"
33}
34#include "DevCodec.h"
35
36#undef LOG_VOICES
37#ifndef VBOX
38//#define USE_MIXER
39#else
40#define USE_MIXER
41#endif
42
43#define INTELHD_SSM_VERSION 1
44PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
45PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
46static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
47
48/* Registers */
49#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
50#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
51#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
52#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
53#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
54#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
55#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
56#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
57#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
58#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
59
60#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
61#define GCAP(pState) (HDA_REG((pState), GCAP))
62
63#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
64#define VMIN(pState) (HDA_REG((pState), VMIN))
65
66#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
67#define VMAJ(pState) (HDA_REG((pState), VMAJ))
68
69#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
70#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
71
72#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
73#define INPAY(pState) (HDA_REG((pState), INPAY))
74
75#define ICH6_HDA_REG_GCTL (5)
76#define ICH6_HDA_GCTL_RST_SHIFT (0)
77#define ICH6_HDA_GCTL_FSH_SHIFT (1)
78#define ICH6_HDA_GCTL_UR_SHIFT (8)
79#define GCTL(pState) (HDA_REG((pState), GCTL))
80
81#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
82#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
83
84#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
85#define STATESTS(pState) (HDA_REG((pState), STATESTS))
86#define ICH6_HDA_STATES_SCSF 0x7
87
88#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
89#define ICH6_HDA_GSTS_FSH_SHIFT (1)
90#define GSTS(pState) (HDA_REG(pState, GSTS))
91
92#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
93#define ICH6_HDA_INTCTL_GIE_SHIFT 31
94#define ICH6_HDA_INTCTL_CIE_SHIFT 30
95#define ICH6_HDA_INTCTL_S0_SHIFT (0)
96#define ICH6_HDA_INTCTL_S1_SHIFT (1)
97#define ICH6_HDA_INTCTL_S2_SHIFT (2)
98#define ICH6_HDA_INTCTL_S3_SHIFT (3)
99#define ICH6_HDA_INTCTL_S4_SHIFT (4)
100#define ICH6_HDA_INTCTL_S5_SHIFT (5)
101#define ICH6_HDA_INTCTL_S6_SHIFT (6)
102#define ICH6_HDA_INTCTL_S7_SHIFT (7)
103#define INTCTL(pState) (HDA_REG((pState), INTCTL))
104#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
105#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
106#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
107#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
108
109/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
110 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
111 * the datasheet.
112 */
113#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
114#define SSYNC(pState) (HDA_REG((pState), SSYNC))
115
116#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
117#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
118#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
119#define ICH6_HDA_INTSTS_S0_SHIFT (0)
120#define ICH6_HDA_INTSTS_S1_SHIFT (1)
121#define ICH6_HDA_INTSTS_S2_SHIFT (2)
122#define ICH6_HDA_INTSTS_S3_SHIFT (3)
123#define ICH6_HDA_INTSTS_S4_SHIFT (4)
124#define ICH6_HDA_INTSTS_S5_SHIFT (5)
125#define ICH6_HDA_INTSTS_S6_SHIFT (6)
126#define ICH6_HDA_INTSTS_S7_SHIFT (7)
127#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
128#define INTSTS(pState) (HDA_REG((pState), INTSTS))
129#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
130#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
131#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
132#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
133
134#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
135#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
136#define ICH6_HDA_REG_CORBWP 15 /* 48 */
137#define ICH6_HDA_REG_CORBRP 16 /* 4A */
138#define ICH6_HDA_CORBRP_RST_SHIFT 15
139#define ICH6_HDA_CORBRP_WP_SHIFT 0
140#define ICH6_HDA_CORBRP_WP_MASK 0xFF
141
142#define CORBRP(pState) (HDA_REG(pState, CORBRP))
143#define CORBWP(pState) (HDA_REG(pState, CORBWP))
144
145#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
146#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
147#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
148
149#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
150
151
152#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
153#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
154#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
155
156#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
157#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
158#define ICH6_HDA_CORBSIZE_SZ 0x3
159#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
160#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
161/* till ich 10 sizes of CORB and RIRB are harcoded to 256 in real hw */
162
163#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
164#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
165
166#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
167#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
168#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
169#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
170
171#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
172#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
173#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
174
175#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
176#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
177#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
178#define ICH6_HDA_ROI_DMA_SHIFT (2)
179#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
180#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
181#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
182#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
183
184#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
185#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
186#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
187#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
188#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
189#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
190
191#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
192#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
193#define ICH6_HDA_RIRBSIZE_SZ 0x3
194
195#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
196#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
197
198
199#define ICH6_HDA_REG_IC 27 /* 0x60 */
200#define IC(pState) (HDA_REG(pState, IC))
201#define ICH6_HDA_REG_IR 28 /* 0x64 */
202#define IR(pState) (HDA_REG(pState, IR))
203#define ICH6_HDA_REG_IRS 29 /* 0x68 */
204#define ICH6_HDA_IRS_ICB_SHIFT (0)
205#define ICH6_HDA_IRS_IRV_SHIFT (1)
206#define IRS(pState) (HDA_REG(pState, IRS))
207#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
208#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
209
210#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
211#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
212#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
213#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
214
215#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
216#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
217
218#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
219#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
220#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
221#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
222#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
223#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
224#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
225#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
226
227#define SD(func, num) SD##num##func
228#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
229#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
230#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
231#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
232#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
233#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
234#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
235#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
236#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
237
238#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
239#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
240#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
241#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
242#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
243#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
244#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
245#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
246
247#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
248#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
249#define ICH6_HDA_SDSTS_DE_SHIFT (4)
250#define ICH6_HDA_SDSTS_FE_SHIFT (3)
251#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
252
253#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
254#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
255#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
256#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
257#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
258#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
259#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
260#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
261
262#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
263
264#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
265#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
266#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
267#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
268#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
269#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
270#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
271#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
272
273#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
274
275#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
276#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
277#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
278#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
279#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
280#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
281#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
282#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
283
284#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
285
286#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
287#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
288#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
289#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
290#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
291#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
292#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
293#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
294
295#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
296#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
297#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
298#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
299#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
300#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
301#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
302#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
303
304#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
305
306#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
307#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
308#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
309#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
310#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
311#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
312#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
313#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
314
315#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
316#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
317#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
318#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
319#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
320#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
321#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
322#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
323
324#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
325
326#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
327#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
328#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
329#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
330#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
331#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
332#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
333#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
334
335#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
336
337/* Predicates */
338
339
340typedef struct INTELHDLinkState
341{
342 /** Pointer to the device instance. */
343 PPDMDEVINSR3 pDevIns;
344 /** Pointer to the connector of the attached audio driver. */
345 PPDMIAUDIOCONNECTOR pDrv;
346 /** Pointer to the attached audio driver. */
347 PPDMIBASE pDrvBase;
348 /** The base interface for LUN\#0. */
349 PDMIBASE IBase;
350 RTGCPHYS addrMMReg;
351 uint32_t au32Regs[113];
352 /* Current BD index */
353 uint32_t u32Cvi;
354 uint64_t u64CviAddr;
355 /* Length of current BD entry */
356 uint32_t u32CviLen;
357 uint32_t u32CviPos;
358 uint32_t u32Cbp;
359 /* Interrupt on completition */
360 bool fCviIoc;
361 uint64_t u64CORBBase;
362 uint64_t u64RIRBBase;
363 uint64_t u64DPBase;
364 uint8_t u8CORBRP;
365 /* pointer on CORB buf */
366 uint32_t *pu32CorbBuf;
367 /* size in bytes of CORB buf */
368 uint32_t cbCorbBuf;
369 /* pointer on RIRB buf */
370 uint64_t *pu64RirbBuf;
371 /* size in bytes of RIRB buf */
372 uint32_t cbRirbBuf;
373 /* indicates if HDA in reset. */
374 bool fInReset;
375 CODECState Codec;
376 uint8_t u8Counter;
377 uint8_t u8StreamsInReset;
378} INTELHDLinkState;
379
380#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
381#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
382
383
384
385
386typedef struct PCIINTELHDLinkState
387{
388 PCIDevice dev;
389 INTELHDLinkState hda;
390} PCIINTELHDLinkState;
391
392DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
393DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
394DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
395DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
396DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
397DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
398DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
399DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
400DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
401DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
402DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
403DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
404DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
405DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
406DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
407DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
408DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
409DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
410
411DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
412DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
413DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
414DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
415DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
416DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
417DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
418DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
419DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
420DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
421DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
422DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
423DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
424static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
425static void fetch_bd(INTELHDLinkState *pState);
426
427/* see 302349 p 6.2*/
428const static struct stIchIntelHDRegMap
429{
430 /** Register offset in the register space. */
431 uint32_t offset;
432 /** Size in bytes. Registers of size > 4 are in fact tables. */
433 uint32_t size;
434 /** Readable bits. */
435 uint32_t readable;
436 /** Writable bits. */
437 uint32_t writable;
438 /** Read callback. */
439 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
440 /** Write callback. */
441 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
442 /** Abbreviated name. */
443 const char *abbrev;
444 /** Full name. */
445 const char *name;
446} s_ichIntelHDRegMap[] =
447{
448 /* offset size read mask write mask read callback write callback abbrev full name */
449 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
450 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
451 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
452 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
453 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
454 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
455 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
456 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
457 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
458 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
459 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
460 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
461 //** @todo r=michaln: Are guests really not reading the WALCLK register at all?
462 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
463 //** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
464 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
465 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
466 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
467 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
468 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
469 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
470 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
471 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
472 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
473 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
474 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
475 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
476 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
477 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
478 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
479 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
480 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
481 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadU16 , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
482 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
483 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
484
485 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
486 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
487 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
488 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
489 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
490 { 0x0008E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOW", "ISD0 FIFO Watermark" },
491 { 0x00090, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
492 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FMT" , "ISD0 Format" },
493 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
494 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
495
496 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
497 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
498 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
499 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
500 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
501 { 0x000AE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOW", "ISD1 FIFO Watermark" },
502 { 0x000B0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
503 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FMT" , "ISD1 Format" },
504 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
505 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
506
507 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
508 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
509 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
510 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
511 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
512 { 0x000CE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOW", "ISD2 FIFO Watermark" },
513 { 0x000D0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
514 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FMT" , "ISD2 Format" },
515 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
516 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
517
518 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
519 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
520 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
521 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
522 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
523 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
524 { 0x000F0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
525 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FMT" , "ISD3 Format" },
526 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
527 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
528
529 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
530 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
531 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
532 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
533 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
534 { 0x0010E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOW", "OSD0 FIFO Watermark" },
535 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOS", "OSD0 FIFO Size" },
536 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FMT" , "OSD0 Format" },
537 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
538 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
539
540 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
541 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
542 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
543 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
544 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
545 { 0x0012E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOW", "OSD1 FIFO Watermark" },
546 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOS", "OSD1 FIFO Size" },
547 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FMT" , "OSD1 Format" },
548 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
549 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
550
551 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
552 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
553 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
554 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
555 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
556 { 0x0014E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOW", "OSD2 FIFO Watermark" },
557 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOS", "OSD2 FIFO Size" },
558 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FMT" , "OSD2 Format" },
559 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
560 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
561
562 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
563 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
564 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
565 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
566 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
567 { 0x0016E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOW", "OSD3 FIFO Watermark" },
568 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOS", "OSD3 FIFO Size" },
569 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FMT" , "OSD3 Format" },
570 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
571 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
572};
573
574static int hdaProcessInterrupt(INTELHDLinkState* pState)
575{
576 bool fIrq = false;
577 if( INTCTL_CIE(pState)
578 && ( RIRBSTS_RINTFL(pState)
579 || RIRBSTS_RIRBOIS(pState)
580 || STATESTS(pState)))
581 {
582 fIrq = true;
583 }
584 if ( INTCTL_SX(pState, 4)
585 && SDSTS(pState, 4) && HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))
586 {
587 fIrq = true;
588 }
589 if (INTCTL_GIE(pState))
590 {
591 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
592 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
593 }
594 return VINF_SUCCESS;
595}
596
597static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
598{
599 int index = 0;
600 //** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
601 for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
602 {
603 if ( u32Offset >= s_ichIntelHDRegMap[index].offset
604 && u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
605 {
606 return index;
607 }
608 }
609 /* Aliases HDA spec 3.3.45 */
610 switch(u32Offset)
611 {
612 case 0x2084:
613 return HDA_REG_IND_NAME(SD0LPIB);
614 case 0x20A4:
615 return HDA_REG_IND_NAME(SD1LPIB);
616 case 0x20C4:
617 return HDA_REG_IND_NAME(SD2LPIB);
618 case 0x20E4:
619 return HDA_REG_IND_NAME(SD3LPIB);
620 case 0x2104:
621 return HDA_REG_IND_NAME(SD4LPIB);
622 case 0x2124:
623 return HDA_REG_IND_NAME(SD5LPIB);
624 case 0x2144:
625 return HDA_REG_IND_NAME(SD6LPIB);
626 case 0x2164:
627 return HDA_REG_IND_NAME(SD7LPIB);
628 }
629 return -1;
630}
631
632static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
633{
634 int rc = VINF_SUCCESS;
635 if (fLocal)
636 {
637 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
638 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
639 if (RT_FAILURE(rc))
640 AssertRCReturn(rc, rc);
641 uint8_t i = 0;
642 do
643 {
644 Log(("hda: corb%02x: ", i));
645 uint8_t j = 0;
646 do
647 {
648 const char *prefix;
649 if ((i + j) == CORBRP(pState))
650 prefix = "[R]";
651 else if ((i + j) == CORBWP(pState))
652 prefix = "[W]";
653 else
654 prefix = " "; /* three spaces */
655 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
656 j++;
657 } while (j < 8);
658 Log(("\n"));
659 i += 8;
660 } while(i != 0);
661 }
662 else
663 {
664 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
665 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
666 if (RT_FAILURE(rc))
667 AssertRCReturn(rc, rc);
668 uint8_t i = 0;
669 do {
670 Log(("hda: rirb%02x: ", i));
671 uint8_t j = 0;
672 do {
673 const char *prefix;
674 if ((i + j) == RIRBWP(pState))
675 prefix = "[W]";
676 else
677 prefix = " ";
678 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
679 } while (++j < 8);
680 Log(("\n"));
681 i += 8;
682 } while (i != 0);
683 }
684 return rc;
685}
686
687#if 0
688static int hdaUnsolictedResponse(INTELHDLinkState *pState, uint64_t pu64UnsolictedResponse)
689{
690 uint8_t rirbWp;
691 if (!HDA_REG_FLAG_VALUE(pState, GCTL, UR))
692 {
693 Log(("hda: unsolicited response %016lx is ignored\n"));
694 return VINF_SUCCESS;
695 }
696}
697#endif
698
699static int hdaCORBCmdProcess(INTELHDLinkState *pState)
700{
701 int rc;
702 uint8_t corbRp;
703 uint8_t corbWp;
704 uint8_t rirbWp;
705
706 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
707
708 rc = hdaCmdSync(pState, true);
709 if (RT_FAILURE(rc))
710 AssertRCReturn(rc, rc);
711 corbRp = CORBRP(pState);
712 corbWp = CORBWP(pState);
713 rirbWp = RIRBWP(pState);
714 Assert((corbWp != corbRp));
715 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
716 while (corbRp != corbWp)
717 {
718 uint32_t cmd;
719 uint64_t resp;
720 corbRp++;
721 cmd = pState->pu32CorbBuf[corbRp];
722 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
723 if (RT_FAILURE(rc))
724 AssertRCReturn(rc, rc);
725 Assert(pfn);
726 (rirbWp)++;
727 rc = pfn(&pState->Codec, cmd, &resp);
728 if (RT_FAILURE(rc))
729 AssertRCReturn(rc, rc);
730 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
731 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
732 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
733 {
734 Log(("hda: unexpected unsolicited response.\n"));
735 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
736 return rc;
737 }
738 pState->pu64RirbBuf[rirbWp] = resp;
739 pState->u8Counter++;
740 if (pState->u8Counter == RINTCNT_N(pState))
741 break;
742 }
743 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
744 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
745 rc = hdaCmdSync(pState, false);
746 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
747 if (RIRBCTL_RIRB_RIC(pState))
748 {
749 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
750 pState->u8Counter = 0;
751 rc = hdaProcessInterrupt(pState);
752 }
753 if (RT_FAILURE(rc))
754 AssertRCReturn(rc, rc);
755 return rc;
756}
757
758static void hdaStreamReset(INTELHDLinkState *pState, uint32_t u32Offset)
759{
760 Log(("hda: reset of stream (%x) started\n", u32Offset));
761 Log(("hda: reset of stream (%x) finished\n", u32Offset));
762}
763
764
765DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
766{
767 *pu32Value = 0;
768 return VINF_SUCCESS;
769}
770DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
771{
772 return VINF_SUCCESS;
773}
774/* U8 */
775DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
776{
777 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
778 return hdaRegReadU32(pState, offset, index, pu32Value);
779}
780
781DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
782{
783 Assert(((u32Value & 0xffffff00) == 0));
784 return hdaRegWriteU32(pState, offset, index, u32Value);
785}
786/* U16 */
787DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
788{
789 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
790 return hdaRegReadU32(pState, offset, index, pu32Value);
791}
792
793DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
794{
795 Assert(((u32Value & 0xffff0000) == 0));
796 return hdaRegWriteU32(pState, offset, index, u32Value);
797}
798
799/* U24 */
800DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
801{
802 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
803 return hdaRegReadU32(pState, offset, index, pu32Value);
804}
805
806DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
807{
808 Assert(((u32Value & 0xff000000) == 0));
809 return hdaRegWriteU32(pState, offset, index, u32Value);
810}
811/* U32 */
812DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
813{
814 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
815 return VINF_SUCCESS;
816}
817
818DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
819{
820 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
821 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
822 return VINF_SUCCESS;
823}
824
825DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
826{
827 return hdaRegReadU32(pState, offset, index, pu32Value);
828}
829
830DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
831{
832 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
833 {
834 /* exit reset state */
835 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
836 pState->fInReset = false;
837 }
838 else
839 {
840 /* enter reset state*/
841 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
842 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
843 {
844 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
845 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
846 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
847 }
848 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
849 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
850 pState->fInReset = true;
851 }
852 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
853 {
854 /* Flush: GSTS:1 set, see 6.2.6*/
855 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
856 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
857 }
858 return VINF_SUCCESS;
859}
860
861DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
862{
863 uint32_t v = pState->au32Regs[index];
864 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
865 pState->au32Regs[index] = (v ^ nv) & v; /* write of 1 clears corresponding bit */
866 return VINF_SUCCESS;
867}
868
869DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
870{
871 uint32_t v = 0;
872 if ( RIRBSTS_RIRBOIS(pState)
873 || RIRBSTS_RINTFL(pState)
874 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
875 || STATESTS(pState))
876 v |= RT_BIT(30);
877#define HDA_IS_STREAM_EVENT(pState, stream) \
878 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
879 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
880 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
881#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
882 MARK_STREAM(pState, 0, v);
883 MARK_STREAM(pState, 1, v);
884 MARK_STREAM(pState, 2, v);
885 MARK_STREAM(pState, 3, v);
886 MARK_STREAM(pState, 4, v);
887 MARK_STREAM(pState, 5, v);
888 MARK_STREAM(pState, 6, v);
889 MARK_STREAM(pState, 7, v);
890 v |= v ? RT_BIT(31) : 0;
891 *pu32Value = v;
892 return VINF_SUCCESS;
893}
894
895DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
896{
897 return hdaRegReadU16(pState, offset, index, pu32Value);
898}
899
900DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
901{
902 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
903 {
904 pState->u8CORBRP = 0;
905 CORBRP(pState) = 0;
906 }
907 else
908 return hdaRegWriteU8(pState, offset, index, u32Value);
909 return VINF_SUCCESS;
910}
911
912DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
913{
914 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
915 AssertRC(rc);
916 if ( CORBWP(pState) != CORBRP(pState)
917 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
918 return hdaCORBCmdProcess(pState);
919 return rc;
920}
921
922DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
923{
924 uint32_t v = CORBSTS(pState);
925 v = (v ^ u32Value) & v;
926 CORBSTS(pState) = v;
927 return VINF_SUCCESS;
928}
929
930DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
931{
932 int rc;
933 rc = hdaRegWriteU16(pState, offset, index, u32Value);
934 if (RT_FAILURE(rc))
935 AssertRCReturn(rc, rc);
936 if (CORBWP(pState) == CORBRP(pState))
937 return VINF_SUCCESS;
938 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
939 return VINF_SUCCESS;
940 rc = hdaCORBCmdProcess(pState);
941 return rc;
942}
943
944DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
945{
946 return hdaRegReadU24(pState, offset, index, pu32Value);
947}
948#define HDA_STREAM_BITMASK(offset) (1 << (((offset) - 0x80) >> 5))
949#define HDA_IS_STREAM_IN_RESET(pState, offset) ((pState)->u8StreamsInReset & HDA_STREAM_BITMASK((offset)))
950DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
951{
952 if(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST))
953 {
954 LogRel(("hda: guest has iniated hw stream reset\n"));
955 pState->u8StreamsInReset |= HDA_STREAM_BITMASK(offset);
956 hdaStreamReset(pState, offset);
957 HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
958 }
959 else if (HDA_IS_STREAM_IN_RESET(pState, offset))
960 {
961 LogRel(("hda: guest has iniated exit of stream reset\n"));
962 pState->u8StreamsInReset &= ~HDA_STREAM_BITMASK(offset);
963 HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
964 }
965 /* @todo: use right offsets for right streams */
966 if (u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
967 {
968 Log(("hda: DMA(%x) switched on\n", offset));
969 AUD_set_active_in(pState->Codec.voice_pi, 1);
970 AUD_set_active_in(pState->Codec.voice_mc, 1);
971 if (offset == 0x100)
972 {
973 fetch_bd(pState);
974 AUD_set_active_out(pState->Codec.voice_po, 1);
975 //SDSTS(pState, 4) |= (1<<5);
976 }
977 }
978 else
979 {
980 Log(("hda: DMA(%x) switched off\n", offset));
981 AUD_set_active_in(pState->Codec.voice_pi, 0);
982 AUD_set_active_in(pState->Codec.voice_mc, 0);
983 if (offset == 0x100)
984 {
985 SDSTS(pState, 4) &= ~(1<<5);
986 AUD_set_active_out(pState->Codec.voice_po, 0);
987 }
988 //SSYNC(pState) &= ~(1<< (offset - 0x80));
989 }
990 int rc = hdaRegWriteU24(pState, offset, index, u32Value);
991 if (RT_FAILURE(rc))
992 AssertRCReturn(rc, VINF_SUCCESS);
993 return rc;
994}
995
996DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
997{
998 uint32_t v = HDA_REG_IND(pState, index);
999 v ^= (u32Value & v);
1000 HDA_REG_IND(pState, index) = v;
1001 hdaProcessInterrupt(pState);
1002#if 0
1003 if ( v != u32Value
1004 && (INTCTL_SALL(pState) & (1 << ((offset - 0x83) >> 5))))
1005 {
1006 int rc;
1007 rc = hdaProcessInterrupt(pState);
1008 if (RT_FAILURE(rc))
1009 AssertRCReturn(rc, rc);
1010 }
1011#endif
1012 return VINF_SUCCESS;
1013}
1014DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1015{
1016 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1017 if (RT_FAILURE(rc))
1018 AssertRCReturn(rc, VINF_SUCCESS);
1019 return rc;
1020}
1021
1022DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1023{
1024 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1025 if (RT_FAILURE(rc))
1026 AssertRCReturn(rc, VINF_SUCCESS);
1027 return rc;
1028}
1029
1030DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1031{
1032 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1033 if (RT_FAILURE(rc))
1034 AssertRCReturn(rc, VINF_SUCCESS);
1035 return rc;
1036}
1037
1038DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1039{
1040 int rc = VINF_SUCCESS;
1041 uint64_t resp;
1042 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1043 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1044 && !IRS_ICB(pState))
1045 {
1046 uint32_t cmd = IC(pState);
1047 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1048 Log(("hda: IC:%x\n", cmd));
1049 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1050 if (RT_FAILURE(rc))
1051 AssertRCReturn(rc, rc);
1052 rc = pfn(&pState->Codec, cmd, &resp);
1053 if (RT_FAILURE(rc))
1054 AssertRCReturn(rc, rc);
1055 IR(pState) = (uint32_t)resp;
1056 Log(("hda: IR:%x\n", IR(pState)));
1057 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* clear busy, result is ready */
1058 return rc;
1059 }
1060 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1061 && IRS_IRV(pState))
1062 IRS(pState) ^= HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1063 return rc;
1064}
1065
1066DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1067{
1068 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1069 {
1070 RIRBWP(pState) = 0;
1071 }
1072 /*The rest of bits are O, see 6.2.22 */
1073 return VINF_SUCCESS;
1074}
1075
1076DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1077{
1078 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1079 if (RT_FAILURE(rc))
1080 AssertRCReturn(rc, rc);
1081 switch(index)
1082 {
1083 case ICH6_HDA_REG_CORBLBASE:
1084 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1085 pState->u64CORBBase |= pState->au32Regs[index];
1086 break;
1087 case ICH6_HDA_REG_CORBUBASE:
1088 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1089 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1090 break;
1091 case ICH6_HDA_REG_RIRLBASE:
1092 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1093 pState->u64RIRBBase |= pState->au32Regs[index];
1094 break;
1095 case ICH6_HDA_REG_RIRUBASE:
1096 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1097 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1098 break;
1099 case ICH6_HDA_REG_DPLBASE:
1100 /* @todo: first bit has special meaning */
1101 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1102 pState->u64DPBase |= pState->au32Regs[index];
1103 break;
1104 case ICH6_HDA_REG_DPUBASE:
1105 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1106 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1107 break;
1108 default:
1109 AssertMsgFailed(("Invalid index"));
1110 }
1111 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1112 return rc;
1113}
1114
1115DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1116{
1117 uint8_t nv = u32Value;
1118 uint8_t v = RIRBSTS(pState);
1119 RIRBSTS(pState) = (v ^ nv) & v;
1120
1121 return hdaProcessInterrupt(pState);
1122}
1123
1124static void dump_bd(INTELHDLinkState *pState)
1125{
1126 uint64_t addr;
1127 uint32_t len;
1128 uint32_t ioc;
1129 uint8_t bdle[16];
1130 uint32_t counter;
1131 uint32_t i;
1132 uint32_t sum = 0;
1133 for (i = 0; i <= SDLVI(pState, 4); ++i)
1134 {
1135 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), SDBDPL(pState, 4) + i*16, bdle, 16);
1136 addr = *(uint64_t *)bdle;
1137 len = *(uint32_t *)&bdle[8];
1138 ioc = *(uint32_t *)&bdle[12];
1139 Log(("hda: %s bdle[%d] a:%x, len:%x, ios:%d\n", (i == pState->u32Cvi? "[C]": " "), i, addr, len, ioc));
1140 sum += len;
1141 }
1142 Log(("hda: sum: %d\n", sum));
1143 for (i = 0; i < 8; ++i)
1144 {
1145 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64DPBase + i*8, &counter, 4);
1146 Log(("hda: %s stream[%d] counter=%x\n", (i) == SDCTL_NUM(pState, 4)? "[C]": " ", i , counter));
1147 }
1148}
1149static void fetch_bd(INTELHDLinkState *pState)
1150{
1151 dump_bd(pState);
1152 uint8_t bdle[16];
1153 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), SDBDPL(pState, 4) + pState->u32Cvi*16, bdle, 16);
1154 pState->u64CviAddr = *(uint64_t *)bdle;
1155 pState->u32CviLen = *(uint32_t *)&bdle[8];
1156 pState->fCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1157}
1158
1159static uint32_t write_audio(INTELHDLinkState *pState, int avail, bool *fStop)
1160{
1161 uint8_t tmpbuf[4096];
1162 uint32_t temp;
1163 uint32_t u32Rest;
1164 uint32_t written = 0;
1165 int to_copy = 0;
1166 u32Rest = pState->u32CviLen - pState->u32CviPos;
1167 temp = audio_MIN(u32Rest, (uint32_t)avail);
1168 if (!temp)
1169 {
1170 *fStop = true;
1171 return written;
1172 }
1173 while (temp)
1174 {
1175 int copied;
1176 to_copy = audio_MIN(temp, 4096U);
1177 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CviAddr + pState->u32CviPos, tmpbuf, to_copy);
1178 copied = AUD_write (pState->Codec.voice_po, tmpbuf, to_copy);
1179 Log (("hda: write_audio max=%x to_copy=%x copied=%x\n",
1180 avail, to_copy, copied));
1181 Assert((copied));
1182 if (!copied)
1183 {
1184 *fStop = true;
1185 break;
1186 }
1187 temp -= copied;
1188 written += copied;
1189 pState->u32CviPos += copied;
1190 }
1191 return written;
1192}
1193
1194DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1195{
1196 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1197 return VINF_SUCCESS;
1198}
1199
1200DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1201{
1202 bool fStop = false;
1203 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1204 switch(src)
1205 {
1206 case PO_INDEX:
1207 {
1208 uint32_t written;
1209 uint32_t u32Counter;
1210 if ( !(SDCTL(pState, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1211 || avail == 0)
1212 return;
1213 SDCTL(pState, 4) |= ((pState->Codec.pNodes[2].dac.u32F06_param & (0xf << 4)) >> 4) << 20;
1214 //fetch_bd(pState);
1215 while( avail
1216 && !fStop)
1217 {
1218 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + 4*8, &u32Counter, 4);
1219 written = write_audio(pState, avail, &fStop);
1220 if ( fStop
1221 && pState->u32CviLen != pState->u32CviPos)
1222 break;
1223 SDLPIB(pState, 4) += written; /* bytes ? */
1224 avail -= written;
1225 u32Counter += written;
1226 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + 4*8, &u32Counter, 4);
1227 if ( pState->u32CviPos == pState->u32CviLen
1228 || SDLPIB(pState, 4) == SDLCBL(pState, 4))
1229 {
1230 if ( SDCTL(pState, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)
1231 && ( ( pState->u32CviPos == pState->u32CviLen
1232 && pState->fCviIoc )
1233 || SDLPIB(pState, 4) == SDLCBL(pState, 4)))
1234 {
1235 SDSTS(pState,4) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1236 hdaProcessInterrupt(pState);
1237 if (SDLPIB(pState, 4) == SDLCBL(pState, 4))
1238 {
1239 SDLPIB(pState, 4) = 0;
1240 u32Counter = 0;
1241 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + 4*8, &u32Counter, 4);
1242 }
1243 }
1244 if (pState->u32CviPos == pState->u32CviLen)
1245 {
1246 pState->u32CviPos = 0;
1247 pState->u32Cvi++;
1248 if (pState->u32Cvi == SDLVI(pState, 4) + 1)
1249 pState->u32Cvi = 0;
1250 }
1251 fStop = false;
1252 fetch_bd(pState);
1253 }
1254 }
1255 }
1256 break;
1257 AssertMsgFailed(("Unexpected index: %x\n", src));
1258 default:
1259 break;
1260 }
1261}
1262
1263/**
1264 * Handle register read operation.
1265 *
1266 * Looks up and calls appropriate handler.
1267 *
1268 * @note: while implementation was detected so called "forgotten" or "hole" registers
1269 * which description is missed in RPM, datasheet or spec.
1270 *
1271 * @returns VBox status code.
1272 *
1273 * @param pState The device state structure.
1274 * @param uOffset Register offset in memory-mapped frame.
1275 * @param pv Where to fetch the value.
1276 * @param cb Number of bytes to write.
1277 * @thread EMT
1278 */
1279PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1280{
1281 int rc = VINF_SUCCESS;
1282 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1283 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1284 int index = hdaLookup(&pThis->hda, u32Offset);
1285 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1286 {
1287 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1288 }
1289 Assert( index != -1
1290 && cb <= 4);
1291 if (index != -1)
1292 {
1293 uint32_t mask = 0;
1294 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1295 uint32_t v = 0;
1296 switch(cb)
1297 {
1298 case 1: mask = 0x000000ff; break;
1299 case 2: mask = 0x0000ffff; break;
1300 case 3: mask = 0x00ffffff; break;
1301 case 4: mask = 0xffffffff; break;
1302 }
1303 mask <<= shift;
1304 rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1305 *(uint32_t *)pv = (v & mask) >> shift;
1306 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
1307 return rc;
1308 }
1309 *(uint32_t *)pv = 0xFF;
1310 Log(("hda: hole at %X is accessed for read\n", u32Offset));
1311 return rc;
1312}
1313
1314/**
1315 * Handle register write operation.
1316 *
1317 * Looks up and calls appropriate handler.
1318 *
1319 * @returns VBox status code.
1320 *
1321 * @param pState The device state structure.
1322 * @param uOffset Register offset in memory-mapped frame.
1323 * @param pv Where to fetch the value.
1324 * @param cb Number of bytes to write.
1325 * @thread EMT
1326 */
1327PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1328{
1329 int rc = VINF_SUCCESS;
1330 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1331 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1332 int index = hdaLookup(&pThis->hda, u32Offset);
1333 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1334 {
1335 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1336 }
1337 Assert( index != -1
1338 && cb <= 4);
1339 if (index != -1)
1340 {
1341 uint32_t v = pThis->hda.au32Regs[index];
1342 uint32_t mask = 0;
1343 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1344 switch(cb)
1345 {
1346 case 1: mask = 0xffffff00; break;
1347 case 2: mask = 0xffff0000; break;
1348 case 3: mask = 0xff000000; break;
1349 case 4: mask = 0x00000000; break;
1350 }
1351 mask <<= shift;
1352 *(uint32_t *)pv = ((v & mask) | (*(uint32_t *)pv & ~mask)) >> shift;
1353 rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
1354 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
1355 return rc;
1356 }
1357 Log(("hda: hole at %X is accessed for write\n", u32Offset));
1358 return rc;
1359}
1360
1361/**
1362 * Callback function for mapping a PCI I/O region.
1363 *
1364 * @return VBox status code.
1365 * @param pPciDev Pointer to PCI device.
1366 * Use pPciDev->pDevIns to get the device instance.
1367 * @param iRegion The region number.
1368 * @param GCPhysAddress Physical address of the region.
1369 * If iType is PCI_ADDRESS_SPACE_IO, this is an
1370 * I/O port, else it's a physical address.
1371 * This address is *NOT* relative
1372 * to pci_mem_base like earlier!
1373 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
1374 */
1375static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
1376 RTGCPHYS GCPhysAddress, uint32_t cb,
1377 PCIADDRESSSPACE enmType)
1378{
1379 int rc;
1380 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1381 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1382 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1383
1384 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1385 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
1386 hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
1387
1388 if (RT_FAILURE(rc))
1389 return rc;
1390
1391 pThis->hda.addrMMReg = GCPhysAddress;
1392 return VINF_SUCCESS;
1393}
1394
1395
1396/**
1397 * Reset notification.
1398 *
1399 * @returns VBox status.
1400 * @param pDevIns The device instance data.
1401 *
1402 * @remark The original sources didn't install a reset handler, but it seems to
1403 * make sense to me so we'll do it.
1404 */
1405static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns)
1406{
1407 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1408 GCAP(&pThis->hda) = 0x4401; /* see 6.2.1 */
1409 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
1410 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1411 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1412 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
1413 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
1414 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
1415 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
1416 CORBRP(&pThis->hda) = 0x0;
1417 RIRBWP(&pThis->hda) = 0x0;
1418
1419 LogRel(("hda: inter HDA reset.\n"));
1420 //** @todo r=michaln: There should be LogRel statements when the guest initializes
1421 // or resets the HDA chip, and possibly also when opening the PCM streams.
1422 pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
1423
1424 if (pThis->hda.pu32CorbBuf)
1425 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
1426 else
1427 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
1428
1429 pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
1430 if (pThis->hda.pu64RirbBuf)
1431 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
1432 else
1433 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
1434
1435 /* Accoding to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
1436 * bits are reserved for stream number 18.2.33 */
1437 SDCTL(&pThis->hda, 0) = 0x40000;
1438 SDCTL(&pThis->hda, 1) = 0x40000;
1439 SDCTL(&pThis->hda, 2) = 0x40000;
1440 SDCTL(&pThis->hda, 3) = 0x40000;
1441 SDCTL(&pThis->hda, 4) = 0x40000;
1442 SDCTL(&pThis->hda, 5) = 0x40000;
1443 SDCTL(&pThis->hda, 6) = 0x40000;
1444 SDCTL(&pThis->hda, 7) = 0x40000;
1445
1446 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1447 SDFIFOS(&pThis->hda, 0) = 0x77;
1448 SDFIFOS(&pThis->hda, 1) = 0x77;
1449 SDFIFOS(&pThis->hda, 2) = 0x77;
1450 SDFIFOS(&pThis->hda, 3) = 0x77;
1451 SDFIFOS(&pThis->hda, 4) = 0xBF;
1452 SDFIFOS(&pThis->hda, 5) = 0xBF;
1453 SDFIFOS(&pThis->hda, 6) = 0xBF;
1454 SDFIFOS(&pThis->hda, 7) = 0xBF;
1455
1456 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
1457 STATESTS(&pThis->hda) = 0x1;
1458
1459 Log(("hda: reset finished\n"));
1460}
1461
1462/**
1463 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1464 */
1465static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
1466 const char *pszIID)
1467{
1468 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
1469 Assert(&pThis->hda.IBase == pInterface);
1470
1471 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
1472 return NULL;
1473}
1474
1475/**
1476 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1477 */
1478static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
1479 PCFGMNODE pCfgHandle)
1480{
1481 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1482 INTELHDLinkState *s = &pThis->hda;
1483 int rc;
1484
1485 Assert(iInstance == 0);
1486 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1487
1488 /*
1489 * Validations.
1490 */
1491 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
1492 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1493 N_ ("Invalid configuration for the INTELHD device"));
1494
1495 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
1496 // poll some register(s).
1497
1498 /*
1499 * Initialize data (most of it anyway).
1500 */
1501 s->pDevIns = pDevIns;
1502 /* IBase */
1503 s->IBase.pfnQueryInterface = hdaQueryInterface;
1504
1505 /* PCI Device (the assertions will be removed later) */
1506 PCIDevSetVendorId (&pThis->dev, 0x8086); /* 00 ro - intel. */
1507 PCIDevSetDeviceId (&pThis->dev, 0x2668); /* 02 ro - 82801 / 82801aa(?). */
1508 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
1509 PCIDevSetStatus (&pThis->dev, 0x0010); /* 06 rwc?,ro? - pcists. */
1510 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
1511 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
1512 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
1513 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
1514 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
1515 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
1516 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
1517 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
1518 verb F20 should provide device/codec recognition. */
1519 PCIDevSetSubSystemVendorId (&pThis->dev, 0x0000); /* 2c ro - intel.) */
1520 PCIDevSetSubSystemId (&pThis->dev, 0x0000); /* 2e ro. */
1521 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
1522 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */ Assert (pThis->dev.config[0x3d] == 0x01);
1523 PCIDevSetCapabilityList(&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
1524
1525 //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
1526 // of these values needs to be properly documented!
1527 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1528 pThis->dev.config[0x40] = 0x01;
1529
1530 pThis->dev.config[0x50] = 0x01;
1531 pThis->dev.config[0x51] = 0x60; /* next */
1532 pThis->dev.config[0x52] = 0x22;
1533 pThis->dev.config[0x53] = 0x00; /* PM - disabled, */
1534
1535#if 0
1536 pThis->dev.config[0x60] = 0x05;
1537 pThis->dev.config[0x61] = 0x70; /* next */
1538 pThis->dev.config[0x62] = 0x00;
1539 pThis->dev.config[0x63] = 0x80;
1540#endif
1541
1542 /*
1543 * Register the PCI device.
1544 */
1545 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
1546 if (RT_FAILURE (rc))
1547 return rc;
1548
1549 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
1550 hdaMap);
1551 if (RT_FAILURE (rc))
1552 return rc;
1553
1554 /*
1555 * Attach driver.
1556 */
1557 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
1558 &s->pDrvBase, "Audio Driver Port");
1559 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1560 Log (("hda: No attached driver!\n"));
1561 else if (RT_FAILURE (rc))
1562 {
1563 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
1564 return rc;
1565 }
1566
1567
1568
1569 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
1570 rc = stac9220Construct(&pThis->hda.Codec);
1571 if (RT_FAILURE(rc))
1572 AssertRCReturn(rc, rc);
1573 hdaReset (pDevIns);
1574 pThis->hda.Codec.id = 0;
1575 pThis->hda.Codec.pfnTransfer = hdaTransfer;
1576 pThis->hda.Codec.pfnReset = hdaCodecReset;
1577 /*
1578 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
1579 * hdaReset shouldn't affects these registers.
1580 */
1581 WAKEEN(&pThis->hda) = 0x0;
1582 STATESTS(&pThis->hda) = 0x0;
1583
1584 return VINF_SUCCESS;
1585}
1586
1587/**
1588 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1589 */
1590static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
1591{
1592 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1593
1594 int rc = stac9220Destruct(&pThis->hda.Codec);
1595 AssertRC(rc);
1596 if (pThis->hda.pu32CorbBuf)
1597 RTMemFree(pThis->hda.pu32CorbBuf);
1598 if (pThis->hda.pu64RirbBuf)
1599 RTMemFree(pThis->hda.pu64RirbBuf);
1600 return VINF_SUCCESS;
1601}
1602
1603/**
1604 * The device registration structure.
1605 */
1606const PDMDEVREG g_DeviceICH6_HDA =
1607{
1608 /* u32Version */
1609 PDM_DEVREG_VERSION,
1610 /* szName */
1611 "hda",
1612 /* szRCMod */
1613 "",
1614 /* szR0Mod */
1615 "",
1616 /* pszDescription */
1617 "ICH IntelHD Audio Controller",
1618 /* fFlags */
1619 PDM_DEVREG_FLAGS_DEFAULT_BITS,
1620 /* fClass */
1621 PDM_DEVREG_CLASS_AUDIO,
1622 /* cMaxInstances */
1623 1,
1624 /* cbInstance */
1625 sizeof(PCIINTELHDLinkState),
1626 /* pfnConstruct */
1627 hdaConstruct,
1628 /* pfnDestruct */
1629 hdaDestruct,
1630 /* pfnRelocate */
1631 NULL,
1632 /* pfnIOCtl */
1633 NULL,
1634 /* pfnPowerOn */
1635 NULL,
1636 /* pfnReset */
1637 hdaReset,
1638 /* pfnSuspend */
1639 NULL,
1640 /* pfnResume */
1641 NULL,
1642 /* pfnAttach */
1643 NULL,
1644 /* pfnDetach */
1645 NULL,
1646 /* pfnQueryInterface. */
1647 NULL,
1648 /* pfnInitComplete */
1649 NULL,
1650 /* pfnPowerOff */
1651 NULL,
1652 /* pfnSoftReset */
1653 NULL,
1654 /* u32VersionEnd */
1655 PDM_DEVREG_VERSION
1656};
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