VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 33218

Last change on this file since 33218 was 33031, checked in by vboxsync, 14 years ago

Devices: global define for using MSI support in devices
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1/* $Id: DevIchIntelHDA.cpp 33031 2010-10-11 08:42:53Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/pdmdev.h>
23#include <iprt/assert.h>
24#include <iprt/uuid.h>
25#include <iprt/string.h>
26#include <iprt/mem.h>
27#include <iprt/asm.h>
28
29#include "../Builtins.h"
30
31extern "C" {
32#include "audio.h"
33}
34#include "DevCodec.h"
35
36#undef LOG_VOICES
37#ifndef VBOX
38//#define USE_MIXER
39#else
40#define USE_MIXER
41#endif
42
43#define HDA_SSM_VERSION 1
44PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
45PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
46static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
47
48/* Registers */
49#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
50#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
51#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
52#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
53#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
54#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
55#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
56#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
57#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
58#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
59
60#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
61#define GCAP(pState) (HDA_REG((pState), GCAP))
62
63#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
64#define VMIN(pState) (HDA_REG((pState), VMIN))
65
66#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
67#define VMAJ(pState) (HDA_REG((pState), VMAJ))
68
69#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
70#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
71
72#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
73#define INPAY(pState) (HDA_REG((pState), INPAY))
74
75#define ICH6_HDA_REG_GCTL (5)
76#define ICH6_HDA_GCTL_RST_SHIFT (0)
77#define ICH6_HDA_GCTL_FSH_SHIFT (1)
78#define ICH6_HDA_GCTL_UR_SHIFT (8)
79#define GCTL(pState) (HDA_REG((pState), GCTL))
80
81#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
82#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
83
84#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
85#define STATESTS(pState) (HDA_REG((pState), STATESTS))
86#define ICH6_HDA_STATES_SCSF 0x7
87
88#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
89#define ICH6_HDA_GSTS_FSH_SHIFT (1)
90#define GSTS(pState) (HDA_REG(pState, GSTS))
91
92#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
93#define ICH6_HDA_INTCTL_GIE_SHIFT 31
94#define ICH6_HDA_INTCTL_CIE_SHIFT 30
95#define ICH6_HDA_INTCTL_S0_SHIFT (0)
96#define ICH6_HDA_INTCTL_S1_SHIFT (1)
97#define ICH6_HDA_INTCTL_S2_SHIFT (2)
98#define ICH6_HDA_INTCTL_S3_SHIFT (3)
99#define ICH6_HDA_INTCTL_S4_SHIFT (4)
100#define ICH6_HDA_INTCTL_S5_SHIFT (5)
101#define ICH6_HDA_INTCTL_S6_SHIFT (6)
102#define ICH6_HDA_INTCTL_S7_SHIFT (7)
103#define INTCTL(pState) (HDA_REG((pState), INTCTL))
104#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
105#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
106#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
107#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
108
109/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
110 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
111 * the datasheet.
112 */
113#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
114#define SSYNC(pState) (HDA_REG((pState), SSYNC))
115
116#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
117#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
118#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
119#define ICH6_HDA_INTSTS_S0_SHIFT (0)
120#define ICH6_HDA_INTSTS_S1_SHIFT (1)
121#define ICH6_HDA_INTSTS_S2_SHIFT (2)
122#define ICH6_HDA_INTSTS_S3_SHIFT (3)
123#define ICH6_HDA_INTSTS_S4_SHIFT (4)
124#define ICH6_HDA_INTSTS_S5_SHIFT (5)
125#define ICH6_HDA_INTSTS_S6_SHIFT (6)
126#define ICH6_HDA_INTSTS_S7_SHIFT (7)
127#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
128#define INTSTS(pState) (HDA_REG((pState), INTSTS))
129#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
130#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
131#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
132#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
133
134#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
135#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
136#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
137#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
138#define ICH6_HDA_REG_CORBWP 15 /* 48 */
139#define ICH6_HDA_REG_CORBRP 16 /* 4A */
140#define ICH6_HDA_CORBRP_RST_SHIFT 15
141#define ICH6_HDA_CORBRP_WP_SHIFT 0
142#define ICH6_HDA_CORBRP_WP_MASK 0xFF
143
144#define CORBRP(pState) (HDA_REG(pState, CORBRP))
145#define CORBWP(pState) (HDA_REG(pState, CORBWP))
146
147#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
148#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
149#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
150
151#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
152
153
154#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
155#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
156#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
157
158#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
159#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
160#define ICH6_HDA_CORBSIZE_SZ 0x3
161#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
162#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
163/* till ich 10 sizes of CORB and RIRB are harcoded to 256 in real hw */
164
165#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
166#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
167
168#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
169#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
170
171#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
172#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
173#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
174#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
175
176#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
177#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
178#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
179
180#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
181#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
182#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
183#define ICH6_HDA_ROI_DMA_SHIFT (2)
184#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
185#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
186#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
187#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
188
189#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
190#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
191#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
192#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
193#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
194#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
195
196#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
197#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
198#define ICH6_HDA_RIRBSIZE_SZ 0x3
199
200#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
201#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
202
203
204#define ICH6_HDA_REG_IC 27 /* 0x60 */
205#define IC(pState) (HDA_REG(pState, IC))
206#define ICH6_HDA_REG_IR 28 /* 0x64 */
207#define IR(pState) (HDA_REG(pState, IR))
208#define ICH6_HDA_REG_IRS 29 /* 0x68 */
209#define ICH6_HDA_IRS_ICB_SHIFT (0)
210#define ICH6_HDA_IRS_IRV_SHIFT (1)
211#define IRS(pState) (HDA_REG(pState, IRS))
212#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
213#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
214
215#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
216#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
217#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
218#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
219#define DPBASE_ENABLED 1
220#define DPBASE_ADDR_MASK (~0x7f)
221
222#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
223#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
224
225#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
226#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
227#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
228#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
229#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
230#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
231#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
232#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
233
234#define SD(func, num) SD##num##func
235#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
236#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
237#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
238#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
239#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
240#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
241#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
242#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
243#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
244
245#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
246#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
247#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
248#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
249#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
250#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
251#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
252#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
253
254#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
255#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
256#define ICH6_HDA_SDSTS_DE_SHIFT (4)
257#define ICH6_HDA_SDSTS_FE_SHIFT (3)
258#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
259
260#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
261#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
262#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
263#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
264#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
265#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
266#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
267#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
268
269#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
270
271#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
272#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
273#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
274#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
275#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
276#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
277#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
278#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
279
280#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
281
282#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
283#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
284#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
285#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
286#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
287#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
288#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
289#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
290
291#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
292
293#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
294#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
295#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
296#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
297#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
298#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
299#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
300#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
301
302#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
303#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
304#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
305#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
306#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
307#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
308#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
309#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
310
311#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
312
313#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
314#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
315#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
316#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
317#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
318#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
319#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
320#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
321
322#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
323#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
324#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
325#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
326#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
327#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
328#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
329#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
330
331#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
332
333#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
334#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
335#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
336#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
337#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
338#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
339#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
340#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
341
342#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
343
344/* Predicates */
345
346typedef struct HDABDLEDESC
347{
348 uint64_t u64BdleCviAddr;
349 uint32_t u32BdleMaxCvi;
350 uint32_t u32BdleCvi;
351 uint32_t u32BdleCviLen;
352 uint32_t u32BdleCviPos;
353 bool fBdleCviIoc;
354} HDABDLEDESC, *PHDABDLEDESC;
355
356typedef struct INTELHDLinkState
357{
358 /** Pointer to the device instance. */
359 PPDMDEVINSR3 pDevIns;
360 /** Pointer to the connector of the attached audio driver. */
361 PPDMIAUDIOCONNECTOR pDrv;
362 /** Pointer to the attached audio driver. */
363 PPDMIBASE pDrvBase;
364 /** The base interface for LUN\#0. */
365 PDMIBASE IBase;
366 RTGCPHYS addrMMReg;
367 uint32_t au32Regs[113];
368 HDABDLEDESC stInBdle;
369 HDABDLEDESC stOutBdle;
370 HDABDLEDESC stMicBdle;
371 /* Interrupt on completition */
372 bool fCviIoc;
373 uint64_t u64CORBBase;
374 uint64_t u64RIRBBase;
375 uint64_t u64DPBase;
376 /* pointer on CORB buf */
377 uint32_t *pu32CorbBuf;
378 /* size in bytes of CORB buf */
379 uint32_t cbCorbBuf;
380 /* pointer on RIRB buf */
381 uint64_t *pu64RirbBuf;
382 /* size in bytes of RIRB buf */
383 uint32_t cbRirbBuf;
384 /* indicates if HDA in reset. */
385 bool fInReset;
386 CODECState Codec;
387 uint8_t u8Counter;
388 uint8_t u8StreamsInReset;
389} INTELHDLinkState;
390
391#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
392#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
393
394
395
396
397typedef struct PCIINTELHDLinkState
398{
399 PCIDevice dev;
400 INTELHDLinkState hda;
401} PCIINTELHDLinkState;
402
403DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
404DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
405DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
406DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
407DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
408DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
409DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
410DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
411DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
412DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
413DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
414DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
415DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
416DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
417DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
418DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
419DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
420DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
421
422DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
423DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
424DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
425DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
426DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
427DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
428DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
429DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
430DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
431DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
432DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
433DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
434DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
435static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
436static void fetch_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
437
438/* see 302349 p 6.2*/
439const static struct stIchIntelHDRegMap
440{
441 /** Register offset in the register space. */
442 uint32_t offset;
443 /** Size in bytes. Registers of size > 4 are in fact tables. */
444 uint32_t size;
445 /** Readable bits. */
446 uint32_t readable;
447 /** Writable bits. */
448 uint32_t writable;
449 /** Read callback. */
450 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
451 /** Write callback. */
452 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
453 /** Abbreviated name. */
454 const char *abbrev;
455 /** Full name. */
456 const char *name;
457} s_ichIntelHDRegMap[] =
458{
459 /* offset size read mask write mask read callback write callback abbrev full name */
460 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
461 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
462 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
463 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
464 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
465 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
466 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
467 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
468 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
469 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
470 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
471 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
472 //** @todo r=michaln: Are guests really not reading the WALCLK register at all?
473 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
474 //** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
475 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
476 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
477 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
478 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
479 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
480 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
481 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
482 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
483 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
484 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
485 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
486 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
487 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
488 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
489 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
490 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
491 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
492 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadU16 , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
493 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
494 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
495
496 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
497 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
498 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
499 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
500 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
501 { 0x0008E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOW", "ISD0 FIFO Watermark" },
502 { 0x00090, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
503 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FMT" , "ISD0 Format" },
504 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
505 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
506
507 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
508 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
509 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
510 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
511 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
512 { 0x000AE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOW", "ISD1 FIFO Watermark" },
513 { 0x000B0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
514 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FMT" , "ISD1 Format" },
515 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
516 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
517
518 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
519 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
520 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
521 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
522 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
523 { 0x000CE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOW", "ISD2 FIFO Watermark" },
524 { 0x000D0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
525 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FMT" , "ISD2 Format" },
526 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
527 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
528
529 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
530 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
531 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
532 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
533 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
534 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
535 { 0x000F0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
536 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FMT" , "ISD3 Format" },
537 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
538 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
539
540 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
541 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
542 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
543 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
544 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
545 { 0x0010E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOW", "OSD0 FIFO Watermark" },
546 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOS", "OSD0 FIFO Size" },
547 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FMT" , "OSD0 Format" },
548 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
549 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
550
551 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
552 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
553 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
554 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
555 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
556 { 0x0012E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOW", "OSD1 FIFO Watermark" },
557 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOS", "OSD1 FIFO Size" },
558 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FMT" , "OSD1 Format" },
559 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
560 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
561
562 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
563 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
564 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
565 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
566 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
567 { 0x0014E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOW", "OSD2 FIFO Watermark" },
568 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOS", "OSD2 FIFO Size" },
569 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FMT" , "OSD2 Format" },
570 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
571 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
572
573 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
574 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
575 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
576 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
577 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
578 { 0x0016E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOW", "OSD3 FIFO Watermark" },
579 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOS", "OSD3 FIFO Size" },
580 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FMT" , "OSD3 Format" },
581 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
582 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
583};
584
585static int hdaProcessInterrupt(INTELHDLinkState* pState)
586{
587#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
588 ( INTCTL_SX((pState), num) \
589 && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
590 bool fIrq = false;
591 if( INTCTL_CIE(pState)
592 && ( RIRBSTS_RINTFL(pState)
593 || RIRBSTS_RIRBOIS(pState)
594 || STATESTS(pState)))
595 {
596 fIrq = true;
597 }
598 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
599 || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
600 {
601 fIrq = true;
602 }
603 if (INTCTL_GIE(pState))
604 {
605 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
606 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
607 }
608 return VINF_SUCCESS;
609}
610
611static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
612{
613 int index = 0;
614 //** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
615 for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
616 {
617 if ( u32Offset >= s_ichIntelHDRegMap[index].offset
618 && u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
619 {
620 return index;
621 }
622 }
623 /* Aliases HDA spec 3.3.45 */
624 switch(u32Offset)
625 {
626 case 0x2084:
627 return HDA_REG_IND_NAME(SD0LPIB);
628 case 0x20A4:
629 return HDA_REG_IND_NAME(SD1LPIB);
630 case 0x20C4:
631 return HDA_REG_IND_NAME(SD2LPIB);
632 case 0x20E4:
633 return HDA_REG_IND_NAME(SD3LPIB);
634 case 0x2104:
635 return HDA_REG_IND_NAME(SD4LPIB);
636 case 0x2124:
637 return HDA_REG_IND_NAME(SD5LPIB);
638 case 0x2144:
639 return HDA_REG_IND_NAME(SD6LPIB);
640 case 0x2164:
641 return HDA_REG_IND_NAME(SD7LPIB);
642 }
643 return -1;
644}
645
646static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
647{
648 int rc = VINF_SUCCESS;
649 if (fLocal)
650 {
651 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
652 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
653 if (RT_FAILURE(rc))
654 AssertRCReturn(rc, rc);
655 uint8_t i = 0;
656 do
657 {
658 Log(("hda: corb%02x: ", i));
659 uint8_t j = 0;
660 do
661 {
662 const char *prefix;
663 if ((i + j) == CORBRP(pState))
664 prefix = "[R]";
665 else if ((i + j) == CORBWP(pState))
666 prefix = "[W]";
667 else
668 prefix = " "; /* three spaces */
669 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
670 j++;
671 } while (j < 8);
672 Log(("\n"));
673 i += 8;
674 } while(i != 0);
675 }
676 else
677 {
678 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
679 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
680 if (RT_FAILURE(rc))
681 AssertRCReturn(rc, rc);
682 uint8_t i = 0;
683 do {
684 Log(("hda: rirb%02x: ", i));
685 uint8_t j = 0;
686 do {
687 const char *prefix;
688 if ((i + j) == RIRBWP(pState))
689 prefix = "[W]";
690 else
691 prefix = " ";
692 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
693 } while (++j < 8);
694 Log(("\n"));
695 i += 8;
696 } while (i != 0);
697 }
698 return rc;
699}
700
701#if 0
702static int hdaUnsolictedResponse(INTELHDLinkState *pState, uint64_t pu64UnsolictedResponse)
703{
704 uint8_t rirbWp;
705 if (!HDA_REG_FLAG_VALUE(pState, GCTL, UR))
706 {
707 Log(("hda: unsolicited response %016lx is ignored\n"));
708 return VINF_SUCCESS;
709 }
710}
711#endif
712
713static int hdaCORBCmdProcess(INTELHDLinkState *pState)
714{
715 int rc;
716 uint8_t corbRp;
717 uint8_t corbWp;
718 uint8_t rirbWp;
719
720 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
721
722 rc = hdaCmdSync(pState, true);
723 if (RT_FAILURE(rc))
724 AssertRCReturn(rc, rc);
725 corbRp = CORBRP(pState);
726 corbWp = CORBWP(pState);
727 rirbWp = RIRBWP(pState);
728 Assert((corbWp != corbRp));
729 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
730 while (corbRp != corbWp)
731 {
732 uint32_t cmd;
733 uint64_t resp;
734 corbRp++;
735 cmd = pState->pu32CorbBuf[corbRp];
736 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
737 if (RT_FAILURE(rc))
738 AssertRCReturn(rc, rc);
739 Assert(pfn);
740 (rirbWp)++;
741 rc = pfn(&pState->Codec, cmd, &resp);
742 if (RT_FAILURE(rc))
743 AssertRCReturn(rc, rc);
744 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
745 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
746 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
747 {
748 Log(("hda: unexpected unsolicited response.\n"));
749 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
750 return rc;
751 }
752 pState->pu64RirbBuf[rirbWp] = resp;
753 pState->u8Counter++;
754 if (pState->u8Counter == RINTCNT_N(pState))
755 break;
756 }
757 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
758 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
759 rc = hdaCmdSync(pState, false);
760 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
761 if (RIRBCTL_RIRB_RIC(pState))
762 {
763 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
764 pState->u8Counter = 0;
765 rc = hdaProcessInterrupt(pState);
766 }
767 if (RT_FAILURE(rc))
768 AssertRCReturn(rc, rc);
769 return rc;
770}
771
772static void hdaStreamReset(INTELHDLinkState *pState, uint32_t u32Offset)
773{
774 Log(("hda: reset of stream (%x) started\n", u32Offset));
775 Log(("hda: reset of stream (%x) finished\n", u32Offset));
776}
777
778
779DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
780{
781 *pu32Value = 0;
782 return VINF_SUCCESS;
783}
784DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
785{
786 return VINF_SUCCESS;
787}
788/* U8 */
789DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
790{
791 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
792 return hdaRegReadU32(pState, offset, index, pu32Value);
793}
794
795DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
796{
797 Assert(((u32Value & 0xffffff00) == 0));
798 return hdaRegWriteU32(pState, offset, index, u32Value);
799}
800/* U16 */
801DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
802{
803 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
804 return hdaRegReadU32(pState, offset, index, pu32Value);
805}
806
807DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
808{
809 Assert(((u32Value & 0xffff0000) == 0));
810 return hdaRegWriteU32(pState, offset, index, u32Value);
811}
812
813/* U24 */
814DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
815{
816 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
817 return hdaRegReadU32(pState, offset, index, pu32Value);
818}
819
820DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
821{
822 Assert(((u32Value & 0xff000000) == 0));
823 return hdaRegWriteU32(pState, offset, index, u32Value);
824}
825/* U32 */
826DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
827{
828 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
829 return VINF_SUCCESS;
830}
831
832DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
833{
834 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
835 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
836 return VINF_SUCCESS;
837}
838
839DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
840{
841 return hdaRegReadU32(pState, offset, index, pu32Value);
842}
843
844DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
845{
846 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
847 {
848 /* exit reset state */
849 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
850 pState->fInReset = false;
851 }
852 else
853 {
854 /* enter reset state*/
855 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
856 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
857 {
858 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
859 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
860 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
861 }
862 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
863 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
864 pState->fInReset = true;
865 }
866 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
867 {
868 /* Flush: GSTS:1 set, see 6.2.6*/
869 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
870 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
871 }
872 return VINF_SUCCESS;
873}
874
875DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
876{
877 uint32_t v = pState->au32Regs[index];
878 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
879 pState->au32Regs[index] = (v ^ nv) & v; /* write of 1 clears corresponding bit */
880 return VINF_SUCCESS;
881}
882
883DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
884{
885 uint32_t v = 0;
886 if ( RIRBSTS_RIRBOIS(pState)
887 || RIRBSTS_RINTFL(pState)
888 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
889 || STATESTS(pState))
890 v |= RT_BIT(30);
891#define HDA_IS_STREAM_EVENT(pState, stream) \
892 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
893 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
894 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
895#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
896 MARK_STREAM(pState, 0, v);
897 MARK_STREAM(pState, 1, v);
898 MARK_STREAM(pState, 2, v);
899 MARK_STREAM(pState, 3, v);
900 MARK_STREAM(pState, 4, v);
901 MARK_STREAM(pState, 5, v);
902 MARK_STREAM(pState, 6, v);
903 MARK_STREAM(pState, 7, v);
904 v |= v ? RT_BIT(31) : 0;
905 *pu32Value = v;
906 return VINF_SUCCESS;
907}
908
909DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
910{
911 return hdaRegReadU16(pState, offset, index, pu32Value);
912}
913
914DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
915{
916 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
917 CORBRP(pState) = 0;
918 else
919 return hdaRegWriteU8(pState, offset, index, u32Value);
920 return VINF_SUCCESS;
921}
922
923DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
924{
925 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
926 AssertRC(rc);
927 if ( CORBWP(pState) != CORBRP(pState)
928 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
929 return hdaCORBCmdProcess(pState);
930 return rc;
931}
932
933DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
934{
935 uint32_t v = CORBSTS(pState);
936 v = (v ^ u32Value) & v;
937 CORBSTS(pState) = v;
938 return VINF_SUCCESS;
939}
940
941DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
942{
943 int rc;
944 rc = hdaRegWriteU16(pState, offset, index, u32Value);
945 if (RT_FAILURE(rc))
946 AssertRCReturn(rc, rc);
947 if (CORBWP(pState) == CORBRP(pState))
948 return VINF_SUCCESS;
949 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
950 return VINF_SUCCESS;
951 rc = hdaCORBCmdProcess(pState);
952 return rc;
953}
954
955DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
956{
957 return hdaRegReadU24(pState, offset, index, pu32Value);
958}
959#define HDA_STREAM_BITMASK(offset) (1 << (((offset) - 0x80) >> 5))
960#define HDA_IS_STREAM_IN_RESET(pState, offset) ((pState)->u8StreamsInReset & HDA_STREAM_BITMASK((offset)))
961DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
962{
963 if(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST))
964 {
965 LogRel(("hda: guest has iniated hw stream reset\n"));
966 pState->u8StreamsInReset |= HDA_STREAM_BITMASK(offset);
967 hdaStreamReset(pState, offset);
968 HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
969 }
970 else if (HDA_IS_STREAM_IN_RESET(pState, offset))
971 {
972 LogRel(("hda: guest has iniated exit of stream reset\n"));
973 pState->u8StreamsInReset &= ~HDA_STREAM_BITMASK(offset);
974 HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
975 }
976 /* @todo: use right offsets for right streams */
977 if (u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
978 {
979 Log(("hda: DMA(%x) switched on\n", offset));
980 if (offset == 0x80)
981 {
982 AUD_set_active_in(pState->Codec.voice_pi, 1);
983 //AUD_set_active_in(pState->Codec.voice_mc, 1);
984 }
985 if (offset == 0x100)
986 {
987 uint64_t u64BaseDMA = SDBDPL(pState, 4);
988 u64BaseDMA |= (((uint64_t)SDBDPU(pState, 4)) << 32);
989 if (u64BaseDMA)
990 {
991 //fetch_bd(pState, u64BaseDMA);
992 AUD_set_active_out(pState->Codec.voice_po, 1);
993 }
994 //SDSTS(pState, 4) |= (1<<5);
995 }
996 }
997 else
998 {
999 Log(("hda: DMA(%x) switched off\n", offset));
1000 if (offset == 0x80)
1001 {
1002 AUD_set_active_in(pState->Codec.voice_pi, 0);
1003 //AUD_set_active_in(pState->Codec.voice_mc, 0);
1004 }
1005 if (offset == 0x100)
1006 {
1007 SDSTS(pState, 4) &= ~(1<<5);
1008 AUD_set_active_out(pState->Codec.voice_po, 0);
1009 }
1010 //SSYNC(pState) &= ~(1<< (offset - 0x80));
1011 }
1012 int rc = hdaRegWriteU24(pState, offset, index, u32Value);
1013 if (RT_FAILURE(rc))
1014 AssertRCReturn(rc, VINF_SUCCESS);
1015 return rc;
1016}
1017
1018DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1019{
1020 uint32_t v = HDA_REG_IND(pState, index);
1021 v ^= (u32Value & v);
1022 HDA_REG_IND(pState, index) = v;
1023 hdaProcessInterrupt(pState);
1024#if 0
1025 if ( v != u32Value
1026 && (INTCTL_SALL(pState) & (1 << ((offset - 0x83) >> 5))))
1027 {
1028 int rc;
1029 rc = hdaProcessInterrupt(pState);
1030 if (RT_FAILURE(rc))
1031 AssertRCReturn(rc, rc);
1032 }
1033#endif
1034 return VINF_SUCCESS;
1035}
1036DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1037{
1038 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1039 if (RT_FAILURE(rc))
1040 AssertRCReturn(rc, VINF_SUCCESS);
1041 return rc;
1042}
1043
1044DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1045{
1046 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1047 if (RT_FAILURE(rc))
1048 AssertRCReturn(rc, VINF_SUCCESS);
1049 return rc;
1050}
1051
1052DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1053{
1054 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1055 if (RT_FAILURE(rc))
1056 AssertRCReturn(rc, VINF_SUCCESS);
1057 return rc;
1058}
1059
1060DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1061{
1062 int rc = VINF_SUCCESS;
1063 uint64_t resp;
1064 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1065 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1066 && !IRS_ICB(pState))
1067 {
1068 uint32_t cmd = IC(pState);
1069 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1070 Log(("hda: IC:%x\n", cmd));
1071 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1072 if (RT_FAILURE(rc))
1073 AssertRCReturn(rc, rc);
1074 rc = pfn(&pState->Codec, cmd, &resp);
1075 if (RT_FAILURE(rc))
1076 AssertRCReturn(rc, rc);
1077 IR(pState) = (uint32_t)resp;
1078 Log(("hda: IR:%x\n", IR(pState)));
1079 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* clear busy, result is ready */
1080 return rc;
1081 }
1082 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1083 && IRS_IRV(pState))
1084 IRS(pState) ^= HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1085 return rc;
1086}
1087
1088DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1089{
1090 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1091 {
1092 RIRBWP(pState) = 0;
1093 }
1094 /*The rest of bits are O, see 6.2.22 */
1095 return VINF_SUCCESS;
1096}
1097
1098DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1099{
1100 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1101 if (RT_FAILURE(rc))
1102 AssertRCReturn(rc, rc);
1103 switch(index)
1104 {
1105 case ICH6_HDA_REG_CORBLBASE:
1106 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1107 pState->u64CORBBase |= pState->au32Regs[index];
1108 break;
1109 case ICH6_HDA_REG_CORBUBASE:
1110 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1111 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1112 break;
1113 case ICH6_HDA_REG_RIRLBASE:
1114 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1115 pState->u64RIRBBase |= pState->au32Regs[index];
1116 break;
1117 case ICH6_HDA_REG_RIRUBASE:
1118 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1119 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1120 break;
1121 case ICH6_HDA_REG_DPLBASE:
1122 /* @todo: first bit has special meaning */
1123 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1124 pState->u64DPBase |= pState->au32Regs[index];
1125 break;
1126 case ICH6_HDA_REG_DPUBASE:
1127 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1128 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1129 break;
1130 default:
1131 AssertMsgFailed(("Invalid index"));
1132 }
1133 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1134 return rc;
1135}
1136
1137DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1138{
1139 uint8_t nv = u32Value;
1140 uint8_t v = RIRBSTS(pState);
1141 RIRBSTS(pState) = (v ^ nv) & v;
1142
1143 return hdaProcessInterrupt(pState);
1144}
1145
1146static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1147{
1148 uint64_t addr;
1149 uint32_t len;
1150 uint32_t ioc;
1151 uint8_t bdle[16];
1152 uint32_t counter;
1153 uint32_t i;
1154 uint32_t sum = 0;
1155 Assert(pBdle && pBdle->u32BdleMaxCvi);
1156 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1157 {
1158 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1159 addr = *(uint64_t *)bdle;
1160 len = *(uint32_t *)&bdle[8];
1161 ioc = *(uint32_t *)&bdle[12];
1162 Log(("hda: %s bdle[%d] a:%lx, len:%x, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc));
1163 sum += len;
1164 }
1165 Log(("hda: sum: %d\n", sum));
1166 for (i = 0; i < 8; ++i)
1167 {
1168 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1169 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
1170 i , counter));
1171 }
1172}
1173static void fetch_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1174{
1175 uint8_t bdle[16];
1176 Assert((u64BaseDMA && pBdle && pBdle->u32BdleMaxCvi));
1177 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1178 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1179 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1180 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1181 dump_bd(pState, pBdle, u64BaseDMA);
1182}
1183
1184static uint32_t read_audio(INTELHDLinkState *pState, int avail, bool *fStop)
1185{
1186 uint8_t tmpbuf[4096];
1187 uint32_t temp;
1188 uint32_t u32Rest = 0;
1189 uint32_t cbRead = 0;
1190 uint32_t to_copy = 0;
1191 /* todo: add input line detection */
1192 PHDABDLEDESC pBdle = &pState->stInBdle;
1193 SWVoiceIn *voice = pState->Codec.voice_pi;
1194 u32Rest = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1195 temp = audio_MIN(u32Rest, (uint32_t)avail);
1196 if (!temp)
1197 {
1198 *fStop = true;
1199 return cbRead;
1200 }
1201 while (temp)
1202 {
1203 int copied;
1204 to_copy = audio_MIN(temp, 4096U);
1205 copied = AUD_read (voice, tmpbuf, to_copy);
1206 Log (("hda: read_audio max=%x to_copy=%x copied=%x\n",
1207 avail, to_copy, copied));
1208 if (!copied)
1209 {
1210 *fStop = true;
1211 break;
1212 }
1213 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, tmpbuf, copied);
1214 temp -= copied;
1215 cbRead += copied;
1216 pBdle->u32BdleCviPos += copied;
1217 }
1218 return cbRead;
1219}
1220static uint32_t write_audio(INTELHDLinkState *pState, int avail, bool *fStop)
1221{
1222 uint8_t tmpbuf[4096];
1223 uint32_t temp;
1224 uint32_t u32Rest;
1225 uint32_t written = 0;
1226 int to_copy = 0;
1227 PHDABDLEDESC pBdle = &pState->stOutBdle;
1228 u32Rest = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1229 temp = audio_MIN(u32Rest, (uint32_t)avail);
1230 if (!temp)
1231 {
1232 *fStop = true;
1233 return written;
1234 }
1235 while (temp)
1236 {
1237 int copied;
1238 to_copy = audio_MIN(temp, 4096U);
1239 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, tmpbuf, to_copy);
1240 copied = AUD_write (pState->Codec.voice_po, tmpbuf, to_copy);
1241 Log (("hda: write_audio max=%x to_copy=%x copied=%x\n",
1242 avail, to_copy, copied));
1243 Assert((copied));
1244 if (!copied)
1245 {
1246 *fStop = true;
1247 break;
1248 }
1249 temp -= copied;
1250 written += copied;
1251 pBdle->u32BdleCviPos += copied;
1252 }
1253 return written;
1254}
1255
1256DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1257{
1258 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1259 return VINF_SUCCESS;
1260}
1261
1262DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1263{
1264 bool fStop = false;
1265 uint64_t u64BaseDMA = 0;
1266 PHDABDLEDESC pBdle = NULL;
1267 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1268 uint32_t nBytes;
1269 uint32_t u32Ctl;
1270 uint32_t *pu32Sts;
1271 uint8_t u8Strm;
1272 uint32_t *pu32Lpib;
1273 uint32_t u32Lcbl;
1274 switch (src)
1275 {
1276 case PO_INDEX:
1277 {
1278 u8Strm = 4;
1279 u32Ctl = SDCTL(pState, 4);
1280 u64BaseDMA = SDBDPL(pState, 4);
1281 u64BaseDMA |= (((uint64_t)SDBDPU(pState, 4)) << 32);
1282 pu32Lpib = &SDLPIB(pState, 4);
1283 pu32Sts = &SDSTS(pState, 4);
1284 u32Lcbl = SDLCBL(pState, 4);
1285 pBdle = &pState->stOutBdle;
1286 pBdle->u32BdleMaxCvi = SDLVI(pState, 4);
1287 break;
1288 }
1289 case PI_INDEX:
1290 {
1291 u8Strm = 0;
1292 u32Ctl = SDCTL(pState, 0);
1293 pu32Lpib = &SDLPIB(pState, 0);
1294 pu32Sts = &SDSTS(pState, 0);
1295 u32Lcbl = SDLCBL(pState, 0);
1296 u64BaseDMA = SDBDPL(pState, 0);
1297 u64BaseDMA |= (((uint64_t)SDBDPU(pState, 0)) << 32);
1298 pBdle = &pState->stInBdle;
1299 pBdle->u32BdleMaxCvi = SDLVI(pState, 0);
1300 break;
1301 }
1302 default:
1303 return;
1304 }
1305 if ( !(u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1306 || !avail
1307 || !u64BaseDMA)
1308 return;
1309 /* Fetch the Buffer Descriptor Entry (BDE). */
1310 fetch_bd(pState, pBdle, u64BaseDMA);
1311 while( avail && !fStop)
1312 {
1313 switch (src)
1314 {
1315 case PO_INDEX:
1316 nBytes = write_audio(pState, avail, &fStop);
1317 break;
1318 case PI_INDEX:
1319 nBytes = read_audio(pState, avail, &fStop);
1320 break;
1321 default:
1322 nBytes = 0;
1323 fStop = true;
1324 AssertMsgFailed(("Unsupported"));
1325 }
1326 /* Update the buffer position and handle Cyclic Buffer Length (CBL) wraparound. */
1327 *pu32Lpib += nBytes;
1328 avail -= nBytes;
1329 if (*pu32Lpib >= u32Lcbl)
1330 *pu32Lpib -= u32Lcbl;
1331
1332 /* Optionally write back the current DMA position. */
1333 if (pState->u64DPBase & DPBASE_ENABLED)
1334 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
1335 (pState->u64DPBase & DPBASE_ADDR_MASK) + u8Strm*8, pu32Lpib, sizeof(*pu32Lpib));
1336
1337 /* Process end of buffer condition. */
1338 if (pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1339 {
1340 if (pBdle->fBdleCviIoc)
1341 {
1342 *pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1343 hdaProcessInterrupt(pState);
1344 }
1345 pBdle->u32BdleCviPos = 0;
1346 pBdle->u32BdleCvi++;
1347 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1348 pBdle->u32BdleCvi = 0;
1349 fStop = true; /* Give the guest a chance to refill (or empty) buffers. */
1350
1351 /* Read the next BDE unless we're exiting. */
1352 if (!fStop)
1353 fetch_bd(pState, pBdle, u64BaseDMA);
1354 }
1355 }
1356}
1357
1358/**
1359 * Handle register read operation.
1360 *
1361 * Looks up and calls appropriate handler.
1362 *
1363 * @note: while implementation was detected so called "forgotten" or "hole" registers
1364 * which description is missed in RPM, datasheet or spec.
1365 *
1366 * @returns VBox status code.
1367 *
1368 * @param pState The device state structure.
1369 * @param uOffset Register offset in memory-mapped frame.
1370 * @param pv Where to fetch the value.
1371 * @param cb Number of bytes to write.
1372 * @thread EMT
1373 */
1374PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1375{
1376 int rc = VINF_SUCCESS;
1377 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1378 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1379 int index = hdaLookup(&pThis->hda, u32Offset);
1380 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1381 {
1382 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1383 }
1384 Assert( index != -1
1385 && cb <= 4);
1386 if (index != -1)
1387 {
1388 uint32_t mask = 0;
1389 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1390 uint32_t v = 0;
1391 switch(cb)
1392 {
1393 case 1: mask = 0x000000ff; break;
1394 case 2: mask = 0x0000ffff; break;
1395 case 3: mask = 0x00ffffff; break;
1396 case 4: mask = 0xffffffff; break;
1397 }
1398 mask <<= shift;
1399 rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1400 *(uint32_t *)pv = (v & mask) >> shift;
1401 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
1402 return rc;
1403 }
1404 *(uint32_t *)pv = 0xFF;
1405 Log(("hda: hole at %X is accessed for read\n", u32Offset));
1406 return rc;
1407}
1408
1409/**
1410 * Handle register write operation.
1411 *
1412 * Looks up and calls appropriate handler.
1413 *
1414 * @returns VBox status code.
1415 *
1416 * @param pState The device state structure.
1417 * @param uOffset Register offset in memory-mapped frame.
1418 * @param pv Where to fetch the value.
1419 * @param cb Number of bytes to write.
1420 * @thread EMT
1421 */
1422PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1423{
1424 int rc = VINF_SUCCESS;
1425 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1426 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1427 int index = hdaLookup(&pThis->hda, u32Offset);
1428 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1429 {
1430 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1431 }
1432 Assert( index != -1
1433 && cb <= 4);
1434 if (index != -1)
1435 {
1436 uint32_t v = pThis->hda.au32Regs[index];
1437 uint32_t mask = 0;
1438 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1439 switch(cb)
1440 {
1441 case 1: mask = 0xffffff00; break;
1442 case 2: mask = 0xffff0000; break;
1443 case 3: mask = 0xff000000; break;
1444 case 4: mask = 0x00000000; break;
1445 }
1446 mask <<= shift;
1447 *(uint32_t *)pv = ((v & mask) | (*(uint32_t *)pv & ~mask)) >> shift;
1448 rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
1449 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
1450 return rc;
1451 }
1452 Log(("hda: hole at %X is accessed for write\n", u32Offset));
1453 return rc;
1454}
1455
1456/**
1457 * Callback function for mapping a PCI I/O region.
1458 *
1459 * @return VBox status code.
1460 * @param pPciDev Pointer to PCI device.
1461 * Use pPciDev->pDevIns to get the device instance.
1462 * @param iRegion The region number.
1463 * @param GCPhysAddress Physical address of the region.
1464 * If iType is PCI_ADDRESS_SPACE_IO, this is an
1465 * I/O port, else it's a physical address.
1466 * This address is *NOT* relative
1467 * to pci_mem_base like earlier!
1468 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
1469 */
1470static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
1471 RTGCPHYS GCPhysAddress, uint32_t cb,
1472 PCIADDRESSSPACE enmType)
1473{
1474 int rc;
1475 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1476 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1477 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1478
1479 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1480 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
1481 hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
1482
1483 if (RT_FAILURE(rc))
1484 return rc;
1485
1486 pThis->hda.addrMMReg = GCPhysAddress;
1487 return VINF_SUCCESS;
1488}
1489
1490/**
1491 * Saves a state of the HDA device.
1492 *
1493 * @returns VBox status code.
1494 * @param pDevIns The device instance.
1495 * @param pSSMHandle The handle to save the state to.
1496 */
1497static DECLCALLBACK(int) hdaSaveExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1498{
1499 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1500 /* Save Codec nodes states */
1501 codecSaveState(&pThis->hda.Codec, pSSMHandle);
1502 /* Save MMIO registers */
1503 SSMR3PutMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1504 /* Save HDA dma counters */
1505 SSMR3PutMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
1506 SSMR3PutMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
1507 SSMR3PutMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
1508 uint8_t voices = AUD_is_active_in(pThis->hda.Codec.voice_pi)? RT_BIT(0):0;
1509 voices |= AUD_is_active_in(pThis->hda.Codec.voice_mc)? RT_BIT(1):0;
1510 voices |= AUD_is_active_out(pThis->hda.Codec.voice_po)? RT_BIT(2):0;
1511 SSMR3PutU8(pSSMHandle, voices);
1512 return VINF_SUCCESS;
1513}
1514
1515/**
1516 * Loads a saved HDA device state.
1517 *
1518 * @returns VBox status code.
1519 * @param pDevIns The device instance.
1520 * @param pSSMHandle The handle to the saved state.
1521 * @param uVersion The data unit version number.
1522 * @param uPass The data pass.
1523 */
1524static DECLCALLBACK(int) hdaLoadExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1525 uint32_t uVersion, uint32_t uPass)
1526{
1527 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1528 /* Load Codec nodes states */
1529 AssertMsgReturn (uVersion == HDA_SSM_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1530 Assert (uPass == SSM_PASS_FINAL); NOREF(uPass);
1531
1532 codecLoadState(&pThis->hda.Codec, pSSMHandle);
1533 /* Load MMIO registers */
1534 SSMR3GetMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1535 /* Load HDA dma counters */
1536 SSMR3GetMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
1537 SSMR3GetMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
1538 SSMR3GetMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
1539 uint8_t voices;
1540 SSMR3GetU8(pSSMHandle, &voices);
1541 AUD_set_active_in(pThis->hda.Codec.voice_pi, voices & RT_BIT(0));
1542 AUD_set_active_in(pThis->hda.Codec.voice_mc, voices & RT_BIT(1));
1543 AUD_set_active_out(pThis->hda.Codec.voice_po, voices & RT_BIT(2));
1544 pThis->hda.u64CORBBase = CORBLBASE(&pThis->hda);
1545 pThis->hda.u64CORBBase |= ((uint64_t)CORBUBASE(&pThis->hda)) << 32;
1546 pThis->hda.u64RIRBBase = RIRLBASE(&pThis->hda);
1547 pThis->hda.u64RIRBBase |= ((uint64_t)RIRUBASE(&pThis->hda)) << 32;
1548 pThis->hda.u64DPBase = DPLBASE(&pThis->hda);
1549 pThis->hda.u64DPBase |= ((uint64_t)DPUBASE(&pThis->hda)) << 32;
1550 return VINF_SUCCESS;
1551}
1552
1553/**
1554 * Reset notification.
1555 *
1556 * @returns VBox status.
1557 * @param pDevIns The device instance data.
1558 *
1559 * @remark The original sources didn't install a reset handler, but it seems to
1560 * make sense to me so we'll do it.
1561 */
1562static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns)
1563{
1564 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1565 GCAP(&pThis->hda) = 0x4401; /* see 6.2.1 */
1566 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
1567 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1568 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1569 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
1570 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
1571 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
1572 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
1573 CORBRP(&pThis->hda) = 0x0;
1574 RIRBWP(&pThis->hda) = 0x0;
1575
1576 LogRel(("hda: inter HDA reset.\n"));
1577 //** @todo r=michaln: There should be LogRel statements when the guest initializes
1578 // or resets the HDA chip, and possibly also when opening the PCM streams.
1579 pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
1580
1581 if (pThis->hda.pu32CorbBuf)
1582 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
1583 else
1584 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
1585
1586 pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
1587 if (pThis->hda.pu64RirbBuf)
1588 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
1589 else
1590 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
1591
1592 /* Accoding to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
1593 * bits are reserved for stream number 18.2.33 */
1594 SDCTL(&pThis->hda, 0) = 0x40000;
1595 SDCTL(&pThis->hda, 1) = 0x40000;
1596 SDCTL(&pThis->hda, 2) = 0x40000;
1597 SDCTL(&pThis->hda, 3) = 0x40000;
1598 SDCTL(&pThis->hda, 4) = 0x40000;
1599 SDCTL(&pThis->hda, 5) = 0x40000;
1600 SDCTL(&pThis->hda, 6) = 0x40000;
1601 SDCTL(&pThis->hda, 7) = 0x40000;
1602
1603 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1604 SDFIFOS(&pThis->hda, 0) = 0x77;
1605 SDFIFOS(&pThis->hda, 1) = 0x77;
1606 SDFIFOS(&pThis->hda, 2) = 0x77;
1607 SDFIFOS(&pThis->hda, 3) = 0x77;
1608 SDFIFOS(&pThis->hda, 4) = 0xBF;
1609 SDFIFOS(&pThis->hda, 5) = 0xBF;
1610 SDFIFOS(&pThis->hda, 6) = 0xBF;
1611 SDFIFOS(&pThis->hda, 7) = 0xBF;
1612
1613 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
1614 STATESTS(&pThis->hda) = 0x1;
1615
1616 Log(("hda: reset finished\n"));
1617}
1618
1619/**
1620 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1621 */
1622static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
1623 const char *pszIID)
1624{
1625 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
1626 Assert(&pThis->hda.IBase == pInterface);
1627
1628 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
1629 return NULL;
1630}
1631
1632//#define HDA_AS_PCI_EXPRESS
1633
1634/**
1635 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1636 */
1637static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
1638 PCFGMNODE pCfgHandle)
1639{
1640 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1641 INTELHDLinkState *s = &pThis->hda;
1642 int rc;
1643
1644 Assert(iInstance == 0);
1645 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1646
1647 /*
1648 * Validations.
1649 */
1650 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
1651 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1652 N_ ("Invalid configuration for the INTELHD device"));
1653
1654 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
1655 // poll some register(s).
1656
1657 /*
1658 * Initialize data (most of it anyway).
1659 */
1660 s->pDevIns = pDevIns;
1661 /* IBase */
1662 s->IBase.pfnQueryInterface = hdaQueryInterface;
1663
1664 /* PCI Device (the assertions will be removed later) */
1665#if 0
1666 /* Linux kernel has whitelist for MSI-enabled HDA, this card seems to be there. */
1667 PCIDevSetVendorId (&pThis->dev, 0x103c); /* HP. */
1668 PCIDevSetDeviceId (&pThis->dev, 0x30f7); /* HP Pavilion dv4t-1300 */
1669#else
1670#if 1
1671 PCIDevSetVendorId (&pThis->dev, 0x8086); /* 00 ro - intel. */
1672 PCIDevSetDeviceId (&pThis->dev, 0x2668); /* 02 ro - 82801 / 82801aa(?). */
1673#else
1674 PCIDevSetVendorId (&pThis->dev, 0x10de); /* nVidia */
1675 PCIDevSetDeviceId (&pThis->dev, 0x0028); /* HDA */
1676#endif
1677#endif
1678 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
1679 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
1680 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
1681 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
1682 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
1683 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
1684 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
1685 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
1686 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
1687 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
1688 verb F20 should provide device/codec recognition. */
1689 PCIDevSetSubSystemVendorId (&pThis->dev, 0x0000); /* 2c ro - intel.) */
1690 PCIDevSetSubSystemId (&pThis->dev, 0x0000); /* 2e ro. */
1691 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
1692 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */
1693
1694#if defined(HDA_AS_PCI_EXPRESS)
1695 PCIDevSetCapabilityList (&pThis->dev, 0x80);
1696#elif defined(VBOX_WITH_MSI_DEVICES)
1697 PCIDevSetCapabilityList (&pThis->dev, 0x60);
1698#else
1699 PCIDevSetCapabilityList (&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
1700#endif
1701
1702 //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
1703 // of these values needs to be properly documented!
1704 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1705 PCIDevSetByte(&pThis->dev, 0x40, 0x01);
1706
1707 /* Power Management */
1708 PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
1709 PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
1710 PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
1711
1712#ifdef HDA_AS_PCI_EXPRESS
1713 /* PCI Express */
1714 PCIDevSetByte (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
1715 PCIDevSetByte (&pThis->dev, 0x80 + 1, 0x60); /* next */
1716 /* Device flags */
1717 PCIDevSetWord (&pThis->dev, 0x80 + 2,
1718 /* version */ 0x1 |
1719 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
1720 /* MSI */ (100) << 9
1721 );
1722 /* Device capabilities */
1723 PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
1724 /* Device control */
1725 PCIDevSetWord (&pThis->dev, 0x80 + 8, 0);
1726 /* Device status */
1727 PCIDevSetWord (&pThis->dev, 0x80 + 10, 0);
1728 /* Link caps */
1729 PCIDevSetDWord (&pThis->dev, 0x80 + 12, 0);
1730 /* Link control */
1731 PCIDevSetWord (&pThis->dev, 0x80 + 16, 0);
1732 /* Link status */
1733 PCIDevSetWord (&pThis->dev, 0x80 + 18, 0);
1734 /* Slot capabilities */
1735 PCIDevSetDWord (&pThis->dev, 0x80 + 20, 0);
1736 /* Slot control */
1737 PCIDevSetWord (&pThis->dev, 0x80 + 24, 0);
1738 /* Slot status */
1739 PCIDevSetWord (&pThis->dev, 0x80 + 26, 0);
1740 /* Root control */
1741 PCIDevSetWord (&pThis->dev, 0x80 + 28, 0);
1742 /* Root capabilities */
1743 PCIDevSetWord (&pThis->dev, 0x80 + 30, 0);
1744 /* Root status */
1745 PCIDevSetDWord (&pThis->dev, 0x80 + 32, 0);
1746 /* Device capabilities 2 */
1747 PCIDevSetDWord (&pThis->dev, 0x80 + 36, 0);
1748 /* Device control 2 */
1749 PCIDevSetQWord (&pThis->dev, 0x80 + 40, 0);
1750 /* Link control 2 */
1751 PCIDevSetQWord (&pThis->dev, 0x80 + 48, 0);
1752 /* Slot control 2 */
1753 PCIDevSetWord (&pThis->dev, 0x80 + 56, 0);
1754#endif
1755
1756 /*
1757 * Register the PCI device.
1758 */
1759 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
1760 if (RT_FAILURE (rc))
1761 return rc;
1762
1763 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
1764 hdaMap);
1765 if (RT_FAILURE (rc))
1766 return rc;
1767
1768#ifdef VBOX_WITH_MSI_DEVICES
1769 PDMMSIREG aMsiReg;
1770 aMsiReg.cVectors = 1;
1771 aMsiReg.iCapOffset = 0x60;
1772 aMsiReg.iNextOffset = 0x50;
1773 aMsiReg.iMsiFlags = 0;
1774 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
1775 if (RT_FAILURE (rc))
1776 {
1777 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
1778 PCIDevSetCapabilityList (&pThis->dev, 0x50);
1779 }
1780#endif
1781
1782 rc = PDMDevHlpSSMRegister (pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
1783 if (RT_FAILURE (rc))
1784 return rc;
1785
1786 /*
1787 * Attach driver.
1788 */
1789 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
1790 &s->pDrvBase, "Audio Driver Port");
1791 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1792 Log (("hda: No attached driver!\n"));
1793 else if (RT_FAILURE (rc))
1794 {
1795 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
1796 return rc;
1797 }
1798
1799
1800
1801 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
1802 rc = codecConstruct(&pThis->hda.Codec, STAC9220_CODEC);
1803 if (RT_FAILURE(rc))
1804 AssertRCReturn(rc, rc);
1805 hdaReset (pDevIns);
1806 pThis->hda.Codec.id = 0;
1807 pThis->hda.Codec.pfnTransfer = hdaTransfer;
1808 pThis->hda.Codec.pfnReset = hdaCodecReset;
1809 /*
1810 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
1811 * hdaReset shouldn't affects these registers.
1812 */
1813 WAKEEN(&pThis->hda) = 0x0;
1814 STATESTS(&pThis->hda) = 0x0;
1815
1816 return VINF_SUCCESS;
1817}
1818
1819/**
1820 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1821 */
1822static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
1823{
1824 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1825
1826 int rc = codecDestruct(&pThis->hda.Codec);
1827 AssertRC(rc);
1828 if (pThis->hda.pu32CorbBuf)
1829 RTMemFree(pThis->hda.pu32CorbBuf);
1830 if (pThis->hda.pu64RirbBuf)
1831 RTMemFree(pThis->hda.pu64RirbBuf);
1832 return VINF_SUCCESS;
1833}
1834
1835/**
1836 * The device registration structure.
1837 */
1838const PDMDEVREG g_DeviceICH6_HDA =
1839{
1840 /* u32Version */
1841 PDM_DEVREG_VERSION,
1842 /* szName */
1843 "hda",
1844 /* szRCMod */
1845 "",
1846 /* szR0Mod */
1847 "",
1848 /* pszDescription */
1849 "ICH IntelHD Audio Controller",
1850 /* fFlags */
1851 PDM_DEVREG_FLAGS_DEFAULT_BITS,
1852 /* fClass */
1853 PDM_DEVREG_CLASS_AUDIO,
1854 /* cMaxInstances */
1855 1,
1856 /* cbInstance */
1857 sizeof(PCIINTELHDLinkState),
1858 /* pfnConstruct */
1859 hdaConstruct,
1860 /* pfnDestruct */
1861 hdaDestruct,
1862 /* pfnRelocate */
1863 NULL,
1864 /* pfnIOCtl */
1865 NULL,
1866 /* pfnPowerOn */
1867 NULL,
1868 /* pfnReset */
1869 hdaReset,
1870 /* pfnSuspend */
1871 NULL,
1872 /* pfnResume */
1873 NULL,
1874 /* pfnAttach */
1875 NULL,
1876 /* pfnDetach */
1877 NULL,
1878 /* pfnQueryInterface. */
1879 NULL,
1880 /* pfnInitComplete */
1881 NULL,
1882 /* pfnPowerOff */
1883 NULL,
1884 /* pfnSoftReset */
1885 NULL,
1886 /* u32VersionEnd */
1887 PDM_DEVREG_VERSION
1888};
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