VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 34497

Last change on this file since 34497 was 34460, checked in by vboxsync, 14 years ago

Audio/HDA: temporary disabled(FIFOW), hdaTransfer doesn't ignore fStop returned from Read/Write handlers, reorganization of hdaReset.
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File size: 100.0 KB
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1/* $Id: DevIchIntelHDA.cpp 34460 2010-11-29 12:47:39Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/pdmdev.h>
23#include <iprt/assert.h>
24#include <iprt/uuid.h>
25#include <iprt/string.h>
26#include <iprt/mem.h>
27#include <iprt/asm.h>
28
29#include "../Builtins.h"
30
31extern "C" {
32#include "audio.h"
33}
34#include "DevCodec.h"
35
36#undef LOG_VOICES
37#ifndef VBOX
38//#define USE_MIXER
39#else
40#define USE_MIXER
41#endif
42#define VBOX_WITH_INTEL_HDA
43
44#define HDA_SSM_VERSION 1
45PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
46PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
47static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
48
49/* Registers */
50#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
51#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
52#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
53#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
54#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
55#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
56#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
57#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
58#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
59#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
60
61#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
62#define GCAP(pState) (HDA_REG((pState), GCAP))
63
64#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
65#define VMIN(pState) (HDA_REG((pState), VMIN))
66
67#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
68#define VMAJ(pState) (HDA_REG((pState), VMAJ))
69
70#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
71#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
72
73#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
74#define INPAY(pState) (HDA_REG((pState), INPAY))
75
76#define ICH6_HDA_REG_GCTL (5)
77#define ICH6_HDA_GCTL_RST_SHIFT (0)
78#define ICH6_HDA_GCTL_FSH_SHIFT (1)
79#define ICH6_HDA_GCTL_UR_SHIFT (8)
80#define GCTL(pState) (HDA_REG((pState), GCTL))
81
82#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
83#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
84
85#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
86#define STATESTS(pState) (HDA_REG((pState), STATESTS))
87#define ICH6_HDA_STATES_SCSF 0x7
88
89#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
90#define ICH6_HDA_GSTS_FSH_SHIFT (1)
91#define GSTS(pState) (HDA_REG(pState, GSTS))
92
93#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
94#define ICH6_HDA_INTCTL_GIE_SHIFT 31
95#define ICH6_HDA_INTCTL_CIE_SHIFT 30
96#define ICH6_HDA_INTCTL_S0_SHIFT (0)
97#define ICH6_HDA_INTCTL_S1_SHIFT (1)
98#define ICH6_HDA_INTCTL_S2_SHIFT (2)
99#define ICH6_HDA_INTCTL_S3_SHIFT (3)
100#define ICH6_HDA_INTCTL_S4_SHIFT (4)
101#define ICH6_HDA_INTCTL_S5_SHIFT (5)
102#define ICH6_HDA_INTCTL_S6_SHIFT (6)
103#define ICH6_HDA_INTCTL_S7_SHIFT (7)
104#define INTCTL(pState) (HDA_REG((pState), INTCTL))
105#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
106#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
107#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
108#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
109
110/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
111 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
112 * the datasheet.
113 */
114#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
115#define SSYNC(pState) (HDA_REG((pState), SSYNC))
116
117#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
118#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
119#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
120#define ICH6_HDA_INTSTS_S0_SHIFT (0)
121#define ICH6_HDA_INTSTS_S1_SHIFT (1)
122#define ICH6_HDA_INTSTS_S2_SHIFT (2)
123#define ICH6_HDA_INTSTS_S3_SHIFT (3)
124#define ICH6_HDA_INTSTS_S4_SHIFT (4)
125#define ICH6_HDA_INTSTS_S5_SHIFT (5)
126#define ICH6_HDA_INTSTS_S6_SHIFT (6)
127#define ICH6_HDA_INTSTS_S7_SHIFT (7)
128#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
129#define INTSTS(pState) (HDA_REG((pState), INTSTS))
130#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
131#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
132#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
133#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
134
135#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
136#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
137#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
138#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
139#define ICH6_HDA_REG_CORBWP 15 /* 48 */
140#define ICH6_HDA_REG_CORBRP 16 /* 4A */
141#define ICH6_HDA_CORBRP_RST_SHIFT 15
142#define ICH6_HDA_CORBRP_WP_SHIFT 0
143#define ICH6_HDA_CORBRP_WP_MASK 0xFF
144
145#define CORBRP(pState) (HDA_REG(pState, CORBRP))
146#define CORBWP(pState) (HDA_REG(pState, CORBWP))
147
148#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
149#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
150#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
151
152#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
153
154
155#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
156#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
157#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
158
159#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
160#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
161#define ICH6_HDA_CORBSIZE_SZ 0x3
162#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
163#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
164/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
165
166#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
167#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
168
169#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
170#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
171
172#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
173#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
174#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
175#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
176
177#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
178#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
179#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
180
181#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
182#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
183#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
184#define ICH6_HDA_ROI_DMA_SHIFT (2)
185#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
186#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
187#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
188#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
189
190#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
191#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
192#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
193#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
194#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
195#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
196
197#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
198#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
199#define ICH6_HDA_RIRBSIZE_SZ 0x3
200
201#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
202#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
203
204
205#define ICH6_HDA_REG_IC 27 /* 0x60 */
206#define IC(pState) (HDA_REG(pState, IC))
207#define ICH6_HDA_REG_IR 28 /* 0x64 */
208#define IR(pState) (HDA_REG(pState, IR))
209#define ICH6_HDA_REG_IRS 29 /* 0x68 */
210#define ICH6_HDA_IRS_ICB_SHIFT (0)
211#define ICH6_HDA_IRS_IRV_SHIFT (1)
212#define IRS(pState) (HDA_REG(pState, IRS))
213#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
214#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
215
216#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
217#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
218#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
219#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
220#define DPBASE_ENABLED 1
221#define DPBASE_ADDR_MASK (~0x7f)
222
223#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
224#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
225/* Note: sdnum here _MUST_ be stream reg number [0,7] */
226#define HDA_STREAM_REG2(pState, name, sdnum) (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
227
228#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
229#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
230#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
231#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
232#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
233#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
234#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
235#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
236
237#define SD(func, num) SD##num##func
238#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
239#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
240#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
241#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
242#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
243#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
244#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
245#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
246#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
247
248#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
249#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
250#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
251#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
252#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
253#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
254#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
255#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
256
257#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
258#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
259#define ICH6_HDA_SDSTS_DE_SHIFT (4)
260#define ICH6_HDA_SDSTS_FE_SHIFT (3)
261#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
262
263#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
264#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
265#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
266#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
267#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
268#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
269#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
270#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
271
272#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
273
274#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
275#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
276#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
277#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
278#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
279#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
280#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
281#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
282
283#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
284
285#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
286#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
287#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
288#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
289#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
290#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
291#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
292#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
293
294#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
295
296#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
297#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
298#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
299#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
300#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
301#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
302#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
303#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
304
305/*
306 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
307 */
308#define HDA_SDFIFOW_8B (0x2)
309#define HDA_SDFIFOW_16B (0x3)
310#define HDA_SDFIFOW_32B (0x4)
311#define SDFIFOW(pState, num) HDA_REG((pState), SD(FIFOW, num))
312
313#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
314#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
315#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
316#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
317#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
318#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
319#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
320#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
321
322/*
323 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
324 * formula: size - 1
325 * Other values not listed are not supported.
326 */
327#define HDA_SDONFIFO_16B (0xF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
328#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
329#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
330#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
331#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
332#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
333#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
334#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
335#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
336
337#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
338#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
339#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
340#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
341#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
342#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
343#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
344#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
345
346#define SDFMT(pState, num) (HDA_REG((pState), SD(FMT, num)))
347#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
348#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
349#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
350#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
351#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
352#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
353#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
354#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
355
356#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
357#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
358#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
359#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
360#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
361#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
362#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
363#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
364
365#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
366
367#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
368#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
369#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
370#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
371#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
372#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
373#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
374#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
375
376#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
377
378/* Predicates */
379
380typedef struct HDABDLEDESC
381{
382 uint64_t u64BdleCviAddr;
383 uint32_t u32BdleMaxCvi;
384 uint32_t u32BdleCvi;
385 uint32_t u32BdleCviLen;
386 uint32_t u32BdleCviPos;
387 bool fBdleCviIoc;
388 uint32_t cbUnderFifoW;
389 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
390} HDABDLEDESC, *PHDABDLEDESC;
391
392typedef struct HDASTREAMTRANSFERDESC
393{
394 uint64_t u64BaseDMA;
395 uint32_t u32Ctl;
396 uint32_t *pu32Sts;
397 uint8_t u8Strm;
398 uint32_t *pu32Lpib;
399 uint32_t u32Cbl;
400 uint32_t u32Fifos;
401} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
402
403typedef struct INTELHDLinkState
404{
405 /** Pointer to the device instance. */
406 PPDMDEVINSR3 pDevIns;
407 /** Pointer to the connector of the attached audio driver. */
408 PPDMIAUDIOCONNECTOR pDrv;
409 /** Pointer to the attached audio driver. */
410 PPDMIBASE pDrvBase;
411 /** The base interface for LUN\#0. */
412 PDMIBASE IBase;
413 RTGCPHYS addrMMReg;
414 uint32_t au32Regs[113];
415 HDABDLEDESC stInBdle;
416 HDABDLEDESC stOutBdle;
417 HDABDLEDESC stMicBdle;
418 /* Interrupt on completion */
419 bool fCviIoc;
420 uint64_t u64CORBBase;
421 uint64_t u64RIRBBase;
422 uint64_t u64DPBase;
423 /* pointer on CORB buf */
424 uint32_t *pu32CorbBuf;
425 /* size in bytes of CORB buf */
426 uint32_t cbCorbBuf;
427 /* pointer on RIRB buf */
428 uint64_t *pu64RirbBuf;
429 /* size in bytes of RIRB buf */
430 uint32_t cbRirbBuf;
431 /* indicates if HDA in reset. */
432 bool fInReset;
433 CODECState Codec;
434 uint8_t u8Counter;
435} INTELHDLinkState, *PINTELHDLinkState;
436
437#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
438#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
439
440#define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In, \
441 SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
442#define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out, \
443 SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
444
445
446
447
448typedef struct PCIINTELHDLinkState
449{
450 PCIDevice dev;
451 INTELHDLinkState hda;
452} PCIINTELHDLinkState;
453
454
455DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
456DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
457DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
458DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
459DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
460DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
461DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
462DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
463DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
464DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
465DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
466DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
467DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
468DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
469DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
470DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
471DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
472DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
473DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
474
475DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
476DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
477DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
478DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
479DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
480DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
481DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
482DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
483DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
484DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
485DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
486DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
487DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
488DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
489DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
490
491static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc);
492static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
493static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
494#ifdef LOG_ENABLED
495static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
496#endif
497
498/* see 302349 p 6.2*/
499const static struct stIchIntelHDRegMap
500{
501 /** Register offset in the register space. */
502 uint32_t offset;
503 /** Size in bytes. Registers of size > 4 are in fact tables. */
504 uint32_t size;
505 /** Readable bits. */
506 uint32_t readable;
507 /** Writable bits. */
508 uint32_t writable;
509 /** Read callback. */
510 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
511 /** Write callback. */
512 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
513 /** Abbreviated name. */
514 const char *abbrev;
515 /** Full name. */
516 const char *name;
517} s_ichIntelHDRegMap[] =
518{
519 /* offset size read mask write mask read callback write callback abbrev full name */
520 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
521 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
522 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
523 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
524 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
525 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
526 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
527 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
528 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
529 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
530 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
531 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
532 //** @todo r=michaln: Are guests really not reading the WALCLK register at all?
533 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
534 //** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
535 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
536 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
537 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
538 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
539 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
540 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
541 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
542 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
543 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
544 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
545 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
546 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
547 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
548 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
549 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
550 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
551 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
552 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
553 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
554 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
555
556 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
557 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
558 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
559 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
560 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
561 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
562 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
563 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FMT" , "ISD0 Format" },
564 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
565 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
566
567 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
568 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
569 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
570 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
571 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
572 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
573 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
574 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FMT" , "ISD1 Format" },
575 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
576 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
577
578 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
579 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
580 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
581 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
582 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
583 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
584 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
585 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FMT" , "ISD2 Format" },
586 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
587 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
588
589 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
590 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
591 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
592 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
593 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
594 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
595 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
596 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FMT" , "ISD3 Format" },
597 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
598 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
599
600 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
601 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
602 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
603 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
604 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
605 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
606 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
607 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FMT" , "OSD0 Format" },
608 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
609 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
610
611 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
612 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
613 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
614 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
615 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
616 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
617 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
618 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FMT" , "OSD1 Format" },
619 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
620 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
621
622 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
623 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
624 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
625 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
626 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
627 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
628 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
629 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FMT" , "OSD2 Format" },
630 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
631 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
632
633 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
634 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
635 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
636 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
637 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
638 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
639 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
640 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FMT" , "OSD3 Format" },
641 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
642 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
643};
644
645static void inline hdaUpdatePosBuf(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
646{
647 if (pState->u64DPBase & DPBASE_ENABLED)
648 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
649 (pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
650}
651static uint32_t inline hdaFifoWToSz(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
652{
653#if 0
654 switch(HDA_STREAM_REG2(pState, FIFOW, pStreamDesc->u8Strm))
655 {
656 case HDA_SDFIFOW_8B: return 8;
657 case HDA_SDFIFOW_16B: return 16;
658 case HDA_SDFIFOW_32B: return 32;
659 default:
660 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
661 }
662#endif
663 return 0;
664}
665
666static int hdaProcessInterrupt(INTELHDLinkState* pState)
667{
668#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
669 ( INTCTL_SX((pState), num) \
670 && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
671 bool fIrq = false;
672 if( INTCTL_CIE(pState)
673 && ( RIRBSTS_RINTFL(pState)
674 || RIRBSTS_RIRBOIS(pState)
675 || STATESTS(pState)))
676 {
677 fIrq = true;
678 }
679 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
680 || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
681 {
682 fIrq = true;
683 }
684 if (INTCTL_GIE(pState))
685 {
686 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
687 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
688 }
689 return VINF_SUCCESS;
690}
691
692static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
693{
694 int index = 0;
695 //** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
696 for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
697 {
698 if ( u32Offset >= s_ichIntelHDRegMap[index].offset
699 && u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
700 {
701 return index;
702 }
703 }
704 /* Aliases HDA spec 3.3.45 */
705 switch(u32Offset)
706 {
707 case 0x2084:
708 return HDA_REG_IND_NAME(SD0LPIB);
709 case 0x20A4:
710 return HDA_REG_IND_NAME(SD1LPIB);
711 case 0x20C4:
712 return HDA_REG_IND_NAME(SD2LPIB);
713 case 0x20E4:
714 return HDA_REG_IND_NAME(SD3LPIB);
715 case 0x2104:
716 return HDA_REG_IND_NAME(SD4LPIB);
717 case 0x2124:
718 return HDA_REG_IND_NAME(SD5LPIB);
719 case 0x2144:
720 return HDA_REG_IND_NAME(SD6LPIB);
721 case 0x2164:
722 return HDA_REG_IND_NAME(SD7LPIB);
723 }
724 return -1;
725}
726
727static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
728{
729 int rc = VINF_SUCCESS;
730 if (fLocal)
731 {
732 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
733 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
734 if (RT_FAILURE(rc))
735 AssertRCReturn(rc, rc);
736#ifdef DEBUG_CMD_BUFFER
737 uint8_t i = 0;
738 do
739 {
740 Log(("hda: corb%02x: ", i));
741 uint8_t j = 0;
742 do
743 {
744 const char *prefix;
745 if ((i + j) == CORBRP(pState))
746 prefix = "[R]";
747 else if ((i + j) == CORBWP(pState))
748 prefix = "[W]";
749 else
750 prefix = " "; /* three spaces */
751 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
752 j++;
753 } while (j < 8);
754 Log(("\n"));
755 i += 8;
756 } while(i != 0);
757#endif
758 }
759 else
760 {
761 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
762 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
763 if (RT_FAILURE(rc))
764 AssertRCReturn(rc, rc);
765#ifdef DEBUG_CMD_BUFFER
766 uint8_t i = 0;
767 do {
768 Log(("hda: rirb%02x: ", i));
769 uint8_t j = 0;
770 do {
771 const char *prefix;
772 if ((i + j) == RIRBWP(pState))
773 prefix = "[W]";
774 else
775 prefix = " ";
776 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
777 } while (++j < 8);
778 Log(("\n"));
779 i += 8;
780 } while (i != 0);
781#endif
782 }
783 return rc;
784}
785
786static int hdaCORBCmdProcess(INTELHDLinkState *pState)
787{
788 int rc;
789 uint8_t corbRp;
790 uint8_t corbWp;
791 uint8_t rirbWp;
792
793 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
794
795 rc = hdaCmdSync(pState, true);
796 if (RT_FAILURE(rc))
797 AssertRCReturn(rc, rc);
798 corbRp = CORBRP(pState);
799 corbWp = CORBWP(pState);
800 rirbWp = RIRBWP(pState);
801 Assert((corbWp != corbRp));
802 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
803 while (corbRp != corbWp)
804 {
805 uint32_t cmd;
806 uint64_t resp;
807 corbRp++;
808 cmd = pState->pu32CorbBuf[corbRp];
809 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
810 if (RT_FAILURE(rc))
811 AssertRCReturn(rc, rc);
812 Assert(pfn);
813 (rirbWp)++;
814 rc = pfn(&pState->Codec, cmd, &resp);
815 if (RT_FAILURE(rc))
816 AssertRCReturn(rc, rc);
817 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
818 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
819 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
820 {
821 Log(("hda: unexpected unsolicited response.\n"));
822 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
823 return rc;
824 }
825 pState->pu64RirbBuf[rirbWp] = resp;
826 pState->u8Counter++;
827 if (pState->u8Counter == RINTCNT_N(pState))
828 break;
829 }
830 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
831 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
832 rc = hdaCmdSync(pState, false);
833 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
834 if (RIRBCTL_RIRB_RIC(pState))
835 {
836 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
837 pState->u8Counter = 0;
838 rc = hdaProcessInterrupt(pState);
839 }
840 if (RT_FAILURE(rc))
841 AssertRCReturn(rc, rc);
842 return rc;
843}
844
845static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
846{
847 Log(("hda: reset of stream (%d) started\n", u8Strm));
848 Assert(( pState
849 && pBdle
850 && pStreamDesc
851 && u8Strm <= 7));
852 memset(pBdle, 0, sizeof(HDABDLEDESC));
853 *pStreamDesc->pu32Lpib = 0;
854 *pStreamDesc->pu32Sts = 0;
855 /* According to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
856 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
857 HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
858
859 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
860 HDA_STREAM_REG2(pState, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
861 HDA_STREAM_REG2(pState, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
862 HDA_STREAM_REG2(pState, CBL, u8Strm) = 0;
863 HDA_STREAM_REG2(pState, LVI, u8Strm) = 0;
864 HDA_STREAM_REG2(pState, FMT, u8Strm) = 0;
865 HDA_STREAM_REG2(pState, BDPU, u8Strm) = 0;
866 HDA_STREAM_REG2(pState, BDPL, u8Strm) = 0;
867 Log(("hda: reset of stream (%d) finished\n", u8Strm));
868}
869
870
871DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
872{
873 *pu32Value = 0;
874 return VINF_SUCCESS;
875}
876DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
877{
878 return VINF_SUCCESS;
879}
880/* U8 */
881DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
882{
883 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
884 return hdaRegReadU32(pState, offset, index, pu32Value);
885}
886
887DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
888{
889 Assert(((u32Value & 0xffffff00) == 0));
890 return hdaRegWriteU32(pState, offset, index, u32Value);
891}
892/* U16 */
893DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
894{
895 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
896 return hdaRegReadU32(pState, offset, index, pu32Value);
897}
898
899DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
900{
901 Assert(((u32Value & 0xffff0000) == 0));
902 return hdaRegWriteU32(pState, offset, index, u32Value);
903}
904
905/* U24 */
906DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
907{
908 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
909 return hdaRegReadU32(pState, offset, index, pu32Value);
910}
911
912DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
913{
914 Assert(((u32Value & 0xff000000) == 0));
915 return hdaRegWriteU32(pState, offset, index, u32Value);
916}
917/* U32 */
918DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
919{
920 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
921 return VINF_SUCCESS;
922}
923
924DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
925{
926 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
927 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
928 return VINF_SUCCESS;
929}
930
931DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
932{
933 return hdaRegReadU32(pState, offset, index, pu32Value);
934}
935
936DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
937{
938 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
939 {
940 /* exit reset state */
941 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
942 pState->fInReset = false;
943 }
944 else
945 {
946 /* enter reset state*/
947 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
948 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
949 {
950 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
951 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
952 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
953 }
954 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
955 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
956 pState->fInReset = true;
957 }
958 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
959 {
960 /* Flush: GSTS:1 set, see 6.2.6*/
961 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
962 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
963 }
964 return VINF_SUCCESS;
965}
966
967DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
968{
969 uint32_t v = pState->au32Regs[index];
970 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
971 pState->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
972 return VINF_SUCCESS;
973}
974
975DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
976{
977 uint32_t v = 0;
978 if ( RIRBSTS_RIRBOIS(pState)
979 || RIRBSTS_RINTFL(pState)
980 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
981 || STATESTS(pState))
982 v |= RT_BIT(30);
983#define HDA_IS_STREAM_EVENT(pState, stream) \
984 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
985 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
986 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
987#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
988 MARK_STREAM(pState, 0, v);
989 MARK_STREAM(pState, 1, v);
990 MARK_STREAM(pState, 2, v);
991 MARK_STREAM(pState, 3, v);
992 MARK_STREAM(pState, 4, v);
993 MARK_STREAM(pState, 5, v);
994 MARK_STREAM(pState, 6, v);
995 MARK_STREAM(pState, 7, v);
996 v |= v ? RT_BIT(31) : 0;
997 *pu32Value = v;
998 return VINF_SUCCESS;
999}
1000
1001DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1002{
1003 return hdaRegReadU16(pState, offset, index, pu32Value);
1004}
1005
1006DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1007{
1008 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1009 CORBRP(pState) = 0;
1010 else
1011 return hdaRegWriteU8(pState, offset, index, u32Value);
1012 return VINF_SUCCESS;
1013}
1014
1015DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1016{
1017 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
1018 AssertRC(rc);
1019 if ( CORBWP(pState) != CORBRP(pState)
1020 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
1021 return hdaCORBCmdProcess(pState);
1022 return rc;
1023}
1024
1025DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1026{
1027 uint32_t v = CORBSTS(pState);
1028 CORBSTS(pState) &= ~(v & u32Value);
1029 return VINF_SUCCESS;
1030}
1031
1032DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1033{
1034 int rc;
1035 rc = hdaRegWriteU16(pState, offset, index, u32Value);
1036 if (RT_FAILURE(rc))
1037 AssertRCReturn(rc, rc);
1038 if (CORBWP(pState) == CORBRP(pState))
1039 return VINF_SUCCESS;
1040 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1041 return VINF_SUCCESS;
1042 rc = hdaCORBCmdProcess(pState);
1043 return rc;
1044}
1045
1046DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1047{
1048 return hdaRegReadU24(pState, offset, index, pu32Value);
1049}
1050
1051DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1052{
1053 bool fRun = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1054 bool fInRun = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1055 bool fReset = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1056 bool fInReset = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1057 int rc = VINF_SUCCESS;
1058 if (fInReset)
1059 {
1060 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1061 * from reset
1062 */
1063 Assert((!fReset));
1064 Log(("hda: guest initiate exit of stream reset.\n"));
1065 goto done;
1066 }
1067 else if (fReset)
1068 {
1069 /*
1070 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1071 */
1072 uint8_t u8Strm = 0;
1073 PHDABDLEDESC pBdle = NULL;
1074 HDASTREAMTRANSFERDESC stStreamDesc;
1075 Assert((!fInRun && !fRun));
1076 switch (index)
1077 {
1078 case ICH6_HDA_REG_SD0CTL:
1079 u8Strm = 0;
1080 pBdle = &pState->stInBdle;
1081 break;
1082 case ICH6_HDA_REG_SD4CTL:
1083 u8Strm = 4;
1084 pBdle = &pState->stOutBdle;
1085 break;
1086 default:
1087 Log(("hda: changing SRST bit on non-attached stream\n"));
1088 goto done;
1089 }
1090 Log(("hda: guest initiate enter to stream reset.\n"));
1091 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1092 hdaStreamReset(pState, pBdle, &stStreamDesc, u8Strm);
1093 goto done;
1094 }
1095
1096 /* we enter here to change DMA states only */
1097 if ( (fInRun && !fRun)
1098 || (fRun && !fInRun))
1099 {
1100 Assert((!fReset && !fInReset));
1101 switch (index)
1102 {
1103 case ICH6_HDA_REG_SD0CTL:
1104 AUD_set_active_in(ISD0FMT_TO_AUDIO_SELECTOR(pState), fRun);
1105 break;
1106 case ICH6_HDA_REG_SD4CTL:
1107 AUD_set_active_out(OSD0FMT_TO_AUDIO_SELECTOR(pState), fRun);
1108 break;
1109 default:
1110 Log(("hda: changing RUN bit on non-attached stream\n"));
1111 goto done;
1112 }
1113 }
1114
1115 done:
1116 rc = hdaRegWriteU24(pState, offset, index, u32Value);
1117 if (RT_FAILURE(rc))
1118 AssertRCReturn(rc, VINF_SUCCESS);
1119 return rc;
1120}
1121
1122DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1123{
1124 uint32_t v = HDA_REG_IND(pState, index);
1125 v &= ~(u32Value & v);
1126 HDA_REG_IND(pState, index) = v;
1127 hdaProcessInterrupt(pState);
1128 return VINF_SUCCESS;
1129}
1130
1131DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1132{
1133 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1134 if (RT_FAILURE(rc))
1135 AssertRCReturn(rc, VINF_SUCCESS);
1136 return rc;
1137}
1138
1139DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1140{
1141 switch (u32Value)
1142 {
1143 case HDA_SDFIFOW_8B:
1144 case HDA_SDFIFOW_16B:
1145 case HDA_SDFIFOW_32B:
1146 return hdaRegWriteU16(pState, offset, index, u32Value);
1147 default:
1148 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1149 return hdaRegWriteU16(pState, offset, index, HDA_SDFIFOW_32B);
1150 }
1151 return VINF_SUCCESS;
1152}
1153/*
1154 * Note this method could be called for changing value on Output Streams only (ICH6 datacheet 18.2.39)
1155 *
1156 */
1157DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1158{
1159 switch (index)
1160 {
1161 /* SDInFIFOS is RO, n=0-3 */
1162 case ICH6_HDA_REG_SD0FIFOS:
1163 case ICH6_HDA_REG_SD1FIFOS:
1164 case ICH6_HDA_REG_SD2FIFOS:
1165 case ICH6_HDA_REG_SD3FIFOS:
1166 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1167 return VINF_SUCCESS;
1168 case ICH6_HDA_REG_SD4FIFOS:
1169 case ICH6_HDA_REG_SD5FIFOS:
1170 case ICH6_HDA_REG_SD6FIFOS:
1171 case ICH6_HDA_REG_SD7FIFOS:
1172 switch(u32Value)
1173 {
1174 case HDA_SDONFIFO_16B:
1175 case HDA_SDONFIFO_32B:
1176 case HDA_SDONFIFO_64B:
1177 case HDA_SDONFIFO_128B:
1178 case HDA_SDONFIFO_192B:
1179 return hdaRegWriteU16(pState, offset, index, u32Value);
1180
1181 case HDA_SDONFIFO_256B:
1182 Log(("hda: 256 bit is unsupported, HDA is switched into 192B mode\n"));
1183 default:
1184 return hdaRegWriteU16(pState, offset, index, HDA_SDONFIFO_192B);
1185 }
1186 return VINF_SUCCESS;
1187 default:
1188 AssertMsgFailed(("Something wierd happens with register lookup routine"));
1189 }
1190 return VINF_SUCCESS;
1191}
1192
1193DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1194{
1195 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1196 if (RT_FAILURE(rc))
1197 AssertRCReturn(rc, VINF_SUCCESS);
1198 return rc;
1199}
1200
1201DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1202{
1203 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1204 if (RT_FAILURE(rc))
1205 AssertRCReturn(rc, VINF_SUCCESS);
1206 return rc;
1207}
1208
1209DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1210{
1211 int rc = VINF_SUCCESS;
1212 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1213 if ( CORBWP(pState) != CORBRP(pState)
1214 || HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1215 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1216
1217 rc = hdaRegReadU32(pState, offset, index, pu32Value);
1218 return rc;
1219}
1220
1221DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1222{
1223 int rc = VINF_SUCCESS;
1224 uint64_t resp;
1225 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1226 /*
1227 * if guest set ICB bit of IRS register HDA should process verb in IC register and
1228 * writes response in IR register and set IRV (valid in case of success) bit of IRS register.
1229 */
1230 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1231 && !IRS_ICB(pState))
1232 {
1233 uint32_t cmd = IC(pState);
1234 if (CORBWP(pState) != CORBRP(pState))
1235 {
1236 /*
1237 * 3.4.3 defines behaviour of immediate Command status register.
1238 */
1239 LogRel(("hda: guest has tried process immediate verb (%x) with active CORB\n", cmd));
1240 return rc;
1241 }
1242 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1243 Log(("hda: IC:%x\n", cmd));
1244 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1245 if (RT_FAILURE(rc))
1246 AssertRCReturn(rc, rc);
1247 rc = pfn(&pState->Codec, cmd, &resp);
1248 if (RT_FAILURE(rc))
1249 AssertRCReturn(rc, rc);
1250 IR(pState) = (uint32_t)resp;
1251 Log(("hda: IR:%x\n", IR(pState)));
1252 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1253 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1254 return rc;
1255 }
1256 /*
1257 * when guest's read the response it should clean the IRV bit of the IRS register.
1258 */
1259 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1260 && IRS_IRV(pState))
1261 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1262 return rc;
1263}
1264
1265DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1266{
1267 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1268 {
1269 RIRBWP(pState) = 0;
1270 }
1271 /*The rest of bits are O, see 6.2.22 */
1272 return VINF_SUCCESS;
1273}
1274
1275DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1276{
1277 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1278 if (RT_FAILURE(rc))
1279 AssertRCReturn(rc, rc);
1280 switch(index)
1281 {
1282 case ICH6_HDA_REG_CORBLBASE:
1283 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1284 pState->u64CORBBase |= pState->au32Regs[index];
1285 break;
1286 case ICH6_HDA_REG_CORBUBASE:
1287 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1288 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1289 break;
1290 case ICH6_HDA_REG_RIRLBASE:
1291 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1292 pState->u64RIRBBase |= pState->au32Regs[index];
1293 break;
1294 case ICH6_HDA_REG_RIRUBASE:
1295 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1296 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1297 break;
1298 case ICH6_HDA_REG_DPLBASE:
1299 /* @todo: first bit has special meaning */
1300 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1301 pState->u64DPBase |= pState->au32Regs[index];
1302 break;
1303 case ICH6_HDA_REG_DPUBASE:
1304 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1305 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1306 break;
1307 default:
1308 AssertMsgFailed(("Invalid index"));
1309 }
1310 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1311 return rc;
1312}
1313
1314DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1315{
1316 uint8_t v = RIRBSTS(pState);
1317 RIRBSTS(pState) &= ~(v & u32Value);
1318
1319 return hdaProcessInterrupt(pState);
1320}
1321
1322#ifdef LOG_ENABLED
1323static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1324{
1325#if 0
1326 uint64_t addr;
1327 uint32_t len;
1328 uint32_t ioc;
1329 uint8_t bdle[16];
1330 uint32_t counter;
1331 uint32_t i;
1332 uint32_t sum = 0;
1333 Assert(pBdle && pBdle->u32BdleMaxCvi);
1334 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1335 {
1336 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1337 addr = *(uint64_t *)bdle;
1338 len = *(uint32_t *)&bdle[8];
1339 ioc = *(uint32_t *)&bdle[12];
1340 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1341 sum += len;
1342 }
1343 Log(("hda: sum: %d\n", sum));
1344 for (i = 0; i < 8; ++i)
1345 {
1346 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1347 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
1348 i , counter));
1349 }
1350#endif
1351}
1352#endif
1353
1354static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1355{
1356 uint8_t bdle[16];
1357 Assert(( pStreamDesc->u64BaseDMA
1358 && pBdle
1359 && pBdle->u32BdleMaxCvi));
1360 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1361 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1362 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1363 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1364#ifdef LOG_ENABLED
1365 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1366#endif
1367}
1368
1369static inline uint32_t hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1370{
1371 uint32_t cb2Copy;
1372#if 0
1373 if (u32SoundBackendBufferBytesAvail <= u32Fifos + 1)
1374 {
1375 /* Some platform offers buffer not multiplied on SDnFIFOS+1 value
1376 * so to avoid situation when the rest of the backend buffer is less
1377 * of SDnFIFOW value, we'll wait for next iteration with fresh buffer.
1378 */
1379 return 0;
1380 }
1381#endif
1382 /*
1383 * Amounts of bytes depends on current position in buffer (u32BdleCviLen-u32BdleCviPos)
1384 */
1385 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1386 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1387 /*
1388 * we may increase the counter in range of [0, FIFOS + 1]
1389 */
1390 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1391 Assert((u32SoundBackendBufferBytesAvail > 0));
1392
1393 /* sanity check to avoid overriding sound backend buffer */
1394 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1395 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1396
1397 if (cb2Copy <= pBdle->cbUnderFifoW)
1398 return 0;
1399 cb2Copy -= pBdle->cbUnderFifoW; /* forcely reserve amount of ureported bytes to copy */
1400 return cb2Copy;
1401}
1402
1403static inline void hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1404{
1405 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1406 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1407 Assert((cbCopied));
1408 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1409 /* Assertion!!! It was copied less than cbUnderFifoW
1410 * Probably we need to move the buffer, but it rather hard to imagine situation
1411 * why it may happen.
1412 */
1413 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write whole buffer including not reported bytes */
1414 if ( pBdle->cbUnderFifoW
1415 && pBdle->cbUnderFifoW <= cbCopied)
1416 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1417
1418 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1419 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Assumption failed */
1420
1421 /* We always increment position on DMA buffer counter because we're always reading to intermediate buffer */
1422 pBdle->u32BdleCviPos += cbArranged2Copy;
1423
1424 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1425 /* We reports all bytes (including unreported previously) */
1426 *pu32DMACursor += cbCopied;
1427 /* reducing backend counter on amount of bytes we copied to backend */
1428 *pu32BackendBufferCapacity -= cbCopied;
1429 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1430 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1431}
1432
1433static inline void hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1434{
1435 Assert((cbCopied, cbArranged2Copy));
1436 *pu32BackendBufferCapacity -= cbCopied;
1437 pBdle->u32BdleCviPos += cbCopied;
1438 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1439 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1440 pBdle->cbUnderFifoW = 0;
1441 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1442 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1443}
1444
1445static inline void hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1446{
1447 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1448 pBdle->u32BdleCviPos += cbCopied;
1449 pBdle->cbUnderFifoW += cbCopied;
1450 /* In case of read transaction we're always coping from backend buffer */
1451 if (pu32BackendBufferCapacity)
1452 *pu32BackendBufferCapacity -= cbCopied;
1453 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1454 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pState, pStreamDesc)));
1455}
1456static inline bool hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1457{
1458 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1459 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1460 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1461 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1462 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1463 hdaUpdatePosBuf(pState, pStreamDesc);
1464
1465 if (pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1466 {
1467 pBdle->u32BdleCviPos = 0;
1468 pBdle->u32BdleCvi++;
1469 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1470 pBdle->u32BdleCvi = 0;
1471 }
1472 return fOnBufferEdge;
1473}
1474
1475static inline void hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbInc)
1476{
1477 /*
1478 * if we're under FIFO Watermark it's expected that HDA doesn't fetch anything.
1479 * (ICH6 datasheet 18.2.38)
1480 */
1481 if (!pBdle->cbUnderFifoW)
1482 {
1483 *pStreamDesc->pu32Lpib += cbInc;
1484
1485 /*
1486 * Assert. Overlapping of buffer counter shouldn't happen.
1487 */
1488 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1489
1490 hdaUpdatePosBuf(pState, pStreamDesc);
1491
1492 }
1493}
1494
1495static inline bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1496{
1497 bool fDoNextTransferLoop = true;
1498 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1499 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1500 {
1501 if ( !pBdle->cbUnderFifoW
1502 && pBdle->fBdleCviIoc)
1503 {
1504 /*
1505 * @todo - more carefully investigate BCIS flag.
1506 * Speech synthesis works fine on Mac Guest if this bit isn't set
1507 * but in general sound quality becomes lesser.
1508 */
1509 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1510 /*
1511 * we should generate the interrupt if ICE bit of SDCTL register is set.
1512 */
1513 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1514 hdaProcessInterrupt(pState);
1515 }
1516 fDoNextTransferLoop = false;
1517 }
1518 return fDoNextTransferLoop;
1519}
1520
1521/*
1522 * hdaReadAudio - copies samples from Qemu Sound back-end to DMA.
1523 * Note: this function writes immediately to DMA buffer, but "reports bytes" when all conditions meet (FIFOW)
1524 */
1525static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1526{
1527 PHDABDLEDESC pBdle = &pState->stInBdle;
1528 uint32_t cbTransfered = 0;
1529 uint32_t cb2Copy = 0;
1530 uint32_t cbBackendCopy = 0;
1531
1532 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1533
1534 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1535 if (!cb2Copy)
1536 {
1537 /* if we enter here we can't report "unreported bits" */
1538 *fStop = true;
1539 goto done;
1540 }
1541
1542
1543 /*
1544 * read from backend input line to last ureported position or at the begining.
1545 */
1546 cbBackendCopy = AUD_read (ISD0FMT_TO_AUDIO_SELECTOR(pState), pBdle->au8HdaBuffer, cb2Copy);
1547 /*
1548 * write on the HDA DMA
1549 */
1550 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1551
1552 /* Don't see reasons why cb2Copy could differ from cbBackendCopy */
1553 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1554
1555 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pState, 0))
1556 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1557 else
1558 {
1559 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1560 *fStop = true;
1561 }
1562 done:
1563 Assert((cbTransfered <= (SDFIFOS(pState, 0) + 1)));
1564 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransfered: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1565 return cbTransfered;
1566}
1567
1568static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1569{
1570 PHDABDLEDESC pBdle = &pState->stOutBdle;
1571 uint32_t cbTransfered = 0;
1572 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1573 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1574
1575 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1576
1577 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1578
1579 /*
1580 * Copy from DMA to the corresponding hdaBuffer (if there exists some bytes from the previous not reported transfer we write to ''pBdle->cbUnderFifoW'' offset)
1581 */
1582 if (!cb2Copy)
1583 {
1584 *fStop = true;
1585 goto done;
1586 }
1587
1588 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1589 /*
1590 * Write to audio backend. we should be sure whether we have enought bytes to copy to Audio backend.
1591 */
1592 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, pStreamDesc))
1593 {
1594 /*
1595 * We feed backend with new portion of fetched samples including not reported.
1596 */
1597 cbBackendCopy = AUD_write (OSD0FMT_TO_AUDIO_SELECTOR(pState), pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1598 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1599 }
1600 else
1601 {
1602 /* Not enough bytes to be processed and reported, check luck on next enterence */
1603 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cb2Copy, NULL);
1604 *fStop = true;
1605 }
1606
1607 done:
1608 Assert((cbTransfered <= (SDFIFOS(pState, 4) + 1)));
1609 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransfered:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1610 return cbTransfered;
1611}
1612
1613DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1614{
1615 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1616 return VINF_SUCCESS;
1617}
1618
1619static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc)
1620{
1621 Assert(( pState
1622 && pBdle
1623 && pStreamDesc
1624 && u8Strm <= 7));
1625 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1626 pStreamDesc->u8Strm = u8Strm;
1627 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pState, CTL, u8Strm);
1628 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pState, BDPL, u8Strm),
1629 HDA_STREAM_REG2(pState, BDPU, u8Strm));
1630 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pState, LPIB, u8Strm);
1631 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pState, STS, u8Strm);
1632 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pState, CBL, u8Strm);
1633 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pState, FIFOS, u8Strm);
1634
1635 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pState, LVI, u8Strm);
1636#ifdef LOG_ENABLED
1637 if ( pBdle
1638 && pBdle->u32BdleMaxCvi)
1639 {
1640 Log(("Initialization of transfer descriptor:\n"));
1641 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1642 }
1643#endif
1644}
1645
1646DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1647{
1648 bool fStop = false;
1649 uint8_t u8Strm = 0;
1650 PHDABDLEDESC pBdle = NULL;
1651 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1652 HDASTREAMTRANSFERDESC stStreamDesc;
1653 uint32_t nBytes;
1654 while( avail && !fStop)
1655 {
1656 switch (src)
1657 {
1658 case PO_INDEX:
1659 {
1660 u8Strm = 4;
1661 pBdle = &pState->stOutBdle;
1662 break;
1663 }
1664 case PI_INDEX:
1665 {
1666 u8Strm = 0;
1667 pBdle = &pState->stInBdle;
1668 break;
1669 }
1670 default:
1671 return;
1672 }
1673 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1674 Assert ( (stStreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1675 && avail
1676 && stStreamDesc.u64BaseDMA);
1677
1678 /* Fetch the Buffer Descriptor Entry (BDE). */
1679
1680 if (hdaIsTransferCountersOverlapped(pState, pBdle, &stStreamDesc))
1681 hdaFetchBdle(pState, pBdle, &stStreamDesc);
1682 *stStreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1683 Assert((avail >= 0 && (stStreamDesc.u32Cbl >= (*stStreamDesc.pu32Lpib)))); /* sanity */
1684 uint32_t u32CblLimit = stStreamDesc.u32Cbl - (*stStreamDesc.pu32Lpib);
1685 Assert((u32CblLimit > hdaFifoWToSz(pState, &stStreamDesc)));
1686 Log(("hda: CBL=%d, LPIB=%d\n", stStreamDesc.u32Cbl, *stStreamDesc.pu32Lpib));
1687 switch (src)
1688 {
1689 case PO_INDEX:
1690 nBytes = hdaWriteAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1691 break;
1692 case PI_INDEX:
1693 nBytes = hdaReadAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1694 break;
1695 default:
1696 nBytes = 0;
1697 fStop = true;
1698 AssertMsgFailed(("Unsupported"));
1699 }
1700 Assert(nBytes <= (stStreamDesc.u32Fifos + 1));
1701 *stStreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1702
1703 /* Process end of buffer condition. */
1704 hdaStreamCounterUpdate(pState, pBdle, &stStreamDesc, nBytes);
1705 fStop = !fStop ? !hdaDoNextTransferCycle(pState, pBdle, &stStreamDesc) : fStop;
1706 }
1707}
1708
1709/**
1710 * Handle register read operation.
1711 *
1712 * Looks up and calls appropriate handler.
1713 *
1714 * @note: while implementation was detected so called "forgotten" or "hole" registers
1715 * which description is missed in RPM, datasheet or spec.
1716 *
1717 * @returns VBox status code.
1718 *
1719 * @param pState The device state structure.
1720 * @param uOffset Register offset in memory-mapped frame.
1721 * @param pv Where to fetch the value.
1722 * @param cb Number of bytes to write.
1723 * @thread EMT
1724 */
1725PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1726{
1727 int rc = VINF_SUCCESS;
1728 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1729 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1730 int index = hdaLookup(&pThis->hda, u32Offset);
1731 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1732 {
1733 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1734 }
1735 if ( index == -1
1736 || cb > 4)
1737 {
1738 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", u32Offset, cb));
1739 }
1740 if (index != -1)
1741 {
1742 uint32_t mask = 0;
1743 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1744 uint32_t v = 0;
1745 switch(cb)
1746 {
1747 case 1: mask = 0x000000ff; break;
1748 case 2: mask = 0x0000ffff; break;
1749 case 3: mask = 0x00ffffff; break;
1750 case 4: mask = 0xffffffff; break;
1751 }
1752 mask <<= shift;
1753 rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1754 *(uint32_t *)pv = (v & mask) >> shift;
1755 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
1756 return rc;
1757 }
1758 *(uint32_t *)pv = 0xFF;
1759 Log(("hda: hole at %X is accessed for read\n", u32Offset));
1760 return rc;
1761}
1762
1763/**
1764 * Handle register write operation.
1765 *
1766 * Looks up and calls appropriate handler.
1767 *
1768 * @returns VBox status code.
1769 *
1770 * @param pState The device state structure.
1771 * @param uOffset Register offset in memory-mapped frame.
1772 * @param pv Where to fetch the value.
1773 * @param cb Number of bytes to write.
1774 * @thread EMT
1775 */
1776PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1777{
1778 int rc = VINF_SUCCESS;
1779 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1780 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1781 int index = hdaLookup(&pThis->hda, u32Offset);
1782 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1783 {
1784 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1785 }
1786 if ( index == -1
1787 || cb > 4)
1788 {
1789 LogRel(("hda: Invalid write access @0x%x(of bytes:%d)\n", u32Offset, cb));
1790 }
1791 if (index != -1)
1792 {
1793 uint32_t v = pThis->hda.au32Regs[index];
1794 uint32_t mask = 0;
1795 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1796 switch(cb)
1797 {
1798 case 1: mask = 0xffffff00; break;
1799 case 2: mask = 0xffff0000; break;
1800 case 3: mask = 0xff000000; break;
1801 case 4: mask = 0x00000000; break;
1802 }
1803 mask <<= shift;
1804 *(uint32_t *)pv = ((v & mask) | (*(uint32_t *)pv & ~mask)) >> shift;
1805 rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
1806 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
1807 return rc;
1808 }
1809 Log(("hda: hole at %X is accessed for write\n", u32Offset));
1810 return rc;
1811}
1812
1813/**
1814 * Callback function for mapping a PCI I/O region.
1815 *
1816 * @return VBox status code.
1817 * @param pPciDev Pointer to PCI device.
1818 * Use pPciDev->pDevIns to get the device instance.
1819 * @param iRegion The region number.
1820 * @param GCPhysAddress Physical address of the region.
1821 * If iType is PCI_ADDRESS_SPACE_IO, this is an
1822 * I/O port, else it's a physical address.
1823 * This address is *NOT* relative
1824 * to pci_mem_base like earlier!
1825 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
1826 */
1827static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
1828 RTGCPHYS GCPhysAddress, uint32_t cb,
1829 PCIADDRESSSPACE enmType)
1830{
1831 int rc;
1832 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1833 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1834 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1835
1836 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1837 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
1838 hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
1839
1840 if (RT_FAILURE(rc))
1841 return rc;
1842
1843 pThis->hda.addrMMReg = GCPhysAddress;
1844 return VINF_SUCCESS;
1845}
1846
1847/**
1848 * Saves a state of the HDA device.
1849 *
1850 * @returns VBox status code.
1851 * @param pDevIns The device instance.
1852 * @param pSSMHandle The handle to save the state to.
1853 */
1854static DECLCALLBACK(int) hdaSaveExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1855{
1856 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1857 /* Save Codec nodes states */
1858 codecSaveState(&pThis->hda.Codec, pSSMHandle);
1859 /* Save MMIO registers */
1860 SSMR3PutMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1861 /* Save HDA dma counters */
1862 SSMR3PutMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
1863 SSMR3PutMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
1864 SSMR3PutMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
1865 return VINF_SUCCESS;
1866}
1867
1868/**
1869 * Loads a saved HDA device state.
1870 *
1871 * @returns VBox status code.
1872 * @param pDevIns The device instance.
1873 * @param pSSMHandle The handle to the saved state.
1874 * @param uVersion The data unit version number.
1875 * @param uPass The data pass.
1876 */
1877static DECLCALLBACK(int) hdaLoadExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1878 uint32_t uVersion, uint32_t uPass)
1879{
1880 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1881 /* Load Codec nodes states */
1882 AssertMsgReturn (uVersion == HDA_SSM_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1883 Assert (uPass == SSM_PASS_FINAL); NOREF(uPass);
1884
1885 codecLoadState(&pThis->hda.Codec, pSSMHandle);
1886 /* Load MMIO registers */
1887 SSMR3GetMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1888 /* Load HDA dma counters */
1889 SSMR3GetMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
1890 SSMR3GetMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
1891 SSMR3GetMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
1892
1893 AUD_set_active_in(ISD0FMT_TO_AUDIO_SELECTOR(&pThis->hda), SDCTL(&pThis->hda, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1894 AUD_set_active_out(OSD0FMT_TO_AUDIO_SELECTOR(&pThis->hda), SDCTL(&pThis->hda, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1895
1896 pThis->hda.u64CORBBase = CORBLBASE(&pThis->hda);
1897 pThis->hda.u64CORBBase |= ((uint64_t)CORBUBASE(&pThis->hda)) << 32;
1898 pThis->hda.u64RIRBBase = RIRLBASE(&pThis->hda);
1899 pThis->hda.u64RIRBBase |= ((uint64_t)RIRUBASE(&pThis->hda)) << 32;
1900 pThis->hda.u64DPBase = DPLBASE(&pThis->hda);
1901 pThis->hda.u64DPBase |= ((uint64_t)DPUBASE(&pThis->hda)) << 32;
1902 return VINF_SUCCESS;
1903}
1904
1905/**
1906 * Reset notification.
1907 *
1908 * @returns VBox status.
1909 * @param pDevIns The device instance data.
1910 *
1911 * @remark The original sources didn't install a reset handler, but it seems to
1912 * make sense to me so we'll do it.
1913 */
1914static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
1915{
1916 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1917 GCAP(&pThis->hda) = 0x4401; /* see 6.2.1 */
1918 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
1919 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1920 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1921 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
1922 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
1923 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
1924 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
1925 CORBRP(&pThis->hda) = 0x0;
1926 RIRBWP(&pThis->hda) = 0x0;
1927
1928 Log(("hda: inter HDA reset.\n"));
1929 pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
1930
1931 if (pThis->hda.pu32CorbBuf)
1932 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
1933 else
1934 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
1935
1936 pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
1937 if (pThis->hda.pu64RirbBuf)
1938 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
1939 else
1940 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
1941
1942#if 0
1943 /* According to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
1944 * bits are reserved for stream number 18.2.33 */
1945 SDCTL(&pThis->hda, 0) = 0x40000;
1946 SDCTL(&pThis->hda, 1) = 0x40000;
1947 SDCTL(&pThis->hda, 2) = 0x40000;
1948 SDCTL(&pThis->hda, 3) = 0x40000;
1949 SDCTL(&pThis->hda, 4) = 0x40000;
1950 SDCTL(&pThis->hda, 5) = 0x40000;
1951 SDCTL(&pThis->hda, 6) = 0x40000;
1952 SDCTL(&pThis->hda, 7) = 0x40000;
1953
1954 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1955 SDFIFOS(&pThis->hda, 0) = HDA_SDINFIFO_120B;
1956 SDFIFOS(&pThis->hda, 1) = HDA_SDINFIFO_120B;
1957 SDFIFOS(&pThis->hda, 2) = HDA_SDINFIFO_120B;
1958 SDFIFOS(&pThis->hda, 3) = HDA_SDINFIFO_120B;
1959
1960 SDFIFOS(&pThis->hda, 4) = HDA_SDONFIFO_192B;
1961 SDFIFOS(&pThis->hda, 5) = HDA_SDONFIFO_192B;
1962 SDFIFOS(&pThis->hda, 6) = HDA_SDONFIFO_192B;
1963 SDFIFOS(&pThis->hda, 7) = HDA_SDONFIFO_192B;
1964
1965 SDFIFOW(&pThis->hda, 0) = HDA_SDFIFOW_8B;
1966 SDFIFOW(&pThis->hda, 4) = HDA_SDFIFOW_32B;
1967#endif
1968 HDABDLEDESC stEmptyBdle;
1969 for(uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
1970 {
1971 HDASTREAMTRANSFERDESC stStreamDesc;
1972 PHDABDLEDESC pBdle = NULL;
1973 if (u8Strm == 0)
1974 pBdle = &pThis->hda.stInBdle;
1975 else if(u8Strm == 4)
1976 pBdle = &pThis->hda.stOutBdle;
1977 else
1978 {
1979 memset(&stEmptyBdle, 0, sizeof(HDABDLEDESC));
1980 pBdle = &stEmptyBdle;
1981 }
1982 hdaInitTransferDescriptor(&pThis->hda, pBdle, u8Strm, &stStreamDesc);
1983 /* hdaStreamReset prevents changing SRST bit, so we zerro it here forcely. */
1984 HDA_STREAM_REG2(&pThis->hda, CTL, u8Strm) = 0;
1985 hdaStreamReset(&pThis->hda, pBdle, &stStreamDesc, u8Strm);
1986 }
1987
1988 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
1989 STATESTS(&pThis->hda) = 0x1;
1990
1991 Log(("hda: reset finished\n"));
1992}
1993
1994/**
1995 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1996 */
1997static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
1998 const char *pszIID)
1999{
2000 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
2001 Assert(&pThis->hda.IBase == pInterface);
2002
2003 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
2004 return NULL;
2005}
2006
2007//#define HDA_AS_PCI_EXPRESS
2008
2009/**
2010 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2011 */
2012static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
2013 PCFGMNODE pCfgHandle)
2014{
2015 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2016 INTELHDLinkState *s = &pThis->hda;
2017 int rc;
2018
2019 Assert(iInstance == 0);
2020 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2021
2022 /*
2023 * Validations.
2024 */
2025 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
2026 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2027 N_ ("Invalid configuration for the INTELHD device"));
2028
2029 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
2030 // poll some register(s).
2031
2032 /*
2033 * Initialize data (most of it anyway).
2034 */
2035 s->pDevIns = pDevIns;
2036 /* IBase */
2037 s->IBase.pfnQueryInterface = hdaQueryInterface;
2038
2039 /* PCI Device (the assertions will be removed later) */
2040#if defined(VBOX_WITH_HP_HDA)
2041 /* Linux kernel has whitelist for MSI-enabled HDA, this card seems to be there. */
2042 PCIDevSetVendorId (&pThis->dev, 0x103c); /* HP. */
2043 PCIDevSetDeviceId (&pThis->dev, 0x30f7); /* HP Pavilion dv4t-1300 */
2044#elif defined(VBOX_WITH_INTEL_HDA)
2045 PCIDevSetVendorId (&pThis->dev, 0x8086); /* 00 ro - intel. */
2046 PCIDevSetDeviceId (&pThis->dev, 0x2668); /* 02 ro - 82801 / 82801aa(?). */
2047#elif defined(VBOX_WITH_NVIDIA_HDA)
2048 PCIDevSetVendorId (&pThis->dev, 0x10de); /* nVidia */
2049 PCIDevSetDeviceId (&pThis->dev, 0x0ac0); /* HDA */
2050#else
2051# error "Please specify your HDA device vendor/device IDs"
2052#endif
2053 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
2054 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2055 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
2056 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
2057 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
2058 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2059 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
2060 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
2061 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2062 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
2063 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */
2064
2065#if defined(HDA_AS_PCI_EXPRESS)
2066 PCIDevSetCapabilityList (&pThis->dev, 0x80);
2067#elif defined(VBOX_WITH_MSI_DEVICES)
2068 PCIDevSetCapabilityList (&pThis->dev, 0x60);
2069#else
2070 PCIDevSetCapabilityList (&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
2071#endif
2072
2073 //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2074 // of these values needs to be properly documented!
2075 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2076 PCIDevSetByte(&pThis->dev, 0x40, 0x01);
2077
2078 /* Power Management */
2079 PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2080 PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
2081 PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2082
2083#ifdef HDA_AS_PCI_EXPRESS
2084 /* PCI Express */
2085 PCIDevSetByte (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2086 PCIDevSetByte (&pThis->dev, 0x80 + 1, 0x60); /* next */
2087 /* Device flags */
2088 PCIDevSetWord (&pThis->dev, 0x80 + 2,
2089 /* version */ 0x1 |
2090 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2091 /* MSI */ (100) << 9
2092 );
2093 /* Device capabilities */
2094 PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2095 /* Device control */
2096 PCIDevSetWord (&pThis->dev, 0x80 + 8, 0);
2097 /* Device status */
2098 PCIDevSetWord (&pThis->dev, 0x80 + 10, 0);
2099 /* Link caps */
2100 PCIDevSetDWord (&pThis->dev, 0x80 + 12, 0);
2101 /* Link control */
2102 PCIDevSetWord (&pThis->dev, 0x80 + 16, 0);
2103 /* Link status */
2104 PCIDevSetWord (&pThis->dev, 0x80 + 18, 0);
2105 /* Slot capabilities */
2106 PCIDevSetDWord (&pThis->dev, 0x80 + 20, 0);
2107 /* Slot control */
2108 PCIDevSetWord (&pThis->dev, 0x80 + 24, 0);
2109 /* Slot status */
2110 PCIDevSetWord (&pThis->dev, 0x80 + 26, 0);
2111 /* Root control */
2112 PCIDevSetWord (&pThis->dev, 0x80 + 28, 0);
2113 /* Root capabilities */
2114 PCIDevSetWord (&pThis->dev, 0x80 + 30, 0);
2115 /* Root status */
2116 PCIDevSetDWord (&pThis->dev, 0x80 + 32, 0);
2117 /* Device capabilities 2 */
2118 PCIDevSetDWord (&pThis->dev, 0x80 + 36, 0);
2119 /* Device control 2 */
2120 PCIDevSetQWord (&pThis->dev, 0x80 + 40, 0);
2121 /* Link control 2 */
2122 PCIDevSetQWord (&pThis->dev, 0x80 + 48, 0);
2123 /* Slot control 2 */
2124 PCIDevSetWord (&pThis->dev, 0x80 + 56, 0);
2125#endif
2126
2127 /*
2128 * Register the PCI device.
2129 */
2130 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
2131 if (RT_FAILURE (rc))
2132 return rc;
2133
2134 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
2135 hdaMap);
2136 if (RT_FAILURE (rc))
2137 return rc;
2138
2139#ifdef VBOX_WITH_MSI_DEVICES
2140 PDMMSIREG aMsiReg;
2141
2142 RT_ZERO(aMsiReg);
2143 aMsiReg.cMsiVectors = 1;
2144 aMsiReg.iMsiCapOffset = 0x60;
2145 aMsiReg.iMsiNextOffset = 0x50;
2146 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
2147 if (RT_FAILURE (rc))
2148 {
2149 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2150 PCIDevSetCapabilityList (&pThis->dev, 0x50);
2151 }
2152#endif
2153
2154 rc = PDMDevHlpSSMRegister (pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2155 if (RT_FAILURE (rc))
2156 return rc;
2157
2158 /*
2159 * Attach driver.
2160 */
2161 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
2162 &s->pDrvBase, "Audio Driver Port");
2163 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2164 Log (("hda: No attached driver!\n"));
2165 else if (RT_FAILURE (rc))
2166 {
2167 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
2168 return rc;
2169 }
2170
2171
2172
2173 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
2174 rc = codecConstruct(&pThis->hda.Codec, /* ALC885_CODEC */ STAC9220_CODEC);
2175 if (RT_FAILURE(rc))
2176 AssertRCReturn(rc, rc);
2177
2178 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2179 verb F20 should provide device/codec recognition. */
2180 Assert(pThis->hda.Codec.u16VendorId);
2181 Assert(pThis->hda.Codec.u16DeviceId);
2182 PCIDevSetSubSystemVendorId (&pThis->dev, pThis->hda.Codec.u16VendorId); /* 2c ro - intel.) */
2183 PCIDevSetSubSystemId (&pThis->dev, pThis->hda.Codec.u16DeviceId); /* 2e ro. */
2184
2185 hdaReset (pDevIns);
2186 pThis->hda.Codec.id = 0;
2187 pThis->hda.Codec.pfnTransfer = hdaTransfer;
2188 pThis->hda.Codec.pfnReset = hdaCodecReset;
2189 /*
2190 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2191 * hdaReset shouldn't affects these registers.
2192 */
2193 WAKEEN(&pThis->hda) = 0x0;
2194 STATESTS(&pThis->hda) = 0x0;
2195
2196 return VINF_SUCCESS;
2197}
2198
2199/**
2200 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2201 */
2202static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
2203{
2204 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2205
2206 int rc = codecDestruct(&pThis->hda.Codec);
2207 AssertRC(rc);
2208 if (pThis->hda.pu32CorbBuf)
2209 RTMemFree(pThis->hda.pu32CorbBuf);
2210 if (pThis->hda.pu64RirbBuf)
2211 RTMemFree(pThis->hda.pu64RirbBuf);
2212 return VINF_SUCCESS;
2213}
2214
2215/**
2216 * The device registration structure.
2217 */
2218const PDMDEVREG g_DeviceICH6_HDA =
2219{
2220 /* u32Version */
2221 PDM_DEVREG_VERSION,
2222 /* szName */
2223 "hda",
2224 /* szRCMod */
2225 "",
2226 /* szR0Mod */
2227 "",
2228 /* pszDescription */
2229 "ICH IntelHD Audio Controller",
2230 /* fFlags */
2231 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2232 /* fClass */
2233 PDM_DEVREG_CLASS_AUDIO,
2234 /* cMaxInstances */
2235 1,
2236 /* cbInstance */
2237 sizeof(PCIINTELHDLinkState),
2238 /* pfnConstruct */
2239 hdaConstruct,
2240 /* pfnDestruct */
2241 hdaDestruct,
2242 /* pfnRelocate */
2243 NULL,
2244 /* pfnIOCtl */
2245 NULL,
2246 /* pfnPowerOn */
2247 NULL,
2248 /* pfnReset */
2249 hdaReset,
2250 /* pfnSuspend */
2251 NULL,
2252 /* pfnResume */
2253 NULL,
2254 /* pfnAttach */
2255 NULL,
2256 /* pfnDetach */
2257 NULL,
2258 /* pfnQueryInterface. */
2259 NULL,
2260 /* pfnInitComplete */
2261 NULL,
2262 /* pfnPowerOff */
2263 NULL,
2264 /* pfnSoftReset */
2265 NULL,
2266 /* u32VersionEnd */
2267 PDM_DEVREG_VERSION
2268};
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