VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 35487

Last change on this file since 35487 was 35487, checked in by vboxsync, 14 years ago

Devices/Audio: fixed fallback to nul host audio driver. Added the fallback to HDA audio device. (xTracker 5404).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 99.4 KB
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1/* $Id: DevIchIntelHDA.cpp 35487 2011-01-11 13:45:20Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/vmm/pdmdev.h>
23#include <iprt/assert.h>
24#include <iprt/uuid.h>
25#include <iprt/string.h>
26#include <iprt/mem.h>
27#include <iprt/asm.h>
28#include <iprt/asm-math.h>
29
30#include "VBoxDD.h"
31
32extern "C" {
33#include "audio.h"
34}
35#include "DevCodec.h"
36
37#define VBOX_WITH_INTEL_HDA
38
39#if defined(VBOX_WITH_HP_HDA)
40/* HP Pavilion dv4t-1300 */
41# define HDA_PCI_VENDOR_ID 0x103c
42# define HDA_PCI_DEICE_ID 0x30f7
43#elif defined(VBOX_WITH_INTEL_HDA)
44/* Intel HDA controller */
45# define HDA_PCI_VENDOR_ID 0x8086
46# define HDA_PCI_DEICE_ID 0x2668
47#elif defined(VBOX_WITH_NVIDIA_HDA)
48/* nVidia HDA controller */
49# define HDA_PCI_VENDOR_ID 0x10de
50# define HDA_PCI_DEICE_ID 0x0ac0
51#else
52# error "Please specify your HDA device vendor/device IDs"
53#endif
54
55#define HDA_SSM_VERSION 1
56PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
57PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
58static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
59
60/* Registers */
61#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
62#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
63#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
64#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
65#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
66#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
67#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
68#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
69#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
70#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
71
72#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
73#define GCAP(pState) (HDA_REG((pState), GCAP))
74/* GCAP HDASpec 3.3.2 This macro compact following information about HDA
75 * oss (15:12) - number of output streams supported
76 * iss (11:8) - number of input streams supported
77 * bss (7:3) - number of bidirection streams suppoted
78 * bds (2:1) - number of serial data out signals supported
79 * b64sup (0) - 64 bit addressing supported.
80 */
81#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
82 ( (((oss) & 0xF) << 12) \
83 | (((iss) & 0xF) << 8) \
84 | (((bss) & 0x1F) << 3) \
85 | (((bds) & 0x3) << 2) \
86 | ((b64sup) & 1))
87#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
88#define VMIN(pState) (HDA_REG((pState), VMIN))
89
90#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
91#define VMAJ(pState) (HDA_REG((pState), VMAJ))
92
93#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
94#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
95
96#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
97#define INPAY(pState) (HDA_REG((pState), INPAY))
98
99#define ICH6_HDA_REG_GCTL (5)
100#define ICH6_HDA_GCTL_RST_SHIFT (0)
101#define ICH6_HDA_GCTL_FSH_SHIFT (1)
102#define ICH6_HDA_GCTL_UR_SHIFT (8)
103#define GCTL(pState) (HDA_REG((pState), GCTL))
104
105#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
106#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
107
108#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
109#define STATESTS(pState) (HDA_REG((pState), STATESTS))
110#define ICH6_HDA_STATES_SCSF 0x7
111
112#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
113#define ICH6_HDA_GSTS_FSH_SHIFT (1)
114#define GSTS(pState) (HDA_REG(pState, GSTS))
115
116#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
117#define ICH6_HDA_INTCTL_GIE_SHIFT 31
118#define ICH6_HDA_INTCTL_CIE_SHIFT 30
119#define ICH6_HDA_INTCTL_S0_SHIFT (0)
120#define ICH6_HDA_INTCTL_S1_SHIFT (1)
121#define ICH6_HDA_INTCTL_S2_SHIFT (2)
122#define ICH6_HDA_INTCTL_S3_SHIFT (3)
123#define ICH6_HDA_INTCTL_S4_SHIFT (4)
124#define ICH6_HDA_INTCTL_S5_SHIFT (5)
125#define ICH6_HDA_INTCTL_S6_SHIFT (6)
126#define ICH6_HDA_INTCTL_S7_SHIFT (7)
127#define INTCTL(pState) (HDA_REG((pState), INTCTL))
128#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
129#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
130#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
131#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
132
133/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
134 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
135 * the datasheet.
136 */
137#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
138#define SSYNC(pState) (HDA_REG((pState), SSYNC))
139
140#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
141#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
142#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
143#define ICH6_HDA_INTSTS_S0_SHIFT (0)
144#define ICH6_HDA_INTSTS_S1_SHIFT (1)
145#define ICH6_HDA_INTSTS_S2_SHIFT (2)
146#define ICH6_HDA_INTSTS_S3_SHIFT (3)
147#define ICH6_HDA_INTSTS_S4_SHIFT (4)
148#define ICH6_HDA_INTSTS_S5_SHIFT (5)
149#define ICH6_HDA_INTSTS_S6_SHIFT (6)
150#define ICH6_HDA_INTSTS_S7_SHIFT (7)
151#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
152#define INTSTS(pState) (HDA_REG((pState), INTSTS))
153#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
154#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
155#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
156#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
157
158#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
159#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
160#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
161#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
162#define ICH6_HDA_REG_CORBWP 15 /* 48 */
163#define ICH6_HDA_REG_CORBRP 16 /* 4A */
164#define ICH6_HDA_CORBRP_RST_SHIFT 15
165#define ICH6_HDA_CORBRP_WP_SHIFT 0
166#define ICH6_HDA_CORBRP_WP_MASK 0xFF
167
168#define CORBRP(pState) (HDA_REG(pState, CORBRP))
169#define CORBWP(pState) (HDA_REG(pState, CORBWP))
170
171#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
172#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
173#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
174
175#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
176
177
178#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
179#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
180#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
181
182#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
183#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
184#define ICH6_HDA_CORBSIZE_SZ 0x3
185#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
186#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
187/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
188
189#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
190#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
191
192#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
193#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
194
195#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
196#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
197#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
198#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
199
200#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
201#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
202#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
203
204#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
205#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
206#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
207#define ICH6_HDA_ROI_DMA_SHIFT (2)
208#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
209#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
210#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
211#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
212
213#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
214#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
215#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
216#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
217#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
218#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
219
220#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
221#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
222#define ICH6_HDA_RIRBSIZE_SZ 0x3
223
224#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
225#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
226
227
228#define ICH6_HDA_REG_IC 27 /* 0x60 */
229#define IC(pState) (HDA_REG(pState, IC))
230#define ICH6_HDA_REG_IR 28 /* 0x64 */
231#define IR(pState) (HDA_REG(pState, IR))
232#define ICH6_HDA_REG_IRS 29 /* 0x68 */
233#define ICH6_HDA_IRS_ICB_SHIFT (0)
234#define ICH6_HDA_IRS_IRV_SHIFT (1)
235#define IRS(pState) (HDA_REG(pState, IRS))
236#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
237#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
238
239#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
240#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
241#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
242#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
243#define DPBASE_ENABLED 1
244#define DPBASE_ADDR_MASK (~0x7f)
245
246#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
247#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
248/* Note: sdnum here _MUST_ be stream reg number [0,7] */
249#define HDA_STREAM_REG2(pState, name, sdnum) (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
250
251#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
252#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
253#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
254#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
255#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
256#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
257#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
258#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
259
260#define SD(func, num) SD##num##func
261#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
262#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
263#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
264#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
265#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
266#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
267#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
268#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
269#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
270
271#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
272#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
273#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
274#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
275#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
276#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
277#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
278#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
279
280#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
281#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
282#define ICH6_HDA_SDSTS_DE_SHIFT (4)
283#define ICH6_HDA_SDSTS_FE_SHIFT (3)
284#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
285
286#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
287#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
288#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
289#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
290#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
291#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
292#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
293#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
294
295#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
296
297#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
298#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
299#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
300#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
301#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
302#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
303#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
304#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
305
306#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
307
308#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
309#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
310#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
311#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
312#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
313#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
314#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
315#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
316
317#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
318
319#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
320#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
321#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
322#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
323#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
324#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
325#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
326#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
327
328/*
329 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
330 */
331#define HDA_SDFIFOW_8B (0x2)
332#define HDA_SDFIFOW_16B (0x3)
333#define HDA_SDFIFOW_32B (0x4)
334#define SDFIFOW(pState, num) HDA_REG((pState), SD(FIFOW, num))
335
336#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
337#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
338#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
339#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
340#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
341#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
342#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
343#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
344
345/*
346 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
347 * formula: size - 1
348 * Other values not listed are not supported.
349 */
350#define HDA_SDONFIFO_16B (0xF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
351#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
352#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
353#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
354#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
355#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
356#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
357#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
358#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
359
360#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
361#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
362#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
363#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
364#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
365#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
366#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
367#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
368
369#define SDFMT(pState, num) (HDA_REG((pState), SD(FMT, num)))
370#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
371#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
372#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
373#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
374#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
375#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
376#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
377#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
378
379#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
380#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
381#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
382#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
383#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
384#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
385#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
386#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
387
388#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
389
390#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
391#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
392#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
393#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
394#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
395#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
396#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
397#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
398
399#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
400
401/* Predicates */
402
403typedef struct HDABDLEDESC
404{
405 uint64_t u64BdleCviAddr;
406 uint32_t u32BdleMaxCvi;
407 uint32_t u32BdleCvi;
408 uint32_t u32BdleCviLen;
409 uint32_t u32BdleCviPos;
410 bool fBdleCviIoc;
411 uint32_t cbUnderFifoW;
412 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
413} HDABDLEDESC, *PHDABDLEDESC;
414
415typedef struct HDASTREAMTRANSFERDESC
416{
417 uint64_t u64BaseDMA;
418 uint32_t u32Ctl;
419 uint32_t *pu32Sts;
420 uint8_t u8Strm;
421 uint32_t *pu32Lpib;
422 uint32_t u32Cbl;
423 uint32_t u32Fifos;
424} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
425
426typedef struct INTELHDLinkState
427{
428 /** Pointer to the device instance. */
429 PPDMDEVINSR3 pDevIns;
430 /** Pointer to the connector of the attached audio driver. */
431 PPDMIAUDIOCONNECTOR pDrv;
432 /** Pointer to the attached audio driver. */
433 PPDMIBASE pDrvBase;
434 /** The base interface for LUN\#0. */
435 PDMIBASE IBase;
436 RTGCPHYS addrMMReg;
437 uint32_t au32Regs[113];
438 HDABDLEDESC stInBdle;
439 HDABDLEDESC stOutBdle;
440 HDABDLEDESC stMicBdle;
441 /* Interrupt on completion */
442 bool fCviIoc;
443 uint64_t u64CORBBase;
444 uint64_t u64RIRBBase;
445 uint64_t u64DPBase;
446 /* pointer on CORB buf */
447 uint32_t *pu32CorbBuf;
448 /* size in bytes of CORB buf */
449 uint32_t cbCorbBuf;
450 /* pointer on RIRB buf */
451 uint64_t *pu64RirbBuf;
452 /* size in bytes of RIRB buf */
453 uint32_t cbRirbBuf;
454 /* indicates if HDA in reset. */
455 bool fInReset;
456 CODECState Codec;
457 uint8_t u8Counter;
458 uint64_t u64BaseTS;
459} INTELHDLinkState, *PINTELHDLinkState;
460
461#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
462#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
463
464#define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In, \
465 SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
466#define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out, \
467 SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
468
469
470
471
472typedef struct PCIINTELHDLinkState
473{
474 PCIDevice dev;
475 INTELHDLinkState hda;
476} PCIINTELHDLinkState;
477
478
479DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
480DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
481DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
482DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
483DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
484DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
485DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
486DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
487DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
488DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
489DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
490DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
491DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
492DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
493DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
494DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
495DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
496DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
497DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
498DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
499
500DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
501DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
502DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
503DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
504DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
505DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
506DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
507DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
508DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
509DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
510DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
511DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
512DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
513DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
514DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
515
516static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc);
517static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
518static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
519#ifdef LOG_ENABLED
520static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
521#endif
522
523/* see 302349 p 6.2*/
524const static struct stIchIntelHDRegMap
525{
526 /** Register offset in the register space. */
527 uint32_t offset;
528 /** Size in bytes. Registers of size > 4 are in fact tables. */
529 uint32_t size;
530 /** Readable bits. */
531 uint32_t readable;
532 /** Writable bits. */
533 uint32_t writable;
534 /** Read callback. */
535 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
536 /** Write callback. */
537 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
538 /** Abbreviated name. */
539 const char *abbrev;
540 /** Full name. */
541 const char *name;
542} s_ichIntelHDRegMap[] =
543{
544 /* offset size read mask write mask read callback write callback abbrev full name */
545 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
546 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
547 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
548 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
549 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
550 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
551 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
552 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
553 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
554 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
555 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
556 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
557 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
558 //** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
559 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
560 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
561 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
562 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
563 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
564 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
565 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
566 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
567 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
568 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
569 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
570 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
571 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
572 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
573 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
574 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
575 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
576 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
577 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
578 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
579
580 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
581 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
582 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
583 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
584 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
585 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
586 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
587 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FMT" , "ISD0 Format" },
588 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
589 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
590
591 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
592 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
593 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
594 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
595 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
596 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
597 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
598 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FMT" , "ISD1 Format" },
599 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
600 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
601
602 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
603 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
604 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
605 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
606 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
607 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
608 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
609 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FMT" , "ISD2 Format" },
610 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
611 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
612
613 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
614 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
615 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
616 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
617 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
618 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
619 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
620 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FMT" , "ISD3 Format" },
621 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
622 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
623
624 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
625 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
626 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
627 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
628 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
629 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
630 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
631 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FMT" , "OSD0 Format" },
632 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
633 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
634
635 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
636 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
637 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
638 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
639 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
640 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
641 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
642 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FMT" , "OSD1 Format" },
643 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
644 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
645
646 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
647 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
648 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
649 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
650 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
651 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
652 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
653 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FMT" , "OSD2 Format" },
654 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
655 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
656
657 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
658 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
659 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
660 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
661 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
662 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
663 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
664 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FMT" , "OSD3 Format" },
665 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
666 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
667};
668
669static void inline hdaUpdatePosBuf(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
670{
671 if (pState->u64DPBase & DPBASE_ENABLED)
672 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
673 (pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
674}
675static uint32_t inline hdaFifoWToSz(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
676{
677#if 0
678 switch(HDA_STREAM_REG2(pState, FIFOW, pStreamDesc->u8Strm))
679 {
680 case HDA_SDFIFOW_8B: return 8;
681 case HDA_SDFIFOW_16B: return 16;
682 case HDA_SDFIFOW_32B: return 32;
683 default:
684 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
685 }
686#endif
687 return 0;
688}
689
690static int hdaProcessInterrupt(INTELHDLinkState* pState)
691{
692#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
693 ( INTCTL_SX((pState), num) \
694 && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
695 bool fIrq = false;
696 if ( INTCTL_CIE(pState)
697 && ( RIRBSTS_RINTFL(pState)
698 || RIRBSTS_RIRBOIS(pState)
699 || (STATESTS(pState) & WAKEEN(pState))))
700 fIrq = true;
701
702 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
703 || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
704 fIrq = true;
705
706 if (INTCTL_GIE(pState))
707 {
708 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
709 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
710 }
711 return VINF_SUCCESS;
712}
713
714static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
715{
716 int index = 0;
717 //** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
718 for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
719 {
720 if ( u32Offset >= s_ichIntelHDRegMap[index].offset
721 && u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
722 {
723 return index;
724 }
725 }
726 /* Aliases HDA spec 3.3.45 */
727 switch(u32Offset)
728 {
729 case 0x2084:
730 return HDA_REG_IND_NAME(SD0LPIB);
731 case 0x20A4:
732 return HDA_REG_IND_NAME(SD1LPIB);
733 case 0x20C4:
734 return HDA_REG_IND_NAME(SD2LPIB);
735 case 0x20E4:
736 return HDA_REG_IND_NAME(SD3LPIB);
737 case 0x2104:
738 return HDA_REG_IND_NAME(SD4LPIB);
739 case 0x2124:
740 return HDA_REG_IND_NAME(SD5LPIB);
741 case 0x2144:
742 return HDA_REG_IND_NAME(SD6LPIB);
743 case 0x2164:
744 return HDA_REG_IND_NAME(SD7LPIB);
745 }
746 return -1;
747}
748
749static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
750{
751 int rc = VINF_SUCCESS;
752 if (fLocal)
753 {
754 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
755 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
756 if (RT_FAILURE(rc))
757 AssertRCReturn(rc, rc);
758#ifdef DEBUG_CMD_BUFFER
759 uint8_t i = 0;
760 do
761 {
762 Log(("hda: corb%02x: ", i));
763 uint8_t j = 0;
764 do
765 {
766 const char *prefix;
767 if ((i + j) == CORBRP(pState))
768 prefix = "[R]";
769 else if ((i + j) == CORBWP(pState))
770 prefix = "[W]";
771 else
772 prefix = " "; /* three spaces */
773 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
774 j++;
775 } while (j < 8);
776 Log(("\n"));
777 i += 8;
778 } while(i != 0);
779#endif
780 }
781 else
782 {
783 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
784 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
785 if (RT_FAILURE(rc))
786 AssertRCReturn(rc, rc);
787#ifdef DEBUG_CMD_BUFFER
788 uint8_t i = 0;
789 do {
790 Log(("hda: rirb%02x: ", i));
791 uint8_t j = 0;
792 do {
793 const char *prefix;
794 if ((i + j) == RIRBWP(pState))
795 prefix = "[W]";
796 else
797 prefix = " ";
798 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
799 } while (++j < 8);
800 Log(("\n"));
801 i += 8;
802 } while (i != 0);
803#endif
804 }
805 return rc;
806}
807
808static int hdaCORBCmdProcess(INTELHDLinkState *pState)
809{
810 int rc;
811 uint8_t corbRp;
812 uint8_t corbWp;
813 uint8_t rirbWp;
814
815 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
816
817 rc = hdaCmdSync(pState, true);
818 if (RT_FAILURE(rc))
819 AssertRCReturn(rc, rc);
820 corbRp = CORBRP(pState);
821 corbWp = CORBWP(pState);
822 rirbWp = RIRBWP(pState);
823 Assert((corbWp != corbRp));
824 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
825 while (corbRp != corbWp)
826 {
827 uint32_t cmd;
828 uint64_t resp;
829 corbRp++;
830 cmd = pState->pu32CorbBuf[corbRp];
831 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
832 if (RT_FAILURE(rc))
833 AssertRCReturn(rc, rc);
834 Assert(pfn);
835 (rirbWp)++;
836 rc = pfn(&pState->Codec, cmd, &resp);
837 if (RT_FAILURE(rc))
838 AssertRCReturn(rc, rc);
839 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
840 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
841 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
842 {
843 Log(("hda: unexpected unsolicited response.\n"));
844 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
845 return rc;
846 }
847 pState->pu64RirbBuf[rirbWp] = resp;
848 pState->u8Counter++;
849 if (pState->u8Counter == RINTCNT_N(pState))
850 break;
851 }
852 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
853 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
854 rc = hdaCmdSync(pState, false);
855 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
856 if (RIRBCTL_RIRB_RIC(pState))
857 {
858 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
859 pState->u8Counter = 0;
860 rc = hdaProcessInterrupt(pState);
861 }
862 if (RT_FAILURE(rc))
863 AssertRCReturn(rc, rc);
864 return rc;
865}
866
867static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
868{
869 Log(("hda: reset of stream (%d) started\n", u8Strm));
870 Assert(( pState
871 && pBdle
872 && pStreamDesc
873 && u8Strm <= 7));
874 memset(pBdle, 0, sizeof(HDABDLEDESC));
875 *pStreamDesc->pu32Lpib = 0;
876 *pStreamDesc->pu32Sts = 0;
877 /* According to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
878 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
879 HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
880
881 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
882 HDA_STREAM_REG2(pState, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
883 HDA_STREAM_REG2(pState, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
884 HDA_STREAM_REG2(pState, CBL, u8Strm) = 0;
885 HDA_STREAM_REG2(pState, LVI, u8Strm) = 0;
886 HDA_STREAM_REG2(pState, FMT, u8Strm) = 0;
887 HDA_STREAM_REG2(pState, BDPU, u8Strm) = 0;
888 HDA_STREAM_REG2(pState, BDPL, u8Strm) = 0;
889 Log(("hda: reset of stream (%d) finished\n", u8Strm));
890}
891
892
893DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
894{
895 *pu32Value = 0;
896 return VINF_SUCCESS;
897}
898DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
899{
900 return VINF_SUCCESS;
901}
902/* U8 */
903DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
904{
905 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
906 return hdaRegReadU32(pState, offset, index, pu32Value);
907}
908
909DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
910{
911 Assert(((u32Value & 0xffffff00) == 0));
912 return hdaRegWriteU32(pState, offset, index, u32Value);
913}
914/* U16 */
915DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
916{
917 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
918 return hdaRegReadU32(pState, offset, index, pu32Value);
919}
920
921DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
922{
923 Assert(((u32Value & 0xffff0000) == 0));
924 return hdaRegWriteU32(pState, offset, index, u32Value);
925}
926
927/* U24 */
928DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
929{
930 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
931 return hdaRegReadU32(pState, offset, index, pu32Value);
932}
933
934DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
935{
936 Assert(((u32Value & 0xff000000) == 0));
937 return hdaRegWriteU32(pState, offset, index, u32Value);
938}
939/* U32 */
940DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
941{
942 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
943 return VINF_SUCCESS;
944}
945
946DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
947{
948 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
949 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
950 return VINF_SUCCESS;
951}
952
953DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
954{
955 return hdaRegReadU32(pState, offset, index, pu32Value);
956}
957
958DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
959{
960 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
961 {
962 /* exit reset state */
963 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
964 pState->fInReset = false;
965 }
966 else
967 {
968 /* enter reset state*/
969 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
970 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
971 {
972 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
973 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
974 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
975 }
976 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
977 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
978 pState->fInReset = true;
979 }
980 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
981 {
982 /* Flush: GSTS:1 set, see 6.2.6*/
983 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
984 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
985 }
986 return VINF_SUCCESS;
987}
988
989DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
990{
991 uint32_t v = pState->au32Regs[index];
992 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
993 pState->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
994 return VINF_SUCCESS;
995}
996
997DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
998{
999 uint32_t v = 0;
1000 if ( RIRBSTS_RIRBOIS(pState)
1001 || RIRBSTS_RINTFL(pState)
1002 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
1003 || STATESTS(pState))
1004 v |= RT_BIT(30);
1005#define HDA_IS_STREAM_EVENT(pState, stream) \
1006 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1007 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1008 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1009#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
1010 MARK_STREAM(pState, 0, v);
1011 MARK_STREAM(pState, 1, v);
1012 MARK_STREAM(pState, 2, v);
1013 MARK_STREAM(pState, 3, v);
1014 MARK_STREAM(pState, 4, v);
1015 MARK_STREAM(pState, 5, v);
1016 MARK_STREAM(pState, 6, v);
1017 MARK_STREAM(pState, 7, v);
1018 v |= v ? RT_BIT(31) : 0;
1019 *pu32Value = v;
1020 return VINF_SUCCESS;
1021}
1022
1023DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1024{
1025 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1026 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pState)) - pState->u64BaseTS, 24, 1000);
1027 return VINF_SUCCESS;
1028}
1029
1030DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1031{
1032 return hdaRegReadU16(pState, offset, index, pu32Value);
1033}
1034
1035DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1036{
1037 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1038 CORBRP(pState) = 0;
1039 else
1040 return hdaRegWriteU8(pState, offset, index, u32Value);
1041 return VINF_SUCCESS;
1042}
1043
1044DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1045{
1046 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
1047 AssertRC(rc);
1048 if ( CORBWP(pState) != CORBRP(pState)
1049 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
1050 return hdaCORBCmdProcess(pState);
1051 return rc;
1052}
1053
1054DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1055{
1056 uint32_t v = CORBSTS(pState);
1057 CORBSTS(pState) &= ~(v & u32Value);
1058 return VINF_SUCCESS;
1059}
1060
1061DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1062{
1063 int rc;
1064 rc = hdaRegWriteU16(pState, offset, index, u32Value);
1065 if (RT_FAILURE(rc))
1066 AssertRCReturn(rc, rc);
1067 if (CORBWP(pState) == CORBRP(pState))
1068 return VINF_SUCCESS;
1069 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1070 return VINF_SUCCESS;
1071 rc = hdaCORBCmdProcess(pState);
1072 return rc;
1073}
1074
1075DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1076{
1077 return hdaRegReadU24(pState, offset, index, pu32Value);
1078}
1079
1080DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1081{
1082 bool fRun = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1083 bool fInRun = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1084 bool fReset = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1085 bool fInReset = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1086 int rc = VINF_SUCCESS;
1087 if (fInReset)
1088 {
1089 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1090 * from reset
1091 */
1092 Assert((!fReset));
1093 Log(("hda: guest initiate exit of stream reset.\n"));
1094 goto done;
1095 }
1096 else if (fReset)
1097 {
1098 /*
1099 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1100 */
1101 uint8_t u8Strm = 0;
1102 PHDABDLEDESC pBdle = NULL;
1103 HDASTREAMTRANSFERDESC stStreamDesc;
1104 Assert((!fInRun && !fRun));
1105 switch (index)
1106 {
1107 case ICH6_HDA_REG_SD0CTL:
1108 u8Strm = 0;
1109 pBdle = &pState->stInBdle;
1110 break;
1111 case ICH6_HDA_REG_SD4CTL:
1112 u8Strm = 4;
1113 pBdle = &pState->stOutBdle;
1114 break;
1115 default:
1116 Log(("hda: changing SRST bit on non-attached stream\n"));
1117 goto done;
1118 }
1119 Log(("hda: guest initiate enter to stream reset.\n"));
1120 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1121 hdaStreamReset(pState, pBdle, &stStreamDesc, u8Strm);
1122 goto done;
1123 }
1124
1125 /* we enter here to change DMA states only */
1126 if ( (fInRun && !fRun)
1127 || (fRun && !fInRun))
1128 {
1129 Assert((!fReset && !fInReset));
1130 switch (index)
1131 {
1132 case ICH6_HDA_REG_SD0CTL:
1133 AUD_set_active_in(ISD0FMT_TO_AUDIO_SELECTOR(pState), fRun);
1134 break;
1135 case ICH6_HDA_REG_SD4CTL:
1136 AUD_set_active_out(OSD0FMT_TO_AUDIO_SELECTOR(pState), fRun);
1137 break;
1138 default:
1139 Log(("hda: changing RUN bit on non-attached stream\n"));
1140 goto done;
1141 }
1142 }
1143
1144 done:
1145 rc = hdaRegWriteU24(pState, offset, index, u32Value);
1146 if (RT_FAILURE(rc))
1147 AssertRCReturn(rc, VINF_SUCCESS);
1148 return rc;
1149}
1150
1151DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1152{
1153 uint32_t v = HDA_REG_IND(pState, index);
1154 v &= ~(u32Value & v);
1155 HDA_REG_IND(pState, index) = v;
1156 hdaProcessInterrupt(pState);
1157 return VINF_SUCCESS;
1158}
1159
1160DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1161{
1162 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1163 if (RT_FAILURE(rc))
1164 AssertRCReturn(rc, VINF_SUCCESS);
1165 return rc;
1166}
1167
1168DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1169{
1170 switch (u32Value)
1171 {
1172 case HDA_SDFIFOW_8B:
1173 case HDA_SDFIFOW_16B:
1174 case HDA_SDFIFOW_32B:
1175 return hdaRegWriteU16(pState, offset, index, u32Value);
1176 default:
1177 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1178 return hdaRegWriteU16(pState, offset, index, HDA_SDFIFOW_32B);
1179 }
1180 return VINF_SUCCESS;
1181}
1182/*
1183 * Note this method could be called for changing value on Output Streams only (ICH6 datacheet 18.2.39)
1184 *
1185 */
1186DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1187{
1188 switch (index)
1189 {
1190 /* SDInFIFOS is RO, n=0-3 */
1191 case ICH6_HDA_REG_SD0FIFOS:
1192 case ICH6_HDA_REG_SD1FIFOS:
1193 case ICH6_HDA_REG_SD2FIFOS:
1194 case ICH6_HDA_REG_SD3FIFOS:
1195 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1196 return VINF_SUCCESS;
1197 case ICH6_HDA_REG_SD4FIFOS:
1198 case ICH6_HDA_REG_SD5FIFOS:
1199 case ICH6_HDA_REG_SD6FIFOS:
1200 case ICH6_HDA_REG_SD7FIFOS:
1201 switch(u32Value)
1202 {
1203 case HDA_SDONFIFO_16B:
1204 case HDA_SDONFIFO_32B:
1205 case HDA_SDONFIFO_64B:
1206 case HDA_SDONFIFO_128B:
1207 case HDA_SDONFIFO_192B:
1208 return hdaRegWriteU16(pState, offset, index, u32Value);
1209
1210 case HDA_SDONFIFO_256B:
1211 Log(("hda: 256 bit is unsupported, HDA is switched into 192B mode\n"));
1212 default:
1213 return hdaRegWriteU16(pState, offset, index, HDA_SDONFIFO_192B);
1214 }
1215 return VINF_SUCCESS;
1216 default:
1217 AssertMsgFailed(("Something wierd happens with register lookup routine"));
1218 }
1219 return VINF_SUCCESS;
1220}
1221
1222DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1223{
1224 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1225 if (RT_FAILURE(rc))
1226 AssertRCReturn(rc, VINF_SUCCESS);
1227 return rc;
1228}
1229
1230DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1231{
1232 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1233 if (RT_FAILURE(rc))
1234 AssertRCReturn(rc, VINF_SUCCESS);
1235 return rc;
1236}
1237
1238DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1239{
1240 int rc = VINF_SUCCESS;
1241 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1242 if ( CORBWP(pState) != CORBRP(pState)
1243 || HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1244 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1245
1246 rc = hdaRegReadU32(pState, offset, index, pu32Value);
1247 return rc;
1248}
1249
1250DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1251{
1252 int rc = VINF_SUCCESS;
1253 uint64_t resp;
1254 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1255 /*
1256 * if guest set ICB bit of IRS register HDA should process verb in IC register and
1257 * writes response in IR register and set IRV (valid in case of success) bit of IRS register.
1258 */
1259 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1260 && !IRS_ICB(pState))
1261 {
1262 uint32_t cmd = IC(pState);
1263 if (CORBWP(pState) != CORBRP(pState))
1264 {
1265 /*
1266 * 3.4.3 defines behaviour of immediate Command status register.
1267 */
1268 LogRel(("hda: guest has tried process immediate verb (%x) with active CORB\n", cmd));
1269 return rc;
1270 }
1271 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1272 Log(("hda: IC:%x\n", cmd));
1273 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1274 if (RT_FAILURE(rc))
1275 AssertRCReturn(rc, rc);
1276 rc = pfn(&pState->Codec, cmd, &resp);
1277 if (RT_FAILURE(rc))
1278 AssertRCReturn(rc, rc);
1279 IR(pState) = (uint32_t)resp;
1280 Log(("hda: IR:%x\n", IR(pState)));
1281 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1282 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1283 return rc;
1284 }
1285 /*
1286 * when guest's read the response it should clean the IRV bit of the IRS register.
1287 */
1288 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1289 && IRS_IRV(pState))
1290 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1291 return rc;
1292}
1293
1294DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1295{
1296 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1297 {
1298 RIRBWP(pState) = 0;
1299 }
1300 /*The rest of bits are O, see 6.2.22 */
1301 return VINF_SUCCESS;
1302}
1303
1304DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1305{
1306 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1307 if (RT_FAILURE(rc))
1308 AssertRCReturn(rc, rc);
1309 switch(index)
1310 {
1311 case ICH6_HDA_REG_CORBLBASE:
1312 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1313 pState->u64CORBBase |= pState->au32Regs[index];
1314 break;
1315 case ICH6_HDA_REG_CORBUBASE:
1316 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1317 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1318 break;
1319 case ICH6_HDA_REG_RIRLBASE:
1320 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1321 pState->u64RIRBBase |= pState->au32Regs[index];
1322 break;
1323 case ICH6_HDA_REG_RIRUBASE:
1324 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1325 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1326 break;
1327 case ICH6_HDA_REG_DPLBASE:
1328 /* @todo: first bit has special meaning */
1329 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1330 pState->u64DPBase |= pState->au32Regs[index];
1331 break;
1332 case ICH6_HDA_REG_DPUBASE:
1333 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1334 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1335 break;
1336 default:
1337 AssertMsgFailed(("Invalid index"));
1338 }
1339 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1340 return rc;
1341}
1342
1343DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1344{
1345 uint8_t v = RIRBSTS(pState);
1346 RIRBSTS(pState) &= ~(v & u32Value);
1347
1348 return hdaProcessInterrupt(pState);
1349}
1350
1351#ifdef LOG_ENABLED
1352static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1353{
1354#if 0
1355 uint64_t addr;
1356 uint32_t len;
1357 uint32_t ioc;
1358 uint8_t bdle[16];
1359 uint32_t counter;
1360 uint32_t i;
1361 uint32_t sum = 0;
1362 Assert(pBdle && pBdle->u32BdleMaxCvi);
1363 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1364 {
1365 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1366 addr = *(uint64_t *)bdle;
1367 len = *(uint32_t *)&bdle[8];
1368 ioc = *(uint32_t *)&bdle[12];
1369 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1370 sum += len;
1371 }
1372 Log(("hda: sum: %d\n", sum));
1373 for (i = 0; i < 8; ++i)
1374 {
1375 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1376 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
1377 i , counter));
1378 }
1379#endif
1380}
1381#endif
1382
1383static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1384{
1385 uint8_t bdle[16];
1386 Assert(( pStreamDesc->u64BaseDMA
1387 && pBdle
1388 && pBdle->u32BdleMaxCvi));
1389 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1390 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1391 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1392 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1393#ifdef LOG_ENABLED
1394 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1395#endif
1396}
1397
1398static inline uint32_t hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1399{
1400 uint32_t cb2Copy;
1401 /*
1402 * Amounts of bytes depends on current position in buffer (u32BdleCviLen-u32BdleCviPos)
1403 */
1404 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1405 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1406 /*
1407 * we may increase the counter in range of [0, FIFOS + 1]
1408 */
1409 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1410 Assert((u32SoundBackendBufferBytesAvail > 0));
1411
1412 /* sanity check to avoid overriding sound backend buffer */
1413 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1414 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1415
1416 if (cb2Copy <= pBdle->cbUnderFifoW)
1417 return 0;
1418 cb2Copy -= pBdle->cbUnderFifoW; /* forcely reserve amount of ureported bytes to copy */
1419 return cb2Copy;
1420}
1421
1422static inline void hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1423{
1424 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1425 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1426 Assert((cbCopied));
1427 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1428 /* Assertion!!! It was copied less than cbUnderFifoW
1429 * Probably we need to move the buffer, but it rather hard to imagine situation
1430 * why it may happen.
1431 */
1432 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write whole buffer including not reported bytes */
1433 if ( pBdle->cbUnderFifoW
1434 && pBdle->cbUnderFifoW <= cbCopied)
1435 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1436
1437 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1438 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Assumption failed */
1439
1440 /* We always increment position on DMA buffer counter because we're always reading to intermediate buffer */
1441 pBdle->u32BdleCviPos += cbArranged2Copy;
1442
1443 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1444 /* We reports all bytes (including unreported previously) */
1445 *pu32DMACursor += cbCopied;
1446 /* reducing backend counter on amount of bytes we copied to backend */
1447 *pu32BackendBufferCapacity -= cbCopied;
1448 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1449 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1450}
1451
1452static inline void hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1453{
1454 Assert((cbCopied, cbArranged2Copy));
1455 *pu32BackendBufferCapacity -= cbCopied;
1456 pBdle->u32BdleCviPos += cbCopied;
1457 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1458 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1459 pBdle->cbUnderFifoW = 0;
1460 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1461 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1462}
1463
1464static inline void hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1465{
1466 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1467 pBdle->u32BdleCviPos += cbCopied;
1468 pBdle->cbUnderFifoW += cbCopied;
1469 /* In case of read transaction we're always coping from backend buffer */
1470 if (pu32BackendBufferCapacity)
1471 *pu32BackendBufferCapacity -= cbCopied;
1472 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1473 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pState, pStreamDesc)));
1474}
1475static inline bool hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1476{
1477 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1478 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1479
1480 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1481
1482 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1483 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1484 hdaUpdatePosBuf(pState, pStreamDesc);
1485
1486 /* don't touch BdleCvi counter on uninitialized descriptor */
1487 if ( pBdle->u32BdleCviPos
1488 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1489 {
1490 pBdle->u32BdleCviPos = 0;
1491 pBdle->u32BdleCvi++;
1492 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1493 pBdle->u32BdleCvi = 0;
1494 }
1495 return fOnBufferEdge;
1496}
1497
1498static inline void hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbInc)
1499{
1500 /*
1501 * if we're under FIFO Watermark it's expected that HDA doesn't fetch anything.
1502 * (ICH6 datasheet 18.2.38)
1503 */
1504 if (!pBdle->cbUnderFifoW)
1505 {
1506 *pStreamDesc->pu32Lpib += cbInc;
1507
1508 /*
1509 * Assert. Overlapping of buffer counter shouldn't happen.
1510 */
1511 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1512
1513 hdaUpdatePosBuf(pState, pStreamDesc);
1514
1515 }
1516}
1517
1518static inline bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1519{
1520 bool fDoNextTransferLoop = true;
1521 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1522 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1523 {
1524 if ( !pBdle->cbUnderFifoW
1525 && pBdle->fBdleCviIoc)
1526 {
1527 /*
1528 * @todo - more carefully investigate BCIS flag.
1529 * Speech synthesis works fine on Mac Guest if this bit isn't set
1530 * but in general sound quality becomes lesser.
1531 */
1532 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1533
1534 /*
1535 * we should generate the interrupt if ICE bit of SDCTL register is set.
1536 */
1537 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1538 hdaProcessInterrupt(pState);
1539 }
1540 fDoNextTransferLoop = false;
1541 }
1542 return fDoNextTransferLoop;
1543}
1544
1545/*
1546 * hdaReadAudio - copies samples from Qemu Sound back-end to DMA.
1547 * Note: this function writes immediately to DMA buffer, but "reports bytes" when all conditions meet (FIFOW)
1548 */
1549static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1550{
1551 PHDABDLEDESC pBdle = &pState->stInBdle;
1552 uint32_t cbTransfered = 0;
1553 uint32_t cb2Copy = 0;
1554 uint32_t cbBackendCopy = 0;
1555
1556 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1557
1558 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1559 if (!cb2Copy)
1560 {
1561 /* if we enter here we can't report "unreported bits" */
1562 *fStop = true;
1563 goto done;
1564 }
1565
1566
1567 /*
1568 * read from backend input line to last ureported position or at the begining.
1569 */
1570 cbBackendCopy = AUD_read (ISD0FMT_TO_AUDIO_SELECTOR(pState), pBdle->au8HdaBuffer, cb2Copy);
1571 /*
1572 * write on the HDA DMA
1573 */
1574 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1575
1576 /* Don't see reasons why cb2Copy could differ from cbBackendCopy */
1577 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1578
1579 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pState, 0))
1580 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1581 else
1582 {
1583 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1584 *fStop = true;
1585 }
1586 done:
1587 Assert((cbTransfered <= (SDFIFOS(pState, 0) + 1)));
1588 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransfered: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1589 return cbTransfered;
1590}
1591
1592static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1593{
1594 PHDABDLEDESC pBdle = &pState->stOutBdle;
1595 uint32_t cbTransfered = 0;
1596 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1597 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1598
1599 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1600
1601 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1602
1603 /*
1604 * Copy from DMA to the corresponding hdaBuffer (if there exists some bytes from the previous not reported transfer we write to ''pBdle->cbUnderFifoW'' offset)
1605 */
1606 if (!cb2Copy)
1607 {
1608 *fStop = true;
1609 goto done;
1610 }
1611
1612 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1613 /*
1614 * Write to audio backend. we should be sure whether we have enought bytes to copy to Audio backend.
1615 */
1616 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, pStreamDesc))
1617 {
1618 /*
1619 * We feed backend with new portion of fetched samples including not reported.
1620 */
1621 cbBackendCopy = AUD_write (OSD0FMT_TO_AUDIO_SELECTOR(pState), pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1622 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1623 }
1624 else
1625 {
1626 /* Not enough bytes to be processed and reported, check luck on next enterence */
1627 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cb2Copy, NULL);
1628 *fStop = true;
1629 }
1630
1631 done:
1632 Assert((cbTransfered <= (SDFIFOS(pState, 4) + 1)));
1633 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransfered:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1634 return cbTransfered;
1635}
1636
1637DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1638{
1639 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1640 return VINF_SUCCESS;
1641}
1642
1643static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc)
1644{
1645 Assert(( pState
1646 && pBdle
1647 && pStreamDesc
1648 && u8Strm <= 7));
1649 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1650 pStreamDesc->u8Strm = u8Strm;
1651 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pState, CTL, u8Strm);
1652 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pState, BDPL, u8Strm),
1653 HDA_STREAM_REG2(pState, BDPU, u8Strm));
1654 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pState, LPIB, u8Strm);
1655 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pState, STS, u8Strm);
1656 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pState, CBL, u8Strm);
1657 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pState, FIFOS, u8Strm);
1658
1659 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pState, LVI, u8Strm);
1660#ifdef LOG_ENABLED
1661 if ( pBdle
1662 && pBdle->u32BdleMaxCvi)
1663 {
1664 Log(("Initialization of transfer descriptor:\n"));
1665 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1666 }
1667#endif
1668}
1669
1670DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1671{
1672 bool fStop = false;
1673 uint8_t u8Strm = 0;
1674 PHDABDLEDESC pBdle = NULL;
1675 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1676 HDASTREAMTRANSFERDESC stStreamDesc;
1677 uint32_t nBytes;
1678 switch (src)
1679 {
1680 case PO_INDEX:
1681 {
1682 u8Strm = 4;
1683 pBdle = &pState->stOutBdle;
1684 break;
1685 }
1686 case PI_INDEX:
1687 {
1688 u8Strm = 0;
1689 pBdle = &pState->stInBdle;
1690 break;
1691 }
1692 default:
1693 return;
1694 }
1695 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1696 while( avail && !fStop)
1697 {
1698 Assert ( (stStreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1699 && avail
1700 && stStreamDesc.u64BaseDMA);
1701
1702 /* Fetch the Buffer Descriptor Entry (BDE). */
1703
1704 if (hdaIsTransferCountersOverlapped(pState, pBdle, &stStreamDesc))
1705 hdaFetchBdle(pState, pBdle, &stStreamDesc);
1706 *stStreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1707 Assert((avail >= 0 && (stStreamDesc.u32Cbl >= (*stStreamDesc.pu32Lpib)))); /* sanity */
1708 uint32_t u32CblLimit = stStreamDesc.u32Cbl - (*stStreamDesc.pu32Lpib);
1709 Assert((u32CblLimit > hdaFifoWToSz(pState, &stStreamDesc)));
1710 Log(("hda: CBL=%d, LPIB=%d\n", stStreamDesc.u32Cbl, *stStreamDesc.pu32Lpib));
1711 switch (src)
1712 {
1713 case PO_INDEX:
1714 nBytes = hdaWriteAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1715 break;
1716 case PI_INDEX:
1717 nBytes = hdaReadAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1718 break;
1719 default:
1720 nBytes = 0;
1721 fStop = true;
1722 AssertMsgFailed(("Unsupported"));
1723 }
1724 Assert(nBytes <= (stStreamDesc.u32Fifos + 1));
1725 *stStreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1726
1727 /* Process end of buffer condition. */
1728 hdaStreamCounterUpdate(pState, pBdle, &stStreamDesc, nBytes);
1729 fStop = !fStop ? !hdaDoNextTransferCycle(pState, pBdle, &stStreamDesc) : fStop;
1730 }
1731}
1732
1733/**
1734 * Handle register read operation.
1735 *
1736 * Looks up and calls appropriate handler.
1737 *
1738 * @note: while implementation was detected so called "forgotten" or "hole" registers
1739 * which description is missed in RPM, datasheet or spec.
1740 *
1741 * @returns VBox status code.
1742 *
1743 * @param pState The device state structure.
1744 * @param uOffset Register offset in memory-mapped frame.
1745 * @param pv Where to fetch the value.
1746 * @param cb Number of bytes to write.
1747 * @thread EMT
1748 */
1749PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1750{
1751 int rc = VINF_SUCCESS;
1752 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1753 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1754 int index = hdaLookup(&pThis->hda, u32Offset);
1755 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1756 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1757
1758 if ( index == -1
1759 || cb > 4)
1760 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", u32Offset, cb));
1761
1762 if (index != -1)
1763 {
1764 uint32_t mask = 0;
1765 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1766 uint32_t v = 0;
1767 switch(cb)
1768 {
1769 case 1: mask = 0x000000ff; break;
1770 case 2: mask = 0x0000ffff; break;
1771 case 3: mask = 0x00ffffff; break;
1772 case 4: mask = 0xffffffff; break;
1773 }
1774 mask <<= shift;
1775 rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1776 *(uint32_t *)pv = (v & mask) >> shift;
1777 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
1778 return rc;
1779 }
1780 *(uint32_t *)pv = 0xFF;
1781 Log(("hda: hole at %X is accessed for read\n", u32Offset));
1782 return rc;
1783}
1784
1785/**
1786 * Handle register write operation.
1787 *
1788 * Looks up and calls appropriate handler.
1789 *
1790 * @returns VBox status code.
1791 *
1792 * @param pState The device state structure.
1793 * @param uOffset Register offset in memory-mapped frame.
1794 * @param pv Where to fetch the value.
1795 * @param cb Number of bytes to write.
1796 * @thread EMT
1797 */
1798PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1799{
1800 int rc = VINF_SUCCESS;
1801 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1802 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1803 int index = hdaLookup(&pThis->hda, u32Offset);
1804
1805 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1806 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1807
1808 if ( index == -1
1809 || cb > 4)
1810 LogRel(("hda: Invalid write access @0x%x(of bytes:%d)\n", u32Offset, cb));
1811
1812 if (index != -1)
1813 {
1814 uint32_t v = pThis->hda.au32Regs[index];
1815 uint32_t mask = 0;
1816 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1817 switch(cb)
1818 {
1819 case 1: mask = 0xffffff00; break;
1820 case 2: mask = 0xffff0000; break;
1821 case 3: mask = 0xff000000; break;
1822 case 4: mask = 0x00000000; break;
1823 }
1824 mask <<= shift;
1825 *(uint32_t *)pv = ((v & mask) | (*(uint32_t *)pv & ~mask)) >> shift;
1826 rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
1827 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
1828 return rc;
1829 }
1830 Log(("hda: hole at %X is accessed for write\n", u32Offset));
1831 return rc;
1832}
1833
1834/**
1835 * Callback function for mapping a PCI I/O region.
1836 *
1837 * @return VBox status code.
1838 * @param pPciDev Pointer to PCI device.
1839 * Use pPciDev->pDevIns to get the device instance.
1840 * @param iRegion The region number.
1841 * @param GCPhysAddress Physical address of the region.
1842 * If iType is PCI_ADDRESS_SPACE_IO, this is an
1843 * I/O port, else it's a physical address.
1844 * This address is *NOT* relative
1845 * to pci_mem_base like earlier!
1846 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
1847 */
1848static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
1849 RTGCPHYS GCPhysAddress, uint32_t cb,
1850 PCIADDRESSSPACE enmType)
1851{
1852 int rc;
1853 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1854 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1855 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1856
1857 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1858 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
1859 hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
1860
1861 if (RT_FAILURE(rc))
1862 return rc;
1863
1864 pThis->hda.addrMMReg = GCPhysAddress;
1865 return VINF_SUCCESS;
1866}
1867
1868/**
1869 * Saves a state of the HDA device.
1870 *
1871 * @returns VBox status code.
1872 * @param pDevIns The device instance.
1873 * @param pSSMHandle The handle to save the state to.
1874 */
1875static DECLCALLBACK(int) hdaSaveExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1876{
1877 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1878 /* Save Codec nodes states */
1879 codecSaveState(&pThis->hda.Codec, pSSMHandle);
1880 /* Save MMIO registers */
1881 SSMR3PutMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1882 /* Save HDA dma counters */
1883 SSMR3PutMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
1884 SSMR3PutMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
1885 SSMR3PutMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
1886 return VINF_SUCCESS;
1887}
1888
1889/**
1890 * Loads a saved HDA device state.
1891 *
1892 * @returns VBox status code.
1893 * @param pDevIns The device instance.
1894 * @param pSSMHandle The handle to the saved state.
1895 * @param uVersion The data unit version number.
1896 * @param uPass The data pass.
1897 */
1898static DECLCALLBACK(int) hdaLoadExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1899 uint32_t uVersion, uint32_t uPass)
1900{
1901 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1902 /* Load Codec nodes states */
1903 AssertMsgReturn (uVersion == HDA_SSM_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1904 Assert (uPass == SSM_PASS_FINAL); NOREF(uPass);
1905
1906 codecLoadState(&pThis->hda.Codec, pSSMHandle);
1907 /* Load MMIO registers */
1908 SSMR3GetMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1909 /* Load HDA dma counters */
1910 SSMR3GetMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
1911 SSMR3GetMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
1912 SSMR3GetMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
1913
1914 AUD_set_active_in(ISD0FMT_TO_AUDIO_SELECTOR(&pThis->hda), SDCTL(&pThis->hda, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1915 AUD_set_active_out(OSD0FMT_TO_AUDIO_SELECTOR(&pThis->hda), SDCTL(&pThis->hda, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1916
1917 pThis->hda.u64CORBBase = CORBLBASE(&pThis->hda);
1918 pThis->hda.u64CORBBase |= ((uint64_t)CORBUBASE(&pThis->hda)) << 32;
1919 pThis->hda.u64RIRBBase = RIRLBASE(&pThis->hda);
1920 pThis->hda.u64RIRBBase |= ((uint64_t)RIRUBASE(&pThis->hda)) << 32;
1921 pThis->hda.u64DPBase = DPLBASE(&pThis->hda);
1922 pThis->hda.u64DPBase |= ((uint64_t)DPUBASE(&pThis->hda)) << 32;
1923 return VINF_SUCCESS;
1924}
1925
1926/**
1927 * Reset notification.
1928 *
1929 * @returns VBox status.
1930 * @param pDevIns The device instance data.
1931 *
1932 * @remark The original sources didn't install a reset handler, but it seems to
1933 * make sense to me so we'll do it.
1934 */
1935static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
1936{
1937 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1938 GCAP(&pThis->hda) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
1939 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
1940 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1941 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1942 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
1943 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
1944 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
1945 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
1946 CORBRP(&pThis->hda) = 0x0;
1947 RIRBWP(&pThis->hda) = 0x0;
1948
1949 Log(("hda: inter HDA reset.\n"));
1950 pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
1951
1952 if (pThis->hda.pu32CorbBuf)
1953 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
1954 else
1955 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
1956
1957 pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
1958 if (pThis->hda.pu64RirbBuf)
1959 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
1960 else
1961 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
1962
1963 pThis->hda.u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
1964
1965 HDABDLEDESC stEmptyBdle;
1966 for(uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
1967 {
1968 HDASTREAMTRANSFERDESC stStreamDesc;
1969 PHDABDLEDESC pBdle = NULL;
1970 if (u8Strm == 0)
1971 pBdle = &pThis->hda.stInBdle;
1972 else if(u8Strm == 4)
1973 pBdle = &pThis->hda.stOutBdle;
1974 else
1975 {
1976 memset(&stEmptyBdle, 0, sizeof(HDABDLEDESC));
1977 pBdle = &stEmptyBdle;
1978 }
1979 hdaInitTransferDescriptor(&pThis->hda, pBdle, u8Strm, &stStreamDesc);
1980 /* hdaStreamReset prevents changing SRST bit, so we zerro it here forcely. */
1981 HDA_STREAM_REG2(&pThis->hda, CTL, u8Strm) = 0;
1982 hdaStreamReset(&pThis->hda, pBdle, &stStreamDesc, u8Strm);
1983 }
1984
1985 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
1986 STATESTS(&pThis->hda) = 0x1;
1987
1988 Log(("hda: reset finished\n"));
1989}
1990
1991/**
1992 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1993 */
1994static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
1995 const char *pszIID)
1996{
1997 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
1998 Assert(&pThis->hda.IBase == pInterface);
1999
2000 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
2001 return NULL;
2002}
2003
2004//#define HDA_AS_PCI_EXPRESS
2005
2006/**
2007 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2008 */
2009static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
2010 PCFGMNODE pCfgHandle)
2011{
2012 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2013 INTELHDLinkState *s = &pThis->hda;
2014 int rc;
2015
2016 Assert(iInstance == 0);
2017 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2018
2019 /*
2020 * Validations.
2021 */
2022 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
2023 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2024 N_ ("Invalid configuration for the INTELHD device"));
2025
2026 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
2027 // poll some register(s).
2028
2029 /*
2030 * Initialize data (most of it anyway).
2031 */
2032 s->pDevIns = pDevIns;
2033 /* IBase */
2034 s->IBase.pfnQueryInterface = hdaQueryInterface;
2035
2036 /* PCI Device (the assertions will be removed later) */
2037 PCIDevSetVendorId (&pThis->dev, HDA_PCI_VENDOR_ID); /* nVidia */
2038 PCIDevSetDeviceId (&pThis->dev, HDA_PCI_DEICE_ID); /* HDA */
2039
2040 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
2041 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2042 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
2043 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
2044 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
2045 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2046 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
2047 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
2048 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2049 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
2050 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */
2051
2052#if defined(HDA_AS_PCI_EXPRESS)
2053 PCIDevSetCapabilityList (&pThis->dev, 0x80);
2054#elif defined(VBOX_WITH_MSI_DEVICES)
2055 PCIDevSetCapabilityList (&pThis->dev, 0x60);
2056#else
2057 PCIDevSetCapabilityList (&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
2058#endif
2059
2060 //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2061 // of these values needs to be properly documented!
2062 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2063 PCIDevSetByte(&pThis->dev, 0x40, 0x01);
2064
2065 /* Power Management */
2066 PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2067 PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
2068 PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2069
2070#ifdef HDA_AS_PCI_EXPRESS
2071 /* PCI Express */
2072 PCIDevSetByte (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2073 PCIDevSetByte (&pThis->dev, 0x80 + 1, 0x60); /* next */
2074 /* Device flags */
2075 PCIDevSetWord (&pThis->dev, 0x80 + 2,
2076 /* version */ 0x1 |
2077 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2078 /* MSI */ (100) << 9
2079 );
2080 /* Device capabilities */
2081 PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2082 /* Device control */
2083 PCIDevSetWord (&pThis->dev, 0x80 + 8, 0);
2084 /* Device status */
2085 PCIDevSetWord (&pThis->dev, 0x80 + 10, 0);
2086 /* Link caps */
2087 PCIDevSetDWord (&pThis->dev, 0x80 + 12, 0);
2088 /* Link control */
2089 PCIDevSetWord (&pThis->dev, 0x80 + 16, 0);
2090 /* Link status */
2091 PCIDevSetWord (&pThis->dev, 0x80 + 18, 0);
2092 /* Slot capabilities */
2093 PCIDevSetDWord (&pThis->dev, 0x80 + 20, 0);
2094 /* Slot control */
2095 PCIDevSetWord (&pThis->dev, 0x80 + 24, 0);
2096 /* Slot status */
2097 PCIDevSetWord (&pThis->dev, 0x80 + 26, 0);
2098 /* Root control */
2099 PCIDevSetWord (&pThis->dev, 0x80 + 28, 0);
2100 /* Root capabilities */
2101 PCIDevSetWord (&pThis->dev, 0x80 + 30, 0);
2102 /* Root status */
2103 PCIDevSetDWord (&pThis->dev, 0x80 + 32, 0);
2104 /* Device capabilities 2 */
2105 PCIDevSetDWord (&pThis->dev, 0x80 + 36, 0);
2106 /* Device control 2 */
2107 PCIDevSetQWord (&pThis->dev, 0x80 + 40, 0);
2108 /* Link control 2 */
2109 PCIDevSetQWord (&pThis->dev, 0x80 + 48, 0);
2110 /* Slot control 2 */
2111 PCIDevSetWord (&pThis->dev, 0x80 + 56, 0);
2112#endif
2113
2114 /*
2115 * Register the PCI device.
2116 */
2117 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
2118 if (RT_FAILURE (rc))
2119 return rc;
2120
2121 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
2122 hdaMap);
2123 if (RT_FAILURE (rc))
2124 return rc;
2125
2126#ifdef VBOX_WITH_MSI_DEVICES
2127 PDMMSIREG aMsiReg;
2128
2129 RT_ZERO(aMsiReg);
2130 aMsiReg.cMsiVectors = 1;
2131 aMsiReg.iMsiCapOffset = 0x60;
2132 aMsiReg.iMsiNextOffset = 0x50;
2133 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
2134 if (RT_FAILURE (rc))
2135 {
2136 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2137 PCIDevSetCapabilityList (&pThis->dev, 0x50);
2138 }
2139#endif
2140
2141 rc = PDMDevHlpSSMRegister (pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2142 if (RT_FAILURE (rc))
2143 return rc;
2144
2145 /*
2146 * Attach driver.
2147 */
2148 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
2149 &s->pDrvBase, "Audio Driver Port");
2150 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2151 Log (("hda: No attached driver!\n"));
2152 else if (RT_FAILURE (rc))
2153 {
2154 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
2155 return rc;
2156 }
2157
2158
2159
2160 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
2161 rc = codecConstruct(pDevIns, &pThis->hda.Codec, /* ALC885_CODEC */ STAC9220_CODEC);
2162 if (RT_FAILURE(rc))
2163 AssertRCReturn(rc, rc);
2164
2165 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2166 verb F20 should provide device/codec recognition. */
2167 Assert(pThis->hda.Codec.u16VendorId);
2168 Assert(pThis->hda.Codec.u16DeviceId);
2169 PCIDevSetSubSystemVendorId (&pThis->dev, pThis->hda.Codec.u16VendorId); /* 2c ro - intel.) */
2170 PCIDevSetSubSystemId (&pThis->dev, pThis->hda.Codec.u16DeviceId); /* 2e ro. */
2171
2172 hdaReset (pDevIns);
2173 pThis->hda.Codec.id = 0;
2174 pThis->hda.Codec.pfnTransfer = hdaTransfer;
2175 pThis->hda.Codec.pfnReset = hdaCodecReset;
2176 /*
2177 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2178 * hdaReset shouldn't affects these registers.
2179 */
2180 WAKEEN(&pThis->hda) = 0x0;
2181 STATESTS(&pThis->hda) = 0x0;
2182
2183 return VINF_SUCCESS;
2184}
2185
2186/**
2187 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2188 */
2189static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
2190{
2191 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2192
2193 int rc = codecDestruct(&pThis->hda.Codec);
2194 AssertRC(rc);
2195 if (pThis->hda.pu32CorbBuf)
2196 RTMemFree(pThis->hda.pu32CorbBuf);
2197 if (pThis->hda.pu64RirbBuf)
2198 RTMemFree(pThis->hda.pu64RirbBuf);
2199 return VINF_SUCCESS;
2200}
2201
2202/**
2203 * The device registration structure.
2204 */
2205const PDMDEVREG g_DeviceICH6_HDA =
2206{
2207 /* u32Version */
2208 PDM_DEVREG_VERSION,
2209 /* szName */
2210 "hda",
2211 /* szRCMod */
2212 "",
2213 /* szR0Mod */
2214 "",
2215 /* pszDescription */
2216 "ICH IntelHD Audio Controller",
2217 /* fFlags */
2218 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2219 /* fClass */
2220 PDM_DEVREG_CLASS_AUDIO,
2221 /* cMaxInstances */
2222 1,
2223 /* cbInstance */
2224 sizeof(PCIINTELHDLinkState),
2225 /* pfnConstruct */
2226 hdaConstruct,
2227 /* pfnDestruct */
2228 hdaDestruct,
2229 /* pfnRelocate */
2230 NULL,
2231 /* pfnIOCtl */
2232 NULL,
2233 /* pfnPowerOn */
2234 NULL,
2235 /* pfnReset */
2236 hdaReset,
2237 /* pfnSuspend */
2238 NULL,
2239 /* pfnResume */
2240 NULL,
2241 /* pfnAttach */
2242 NULL,
2243 /* pfnDetach */
2244 NULL,
2245 /* pfnQueryInterface. */
2246 NULL,
2247 /* pfnInitComplete */
2248 NULL,
2249 /* pfnPowerOff */
2250 NULL,
2251 /* pfnSoftReset */
2252 NULL,
2253 /* u32VersionEnd */
2254 PDM_DEVREG_VERSION
2255};
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