VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 36864

Last change on this file since 36864 was 36691, checked in by vboxsync, 14 years ago

HDA/Audio: Some clean up. Codecs macro definitions splited from implementation.

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1/* $Id: DevIchIntelHDA.cpp 36691 2011-04-18 03:03:15Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/vmm/pdmdev.h>
23#include <iprt/assert.h>
24#include <iprt/uuid.h>
25#include <iprt/string.h>
26#include <iprt/mem.h>
27#include <iprt/asm.h>
28#include <iprt/asm-math.h>
29
30#include "VBoxDD.h"
31
32extern "C" {
33#include "audio.h"
34}
35#include "DevCodec.h"
36
37#define VBOX_WITH_INTEL_HDA
38
39#if defined(VBOX_WITH_HP_HDA)
40/* HP Pavilion dv4t-1300 */
41# define HDA_PCI_VENDOR_ID 0x103c
42# define HDA_PCI_DEICE_ID 0x30f7
43#elif defined(VBOX_WITH_INTEL_HDA)
44/* Intel HDA controller */
45# define HDA_PCI_VENDOR_ID 0x8086
46# define HDA_PCI_DEICE_ID 0x2668
47#elif defined(VBOX_WITH_NVIDIA_HDA)
48/* nVidia HDA controller */
49# define HDA_PCI_VENDOR_ID 0x10de
50# define HDA_PCI_DEICE_ID 0x0ac0
51#else
52# error "Please specify your HDA device vendor/device IDs"
53#endif
54
55#define HDA_SSM_VERSION 1
56PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
57PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
58static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
59
60#define HDA_NREGS 112
61/* Registers */
62#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
63#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
64#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
65#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
66#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
67#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
68#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
69#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
70#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
71#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
72
73#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
74#define GCAP(pState) (HDA_REG((pState), GCAP))
75/* GCAP HDASpec 3.3.2 This macro compact following information about HDA
76 * oss (15:12) - number of output streams supported
77 * iss (11:8) - number of input streams supported
78 * bss (7:3) - number of bidirection streams suppoted
79 * bds (2:1) - number of serial data out signals supported
80 * b64sup (0) - 64 bit addressing supported.
81 */
82#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
83 ( (((oss) & 0xF) << 12) \
84 | (((iss) & 0xF) << 8) \
85 | (((bss) & 0x1F) << 3) \
86 | (((bds) & 0x3) << 2) \
87 | ((b64sup) & 1))
88#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
89#define VMIN(pState) (HDA_REG((pState), VMIN))
90
91#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
92#define VMAJ(pState) (HDA_REG((pState), VMAJ))
93
94#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
95#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
96
97#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
98#define INPAY(pState) (HDA_REG((pState), INPAY))
99
100#define ICH6_HDA_REG_GCTL (5)
101#define ICH6_HDA_GCTL_RST_SHIFT (0)
102#define ICH6_HDA_GCTL_FSH_SHIFT (1)
103#define ICH6_HDA_GCTL_UR_SHIFT (8)
104#define GCTL(pState) (HDA_REG((pState), GCTL))
105
106#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
107#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
108
109#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
110#define STATESTS(pState) (HDA_REG((pState), STATESTS))
111#define ICH6_HDA_STATES_SCSF 0x7
112
113#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
114#define ICH6_HDA_GSTS_FSH_SHIFT (1)
115#define GSTS(pState) (HDA_REG(pState, GSTS))
116
117#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
118#define ICH6_HDA_INTCTL_GIE_SHIFT 31
119#define ICH6_HDA_INTCTL_CIE_SHIFT 30
120#define ICH6_HDA_INTCTL_S0_SHIFT (0)
121#define ICH6_HDA_INTCTL_S1_SHIFT (1)
122#define ICH6_HDA_INTCTL_S2_SHIFT (2)
123#define ICH6_HDA_INTCTL_S3_SHIFT (3)
124#define ICH6_HDA_INTCTL_S4_SHIFT (4)
125#define ICH6_HDA_INTCTL_S5_SHIFT (5)
126#define ICH6_HDA_INTCTL_S6_SHIFT (6)
127#define ICH6_HDA_INTCTL_S7_SHIFT (7)
128#define INTCTL(pState) (HDA_REG((pState), INTCTL))
129#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
130#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
131#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
132#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
133
134/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
135 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
136 * the datasheet.
137 */
138#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
139#define SSYNC(pState) (HDA_REG((pState), SSYNC))
140
141#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
142#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
143#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
144#define ICH6_HDA_INTSTS_S0_SHIFT (0)
145#define ICH6_HDA_INTSTS_S1_SHIFT (1)
146#define ICH6_HDA_INTSTS_S2_SHIFT (2)
147#define ICH6_HDA_INTSTS_S3_SHIFT (3)
148#define ICH6_HDA_INTSTS_S4_SHIFT (4)
149#define ICH6_HDA_INTSTS_S5_SHIFT (5)
150#define ICH6_HDA_INTSTS_S6_SHIFT (6)
151#define ICH6_HDA_INTSTS_S7_SHIFT (7)
152#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
153#define INTSTS(pState) (HDA_REG((pState), INTSTS))
154#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
155#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
156#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
157#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
158
159#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
160#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
161#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
162#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
163#define ICH6_HDA_REG_CORBWP 15 /* 48 */
164#define ICH6_HDA_REG_CORBRP 16 /* 4A */
165#define ICH6_HDA_CORBRP_RST_SHIFT 15
166#define ICH6_HDA_CORBRP_WP_SHIFT 0
167#define ICH6_HDA_CORBRP_WP_MASK 0xFF
168
169#define CORBRP(pState) (HDA_REG(pState, CORBRP))
170#define CORBWP(pState) (HDA_REG(pState, CORBWP))
171
172#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
173#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
174#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
175
176#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
177
178
179#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
180#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
181#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
182
183#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
184#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
185#define ICH6_HDA_CORBSIZE_SZ 0x3
186#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
187#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
188/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
189
190#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
191#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
192
193#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
194#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
195
196#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
197#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
198#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
199#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
200
201#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
202#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
203#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
204
205#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
206#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
207#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
208#define ICH6_HDA_ROI_DMA_SHIFT (2)
209#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
210#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
211#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
212#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
213
214#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
215#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
216#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
217#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
218#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
219#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
220
221#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
222#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
223#define ICH6_HDA_RIRBSIZE_SZ 0x3
224
225#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
226#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
227
228
229#define ICH6_HDA_REG_IC 27 /* 0x60 */
230#define IC(pState) (HDA_REG(pState, IC))
231#define ICH6_HDA_REG_IR 28 /* 0x64 */
232#define IR(pState) (HDA_REG(pState, IR))
233#define ICH6_HDA_REG_IRS 29 /* 0x68 */
234#define ICH6_HDA_IRS_ICB_SHIFT (0)
235#define ICH6_HDA_IRS_IRV_SHIFT (1)
236#define IRS(pState) (HDA_REG(pState, IRS))
237#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
238#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
239
240#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
241#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
242#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
243#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
244#define DPBASE_ENABLED 1
245#define DPBASE_ADDR_MASK (~0x7f)
246
247#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
248#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
249/* Note: sdnum here _MUST_ be stream reg number [0,7] */
250#define HDA_STREAM_REG2(pState, name, sdnum) (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
251
252#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
253#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
254#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
255#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
256#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
257#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
258#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
259#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
260
261#define SD(func, num) SD##num##func
262#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
263#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
264#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
265#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
266#define ICH6_HDA_SDCTL_DIR_SHIFT (19)
267#define ICH6_HDA_SDCTL_TP_SHIFT (18)
268#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)
269#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)
270#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
271#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
272#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
273#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
274#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
275
276#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
277#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
278#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
279#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
280#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
281#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
282#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
283#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
284
285#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
286#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
287#define ICH6_HDA_SDSTS_DE_SHIFT (4)
288#define ICH6_HDA_SDSTS_FE_SHIFT (3)
289#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
290
291#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
292#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
293#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
294#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
295#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
296#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
297#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
298#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
299
300#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
301
302#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
303#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
304#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
305#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
306#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
307#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
308#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
309#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
310
311#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
312
313#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
314#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
315#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
316#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
317#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
318#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
319#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
320#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
321
322#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
323
324#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
325#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
326#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
327#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
328#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
329#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
330#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
331#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
332
333/*
334 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
335 */
336#define HDA_SDFIFOW_8B (0x2)
337#define HDA_SDFIFOW_16B (0x3)
338#define HDA_SDFIFOW_32B (0x4)
339#define SDFIFOW(pState, num) HDA_REG((pState), SD(FIFOW, num))
340
341#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
342#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
343#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
344#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
345#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
346#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
347#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
348#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
349
350/*
351 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
352 * formula: size - 1
353 * Other values not listed are not supported.
354 */
355#define HDA_SDONFIFO_16B (0xF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
356#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
357#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
358#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
359#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
360#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
361#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
362#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
363#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
364
365#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
366#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
367#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
368#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
369#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
370#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
371#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
372#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
373
374#define SDFMT(pState, num) (HDA_REG((pState), SD(FMT, num)))
375#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
376#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
377#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
378#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
379#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
380#define ICH6_HDA_SDFMT_BITS_SHIFT (4)
381#define ICH6_HDA_SDFMT_BITS_MASK (0x7)
382#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
383#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
384#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
385
386#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
387#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
388#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
389#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
390#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
391#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
392#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
393#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
394
395#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
396
397#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
398#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
399#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
400#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
401#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
402#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
403#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
404#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
405
406#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
407
408/* Predicates */
409
410typedef struct HDABDLEDESC
411{
412 uint64_t u64BdleCviAddr;
413 uint32_t u32BdleMaxCvi;
414 uint32_t u32BdleCvi;
415 uint32_t u32BdleCviLen;
416 uint32_t u32BdleCviPos;
417 bool fBdleCviIoc;
418 uint32_t cbUnderFifoW;
419 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
420} HDABDLEDESC, *PHDABDLEDESC;
421
422typedef struct HDASTREAMTRANSFERDESC
423{
424 uint64_t u64BaseDMA;
425 uint32_t u32Ctl;
426 uint32_t *pu32Sts;
427 uint8_t u8Strm;
428 uint32_t *pu32Lpib;
429 uint32_t u32Cbl;
430 uint32_t u32Fifos;
431} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
432
433typedef struct INTELHDLinkState
434{
435 /** Pointer to the device instance. */
436 PPDMDEVINSR3 pDevIns;
437 /** Pointer to the connector of the attached audio driver. */
438 PPDMIAUDIOCONNECTOR pDrv;
439 /** Pointer to the attached audio driver. */
440 PPDMIBASE pDrvBase;
441 /** The base interface for LUN\#0. */
442 PDMIBASE IBase;
443 RTGCPHYS addrMMReg;
444 uint32_t au32Regs[HDA_NREGS];
445 HDABDLEDESC stInBdle;
446 HDABDLEDESC stOutBdle;
447 HDABDLEDESC stMicBdle;
448 /* Interrupt on completion */
449 bool fCviIoc;
450 uint64_t u64CORBBase;
451 uint64_t u64RIRBBase;
452 uint64_t u64DPBase;
453 /* pointer on CORB buf */
454 uint32_t *pu32CorbBuf;
455 /* size in bytes of CORB buf */
456 uint32_t cbCorbBuf;
457 /* pointer on RIRB buf */
458 uint64_t *pu64RirbBuf;
459 /* size in bytes of RIRB buf */
460 uint32_t cbRirbBuf;
461 /* indicates if HDA in reset. */
462 bool fInReset;
463 CODECState Codec;
464 uint8_t u8Counter;
465 uint64_t u64BaseTS;
466} INTELHDLinkState, *PINTELHDLinkState;
467
468#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
469#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
470
471#define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In, \
472 SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
473#define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out, \
474 SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
475
476
477
478
479typedef struct PCIINTELHDLinkState
480{
481 PCIDevice dev;
482 INTELHDLinkState hda;
483} PCIINTELHDLinkState;
484
485
486DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
487DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
488DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
489DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
490DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
491DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
492DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
493DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
494DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
495DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
496DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
497DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
498DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
499DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
500DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
501DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
502DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
503DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
504DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
505DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
506
507DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
508DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
509DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
510DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
511DECLCALLBACK(int)hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
512DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
513DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
514DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
515DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
516DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
517DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
518DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
519DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
520DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
521DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
522DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
523
524static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc);
525static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
526static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
527#ifdef LOG_ENABLED
528static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
529#endif
530
531
532/* see 302349 p 6.2*/
533const static struct stIchIntelHDRegMap
534{
535 /** Register offset in the register space. */
536 uint32_t offset;
537 /** Size in bytes. Registers of size > 4 are in fact tables. */
538 uint32_t size;
539 /** Readable bits. */
540 uint32_t readable;
541 /** Writable bits. */
542 uint32_t writable;
543 /** Read callback. */
544 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
545 /** Write callback. */
546 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
547 /** Abbreviated name. */
548 const char *abbrev;
549 /** Full name. */
550 const char *name;
551} s_ichIntelHDRegMap[HDA_NREGS] =
552{
553 /* offset size read mask write mask read callback write callback abbrev full name */
554 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
555 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
556 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
557 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
558 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
559 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
560 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
561 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
562 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
563 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
564 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
565 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
566 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
567 //** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
568 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
569 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
570 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
571 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
572 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
573 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
574 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
575 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
576 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
577 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
578 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
579 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
580 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
581 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
582 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
583 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
584 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
585 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
586 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
587 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
588
589 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
590 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
591 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
592 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
593 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
594 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
595 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
596 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
597 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
598 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
599
600 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
601 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
602 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
603 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
604 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
605 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
606 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
607 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
608 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
609 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
610
611 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
612 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
613 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
614 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
615 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
616 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
617 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
618 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
619 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
620 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
621
622 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
623 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
624 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
625 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
626 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
627 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
628 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
629 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
630 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
631 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
632
633 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
634 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
635 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
636 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
637 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
638 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
639 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
640 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
641 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
642 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
643
644 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
645 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
646 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
647 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
648 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
649 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
650 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
651 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
652 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
653 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
654
655 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
656 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
657 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
658 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
659 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
660 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
661 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
662 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
663 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
664 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
665
666 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
667 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
668 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
669 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
670 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
671 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
672 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
673 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
674 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
675 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
676};
677
678static void inline hdaUpdatePosBuf(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
679{
680 if (pState->u64DPBase & DPBASE_ENABLED)
681 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
682 (pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
683}
684static uint32_t inline hdaFifoWToSz(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
685{
686#if 0
687 switch(HDA_STREAM_REG2(pState, FIFOW, pStreamDesc->u8Strm))
688 {
689 case HDA_SDFIFOW_8B: return 8;
690 case HDA_SDFIFOW_16B: return 16;
691 case HDA_SDFIFOW_32B: return 32;
692 default:
693 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
694 }
695#endif
696 return 0;
697}
698
699static int hdaProcessInterrupt(INTELHDLinkState* pState)
700{
701#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
702 ( INTCTL_SX((pState), num) \
703 && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
704 bool fIrq = false;
705 if ( INTCTL_CIE(pState)
706 && ( RIRBSTS_RINTFL(pState)
707 || RIRBSTS_RIRBOIS(pState)
708 || (STATESTS(pState) & WAKEEN(pState))))
709 fIrq = true;
710
711 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
712 || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
713 fIrq = true;
714
715 if (INTCTL_GIE(pState))
716 {
717 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
718 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
719 }
720 return VINF_SUCCESS;
721}
722
723static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
724{
725 int index = 0;
726 //** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
727 for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
728 {
729 if ( u32Offset >= s_ichIntelHDRegMap[index].offset
730 && u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
731 {
732 return index;
733 }
734 }
735 /* Aliases HDA spec 3.3.45 */
736 switch(u32Offset)
737 {
738 case 0x2084:
739 return HDA_REG_IND_NAME(SD0LPIB);
740 case 0x20A4:
741 return HDA_REG_IND_NAME(SD1LPIB);
742 case 0x20C4:
743 return HDA_REG_IND_NAME(SD2LPIB);
744 case 0x20E4:
745 return HDA_REG_IND_NAME(SD3LPIB);
746 case 0x2104:
747 return HDA_REG_IND_NAME(SD4LPIB);
748 case 0x2124:
749 return HDA_REG_IND_NAME(SD5LPIB);
750 case 0x2144:
751 return HDA_REG_IND_NAME(SD6LPIB);
752 case 0x2164:
753 return HDA_REG_IND_NAME(SD7LPIB);
754 }
755 return -1;
756}
757
758static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
759{
760 int rc = VINF_SUCCESS;
761 if (fLocal)
762 {
763 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
764 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
765 if (RT_FAILURE(rc))
766 AssertRCReturn(rc, rc);
767#ifdef DEBUG_CMD_BUFFER
768 uint8_t i = 0;
769 do
770 {
771 Log(("hda: corb%02x: ", i));
772 uint8_t j = 0;
773 do
774 {
775 const char *prefix;
776 if ((i + j) == CORBRP(pState))
777 prefix = "[R]";
778 else if ((i + j) == CORBWP(pState))
779 prefix = "[W]";
780 else
781 prefix = " "; /* three spaces */
782 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
783 j++;
784 } while (j < 8);
785 Log(("\n"));
786 i += 8;
787 } while(i != 0);
788#endif
789 }
790 else
791 {
792 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
793 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
794 if (RT_FAILURE(rc))
795 AssertRCReturn(rc, rc);
796#ifdef DEBUG_CMD_BUFFER
797 uint8_t i = 0;
798 do {
799 Log(("hda: rirb%02x: ", i));
800 uint8_t j = 0;
801 do {
802 const char *prefix;
803 if ((i + j) == RIRBWP(pState))
804 prefix = "[W]";
805 else
806 prefix = " ";
807 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
808 } while (++j < 8);
809 Log(("\n"));
810 i += 8;
811 } while (i != 0);
812#endif
813 }
814 return rc;
815}
816
817static int hdaCORBCmdProcess(INTELHDLinkState *pState)
818{
819 int rc;
820 uint8_t corbRp;
821 uint8_t corbWp;
822 uint8_t rirbWp;
823
824 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
825
826 rc = hdaCmdSync(pState, true);
827 if (RT_FAILURE(rc))
828 AssertRCReturn(rc, rc);
829 corbRp = CORBRP(pState);
830 corbWp = CORBWP(pState);
831 rirbWp = RIRBWP(pState);
832 Assert((corbWp != corbRp));
833 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
834 while (corbRp != corbWp)
835 {
836 uint32_t cmd;
837 uint64_t resp;
838 corbRp++;
839 cmd = pState->pu32CorbBuf[corbRp];
840 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
841 if (RT_FAILURE(rc))
842 AssertRCReturn(rc, rc);
843 Assert(pfn);
844 (rirbWp)++;
845 rc = pfn(&pState->Codec, cmd, &resp);
846 if (RT_FAILURE(rc))
847 AssertRCReturn(rc, rc);
848 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
849 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
850 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
851 {
852 Log(("hda: unexpected unsolicited response.\n"));
853 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
854 return rc;
855 }
856 pState->pu64RirbBuf[rirbWp] = resp;
857 pState->u8Counter++;
858 if (pState->u8Counter == RINTCNT_N(pState))
859 break;
860 }
861 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
862 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
863 rc = hdaCmdSync(pState, false);
864 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
865 if (RIRBCTL_RIRB_RIC(pState))
866 {
867 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
868 pState->u8Counter = 0;
869 rc = hdaProcessInterrupt(pState);
870 }
871 if (RT_FAILURE(rc))
872 AssertRCReturn(rc, rc);
873 return rc;
874}
875
876static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
877{
878 Log(("hda: reset of stream (%d) started\n", u8Strm));
879 Assert(( pState
880 && pBdle
881 && pStreamDesc
882 && u8Strm <= 7));
883 memset(pBdle, 0, sizeof(HDABDLEDESC));
884 *pStreamDesc->pu32Lpib = 0;
885 *pStreamDesc->pu32Sts = 0;
886 /* According to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
887 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
888 HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
889
890 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
891 HDA_STREAM_REG2(pState, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
892 HDA_STREAM_REG2(pState, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
893 HDA_STREAM_REG2(pState, CBL, u8Strm) = 0;
894 HDA_STREAM_REG2(pState, LVI, u8Strm) = 0;
895 HDA_STREAM_REG2(pState, FMT, u8Strm) = 0;
896 HDA_STREAM_REG2(pState, BDPU, u8Strm) = 0;
897 HDA_STREAM_REG2(pState, BDPL, u8Strm) = 0;
898 Log(("hda: reset of stream (%d) finished\n", u8Strm));
899}
900
901
902DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
903{
904 *pu32Value = 0;
905 return VINF_SUCCESS;
906}
907DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
908{
909 return VINF_SUCCESS;
910}
911/* U8 */
912DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
913{
914 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
915 return hdaRegReadU32(pState, offset, index, pu32Value);
916}
917
918DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
919{
920 Assert(((u32Value & 0xffffff00) == 0));
921 return hdaRegWriteU32(pState, offset, index, u32Value);
922}
923/* U16 */
924DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
925{
926 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
927 return hdaRegReadU32(pState, offset, index, pu32Value);
928}
929
930DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
931{
932 Assert(((u32Value & 0xffff0000) == 0));
933 return hdaRegWriteU32(pState, offset, index, u32Value);
934}
935
936/* U24 */
937DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
938{
939 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
940 return hdaRegReadU32(pState, offset, index, pu32Value);
941}
942
943DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
944{
945 Assert(((u32Value & 0xff000000) == 0));
946 return hdaRegWriteU32(pState, offset, index, u32Value);
947}
948/* U32 */
949DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
950{
951 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
952 return VINF_SUCCESS;
953}
954
955DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
956{
957 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
958 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
959 return VINF_SUCCESS;
960}
961
962DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
963{
964 return hdaRegReadU32(pState, offset, index, pu32Value);
965}
966
967DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
968{
969 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
970 {
971 /* exit reset state */
972 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
973 pState->fInReset = false;
974 }
975 else
976 {
977 /* enter reset state*/
978 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
979 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
980 {
981 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
982 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
983 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
984 }
985 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
986 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
987 pState->fInReset = true;
988 }
989 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
990 {
991 /* Flush: GSTS:1 set, see 6.2.6*/
992 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
993 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
994 }
995 return VINF_SUCCESS;
996}
997
998DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
999{
1000 uint32_t v = pState->au32Regs[index];
1001 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
1002 pState->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
1003 return VINF_SUCCESS;
1004}
1005
1006DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1007{
1008 uint32_t v = 0;
1009 if ( RIRBSTS_RIRBOIS(pState)
1010 || RIRBSTS_RINTFL(pState)
1011 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
1012 || STATESTS(pState))
1013 v |= RT_BIT(30);
1014#define HDA_IS_STREAM_EVENT(pState, stream) \
1015 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1016 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1017 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1018#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
1019 MARK_STREAM(pState, 0, v);
1020 MARK_STREAM(pState, 1, v);
1021 MARK_STREAM(pState, 2, v);
1022 MARK_STREAM(pState, 3, v);
1023 MARK_STREAM(pState, 4, v);
1024 MARK_STREAM(pState, 5, v);
1025 MARK_STREAM(pState, 6, v);
1026 MARK_STREAM(pState, 7, v);
1027 v |= v ? RT_BIT(31) : 0;
1028 *pu32Value = v;
1029 return VINF_SUCCESS;
1030}
1031
1032DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1033{
1034 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1035 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pState)) - pState->u64BaseTS, 24, 1000);
1036 return VINF_SUCCESS;
1037}
1038
1039DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1040{
1041 return hdaRegReadU16(pState, offset, index, pu32Value);
1042}
1043
1044DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1045{
1046 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1047 CORBRP(pState) = 0;
1048 else
1049 return hdaRegWriteU8(pState, offset, index, u32Value);
1050 return VINF_SUCCESS;
1051}
1052
1053DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1054{
1055 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
1056 AssertRC(rc);
1057 if ( CORBWP(pState) != CORBRP(pState)
1058 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
1059 return hdaCORBCmdProcess(pState);
1060 return rc;
1061}
1062
1063DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1064{
1065 uint32_t v = CORBSTS(pState);
1066 CORBSTS(pState) &= ~(v & u32Value);
1067 return VINF_SUCCESS;
1068}
1069
1070DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1071{
1072 int rc;
1073 rc = hdaRegWriteU16(pState, offset, index, u32Value);
1074 if (RT_FAILURE(rc))
1075 AssertRCReturn(rc, rc);
1076 if (CORBWP(pState) == CORBRP(pState))
1077 return VINF_SUCCESS;
1078 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1079 return VINF_SUCCESS;
1080 rc = hdaCORBCmdProcess(pState);
1081 return rc;
1082}
1083
1084DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1085{
1086 return hdaRegReadU24(pState, offset, index, pu32Value);
1087}
1088
1089DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1090{
1091 bool fRun = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1092 bool fInRun = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1093 bool fReset = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1094 bool fInReset = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1095 int rc = VINF_SUCCESS;
1096 if (fInReset)
1097 {
1098 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1099 * from reset
1100 */
1101 Assert((!fReset));
1102 Log(("hda: guest initiate exit of stream reset.\n"));
1103 goto done;
1104 }
1105 else if (fReset)
1106 {
1107 /*
1108 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1109 */
1110 uint8_t u8Strm = 0;
1111 PHDABDLEDESC pBdle = NULL;
1112 HDASTREAMTRANSFERDESC stStreamDesc;
1113 Assert((!fInRun && !fRun));
1114 switch (index)
1115 {
1116 case ICH6_HDA_REG_SD0CTL:
1117 u8Strm = 0;
1118 pBdle = &pState->stInBdle;
1119 break;
1120 case ICH6_HDA_REG_SD4CTL:
1121 u8Strm = 4;
1122 pBdle = &pState->stOutBdle;
1123 break;
1124 default:
1125 Log(("hda: changing SRST bit on non-attached stream\n"));
1126 goto done;
1127 }
1128 Log(("hda: guest initiate enter to stream reset.\n"));
1129 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1130 hdaStreamReset(pState, pBdle, &stStreamDesc, u8Strm);
1131 goto done;
1132 }
1133
1134 /* we enter here to change DMA states only */
1135 if ( (fInRun && !fRun)
1136 || (fRun && !fInRun))
1137 {
1138 Assert((!fReset && !fInReset));
1139 switch (index)
1140 {
1141 case ICH6_HDA_REG_SD0CTL:
1142 AUD_set_active_in(pState->Codec.SwVoiceIn, fRun);
1143 break;
1144 case ICH6_HDA_REG_SD4CTL:
1145 AUD_set_active_out(pState->Codec.SwVoiceOut, fRun);
1146 break;
1147 default:
1148 Log(("hda: changing RUN bit on non-attached stream\n"));
1149 goto done;
1150 }
1151 }
1152
1153 done:
1154 rc = hdaRegWriteU24(pState, offset, index, u32Value);
1155 if (RT_FAILURE(rc))
1156 AssertRCReturn(rc, VINF_SUCCESS);
1157 return rc;
1158}
1159
1160DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1161{
1162 uint32_t v = HDA_REG_IND(pState, index);
1163 v &= ~(u32Value & v);
1164 HDA_REG_IND(pState, index) = v;
1165 hdaProcessInterrupt(pState);
1166 return VINF_SUCCESS;
1167}
1168
1169DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1170{
1171 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1172 if (RT_FAILURE(rc))
1173 AssertRCReturn(rc, VINF_SUCCESS);
1174 return rc;
1175}
1176
1177DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1178{
1179 switch (u32Value)
1180 {
1181 case HDA_SDFIFOW_8B:
1182 case HDA_SDFIFOW_16B:
1183 case HDA_SDFIFOW_32B:
1184 return hdaRegWriteU16(pState, offset, index, u32Value);
1185 default:
1186 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1187 return hdaRegWriteU16(pState, offset, index, HDA_SDFIFOW_32B);
1188 }
1189 return VINF_SUCCESS;
1190}
1191/*
1192 * Note this method could be called for changing value on Output Streams only (ICH6 datacheet 18.2.39)
1193 *
1194 */
1195DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1196{
1197 switch (index)
1198 {
1199 /* SDInFIFOS is RO, n=0-3 */
1200 case ICH6_HDA_REG_SD0FIFOS:
1201 case ICH6_HDA_REG_SD1FIFOS:
1202 case ICH6_HDA_REG_SD2FIFOS:
1203 case ICH6_HDA_REG_SD3FIFOS:
1204 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1205 return VINF_SUCCESS;
1206 case ICH6_HDA_REG_SD4FIFOS:
1207 case ICH6_HDA_REG_SD5FIFOS:
1208 case ICH6_HDA_REG_SD6FIFOS:
1209 case ICH6_HDA_REG_SD7FIFOS:
1210 switch(u32Value)
1211 {
1212 case HDA_SDONFIFO_16B:
1213 case HDA_SDONFIFO_32B:
1214 case HDA_SDONFIFO_64B:
1215 case HDA_SDONFIFO_128B:
1216 case HDA_SDONFIFO_192B:
1217 return hdaRegWriteU16(pState, offset, index, u32Value);
1218
1219 case HDA_SDONFIFO_256B:
1220 Log(("hda: 256 bit is unsupported, HDA is switched into 192B mode\n"));
1221 default:
1222 return hdaRegWriteU16(pState, offset, index, HDA_SDONFIFO_192B);
1223 }
1224 return VINF_SUCCESS;
1225 default:
1226 AssertMsgFailed(("Something wierd happens with register lookup routine"));
1227 }
1228 return VINF_SUCCESS;
1229}
1230
1231static void inline hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1232{
1233 Assert((pAudSetting));
1234#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1235 uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1236 uint32_t u32HzMult = 1;
1237 uint32_t u32HzDiv = 1;
1238 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))
1239 {
1240 case 0: u32HzMult = 1; break;
1241 case 1: u32HzMult = 2; break;
1242 case 2: u32HzMult = 3; break;
1243 case 3: u32HzMult = 4; break;
1244 default:
1245 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1246 }
1247 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))
1248 {
1249 case 0: u32HzDiv = 1; break;
1250 case 1: u32HzDiv = 2; break;
1251 case 2: u32HzDiv = 3; break;
1252 case 3: u32HzDiv = 4; break;
1253 case 4: u32HzDiv = 5; break;
1254 case 5: u32HzDiv = 6; break;
1255 case 6: u32HzDiv = 7; break;
1256 case 7: u32HzDiv = 8; break;
1257 }
1258 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1259
1260 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_BITS_MASK, ICH6_HDA_SDFMT_BITS_SHIFT))
1261 {
1262 case 0:
1263 Log(("hda: %s requested 8 bit\n", __FUNCTION__));
1264 pAudSetting->fmt = AUD_FMT_S8;
1265 break;
1266 case 1:
1267 Log(("hda: %s requested 16 bit\n", __FUNCTION__));
1268 pAudSetting->fmt = AUD_FMT_S16;
1269 break;
1270 case 2:
1271 Log(("hda: %s requested 20 bit\n", __FUNCTION__));
1272 break;
1273 case 3:
1274 Log(("hda: %s requested 24 bit\n", __FUNCTION__));
1275 break;
1276 case 4:
1277 Log(("hda: %s requested 32 bit\n", __FUNCTION__));
1278 pAudSetting->fmt = AUD_FMT_S32;
1279 break;
1280 default:
1281 AssertMsgFailed(("Unsupported"));
1282 }
1283 pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;
1284 pAudSetting->fmt = AUD_FMT_S16;
1285 pAudSetting->endianness = 0;
1286#undef EXTRACT_VALUE
1287}
1288
1289DECLCALLBACK(int)hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1290{
1291#ifdef VBOX_WITH_HDA_CODEC_EMU
1292 /* @todo here some more investigations are required. */
1293 int rc = 0;
1294 audsettings_t as;
1295 /* no reason to reopen voice with same settings */
1296 if (u32Value == HDA_REG_IND(pState, index))
1297 return VINF_SUCCESS;
1298 hdaSdFmtToAudSettings(u32Value, &as);
1299 switch (index)
1300 {
1301 case ICH6_HDA_REG_SD0FMT:
1302 rc = codecOpenVoice(&pState->Codec, PI_INDEX, &as);
1303 break;
1304 case ICH6_HDA_REG_SD4FMT:
1305 rc = codecOpenVoice(&pState->Codec, PO_INDEX, &as);
1306 break;
1307 default:
1308 Log(("HDA: attempt to change format on %d\n", index));
1309 rc = 0;
1310 }
1311 return hdaRegWriteU16(pState, offset, index, u32Value);
1312#else
1313 return hdaRegWriteU16(pState, offset, index, u32Value);
1314#endif
1315}
1316
1317DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1318{
1319 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1320 if (RT_FAILURE(rc))
1321 AssertRCReturn(rc, VINF_SUCCESS);
1322 return rc;
1323}
1324
1325DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1326{
1327 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1328 if (RT_FAILURE(rc))
1329 AssertRCReturn(rc, VINF_SUCCESS);
1330 return rc;
1331}
1332
1333DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1334{
1335 int rc = VINF_SUCCESS;
1336 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1337 if ( CORBWP(pState) != CORBRP(pState)
1338 || HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1339 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1340
1341 rc = hdaRegReadU32(pState, offset, index, pu32Value);
1342 return rc;
1343}
1344
1345DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1346{
1347 int rc = VINF_SUCCESS;
1348 uint64_t resp;
1349 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1350 /*
1351 * if guest set ICB bit of IRS register HDA should process verb in IC register and
1352 * writes response in IR register and set IRV (valid in case of success) bit of IRS register.
1353 */
1354 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1355 && !IRS_ICB(pState))
1356 {
1357 uint32_t cmd = IC(pState);
1358 if (CORBWP(pState) != CORBRP(pState))
1359 {
1360 /*
1361 * 3.4.3 defines behaviour of immediate Command status register.
1362 */
1363 LogRel(("hda: guest has tried process immediate verb (%x) with active CORB\n", cmd));
1364 return rc;
1365 }
1366 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1367 Log(("hda: IC:%x\n", cmd));
1368 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1369 if (RT_FAILURE(rc))
1370 AssertRCReturn(rc, rc);
1371 rc = pfn(&pState->Codec, cmd, &resp);
1372 if (RT_FAILURE(rc))
1373 AssertRCReturn(rc, rc);
1374 IR(pState) = (uint32_t)resp;
1375 Log(("hda: IR:%x\n", IR(pState)));
1376 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1377 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1378 return rc;
1379 }
1380 /*
1381 * when guest's read the response it should clean the IRV bit of the IRS register.
1382 */
1383 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1384 && IRS_IRV(pState))
1385 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1386 return rc;
1387}
1388
1389DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1390{
1391 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1392 {
1393 RIRBWP(pState) = 0;
1394 }
1395 /*The rest of bits are O, see 6.2.22 */
1396 return VINF_SUCCESS;
1397}
1398
1399DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1400{
1401 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1402 if (RT_FAILURE(rc))
1403 AssertRCReturn(rc, rc);
1404 switch(index)
1405 {
1406 case ICH6_HDA_REG_CORBLBASE:
1407 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1408 pState->u64CORBBase |= pState->au32Regs[index];
1409 break;
1410 case ICH6_HDA_REG_CORBUBASE:
1411 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1412 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1413 break;
1414 case ICH6_HDA_REG_RIRLBASE:
1415 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1416 pState->u64RIRBBase |= pState->au32Regs[index];
1417 break;
1418 case ICH6_HDA_REG_RIRUBASE:
1419 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1420 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1421 break;
1422 case ICH6_HDA_REG_DPLBASE:
1423 /* @todo: first bit has special meaning */
1424 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1425 pState->u64DPBase |= pState->au32Regs[index];
1426 break;
1427 case ICH6_HDA_REG_DPUBASE:
1428 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1429 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1430 break;
1431 default:
1432 AssertMsgFailed(("Invalid index"));
1433 }
1434 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1435 return rc;
1436}
1437
1438DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1439{
1440 uint8_t v = RIRBSTS(pState);
1441 RIRBSTS(pState) &= ~(v & u32Value);
1442
1443 return hdaProcessInterrupt(pState);
1444}
1445
1446#ifdef LOG_ENABLED
1447static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1448{
1449#if 0
1450 uint64_t addr;
1451 uint32_t len;
1452 uint32_t ioc;
1453 uint8_t bdle[16];
1454 uint32_t counter;
1455 uint32_t i;
1456 uint32_t sum = 0;
1457 Assert(pBdle && pBdle->u32BdleMaxCvi);
1458 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1459 {
1460 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1461 addr = *(uint64_t *)bdle;
1462 len = *(uint32_t *)&bdle[8];
1463 ioc = *(uint32_t *)&bdle[12];
1464 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1465 sum += len;
1466 }
1467 Log(("hda: sum: %d\n", sum));
1468 for (i = 0; i < 8; ++i)
1469 {
1470 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1471 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
1472 i , counter));
1473 }
1474#endif
1475}
1476#endif
1477
1478static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1479{
1480 uint8_t bdle[16];
1481 Assert(( pStreamDesc->u64BaseDMA
1482 && pBdle
1483 && pBdle->u32BdleMaxCvi));
1484 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1485 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1486 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1487 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1488#ifdef LOG_ENABLED
1489 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1490#endif
1491}
1492
1493static inline uint32_t hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1494{
1495 uint32_t cb2Copy;
1496 /*
1497 * Amounts of bytes depends on current position in buffer (u32BdleCviLen-u32BdleCviPos)
1498 */
1499 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1500 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1501 /*
1502 * we may increase the counter in range of [0, FIFOS + 1]
1503 */
1504 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1505 Assert((u32SoundBackendBufferBytesAvail > 0));
1506
1507 /* sanity check to avoid overriding sound backend buffer */
1508 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1509 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1510
1511 if (cb2Copy <= pBdle->cbUnderFifoW)
1512 return 0;
1513 cb2Copy -= pBdle->cbUnderFifoW; /* forcely reserve amount of ureported bytes to copy */
1514 return cb2Copy;
1515}
1516
1517static inline void hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1518{
1519 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1520 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1521 Assert((cbCopied));
1522 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1523 /* Assertion!!! It was copied less than cbUnderFifoW
1524 * Probably we need to move the buffer, but it rather hard to imagine situation
1525 * why it may happen.
1526 */
1527 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write whole buffer including not reported bytes */
1528 if ( pBdle->cbUnderFifoW
1529 && pBdle->cbUnderFifoW <= cbCopied)
1530 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1531
1532 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1533 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Assumption failed */
1534
1535 /* We always increment position on DMA buffer counter because we're always reading to intermediate buffer */
1536 pBdle->u32BdleCviPos += cbArranged2Copy;
1537
1538 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1539 /* We reports all bytes (including unreported previously) */
1540 *pu32DMACursor += cbCopied;
1541 /* reducing backend counter on amount of bytes we copied to backend */
1542 *pu32BackendBufferCapacity -= cbCopied;
1543 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1544 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1545}
1546
1547static inline void hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1548{
1549 Assert((cbCopied, cbArranged2Copy));
1550 *pu32BackendBufferCapacity -= cbCopied;
1551 pBdle->u32BdleCviPos += cbCopied;
1552 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1553 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1554 pBdle->cbUnderFifoW = 0;
1555 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1556 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1557}
1558
1559static inline void hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1560{
1561 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1562 pBdle->u32BdleCviPos += cbCopied;
1563 pBdle->cbUnderFifoW += cbCopied;
1564 /* In case of read transaction we're always coping from backend buffer */
1565 if (pu32BackendBufferCapacity)
1566 *pu32BackendBufferCapacity -= cbCopied;
1567 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1568 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pState, pStreamDesc)));
1569}
1570static inline bool hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1571{
1572 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1573 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1574
1575 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1576
1577 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1578 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1579 hdaUpdatePosBuf(pState, pStreamDesc);
1580
1581 /* don't touch BdleCvi counter on uninitialized descriptor */
1582 if ( pBdle->u32BdleCviPos
1583 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1584 {
1585 pBdle->u32BdleCviPos = 0;
1586 pBdle->u32BdleCvi++;
1587 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1588 pBdle->u32BdleCvi = 0;
1589 }
1590 return fOnBufferEdge;
1591}
1592
1593static inline void hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbInc)
1594{
1595 /*
1596 * if we're under FIFO Watermark it's expected that HDA doesn't fetch anything.
1597 * (ICH6 datasheet 18.2.38)
1598 */
1599 if (!pBdle->cbUnderFifoW)
1600 {
1601 *pStreamDesc->pu32Lpib += cbInc;
1602
1603 /*
1604 * Assert. Overlapping of buffer counter shouldn't happen.
1605 */
1606 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1607
1608 hdaUpdatePosBuf(pState, pStreamDesc);
1609
1610 }
1611}
1612
1613static inline bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1614{
1615 bool fDoNextTransferLoop = true;
1616 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1617 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1618 {
1619 if ( !pBdle->cbUnderFifoW
1620 && pBdle->fBdleCviIoc)
1621 {
1622 /*
1623 * @todo - more carefully investigate BCIS flag.
1624 * Speech synthesis works fine on Mac Guest if this bit isn't set
1625 * but in general sound quality becomes lesser.
1626 */
1627 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1628
1629 /*
1630 * we should generate the interrupt if ICE bit of SDCTL register is set.
1631 */
1632 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1633 hdaProcessInterrupt(pState);
1634 }
1635 fDoNextTransferLoop = false;
1636 }
1637 return fDoNextTransferLoop;
1638}
1639
1640/*
1641 * hdaReadAudio - copies samples from Qemu Sound back-end to DMA.
1642 * Note: this function writes immediately to DMA buffer, but "reports bytes" when all conditions meet (FIFOW)
1643 */
1644static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1645{
1646 PHDABDLEDESC pBdle = &pState->stInBdle;
1647 uint32_t cbTransfered = 0;
1648 uint32_t cb2Copy = 0;
1649 uint32_t cbBackendCopy = 0;
1650
1651 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1652
1653 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1654 if (!cb2Copy)
1655 {
1656 /* if we enter here we can't report "unreported bits" */
1657 *fStop = true;
1658 goto done;
1659 }
1660
1661
1662 /*
1663 * read from backend input line to last ureported position or at the begining.
1664 */
1665 cbBackendCopy = AUD_read (pState->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1666 /*
1667 * write on the HDA DMA
1668 */
1669 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1670
1671 /* Don't see reasons why cb2Copy could differ from cbBackendCopy */
1672 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1673
1674 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pState, 0))
1675 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1676 else
1677 {
1678 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1679 *fStop = true;
1680 }
1681 done:
1682 Assert((cbTransfered <= (SDFIFOS(pState, 0) + 1)));
1683 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransfered: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1684 return cbTransfered;
1685}
1686
1687static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1688{
1689 PHDABDLEDESC pBdle = &pState->stOutBdle;
1690 uint32_t cbTransfered = 0;
1691 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1692 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1693
1694 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1695
1696 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1697
1698 /*
1699 * Copy from DMA to the corresponding hdaBuffer (if there exists some bytes from the previous not reported transfer we write to ''pBdle->cbUnderFifoW'' offset)
1700 */
1701 if (!cb2Copy)
1702 {
1703 *fStop = true;
1704 goto done;
1705 }
1706
1707 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1708 /*
1709 * Write to audio backend. we should be sure whether we have enought bytes to copy to Audio backend.
1710 */
1711 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, pStreamDesc))
1712 {
1713 /*
1714 * We feed backend with new portion of fetched samples including not reported.
1715 */
1716 cbBackendCopy = AUD_write (pState->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1717 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1718 }
1719 else
1720 {
1721 /* Not enough bytes to be processed and reported, check luck on next enterence */
1722 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cb2Copy, NULL);
1723 *fStop = true;
1724 }
1725
1726 done:
1727 Assert((cbTransfered <= (SDFIFOS(pState, 4) + 1)));
1728 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransfered:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1729 return cbTransfered;
1730}
1731
1732DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1733{
1734 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1735 return VINF_SUCCESS;
1736}
1737
1738static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc)
1739{
1740 Assert(( pState
1741 && pBdle
1742 && pStreamDesc
1743 && u8Strm <= 7));
1744 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1745 pStreamDesc->u8Strm = u8Strm;
1746 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pState, CTL, u8Strm);
1747 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pState, BDPL, u8Strm),
1748 HDA_STREAM_REG2(pState, BDPU, u8Strm));
1749 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pState, LPIB, u8Strm);
1750 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pState, STS, u8Strm);
1751 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pState, CBL, u8Strm);
1752 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pState, FIFOS, u8Strm);
1753
1754 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pState, LVI, u8Strm);
1755#ifdef LOG_ENABLED
1756 if ( pBdle
1757 && pBdle->u32BdleMaxCvi)
1758 {
1759 Log(("Initialization of transfer descriptor:\n"));
1760 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1761 }
1762#endif
1763}
1764
1765DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1766{
1767 bool fStop = false;
1768 uint8_t u8Strm = 0;
1769 PHDABDLEDESC pBdle = NULL;
1770 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1771 HDASTREAMTRANSFERDESC stStreamDesc;
1772 uint32_t nBytes;
1773 switch (src)
1774 {
1775 case PO_INDEX:
1776 {
1777 u8Strm = 4;
1778 pBdle = &pState->stOutBdle;
1779 break;
1780 }
1781 case PI_INDEX:
1782 {
1783 u8Strm = 0;
1784 pBdle = &pState->stInBdle;
1785 break;
1786 }
1787 default:
1788 return;
1789 }
1790 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1791 while( avail && !fStop)
1792 {
1793 Assert ( (stStreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1794 && avail
1795 && stStreamDesc.u64BaseDMA);
1796
1797 /* Fetch the Buffer Descriptor Entry (BDE). */
1798
1799 if (hdaIsTransferCountersOverlapped(pState, pBdle, &stStreamDesc))
1800 hdaFetchBdle(pState, pBdle, &stStreamDesc);
1801 *stStreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1802 Assert((avail >= 0 && (stStreamDesc.u32Cbl >= (*stStreamDesc.pu32Lpib)))); /* sanity */
1803 uint32_t u32CblLimit = stStreamDesc.u32Cbl - (*stStreamDesc.pu32Lpib);
1804 Assert((u32CblLimit > hdaFifoWToSz(pState, &stStreamDesc)));
1805 Log(("hda: CBL=%d, LPIB=%d\n", stStreamDesc.u32Cbl, *stStreamDesc.pu32Lpib));
1806 switch (src)
1807 {
1808 case PO_INDEX:
1809 nBytes = hdaWriteAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1810 break;
1811 case PI_INDEX:
1812 nBytes = hdaReadAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1813 break;
1814 default:
1815 nBytes = 0;
1816 fStop = true;
1817 AssertMsgFailed(("Unsupported"));
1818 }
1819 Assert(nBytes <= (stStreamDesc.u32Fifos + 1));
1820 *stStreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1821
1822 /* Process end of buffer condition. */
1823 hdaStreamCounterUpdate(pState, pBdle, &stStreamDesc, nBytes);
1824 fStop = !fStop ? !hdaDoNextTransferCycle(pState, pBdle, &stStreamDesc) : fStop;
1825 }
1826}
1827
1828/**
1829 * Handle register read operation.
1830 *
1831 * Looks up and calls appropriate handler.
1832 *
1833 * @note: while implementation was detected so called "forgotten" or "hole" registers
1834 * which description is missed in RPM, datasheet or spec.
1835 *
1836 * @returns VBox status code.
1837 *
1838 * @param pState The device state structure.
1839 * @param uOffset Register offset in memory-mapped frame.
1840 * @param pv Where to fetch the value.
1841 * @param cb Number of bytes to write.
1842 * @thread EMT
1843 */
1844PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1845{
1846 int rc = VINF_SUCCESS;
1847 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1848 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1849 int index = hdaLookup(&pThis->hda, u32Offset);
1850 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1851 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1852
1853 if ( index == -1
1854 || cb > 4)
1855 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", u32Offset, cb));
1856
1857 if (index != -1)
1858 {
1859 uint32_t mask = 0;
1860 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1861 uint32_t v = 0;
1862 switch(cb)
1863 {
1864 case 1: mask = 0x000000ff; break;
1865 case 2: mask = 0x0000ffff; break;
1866 case 3: mask = 0x00ffffff; break;
1867 case 4: mask = 0xffffffff; break;
1868 }
1869 mask <<= shift;
1870 rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1871 *(uint32_t *)pv = (v & mask) >> shift;
1872 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
1873 return rc;
1874 }
1875 *(uint32_t *)pv = 0xFF;
1876 Log(("hda: hole at %X is accessed for read\n", u32Offset));
1877 return rc;
1878}
1879
1880/**
1881 * Handle register write operation.
1882 *
1883 * Looks up and calls appropriate handler.
1884 *
1885 * @returns VBox status code.
1886 *
1887 * @param pState The device state structure.
1888 * @param uOffset Register offset in memory-mapped frame.
1889 * @param pv Where to fetch the value.
1890 * @param cb Number of bytes to write.
1891 * @thread EMT
1892 */
1893PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1894{
1895 int rc = VINF_SUCCESS;
1896 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1897 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1898 int index = hdaLookup(&pThis->hda, u32Offset);
1899
1900 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1901 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1902
1903 if ( index == -1
1904 || cb > 4)
1905 LogRel(("hda: Invalid write access @0x%x(of bytes:%d)\n", u32Offset, cb));
1906
1907 if (index != -1)
1908 {
1909 uint32_t v = pThis->hda.au32Regs[index];
1910 uint32_t mask = 0;
1911 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1912 switch(cb)
1913 {
1914 case 1: mask = 0xffffff00; break;
1915 case 2: mask = 0xffff0000; break;
1916 case 3: mask = 0xff000000; break;
1917 case 4: mask = 0x00000000; break;
1918 }
1919 mask <<= shift;
1920 *(uint32_t *)pv = ((v & mask) | (*(uint32_t *)pv & ~mask)) >> shift;
1921 rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
1922 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
1923 return rc;
1924 }
1925 Log(("hda: hole at %X is accessed for write\n", u32Offset));
1926 return rc;
1927}
1928
1929/**
1930 * Callback function for mapping a PCI I/O region.
1931 *
1932 * @return VBox status code.
1933 * @param pPciDev Pointer to PCI device.
1934 * Use pPciDev->pDevIns to get the device instance.
1935 * @param iRegion The region number.
1936 * @param GCPhysAddress Physical address of the region.
1937 * If iType is PCI_ADDRESS_SPACE_IO, this is an
1938 * I/O port, else it's a physical address.
1939 * This address is *NOT* relative
1940 * to pci_mem_base like earlier!
1941 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
1942 */
1943static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
1944 RTGCPHYS GCPhysAddress, uint32_t cb,
1945 PCIADDRESSSPACE enmType)
1946{
1947 int rc;
1948 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1949 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1950 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1951
1952 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1953 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
1954 hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
1955
1956 if (RT_FAILURE(rc))
1957 return rc;
1958
1959 pThis->hda.addrMMReg = GCPhysAddress;
1960 return VINF_SUCCESS;
1961}
1962
1963/**
1964 * Saves a state of the HDA device.
1965 *
1966 * @returns VBox status code.
1967 * @param pDevIns The device instance.
1968 * @param pSSMHandle The handle to save the state to.
1969 */
1970static DECLCALLBACK(int) hdaSaveExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1971{
1972 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1973 /* Save Codec nodes states */
1974 codecSaveState(&pThis->hda.Codec, pSSMHandle);
1975 /* Save MMIO registers */
1976 SSMR3PutMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1977 /* Save HDA dma counters */
1978 SSMR3PutMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
1979 SSMR3PutMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
1980 SSMR3PutMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
1981 return VINF_SUCCESS;
1982}
1983
1984/**
1985 * Loads a saved HDA device state.
1986 *
1987 * @returns VBox status code.
1988 * @param pDevIns The device instance.
1989 * @param pSSMHandle The handle to the saved state.
1990 * @param uVersion The data unit version number.
1991 * @param uPass The data pass.
1992 */
1993static DECLCALLBACK(int) hdaLoadExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1994 uint32_t uVersion, uint32_t uPass)
1995{
1996 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1997 /* Load Codec nodes states */
1998 AssertMsgReturn (uVersion == HDA_SSM_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1999 Assert (uPass == SSM_PASS_FINAL); NOREF(uPass);
2000
2001 codecLoadState(&pThis->hda.Codec, pSSMHandle);
2002 /* Load MMIO registers */
2003 SSMR3GetMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
2004 /* Load HDA dma counters */
2005 SSMR3GetMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
2006 SSMR3GetMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
2007 SSMR3GetMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
2008
2009 AUD_set_active_in(pThis->hda.Codec.SwVoiceIn, SDCTL(&pThis->hda, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2010 AUD_set_active_out(pThis->hda.Codec.SwVoiceOut, SDCTL(&pThis->hda, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2011
2012 pThis->hda.u64CORBBase = CORBLBASE(&pThis->hda);
2013 pThis->hda.u64CORBBase |= ((uint64_t)CORBUBASE(&pThis->hda)) << 32;
2014 pThis->hda.u64RIRBBase = RIRLBASE(&pThis->hda);
2015 pThis->hda.u64RIRBBase |= ((uint64_t)RIRUBASE(&pThis->hda)) << 32;
2016 pThis->hda.u64DPBase = DPLBASE(&pThis->hda);
2017 pThis->hda.u64DPBase |= ((uint64_t)DPUBASE(&pThis->hda)) << 32;
2018 return VINF_SUCCESS;
2019}
2020
2021/**
2022 * Reset notification.
2023 *
2024 * @returns VBox status.
2025 * @param pDevIns The device instance data.
2026 *
2027 * @remark The original sources didn't install a reset handler, but it seems to
2028 * make sense to me so we'll do it.
2029 */
2030static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
2031{
2032 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2033 GCAP(&pThis->hda) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
2034 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
2035 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2036 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2037 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
2038 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
2039 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
2040 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
2041 CORBRP(&pThis->hda) = 0x0;
2042 RIRBWP(&pThis->hda) = 0x0;
2043
2044 Log(("hda: inter HDA reset.\n"));
2045 pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
2046
2047 if (pThis->hda.pu32CorbBuf)
2048 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
2049 else
2050 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
2051
2052 pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
2053 if (pThis->hda.pu64RirbBuf)
2054 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
2055 else
2056 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
2057
2058 pThis->hda.u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2059
2060 HDABDLEDESC stEmptyBdle;
2061 for(uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2062 {
2063 HDASTREAMTRANSFERDESC stStreamDesc;
2064 PHDABDLEDESC pBdle = NULL;
2065 if (u8Strm == 0)
2066 pBdle = &pThis->hda.stInBdle;
2067 else if(u8Strm == 4)
2068 pBdle = &pThis->hda.stOutBdle;
2069 else
2070 {
2071 memset(&stEmptyBdle, 0, sizeof(HDABDLEDESC));
2072 pBdle = &stEmptyBdle;
2073 }
2074 hdaInitTransferDescriptor(&pThis->hda, pBdle, u8Strm, &stStreamDesc);
2075 /* hdaStreamReset prevents changing SRST bit, so we zerro it here forcely. */
2076 HDA_STREAM_REG2(&pThis->hda, CTL, u8Strm) = 0;
2077 hdaStreamReset(&pThis->hda, pBdle, &stStreamDesc, u8Strm);
2078 }
2079
2080 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
2081 STATESTS(&pThis->hda) = 0x1;
2082
2083 Log(("hda: reset finished\n"));
2084}
2085
2086/**
2087 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2088 */
2089static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
2090 const char *pszIID)
2091{
2092 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
2093 Assert(&pThis->hda.IBase == pInterface);
2094
2095 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
2096 return NULL;
2097}
2098
2099static inline int hdaLookUpRegisterByName(INTELHDLinkState *pState, const char *pszArgs)
2100{
2101 int iReg = 0;
2102 for (; iReg < HDA_NREGS; ++iReg)
2103 if (!RTStrICmp(s_ichIntelHDRegMap[iReg].abbrev, pszArgs))
2104 return iReg;
2105 return -1;
2106}
2107static inline void hdaDbgPrintRegister(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaIndex)
2108{
2109 Assert( pState
2110 && iHdaIndex >= 0
2111 && iHdaIndex < HDA_NREGS);
2112 pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", s_ichIntelHDRegMap[iHdaIndex].abbrev, pState->au32Regs[iHdaIndex]);
2113}
2114static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2115{
2116 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2117 INTELHDLinkState *hda = &pThis->hda;
2118 int iHdaRegisterIndex = hdaLookUpRegisterByName(hda, pszArgs);
2119 if (iHdaRegisterIndex != -1)
2120 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2121 else
2122 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
2123 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2124}
2125
2126static inline void hdaDbgPrintStream(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
2127{
2128 Assert( pState
2129 && iHdaStrmIndex >= 0
2130 && iHdaStrmIndex < 7);
2131 pHlp->pfnPrintf(pHlp, "Dump of %d Hda Stream:\n", iHdaStrmIndex);
2132 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, CTL, iHdaStrmIndex));
2133 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, STS, iHdaStrmIndex));
2134 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOS, iHdaStrmIndex));
2135 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOW, iHdaStrmIndex));
2136}
2137
2138static inline int hdaLookUpStreamIndex(INTELHDLinkState *pState, const char *pszArgs)
2139{
2140 /* todo: add args parsing */
2141 return -1;
2142}
2143static DECLCALLBACK(void) hdaDbgStreamInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2144{
2145 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2146 INTELHDLinkState *hda = &pThis->hda;
2147 int iHdaStrmIndex = hdaLookUpStreamIndex(hda, pszArgs);
2148 if (iHdaStrmIndex != -1)
2149 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2150 else
2151 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
2152 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2153}
2154
2155/* Codec debugger interface */
2156static DECLCALLBACK(void) hdaCodecDbgNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2157{
2158 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2159 INTELHDLinkState *hda = &pThis->hda;
2160 if (hda->Codec.pfnCodecDbgListNodes)
2161 hda->Codec.pfnCodecDbgListNodes(&hda->Codec, pHlp, pszArgs);
2162 else
2163 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2164}
2165
2166static DECLCALLBACK(void) hdaCodecDbgSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2167{
2168 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2169 INTELHDLinkState *hda = &pThis->hda;
2170 if (hda->Codec.pfnCodecDbgSelector)
2171 hda->Codec.pfnCodecDbgSelector(&hda->Codec, pHlp, pszArgs);
2172 else
2173 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2174}
2175
2176//#define HDA_AS_PCI_EXPRESS
2177/* Misc routines */
2178static inline bool printHdaIsValid(const char *pszType, const char *pszExpectedFlag)
2179{
2180 return (RTStrCmp(pszType, pszExpectedFlag) == 0);
2181}
2182static const char *printHdaYesNo(bool fFlag)
2183{
2184 return fFlag ? "yes" : "no";
2185}
2186static DECLCALLBACK(size_t)
2187printHdaStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2188 const char *pszType, void const *pvValue,
2189 int cchWidth, int cchPrecision, unsigned fFlags,
2190 void *pvUser)
2191{
2192 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
2193 size_t cb = 0;
2194 if (!printHdaIsValid(pszType, "sdctl"))
2195 return cb;
2196 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2197 "SDCTL(raw: %#0x, strm:0x%x, dir:%s, tp:%s strip:%x, deie:%s, ioce:%s, run:%s, srst:%s)",
2198 sdCtl,
2199 ((sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> ICH6_HDA_SDCTL_NUM_SHIFT),
2200 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR))),
2201 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP))),
2202 ((sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> ICH6_HDA_SDCTL_STRIPE_SHIFT),
2203 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE))),
2204 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))),
2205 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))),
2206 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST))));
2207 return cb;
2208}
2209
2210static DECLCALLBACK(size_t)
2211printHdaStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2212 const char *pszType, void const *pvValue,
2213 int cchWidth, int cchPrecision, unsigned fFlags,
2214 void *pvUser)
2215{
2216 uint32_t sdFifos = (uint32_t)(uintptr_t)pvValue;
2217 uint32_t u32Bytes = 0;
2218 size_t cb = 0;
2219 if (!printHdaIsValid(pszType, "sdfifos"))
2220 return cb;
2221 switch(sdFifos)
2222 {
2223 case HDA_SDONFIFO_16B: u32Bytes = 16; break;
2224 case HDA_SDONFIFO_32B: u32Bytes = 32; break;
2225 case HDA_SDONFIFO_64B: u32Bytes = 64; break;
2226 case HDA_SDONFIFO_128B: u32Bytes = 128; break;
2227 case HDA_SDONFIFO_192B: u32Bytes = 192; break;
2228 case HDA_SDONFIFO_256B: u32Bytes = 256; break;
2229 case HDA_SDINFIFO_120B: u32Bytes = 120; break;
2230 case HDA_SDINFIFO_160B: u32Bytes = 160; break;
2231 default:;
2232 }
2233 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2234 "SDFIFOS(raw: %#0x, sdfifos:%d B)",
2235 sdFifos,
2236 u32Bytes);
2237 return cb;
2238}
2239
2240static DECLCALLBACK(size_t)
2241printHdaStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2242 const char *pszType, void const *pvValue,
2243 int cchWidth, int cchPrecision, unsigned fFlags,
2244 void *pvUser)
2245{
2246 uint32_t sdFifow = (uint32_t)(uintptr_t)pvValue;
2247 uint32_t u32Bytes = 0;
2248 size_t cb = 0;
2249 if (!printHdaIsValid(pszType, "sdfifow"))
2250 return cb;
2251 switch(sdFifow)
2252 {
2253 case HDA_SDFIFOW_8B: u32Bytes = 8; break;
2254 case HDA_SDFIFOW_16B: u32Bytes = 16; break;
2255 case HDA_SDFIFOW_32B: u32Bytes = 32; break;
2256 }
2257 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2258 "SDFIFOW(raw: %#0x, sdfifow:%d B)",
2259 sdFifow,
2260 u32Bytes);
2261 return cb;
2262}
2263
2264static DECLCALLBACK(size_t)
2265printHdaStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2266 const char *pszType, void const *pvValue,
2267 int cchWidth, int cchPrecision, unsigned fFlags,
2268 void *pvUser)
2269{
2270 uint32_t sdSts = (uint32_t)(uintptr_t)pvValue;
2271 size_t cb = 0;
2272 if (!printHdaIsValid(pszType, "sdsts"))
2273 return cb;
2274 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2275 "SDSTS(raw: %#0x, fifordy:%s, dese:%s, fifoe:%s, bcis:%s)",
2276 sdSts,
2277 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY))),
2278 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE))),
2279 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE))),
2280 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))));
2281 return cb;
2282}
2283/**
2284 * This routine registers debugger info extensions and custom printf formatters
2285 */
2286static inline int hdaInitMisc(PPDMDEVINS pDevIns)
2287{
2288 int rc;
2289 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
2290 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgStreamInfo);
2291 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaCodecDbgNodes);
2292 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaCodecDbgSelector);
2293 rc = RTStrFormatTypeRegister("sdctl", printHdaStrmCtl, NULL);
2294 AssertRC(rc);
2295 rc = RTStrFormatTypeRegister("sdsts", printHdaStrmSts, NULL);
2296 AssertRC(rc);
2297 rc = RTStrFormatTypeRegister("sdfifos", printHdaStrmFifos, NULL);
2298 AssertRC(rc);
2299 rc = RTStrFormatTypeRegister("sdfifow", printHdaStrmFifow, NULL);
2300 AssertRC(rc);
2301#if 0
2302 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
2303 AssertRC(rc);
2304#endif
2305 return rc;
2306}
2307
2308/**
2309 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2310 */
2311static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
2312 PCFGMNODE pCfgHandle)
2313{
2314 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2315 INTELHDLinkState *s = &pThis->hda;
2316 int rc;
2317
2318 Assert(iInstance == 0);
2319 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2320
2321 /*
2322 * Validations.
2323 */
2324 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
2325 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2326 N_ ("Invalid configuration for the INTELHD device"));
2327
2328 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
2329 // poll some register(s).
2330
2331 /*
2332 * Initialize data (most of it anyway).
2333 */
2334 s->pDevIns = pDevIns;
2335 /* IBase */
2336 s->IBase.pfnQueryInterface = hdaQueryInterface;
2337
2338 /* PCI Device (the assertions will be removed later) */
2339 PCIDevSetVendorId (&pThis->dev, HDA_PCI_VENDOR_ID); /* nVidia */
2340 PCIDevSetDeviceId (&pThis->dev, HDA_PCI_DEICE_ID); /* HDA */
2341
2342 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
2343 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2344 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
2345 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
2346 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
2347 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2348 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
2349 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
2350 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2351 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
2352 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */
2353
2354#if defined(HDA_AS_PCI_EXPRESS)
2355 PCIDevSetCapabilityList (&pThis->dev, 0x80);
2356#elif defined(VBOX_WITH_MSI_DEVICES)
2357 PCIDevSetCapabilityList (&pThis->dev, 0x60);
2358#else
2359 PCIDevSetCapabilityList (&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
2360#endif
2361
2362 //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2363 // of these values needs to be properly documented!
2364 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2365 PCIDevSetByte(&pThis->dev, 0x40, 0x01);
2366
2367 /* Power Management */
2368 PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2369 PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
2370 PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2371
2372#ifdef HDA_AS_PCI_EXPRESS
2373 /* PCI Express */
2374 PCIDevSetByte (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2375 PCIDevSetByte (&pThis->dev, 0x80 + 1, 0x60); /* next */
2376 /* Device flags */
2377 PCIDevSetWord (&pThis->dev, 0x80 + 2,
2378 /* version */ 0x1 |
2379 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2380 /* MSI */ (100) << 9
2381 );
2382 /* Device capabilities */
2383 PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2384 /* Device control */
2385 PCIDevSetWord (&pThis->dev, 0x80 + 8, 0);
2386 /* Device status */
2387 PCIDevSetWord (&pThis->dev, 0x80 + 10, 0);
2388 /* Link caps */
2389 PCIDevSetDWord (&pThis->dev, 0x80 + 12, 0);
2390 /* Link control */
2391 PCIDevSetWord (&pThis->dev, 0x80 + 16, 0);
2392 /* Link status */
2393 PCIDevSetWord (&pThis->dev, 0x80 + 18, 0);
2394 /* Slot capabilities */
2395 PCIDevSetDWord (&pThis->dev, 0x80 + 20, 0);
2396 /* Slot control */
2397 PCIDevSetWord (&pThis->dev, 0x80 + 24, 0);
2398 /* Slot status */
2399 PCIDevSetWord (&pThis->dev, 0x80 + 26, 0);
2400 /* Root control */
2401 PCIDevSetWord (&pThis->dev, 0x80 + 28, 0);
2402 /* Root capabilities */
2403 PCIDevSetWord (&pThis->dev, 0x80 + 30, 0);
2404 /* Root status */
2405 PCIDevSetDWord (&pThis->dev, 0x80 + 32, 0);
2406 /* Device capabilities 2 */
2407 PCIDevSetDWord (&pThis->dev, 0x80 + 36, 0);
2408 /* Device control 2 */
2409 PCIDevSetQWord (&pThis->dev, 0x80 + 40, 0);
2410 /* Link control 2 */
2411 PCIDevSetQWord (&pThis->dev, 0x80 + 48, 0);
2412 /* Slot control 2 */
2413 PCIDevSetWord (&pThis->dev, 0x80 + 56, 0);
2414#endif
2415
2416 /*
2417 * Register the PCI device.
2418 */
2419 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
2420 if (RT_FAILURE (rc))
2421 return rc;
2422
2423 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
2424 hdaMap);
2425 if (RT_FAILURE (rc))
2426 return rc;
2427
2428#ifdef VBOX_WITH_MSI_DEVICES
2429 PDMMSIREG aMsiReg;
2430
2431 RT_ZERO(aMsiReg);
2432 aMsiReg.cMsiVectors = 1;
2433 aMsiReg.iMsiCapOffset = 0x60;
2434 aMsiReg.iMsiNextOffset = 0x50;
2435 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
2436 if (RT_FAILURE (rc))
2437 {
2438 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2439 PCIDevSetCapabilityList (&pThis->dev, 0x50);
2440 }
2441#endif
2442
2443 rc = PDMDevHlpSSMRegister (pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2444 if (RT_FAILURE (rc))
2445 return rc;
2446
2447 /*
2448 * Attach driver.
2449 */
2450 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
2451 &s->pDrvBase, "Audio Driver Port");
2452 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2453 Log (("hda: No attached driver!\n"));
2454 else if (RT_FAILURE (rc))
2455 {
2456 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
2457 return rc;
2458 }
2459
2460
2461
2462 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
2463 rc = codecConstruct(pDevIns, &pThis->hda.Codec, pCfgHandle);
2464 if (RT_FAILURE(rc))
2465 AssertRCReturn(rc, rc);
2466
2467 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2468 verb F20 should provide device/codec recognition. */
2469 Assert(pThis->hda.Codec.u16VendorId);
2470 Assert(pThis->hda.Codec.u16DeviceId);
2471 PCIDevSetSubSystemVendorId (&pThis->dev, pThis->hda.Codec.u16VendorId); /* 2c ro - intel.) */
2472 PCIDevSetSubSystemId (&pThis->dev, pThis->hda.Codec.u16DeviceId); /* 2e ro. */
2473
2474 hdaReset (pDevIns);
2475 pThis->hda.Codec.id = 0;
2476 pThis->hda.Codec.pfnTransfer = hdaTransfer;
2477 pThis->hda.Codec.pfnReset = hdaCodecReset;
2478 /*
2479 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2480 * hdaReset shouldn't affects these registers.
2481 */
2482 WAKEEN(&pThis->hda) = 0x0;
2483 STATESTS(&pThis->hda) = 0x0;
2484 hdaInitMisc(pDevIns);
2485
2486 return VINF_SUCCESS;
2487}
2488
2489/**
2490 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2491 */
2492static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
2493{
2494 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2495
2496 int rc = codecDestruct(&pThis->hda.Codec);
2497 AssertRC(rc);
2498 if (pThis->hda.pu32CorbBuf)
2499 RTMemFree(pThis->hda.pu32CorbBuf);
2500 if (pThis->hda.pu64RirbBuf)
2501 RTMemFree(pThis->hda.pu64RirbBuf);
2502 return VINF_SUCCESS;
2503}
2504
2505/**
2506 * The device registration structure.
2507 */
2508const PDMDEVREG g_DeviceICH6_HDA =
2509{
2510 /* u32Version */
2511 PDM_DEVREG_VERSION,
2512 /* szName */
2513 "hda",
2514 /* szRCMod */
2515 "",
2516 /* szR0Mod */
2517 "",
2518 /* pszDescription */
2519 "ICH IntelHD Audio Controller",
2520 /* fFlags */
2521 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2522 /* fClass */
2523 PDM_DEVREG_CLASS_AUDIO,
2524 /* cMaxInstances */
2525 1,
2526 /* cbInstance */
2527 sizeof(PCIINTELHDLinkState),
2528 /* pfnConstruct */
2529 hdaConstruct,
2530 /* pfnDestruct */
2531 hdaDestruct,
2532 /* pfnRelocate */
2533 NULL,
2534 /* pfnIOCtl */
2535 NULL,
2536 /* pfnPowerOn */
2537 NULL,
2538 /* pfnReset */
2539 hdaReset,
2540 /* pfnSuspend */
2541 NULL,
2542 /* pfnResume */
2543 NULL,
2544 /* pfnAttach */
2545 NULL,
2546 /* pfnDetach */
2547 NULL,
2548 /* pfnQueryInterface. */
2549 NULL,
2550 /* pfnInitComplete */
2551 NULL,
2552 /* pfnPowerOff */
2553 NULL,
2554 /* pfnSoftReset */
2555 NULL,
2556 /* u32VersionEnd */
2557 PDM_DEVREG_VERSION
2558};
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