VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 44582

Last change on this file since 44582 was 44571, checked in by vboxsync, 12 years ago

Fixed hungarian typos in MSI registration code. Some E1000 prefix adjustments.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 118.2 KB
Line 
1/* $Id: DevIchIntelHDA.cpp 44571 2013-02-06 14:10:37Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/vmm/pdmdev.h>
23#include <VBox/version.h>
24
25#include <iprt/assert.h>
26#include <iprt/uuid.h>
27#include <iprt/string.h>
28#include <iprt/mem.h>
29#include <iprt/asm.h>
30#include <iprt/asm-math.h>
31
32#include "VBoxDD.h"
33
34extern "C" {
35#include "audio.h"
36}
37#include "DevCodec.h"
38
39#define VBOX_WITH_INTEL_HDA
40
41#if defined(VBOX_WITH_HP_HDA)
42/* HP Pavilion dv4t-1300 */
43# define HDA_PCI_VENDOR_ID 0x103c
44# define HDA_PCI_DEICE_ID 0x30f7
45#elif defined(VBOX_WITH_INTEL_HDA)
46/* Intel HDA controller */
47# define HDA_PCI_VENDOR_ID 0x8086
48# define HDA_PCI_DEICE_ID 0x2668
49#elif defined(VBOX_WITH_NVIDIA_HDA)
50/* nVidia HDA controller */
51# define HDA_PCI_VENDOR_ID 0x10de
52# define HDA_PCI_DEICE_ID 0x0ac0
53#else
54# error "Please specify your HDA device vendor/device IDs"
55#endif
56
57PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
58PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb);
59static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
60
61#define HDA_NREGS 112
62/* Registers */
63#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
64#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
65#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
66#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
67#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
68#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
69#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
70#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
71#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
72#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
73
74#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
75#define GCAP(pState) (HDA_REG((pState), GCAP))
76/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
77 * oss (15:12) - number of output streams supported
78 * iss (11:8) - number of input streams supported
79 * bss (7:3) - number of bidirectional streams supported
80 * bds (2:1) - number of serial data out signals supported
81 * b64sup (0) - 64 bit addressing supported.
82 */
83#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
84 ( (((oss) & 0xF) << 12) \
85 | (((iss) & 0xF) << 8) \
86 | (((bss) & 0x1F) << 3) \
87 | (((bds) & 0x3) << 2) \
88 | ((b64sup) & 1))
89#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
90#define VMIN(pState) (HDA_REG((pState), VMIN))
91
92#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
93#define VMAJ(pState) (HDA_REG((pState), VMAJ))
94
95#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
96#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
97
98#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
99#define INPAY(pState) (HDA_REG((pState), INPAY))
100
101#define ICH6_HDA_REG_GCTL (5)
102#define ICH6_HDA_GCTL_RST_SHIFT (0)
103#define ICH6_HDA_GCTL_FSH_SHIFT (1)
104#define ICH6_HDA_GCTL_UR_SHIFT (8)
105#define GCTL(pState) (HDA_REG((pState), GCTL))
106
107#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
108#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
109
110#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
111#define STATESTS(pState) (HDA_REG((pState), STATESTS))
112#define ICH6_HDA_STATES_SCSF 0x7
113
114#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
115#define ICH6_HDA_GSTS_FSH_SHIFT (1)
116#define GSTS(pState) (HDA_REG(pState, GSTS))
117
118#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
119#define ICH6_HDA_INTCTL_GIE_SHIFT 31
120#define ICH6_HDA_INTCTL_CIE_SHIFT 30
121#define ICH6_HDA_INTCTL_S0_SHIFT (0)
122#define ICH6_HDA_INTCTL_S1_SHIFT (1)
123#define ICH6_HDA_INTCTL_S2_SHIFT (2)
124#define ICH6_HDA_INTCTL_S3_SHIFT (3)
125#define ICH6_HDA_INTCTL_S4_SHIFT (4)
126#define ICH6_HDA_INTCTL_S5_SHIFT (5)
127#define ICH6_HDA_INTCTL_S6_SHIFT (6)
128#define ICH6_HDA_INTCTL_S7_SHIFT (7)
129#define INTCTL(pState) (HDA_REG((pState), INTCTL))
130#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
131#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
132#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
133#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
134
135/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
136 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
137 * the datasheet.
138 */
139#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
140#define SSYNC(pState) (HDA_REG((pState), SSYNC))
141
142#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
143#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
144#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
145#define ICH6_HDA_INTSTS_S0_SHIFT (0)
146#define ICH6_HDA_INTSTS_S1_SHIFT (1)
147#define ICH6_HDA_INTSTS_S2_SHIFT (2)
148#define ICH6_HDA_INTSTS_S3_SHIFT (3)
149#define ICH6_HDA_INTSTS_S4_SHIFT (4)
150#define ICH6_HDA_INTSTS_S5_SHIFT (5)
151#define ICH6_HDA_INTSTS_S6_SHIFT (6)
152#define ICH6_HDA_INTSTS_S7_SHIFT (7)
153#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
154#define INTSTS(pState) (HDA_REG((pState), INTSTS))
155#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
156#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
157#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
158#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
159
160#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
161#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
162#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
163#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
164#define ICH6_HDA_REG_CORBWP 15 /* 48 */
165#define ICH6_HDA_REG_CORBRP 16 /* 4A */
166#define ICH6_HDA_CORBRP_RST_SHIFT 15
167#define ICH6_HDA_CORBRP_WP_SHIFT 0
168#define ICH6_HDA_CORBRP_WP_MASK 0xFF
169
170#define CORBRP(pState) (HDA_REG(pState, CORBRP))
171#define CORBWP(pState) (HDA_REG(pState, CORBWP))
172
173#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
174#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
175#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
176
177#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
178
179
180#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
181#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
182#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
183
184#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
185#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
186#define ICH6_HDA_CORBSIZE_SZ 0x3
187#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
188#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
189/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
190
191#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
192#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
193
194#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
195#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
196
197#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
198#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
199#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
200#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
201
202#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
203#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
204#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
205
206#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
207#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
208#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
209#define ICH6_HDA_ROI_DMA_SHIFT (2)
210#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
211#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
212#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
213#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
214
215#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
216#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
217#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
218#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
219#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
220#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
221
222#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
223#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
224#define ICH6_HDA_RIRBSIZE_SZ 0x3
225
226#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
227#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
228
229
230#define ICH6_HDA_REG_IC 27 /* 0x60 */
231#define IC(pState) (HDA_REG(pState, IC))
232#define ICH6_HDA_REG_IR 28 /* 0x64 */
233#define IR(pState) (HDA_REG(pState, IR))
234#define ICH6_HDA_REG_IRS 29 /* 0x68 */
235#define ICH6_HDA_IRS_ICB_SHIFT (0)
236#define ICH6_HDA_IRS_IRV_SHIFT (1)
237#define IRS(pState) (HDA_REG(pState, IRS))
238#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
239#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
240
241#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
242#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
243#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
244#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
245#define DPBASE_ENABLED 1
246#define DPBASE_ADDR_MASK (~0x7f)
247
248#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
249#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
250/* Note: sdnum here _MUST_ be stream reg number [0,7] */
251#define HDA_STREAM_REG2(pState, name, sdnum) (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
252
253#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
254#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
255#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
256#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
257#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
258#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
259#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
260#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
261
262#define SD(func, num) SD##num##func
263#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
264#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
265#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
266#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
267#define ICH6_HDA_SDCTL_DIR_SHIFT (19)
268#define ICH6_HDA_SDCTL_TP_SHIFT (18)
269#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)
270#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)
271#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
272#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
273#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
274#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
275#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
276
277#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
278#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
279#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
280#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
281#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
282#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
283#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
284#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
285
286#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
287#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
288#define ICH6_HDA_SDSTS_DE_SHIFT (4)
289#define ICH6_HDA_SDSTS_FE_SHIFT (3)
290#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
291
292#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
293#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
294#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
295#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
296#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
297#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
298#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
299#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
300
301#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
302
303#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
304#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
305#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
306#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
307#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
308#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
309#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
310#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
311
312#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
313
314#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
315#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
316#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
317#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
318#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
319#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
320#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
321#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
322
323#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
324
325#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
326#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
327#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
328#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
329#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
330#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
331#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
332#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
333
334/*
335 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
336 */
337#define HDA_SDFIFOW_8B (0x2)
338#define HDA_SDFIFOW_16B (0x3)
339#define HDA_SDFIFOW_32B (0x4)
340#define SDFIFOW(pState, num) HDA_REG((pState), SD(FIFOW, num))
341
342#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
343#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
344#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
345#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
346#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
347#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
348#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
349#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
350
351/*
352 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
353 * formula: size - 1
354 * Other values not listed are not supported.
355 */
356#define HDA_SDONFIFO_16B (0x0F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
357#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
358#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
359#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
360#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
361#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
362#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
363#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
364#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
365
366#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
367#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
368#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
369#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
370#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
371#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
372#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
373#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
374
375#define SDFMT(pState, num) (HDA_REG((pState), SD(FMT, num)))
376#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
377#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
378#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
379#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
380#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
381#define ICH6_HDA_SDFMT_BITS_SHIFT (4)
382#define ICH6_HDA_SDFMT_BITS_MASK (0x7)
383#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
384#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
385#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
386
387#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
388#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
389#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
390#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
391#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
392#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
393#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
394#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
395
396#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
397
398#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
399#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
400#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
401#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
402#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
403#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
404#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
405#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
406
407#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
408
409
410typedef struct HDABDLEDESC
411{
412 uint64_t u64BdleCviAddr;
413 uint32_t u32BdleMaxCvi;
414 uint32_t u32BdleCvi;
415 uint32_t u32BdleCviLen;
416 uint32_t u32BdleCviPos;
417 bool fBdleCviIoc;
418 uint32_t cbUnderFifoW;
419 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
420} HDABDLEDESC, *PHDABDLEDESC;
421
422
423/** HDABDLEDESC field descriptors the v3+ saved state. */
424static SSMFIELD const g_aHdaBDLEDescFields[] =
425{
426 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
427 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
428 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
429 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
430 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
431 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
432 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
433 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
434 SSMFIELD_ENTRY_TERM()
435};
436
437/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
438static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
439{
440 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
441 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
442 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
443 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
444 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
445 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
446 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
447 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
448 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
449 SSMFIELD_ENTRY_TERM()
450};
451
452typedef struct HDASTREAMTRANSFERDESC
453{
454 uint64_t u64BaseDMA;
455 uint32_t u32Ctl;
456 uint32_t *pu32Sts;
457 uint8_t u8Strm;
458 uint32_t *pu32Lpib;
459 uint32_t u32Cbl;
460 uint32_t u32Fifos;
461} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
462
463typedef struct INTELHDLinkState
464{
465 /** Pointer to the device instance. */
466 PPDMDEVINSR3 pDevIns;
467 /** Pointer to the connector of the attached audio driver. */
468 PPDMIAUDIOCONNECTOR pDrv;
469 /** Pointer to the attached audio driver. */
470 PPDMIBASE pDrvBase;
471 /** The base interface for LUN\#0. */
472 PDMIBASE IBase;
473 RTGCPHYS addrMMReg;
474 uint32_t au32Regs[HDA_NREGS];
475 HDABDLEDESC stInBdle;
476 HDABDLEDESC stOutBdle;
477 HDABDLEDESC stMicBdle;
478 /* Interrupt on completion */
479 bool fCviIoc;
480 uint64_t u64CORBBase;
481 uint64_t u64RIRBBase;
482 uint64_t u64DPBase;
483 /* pointer to CORB buf */
484 uint32_t *pu32CorbBuf;
485 /* size in bytes of CORB buf */
486 uint32_t cbCorbBuf;
487 /* pointer on RIRB buf */
488 uint64_t *pu64RirbBuf;
489 /* size in bytes of RIRB buf */
490 uint32_t cbRirbBuf;
491 /* indicates if HDA in reset. */
492 bool fInReset;
493 CODECState Codec;
494 uint8_t u8Counter;
495 uint64_t u64BaseTS;
496} INTELHDLinkState, *PINTELHDLinkState;
497
498#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
499#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
500
501#define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In, \
502 SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
503#define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out, \
504 SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
505
506
507
508
509typedef struct PCIINTELHDLinkState
510{
511 PCIDevice dev;
512 INTELHDLinkState hda;
513} PCIINTELHDLinkState;
514
515
516/** @todo r=bird: Why aren't these static? And why use DECLCALLBACK for
517 * internal functions? */
518DECLCALLBACK(int) hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
519DECLCALLBACK(int) hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
520DECLCALLBACK(int) hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
521DECLCALLBACK(int) hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
522DECLCALLBACK(int) hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
523DECLCALLBACK(int) hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
524DECLCALLBACK(int) hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
525DECLCALLBACK(int) hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
526DECLCALLBACK(int) hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
527DECLCALLBACK(int) hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
528DECLCALLBACK(int) hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
529DECLCALLBACK(int) hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
530DECLCALLBACK(int) hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
531DECLCALLBACK(int) hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
532DECLCALLBACK(int) hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
533DECLCALLBACK(int) hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
534DECLCALLBACK(int) hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
535DECLCALLBACK(int) hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
536DECLCALLBACK(int) hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
537DECLCALLBACK(int) hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
538
539DECLCALLBACK(int) hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
540DECLCALLBACK(int) hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
541DECLCALLBACK(int) hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
542DECLCALLBACK(int) hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
543DECLCALLBACK(int) hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
544DECLCALLBACK(int) hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
545DECLCALLBACK(int) hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
546DECLCALLBACK(int) hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
547DECLCALLBACK(int) hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
548DECLCALLBACK(int) hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
549DECLCALLBACK(int) hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
550DECLCALLBACK(int) hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
551DECLCALLBACK(int) hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
552DECLCALLBACK(int) hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
553DECLCALLBACK(int) hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
554DECLCALLBACK(int) hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
555
556DECLINLINE(void) hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc);
557static int hdaMMIORegLookup(INTELHDLinkState* pState, uint32_t u32Offset);
558static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
559#ifdef LOG_ENABLED
560static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
561#endif
562
563
564/* see 302349 p 6.2*/
565const static struct stIchIntelHDRegMap
566{
567 /** Register offset in the register space. */
568 uint32_t offset;
569 /** Size in bytes. Registers of size > 4 are in fact tables. */
570 uint32_t size;
571 /** Readable bits. */
572 uint32_t readable;
573 /** Writable bits. */
574 uint32_t writable;
575 /** Read callback. */
576 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
577 /** Write callback. */
578 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
579 /** Abbreviated name. */
580 const char *abbrev;
581 /** Full name. */
582 const char *name;
583} s_ichIntelHDRegMap[HDA_NREGS] =
584{
585 /* offset size read mask write mask read callback write callback abbrev full name */
586 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
587 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
588 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
589 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
590 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
591 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
592 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
593 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
594 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
595 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
596 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
597 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
598 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
599 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
600 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
601 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
602 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
603 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
604 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
605 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
606 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
607 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
608 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
609 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
610 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
611 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
612 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
613 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
614 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
615 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
616 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
617 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
618 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
619 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
620
621 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
622 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
623 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
624 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
625 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
626 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
627 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
628 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
629 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
630 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
631
632 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
633 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
634 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
635 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
636 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
637 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
638 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
639 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
640 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
641 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
642
643 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
644 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
645 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
646 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
647 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
648 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
649 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
650 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
651 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
652 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
653
654 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
655 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
656 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
657 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
658 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
659 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
660 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
661 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
662 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
663 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
664
665 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
666 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
667 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
668 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
669 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
670 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
671 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
672 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
673 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
674 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
675
676 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
677 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
678 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
679 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
680 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
681 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
682 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
683 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
684 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
685 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
686
687 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
688 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
689 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
690 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
691 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
692 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
693 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
694 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
695 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
696 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
697
698 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
699 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
700 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
701 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
702 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
703 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
704 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
705 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
706 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
707 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
708};
709
710static void inline hdaUpdatePosBuf(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
711{
712 if (pState->u64DPBase & DPBASE_ENABLED)
713 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
714 (pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
715}
716static uint32_t inline hdaFifoWToSz(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
717{
718#if 0
719 switch(HDA_STREAM_REG2(pState, FIFOW, pStreamDesc->u8Strm))
720 {
721 case HDA_SDFIFOW_8B: return 8;
722 case HDA_SDFIFOW_16B: return 16;
723 case HDA_SDFIFOW_32B: return 32;
724 default:
725 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
726 }
727#endif
728 return 0;
729}
730
731static int hdaProcessInterrupt(INTELHDLinkState* pState)
732{
733#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
734 ( INTCTL_SX((pState), num) \
735 && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
736 bool fIrq = false;
737 if ( INTCTL_CIE(pState)
738 && ( RIRBSTS_RINTFL(pState)
739 || RIRBSTS_RIRBOIS(pState)
740 || (STATESTS(pState) & WAKEEN(pState))))
741 fIrq = true;
742
743 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
744 || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
745 fIrq = true;
746
747 if (INTCTL_GIE(pState))
748 {
749 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
750 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
751 }
752 return VINF_SUCCESS;
753}
754
755static int hdaMMIORegLookup(INTELHDLinkState* pState, uint32_t u32Offset)
756{
757 int idxMiddle;
758 int idxHigh = RT_ELEMENTS(s_ichIntelHDRegMap);
759 int idxLow = 0;
760 /* Aliases HDA spec 3.3.45 */
761 switch(u32Offset)
762 {
763 case 0x2084:
764 return HDA_REG_IND_NAME(SD0LPIB);
765 case 0x20A4:
766 return HDA_REG_IND_NAME(SD1LPIB);
767 case 0x20C4:
768 return HDA_REG_IND_NAME(SD2LPIB);
769 case 0x20E4:
770 return HDA_REG_IND_NAME(SD3LPIB);
771 case 0x2104:
772 return HDA_REG_IND_NAME(SD4LPIB);
773 case 0x2124:
774 return HDA_REG_IND_NAME(SD5LPIB);
775 case 0x2144:
776 return HDA_REG_IND_NAME(SD6LPIB);
777 case 0x2164:
778 return HDA_REG_IND_NAME(SD7LPIB);
779 }
780 while (1)
781 {
782#ifdef DEBUG_vvl
783 Assert(( idxHigh >= 0
784 && idxLow >= 0));
785#endif
786 if ( idxHigh < idxLow
787 || idxHigh < 0)
788 break;
789 idxMiddle = idxLow + (idxHigh - idxLow)/2;
790 if (u32Offset < s_ichIntelHDRegMap[idxMiddle].offset)
791 {
792 idxHigh = idxMiddle - 1;
793 continue;
794 }
795 if (u32Offset >= s_ichIntelHDRegMap[idxMiddle].offset + s_ichIntelHDRegMap[idxMiddle].size)
796 {
797 idxLow = idxMiddle + 1;
798 continue;
799 }
800 if ( u32Offset >= s_ichIntelHDRegMap[idxMiddle].offset
801 && u32Offset < s_ichIntelHDRegMap[idxMiddle].offset + s_ichIntelHDRegMap[idxMiddle].size)
802 return idxMiddle;
803 }
804 return -1;
805}
806
807static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
808{
809 int rc = VINF_SUCCESS;
810 if (fLocal)
811 {
812 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
813 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
814 if (RT_FAILURE(rc))
815 AssertRCReturn(rc, rc);
816#ifdef DEBUG_CMD_BUFFER
817 uint8_t i = 0;
818 do
819 {
820 Log(("hda: corb%02x: ", i));
821 uint8_t j = 0;
822 do
823 {
824 const char *prefix;
825 if ((i + j) == CORBRP(pState))
826 prefix = "[R]";
827 else if ((i + j) == CORBWP(pState))
828 prefix = "[W]";
829 else
830 prefix = " "; /* three spaces */
831 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
832 j++;
833 } while (j < 8);
834 Log(("\n"));
835 i += 8;
836 } while(i != 0);
837#endif
838 }
839 else
840 {
841 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
842 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
843 if (RT_FAILURE(rc))
844 AssertRCReturn(rc, rc);
845#ifdef DEBUG_CMD_BUFFER
846 uint8_t i = 0;
847 do {
848 Log(("hda: rirb%02x: ", i));
849 uint8_t j = 0;
850 do {
851 const char *prefix;
852 if ((i + j) == RIRBWP(pState))
853 prefix = "[W]";
854 else
855 prefix = " ";
856 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
857 } while (++j < 8);
858 Log(("\n"));
859 i += 8;
860 } while (i != 0);
861#endif
862 }
863 return rc;
864}
865
866static int hdaCORBCmdProcess(INTELHDLinkState *pState)
867{
868 int rc;
869 uint8_t corbRp;
870 uint8_t corbWp;
871 uint8_t rirbWp;
872
873 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
874
875 rc = hdaCmdSync(pState, true);
876 if (RT_FAILURE(rc))
877 AssertRCReturn(rc, rc);
878 corbRp = CORBRP(pState);
879 corbWp = CORBWP(pState);
880 rirbWp = RIRBWP(pState);
881 Assert((corbWp != corbRp));
882 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
883 while (corbRp != corbWp)
884 {
885 uint32_t cmd;
886 uint64_t resp;
887 pfn = (PFNCODECVERBPROCESSOR)NULL;
888 corbRp++;
889 cmd = pState->pu32CorbBuf[corbRp];
890 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
891 if (RT_FAILURE(rc))
892 AssertRCReturn(rc, rc);
893 Assert(pfn);
894 (rirbWp)++;
895
896 if (RT_LIKELY(pfn))
897 rc = pfn(&pState->Codec, cmd, &resp);
898 else
899 rc = VERR_INVALID_FUNCTION;
900
901 if (RT_FAILURE(rc))
902 AssertRCReturn(rc, rc);
903 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
904 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
905 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
906 {
907 Log(("hda: unexpected unsolicited response.\n"));
908 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
909 return rc;
910 }
911 pState->pu64RirbBuf[rirbWp] = resp;
912 pState->u8Counter++;
913 if (pState->u8Counter == RINTCNT_N(pState))
914 break;
915 }
916 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
917 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
918 rc = hdaCmdSync(pState, false);
919 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
920 if (RIRBCTL_RIRB_RIC(pState))
921 {
922 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
923 pState->u8Counter = 0;
924 rc = hdaProcessInterrupt(pState);
925 }
926 if (RT_FAILURE(rc))
927 AssertRCReturn(rc, rc);
928 return rc;
929}
930
931static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
932{
933 Log(("hda: reset of stream (%d) started\n", u8Strm));
934 Assert(( pState
935 && pBdle
936 && pStreamDesc
937 && u8Strm <= 7));
938 memset(pBdle, 0, sizeof(HDABDLEDESC));
939 *pStreamDesc->pu32Lpib = 0;
940 *pStreamDesc->pu32Sts = 0;
941 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
942 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
943 HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
944
945 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
946 HDA_STREAM_REG2(pState, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
947 HDA_STREAM_REG2(pState, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
948 HDA_STREAM_REG2(pState, CBL, u8Strm) = 0;
949 HDA_STREAM_REG2(pState, LVI, u8Strm) = 0;
950 HDA_STREAM_REG2(pState, FMT, u8Strm) = 0;
951 HDA_STREAM_REG2(pState, BDPU, u8Strm) = 0;
952 HDA_STREAM_REG2(pState, BDPL, u8Strm) = 0;
953 Log(("hda: reset of stream (%d) finished\n", u8Strm));
954}
955
956
957DECLCALLBACK(int) hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
958{
959 *pu32Value = 0;
960 return VINF_SUCCESS;
961}
962DECLCALLBACK(int) hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
963{
964 return VINF_SUCCESS;
965}
966/* U8 */
967DECLCALLBACK(int) hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
968{
969 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
970 return hdaRegReadU32(pState, offset, index, pu32Value);
971}
972
973DECLCALLBACK(int) hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
974{
975 Assert(((u32Value & 0xffffff00) == 0));
976 return hdaRegWriteU32(pState, offset, index, u32Value);
977}
978/* U16 */
979DECLCALLBACK(int) hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
980{
981 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
982 return hdaRegReadU32(pState, offset, index, pu32Value);
983}
984
985DECLCALLBACK(int) hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
986{
987 Assert(((u32Value & 0xffff0000) == 0));
988 return hdaRegWriteU32(pState, offset, index, u32Value);
989}
990
991/* U24 */
992DECLCALLBACK(int) hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
993{
994 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
995 return hdaRegReadU32(pState, offset, index, pu32Value);
996}
997
998DECLCALLBACK(int) hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
999{
1000 Assert(((u32Value & 0xff000000) == 0));
1001 return hdaRegWriteU32(pState, offset, index, u32Value);
1002}
1003/* U32 */
1004DECLCALLBACK(int) hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1005{
1006 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
1007 return VINF_SUCCESS;
1008}
1009
1010DECLCALLBACK(int) hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1011{
1012 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
1013 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
1014 return VINF_SUCCESS;
1015}
1016
1017DECLCALLBACK(int) hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1018{
1019 return hdaRegReadU32(pState, offset, index, pu32Value);
1020}
1021
1022DECLCALLBACK(int) hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1023{
1024 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1025 {
1026 /* exit reset state */
1027 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1028 pState->fInReset = false;
1029 }
1030 else
1031 {
1032 /* enter reset state*/
1033 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
1034 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
1035 {
1036 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1037 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
1038 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
1039 }
1040 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
1041 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1042 pState->fInReset = true;
1043 }
1044 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1045 {
1046 /* Flush: GSTS:1 set, see 6.2.6*/
1047 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1048 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1049 }
1050 return VINF_SUCCESS;
1051}
1052
1053DECLCALLBACK(int) hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1054{
1055 uint32_t v = pState->au32Regs[index];
1056 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
1057 pState->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
1058 return VINF_SUCCESS;
1059}
1060
1061DECLCALLBACK(int) hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1062{
1063 uint32_t v = 0;
1064 if ( RIRBSTS_RIRBOIS(pState)
1065 || RIRBSTS_RINTFL(pState)
1066 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
1067 || STATESTS(pState))
1068 v |= RT_BIT(30);
1069#define HDA_IS_STREAM_EVENT(pState, stream) \
1070 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1071 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1072 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1073#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
1074 MARK_STREAM(pState, 0, v);
1075 MARK_STREAM(pState, 1, v);
1076 MARK_STREAM(pState, 2, v);
1077 MARK_STREAM(pState, 3, v);
1078 MARK_STREAM(pState, 4, v);
1079 MARK_STREAM(pState, 5, v);
1080 MARK_STREAM(pState, 6, v);
1081 MARK_STREAM(pState, 7, v);
1082 v |= v ? RT_BIT(31) : 0;
1083 *pu32Value = v;
1084 return VINF_SUCCESS;
1085}
1086
1087DECLCALLBACK(int) hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1088{
1089 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1090 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pState)) - pState->u64BaseTS, 24, 1000);
1091 return VINF_SUCCESS;
1092}
1093
1094DECLCALLBACK(int) hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1095{
1096 return hdaRegReadU16(pState, offset, index, pu32Value);
1097}
1098
1099DECLCALLBACK(int) hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1100{
1101 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1102 CORBRP(pState) = 0;
1103 else
1104 return hdaRegWriteU8(pState, offset, index, u32Value);
1105 return VINF_SUCCESS;
1106}
1107
1108DECLCALLBACK(int) hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1109{
1110 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
1111 AssertRC(rc);
1112 if ( CORBWP(pState) != CORBRP(pState)
1113 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
1114 return hdaCORBCmdProcess(pState);
1115 return rc;
1116}
1117
1118DECLCALLBACK(int) hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1119{
1120 uint32_t v = CORBSTS(pState);
1121 CORBSTS(pState) &= ~(v & u32Value);
1122 return VINF_SUCCESS;
1123}
1124
1125DECLCALLBACK(int) hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1126{
1127 int rc;
1128 rc = hdaRegWriteU16(pState, offset, index, u32Value);
1129 if (RT_FAILURE(rc))
1130 AssertRCReturn(rc, rc);
1131 if (CORBWP(pState) == CORBRP(pState))
1132 return VINF_SUCCESS;
1133 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1134 return VINF_SUCCESS;
1135 rc = hdaCORBCmdProcess(pState);
1136 return rc;
1137}
1138
1139DECLCALLBACK(int) hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1140{
1141 return hdaRegReadU24(pState, offset, index, pu32Value);
1142}
1143
1144DECLCALLBACK(int) hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1145{
1146 bool fRun = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1147 bool fInRun = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1148 bool fReset = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1149 bool fInReset = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1150 int rc = VINF_SUCCESS;
1151 if (fInReset)
1152 {
1153 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1154 * from reset
1155 */
1156 Assert((!fReset));
1157 Log(("hda: guest initiated exit of stream reset.\n"));
1158 goto done;
1159 }
1160 else if (fReset)
1161 {
1162 /*
1163 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1164 */
1165 uint8_t u8Strm = 0;
1166 PHDABDLEDESC pBdle = NULL;
1167 HDASTREAMTRANSFERDESC stStreamDesc;
1168 Assert((!fInRun && !fRun));
1169 switch (index)
1170 {
1171 case ICH6_HDA_REG_SD0CTL:
1172 u8Strm = 0;
1173 pBdle = &pState->stInBdle;
1174 break;
1175 case ICH6_HDA_REG_SD4CTL:
1176 u8Strm = 4;
1177 pBdle = &pState->stOutBdle;
1178 break;
1179 default:
1180 Log(("hda: changing SRST bit on non-attached stream\n"));
1181 goto done;
1182 }
1183 Log(("hda: guest initiated enter to stream reset.\n"));
1184 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1185 hdaStreamReset(pState, pBdle, &stStreamDesc, u8Strm);
1186 goto done;
1187 }
1188
1189 /* we enter here to change DMA states only */
1190 if ( (fInRun && !fRun)
1191 || (fRun && !fInRun))
1192 {
1193 Assert((!fReset && !fInReset));
1194 switch (index)
1195 {
1196 case ICH6_HDA_REG_SD0CTL:
1197 AUD_set_active_in(pState->Codec.SwVoiceIn, fRun);
1198 break;
1199 case ICH6_HDA_REG_SD4CTL:
1200 AUD_set_active_out(pState->Codec.SwVoiceOut, fRun);
1201 break;
1202 default:
1203 Log(("hda: changing RUN bit on non-attached stream\n"));
1204 goto done;
1205 }
1206 }
1207
1208 done:
1209 rc = hdaRegWriteU24(pState, offset, index, u32Value);
1210 if (RT_FAILURE(rc))
1211 AssertRCReturn(rc, VINF_SUCCESS);
1212 return rc;
1213}
1214
1215DECLCALLBACK(int) hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1216{
1217 uint32_t v = HDA_REG_IND(pState, index);
1218 v &= ~(u32Value & v);
1219 HDA_REG_IND(pState, index) = v;
1220 hdaProcessInterrupt(pState);
1221 return VINF_SUCCESS;
1222}
1223
1224DECLCALLBACK(int) hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1225{
1226 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1227 if (RT_FAILURE(rc))
1228 AssertRCReturn(rc, VINF_SUCCESS);
1229 return rc;
1230}
1231
1232DECLCALLBACK(int) hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1233{
1234 switch (u32Value)
1235 {
1236 case HDA_SDFIFOW_8B:
1237 case HDA_SDFIFOW_16B:
1238 case HDA_SDFIFOW_32B:
1239 return hdaRegWriteU16(pState, offset, index, u32Value);
1240 default:
1241 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1242 return hdaRegWriteU16(pState, offset, index, HDA_SDFIFOW_32B);
1243 }
1244 return VINF_SUCCESS;
1245}
1246/*
1247 * Note this method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39)
1248 *
1249 */
1250DECLCALLBACK(int) hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1251{
1252 switch (index)
1253 {
1254 /* SDInFIFOS is RO, n=0-3 */
1255 case ICH6_HDA_REG_SD0FIFOS:
1256 case ICH6_HDA_REG_SD1FIFOS:
1257 case ICH6_HDA_REG_SD2FIFOS:
1258 case ICH6_HDA_REG_SD3FIFOS:
1259 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1260 return VINF_SUCCESS;
1261 case ICH6_HDA_REG_SD4FIFOS:
1262 case ICH6_HDA_REG_SD5FIFOS:
1263 case ICH6_HDA_REG_SD6FIFOS:
1264 case ICH6_HDA_REG_SD7FIFOS:
1265 switch(u32Value)
1266 {
1267 case HDA_SDONFIFO_16B:
1268 case HDA_SDONFIFO_32B:
1269 case HDA_SDONFIFO_64B:
1270 case HDA_SDONFIFO_128B:
1271 case HDA_SDONFIFO_192B:
1272 return hdaRegWriteU16(pState, offset, index, u32Value);
1273
1274 case HDA_SDONFIFO_256B:
1275 Log(("hda: 256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1276 default:
1277 return hdaRegWriteU16(pState, offset, index, HDA_SDONFIFO_192B);
1278 }
1279 return VINF_SUCCESS;
1280 default:
1281 AssertMsgFailed(("Something weird happened with register lookup routine"));
1282 }
1283 return VINF_SUCCESS;
1284}
1285
1286static void inline hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1287{
1288 Assert((pAudSetting));
1289#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1290 uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1291 uint32_t u32HzMult = 1;
1292 uint32_t u32HzDiv = 1;
1293 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))
1294 {
1295 case 0: u32HzMult = 1; break;
1296 case 1: u32HzMult = 2; break;
1297 case 2: u32HzMult = 3; break;
1298 case 3: u32HzMult = 4; break;
1299 default:
1300 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1301 }
1302 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))
1303 {
1304 case 0: u32HzDiv = 1; break;
1305 case 1: u32HzDiv = 2; break;
1306 case 2: u32HzDiv = 3; break;
1307 case 3: u32HzDiv = 4; break;
1308 case 4: u32HzDiv = 5; break;
1309 case 5: u32HzDiv = 6; break;
1310 case 6: u32HzDiv = 7; break;
1311 case 7: u32HzDiv = 8; break;
1312 }
1313 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1314
1315 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_BITS_MASK, ICH6_HDA_SDFMT_BITS_SHIFT))
1316 {
1317 case 0:
1318 Log(("hda: %s requested 8-bit\n", __FUNCTION__));
1319 pAudSetting->fmt = AUD_FMT_S8;
1320 break;
1321 case 1:
1322 Log(("hda: %s requested 16-bit\n", __FUNCTION__));
1323 pAudSetting->fmt = AUD_FMT_S16;
1324 break;
1325 case 2:
1326 Log(("hda: %s requested 20-bit\n", __FUNCTION__));
1327 break;
1328 case 3:
1329 Log(("hda: %s requested 24-bit\n", __FUNCTION__));
1330 break;
1331 case 4:
1332 Log(("hda: %s requested 32-bit\n", __FUNCTION__));
1333 pAudSetting->fmt = AUD_FMT_S32;
1334 break;
1335 default:
1336 AssertMsgFailed(("Unsupported"));
1337 }
1338 pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;
1339 pAudSetting->fmt = AUD_FMT_S16;
1340 pAudSetting->endianness = 0;
1341#undef EXTRACT_VALUE
1342}
1343
1344DECLCALLBACK(int) hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1345{
1346#ifdef VBOX_WITH_HDA_CODEC_EMU
1347 /* @todo a bit more investigation is required here. */
1348 int rc = 0;
1349 audsettings_t as;
1350 /* no reason to reopen voice with same settings */
1351 if (u32Value == HDA_REG_IND(pState, index))
1352 return VINF_SUCCESS;
1353 hdaSdFmtToAudSettings(u32Value, &as);
1354 switch (index)
1355 {
1356 case ICH6_HDA_REG_SD0FMT:
1357 rc = codecOpenVoice(&pState->Codec, PI_INDEX, &as);
1358 break;
1359 case ICH6_HDA_REG_SD4FMT:
1360 rc = codecOpenVoice(&pState->Codec, PO_INDEX, &as);
1361 break;
1362 default:
1363 Log(("HDA: attempt to change format on %d\n", index));
1364 rc = 0;
1365 }
1366 return hdaRegWriteU16(pState, offset, index, u32Value);
1367#else
1368 return hdaRegWriteU16(pState, offset, index, u32Value);
1369#endif
1370}
1371
1372DECLCALLBACK(int) hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1373{
1374 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1375 if (RT_FAILURE(rc))
1376 AssertRCReturn(rc, VINF_SUCCESS);
1377 return rc;
1378}
1379
1380DECLCALLBACK(int) hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1381{
1382 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1383 if (RT_FAILURE(rc))
1384 AssertRCReturn(rc, VINF_SUCCESS);
1385 return rc;
1386}
1387
1388DECLCALLBACK(int) hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1389{
1390 int rc = VINF_SUCCESS;
1391 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1392 if ( CORBWP(pState) != CORBRP(pState)
1393 || HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1394 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1395
1396 rc = hdaRegReadU32(pState, offset, index, pu32Value);
1397 return rc;
1398}
1399
1400DECLCALLBACK(int) hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1401{
1402 int rc = VINF_SUCCESS;
1403 uint64_t resp;
1404 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1405 /*
1406 * if guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1407 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1408 */
1409 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1410 && !IRS_ICB(pState))
1411 {
1412 uint32_t cmd = IC(pState);
1413 if (CORBWP(pState) != CORBRP(pState))
1414 {
1415 /*
1416 * 3.4.3 defines behavior of immediate Command status register.
1417 */
1418 LogRel(("hda: guest attempted process immediate verb (%x) with active CORB\n", cmd));
1419 return rc;
1420 }
1421 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1422 Log(("hda: IC:%x\n", cmd));
1423 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1424 if (RT_FAILURE(rc))
1425 AssertRCReturn(rc, rc);
1426 rc = pfn(&pState->Codec, cmd, &resp);
1427 if (RT_FAILURE(rc))
1428 AssertRCReturn(rc, rc);
1429 IR(pState) = (uint32_t)resp;
1430 Log(("hda: IR:%x\n", IR(pState)));
1431 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1432 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1433 return rc;
1434 }
1435 /*
1436 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1437 */
1438 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1439 && IRS_IRV(pState))
1440 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1441 return rc;
1442}
1443
1444DECLCALLBACK(int) hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1445{
1446 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1447 {
1448 RIRBWP(pState) = 0;
1449 }
1450 /* The remaining bits are O, see 6.2.22 */
1451 return VINF_SUCCESS;
1452}
1453
1454DECLCALLBACK(int) hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1455{
1456 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1457 if (RT_FAILURE(rc))
1458 AssertRCReturn(rc, rc);
1459 switch(index)
1460 {
1461 case ICH6_HDA_REG_CORBLBASE:
1462 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1463 pState->u64CORBBase |= pState->au32Regs[index];
1464 break;
1465 case ICH6_HDA_REG_CORBUBASE:
1466 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1467 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1468 break;
1469 case ICH6_HDA_REG_RIRLBASE:
1470 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1471 pState->u64RIRBBase |= pState->au32Regs[index];
1472 break;
1473 case ICH6_HDA_REG_RIRUBASE:
1474 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1475 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1476 break;
1477 case ICH6_HDA_REG_DPLBASE:
1478 /* @todo: first bit has special meaning */
1479 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1480 pState->u64DPBase |= pState->au32Regs[index];
1481 break;
1482 case ICH6_HDA_REG_DPUBASE:
1483 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1484 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1485 break;
1486 default:
1487 AssertMsgFailed(("Invalid index"));
1488 }
1489 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1490 return rc;
1491}
1492
1493DECLCALLBACK(int) hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1494{
1495 uint8_t v = RIRBSTS(pState);
1496 RIRBSTS(pState) &= ~(v & u32Value);
1497
1498 return hdaProcessInterrupt(pState);
1499}
1500
1501#ifdef LOG_ENABLED
1502static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1503{
1504#if 0
1505 uint64_t addr;
1506 uint32_t len;
1507 uint32_t ioc;
1508 uint8_t bdle[16];
1509 uint32_t counter;
1510 uint32_t i;
1511 uint32_t sum = 0;
1512 Assert(pBdle && pBdle->u32BdleMaxCvi);
1513 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1514 {
1515 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1516 addr = *(uint64_t *)bdle;
1517 len = *(uint32_t *)&bdle[8];
1518 ioc = *(uint32_t *)&bdle[12];
1519 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1520 sum += len;
1521 }
1522 Log(("hda: sum: %d\n", sum));
1523 for (i = 0; i < 8; ++i)
1524 {
1525 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1526 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
1527 i , counter));
1528 }
1529#endif
1530}
1531#endif
1532
1533static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1534{
1535 uint8_t bdle[16];
1536 Assert(( pStreamDesc->u64BaseDMA
1537 && pBdle
1538 && pBdle->u32BdleMaxCvi));
1539 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1540 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1541 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1542 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1543#ifdef LOG_ENABLED
1544 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1545#endif
1546}
1547
1548static inline uint32_t hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1549{
1550 uint32_t cb2Copy;
1551 /*
1552 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
1553 */
1554 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1555 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1556 /*
1557 * we may increase the counter in range of [0, FIFOS + 1]
1558 */
1559 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1560 Assert((u32SoundBackendBufferBytesAvail > 0));
1561
1562 /* sanity check to avoid overriding the backend audio buffer */
1563 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1564 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1565
1566 if (cb2Copy <= pBdle->cbUnderFifoW)
1567 return 0;
1568 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
1569 return cb2Copy;
1570}
1571
1572DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1573{
1574 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1575 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1576 Assert((cbCopied));
1577 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1578 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
1579 * Probably we need to move the buffer, but it is rather hard to imagine a situation
1580 * where it might happen.
1581 */
1582 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write the entire buffer including unreported bytes */
1583 if ( pBdle->cbUnderFifoW
1584 && pBdle->cbUnderFifoW <= cbCopied)
1585 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1586
1587 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1588 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
1589
1590 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
1591 pBdle->u32BdleCviPos += cbArranged2Copy;
1592
1593 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1594 /* We report all bytes (including previously unreported bytes) */
1595 *pu32DMACursor += cbCopied;
1596 /* Decrease the backend counter by the number of bytes we copied to the backend */
1597 *pu32BackendBufferCapacity -= cbCopied;
1598 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1599 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1600}
1601
1602DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1603{
1604 Assert((cbCopied, cbArranged2Copy));
1605 *pu32BackendBufferCapacity -= cbCopied;
1606 pBdle->u32BdleCviPos += cbCopied;
1607 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1608 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1609 pBdle->cbUnderFifoW = 0;
1610 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1611 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1612}
1613
1614DECLINLINE(void) hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1615{
1616 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1617 pBdle->u32BdleCviPos += cbCopied;
1618 pBdle->cbUnderFifoW += cbCopied;
1619 /* In case of a read transaction we're always copying from the backend buffer */
1620 if (pu32BackendBufferCapacity)
1621 *pu32BackendBufferCapacity -= cbCopied;
1622 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1623 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pState, pStreamDesc)));
1624}
1625static inline bool hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1626{
1627 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1628 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1629
1630 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1631
1632 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1633 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1634 hdaUpdatePosBuf(pState, pStreamDesc);
1635
1636 /* don't touch BdleCvi counter on uninitialized descriptor */
1637 if ( pBdle->u32BdleCviPos
1638 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1639 {
1640 pBdle->u32BdleCviPos = 0;
1641 pBdle->u32BdleCvi++;
1642 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1643 pBdle->u32BdleCvi = 0;
1644 }
1645 return fOnBufferEdge;
1646}
1647
1648DECLINLINE(void) hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbInc)
1649{
1650 /*
1651 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
1652 * (ICH6 datasheet 18.2.38)
1653 */
1654 if (!pBdle->cbUnderFifoW)
1655 {
1656 *pStreamDesc->pu32Lpib += cbInc;
1657
1658 /*
1659 * Assert. The buffer counters should never overlap.
1660 */
1661 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1662
1663 hdaUpdatePosBuf(pState, pStreamDesc);
1664
1665 }
1666}
1667
1668static inline bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1669{
1670 bool fDoNextTransferLoop = true;
1671 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1672 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1673 {
1674 if ( !pBdle->cbUnderFifoW
1675 && pBdle->fBdleCviIoc)
1676 {
1677 /*
1678 * @todo - more carefully investigate BCIS flag.
1679 * Speech synthesis works fine on Mac Guest if this bit isn't set
1680 * but in general sound quality gets worse.
1681 */
1682 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1683
1684 /*
1685 * we should generate the interrupt if ICE bit of SDCTL register is set.
1686 */
1687 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1688 hdaProcessInterrupt(pState);
1689 }
1690 fDoNextTransferLoop = false;
1691 }
1692 return fDoNextTransferLoop;
1693}
1694
1695/*
1696 * hdaReadAudio - copies samples from audio backend to DMA.
1697 * Note: this function writes to the DMA buffer immediately, but "reports bytes" when all conditions are met (FIFOW)
1698 */
1699static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1700{
1701 PHDABDLEDESC pBdle = &pState->stInBdle;
1702 uint32_t cbTransferred = 0;
1703 uint32_t cb2Copy = 0;
1704 uint32_t cbBackendCopy = 0;
1705
1706 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1707
1708 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1709 if (!cb2Copy)
1710 {
1711 /* if we enter here we can't report "unreported bits" */
1712 *fStop = true;
1713 goto done;
1714 }
1715
1716
1717 /*
1718 * read from backend input line to the last unreported position or at the begining.
1719 */
1720 cbBackendCopy = AUD_read (pState->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1721 /*
1722 * write the HDA DMA buffer
1723 */
1724 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1725
1726 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
1727 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1728
1729 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pState, 0))
1730 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1731 else
1732 {
1733 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1734 *fStop = true;
1735 }
1736 done:
1737 Assert((cbTransferred <= (SDFIFOS(pState, 0) + 1)));
1738 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1739 return cbTransferred;
1740}
1741
1742static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1743{
1744 PHDABDLEDESC pBdle = &pState->stOutBdle;
1745 uint32_t cbTransferred = 0;
1746 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1747 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1748
1749 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1750
1751 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1752
1753 /*
1754 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the previous unreported transfer we write at offset ''pBdle->cbUnderFifoW'')
1755 */
1756 if (!cb2Copy)
1757 {
1758 *fStop = true;
1759 goto done;
1760 }
1761
1762 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1763 /*
1764 * Write to audio backend. we should ensure that we have enough bytes to copy to the backend.
1765 */
1766 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, pStreamDesc))
1767 {
1768 /*
1769 * Feed the newly fetched samples, including unreported ones, to the backend.
1770 */
1771 cbBackendCopy = AUD_write (pState->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1772 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1773 }
1774 else
1775 {
1776 /* Not enough bytes to be processed and reported, we'll try our luck next time around */
1777 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cb2Copy, NULL);
1778 *fStop = true;
1779 }
1780
1781 done:
1782 Assert((cbTransferred <= (SDFIFOS(pState, 4) + 1)));
1783 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransferred:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1784 return cbTransferred;
1785}
1786
1787DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1788{
1789 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1790 return VINF_SUCCESS;
1791}
1792
1793DECLINLINE(void) hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc)
1794{
1795 Assert(( pState
1796 && pBdle
1797 && pStreamDesc
1798 && u8Strm <= 7));
1799 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1800 pStreamDesc->u8Strm = u8Strm;
1801 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pState, CTL, u8Strm);
1802 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pState, BDPL, u8Strm),
1803 HDA_STREAM_REG2(pState, BDPU, u8Strm));
1804 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pState, LPIB, u8Strm);
1805 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pState, STS, u8Strm);
1806 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pState, CBL, u8Strm);
1807 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pState, FIFOS, u8Strm);
1808
1809 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pState, LVI, u8Strm);
1810#ifdef LOG_ENABLED
1811 if ( pBdle
1812 && pBdle->u32BdleMaxCvi)
1813 {
1814 Log(("Initialization of transfer descriptor:\n"));
1815 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1816 }
1817#endif
1818}
1819
1820DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1821{
1822 bool fStop = false;
1823 uint8_t u8Strm = 0;
1824 PHDABDLEDESC pBdle = NULL;
1825 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1826 HDASTREAMTRANSFERDESC stStreamDesc;
1827 uint32_t nBytes;
1828 switch (src)
1829 {
1830 case PO_INDEX:
1831 {
1832 u8Strm = 4;
1833 pBdle = &pState->stOutBdle;
1834 break;
1835 }
1836 case PI_INDEX:
1837 {
1838 u8Strm = 0;
1839 pBdle = &pState->stInBdle;
1840 break;
1841 }
1842 default:
1843 return;
1844 }
1845 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1846 while( avail && !fStop)
1847 {
1848 Assert ( (stStreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1849 && avail
1850 && stStreamDesc.u64BaseDMA);
1851
1852 /* Fetch the Buffer Descriptor Entry (BDE). */
1853
1854 if (hdaIsTransferCountersOverlapped(pState, pBdle, &stStreamDesc))
1855 hdaFetchBdle(pState, pBdle, &stStreamDesc);
1856 *stStreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1857 Assert((avail >= 0 && (stStreamDesc.u32Cbl >= (*stStreamDesc.pu32Lpib)))); /* sanity */
1858 uint32_t u32CblLimit = stStreamDesc.u32Cbl - (*stStreamDesc.pu32Lpib);
1859 Assert((u32CblLimit > hdaFifoWToSz(pState, &stStreamDesc)));
1860 Log(("hda: CBL=%d, LPIB=%d\n", stStreamDesc.u32Cbl, *stStreamDesc.pu32Lpib));
1861 switch (src)
1862 {
1863 case PO_INDEX:
1864 nBytes = hdaWriteAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1865 break;
1866 case PI_INDEX:
1867 nBytes = hdaReadAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1868 break;
1869 default:
1870 nBytes = 0;
1871 fStop = true;
1872 AssertMsgFailed(("Unsupported"));
1873 }
1874 Assert(nBytes <= (stStreamDesc.u32Fifos + 1));
1875 *stStreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1876
1877 /* Process end of buffer condition. */
1878 hdaStreamCounterUpdate(pState, pBdle, &stStreamDesc, nBytes);
1879 fStop = !fStop ? !hdaDoNextTransferCycle(pState, pBdle, &stStreamDesc) : fStop;
1880 }
1881}
1882
1883/**
1884 * Handle register read operation.
1885 *
1886 * Looks up and calls the appropriate handler.
1887 *
1888 * @note: During implementation, we discovered so-called "forgotten" or "hole" registers
1889 * whose description is not listed in the RPM, datasheet, or spec.
1890 *
1891 * @returns VBox status code.
1892 *
1893 * @param pState The device state structure.
1894 * @param uOffset Register offset in memory-mapped area.
1895 * @param pv Where to place the value.
1896 * @param cb Number of bytes to write.
1897 * @thread EMT
1898 */
1899PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1900{
1901 int rc = VINF_SUCCESS;
1902 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1903 uint32_t offReg = GCPhysAddr - pThis->hda.addrMMReg;
1904 int idxReg = hdaMMIORegLookup(&pThis->hda, offReg);
1905 if (pThis->hda.fInReset && idxReg != ICH6_HDA_REG_GCTL)
1906 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1907
1908 if (idxReg == -1)
1909 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
1910
1911 if (idxReg != -1)
1912 {
1913 /** @todo r=bird: Accesses crossing register boundraries aren't handled
1914 * right from what I can tell? If they are, please explain
1915 * what the rules are. */
1916 uint32_t mask = 0;
1917 uint32_t shift = (s_ichIntelHDRegMap[idxReg].offset - offReg) % sizeof(uint32_t) * 8;
1918 uint32_t u32Value = 0;
1919 switch(cb)
1920 {
1921 case 1: mask = 0x000000ff; break;
1922 case 2: mask = 0x0000ffff; break;
1923 case 4:
1924 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
1925 case 8:
1926 mask = 0xffffffff;
1927 cb = 4;
1928 break;
1929 }
1930#if 0
1931 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
1932 */
1933 //Assert((cb <= s_ichIntelHDRegMap[idxReg].size - (offReg - s_ichIntelHDRegMap[idxReg].offset)));
1934 if (cb > s_ichIntelHDRegMap[idxReg].size - (offReg - s_ichIntelHDRegMap[idxReg].offset))
1935 {
1936 int off = cb - (s_ichIntelHDRegMap[idxReg].size - (offReg - s_ichIntelHDRegMap[idxReg].offset));
1937 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
1938 if (RT_FAILURE(rc))
1939 AssertRCReturn (rc, rc);
1940 }
1941 //Assert(((offReg - s_ichIntelHDRegMap[idxReg].offset) == 0));
1942#endif
1943 mask <<= shift;
1944 rc = s_ichIntelHDRegMap[idxReg].pfnRead(&pThis->hda, offReg, idxReg, &u32Value);
1945 *(uint32_t *)pv |= (u32Value & mask);
1946 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[idxReg].abbrev, u32Value, *(uint32_t *)pv));
1947 return rc;
1948 }
1949 *(uint32_t *)pv = 0xFF;
1950 Log(("hda: hole at %x is accessed for read\n", offReg));
1951 return rc;
1952}
1953
1954/**
1955 * Handle register write operation.
1956 *
1957 * Looks up and calls the appropriate handler.
1958 *
1959 * @returns VBox status code.
1960 *
1961 * @param pState The device state structure.
1962 * @param uOffset Register offset in memory-mapped area.
1963 * @param pv Where to fetch the value.
1964 * @param cb Number of bytes to write.
1965 * @thread EMT
1966 */
1967PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1968{
1969 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1970 uint32_t offReg = GCPhysAddr - pThis->hda.addrMMReg;
1971 int idxReg = hdaMMIORegLookup(&pThis->hda, offReg);
1972 int rc = VINF_SUCCESS;
1973
1974 if (pThis->hda.fInReset && idxReg != ICH6_HDA_REG_GCTL)
1975 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1976
1977 if ( idxReg == -1
1978 || cb > 4)
1979 LogRel(("hda: Invalid write access @0x%x(of bytes:%d)\n", offReg, cb));
1980
1981 if (idxReg != -1)
1982 {
1983 /** @todo r=bird: This looks like code for handling unaligned register
1984 * accesses. If it isn't, then add a comment explaining what you're
1985 * trying to do here. OTOH, if it is then it has the following
1986 * issues:
1987 * -# You're calculating the wrong new value for the register.
1988 * -# You're not handling cross register accesses. Imagine a
1989 * 4-byte write starting at CORBCTL, or a 8-byte write.
1990 *
1991 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
1992 * nobody seems to be using it and it just adds complexity when reading
1993 * the code.
1994 *
1995 */
1996 uint32_t u32CurValue = pThis->hda.au32Regs[idxReg];
1997 uint32_t u32NewValue;
1998 uint32_t mask;
1999 switch (cb)
2000 {
2001 case 1:
2002 u32NewValue = *(uint8_t const *)pv;
2003 mask = 0xff;
2004 break;
2005 case 2:
2006 u32NewValue = *(uint16_t const *)pv;
2007 mask = 0xffff;
2008 break;
2009 case 4:
2010 case 8:
2011 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2012 u32NewValue = *(uint32_t const *)pv;
2013 mask = 0xffffffff;
2014 cb = 4;
2015 break;
2016 default:
2017 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
2018 }
2019 /* cross-register access, see corresponding comment in hdaMMIORead */
2020#if 0
2021 if (cb > s_ichIntelHDRegMap[idxReg].size - (offReg - s_ichIntelHDRegMap[idxReg].offset))
2022 {
2023 int off = cb - (s_ichIntelHDRegMap[idxReg].size - (offReg - s_ichIntelHDRegMap[idxReg].offset));
2024 rc = hdaMMIOWrite(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2025 if (RT_FAILURE(rc))
2026 AssertRCReturn (rc, rc);
2027 }
2028#endif
2029 uint32_t shift = (s_ichIntelHDRegMap[idxReg].offset - offReg) % sizeof(uint32_t) * 8;
2030 mask <<= shift;
2031 u32NewValue <<= shift;
2032 u32NewValue &= mask;
2033 u32NewValue |= (u32CurValue & ~mask);
2034
2035 rc = s_ichIntelHDRegMap[idxReg].pfnWrite(&pThis->hda, offReg, idxReg, u32NewValue);
2036 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[idxReg].abbrev, u32NewValue,
2037 u32CurValue, pThis->hda.au32Regs[idxReg]));
2038 return rc;
2039 }
2040
2041 Log(("hda: hole at %x is accessed for write\n", offReg));
2042 return rc;
2043}
2044
2045/**
2046 * Callback function for mapping a PCI I/O region.
2047 *
2048 * @return VBox status code.
2049 * @param pPciDev Pointer to PCI device.
2050 * Use pPciDev->pDevIns to get the device instance.
2051 * @param iRegion The region number.
2052 * @param GCPhysAddress Physical address of the region.
2053 * If iType is PCI_ADDRESS_SPACE_IO, this is an
2054 * I/O port, else it's a physical address.
2055 * This address is *NOT* relative
2056 * to pci_mem_base like earlier!
2057 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
2058 */
2059static DECLCALLBACK(int) hdaMap(PPCIDEVICE pPciDev, int iRegion,
2060 RTGCPHYS GCPhysAddress, uint32_t cb,
2061 PCIADDRESSSPACE enmType)
2062{
2063 int rc;
2064 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2065 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
2066 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
2067
2068 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2069 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2070 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
2071 hdaMMIOWrite, hdaMMIORead, "ICH6_HDA");
2072
2073 if (RT_FAILURE(rc))
2074 return rc;
2075
2076 pThis->hda.addrMMReg = GCPhysAddress;
2077 return VINF_SUCCESS;
2078}
2079
2080/**
2081 * Saves the state of the HDA device.
2082 *
2083 * @returns VBox status code.
2084 * @param pDevIns The device instance.
2085 * @param pSSM The handle to save the state to.
2086 */
2087static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2088{
2089 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2090 /* Save Codec nodes states */
2091 codecSaveState(&pThis->hda.Codec, pSSM);
2092
2093 /* Save MMIO registers */
2094 AssertCompile(RT_ELEMENTS(pThis->hda.au32Regs) == 112);
2095 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->hda.au32Regs));
2096 SSMR3PutMem(pSSM, pThis->hda.au32Regs, sizeof(pThis->hda.au32Regs));
2097
2098 /* Save HDA dma counters */
2099 SSMR3PutStructEx(pSSM, &pThis->hda.stOutBdle, sizeof(pThis->hda.stOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2100 SSMR3PutStructEx(pSSM, &pThis->hda.stMicBdle, sizeof(pThis->hda.stMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2101 SSMR3PutStructEx(pSSM, &pThis->hda.stInBdle, sizeof(pThis->hda.stInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2102 return VINF_SUCCESS;
2103}
2104
2105/**
2106 * Loads a saved HDA device state.
2107 *
2108 * @returns VBox status code.
2109 * @param pDevIns The device instance.
2110 * @param pSSM The handle to the saved state.
2111 * @param uVersion The data unit version number.
2112 * @param uPass The data pass.
2113 */
2114static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2115{
2116 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2117
2118 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2119
2120 /*
2121 * Load Codec nodes states.
2122 */
2123 int rc = codecLoadState(&pThis->hda.Codec, pSSM, uVersion);
2124 if (RT_FAILURE(rc))
2125 return rc;
2126
2127 /*
2128 * Load MMIO registers.
2129 */
2130 uint32_t cRegs;
2131 switch (uVersion)
2132 {
2133 case HDA_SSM_VERSION_1:
2134 /* Starting with r71199, we would save 112 instead of 113
2135 registers due to some code cleanups. This only affected trunk
2136 builds in the 4.1 development period. */
2137 cRegs = 113;
2138 if (SSMR3HandleRevision(pSSM) >= 71199)
2139 {
2140 uint32_t uVer = SSMR3HandleVersion(pSSM);
2141 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
2142 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
2143 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
2144 cRegs = 112;
2145 }
2146 break;
2147
2148 case HDA_SSM_VERSION_2:
2149 case HDA_SSM_VERSION_3:
2150 cRegs = 112;
2151 AssertCompile(RT_ELEMENTS(pThis->hda.au32Regs) == 112);
2152 break;
2153
2154 case HDA_SSM_VERSION:
2155 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
2156 AssertLogRelMsgReturn(cRegs == RT_ELEMENTS(pThis->hda.au32Regs),
2157 ("cRegs is %d, expected %d\n", cRegs, RT_ELEMENTS(pThis->hda.au32Regs)),
2158 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2159 break;
2160
2161 default:
2162 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2163 }
2164
2165 if (cRegs >= RT_ELEMENTS(pThis->hda.au32Regs))
2166 {
2167 SSMR3GetMem(pSSM, pThis->hda.au32Regs, sizeof(pThis->hda.au32Regs));
2168 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->hda.au32Regs)));
2169 }
2170 else
2171 {
2172 RT_ZERO(pThis->hda.au32Regs);
2173 SSMR3GetMem(pSSM, pThis->hda.au32Regs, sizeof(uint32_t) * cRegs);
2174 }
2175
2176 /*
2177 * Load HDA dma counters.
2178 */
2179 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
2180 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
2181 SSMR3GetStructEx(pSSM, &pThis->hda.stOutBdle, sizeof(pThis->hda.stOutBdle), fFlags, paFields, NULL);
2182 SSMR3GetStructEx(pSSM, &pThis->hda.stMicBdle, sizeof(pThis->hda.stMicBdle), fFlags, paFields, NULL);
2183 rc = SSMR3GetStructEx(pSSM, &pThis->hda.stInBdle, sizeof(pThis->hda.stInBdle), fFlags, paFields, NULL);
2184 AssertRCReturn(rc, rc);
2185
2186 /*
2187 * Update stuff after the state changes.
2188 */
2189 AUD_set_active_in(pThis->hda.Codec.SwVoiceIn, SDCTL(&pThis->hda, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2190 AUD_set_active_out(pThis->hda.Codec.SwVoiceOut, SDCTL(&pThis->hda, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2191
2192 pThis->hda.u64CORBBase = RT_MAKE_U64(CORBLBASE(&pThis->hda), CORBUBASE(&pThis->hda));
2193 pThis->hda.u64RIRBBase = RT_MAKE_U64(RIRLBASE(&pThis->hda), RIRUBASE(&pThis->hda));
2194 pThis->hda.u64DPBase = RT_MAKE_U64(DPLBASE(&pThis->hda), DPUBASE(&pThis->hda));
2195 return VINF_SUCCESS;
2196}
2197
2198/**
2199 * Reset notification.
2200 *
2201 * @returns VBox status.
2202 * @param pDevIns The device instance data.
2203 *
2204 * @remark The original sources didn't install a reset handler, but it seems to
2205 * make sense to me so we'll do it.
2206 */
2207static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
2208{
2209 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2210 GCAP(&pThis->hda) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
2211 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
2212 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2213 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2214 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
2215 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
2216 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
2217 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
2218 CORBRP(&pThis->hda) = 0x0;
2219 RIRBWP(&pThis->hda) = 0x0;
2220
2221 Log(("hda: inter HDA reset.\n"));
2222 pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
2223
2224 if (pThis->hda.pu32CorbBuf)
2225 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
2226 else
2227 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
2228
2229 pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
2230 if (pThis->hda.pu64RirbBuf)
2231 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
2232 else
2233 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
2234
2235 pThis->hda.u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2236
2237 HDABDLEDESC stEmptyBdle;
2238 for(uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2239 {
2240 HDASTREAMTRANSFERDESC stStreamDesc;
2241 PHDABDLEDESC pBdle = NULL;
2242 if (u8Strm == 0)
2243 pBdle = &pThis->hda.stInBdle;
2244 else if(u8Strm == 4)
2245 pBdle = &pThis->hda.stOutBdle;
2246 else
2247 {
2248 memset(&stEmptyBdle, 0, sizeof(HDABDLEDESC));
2249 pBdle = &stEmptyBdle;
2250 }
2251 hdaInitTransferDescriptor(&pThis->hda, pBdle, u8Strm, &stStreamDesc);
2252 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
2253 HDA_STREAM_REG2(&pThis->hda, CTL, u8Strm) = 0;
2254 hdaStreamReset(&pThis->hda, pBdle, &stStreamDesc, u8Strm);
2255 }
2256
2257 /* emulation of codec "wake up" (HDA spec 5.5.1 and 6.5)*/
2258 STATESTS(&pThis->hda) = 0x1;
2259
2260 Log(("hda: reset finished\n"));
2261}
2262
2263/**
2264 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2265 */
2266static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
2267 const char *pszIID)
2268{
2269 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
2270 Assert(&pThis->hda.IBase == pInterface);
2271
2272 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
2273 return NULL;
2274}
2275
2276DECLINLINE(int) hdaLookUpRegisterByName(INTELHDLinkState *pState, const char *pszArgs)
2277{
2278 int iReg = 0;
2279 for (; iReg < HDA_NREGS; ++iReg)
2280 if (!RTStrICmp(s_ichIntelHDRegMap[iReg].abbrev, pszArgs))
2281 return iReg;
2282 return -1;
2283}
2284DECLINLINE(void) hdaDbgPrintRegister(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaIndex)
2285{
2286 Assert( pState
2287 && iHdaIndex >= 0
2288 && iHdaIndex < HDA_NREGS);
2289 pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", s_ichIntelHDRegMap[iHdaIndex].abbrev, pState->au32Regs[iHdaIndex]);
2290}
2291static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2292{
2293 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2294 INTELHDLinkState *hda = &pThis->hda;
2295 int iHdaRegisterIndex = hdaLookUpRegisterByName(hda, pszArgs);
2296 if (iHdaRegisterIndex != -1)
2297 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2298 else
2299 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
2300 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2301}
2302
2303DECLINLINE(void) hdaDbgPrintStream(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
2304{
2305 Assert( pState
2306 && iHdaStrmIndex >= 0
2307 && iHdaStrmIndex < 7);
2308 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
2309 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, CTL, iHdaStrmIndex));
2310 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, STS, iHdaStrmIndex));
2311 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOS, iHdaStrmIndex));
2312 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOW, iHdaStrmIndex));
2313}
2314
2315DECLINLINE(int) hdaLookUpStreamIndex(INTELHDLinkState *pState, const char *pszArgs)
2316{
2317 /* todo: add args parsing */
2318 return -1;
2319}
2320static DECLCALLBACK(void) hdaDbgStreamInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2321{
2322 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2323 INTELHDLinkState *hda = &pThis->hda;
2324 int iHdaStrmIndex = hdaLookUpStreamIndex(hda, pszArgs);
2325 if (iHdaStrmIndex != -1)
2326 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2327 else
2328 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
2329 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2330}
2331
2332/* Codec debugger interface */
2333static DECLCALLBACK(void) hdaCodecDbgNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2334{
2335 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2336 INTELHDLinkState *hda = &pThis->hda;
2337 if (hda->Codec.pfnCodecDbgListNodes)
2338 hda->Codec.pfnCodecDbgListNodes(&hda->Codec, pHlp, pszArgs);
2339 else
2340 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2341}
2342
2343static DECLCALLBACK(void) hdaCodecDbgSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2344{
2345 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2346 INTELHDLinkState *hda = &pThis->hda;
2347 if (hda->Codec.pfnCodecDbgSelector)
2348 hda->Codec.pfnCodecDbgSelector(&hda->Codec, pHlp, pszArgs);
2349 else
2350 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2351}
2352
2353//#define HDA_AS_PCI_EXPRESS
2354/* Misc routines */
2355static inline bool printHdaIsValid(const char *pszType, const char *pszExpectedFlag)
2356{
2357 return (RTStrCmp(pszType, pszExpectedFlag) == 0);
2358}
2359static const char *printHdaYesNo(bool fFlag)
2360{
2361 return fFlag ? "yes" : "no";
2362}
2363static DECLCALLBACK(size_t)
2364printHdaStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2365 const char *pszType, void const *pvValue,
2366 int cchWidth, int cchPrecision, unsigned fFlags,
2367 void *pvUser)
2368{
2369 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
2370 size_t cb = 0;
2371 if (!printHdaIsValid(pszType, "sdctl"))
2372 return cb;
2373 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2374 "SDCTL(raw: %#0x, strm:0x%x, dir:%s, tp:%s strip:%x, deie:%s, ioce:%s, run:%s, srst:%s)",
2375 sdCtl,
2376 ((sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> ICH6_HDA_SDCTL_NUM_SHIFT),
2377 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR))),
2378 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP))),
2379 ((sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> ICH6_HDA_SDCTL_STRIPE_SHIFT),
2380 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE))),
2381 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))),
2382 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))),
2383 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST))));
2384 return cb;
2385}
2386
2387static DECLCALLBACK(size_t)
2388printHdaStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2389 const char *pszType, void const *pvValue,
2390 int cchWidth, int cchPrecision, unsigned fFlags,
2391 void *pvUser)
2392{
2393 uint32_t sdFifos = (uint32_t)(uintptr_t)pvValue;
2394 uint32_t u32Bytes = 0;
2395 size_t cb = 0;
2396 if (!printHdaIsValid(pszType, "sdfifos"))
2397 return cb;
2398 switch(sdFifos)
2399 {
2400 case HDA_SDONFIFO_16B: u32Bytes = 16; break;
2401 case HDA_SDONFIFO_32B: u32Bytes = 32; break;
2402 case HDA_SDONFIFO_64B: u32Bytes = 64; break;
2403 case HDA_SDONFIFO_128B: u32Bytes = 128; break;
2404 case HDA_SDONFIFO_192B: u32Bytes = 192; break;
2405 case HDA_SDONFIFO_256B: u32Bytes = 256; break;
2406 case HDA_SDINFIFO_120B: u32Bytes = 120; break;
2407 case HDA_SDINFIFO_160B: u32Bytes = 160; break;
2408 default:;
2409 }
2410 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2411 "SDFIFOS(raw: %#0x, sdfifos:%d B)",
2412 sdFifos,
2413 u32Bytes);
2414 return cb;
2415}
2416
2417static DECLCALLBACK(size_t)
2418printHdaStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2419 const char *pszType, void const *pvValue,
2420 int cchWidth, int cchPrecision, unsigned fFlags,
2421 void *pvUser)
2422{
2423 uint32_t sdFifow = (uint32_t)(uintptr_t)pvValue;
2424 uint32_t u32Bytes = 0;
2425 size_t cb = 0;
2426 if (!printHdaIsValid(pszType, "sdfifow"))
2427 return cb;
2428 switch(sdFifow)
2429 {
2430 case HDA_SDFIFOW_8B: u32Bytes = 8; break;
2431 case HDA_SDFIFOW_16B: u32Bytes = 16; break;
2432 case HDA_SDFIFOW_32B: u32Bytes = 32; break;
2433 }
2434 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2435 "SDFIFOW(raw: %#0x, sdfifow:%d B)",
2436 sdFifow,
2437 u32Bytes);
2438 return cb;
2439}
2440
2441static DECLCALLBACK(size_t)
2442printHdaStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2443 const char *pszType, void const *pvValue,
2444 int cchWidth, int cchPrecision, unsigned fFlags,
2445 void *pvUser)
2446{
2447 uint32_t sdSts = (uint32_t)(uintptr_t)pvValue;
2448 size_t cb = 0;
2449 if (!printHdaIsValid(pszType, "sdsts"))
2450 return cb;
2451 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2452 "SDSTS(raw: %#0x, fifordy:%s, dese:%s, fifoe:%s, bcis:%s)",
2453 sdSts,
2454 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY))),
2455 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE))),
2456 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE))),
2457 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))));
2458 return cb;
2459}
2460/**
2461 * This routine registers debugger info extensions and custom printf formatters
2462 */
2463DECLINLINE(int) hdaInitMisc(PPDMDEVINS pDevIns)
2464{
2465 int rc;
2466 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
2467 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgStreamInfo);
2468 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaCodecDbgNodes);
2469 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaCodecDbgSelector);
2470 rc = RTStrFormatTypeRegister("sdctl", printHdaStrmCtl, NULL);
2471 AssertRC(rc);
2472 rc = RTStrFormatTypeRegister("sdsts", printHdaStrmSts, NULL);
2473 AssertRC(rc);
2474 rc = RTStrFormatTypeRegister("sdfifos", printHdaStrmFifos, NULL);
2475 AssertRC(rc);
2476 rc = RTStrFormatTypeRegister("sdfifow", printHdaStrmFifow, NULL);
2477 AssertRC(rc);
2478#if 0
2479 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
2480 AssertRC(rc);
2481#endif
2482 return rc;
2483}
2484
2485/**
2486 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2487 */
2488static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
2489 PCFGMNODE pCfgHandle)
2490{
2491 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2492 INTELHDLinkState *s = &pThis->hda;
2493 int rc;
2494
2495 Assert(iInstance == 0);
2496 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2497
2498 /*
2499 * Validations.
2500 */
2501 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
2502 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2503 N_ ("Invalid configuration for the Intel HDA device"));
2504
2505 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
2506 // poll some register(s).
2507
2508 /*
2509 * Initialize data (most of it anyway).
2510 */
2511 s->pDevIns = pDevIns;
2512 /* IBase */
2513 s->IBase.pfnQueryInterface = hdaQueryInterface;
2514
2515 /* PCI Device */
2516 PCIDevSetVendorId (&pThis->dev, HDA_PCI_VENDOR_ID); /* nVidia */
2517 PCIDevSetDeviceId (&pThis->dev, HDA_PCI_DEICE_ID); /* HDA */
2518
2519 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
2520 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2521 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
2522 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
2523 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
2524 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2525 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
2526 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
2527 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2528 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
2529 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */
2530
2531#if defined(HDA_AS_PCI_EXPRESS)
2532 PCIDevSetCapabilityList (&pThis->dev, 0x80);
2533#elif defined(VBOX_WITH_MSI_DEVICES)
2534 PCIDevSetCapabilityList (&pThis->dev, 0x60);
2535#else
2536 PCIDevSetCapabilityList (&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
2537#endif
2538
2539 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2540 // of these values needs to be properly documented!
2541 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2542 PCIDevSetByte(&pThis->dev, 0x40, 0x01);
2543
2544 /* Power Management */
2545 PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2546 PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
2547 PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2548
2549#ifdef HDA_AS_PCI_EXPRESS
2550 /* PCI Express */
2551 PCIDevSetByte (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2552 PCIDevSetByte (&pThis->dev, 0x80 + 1, 0x60); /* next */
2553 /* Device flags */
2554 PCIDevSetWord (&pThis->dev, 0x80 + 2,
2555 /* version */ 0x1 |
2556 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2557 /* MSI */ (100) << 9
2558 );
2559 /* Device capabilities */
2560 PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2561 /* Device control */
2562 PCIDevSetWord (&pThis->dev, 0x80 + 8, 0);
2563 /* Device status */
2564 PCIDevSetWord (&pThis->dev, 0x80 + 10, 0);
2565 /* Link caps */
2566 PCIDevSetDWord (&pThis->dev, 0x80 + 12, 0);
2567 /* Link control */
2568 PCIDevSetWord (&pThis->dev, 0x80 + 16, 0);
2569 /* Link status */
2570 PCIDevSetWord (&pThis->dev, 0x80 + 18, 0);
2571 /* Slot capabilities */
2572 PCIDevSetDWord (&pThis->dev, 0x80 + 20, 0);
2573 /* Slot control */
2574 PCIDevSetWord (&pThis->dev, 0x80 + 24, 0);
2575 /* Slot status */
2576 PCIDevSetWord (&pThis->dev, 0x80 + 26, 0);
2577 /* Root control */
2578 PCIDevSetWord (&pThis->dev, 0x80 + 28, 0);
2579 /* Root capabilities */
2580 PCIDevSetWord (&pThis->dev, 0x80 + 30, 0);
2581 /* Root status */
2582 PCIDevSetDWord (&pThis->dev, 0x80 + 32, 0);
2583 /* Device capabilities 2 */
2584 PCIDevSetDWord (&pThis->dev, 0x80 + 36, 0);
2585 /* Device control 2 */
2586 PCIDevSetQWord (&pThis->dev, 0x80 + 40, 0);
2587 /* Link control 2 */
2588 PCIDevSetQWord (&pThis->dev, 0x80 + 48, 0);
2589 /* Slot control 2 */
2590 PCIDevSetWord (&pThis->dev, 0x80 + 56, 0);
2591#endif
2592
2593 /*
2594 * Register the PCI device.
2595 */
2596 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
2597 if (RT_FAILURE (rc))
2598 return rc;
2599
2600 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
2601 hdaMap);
2602 if (RT_FAILURE (rc))
2603 return rc;
2604
2605#ifdef VBOX_WITH_MSI_DEVICES
2606 PDMMSIREG MsiReg;
2607 RT_ZERO(MsiReg);
2608 MsiReg.cMsiVectors = 1;
2609 MsiReg.iMsiCapOffset = 0x60;
2610 MsiReg.iMsiNextOffset = 0x50;
2611 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
2612 if (RT_FAILURE (rc))
2613 {
2614 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2615 PCIDevSetCapabilityList (&pThis->dev, 0x50);
2616 }
2617#endif
2618
2619 rc = PDMDevHlpSSMRegister (pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2620 if (RT_FAILURE (rc))
2621 return rc;
2622
2623 /*
2624 * Attach driver.
2625 */
2626 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
2627 &s->pDrvBase, "Audio Driver Port");
2628 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2629 Log (("hda: No attached driver!\n"));
2630 else if (RT_FAILURE (rc))
2631 {
2632 AssertMsgFailed (("Failed to attach Intel HDA LUN #0! rc=%Rrc\n", rc));
2633 return rc;
2634 }
2635
2636
2637
2638 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
2639 rc = codecConstruct(pDevIns, &pThis->hda.Codec, pCfgHandle);
2640 if (RT_FAILURE(rc))
2641 AssertRCReturn(rc, rc);
2642
2643 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2644 verb F20 should provide device/codec recognition. */
2645 Assert(pThis->hda.Codec.u16VendorId);
2646 Assert(pThis->hda.Codec.u16DeviceId);
2647 PCIDevSetSubSystemVendorId (&pThis->dev, pThis->hda.Codec.u16VendorId); /* 2c ro - intel.) */
2648 PCIDevSetSubSystemId (&pThis->dev, pThis->hda.Codec.u16DeviceId); /* 2e ro. */
2649
2650 hdaReset (pDevIns);
2651 pThis->hda.Codec.id = 0;
2652 pThis->hda.Codec.pfnTransfer = hdaTransfer;
2653 pThis->hda.Codec.pfnReset = hdaCodecReset;
2654 /*
2655 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2656 * hdaReset shouldn't affects these registers.
2657 */
2658 WAKEEN(&pThis->hda) = 0x0;
2659 STATESTS(&pThis->hda) = 0x0;
2660 hdaInitMisc(pDevIns);
2661
2662 return VINF_SUCCESS;
2663}
2664
2665/**
2666 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2667 */
2668static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
2669{
2670 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2671
2672 int rc = codecDestruct(&pThis->hda.Codec);
2673 AssertRC(rc);
2674 if (pThis->hda.pu32CorbBuf)
2675 RTMemFree(pThis->hda.pu32CorbBuf);
2676 if (pThis->hda.pu64RirbBuf)
2677 RTMemFree(pThis->hda.pu64RirbBuf);
2678 return VINF_SUCCESS;
2679}
2680
2681/**
2682 * The device registration structure.
2683 */
2684const PDMDEVREG g_DeviceICH6_HDA =
2685{
2686 /* u32Version */
2687 PDM_DEVREG_VERSION,
2688 /* szName */
2689 "hda",
2690 /* szRCMod */
2691 "",
2692 /* szR0Mod */
2693 "",
2694 /* pszDescription */
2695 "Intel HD Audio Controller",
2696 /* fFlags */
2697 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2698 /* fClass */
2699 PDM_DEVREG_CLASS_AUDIO,
2700 /* cMaxInstances */
2701 1,
2702 /* cbInstance */
2703 sizeof(PCIINTELHDLinkState),
2704 /* pfnConstruct */
2705 hdaConstruct,
2706 /* pfnDestruct */
2707 hdaDestruct,
2708 /* pfnRelocate */
2709 NULL,
2710 /* pfnIOCtl */
2711 NULL,
2712 /* pfnPowerOn */
2713 NULL,
2714 /* pfnReset */
2715 hdaReset,
2716 /* pfnSuspend */
2717 NULL,
2718 /* pfnResume */
2719 NULL,
2720 /* pfnAttach */
2721 NULL,
2722 /* pfnDetach */
2723 NULL,
2724 /* pfnQueryInterface. */
2725 NULL,
2726 /* pfnInitComplete */
2727 NULL,
2728 /* pfnPowerOff */
2729 NULL,
2730 /* pfnSoftReset */
2731 NULL,
2732 /* u32VersionEnd */
2733 PDM_DEVREG_VERSION
2734};
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette