VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 44639

Last change on this file since 44639 was 44639, checked in by vboxsync, 12 years ago

Eliminated PCIINTELHDLinkState, moving the pci device structure up into INTELHDLinkState. Codec pNodes -> paNodes.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 114.8 KB
Line 
1/* $Id: DevIchIntelHDA.cpp 44639 2013-02-11 19:25:42Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/vmm/pdmdev.h>
23#include <VBox/version.h>
24
25#include <iprt/assert.h>
26#include <iprt/uuid.h>
27#include <iprt/string.h>
28#include <iprt/mem.h>
29#include <iprt/asm.h>
30#include <iprt/asm-math.h>
31
32#include "VBoxDD.h"
33
34extern "C" {
35#include "audio.h"
36}
37#include "DevCodec.h"
38
39
40/*******************************************************************************
41* Defined Constants And Macros *
42*******************************************************************************/
43//#define HDA_AS_PCI_EXPRESS
44#define VBOX_WITH_INTEL_HDA
45
46#if defined(VBOX_WITH_HP_HDA)
47/* HP Pavilion dv4t-1300 */
48# define HDA_PCI_VENDOR_ID 0x103c
49# define HDA_PCI_DEICE_ID 0x30f7
50#elif defined(VBOX_WITH_INTEL_HDA)
51/* Intel HDA controller */
52# define HDA_PCI_VENDOR_ID 0x8086
53# define HDA_PCI_DEICE_ID 0x2668
54#elif defined(VBOX_WITH_NVIDIA_HDA)
55/* nVidia HDA controller */
56# define HDA_PCI_VENDOR_ID 0x10de
57# define HDA_PCI_DEICE_ID 0x0ac0
58#else
59# error "Please specify your HDA device vendor/device IDs"
60#endif
61
62#define HDA_NREGS 112
63/* Registers */
64#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
65#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
66#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
67#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
68#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
69#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
70#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
71#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
72#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
73#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
74
75#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
76#define GCAP(pState) (HDA_REG((pState), GCAP))
77/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
78 * oss (15:12) - number of output streams supported
79 * iss (11:8) - number of input streams supported
80 * bss (7:3) - number of bidirectional streams supported
81 * bds (2:1) - number of serial data out signals supported
82 * b64sup (0) - 64 bit addressing supported.
83 */
84#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
85 ( (((oss) & 0xF) << 12) \
86 | (((iss) & 0xF) << 8) \
87 | (((bss) & 0x1F) << 3) \
88 | (((bds) & 0x3) << 2) \
89 | ((b64sup) & 1))
90#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
91#define VMIN(pState) (HDA_REG((pState), VMIN))
92
93#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
94#define VMAJ(pState) (HDA_REG((pState), VMAJ))
95
96#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
97#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
98
99#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
100#define INPAY(pState) (HDA_REG((pState), INPAY))
101
102#define ICH6_HDA_REG_GCTL (5)
103#define ICH6_HDA_GCTL_RST_SHIFT (0)
104#define ICH6_HDA_GCTL_FSH_SHIFT (1)
105#define ICH6_HDA_GCTL_UR_SHIFT (8)
106#define GCTL(pState) (HDA_REG((pState), GCTL))
107
108#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
109#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
110
111#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
112#define STATESTS(pState) (HDA_REG((pState), STATESTS))
113#define ICH6_HDA_STATES_SCSF 0x7
114
115#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
116#define ICH6_HDA_GSTS_FSH_SHIFT (1)
117#define GSTS(pState) (HDA_REG(pState, GSTS))
118
119#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
120#define ICH6_HDA_INTCTL_GIE_SHIFT 31
121#define ICH6_HDA_INTCTL_CIE_SHIFT 30
122#define ICH6_HDA_INTCTL_S0_SHIFT (0)
123#define ICH6_HDA_INTCTL_S1_SHIFT (1)
124#define ICH6_HDA_INTCTL_S2_SHIFT (2)
125#define ICH6_HDA_INTCTL_S3_SHIFT (3)
126#define ICH6_HDA_INTCTL_S4_SHIFT (4)
127#define ICH6_HDA_INTCTL_S5_SHIFT (5)
128#define ICH6_HDA_INTCTL_S6_SHIFT (6)
129#define ICH6_HDA_INTCTL_S7_SHIFT (7)
130#define INTCTL(pState) (HDA_REG((pState), INTCTL))
131#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
132#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
133#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
134#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
135
136/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
137 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
138 * the datasheet.
139 */
140#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
141#define SSYNC(pState) (HDA_REG((pState), SSYNC))
142
143#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
144#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
145#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
146#define ICH6_HDA_INTSTS_S0_SHIFT (0)
147#define ICH6_HDA_INTSTS_S1_SHIFT (1)
148#define ICH6_HDA_INTSTS_S2_SHIFT (2)
149#define ICH6_HDA_INTSTS_S3_SHIFT (3)
150#define ICH6_HDA_INTSTS_S4_SHIFT (4)
151#define ICH6_HDA_INTSTS_S5_SHIFT (5)
152#define ICH6_HDA_INTSTS_S6_SHIFT (6)
153#define ICH6_HDA_INTSTS_S7_SHIFT (7)
154#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
155#define INTSTS(pState) (HDA_REG((pState), INTSTS))
156#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
157#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
158#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
159#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
160
161#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
162#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
163#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
164#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
165#define ICH6_HDA_REG_CORBWP 15 /* 48 */
166#define ICH6_HDA_REG_CORBRP 16 /* 4A */
167#define ICH6_HDA_CORBRP_RST_SHIFT 15
168#define ICH6_HDA_CORBRP_WP_SHIFT 0
169#define ICH6_HDA_CORBRP_WP_MASK 0xFF
170
171#define CORBRP(pState) (HDA_REG(pState, CORBRP))
172#define CORBWP(pState) (HDA_REG(pState, CORBWP))
173
174#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
175#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
176#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
177
178#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
179
180
181#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
182#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
183#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
184
185#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
186#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
187#define ICH6_HDA_CORBSIZE_SZ 0x3
188#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
189#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
190/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
191
192#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
193#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
194
195#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
196#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
197
198#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
199#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
200#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
201#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
202
203#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
204#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
205#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
206
207#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
208#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
209#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
210#define ICH6_HDA_ROI_DMA_SHIFT (2)
211#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
212#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
213#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
214#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
215
216#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
217#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
218#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
219#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
220#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
221#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
222
223#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
224#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
225#define ICH6_HDA_RIRBSIZE_SZ 0x3
226
227#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
228#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
229
230
231#define ICH6_HDA_REG_IC 27 /* 0x60 */
232#define IC(pState) (HDA_REG(pState, IC))
233#define ICH6_HDA_REG_IR 28 /* 0x64 */
234#define IR(pState) (HDA_REG(pState, IR))
235#define ICH6_HDA_REG_IRS 29 /* 0x68 */
236#define ICH6_HDA_IRS_ICB_SHIFT (0)
237#define ICH6_HDA_IRS_IRV_SHIFT (1)
238#define IRS(pState) (HDA_REG(pState, IRS))
239#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
240#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
241
242#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
243#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
244#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
245#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
246#define DPBASE_ENABLED 1
247#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
248
249#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
250#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
251/* Note: sdnum here _MUST_ be stream reg number [0,7] */
252#define HDA_STREAM_REG2(pState, name, sdnum) (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
253
254#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
255#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
256#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
257#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
258#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
259#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
260#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
261#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
262
263#define SD(func, num) SD##num##func
264#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
265#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
266#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
267#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
268#define ICH6_HDA_SDCTL_DIR_SHIFT (19)
269#define ICH6_HDA_SDCTL_TP_SHIFT (18)
270#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)
271#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)
272#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
273#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
274#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
275#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
276#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
277
278#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
279#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
280#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
281#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
282#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
283#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
284#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
285#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
286
287#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
288#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
289#define ICH6_HDA_SDSTS_DE_SHIFT (4)
290#define ICH6_HDA_SDSTS_FE_SHIFT (3)
291#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
292
293#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
294#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
295#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
296#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
297#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
298#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
299#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
300#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
301
302#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
303
304#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
305#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
306#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
307#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
308#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
309#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
310#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
311#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
312
313#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
314
315#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
316#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
317#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
318#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
319#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
320#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
321#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
322#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
323
324#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
325
326#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
327#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
328#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
329#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
330#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
331#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
332#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
333#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
334
335/*
336 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
337 */
338#define HDA_SDFIFOW_8B (0x2)
339#define HDA_SDFIFOW_16B (0x3)
340#define HDA_SDFIFOW_32B (0x4)
341#define SDFIFOW(pState, num) HDA_REG((pState), SD(FIFOW, num))
342
343#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
344#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
345#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
346#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
347#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
348#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
349#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
350#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
351
352/*
353 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
354 * formula: size - 1
355 * Other values not listed are not supported.
356 */
357#define HDA_SDONFIFO_16B (0x0F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
358#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
359#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
360#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
361#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
362#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
363#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
364#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
365#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
366
367#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
368#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
369#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
370#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
371#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
372#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
373#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
374#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
375
376#define SDFMT(pState, num) (HDA_REG((pState), SD(FMT, num)))
377#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
378#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
379#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
380#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
381#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
382#define ICH6_HDA_SDFMT_BITS_SHIFT (4)
383#define ICH6_HDA_SDFMT_BITS_MASK (0x7)
384#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
385#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
386#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
387
388#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
389#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
390#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
391#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
392#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
393#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
394#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
395#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
396
397#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
398
399#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
400#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
401#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
402#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
403#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
404#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
405#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
406#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
407
408#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
409
410
411/*******************************************************************************
412* Structures and Typedefs *
413*******************************************************************************/
414typedef struct HDABDLEDESC
415{
416 uint64_t u64BdleCviAddr;
417 uint32_t u32BdleMaxCvi;
418 uint32_t u32BdleCvi;
419 uint32_t u32BdleCviLen;
420 uint32_t u32BdleCviPos;
421 bool fBdleCviIoc;
422 uint32_t cbUnderFifoW;
423 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
424} HDABDLEDESC, *PHDABDLEDESC;
425
426typedef struct HDASTREAMTRANSFERDESC
427{
428 uint64_t u64BaseDMA;
429 uint32_t u32Ctl;
430 uint32_t *pu32Sts;
431 uint8_t u8Strm;
432 uint32_t *pu32Lpib;
433 uint32_t u32Cbl;
434 uint32_t u32Fifos;
435} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
436
437typedef struct INTELHDLinkState
438{
439 /** The PCI device structure. */
440 PCIDevice PciDev;
441 /** Pointer to the device instance. */
442 PPDMDEVINSR3 pDevIns;
443 /** Pointer to the connector of the attached audio driver. */
444 PPDMIAUDIOCONNECTOR pDrv;
445 /** Pointer to the attached audio driver. */
446 PPDMIBASE pDrvBase;
447 /** The base interface for LUN\#0. */
448 PDMIBASE IBase;
449 RTGCPHYS addrMMReg;
450 uint32_t au32Regs[HDA_NREGS];
451 HDABDLEDESC stInBdle;
452 HDABDLEDESC stOutBdle;
453 HDABDLEDESC stMicBdle;
454 /** Interrupt on completion */
455 bool fCviIoc;
456 uint64_t u64CORBBase;
457 uint64_t u64RIRBBase;
458 uint64_t u64DPBase;
459 /** pointer to CORB buf */
460 uint32_t *pu32CorbBuf;
461 /** size in bytes of CORB buf */
462 uint32_t cbCorbBuf;
463 /** pointer on RIRB buf */
464 uint64_t *pu64RirbBuf;
465 /** size in bytes of RIRB buf */
466 uint32_t cbRirbBuf;
467 /** indicates if HDA in reset. */
468 bool fInReset;
469 CODECState Codec;
470 uint8_t u8Counter;
471 uint64_t u64BaseTS;
472} INTELHDLinkState, *PINTELHDLinkState;
473/** ICH Intel HD Audio Controller state. */
474typedef INTELHDLinkState HDASTATE;
475/** Pointer to the ICH Intel HD Audio Controller state. */
476typedef HDASTATE *PHDASTATE;
477
478#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
479#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PHDASTATE)(pPciDev))
480
481#define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In, \
482 SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
483#define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out, \
484 SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
485
486
487/*******************************************************************************
488* Internal Functions *
489*******************************************************************************/
490static FNPDMDEVRESET hdaReset;
491
492/** @todo r=bird: Why aren't these static? And why use DECLCALLBACK for
493 * internal functions? */
494DECLCALLBACK(int) hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
495DECLCALLBACK(int) hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
496DECLCALLBACK(int) hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
497DECLCALLBACK(int) hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
498DECLCALLBACK(int) hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
499DECLCALLBACK(int) hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
500DECLCALLBACK(int) hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
501DECLCALLBACK(int) hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
502DECLCALLBACK(int) hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
503DECLCALLBACK(int) hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
504DECLCALLBACK(int) hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
505DECLCALLBACK(int) hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
506DECLCALLBACK(int) hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
507DECLCALLBACK(int) hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
508DECLCALLBACK(int) hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
509DECLCALLBACK(int) hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
510DECLCALLBACK(int) hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
511DECLCALLBACK(int) hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
512DECLCALLBACK(int) hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
513DECLCALLBACK(int) hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
514
515DECLCALLBACK(int) hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
516DECLCALLBACK(int) hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
517DECLCALLBACK(int) hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
518DECLCALLBACK(int) hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
519DECLCALLBACK(int) hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
520DECLCALLBACK(int) hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
521DECLCALLBACK(int) hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
522DECLCALLBACK(int) hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
523DECLCALLBACK(int) hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
524DECLCALLBACK(int) hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
525DECLCALLBACK(int) hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
526DECLCALLBACK(int) hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
527DECLCALLBACK(int) hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
528DECLCALLBACK(int) hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
529DECLCALLBACK(int) hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
530DECLCALLBACK(int) hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
531
532DECLINLINE(void) hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm,
533 PHDASTREAMTRANSFERDESC pStreamDesc);
534static int hdaMMIORegLookup(INTELHDLinkState* pState, uint32_t offReg);
535static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
536#ifdef LOG_ENABLED
537static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
538#endif
539
540
541/*******************************************************************************
542* Global Variables *
543*******************************************************************************/
544/* see 302349 p 6.2*/
545static const struct
546{
547 /** Register offset in the register space. */
548 uint32_t offset;
549 /** Size in bytes. Registers of size > 4 are in fact tables. */
550 uint32_t size;
551 /** Readable bits. */
552 uint32_t readable;
553 /** Writable bits. */
554 uint32_t writable;
555 /** Read callback. */
556 int (*pfnRead)(INTELHDLinkState *pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
557 /** Write callback. */
558 int (*pfnWrite)(INTELHDLinkState *pState, uint32_t offset, uint32_t index, uint32_t u32Value);
559 /** Abbreviated name. */
560 const char *abbrev;
561 /** Full name. */
562 const char *name;
563} g_aIchIntelHDRegMap[HDA_NREGS] =
564{
565 /* offset size read mask write mask read callback write callback abbrev full name */
566 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
567 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
568 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
569 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
570 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
571 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
572 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
573 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
574 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
575 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
576 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
577 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
578 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
579 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
580 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
581 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
582 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
583 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
584 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
585 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
586 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
587 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
588 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
589 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
590 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
591 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
592 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
593 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
594 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
595 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
596 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
597 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
598 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
599 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
600
601 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
602 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
603 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
604 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
605 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
606 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
607 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
608 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
609 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
610 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
611
612 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
613 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
614 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
615 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
616 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
617 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
618 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
619 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
620 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
621 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
622
623 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
624 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
625 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
626 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
627 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
628 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
629 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
630 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
631 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
632 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
633
634 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
635 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
636 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
637 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
638 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
639 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
640 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
641 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
642 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
643 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
644
645 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
646 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
647 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
648 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
649 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
650 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
651 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
652 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
653 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
654 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
655
656 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
657 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
658 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
659 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
660 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
661 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
662 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
663 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
664 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
665 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
666
667 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
668 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
669 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
670 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
671 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
672 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
673 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
674 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
675 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
676 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
677
678 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
679 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
680 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
681 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
682 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
683 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
684 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
685 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
686 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
687 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
688};
689
690/** HDABDLEDESC field descriptors the v3+ saved state. */
691static SSMFIELD const g_aHdaBDLEDescFields[] =
692{
693 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
694 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
695 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
696 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
697 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
698 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
699 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
700 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
701 SSMFIELD_ENTRY_TERM()
702};
703
704/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
705static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
706{
707 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
708 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
709 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
710 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
711 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
712 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
713 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
714 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
715 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
716 SSMFIELD_ENTRY_TERM()
717};
718
719
720DECLINLINE(void) hdaUpdatePosBuf(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
721{
722 if (pState->u64DPBase & DPBASE_ENABLED)
723 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
724 (pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
725}
726DECLINLINE(uint32_t) hdaFifoWToSz(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
727{
728#if 0
729 switch(HDA_STREAM_REG2(pState, FIFOW, pStreamDesc->u8Strm))
730 {
731 case HDA_SDFIFOW_8B: return 8;
732 case HDA_SDFIFOW_16B: return 16;
733 case HDA_SDFIFOW_32B: return 32;
734 default:
735 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
736 }
737#endif
738 return 0;
739}
740
741static int hdaProcessInterrupt(INTELHDLinkState* pState)
742{
743#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
744 ( INTCTL_SX((pState), num) \
745 && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
746 bool fIrq = false;
747 if ( INTCTL_CIE(pState)
748 && ( RIRBSTS_RINTFL(pState)
749 || RIRBSTS_RIRBOIS(pState)
750 || (STATESTS(pState) & WAKEEN(pState))))
751 fIrq = true;
752
753 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
754 || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
755 fIrq = true;
756
757 if (INTCTL_GIE(pState))
758 {
759 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
760 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
761 }
762 return VINF_SUCCESS;
763}
764
765static int hdaMMIORegLookup(INTELHDLinkState* pState, uint32_t offReg)
766{
767 /*
768 * Aliases HDA spec 3.3.45
769 */
770 switch (offReg)
771 {
772 case 0x2084:
773 return HDA_REG_IND_NAME(SD0LPIB);
774 case 0x20A4:
775 return HDA_REG_IND_NAME(SD1LPIB);
776 case 0x20C4:
777 return HDA_REG_IND_NAME(SD2LPIB);
778 case 0x20E4:
779 return HDA_REG_IND_NAME(SD3LPIB);
780 case 0x2104:
781 return HDA_REG_IND_NAME(SD4LPIB);
782 case 0x2124:
783 return HDA_REG_IND_NAME(SD5LPIB);
784 case 0x2144:
785 return HDA_REG_IND_NAME(SD6LPIB);
786 case 0x2164:
787 return HDA_REG_IND_NAME(SD7LPIB);
788 }
789
790 /*
791 * Binary search the
792 */
793 int idxHigh = RT_ELEMENTS(g_aIchIntelHDRegMap);
794 int idxLow = 0;
795 for (;;)
796 {
797#ifdef DEBUG_vvl
798 Assert( idxHigh >= 0
799 && idxLow >= 0);
800#endif
801 if ( idxHigh < idxLow
802 || idxHigh < 0)
803 break;
804 int idxMiddle = idxLow + (idxHigh - idxLow) / 2;
805 if (offReg < g_aIchIntelHDRegMap[idxMiddle].offset)
806 idxHigh = idxMiddle - 1;
807 else if (offReg >= g_aIchIntelHDRegMap[idxMiddle].offset + g_aIchIntelHDRegMap[idxMiddle].size)
808 idxLow = idxMiddle + 1;
809 else if ( offReg >= g_aIchIntelHDRegMap[idxMiddle].offset
810 && offReg < g_aIchIntelHDRegMap[idxMiddle].offset + g_aIchIntelHDRegMap[idxMiddle].size)
811 return idxMiddle;
812 }
813 return -1;
814}
815
816static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
817{
818 int rc = VINF_SUCCESS;
819 if (fLocal)
820 {
821 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
822 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
823 if (RT_FAILURE(rc))
824 AssertRCReturn(rc, rc);
825#ifdef DEBUG_CMD_BUFFER
826 uint8_t i = 0;
827 do
828 {
829 Log(("hda: corb%02x: ", i));
830 uint8_t j = 0;
831 do
832 {
833 const char *prefix;
834 if ((i + j) == CORBRP(pState))
835 prefix = "[R]";
836 else if ((i + j) == CORBWP(pState))
837 prefix = "[W]";
838 else
839 prefix = " "; /* three spaces */
840 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
841 j++;
842 } while (j < 8);
843 Log(("\n"));
844 i += 8;
845 } while(i != 0);
846#endif
847 }
848 else
849 {
850 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
851 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
852 if (RT_FAILURE(rc))
853 AssertRCReturn(rc, rc);
854#ifdef DEBUG_CMD_BUFFER
855 uint8_t i = 0;
856 do {
857 Log(("hda: rirb%02x: ", i));
858 uint8_t j = 0;
859 do {
860 const char *prefix;
861 if ((i + j) == RIRBWP(pState))
862 prefix = "[W]";
863 else
864 prefix = " ";
865 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
866 } while (++j < 8);
867 Log(("\n"));
868 i += 8;
869 } while (i != 0);
870#endif
871 }
872 return rc;
873}
874
875static int hdaCORBCmdProcess(INTELHDLinkState *pState)
876{
877 int rc;
878 uint8_t corbRp;
879 uint8_t corbWp;
880 uint8_t rirbWp;
881
882 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
883
884 rc = hdaCmdSync(pState, true);
885 if (RT_FAILURE(rc))
886 AssertRCReturn(rc, rc);
887 corbRp = CORBRP(pState);
888 corbWp = CORBWP(pState);
889 rirbWp = RIRBWP(pState);
890 Assert((corbWp != corbRp));
891 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
892 while (corbRp != corbWp)
893 {
894 uint32_t cmd;
895 uint64_t resp;
896 pfn = (PFNCODECVERBPROCESSOR)NULL;
897 corbRp++;
898 cmd = pState->pu32CorbBuf[corbRp];
899 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
900 if (RT_FAILURE(rc))
901 AssertRCReturn(rc, rc);
902 Assert(pfn);
903 (rirbWp)++;
904
905 if (RT_LIKELY(pfn))
906 rc = pfn(&pState->Codec, cmd, &resp);
907 else
908 rc = VERR_INVALID_FUNCTION;
909
910 if (RT_FAILURE(rc))
911 AssertRCReturn(rc, rc);
912 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
913 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
914 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
915 {
916 Log(("hda: unexpected unsolicited response.\n"));
917 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
918 return rc;
919 }
920 pState->pu64RirbBuf[rirbWp] = resp;
921 pState->u8Counter++;
922 if (pState->u8Counter == RINTCNT_N(pState))
923 break;
924 }
925 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
926 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
927 rc = hdaCmdSync(pState, false);
928 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
929 if (RIRBCTL_RIRB_RIC(pState))
930 {
931 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
932 pState->u8Counter = 0;
933 rc = hdaProcessInterrupt(pState);
934 }
935 if (RT_FAILURE(rc))
936 AssertRCReturn(rc, rc);
937 return rc;
938}
939
940static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
941{
942 Log(("hda: reset of stream (%d) started\n", u8Strm));
943 Assert(( pState
944 && pBdle
945 && pStreamDesc
946 && u8Strm <= 7));
947 memset(pBdle, 0, sizeof(HDABDLEDESC));
948 *pStreamDesc->pu32Lpib = 0;
949 *pStreamDesc->pu32Sts = 0;
950 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
951 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
952 HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
953
954 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
955 HDA_STREAM_REG2(pState, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
956 HDA_STREAM_REG2(pState, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
957 HDA_STREAM_REG2(pState, CBL, u8Strm) = 0;
958 HDA_STREAM_REG2(pState, LVI, u8Strm) = 0;
959 HDA_STREAM_REG2(pState, FMT, u8Strm) = 0;
960 HDA_STREAM_REG2(pState, BDPU, u8Strm) = 0;
961 HDA_STREAM_REG2(pState, BDPL, u8Strm) = 0;
962 Log(("hda: reset of stream (%d) finished\n", u8Strm));
963}
964
965
966DECLCALLBACK(int) hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
967{
968 *pu32Value = 0;
969 return VINF_SUCCESS;
970}
971DECLCALLBACK(int) hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
972{
973 return VINF_SUCCESS;
974}
975/* U8 */
976DECLCALLBACK(int) hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
977{
978 Assert(((pState->au32Regs[index] & g_aIchIntelHDRegMap[index].readable) & 0xffffff00) == 0);
979 return hdaRegReadU32(pState, offset, index, pu32Value);
980}
981
982DECLCALLBACK(int) hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
983{
984 Assert(((u32Value & 0xffffff00) == 0));
985 return hdaRegWriteU32(pState, offset, index, u32Value);
986}
987/* U16 */
988DECLCALLBACK(int) hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
989{
990 Assert(((pState->au32Regs[index] & g_aIchIntelHDRegMap[index].readable) & 0xffff0000) == 0);
991 return hdaRegReadU32(pState, offset, index, pu32Value);
992}
993
994DECLCALLBACK(int) hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
995{
996 Assert(((u32Value & 0xffff0000) == 0));
997 return hdaRegWriteU32(pState, offset, index, u32Value);
998}
999
1000/* U24 */
1001DECLCALLBACK(int) hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1002{
1003 Assert(((pState->au32Regs[index] & g_aIchIntelHDRegMap[index].readable) & 0xff000000) == 0);
1004 return hdaRegReadU32(pState, offset, index, pu32Value);
1005}
1006
1007DECLCALLBACK(int) hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1008{
1009 Assert(((u32Value & 0xff000000) == 0));
1010 return hdaRegWriteU32(pState, offset, index, u32Value);
1011}
1012/* U32 */
1013DECLCALLBACK(int) hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1014{
1015 *pu32Value = pState->au32Regs[index] & g_aIchIntelHDRegMap[index].readable;
1016 return VINF_SUCCESS;
1017}
1018
1019DECLCALLBACK(int) hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1020{
1021 pState->au32Regs[index] = (u32Value & g_aIchIntelHDRegMap[index].writable)
1022 | (pState->au32Regs[index] & ~g_aIchIntelHDRegMap[index].writable);
1023 return VINF_SUCCESS;
1024}
1025
1026DECLCALLBACK(int) hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1027{
1028 return hdaRegReadU32(pState, offset, index, pu32Value);
1029}
1030
1031DECLCALLBACK(int) hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1032{
1033 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1034 {
1035 /* exit reset state */
1036 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1037 pState->fInReset = false;
1038 }
1039 else
1040 {
1041 /* enter reset state*/
1042 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
1043 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
1044 {
1045 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1046 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
1047 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
1048 }
1049 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
1050 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1051 pState->fInReset = true;
1052 }
1053 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1054 {
1055 /* Flush: GSTS:1 set, see 6.2.6*/
1056 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1057 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1058 }
1059 return VINF_SUCCESS;
1060}
1061
1062DECLCALLBACK(int) hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1063{
1064 uint32_t v = pState->au32Regs[index];
1065 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
1066 pState->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
1067 return VINF_SUCCESS;
1068}
1069
1070DECLCALLBACK(int) hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1071{
1072 uint32_t v = 0;
1073 if ( RIRBSTS_RIRBOIS(pState)
1074 || RIRBSTS_RINTFL(pState)
1075 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
1076 || STATESTS(pState))
1077 v |= RT_BIT(30);
1078#define HDA_IS_STREAM_EVENT(pState, stream) \
1079 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1080 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1081 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1082#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
1083 MARK_STREAM(pState, 0, v);
1084 MARK_STREAM(pState, 1, v);
1085 MARK_STREAM(pState, 2, v);
1086 MARK_STREAM(pState, 3, v);
1087 MARK_STREAM(pState, 4, v);
1088 MARK_STREAM(pState, 5, v);
1089 MARK_STREAM(pState, 6, v);
1090 MARK_STREAM(pState, 7, v);
1091 v |= v ? RT_BIT(31) : 0;
1092 *pu32Value = v;
1093 return VINF_SUCCESS;
1094}
1095
1096DECLCALLBACK(int) hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1097{
1098 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1099 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pState))
1100 - pState->u64BaseTS, 24, 1000);
1101 return VINF_SUCCESS;
1102}
1103
1104DECLCALLBACK(int) hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1105{
1106 return hdaRegReadU16(pState, offset, index, pu32Value);
1107}
1108
1109DECLCALLBACK(int) hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1110{
1111 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1112 CORBRP(pState) = 0;
1113 else
1114 return hdaRegWriteU8(pState, offset, index, u32Value);
1115 return VINF_SUCCESS;
1116}
1117
1118DECLCALLBACK(int) hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1119{
1120 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
1121 AssertRC(rc);
1122 if ( CORBWP(pState) != CORBRP(pState)
1123 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
1124 return hdaCORBCmdProcess(pState);
1125 return rc;
1126}
1127
1128DECLCALLBACK(int) hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1129{
1130 uint32_t v = CORBSTS(pState);
1131 CORBSTS(pState) &= ~(v & u32Value);
1132 return VINF_SUCCESS;
1133}
1134
1135DECLCALLBACK(int) hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1136{
1137 int rc;
1138 rc = hdaRegWriteU16(pState, offset, index, u32Value);
1139 if (RT_FAILURE(rc))
1140 AssertRCReturn(rc, rc);
1141 if (CORBWP(pState) == CORBRP(pState))
1142 return VINF_SUCCESS;
1143 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1144 return VINF_SUCCESS;
1145 rc = hdaCORBCmdProcess(pState);
1146 return rc;
1147}
1148
1149DECLCALLBACK(int) hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1150{
1151 return hdaRegReadU24(pState, offset, index, pu32Value);
1152}
1153
1154DECLCALLBACK(int) hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1155{
1156 bool fRun = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1157 bool fInRun = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1158 bool fReset = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1159 bool fInReset = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1160 int rc = VINF_SUCCESS;
1161 if (fInReset)
1162 {
1163 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1164 * from reset
1165 */
1166 Assert((!fReset));
1167 Log(("hda: guest initiated exit of stream reset.\n"));
1168 goto l_done;
1169 }
1170 else if (fReset)
1171 {
1172 /*
1173 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1174 */
1175 uint8_t u8Strm = 0;
1176 PHDABDLEDESC pBdle = NULL;
1177 HDASTREAMTRANSFERDESC StreamDesc;
1178 Assert((!fInRun && !fRun));
1179 switch (index)
1180 {
1181 case ICH6_HDA_REG_SD0CTL:
1182 u8Strm = 0;
1183 pBdle = &pState->stInBdle;
1184 break;
1185 case ICH6_HDA_REG_SD4CTL:
1186 u8Strm = 4;
1187 pBdle = &pState->stOutBdle;
1188 break;
1189 default:
1190 Log(("hda: changing SRST bit on non-attached stream\n"));
1191 goto l_done;
1192 }
1193 Log(("hda: guest initiated enter to stream reset.\n"));
1194 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &StreamDesc);
1195 hdaStreamReset(pState, pBdle, &StreamDesc, u8Strm);
1196 goto l_done;
1197 }
1198
1199 /* we enter here to change DMA states only */
1200 if ( (fInRun && !fRun)
1201 || (fRun && !fInRun))
1202 {
1203 Assert((!fReset && !fInReset));
1204 switch (index)
1205 {
1206 case ICH6_HDA_REG_SD0CTL:
1207 AUD_set_active_in(pState->Codec.SwVoiceIn, fRun);
1208 break;
1209 case ICH6_HDA_REG_SD4CTL:
1210 AUD_set_active_out(pState->Codec.SwVoiceOut, fRun);
1211 break;
1212 default:
1213 Log(("hda: changing RUN bit on non-attached stream\n"));
1214 goto l_done;
1215 }
1216 }
1217
1218l_done:
1219 rc = hdaRegWriteU24(pState, offset, index, u32Value);
1220 if (RT_FAILURE(rc))
1221 AssertRCReturn(rc, VINF_SUCCESS);
1222 return rc;
1223}
1224
1225DECLCALLBACK(int) hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1226{
1227 uint32_t v = HDA_REG_IND(pState, index);
1228 v &= ~(u32Value & v);
1229 HDA_REG_IND(pState, index) = v;
1230 hdaProcessInterrupt(pState);
1231 return VINF_SUCCESS;
1232}
1233
1234DECLCALLBACK(int) hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1235{
1236 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1237 if (RT_FAILURE(rc))
1238 AssertRCReturn(rc, VINF_SUCCESS);
1239 return rc;
1240}
1241
1242DECLCALLBACK(int) hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1243{
1244 switch (u32Value)
1245 {
1246 case HDA_SDFIFOW_8B:
1247 case HDA_SDFIFOW_16B:
1248 case HDA_SDFIFOW_32B:
1249 return hdaRegWriteU16(pState, offset, index, u32Value);
1250 default:
1251 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1252 return hdaRegWriteU16(pState, offset, index, HDA_SDFIFOW_32B);
1253 }
1254 return VINF_SUCCESS;
1255}
1256/*
1257 * Note this method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39)
1258 *
1259 */
1260DECLCALLBACK(int) hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1261{
1262 switch (index)
1263 {
1264 /* SDInFIFOS is RO, n=0-3 */
1265 case ICH6_HDA_REG_SD0FIFOS:
1266 case ICH6_HDA_REG_SD1FIFOS:
1267 case ICH6_HDA_REG_SD2FIFOS:
1268 case ICH6_HDA_REG_SD3FIFOS:
1269 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1270 return VINF_SUCCESS;
1271 case ICH6_HDA_REG_SD4FIFOS:
1272 case ICH6_HDA_REG_SD5FIFOS:
1273 case ICH6_HDA_REG_SD6FIFOS:
1274 case ICH6_HDA_REG_SD7FIFOS:
1275 switch(u32Value)
1276 {
1277 case HDA_SDONFIFO_16B:
1278 case HDA_SDONFIFO_32B:
1279 case HDA_SDONFIFO_64B:
1280 case HDA_SDONFIFO_128B:
1281 case HDA_SDONFIFO_192B:
1282 return hdaRegWriteU16(pState, offset, index, u32Value);
1283
1284 case HDA_SDONFIFO_256B:
1285 Log(("hda: 256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1286 default:
1287 return hdaRegWriteU16(pState, offset, index, HDA_SDONFIFO_192B);
1288 }
1289 return VINF_SUCCESS;
1290 default:
1291 AssertMsgFailed(("Something weird happened with register lookup routine"));
1292 }
1293 return VINF_SUCCESS;
1294}
1295
1296static void hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1297{
1298 Assert((pAudSetting));
1299#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1300 uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1301 uint32_t u32HzMult = 1;
1302 uint32_t u32HzDiv = 1;
1303 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))
1304 {
1305 case 0: u32HzMult = 1; break;
1306 case 1: u32HzMult = 2; break;
1307 case 2: u32HzMult = 3; break;
1308 case 3: u32HzMult = 4; break;
1309 default:
1310 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1311 }
1312 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))
1313 {
1314 case 0: u32HzDiv = 1; break;
1315 case 1: u32HzDiv = 2; break;
1316 case 2: u32HzDiv = 3; break;
1317 case 3: u32HzDiv = 4; break;
1318 case 4: u32HzDiv = 5; break;
1319 case 5: u32HzDiv = 6; break;
1320 case 6: u32HzDiv = 7; break;
1321 case 7: u32HzDiv = 8; break;
1322 }
1323 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1324
1325 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_BITS_MASK, ICH6_HDA_SDFMT_BITS_SHIFT))
1326 {
1327 case 0:
1328 Log(("hda: %s requested 8-bit\n", __FUNCTION__));
1329 pAudSetting->fmt = AUD_FMT_S8;
1330 break;
1331 case 1:
1332 Log(("hda: %s requested 16-bit\n", __FUNCTION__));
1333 pAudSetting->fmt = AUD_FMT_S16;
1334 break;
1335 case 2:
1336 Log(("hda: %s requested 20-bit\n", __FUNCTION__));
1337 break;
1338 case 3:
1339 Log(("hda: %s requested 24-bit\n", __FUNCTION__));
1340 break;
1341 case 4:
1342 Log(("hda: %s requested 32-bit\n", __FUNCTION__));
1343 pAudSetting->fmt = AUD_FMT_S32;
1344 break;
1345 default:
1346 AssertMsgFailed(("Unsupported"));
1347 }
1348 pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;
1349 pAudSetting->fmt = AUD_FMT_S16;
1350 pAudSetting->endianness = 0;
1351#undef EXTRACT_VALUE
1352}
1353
1354DECLCALLBACK(int) hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1355{
1356#ifdef VBOX_WITH_HDA_CODEC_EMU
1357 /* @todo a bit more investigation is required here. */
1358 int rc = 0;
1359 audsettings_t as;
1360 /* no reason to reopen voice with same settings */
1361 if (u32Value == HDA_REG_IND(pState, index))
1362 return VINF_SUCCESS;
1363 hdaSdFmtToAudSettings(u32Value, &as);
1364 switch (index)
1365 {
1366 case ICH6_HDA_REG_SD0FMT:
1367 rc = codecOpenVoice(&pState->Codec, PI_INDEX, &as);
1368 break;
1369 case ICH6_HDA_REG_SD4FMT:
1370 rc = codecOpenVoice(&pState->Codec, PO_INDEX, &as);
1371 break;
1372 default:
1373 Log(("HDA: attempt to change format on %d\n", index));
1374 rc = 0;
1375 }
1376 return hdaRegWriteU16(pState, offset, index, u32Value);
1377#else
1378 return hdaRegWriteU16(pState, offset, index, u32Value);
1379#endif
1380}
1381
1382DECLCALLBACK(int) hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1383{
1384 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1385 if (RT_FAILURE(rc))
1386 AssertRCReturn(rc, VINF_SUCCESS);
1387 return rc;
1388}
1389
1390DECLCALLBACK(int) hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1391{
1392 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1393 if (RT_FAILURE(rc))
1394 AssertRCReturn(rc, VINF_SUCCESS);
1395 return rc;
1396}
1397
1398DECLCALLBACK(int) hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1399{
1400 int rc = VINF_SUCCESS;
1401 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1402 if ( CORBWP(pState) != CORBRP(pState)
1403 || HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1404 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1405
1406 rc = hdaRegReadU32(pState, offset, index, pu32Value);
1407 return rc;
1408}
1409
1410DECLCALLBACK(int) hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1411{
1412 int rc = VINF_SUCCESS;
1413 uint64_t resp;
1414 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1415 /*
1416 * if guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1417 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1418 */
1419 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1420 && !IRS_ICB(pState))
1421 {
1422 uint32_t cmd = IC(pState);
1423 if (CORBWP(pState) != CORBRP(pState))
1424 {
1425 /*
1426 * 3.4.3 defines behavior of immediate Command status register.
1427 */
1428 LogRel(("hda: guest attempted process immediate verb (%x) with active CORB\n", cmd));
1429 return rc;
1430 }
1431 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1432 Log(("hda: IC:%x\n", cmd));
1433 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1434 if (RT_FAILURE(rc))
1435 AssertRCReturn(rc, rc);
1436 rc = pfn(&pState->Codec, cmd, &resp);
1437 if (RT_FAILURE(rc))
1438 AssertRCReturn(rc, rc);
1439 IR(pState) = (uint32_t)resp;
1440 Log(("hda: IR:%x\n", IR(pState)));
1441 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1442 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1443 return rc;
1444 }
1445 /*
1446 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1447 */
1448 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1449 && IRS_IRV(pState))
1450 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1451 return rc;
1452}
1453
1454DECLCALLBACK(int) hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1455{
1456 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1457 {
1458 RIRBWP(pState) = 0;
1459 }
1460 /* The remaining bits are O, see 6.2.22 */
1461 return VINF_SUCCESS;
1462}
1463
1464DECLCALLBACK(int) hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1465{
1466 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1467 if (RT_FAILURE(rc))
1468 AssertRCReturn(rc, rc);
1469 switch(index)
1470 {
1471 case ICH6_HDA_REG_CORBLBASE:
1472 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1473 pState->u64CORBBase |= pState->au32Regs[index];
1474 break;
1475 case ICH6_HDA_REG_CORBUBASE:
1476 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1477 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1478 break;
1479 case ICH6_HDA_REG_RIRLBASE:
1480 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1481 pState->u64RIRBBase |= pState->au32Regs[index];
1482 break;
1483 case ICH6_HDA_REG_RIRUBASE:
1484 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1485 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1486 break;
1487 case ICH6_HDA_REG_DPLBASE:
1488 /* @todo: first bit has special meaning */
1489 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1490 pState->u64DPBase |= pState->au32Regs[index];
1491 break;
1492 case ICH6_HDA_REG_DPUBASE:
1493 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1494 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1495 break;
1496 default:
1497 AssertMsgFailed(("Invalid index"));
1498 }
1499 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1500 return rc;
1501}
1502
1503DECLCALLBACK(int) hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1504{
1505 uint8_t v = RIRBSTS(pState);
1506 RIRBSTS(pState) &= ~(v & u32Value);
1507
1508 return hdaProcessInterrupt(pState);
1509}
1510
1511#ifdef LOG_ENABLED
1512static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1513{
1514#if 0
1515 uint64_t addr;
1516 uint32_t len;
1517 uint32_t ioc;
1518 uint8_t bdle[16];
1519 uint32_t counter;
1520 uint32_t i;
1521 uint32_t sum = 0;
1522 Assert(pBdle && pBdle->u32BdleMaxCvi);
1523 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1524 {
1525 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1526 addr = *(uint64_t *)bdle;
1527 len = *(uint32_t *)&bdle[8];
1528 ioc = *(uint32_t *)&bdle[12];
1529 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1530 sum += len;
1531 }
1532 Log(("hda: sum: %d\n", sum));
1533 for (i = 0; i < 8; ++i)
1534 {
1535 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1536 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
1537 i , counter));
1538 }
1539#endif
1540}
1541#endif
1542
1543static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1544{
1545 uint8_t bdle[16];
1546 Assert(( pStreamDesc->u64BaseDMA
1547 && pBdle
1548 && pBdle->u32BdleMaxCvi));
1549 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1550 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1551 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1552 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1553#ifdef LOG_ENABLED
1554 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1555#endif
1556}
1557
1558DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1559 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1560{
1561 uint32_t cb2Copy;
1562 /*
1563 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
1564 */
1565 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1566 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1567 /*
1568 * we may increase the counter in range of [0, FIFOS + 1]
1569 */
1570 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1571 Assert((u32SoundBackendBufferBytesAvail > 0));
1572
1573 /* sanity check to avoid overriding the backend audio buffer */
1574 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1575 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1576
1577 if (cb2Copy <= pBdle->cbUnderFifoW)
1578 return 0;
1579 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
1580 return cb2Copy;
1581}
1582
1583DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1584 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1585{
1586 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1587 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1588 Assert((cbCopied));
1589 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1590 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
1591 * Probably we need to move the buffer, but it is rather hard to imagine a situation
1592 * where it might happen.
1593 */
1594 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write the entire buffer including unreported bytes */
1595 if ( pBdle->cbUnderFifoW
1596 && pBdle->cbUnderFifoW <= cbCopied)
1597 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1598
1599 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1600 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
1601
1602 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
1603 pBdle->u32BdleCviPos += cbArranged2Copy;
1604
1605 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1606 /* We report all bytes (including previously unreported bytes) */
1607 *pu32DMACursor += cbCopied;
1608 /* Decrease the backend counter by the number of bytes we copied to the backend */
1609 *pu32BackendBufferCapacity -= cbCopied;
1610 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1611 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1612}
1613
1614DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1615 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1616{
1617 Assert((cbCopied, cbArranged2Copy));
1618 *pu32BackendBufferCapacity -= cbCopied;
1619 pBdle->u32BdleCviPos += cbCopied;
1620 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1621 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1622 pBdle->cbUnderFifoW = 0;
1623 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1624 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1625}
1626
1627DECLINLINE(void) hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1628 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1629{
1630 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1631 pBdle->u32BdleCviPos += cbCopied;
1632 pBdle->cbUnderFifoW += cbCopied;
1633 /* In case of a read transaction we're always copying from the backend buffer */
1634 if (pu32BackendBufferCapacity)
1635 *pu32BackendBufferCapacity -= cbCopied;
1636 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1637 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pState, pStreamDesc)));
1638}
1639
1640DECLINLINE(bool) hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1641{
1642 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1643 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1644
1645 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1646
1647 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1648 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1649 hdaUpdatePosBuf(pState, pStreamDesc);
1650
1651 /* don't touch BdleCvi counter on uninitialized descriptor */
1652 if ( pBdle->u32BdleCviPos
1653 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1654 {
1655 pBdle->u32BdleCviPos = 0;
1656 pBdle->u32BdleCvi++;
1657 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1658 pBdle->u32BdleCvi = 0;
1659 }
1660 return fOnBufferEdge;
1661}
1662
1663DECLINLINE(void) hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1664 uint32_t cbInc)
1665{
1666 /*
1667 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
1668 * (ICH6 datasheet 18.2.38)
1669 */
1670 if (!pBdle->cbUnderFifoW)
1671 {
1672 *pStreamDesc->pu32Lpib += cbInc;
1673
1674 /*
1675 * Assert. The buffer counters should never overlap.
1676 */
1677 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1678
1679 hdaUpdatePosBuf(pState, pStreamDesc);
1680
1681 }
1682}
1683
1684static bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1685{
1686 bool fDoNextTransferLoop = true;
1687 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1688 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1689 {
1690 if ( !pBdle->cbUnderFifoW
1691 && pBdle->fBdleCviIoc)
1692 {
1693 /*
1694 * @todo - more carefully investigate BCIS flag.
1695 * Speech synthesis works fine on Mac Guest if this bit isn't set
1696 * but in general sound quality gets worse.
1697 */
1698 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1699
1700 /*
1701 * we should generate the interrupt if ICE bit of SDCTL register is set.
1702 */
1703 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1704 hdaProcessInterrupt(pState);
1705 }
1706 fDoNextTransferLoop = false;
1707 }
1708 return fDoNextTransferLoop;
1709}
1710
1711/*
1712 * hdaReadAudio - copies samples from audio backend to DMA.
1713 * Note: this function writes to the DMA buffer immediately, but "reports bytes" when all conditions are met (FIFOW)
1714 */
1715static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1716{
1717 PHDABDLEDESC pBdle = &pState->stInBdle;
1718 uint32_t cbTransferred = 0;
1719 uint32_t cb2Copy = 0;
1720 uint32_t cbBackendCopy = 0;
1721
1722 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1723
1724 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1725 if (!cb2Copy)
1726 {
1727 /* if we enter here we can't report "unreported bits" */
1728 *fStop = true;
1729 goto l_done;
1730 }
1731
1732
1733 /*
1734 * read from backend input line to the last unreported position or at the begining.
1735 */
1736 cbBackendCopy = AUD_read (pState->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1737 /*
1738 * write the HDA DMA buffer
1739 */
1740 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1741
1742 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
1743 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1744
1745 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pState, 0))
1746 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1747 else
1748 {
1749 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1750 *fStop = true;
1751 }
1752l_done:
1753 Assert((cbTransferred <= (SDFIFOS(pState, 0) + 1)));
1754 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1755 return cbTransferred;
1756}
1757
1758static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1759{
1760 PHDABDLEDESC pBdle = &pState->stOutBdle;
1761 uint32_t cbTransferred = 0;
1762 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1763 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1764
1765 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1766
1767 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1768
1769 /*
1770 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the previous unreported transfer we write at offset ''pBdle->cbUnderFifoW'')
1771 */
1772 if (!cb2Copy)
1773 {
1774 *fStop = true;
1775 goto l_done;
1776 }
1777
1778 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1779 /*
1780 * Write to audio backend. we should ensure that we have enough bytes to copy to the backend.
1781 */
1782 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, pStreamDesc))
1783 {
1784 /*
1785 * Feed the newly fetched samples, including unreported ones, to the backend.
1786 */
1787 cbBackendCopy = AUD_write (pState->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1788 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1789 }
1790 else
1791 {
1792 /* Not enough bytes to be processed and reported, we'll try our luck next time around */
1793 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cb2Copy, NULL);
1794 *fStop = true;
1795 }
1796
1797l_done:
1798 Assert((cbTransferred <= (SDFIFOS(pState, 4) + 1)));
1799 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransferred:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1800 return cbTransferred;
1801}
1802
1803/**
1804 * @interface_method_impl{HDACODEC,pfnReset}
1805 */
1806DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1807{
1808 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pvHDAState;
1809 return VINF_SUCCESS;
1810}
1811
1812DECLINLINE(void) hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm,
1813 PHDASTREAMTRANSFERDESC pStreamDesc)
1814{
1815 Assert(pState); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
1816
1817 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1818 pStreamDesc->u8Strm = u8Strm;
1819 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pState, CTL, u8Strm);
1820 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pState, BDPL, u8Strm),
1821 HDA_STREAM_REG2(pState, BDPU, u8Strm));
1822 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pState, LPIB, u8Strm);
1823 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pState, STS, u8Strm);
1824 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pState, CBL, u8Strm);
1825 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pState, FIFOS, u8Strm);
1826
1827 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pState, LVI, u8Strm);
1828
1829#ifdef LOG_ENABLED
1830 if ( pBdle
1831 && pBdle->u32BdleMaxCvi)
1832 {
1833 Log(("Initialization of transfer descriptor:\n"));
1834 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1835 }
1836#endif
1837}
1838
1839
1840/**
1841 * @interface_method_impl{HDACODEC,pfnTransfer}
1842 */
1843static DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1844{
1845 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pvHDAState;
1846 uint8_t u8Strm = 0;
1847 PHDABDLEDESC pBdle = NULL;
1848
1849 switch (src)
1850 {
1851 case PO_INDEX:
1852 {
1853 u8Strm = 4;
1854 pBdle = &pState->stOutBdle;
1855 break;
1856 }
1857 case PI_INDEX:
1858 {
1859 u8Strm = 0;
1860 pBdle = &pState->stInBdle;
1861 break;
1862 }
1863 default:
1864 return;
1865 }
1866
1867 HDASTREAMTRANSFERDESC StreamDesc;
1868 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &StreamDesc);
1869
1870 bool fStop = false;
1871 while (avail && !fStop)
1872 {
1873 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1874 && avail
1875 && StreamDesc.u64BaseDMA);
1876
1877 /* Fetch the Buffer Descriptor Entry (BDE). */
1878
1879 if (hdaIsTransferCountersOverlapped(pState, pBdle, &StreamDesc))
1880 hdaFetchBdle(pState, pBdle, &StreamDesc);
1881 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1882 Assert((avail >= 0 && (StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib)))); /* sanity */
1883 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
1884 Assert((u32CblLimit > hdaFifoWToSz(pState, &StreamDesc)));
1885 Log(("hda: CBL=%d, LPIB=%d\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
1886 uint32_t cb;
1887 switch (src)
1888 {
1889 case PO_INDEX:
1890 cb = hdaWriteAudio(pState, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1891 break;
1892 case PI_INDEX:
1893 cb = hdaReadAudio(pState, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1894 break;
1895 default:
1896 cb = 0;
1897 fStop = true;
1898 AssertMsgFailed(("Unsupported"));
1899 }
1900 Assert(cb <= StreamDesc.u32Fifos + 1);
1901 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1902
1903 /* Process end of buffer condition. */
1904 hdaStreamCounterUpdate(pState, pBdle, &StreamDesc, cb);
1905 fStop = !fStop ? !hdaDoNextTransferCycle(pState, pBdle, &StreamDesc) : fStop;
1906 }
1907}
1908
1909
1910/* MMIO callbacks */
1911
1912/**
1913 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
1914 *
1915 * @note During implementation, we discovered so-called "forgotten" or "hole"
1916 * registers whose description is not listed in the RPM, datasheet, or
1917 * spec.
1918 */
1919PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1920{
1921 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
1922 uint32_t offReg = GCPhysAddr - pThis->addrMMReg;
1923 int idxReg = hdaMMIORegLookup(pThis, offReg);
1924 int rc;
1925 Assert(!(offReg & 3)); Assert(cb == 4);
1926
1927 if (pThis->fInReset && idxReg != ICH6_HDA_REG_GCTL)
1928 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1929
1930 if (idxReg == -1)
1931 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
1932
1933 if (idxReg != -1)
1934 {
1935 rc = g_aIchIntelHDRegMap[idxReg].pfnRead(pThis, offReg, idxReg, (uint32_t *)pv);
1936 Log(("hda: read %s[%x/%x]\n", g_aIchIntelHDRegMap[idxReg].abbrev, *(uint32_t *)pv));
1937 }
1938 else
1939 {
1940 rc = VINF_IOM_MMIO_UNUSED_FF;
1941 Log(("hda: hole at %x is accessed for read\n", offReg));
1942 }
1943 return rc;
1944}
1945
1946
1947/**
1948 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
1949 */
1950PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1951{
1952 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
1953 uint32_t offReg = GCPhysAddr - pThis->addrMMReg;
1954 int idxReg = hdaMMIORegLookup(pThis, offReg);
1955 int rc;
1956 Assert(!(offReg & 3)); Assert(cb == 4);
1957
1958 if (pThis->fInReset && idxReg != ICH6_HDA_REG_GCTL)
1959 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1960
1961 if (idxReg != -1)
1962 {
1963#ifdef LOG_ENABLED
1964 uint32_t const u32CurValue = pThis->au32Regs[idxReg];
1965#endif
1966 rc = g_aIchIntelHDRegMap[idxReg].pfnWrite(pThis, offReg, idxReg, *(uint32_t const *)pv);
1967 Log(("hda: write %s:(%x) %x => %x\n", g_aIchIntelHDRegMap[idxReg].abbrev, *(uint32_t const *)pv,
1968 u32CurValue, pThis->au32Regs[idxReg]));
1969 }
1970 else
1971 {
1972 LogRel(("hda: Invalid write access @0x%x\n", offReg));
1973 rc = VINF_SUCCESS;
1974 }
1975
1976 Log(("hda: hole at %x is accessed for write\n", offReg));
1977 return rc;
1978}
1979
1980
1981/* PCI callback. */
1982
1983/**
1984 * @callback_method_impl{FNPCIIOREGIONMAP}
1985 */
1986static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
1987 PCIADDRESSSPACE enmType)
1988{
1989 int rc;
1990 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1991 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1992 PHDASTATE pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1993
1994 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
1995 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1996 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
1997 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_READ_MISSING,
1998 hdaMMIOWrite, hdaMMIORead, "ICH6_HDA");
1999
2000 if (RT_FAILURE(rc))
2001 return rc;
2002
2003 pThis->addrMMReg = GCPhysAddress;
2004 return VINF_SUCCESS;
2005}
2006
2007
2008/* Saved state callbacks. */
2009
2010/**
2011 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2012 */
2013static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2014{
2015 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2016 /* Save Codec nodes states */
2017 codecSaveState(&pThis->Codec, pSSM);
2018
2019 /* Save MMIO registers */
2020 AssertCompile(RT_ELEMENTS(pThis->au32Regs) == 112);
2021 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
2022 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
2023
2024 /* Save HDA dma counters */
2025 SSMR3PutStructEx(pSSM, &pThis->stOutBdle, sizeof(pThis->stOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2026 SSMR3PutStructEx(pSSM, &pThis->stMicBdle, sizeof(pThis->stMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2027 SSMR3PutStructEx(pSSM, &pThis->stInBdle, sizeof(pThis->stInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2028 return VINF_SUCCESS;
2029}
2030
2031
2032/**
2033 * @callback_method_impl{FNSSMDEVLOADEXEC}
2034 */
2035static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2036{
2037 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2038
2039 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2040
2041 /*
2042 * Load Codec nodes states.
2043 */
2044 int rc = codecLoadState(&pThis->Codec, pSSM, uVersion);
2045 if (RT_FAILURE(rc))
2046 return rc;
2047
2048 /*
2049 * Load MMIO registers.
2050 */
2051 uint32_t cRegs;
2052 switch (uVersion)
2053 {
2054 case HDA_SSM_VERSION_1:
2055 /* Starting with r71199, we would save 112 instead of 113
2056 registers due to some code cleanups. This only affected trunk
2057 builds in the 4.1 development period. */
2058 cRegs = 113;
2059 if (SSMR3HandleRevision(pSSM) >= 71199)
2060 {
2061 uint32_t uVer = SSMR3HandleVersion(pSSM);
2062 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
2063 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
2064 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
2065 cRegs = 112;
2066 }
2067 break;
2068
2069 case HDA_SSM_VERSION_2:
2070 case HDA_SSM_VERSION_3:
2071 cRegs = 112;
2072 AssertCompile(RT_ELEMENTS(pThis->au32Regs) == 112);
2073 break;
2074
2075 case HDA_SSM_VERSION:
2076 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
2077 AssertLogRelMsgReturn(cRegs == RT_ELEMENTS(pThis->au32Regs),
2078 ("cRegs is %d, expected %d\n", cRegs, RT_ELEMENTS(pThis->au32Regs)),
2079 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2080 break;
2081
2082 default:
2083 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2084 }
2085
2086 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
2087 {
2088 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
2089 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
2090 }
2091 else
2092 {
2093 RT_ZERO(pThis->au32Regs);
2094 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
2095 }
2096
2097 /*
2098 * Load HDA dma counters.
2099 */
2100 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
2101 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
2102 SSMR3GetStructEx(pSSM, &pThis->stOutBdle, sizeof(pThis->stOutBdle), fFlags, paFields, NULL);
2103 SSMR3GetStructEx(pSSM, &pThis->stMicBdle, sizeof(pThis->stMicBdle), fFlags, paFields, NULL);
2104 rc = SSMR3GetStructEx(pSSM, &pThis->stInBdle, sizeof(pThis->stInBdle), fFlags, paFields, NULL);
2105 AssertRCReturn(rc, rc);
2106
2107 /*
2108 * Update stuff after the state changes.
2109 */
2110 AUD_set_active_in(pThis->Codec.SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2111 AUD_set_active_out(pThis->Codec.SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2112
2113 pThis->u64CORBBase = RT_MAKE_U64(CORBLBASE(pThis), CORBUBASE(pThis));
2114 pThis->u64RIRBBase = RT_MAKE_U64(RIRLBASE(pThis), RIRUBASE(pThis));
2115 pThis->u64DPBase = RT_MAKE_U64(DPLBASE(pThis), DPUBASE(pThis));
2116 return VINF_SUCCESS;
2117}
2118
2119
2120/* Debug and log type formatters. */
2121
2122/**
2123 * @callback_method_impl{FNRTSTRFORMATTYPE}
2124 */
2125static DECLCALLBACK(size_t)
2126hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2127 const char *pszType, void const *pvValue,
2128 int cchWidth, int cchPrecision, unsigned fFlags,
2129 void *pvUser)
2130{
2131 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
2132 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2133 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
2134 sdCtl,
2135 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> ICH6_HDA_SDCTL_NUM_SHIFT,
2136 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
2137 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
2138 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> ICH6_HDA_SDCTL_STRIPE_SHIFT,
2139 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
2140 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
2141 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
2142 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
2143}
2144
2145/**
2146 * @callback_method_impl{FNRTSTRFORMATTYPE}
2147 */
2148static DECLCALLBACK(size_t)
2149hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2150 const char *pszType, void const *pvValue,
2151 int cchWidth, int cchPrecision, unsigned fFlags,
2152 void *pvUser)
2153{
2154 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
2155 uint32_t cb;
2156 switch (uSdFifos)
2157 {
2158 case HDA_SDONFIFO_16B: cb = 16; break;
2159 case HDA_SDONFIFO_32B: cb = 32; break;
2160 case HDA_SDONFIFO_64B: cb = 64; break;
2161 case HDA_SDONFIFO_128B: cb = 128; break;
2162 case HDA_SDONFIFO_192B: cb = 192; break;
2163 case HDA_SDONFIFO_256B: cb = 256; break;
2164 case HDA_SDINFIFO_120B: cb = 120; break;
2165 case HDA_SDINFIFO_160B: cb = 160; break;
2166 default: cb = 0; break;
2167 }
2168 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
2169}
2170
2171/**
2172 * @callback_method_impl{FNRTSTRFORMATTYPE}
2173 */
2174static DECLCALLBACK(size_t)
2175hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2176 const char *pszType, void const *pvValue,
2177 int cchWidth, int cchPrecision, unsigned fFlags,
2178 void *pvUser)
2179{
2180 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
2181 uint32_t cb;
2182 switch (uSdFifos)
2183 {
2184 case HDA_SDFIFOW_8B: cb = 8; break;
2185 case HDA_SDFIFOW_16B: cb = 16; break;
2186 case HDA_SDFIFOW_32B: cb = 32; break;
2187 default: cb = 0; break;
2188 }
2189 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
2190}
2191
2192/**
2193 * @callback_method_impl{FNRTSTRFORMATTYPE}
2194 */
2195static DECLCALLBACK(size_t)
2196hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2197 const char *pszType, void const *pvValue,
2198 int cchWidth, int cchPrecision, unsigned fFlags,
2199 void *pvUser)
2200{
2201 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
2202 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2203 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
2204 uSdSts,
2205 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
2206 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
2207 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
2208 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
2209}
2210
2211
2212static int hdaLookUpRegisterByName(INTELHDLinkState *pState, const char *pszArgs)
2213{
2214 int iReg = 0;
2215 for (; iReg < HDA_NREGS; ++iReg)
2216 if (!RTStrICmp(g_aIchIntelHDRegMap[iReg].abbrev, pszArgs))
2217 return iReg;
2218 return -1;
2219}
2220
2221
2222static void hdaDbgPrintRegister(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaIndex)
2223{
2224 Assert( pState
2225 && iHdaIndex >= 0
2226 && iHdaIndex < HDA_NREGS);
2227 pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", g_aIchIntelHDRegMap[iHdaIndex].abbrev, pState->au32Regs[iHdaIndex]);
2228}
2229
2230
2231/**
2232 * @callback_method_impl{FNDBGFHANDLERDEV}
2233 */
2234static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2235{
2236 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2237 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
2238 if (iHdaRegisterIndex != -1)
2239 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
2240 else
2241 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
2242 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
2243}
2244
2245
2246static void hdaDbgPrintStream(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
2247{
2248 Assert( pState
2249 && iHdaStrmIndex >= 0
2250 && iHdaStrmIndex < 7);
2251 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
2252 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, CTL, iHdaStrmIndex));
2253 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, STS, iHdaStrmIndex));
2254 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOS, iHdaStrmIndex));
2255 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOW, iHdaStrmIndex));
2256}
2257
2258
2259static int hdaLookUpStreamIndex(INTELHDLinkState *pState, const char *pszArgs)
2260{
2261 /* todo: add args parsing */
2262 return -1;
2263}
2264
2265
2266/**
2267 * @callback_method_impl{FNDBGFHANDLERDEV}
2268 */
2269static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2270{
2271 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2272 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
2273 if (iHdaStrmIndex != -1)
2274 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
2275 else
2276 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
2277 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
2278}
2279
2280/**
2281 * @callback_method_impl{FNDBGFHANDLERDEV}
2282 */
2283static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2284{
2285 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2286 if (pThis->Codec.pfnCodecDbgListNodes)
2287 pThis->Codec.pfnCodecDbgListNodes(&pThis->Codec, pHlp, pszArgs);
2288 else
2289 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2290}
2291
2292
2293/**
2294 * @callback_method_impl{FNDBGFHANDLERDEV}
2295 */
2296static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2297{
2298 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2299 if (pThis->Codec.pfnCodecDbgSelector)
2300 pThis->Codec.pfnCodecDbgSelector(&pThis->Codec, pHlp, pszArgs);
2301 else
2302 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2303}
2304
2305
2306/* PDMIBASE */
2307
2308/**
2309 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2310 */
2311static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
2312{
2313 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
2314 Assert(&pThis->IBase == pInterface);
2315
2316 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2317 return NULL;
2318}
2319
2320
2321/* PDMDEVREG */
2322
2323/**
2324 * Reset notification.
2325 *
2326 * @returns VBox status.
2327 * @param pDevIns The device instance data.
2328 *
2329 * @remark The original sources didn't install a reset handler, but it seems to
2330 * make sense to me so we'll do it.
2331 */
2332static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
2333{
2334 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2335 GCAP(pThis) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
2336 VMIN(pThis) = 0x00; /* see 6.2.2 */
2337 VMAJ(pThis) = 0x01; /* see 6.2.3 */
2338 VMAJ(pThis) = 0x01; /* see 6.2.3 */
2339 OUTPAY(pThis) = 0x003C; /* see 6.2.4 */
2340 INPAY(pThis) = 0x001D; /* see 6.2.5 */
2341 pThis->au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
2342 pThis->au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
2343 CORBRP(pThis) = 0x0;
2344 RIRBWP(pThis) = 0x0;
2345
2346 Log(("hda: inter HDA reset.\n"));
2347 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
2348
2349 if (pThis->pu32CorbBuf)
2350 memset(pThis->pu32CorbBuf, 0, pThis->cbCorbBuf);
2351 else
2352 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
2353
2354 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
2355 if (pThis->pu64RirbBuf)
2356 memset(pThis->pu64RirbBuf, 0, pThis->cbRirbBuf);
2357 else
2358 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
2359
2360 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2361
2362 HDABDLEDESC stEmptyBdle;
2363 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2364 {
2365 HDASTREAMTRANSFERDESC StreamDesc;
2366 PHDABDLEDESC pBdle = NULL;
2367 if (u8Strm == 0)
2368 pBdle = &pThis->stInBdle;
2369 else if(u8Strm == 4)
2370 pBdle = &pThis->stOutBdle;
2371 else
2372 {
2373 memset(&stEmptyBdle, 0, sizeof(HDABDLEDESC));
2374 pBdle = &stEmptyBdle;
2375 }
2376 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2377 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
2378 HDA_STREAM_REG2(pThis, CTL, u8Strm) = 0;
2379 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
2380 }
2381
2382 /* emulation of codec "wake up" (HDA spec 5.5.1 and 6.5)*/
2383 STATESTS(pThis) = 0x1;
2384
2385 Log(("hda: reset finished\n"));
2386}
2387
2388
2389/**
2390 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2391 */
2392static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
2393{
2394 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2395
2396 int rc = codecDestruct(&pThis->Codec);
2397 AssertRC(rc);
2398
2399 RTMemFree(pThis->pu32CorbBuf);
2400 pThis->pu32CorbBuf = NULL;
2401
2402 RTMemFree(pThis->pu64RirbBuf);
2403 pThis->pu64RirbBuf = NULL;
2404
2405 return VINF_SUCCESS;
2406}
2407
2408/**
2409 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2410 */
2411static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2412{
2413 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2414 int rc;
2415
2416 Assert(iInstance == 0);
2417 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2418
2419 /*
2420 * Validations.
2421 */
2422 if (!CFGMR3AreValuesValid(pCfgHandle, "\0"))
2423 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2424 N_ ("Invalid configuration for the Intel HDA device"));
2425
2426 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
2427 // poll some register(pThis).
2428
2429 /*
2430 * Initialize data (most of it anyway).
2431 */
2432 pThis->pDevIns = pDevIns;
2433 /* IBase */
2434 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
2435
2436 /* PCI Device */
2437 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
2438 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEICE_ID); /* HDA */
2439
2440 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
2441 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2442 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
2443 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
2444 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
2445 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2446 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
2447 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
2448 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2449 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
2450 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
2451
2452#if defined(HDA_AS_PCI_EXPRESS)
2453 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
2454#elif defined(VBOX_WITH_MSI_DEVICES)
2455 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
2456#else
2457 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
2458#endif
2459
2460 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2461 /// of these values needs to be properly documented!
2462 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2463 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
2464
2465 /* Power Management */
2466 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2467 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
2468 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2469
2470#ifdef HDA_AS_PCI_EXPRESS
2471 /* PCI Express */
2472 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2473 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
2474 /* Device flags */
2475 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
2476 /* version */ 0x1 |
2477 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2478 /* MSI */ (100) << 9 );
2479 /* Device capabilities */
2480 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2481 /* Device control */
2482 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
2483 /* Device status */
2484 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
2485 /* Link caps */
2486 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
2487 /* Link control */
2488 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
2489 /* Link status */
2490 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
2491 /* Slot capabilities */
2492 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
2493 /* Slot control */
2494 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
2495 /* Slot status */
2496 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
2497 /* Root control */
2498 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
2499 /* Root capabilities */
2500 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
2501 /* Root status */
2502 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
2503 /* Device capabilities 2 */
2504 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
2505 /* Device control 2 */
2506 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
2507 /* Link control 2 */
2508 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
2509 /* Slot control 2 */
2510 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
2511#endif
2512
2513 /*
2514 * Register the PCI device.
2515 */
2516 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
2517 if (RT_FAILURE(rc))
2518 return rc;
2519
2520 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
2521 if (RT_FAILURE(rc))
2522 return rc;
2523
2524#ifdef VBOX_WITH_MSI_DEVICES
2525 PDMMSIREG MsiReg;
2526 RT_ZERO(MsiReg);
2527 MsiReg.cMsiVectors = 1;
2528 MsiReg.iMsiCapOffset = 0x60;
2529 MsiReg.iMsiNextOffset = 0x50;
2530 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
2531 if (RT_FAILURE(rc))
2532 {
2533 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2534 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
2535 }
2536#endif
2537
2538 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2539 if (RT_FAILURE(rc))
2540 return rc;
2541
2542 /*
2543 * Attach driver.
2544 */
2545 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Audio Driver Port");
2546 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2547 Log(("hda: No attached driver!\n"));
2548 else if (RT_FAILURE(rc))
2549 {
2550 AssertMsgFailed(("Failed to attach Intel HDA LUN #0! rc=%Rrc\n", rc));
2551 return rc;
2552 }
2553
2554 pThis->Codec.pvHDAState = pThis;
2555 rc = codecConstruct(pDevIns, &pThis->Codec, pCfgHandle);
2556 if (RT_FAILURE(rc))
2557 AssertRCReturn(rc, rc);
2558
2559 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2560 verb F20 should provide device/codec recognition. */
2561 Assert(pThis->Codec.u16VendorId);
2562 Assert(pThis->Codec.u16DeviceId);
2563 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->Codec.u16VendorId); /* 2c ro - intel.) */
2564 PCIDevSetSubSystemId( &pThis->PciDev, pThis->Codec.u16DeviceId); /* 2e ro. */
2565
2566 hdaReset(pDevIns);
2567 pThis->Codec.id = 0;
2568 pThis->Codec.pfnTransfer = hdaTransfer;
2569 pThis->Codec.pfnReset = hdaCodecReset;
2570
2571 /*
2572 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2573 * hdaReset shouldn't affects these registers.
2574 */
2575 WAKEEN(pThis) = 0x0;
2576 STATESTS(pThis) = 0x0;
2577
2578 /*
2579 * Debug and string formatter types.
2580 */
2581 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
2582 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
2583 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
2584 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
2585
2586 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
2587 AssertRC(rc);
2588 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
2589 AssertRC(rc);
2590 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
2591 AssertRC(rc);
2592 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
2593 AssertRC(rc);
2594#if 0
2595 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
2596 AssertRC(rc);
2597#endif
2598
2599 return VINF_SUCCESS;
2600}
2601
2602/**
2603 * The device registration structure.
2604 */
2605const PDMDEVREG g_DeviceICH6_HDA =
2606{
2607 /* u32Version */
2608 PDM_DEVREG_VERSION,
2609 /* szName */
2610 "hda",
2611 /* szRCMod */
2612 "",
2613 /* szR0Mod */
2614 "",
2615 /* pszDescription */
2616 "Intel HD Audio Controller",
2617 /* fFlags */
2618 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2619 /* fClass */
2620 PDM_DEVREG_CLASS_AUDIO,
2621 /* cMaxInstances */
2622 1,
2623 /* cbInstance */
2624 sizeof(HDASTATE),
2625 /* pfnConstruct */
2626 hdaConstruct,
2627 /* pfnDestruct */
2628 hdaDestruct,
2629 /* pfnRelocate */
2630 NULL,
2631 /* pfnIOCtl */
2632 NULL,
2633 /* pfnPowerOn */
2634 NULL,
2635 /* pfnReset */
2636 hdaReset,
2637 /* pfnSuspend */
2638 NULL,
2639 /* pfnResume */
2640 NULL,
2641 /* pfnAttach */
2642 NULL,
2643 /* pfnDetach */
2644 NULL,
2645 /* pfnQueryInterface. */
2646 NULL,
2647 /* pfnInitComplete */
2648 NULL,
2649 /* pfnPowerOff */
2650 NULL,
2651 /* pfnSoftReset */
2652 NULL,
2653 /* u32VersionEnd */
2654 PDM_DEVREG_VERSION
2655};
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