VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 44646

Last change on this file since 44646 was 44646, checked in by vboxsync, 12 years ago

DevIchIntelHDA.cpp: Last batch of cleanups.
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1/* $Id: DevIchIntelHDA.cpp 44646 2013-02-11 20:07:44Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/vmm/pdmdev.h>
23#include <VBox/version.h>
24
25#include <iprt/assert.h>
26#include <iprt/uuid.h>
27#include <iprt/string.h>
28#include <iprt/mem.h>
29#include <iprt/asm.h>
30#include <iprt/asm-math.h>
31
32#include "VBoxDD.h"
33
34extern "C" {
35#include "audio.h"
36}
37#include "DevCodec.h"
38
39
40/*******************************************************************************
41* Defined Constants And Macros *
42*******************************************************************************/
43//#define HDA_AS_PCI_EXPRESS
44#define VBOX_WITH_INTEL_HDA
45
46#if defined(VBOX_WITH_HP_HDA)
47/* HP Pavilion dv4t-1300 */
48# define HDA_PCI_VENDOR_ID 0x103c
49# define HDA_PCI_DEICE_ID 0x30f7
50#elif defined(VBOX_WITH_INTEL_HDA)
51/* Intel HDA controller */
52# define HDA_PCI_VENDOR_ID 0x8086
53# define HDA_PCI_DEICE_ID 0x2668
54#elif defined(VBOX_WITH_NVIDIA_HDA)
55/* nVidia HDA controller */
56# define HDA_PCI_VENDOR_ID 0x10de
57# define HDA_PCI_DEICE_ID 0x0ac0
58#else
59# error "Please specify your HDA device vendor/device IDs"
60#endif
61
62#define HDA_NREGS 112
63/* Registers */
64#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
65#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
66#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
67#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
68#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
69#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[(x)])
70#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
71#define HDA_REG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
72#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
73#define HDA_REG_SVALUE(pThis, reg, val) (HDA_REG_VALUE(pThis, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
74
75#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
76#define GCAP(pThis) (HDA_REG((pThis), GCAP))
77/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
78 * oss (15:12) - number of output streams supported
79 * iss (11:8) - number of input streams supported
80 * bss (7:3) - number of bidirectional streams supported
81 * bds (2:1) - number of serial data out signals supported
82 * b64sup (0) - 64 bit addressing supported.
83 */
84#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
85 ( (((oss) & 0xF) << 12) \
86 | (((iss) & 0xF) << 8) \
87 | (((bss) & 0x1F) << 3) \
88 | (((bds) & 0x3) << 2) \
89 | ((b64sup) & 1))
90#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
91#define VMIN(pThis) (HDA_REG((pThis), VMIN))
92
93#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
94#define VMAJ(pThis) (HDA_REG((pThis), VMAJ))
95
96#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
97#define OUTPAY(pThis) (HDA_REG((pThis), OUTPAY))
98
99#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
100#define INPAY(pThis) (HDA_REG((pThis), INPAY))
101
102#define ICH6_HDA_REG_GCTL (5)
103#define ICH6_HDA_GCTL_RST_SHIFT (0)
104#define ICH6_HDA_GCTL_FSH_SHIFT (1)
105#define ICH6_HDA_GCTL_UR_SHIFT (8)
106#define GCTL(pThis) (HDA_REG((pThis), GCTL))
107
108#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
109#define WAKEEN(pThis) (HDA_REG((pThis), WAKEEN))
110
111#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
112#define STATESTS(pThis) (HDA_REG((pThis), STATESTS))
113#define ICH6_HDA_STATES_SCSF 0x7
114
115#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
116#define ICH6_HDA_GSTS_FSH_SHIFT (1)
117#define GSTS(pThis) (HDA_REG(pThis, GSTS))
118
119#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
120#define ICH6_HDA_INTCTL_GIE_SHIFT 31
121#define ICH6_HDA_INTCTL_CIE_SHIFT 30
122#define ICH6_HDA_INTCTL_S0_SHIFT (0)
123#define ICH6_HDA_INTCTL_S1_SHIFT (1)
124#define ICH6_HDA_INTCTL_S2_SHIFT (2)
125#define ICH6_HDA_INTCTL_S3_SHIFT (3)
126#define ICH6_HDA_INTCTL_S4_SHIFT (4)
127#define ICH6_HDA_INTCTL_S5_SHIFT (5)
128#define ICH6_HDA_INTCTL_S6_SHIFT (6)
129#define ICH6_HDA_INTCTL_S7_SHIFT (7)
130#define INTCTL(pThis) (HDA_REG((pThis), INTCTL))
131#define INTCTL_GIE(pThis) (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
132#define INTCTL_CIE(pThis) (HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE))
133#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
134#define INTCTL_SALL(pThis) (INTCTL((pThis)) & 0xFF)
135
136/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
137 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
138 * the datasheet.
139 */
140#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
141#define SSYNC(pThis) (HDA_REG((pThis), SSYNC))
142
143#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
144#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
145#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
146#define ICH6_HDA_INTSTS_S0_SHIFT (0)
147#define ICH6_HDA_INTSTS_S1_SHIFT (1)
148#define ICH6_HDA_INTSTS_S2_SHIFT (2)
149#define ICH6_HDA_INTSTS_S3_SHIFT (3)
150#define ICH6_HDA_INTSTS_S4_SHIFT (4)
151#define ICH6_HDA_INTSTS_S5_SHIFT (5)
152#define ICH6_HDA_INTSTS_S6_SHIFT (6)
153#define ICH6_HDA_INTSTS_S7_SHIFT (7)
154#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
155#define INTSTS(pThis) (HDA_REG((pThis), INTSTS))
156#define INTSTS_GIS(pThis) (HDA_REG_FLAG_VALUE((pThis), INTSTS, GIS)
157#define INTSTS_CIS(pThis) (HDA_REG_FLAG_VALUE((pThis), INTSTS, CIS)
158#define INTSTS_SX(pThis, X) (HDA_REG_FLAG_VALUE(pThis), INTSTS, S##X)
159#define INTSTS_SANY(pThis) (INTSTS((pThis)) & 0xFF)
160
161#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
162#define CORBLBASE(pThis) (HDA_REG((pThis), CORBLBASE))
163#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
164#define CORBUBASE(pThis) (HDA_REG((pThis), CORBUBASE))
165#define ICH6_HDA_REG_CORBWP 15 /* 48 */
166#define ICH6_HDA_REG_CORBRP 16 /* 4A */
167#define ICH6_HDA_CORBRP_RST_SHIFT 15
168#define ICH6_HDA_CORBRP_WP_SHIFT 0
169#define ICH6_HDA_CORBRP_WP_MASK 0xFF
170
171#define CORBRP(pThis) (HDA_REG(pThis, CORBRP))
172#define CORBWP(pThis) (HDA_REG(pThis, CORBWP))
173
174#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
175#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
176#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
177
178#define CORBCTL(pThis) (HDA_REG(pThis, CORBCTL))
179
180
181#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
182#define CORBSTS(pThis) (HDA_REG(pThis, CORBSTS))
183#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
184
185#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
186#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
187#define ICH6_HDA_CORBSIZE_SZ 0x3
188#define CORBSIZE_SZ(pThis) (HDA_REG(pThis, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
189#define CORBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
190/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
191
192#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
193#define RIRLBASE(pThis) (HDA_REG((pThis), RIRLBASE))
194
195#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
196#define RIRUBASE(pThis) (HDA_REG((pThis), RIRUBASE))
197
198#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
199#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
200#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
201#define RIRBWP(pThis) (HDA_REG(pThis, RIRBWP))
202
203#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
204#define RINTCNT(pThis) (HDA_REG((pThis), RINTCNT))
205#define RINTCNT_N(pThis) (RINTCNT((pThis)) & 0xff)
206
207#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
208#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
209#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
210#define ICH6_HDA_ROI_DMA_SHIFT (2)
211#define RIRBCTL(pThis) (HDA_REG((pThis), RIRBCTL))
212#define RIRBCTL_RIRB_RIC(pThis) (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
213#define RIRBCTL_RIRB_DMA(pThis) (HDA_REG_FLAG_VALUE((pThis), RIRBCTL, DMA)
214#define RIRBCTL_ROI(pThis) (HDA_REG_FLAG_VALUE((pThis), RIRBCTL, ROI))
215
216#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
217#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
218#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
219#define RIRBSTS(pThis) (HDA_REG(pThis, RIRBSTS))
220#define RIRBSTS_RINTFL(pThis) (HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL))
221#define RIRBSTS_RIRBOIS(pThis) (HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS))
222
223#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
224#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
225#define ICH6_HDA_RIRBSIZE_SZ 0x3
226
227#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
228#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
229
230
231#define ICH6_HDA_REG_IC 27 /* 0x60 */
232#define IC(pThis) (HDA_REG(pThis, IC))
233#define ICH6_HDA_REG_IR 28 /* 0x64 */
234#define IR(pThis) (HDA_REG(pThis, IR))
235#define ICH6_HDA_REG_IRS 29 /* 0x68 */
236#define ICH6_HDA_IRS_ICB_SHIFT (0)
237#define ICH6_HDA_IRS_IRV_SHIFT (1)
238#define IRS(pThis) (HDA_REG(pThis, IRS))
239#define IRS_ICB(pThis) (HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
240#define IRS_IRV(pThis) (HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
241
242#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
243#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
244#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
245#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
246#define DPBASE_ENABLED 1
247#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
248
249#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
250#define HDA_STREAM_REG(pThis, name, num) (HDA_REG((pThis), N_(HDA_STREAM_REG_DEF(name, num))))
251/* Note: sdnum here _MUST_ be stream reg number [0,7] */
252#define HDA_STREAM_REG2(pThis, name, sdnum) (HDA_REG_IND((pThis), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
253
254#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
255#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
256#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
257#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
258#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
259#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
260#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
261#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
262
263#define SD(func, num) SD##num##func
264#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
265#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
266#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
267#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
268#define ICH6_HDA_SDCTL_DIR_SHIFT (19)
269#define ICH6_HDA_SDCTL_TP_SHIFT (18)
270#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)
271#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)
272#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
273#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
274#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
275#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
276#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
277
278#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
279#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
280#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
281#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
282#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
283#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
284#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
285#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
286
287#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
288#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
289#define ICH6_HDA_SDSTS_DE_SHIFT (4)
290#define ICH6_HDA_SDSTS_FE_SHIFT (3)
291#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
292
293#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
294#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
295#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
296#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
297#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
298#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
299#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
300#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
301
302#define SDLPIB(pThis, num) HDA_REG((pThis), SD(LPIB, num))
303
304#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
305#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
306#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
307#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
308#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
309#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
310#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
311#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
312
313#define SDLCBL(pThis, num) HDA_REG((pThis), SD(CBL, num))
314
315#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
316#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
317#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
318#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
319#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
320#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
321#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
322#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
323
324#define SDLVI(pThis, num) HDA_REG((pThis), SD(LVI, num))
325
326#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
327#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
328#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
329#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
330#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
331#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
332#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
333#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
334
335/*
336 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
337 */
338#define HDA_SDFIFOW_8B (0x2)
339#define HDA_SDFIFOW_16B (0x3)
340#define HDA_SDFIFOW_32B (0x4)
341#define SDFIFOW(pThis, num) HDA_REG((pThis), SD(FIFOW, num))
342
343#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
344#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
345#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
346#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
347#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
348#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
349#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
350#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
351
352/*
353 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
354 * formula: size - 1
355 * Other values not listed are not supported.
356 */
357#define HDA_SDONFIFO_16B (0x0F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
358#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
359#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
360#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
361#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
362#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
363#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
364#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
365#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
366
367#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
368#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
369#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
370#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
371#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
372#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
373#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
374#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
375
376#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
377#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
378#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
379#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
380#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
381#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
382#define ICH6_HDA_SDFMT_BITS_SHIFT (4)
383#define ICH6_HDA_SDFMT_BITS_MASK (0x7)
384#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
385#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
386#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
387
388#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
389#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
390#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
391#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
392#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
393#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
394#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
395#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
396
397#define SDBDPL(pThis, num) HDA_REG((pThis), SD(BDPL, num))
398
399#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
400#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
401#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
402#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
403#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
404#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
405#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
406#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
407
408#define SDBDPU(pThis, num) HDA_REG((pThis), SD(BDPU, num))
409
410
411/*******************************************************************************
412* Structures and Typedefs *
413*******************************************************************************/
414typedef struct HDABDLEDESC
415{
416 uint64_t u64BdleCviAddr;
417 uint32_t u32BdleMaxCvi;
418 uint32_t u32BdleCvi;
419 uint32_t u32BdleCviLen;
420 uint32_t u32BdleCviPos;
421 bool fBdleCviIoc;
422 uint32_t cbUnderFifoW;
423 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
424} HDABDLEDESC, *PHDABDLEDESC;
425
426typedef struct HDASTREAMTRANSFERDESC
427{
428 uint64_t u64BaseDMA;
429 uint32_t u32Ctl;
430 uint32_t *pu32Sts;
431 uint8_t u8Strm;
432 uint32_t *pu32Lpib;
433 uint32_t u32Cbl;
434 uint32_t u32Fifos;
435} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
436
437/**
438 * ICH Intel HD Audio Controller state.
439 */
440typedef struct HDASTATE
441{
442 /** The PCI device structure. */
443 PCIDevice PciDev;
444 /** Pointer to the device instance. */
445 PPDMDEVINSR3 pDevIns;
446 /** Pointer to the connector of the attached audio driver. */
447 PPDMIAUDIOCONNECTOR pDrv;
448 /** Pointer to the attached audio driver. */
449 PPDMIBASE pDrvBase;
450 /** The base interface for LUN\#0. */
451 PDMIBASE IBase;
452 RTGCPHYS MMIOBaseAddr;
453 uint32_t au32Regs[HDA_NREGS];
454 HDABDLEDESC StInBdle;
455 HDABDLEDESC StOutBdle;
456 HDABDLEDESC StMicBdle;
457 /** Interrupt on completion */
458 bool fCviIoc;
459 uint64_t u64CORBBase;
460 uint64_t u64RIRBBase;
461 uint64_t u64DPBase;
462 /** pointer to CORB buf */
463 uint32_t *pu32CorbBuf;
464 /** size in bytes of CORB buf */
465 uint32_t cbCorbBuf;
466 /** pointer on RIRB buf */
467 uint64_t *pu64RirbBuf;
468 /** size in bytes of RIRB buf */
469 uint32_t cbRirbBuf;
470 /** indicates if HDA in reset. */
471 bool fInReset;
472 CODECState Codec;
473 /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
474 uint8_t u8Counter;
475 uint64_t u64BaseTS;
476} HDASTATE;
477/** Pointer to the ICH Intel HD Audio Controller state. */
478typedef HDASTATE *PHDASTATE;
479
480#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
481 ( AUDIO_FORMAT_SELECTOR(&(pThis)->Codec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
482#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
483 ( AUDIO_FORMAT_SELECTOR(&(pThis)->Codec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
484
485
486/*******************************************************************************
487* Internal Functions *
488*******************************************************************************/
489static FNPDMDEVRESET hdaReset;
490
491static int hdaRegReadUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
492static int hdaRegWriteUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
493static int hdaRegReadGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
494static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
495static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
496static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
497static int hdaRegReadGCAP(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
498static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
499static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
500static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
501static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
502static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
503static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
504static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
505static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
506static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
507static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
508static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
509static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
510static int hdaRegReadSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
511
512static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
513static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
514static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
515static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
516static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
517static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
518static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
519static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
520static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
521static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
522static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
523static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
524static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
525static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
526static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
527static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
528
529DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
530 PHDASTREAMTRANSFERDESC pStreamDesc);
531static int hdaMMIORegLookup(PHDASTATE pThis, uint32_t offReg);
532static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
533#ifdef LOG_ENABLED
534static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
535#endif
536
537
538/*******************************************************************************
539* Global Variables *
540*******************************************************************************/
541/* see 302349 p 6.2*/
542static const struct
543{
544 /** Register offset in the register space. */
545 uint32_t offset;
546 /** Size in bytes. Registers of size > 4 are in fact tables. */
547 uint32_t size;
548 /** Readable bits. */
549 uint32_t readable;
550 /** Writable bits. */
551 uint32_t writable;
552 /** Read callback. */
553 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
554 /** Write callback. */
555 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
556 /** Abbreviated name. */
557 const char *abbrev;
558 /** Full name. */
559 const char *name;
560} g_aIchIntelHDRegMap[HDA_NREGS] =
561{
562 /* offset size read mask write mask read callback write callback abbrev full name */
563 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
564 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
565 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
566 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
567 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
568 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
569 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
570 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
571 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
572 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
573 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
574 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
575 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
576 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
577 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
578 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
579 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
580 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
581 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
582 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
583 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
584 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
585 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
586 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
587 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
588 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
589 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
590 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
591 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
592 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
593 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
594 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
595 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
596 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
597
598 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
599 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
600 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
601 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
602 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
603 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
604 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
605 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
606 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
607 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
608
609 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
610 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
611 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
612 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
613 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
614 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
615 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
616 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
617 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
618 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
619
620 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
621 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
622 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
623 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
624 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
625 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
626 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
627 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
628 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
629 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
630
631 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
632 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
633 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
634 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
635 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
636 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
637 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
638 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
639 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
640 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
641
642 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
643 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
644 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
645 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
646 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
647 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
648 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
649 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
650 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
651 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
652
653 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
654 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
655 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
656 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
657 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
658 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
659 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
660 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
661 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
662 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
663
664 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
665 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
666 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
667 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
668 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
669 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
670 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
671 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
672 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
673 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
674
675 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
676 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
677 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
678 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
679 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
680 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
681 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
682 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
683 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
684 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
685};
686
687/** HDABDLEDESC field descriptors the v3+ saved state. */
688static SSMFIELD const g_aHdaBDLEDescFields[] =
689{
690 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
691 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
692 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
693 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
694 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
695 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
696 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
697 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
698 SSMFIELD_ENTRY_TERM()
699};
700
701/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
702static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
703{
704 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
705 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
706 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
707 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
708 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
709 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
710 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
711 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
712 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
713 SSMFIELD_ENTRY_TERM()
714};
715
716
717DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
718{
719 if (pThis->u64DPBase & DPBASE_ENABLED)
720 PDMDevHlpPhysWrite(pThis->pDevIns,
721 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
722 pStreamDesc->pu32Lpib, sizeof(uint32_t));
723}
724DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
725{
726#if 0
727 switch(HDA_STREAM_REG2(pThis, FIFOW, pStreamDesc->u8Strm))
728 {
729 case HDA_SDFIFOW_8B: return 8;
730 case HDA_SDFIFOW_16B: return 16;
731 case HDA_SDFIFOW_32B: return 32;
732 default:
733 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
734 }
735#endif
736 return 0;
737}
738
739static int hdaProcessInterrupt(PHDASTATE pThis)
740{
741#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
742 ( INTCTL_SX((pThis), num) \
743 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
744 bool fIrq = false;
745 if ( INTCTL_CIE(pThis)
746 && ( RIRBSTS_RINTFL(pThis)
747 || RIRBSTS_RIRBOIS(pThis)
748 || (STATESTS(pThis) & WAKEEN(pThis))))
749 fIrq = true;
750
751 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
752 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
753 fIrq = true;
754
755 if (INTCTL_GIE(pThis))
756 {
757 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
758 PDMDevHlpPCISetIrq(pThis->pDevIns, 0 , fIrq);
759 }
760 return VINF_SUCCESS;
761}
762
763static int hdaMMIORegLookup(PHDASTATE pThis, uint32_t offReg)
764{
765 /*
766 * Aliases HDA spec 3.3.45
767 */
768 switch (offReg)
769 {
770 case 0x2084:
771 return HDA_REG_IND_NAME(SD0LPIB);
772 case 0x20A4:
773 return HDA_REG_IND_NAME(SD1LPIB);
774 case 0x20C4:
775 return HDA_REG_IND_NAME(SD2LPIB);
776 case 0x20E4:
777 return HDA_REG_IND_NAME(SD3LPIB);
778 case 0x2104:
779 return HDA_REG_IND_NAME(SD4LPIB);
780 case 0x2124:
781 return HDA_REG_IND_NAME(SD5LPIB);
782 case 0x2144:
783 return HDA_REG_IND_NAME(SD6LPIB);
784 case 0x2164:
785 return HDA_REG_IND_NAME(SD7LPIB);
786 }
787
788 /*
789 * Binary search the
790 */
791 int idxHigh = RT_ELEMENTS(g_aIchIntelHDRegMap);
792 int idxLow = 0;
793 for (;;)
794 {
795#ifdef DEBUG_vvl
796 Assert( idxHigh >= 0
797 && idxLow >= 0);
798#endif
799 if ( idxHigh < idxLow
800 || idxHigh < 0)
801 break;
802 int idxMiddle = idxLow + (idxHigh - idxLow) / 2;
803 if (offReg < g_aIchIntelHDRegMap[idxMiddle].offset)
804 idxHigh = idxMiddle - 1;
805 else if (offReg >= g_aIchIntelHDRegMap[idxMiddle].offset + g_aIchIntelHDRegMap[idxMiddle].size)
806 idxLow = idxMiddle + 1;
807 else if ( offReg >= g_aIchIntelHDRegMap[idxMiddle].offset
808 && offReg < g_aIchIntelHDRegMap[idxMiddle].offset + g_aIchIntelHDRegMap[idxMiddle].size)
809 return idxMiddle;
810 }
811 return -1;
812}
813
814static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
815{
816 int rc = VINF_SUCCESS;
817 if (fLocal)
818 {
819 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
820 rc = PDMDevHlpPhysRead(pThis->pDevIns, pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
821 if (RT_FAILURE(rc))
822 AssertRCReturn(rc, rc);
823#ifdef DEBUG_CMD_BUFFER
824 uint8_t i = 0;
825 do
826 {
827 Log(("hda: corb%02x: ", i));
828 uint8_t j = 0;
829 do
830 {
831 const char *prefix;
832 if ((i + j) == CORBRP(pThis))
833 prefix = "[R]";
834 else if ((i + j) == CORBWP(pThis))
835 prefix = "[W]";
836 else
837 prefix = " "; /* three spaces */
838 Log(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
839 j++;
840 } while (j < 8);
841 Log(("\n"));
842 i += 8;
843 } while(i != 0);
844#endif
845 }
846 else
847 {
848 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
849 rc = PDMDevHlpPhysWrite(pThis->pDevIns, pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
850 if (RT_FAILURE(rc))
851 AssertRCReturn(rc, rc);
852#ifdef DEBUG_CMD_BUFFER
853 uint8_t i = 0;
854 do {
855 Log(("hda: rirb%02x: ", i));
856 uint8_t j = 0;
857 do {
858 const char *prefix;
859 if ((i + j) == RIRBWP(pThis))
860 prefix = "[W]";
861 else
862 prefix = " ";
863 Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
864 } while (++j < 8);
865 Log(("\n"));
866 i += 8;
867 } while (i != 0);
868#endif
869 }
870 return rc;
871}
872
873static int hdaCORBCmdProcess(PHDASTATE pThis)
874{
875 int rc;
876 uint8_t corbRp;
877 uint8_t corbWp;
878 uint8_t rirbWp;
879
880 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
881
882 rc = hdaCmdSync(pThis, true);
883 if (RT_FAILURE(rc))
884 AssertRCReturn(rc, rc);
885 corbRp = CORBRP(pThis);
886 corbWp = CORBWP(pThis);
887 rirbWp = RIRBWP(pThis);
888 Assert((corbWp != corbRp));
889 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pThis), CORBWP(pThis), RIRBWP(pThis)));
890 while (corbRp != corbWp)
891 {
892 uint32_t cmd;
893 uint64_t resp;
894 pfn = (PFNCODECVERBPROCESSOR)NULL;
895 corbRp++;
896 cmd = pThis->pu32CorbBuf[corbRp];
897 rc = pThis->Codec.pfnLookup(&pThis->Codec, cmd, &pfn);
898 if (RT_FAILURE(rc))
899 AssertRCReturn(rc, rc);
900 Assert(pfn);
901 (rirbWp)++;
902
903 if (RT_LIKELY(pfn))
904 rc = pfn(&pThis->Codec, cmd, &resp);
905 else
906 rc = VERR_INVALID_FUNCTION;
907
908 if (RT_FAILURE(rc))
909 AssertRCReturn(rc, rc);
910 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
911 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
912 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
913 {
914 Log(("hda: unexpected unsolicited response.\n"));
915 pThis->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
916 return rc;
917 }
918 pThis->pu64RirbBuf[rirbWp] = resp;
919 pThis->u8Counter++;
920 if (pThis->u8Counter == RINTCNT_N(pThis))
921 break;
922 }
923 pThis->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
924 pThis->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
925 rc = hdaCmdSync(pThis, false);
926 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pThis), CORBWP(pThis), RIRBWP(pThis)));
927 if (RIRBCTL_RIRB_RIC(pThis))
928 {
929 RIRBSTS((pThis)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
930 pThis->u8Counter = 0;
931 rc = hdaProcessInterrupt(pThis);
932 }
933 if (RT_FAILURE(rc))
934 AssertRCReturn(rc, rc);
935 return rc;
936}
937
938static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
939{
940 Log(("hda: reset of stream (%d) started\n", u8Strm));
941 Assert(( pThis
942 && pBdle
943 && pStreamDesc
944 && u8Strm <= 7));
945 memset(pBdle, 0, sizeof(HDABDLEDESC));
946 *pStreamDesc->pu32Lpib = 0;
947 *pStreamDesc->pu32Sts = 0;
948 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
949 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
950 HDA_STREAM_REG2(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
951
952 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
953 HDA_STREAM_REG2(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
954 HDA_STREAM_REG2(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
955 HDA_STREAM_REG2(pThis, CBL, u8Strm) = 0;
956 HDA_STREAM_REG2(pThis, LVI, u8Strm) = 0;
957 HDA_STREAM_REG2(pThis, FMT, u8Strm) = 0;
958 HDA_STREAM_REG2(pThis, BDPU, u8Strm) = 0;
959 HDA_STREAM_REG2(pThis, BDPL, u8Strm) = 0;
960 Log(("hda: reset of stream (%d) finished\n", u8Strm));
961}
962
963
964/* Register access handlers. */
965
966static int hdaRegReadUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
967{
968 *pu32Value = 0;
969 return VINF_SUCCESS;
970}
971
972static int hdaRegWriteUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
973{
974 return VINF_SUCCESS;
975}
976
977/* U8 */
978static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
979{
980 Assert(((pThis->au32Regs[iReg] & g_aIchIntelHDRegMap[iReg].readable) & 0xffffff00) == 0);
981 return hdaRegReadU32(pThis, iReg, pu32Value);
982}
983
984static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
985{
986 Assert((u32Value & 0xffffff00) == 0);
987 return hdaRegWriteU32(pThis, iReg, u32Value);
988}
989
990/* U16 */
991static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
992{
993 Assert(((pThis->au32Regs[iReg] & g_aIchIntelHDRegMap[iReg].readable) & 0xffff0000) == 0);
994 return hdaRegReadU32(pThis, iReg, pu32Value);
995}
996
997static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
998{
999 Assert((u32Value & 0xffff0000) == 0);
1000 return hdaRegWriteU32(pThis, iReg, u32Value);
1001}
1002
1003/* U24 */
1004static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1005{
1006 Assert(((pThis->au32Regs[iReg] & g_aIchIntelHDRegMap[iReg].readable) & 0xff000000) == 0);
1007 return hdaRegReadU32(pThis, iReg, pu32Value);
1008}
1009
1010static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1011{
1012 Assert((u32Value & 0xff000000) == 0);
1013 return hdaRegWriteU32(pThis, iReg, u32Value);
1014}
1015
1016/* U32 */
1017static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1018{
1019 *pu32Value = pThis->au32Regs[iReg] & g_aIchIntelHDRegMap[iReg].readable;
1020 return VINF_SUCCESS;
1021}
1022
1023static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1024{
1025 pThis->au32Regs[iReg] = (u32Value & g_aIchIntelHDRegMap[iReg].writable)
1026 | (pThis->au32Regs[iReg] & ~g_aIchIntelHDRegMap[iReg].writable);
1027 return VINF_SUCCESS;
1028}
1029
1030static int hdaRegReadGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1031{
1032 return hdaRegReadU32(pThis, iReg, pu32Value);
1033}
1034
1035static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1036{
1037 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1038 {
1039 /* exit reset state */
1040 GCTL(pThis) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1041 pThis->fInReset = false;
1042 }
1043 else
1044 {
1045 /* enter reset state*/
1046 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1047 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1048 {
1049 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1050 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1051 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1052 }
1053 hdaReset(pThis->pDevIns);
1054 GCTL(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1055 pThis->fInReset = true;
1056 }
1057 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1058 {
1059 /* Flush: GSTS:1 set, see 6.2.6*/
1060 GSTS(pThis) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1061 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1062 }
1063 return VINF_SUCCESS;
1064}
1065
1066static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1067{
1068 uint32_t v = pThis->au32Regs[iReg];
1069 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
1070 pThis->au32Regs[iReg] &= ~(v & nv); /* write of 1 clears corresponding bit */
1071 return VINF_SUCCESS;
1072}
1073
1074static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1075{
1076 uint32_t v = 0;
1077 if ( RIRBSTS_RIRBOIS(pThis)
1078 || RIRBSTS_RINTFL(pThis)
1079 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1080 || STATESTS(pThis))
1081 v |= RT_BIT(30);
1082#define HDA_IS_STREAM_EVENT(pThis, stream) \
1083 ( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1084 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1085 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1086#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
1087 MARK_STREAM(pThis, 0, v);
1088 MARK_STREAM(pThis, 1, v);
1089 MARK_STREAM(pThis, 2, v);
1090 MARK_STREAM(pThis, 3, v);
1091 MARK_STREAM(pThis, 4, v);
1092 MARK_STREAM(pThis, 5, v);
1093 MARK_STREAM(pThis, 6, v);
1094 MARK_STREAM(pThis, 7, v);
1095 v |= v ? RT_BIT(31) : 0;
1096 *pu32Value = v;
1097 return VINF_SUCCESS;
1098}
1099
1100static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1101{
1102 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1103 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->pDevIns)
1104 - pThis->u64BaseTS, 24, 1000);
1105 return VINF_SUCCESS;
1106}
1107
1108static int hdaRegReadGCAP(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1109{
1110 return hdaRegReadU16(pThis, iReg, pu32Value);
1111}
1112
1113static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1114{
1115 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1116 CORBRP(pThis) = 0;
1117 else
1118 return hdaRegWriteU8(pThis, iReg, u32Value);
1119 return VINF_SUCCESS;
1120}
1121
1122static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1123{
1124 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1125 AssertRC(rc);
1126 if ( CORBWP(pThis) != CORBRP(pThis)
1127 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1128 return hdaCORBCmdProcess(pThis);
1129 return rc;
1130}
1131
1132static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1133{
1134 uint32_t v = CORBSTS(pThis);
1135 CORBSTS(pThis) &= ~(v & u32Value);
1136 return VINF_SUCCESS;
1137}
1138
1139static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1140{
1141 int rc;
1142 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1143 if (RT_FAILURE(rc))
1144 AssertRCReturn(rc, rc);
1145 if (CORBWP(pThis) == CORBRP(pThis))
1146 return VINF_SUCCESS;
1147 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1148 return VINF_SUCCESS;
1149 rc = hdaCORBCmdProcess(pThis);
1150 return rc;
1151}
1152
1153static int hdaRegReadSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1154{
1155 return hdaRegReadU24(pThis, iReg, pu32Value);
1156}
1157
1158static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1159{
1160 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1161 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1162 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1163 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1164 int rc = VINF_SUCCESS;
1165 if (fInReset)
1166 {
1167 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1168 * from reset
1169 */
1170 Assert((!fReset));
1171 Log(("hda: guest initiated exit of stream reset.\n"));
1172 goto l_done;
1173 }
1174 else if (fReset)
1175 {
1176 /*
1177 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1178 */
1179 uint8_t u8Strm = 0;
1180 PHDABDLEDESC pBdle = NULL;
1181 HDASTREAMTRANSFERDESC StreamDesc;
1182 Assert((!fInRun && !fRun));
1183 switch (iReg)
1184 {
1185 case ICH6_HDA_REG_SD0CTL:
1186 u8Strm = 0;
1187 pBdle = &pThis->StInBdle;
1188 break;
1189 case ICH6_HDA_REG_SD4CTL:
1190 u8Strm = 4;
1191 pBdle = &pThis->StOutBdle;
1192 break;
1193 default:
1194 Log(("hda: changing SRST bit on non-attached stream\n"));
1195 goto l_done;
1196 }
1197 Log(("hda: guest initiated enter to stream reset.\n"));
1198 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1199 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
1200 goto l_done;
1201 }
1202
1203 /* we enter here to change DMA states only */
1204 if ( (fInRun && !fRun)
1205 || (fRun && !fInRun))
1206 {
1207 Assert((!fReset && !fInReset));
1208 switch (iReg)
1209 {
1210 case ICH6_HDA_REG_SD0CTL:
1211 AUD_set_active_in(pThis->Codec.SwVoiceIn, fRun);
1212 break;
1213 case ICH6_HDA_REG_SD4CTL:
1214 AUD_set_active_out(pThis->Codec.SwVoiceOut, fRun);
1215 break;
1216 default:
1217 Log(("hda: changing RUN bit on non-attached stream\n"));
1218 goto l_done;
1219 }
1220 }
1221
1222l_done:
1223 rc = hdaRegWriteU24(pThis, iReg, u32Value);
1224 if (RT_FAILURE(rc))
1225 AssertRCReturn(rc, VINF_SUCCESS);
1226 return rc;
1227}
1228
1229static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1230{
1231 uint32_t v = HDA_REG_IND(pThis, iReg);
1232 v &= ~(u32Value & v);
1233 HDA_REG_IND(pThis, iReg) = v;
1234 hdaProcessInterrupt(pThis);
1235 return VINF_SUCCESS;
1236}
1237
1238static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1239{
1240 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1241 if (RT_FAILURE(rc))
1242 AssertRCReturn(rc, VINF_SUCCESS);
1243 return rc;
1244}
1245
1246static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1247{
1248 switch (u32Value)
1249 {
1250 case HDA_SDFIFOW_8B:
1251 case HDA_SDFIFOW_16B:
1252 case HDA_SDFIFOW_32B:
1253 return hdaRegWriteU16(pThis, iReg, u32Value);
1254 default:
1255 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1256 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1257 }
1258 return VINF_SUCCESS;
1259}
1260
1261/**
1262 * @note This method could be called for changing value on Output Streams
1263 * only (ICH6 datasheet 18.2.39)
1264 */
1265static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1266{
1267 switch (iReg)
1268 {
1269 /* SDInFIFOS is RO, n=0-3 */
1270 case ICH6_HDA_REG_SD0FIFOS:
1271 case ICH6_HDA_REG_SD1FIFOS:
1272 case ICH6_HDA_REG_SD2FIFOS:
1273 case ICH6_HDA_REG_SD3FIFOS:
1274 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1275 return VINF_SUCCESS;
1276 case ICH6_HDA_REG_SD4FIFOS:
1277 case ICH6_HDA_REG_SD5FIFOS:
1278 case ICH6_HDA_REG_SD6FIFOS:
1279 case ICH6_HDA_REG_SD7FIFOS:
1280 switch(u32Value)
1281 {
1282 case HDA_SDONFIFO_16B:
1283 case HDA_SDONFIFO_32B:
1284 case HDA_SDONFIFO_64B:
1285 case HDA_SDONFIFO_128B:
1286 case HDA_SDONFIFO_192B:
1287 return hdaRegWriteU16(pThis, iReg, u32Value);
1288
1289 case HDA_SDONFIFO_256B:
1290 Log(("hda: 256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1291 default:
1292 return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);
1293 }
1294 return VINF_SUCCESS;
1295 default:
1296 AssertMsgFailed(("Something weird happened with register lookup routine"));
1297 }
1298 return VINF_SUCCESS;
1299}
1300
1301static void hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1302{
1303 Assert((pAudSetting));
1304#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1305 uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1306 uint32_t u32HzMult = 1;
1307 uint32_t u32HzDiv = 1;
1308 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))
1309 {
1310 case 0: u32HzMult = 1; break;
1311 case 1: u32HzMult = 2; break;
1312 case 2: u32HzMult = 3; break;
1313 case 3: u32HzMult = 4; break;
1314 default:
1315 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1316 }
1317 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))
1318 {
1319 case 0: u32HzDiv = 1; break;
1320 case 1: u32HzDiv = 2; break;
1321 case 2: u32HzDiv = 3; break;
1322 case 3: u32HzDiv = 4; break;
1323 case 4: u32HzDiv = 5; break;
1324 case 5: u32HzDiv = 6; break;
1325 case 6: u32HzDiv = 7; break;
1326 case 7: u32HzDiv = 8; break;
1327 }
1328 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1329
1330 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_BITS_MASK, ICH6_HDA_SDFMT_BITS_SHIFT))
1331 {
1332 case 0:
1333 Log(("hda: %s requested 8-bit\n", __FUNCTION__));
1334 pAudSetting->fmt = AUD_FMT_S8;
1335 break;
1336 case 1:
1337 Log(("hda: %s requested 16-bit\n", __FUNCTION__));
1338 pAudSetting->fmt = AUD_FMT_S16;
1339 break;
1340 case 2:
1341 Log(("hda: %s requested 20-bit\n", __FUNCTION__));
1342 break;
1343 case 3:
1344 Log(("hda: %s requested 24-bit\n", __FUNCTION__));
1345 break;
1346 case 4:
1347 Log(("hda: %s requested 32-bit\n", __FUNCTION__));
1348 pAudSetting->fmt = AUD_FMT_S32;
1349 break;
1350 default:
1351 AssertMsgFailed(("Unsupported"));
1352 }
1353 pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;
1354 pAudSetting->fmt = AUD_FMT_S16;
1355 pAudSetting->endianness = 0;
1356#undef EXTRACT_VALUE
1357}
1358
1359static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1360{
1361#ifdef VBOX_WITH_HDA_CODEC_EMU
1362 /** @todo a bit more investigation is required here. */
1363 int rc = 0;
1364 audsettings_t as;
1365 /* no reason to reopen voice with same settings */
1366 if (u32Value == HDA_REG_IND(pThis, iReg))
1367 return VINF_SUCCESS;
1368 hdaSdFmtToAudSettings(u32Value, &as);
1369 switch (iReg)
1370 {
1371 case ICH6_HDA_REG_SD0FMT:
1372 rc = codecOpenVoice(&pThis->Codec, PI_INDEX, &as);
1373 break;
1374 case ICH6_HDA_REG_SD4FMT:
1375 rc = codecOpenVoice(&pThis->Codec, PO_INDEX, &as);
1376 break;
1377 default:
1378 Log(("HDA: attempt to change format on %d\n", iReg));
1379 rc = 0;
1380 }
1381 return hdaRegWriteU16(pThis, iReg, u32Value);
1382#else
1383 return hdaRegWriteU16(pThis, iReg, u32Value);
1384#endif
1385}
1386
1387static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1388{
1389 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1390 if (RT_FAILURE(rc))
1391 AssertRCReturn(rc, VINF_SUCCESS);
1392 return rc;
1393}
1394
1395static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1396{
1397 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1398 if (RT_FAILURE(rc))
1399 AssertRCReturn(rc, VINF_SUCCESS);
1400 return rc;
1401}
1402
1403static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1404{
1405 int rc = VINF_SUCCESS;
1406 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1407 if ( CORBWP(pThis) != CORBRP(pThis)
1408 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1409 IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1410
1411 rc = hdaRegReadU32(pThis, iReg, pu32Value);
1412 return rc;
1413}
1414
1415static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1416{
1417 int rc = VINF_SUCCESS;
1418 uint64_t resp;
1419 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1420 /*
1421 * if guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1422 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1423 */
1424 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1425 && !IRS_ICB(pThis))
1426 {
1427 uint32_t cmd = IC(pThis);
1428 if (CORBWP(pThis) != CORBRP(pThis))
1429 {
1430 /*
1431 * 3.4.3 defines behavior of immediate Command status register.
1432 */
1433 LogRel(("hda: guest attempted process immediate verb (%x) with active CORB\n", cmd));
1434 return rc;
1435 }
1436 IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1437 Log(("hda: IC:%x\n", cmd));
1438 rc = pThis->Codec.pfnLookup(&pThis->Codec, cmd, &pfn);
1439 if (RT_FAILURE(rc))
1440 AssertRCReturn(rc, rc);
1441 rc = pfn(&pThis->Codec, cmd, &resp);
1442 if (RT_FAILURE(rc))
1443 AssertRCReturn(rc, rc);
1444 IR(pThis) = (uint32_t)resp;
1445 Log(("hda: IR:%x\n", IR(pThis)));
1446 IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1447 IRS(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1448 return rc;
1449 }
1450 /*
1451 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1452 */
1453 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1454 && IRS_IRV(pThis))
1455 IRS(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1456 return rc;
1457}
1458
1459static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1460{
1461 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1462 {
1463 RIRBWP(pThis) = 0;
1464 }
1465 /* The remaining bits are O, see 6.2.22 */
1466 return VINF_SUCCESS;
1467}
1468
1469static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1470{
1471 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1472 if (RT_FAILURE(rc))
1473 AssertRCReturn(rc, rc);
1474 switch(iReg)
1475 {
1476 case ICH6_HDA_REG_CORBLBASE:
1477 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
1478 pThis->u64CORBBase |= pThis->au32Regs[iReg];
1479 break;
1480 case ICH6_HDA_REG_CORBUBASE:
1481 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
1482 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iReg] << 32);
1483 break;
1484 case ICH6_HDA_REG_RIRLBASE:
1485 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
1486 pThis->u64RIRBBase |= pThis->au32Regs[iReg];
1487 break;
1488 case ICH6_HDA_REG_RIRUBASE:
1489 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
1490 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iReg] << 32);
1491 break;
1492 case ICH6_HDA_REG_DPLBASE:
1493 /** @todo: first bit has special meaning */
1494 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
1495 pThis->u64DPBase |= pThis->au32Regs[iReg];
1496 break;
1497 case ICH6_HDA_REG_DPUBASE:
1498 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
1499 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iReg] << 32);
1500 break;
1501 default:
1502 AssertMsgFailed(("Invalid index"));
1503 }
1504 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
1505 return rc;
1506}
1507
1508static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1509{
1510 uint8_t v = RIRBSTS(pThis);
1511 RIRBSTS(pThis) &= ~(v & u32Value);
1512
1513 return hdaProcessInterrupt(pThis);
1514}
1515
1516#ifdef LOG_ENABLED
1517static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1518{
1519#if 0
1520 uint64_t addr;
1521 uint32_t len;
1522 uint32_t ioc;
1523 uint8_t bdle[16];
1524 uint32_t counter;
1525 uint32_t i;
1526 uint32_t sum = 0;
1527 Assert(pBdle && pBdle->u32BdleMaxCvi);
1528 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1529 {
1530 PDMDevHlpPhysRead(pThis->pDevIns, u64BaseDMA + i*16, bdle, 16);
1531 addr = *(uint64_t *)bdle;
1532 len = *(uint32_t *)&bdle[8];
1533 ioc = *(uint32_t *)&bdle[12];
1534 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1535 sum += len;
1536 }
1537 Log(("hda: sum: %d\n", sum));
1538 for (i = 0; i < 8; ++i)
1539 {
1540 PDMDevHlpPhysRead(pThis->pDevIns, (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1541 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
1542 i , counter));
1543 }
1544#endif
1545}
1546#endif
1547
1548static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1549{
1550 uint8_t bdle[16];
1551 Assert(( pStreamDesc->u64BaseDMA
1552 && pBdle
1553 && pBdle->u32BdleMaxCvi));
1554 PDMDevHlpPhysRead(pThis->pDevIns, pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1555 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1556 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1557 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1558#ifdef LOG_ENABLED
1559 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
1560#endif
1561}
1562
1563DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1564 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1565{
1566 uint32_t cb2Copy;
1567 /*
1568 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
1569 */
1570 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1571 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1572 /*
1573 * we may increase the counter in range of [0, FIFOS + 1]
1574 */
1575 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1576 Assert((u32SoundBackendBufferBytesAvail > 0));
1577
1578 /* sanity check to avoid overriding the backend audio buffer */
1579 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1580 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1581
1582 if (cb2Copy <= pBdle->cbUnderFifoW)
1583 return 0;
1584 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
1585 return cb2Copy;
1586}
1587
1588DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1589 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1590{
1591 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1592 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1593 Assert((cbCopied));
1594 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1595 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
1596 * Probably we need to move the buffer, but it is rather hard to imagine a situation
1597 * where it might happen.
1598 */
1599 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write the entire buffer including unreported bytes */
1600 if ( pBdle->cbUnderFifoW
1601 && pBdle->cbUnderFifoW <= cbCopied)
1602 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1603
1604 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1605 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
1606
1607 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
1608 pBdle->u32BdleCviPos += cbArranged2Copy;
1609
1610 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1611 /* We report all bytes (including previously unreported bytes) */
1612 *pu32DMACursor += cbCopied;
1613 /* Decrease the backend counter by the number of bytes we copied to the backend */
1614 *pu32BackendBufferCapacity -= cbCopied;
1615 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1616 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1617}
1618
1619DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1620 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1621{
1622 Assert((cbCopied, cbArranged2Copy));
1623 *pu32BackendBufferCapacity -= cbCopied;
1624 pBdle->u32BdleCviPos += cbCopied;
1625 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1626 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1627 pBdle->cbUnderFifoW = 0;
1628 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1629 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1630}
1631
1632DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1633 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1634{
1635 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1636 pBdle->u32BdleCviPos += cbCopied;
1637 pBdle->cbUnderFifoW += cbCopied;
1638 /* In case of a read transaction we're always copying from the backend buffer */
1639 if (pu32BackendBufferCapacity)
1640 *pu32BackendBufferCapacity -= cbCopied;
1641 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1642 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
1643}
1644
1645DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1646{
1647 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1648 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1649
1650 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1651
1652 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1653 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1654 hdaUpdatePosBuf(pThis, pStreamDesc);
1655
1656 /* don't touch BdleCvi counter on uninitialized descriptor */
1657 if ( pBdle->u32BdleCviPos
1658 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1659 {
1660 pBdle->u32BdleCviPos = 0;
1661 pBdle->u32BdleCvi++;
1662 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1663 pBdle->u32BdleCvi = 0;
1664 }
1665 return fOnBufferEdge;
1666}
1667
1668DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1669 uint32_t cbInc)
1670{
1671 /*
1672 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
1673 * (ICH6 datasheet 18.2.38)
1674 */
1675 if (!pBdle->cbUnderFifoW)
1676 {
1677 *pStreamDesc->pu32Lpib += cbInc;
1678
1679 /*
1680 * Assert. The buffer counters should never overlap.
1681 */
1682 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1683
1684 hdaUpdatePosBuf(pThis, pStreamDesc);
1685
1686 }
1687}
1688
1689static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1690{
1691 bool fDoNextTransferLoop = true;
1692 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1693 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1694 {
1695 if ( !pBdle->cbUnderFifoW
1696 && pBdle->fBdleCviIoc)
1697 {
1698 /**
1699 * @todo - more carefully investigate BCIS flag.
1700 * Speech synthesis works fine on Mac Guest if this bit isn't set
1701 * but in general sound quality gets worse.
1702 */
1703 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1704
1705 /*
1706 * we should generate the interrupt if ICE bit of SDCTL register is set.
1707 */
1708 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1709 hdaProcessInterrupt(pThis);
1710 }
1711 fDoNextTransferLoop = false;
1712 }
1713 return fDoNextTransferLoop;
1714}
1715
1716/*
1717 * hdaReadAudio - copies samples from audio backend to DMA.
1718 * Note: this function writes to the DMA buffer immediately, but "reports bytes" when all conditions are met (FIFOW)
1719 */
1720static uint32_t hdaReadAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1721{
1722 PHDABDLEDESC pBdle = &pThis->StInBdle;
1723 uint32_t cbTransferred = 0;
1724 uint32_t cb2Copy = 0;
1725 uint32_t cbBackendCopy = 0;
1726
1727 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1728
1729 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1730 if (!cb2Copy)
1731 {
1732 /* if we enter here we can't report "unreported bits" */
1733 *fStop = true;
1734 goto l_done;
1735 }
1736
1737
1738 /*
1739 * read from backend input line to the last unreported position or at the begining.
1740 */
1741 cbBackendCopy = AUD_read(pThis->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1742 /*
1743 * write the HDA DMA buffer
1744 */
1745 PDMDevHlpPhysWrite(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1746
1747 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
1748 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1749
1750 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pThis, 0))
1751 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1752 else
1753 {
1754 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1755 *fStop = true;
1756 }
1757l_done:
1758 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
1759 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1760 return cbTransferred;
1761}
1762
1763static uint32_t hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1764{
1765 PHDABDLEDESC pBdle = &pThis->StOutBdle;
1766 uint32_t cbTransferred = 0;
1767 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1768 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1769
1770 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1771
1772 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1773
1774 /*
1775 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
1776 * previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
1777 */
1778 if (!cb2Copy)
1779 {
1780 *fStop = true;
1781 goto l_done;
1782 }
1783
1784 PDMDevHlpPhysRead(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1785 /*
1786 * Write to audio backend. we should ensure that we have enough bytes to copy to the backend.
1787 */
1788 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
1789 {
1790 /*
1791 * Feed the newly fetched samples, including unreported ones, to the backend.
1792 */
1793 cbBackendCopy = AUD_write (pThis->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1794 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1795 }
1796 else
1797 {
1798 /* Not enough bytes to be processed and reported, we'll try our luck next time around */
1799 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
1800 *fStop = true;
1801 }
1802
1803l_done:
1804 Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
1805 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransferred:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1806 return cbTransferred;
1807}
1808
1809/**
1810 * @interface_method_impl{HDACODEC,pfnReset}
1811 */
1812DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1813{
1814 PHDASTATE pThis = (PHDASTATE)pCodecState->pvHDAState;
1815 return VINF_SUCCESS;
1816}
1817
1818DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
1819 PHDASTREAMTRANSFERDESC pStreamDesc)
1820{
1821 Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
1822
1823 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1824 pStreamDesc->u8Strm = u8Strm;
1825 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pThis, CTL, u8Strm);
1826 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pThis, BDPL, u8Strm),
1827 HDA_STREAM_REG2(pThis, BDPU, u8Strm));
1828 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pThis, LPIB, u8Strm);
1829 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pThis, STS, u8Strm);
1830 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pThis, CBL, u8Strm);
1831 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pThis, FIFOS, u8Strm);
1832
1833 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pThis, LVI, u8Strm);
1834
1835#ifdef LOG_ENABLED
1836 if ( pBdle
1837 && pBdle->u32BdleMaxCvi)
1838 {
1839 Log(("Initialization of transfer descriptor:\n"));
1840 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
1841 }
1842#endif
1843}
1844
1845
1846/**
1847 * @interface_method_impl{HDACODEC,pfnTransfer}
1848 */
1849static DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1850{
1851 PHDASTATE pThis = (PHDASTATE)pCodecState->pvHDAState;
1852 uint8_t u8Strm = 0;
1853 PHDABDLEDESC pBdle = NULL;
1854
1855 switch (src)
1856 {
1857 case PO_INDEX:
1858 {
1859 u8Strm = 4;
1860 pBdle = &pThis->StOutBdle;
1861 break;
1862 }
1863 case PI_INDEX:
1864 {
1865 u8Strm = 0;
1866 pBdle = &pThis->StInBdle;
1867 break;
1868 }
1869 default:
1870 return;
1871 }
1872
1873 HDASTREAMTRANSFERDESC StreamDesc;
1874 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1875
1876 bool fStop = false;
1877 while (avail && !fStop)
1878 {
1879 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1880 && avail
1881 && StreamDesc.u64BaseDMA);
1882
1883 /* Fetch the Buffer Descriptor Entry (BDE). */
1884
1885 if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
1886 hdaFetchBdle(pThis, pBdle, &StreamDesc);
1887 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1888 Assert((avail >= 0 && (StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib)))); /* sanity */
1889 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
1890 Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
1891 Log(("hda: CBL=%d, LPIB=%d\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
1892 uint32_t cb;
1893 switch (src)
1894 {
1895 case PO_INDEX:
1896 cb = hdaWriteAudio(pThis, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1897 break;
1898 case PI_INDEX:
1899 cb = hdaReadAudio(pThis, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1900 break;
1901 default:
1902 cb = 0;
1903 fStop = true;
1904 AssertMsgFailed(("Unsupported"));
1905 }
1906 Assert(cb <= StreamDesc.u32Fifos + 1);
1907 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1908
1909 /* Process end of buffer condition. */
1910 hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cb);
1911 fStop = !fStop ? !hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc) : fStop;
1912 }
1913}
1914
1915
1916/* MMIO callbacks */
1917
1918/**
1919 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
1920 *
1921 * @note During implementation, we discovered so-called "forgotten" or "hole"
1922 * registers whose description is not listed in the RPM, datasheet, or
1923 * spec.
1924 */
1925PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1926{
1927 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
1928 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
1929 int idxReg = hdaMMIORegLookup(pThis, offReg);
1930 int rc;
1931 Assert(!(offReg & 3)); Assert(cb == 4);
1932
1933 if (pThis->fInReset && idxReg != ICH6_HDA_REG_GCTL)
1934 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1935
1936 if (idxReg == -1)
1937 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
1938
1939 if (idxReg != -1)
1940 {
1941 rc = g_aIchIntelHDRegMap[idxReg].pfnRead(pThis, idxReg, (uint32_t *)pv);
1942 Log(("hda: read %s[%x/%x]\n", g_aIchIntelHDRegMap[idxReg].abbrev, *(uint32_t *)pv));
1943 }
1944 else
1945 {
1946 rc = VINF_IOM_MMIO_UNUSED_FF;
1947 Log(("hda: hole at %x is accessed for read\n", offReg));
1948 }
1949 return rc;
1950}
1951
1952
1953/**
1954 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
1955 */
1956PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1957{
1958 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
1959 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
1960 int idxReg = hdaMMIORegLookup(pThis, offReg);
1961 int rc;
1962 Assert(!(offReg & 3)); Assert(cb == 4);
1963
1964 if (pThis->fInReset && idxReg != ICH6_HDA_REG_GCTL)
1965 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1966
1967 if (idxReg != -1)
1968 {
1969#ifdef LOG_ENABLED
1970 uint32_t const u32CurValue = pThis->au32Regs[idxReg];
1971#endif
1972 rc = g_aIchIntelHDRegMap[idxReg].pfnWrite(pThis, idxReg, *(uint32_t const *)pv);
1973 Log(("hda: write %s:(%x) %x => %x\n", g_aIchIntelHDRegMap[idxReg].abbrev, *(uint32_t const *)pv,
1974 u32CurValue, pThis->au32Regs[idxReg]));
1975 }
1976 else
1977 {
1978 LogRel(("hda: Invalid write access @0x%x\n", offReg));
1979 rc = VINF_SUCCESS;
1980 }
1981
1982 Log(("hda: hole at %x is accessed for write\n", offReg));
1983 return rc;
1984}
1985
1986
1987/* PCI callback. */
1988
1989/**
1990 * @callback_method_impl{FNPCIIOREGIONMAP}
1991 */
1992static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
1993 PCIADDRESSSPACE enmType)
1994{
1995 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1996 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
1997 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1998 int rc;
1999
2000 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2001 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2002 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2003 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_READ_MISSING,
2004 hdaMMIOWrite, hdaMMIORead, "ICH6_HDA");
2005
2006 if (RT_FAILURE(rc))
2007 return rc;
2008
2009 pThis->MMIOBaseAddr = GCPhysAddress;
2010 return VINF_SUCCESS;
2011}
2012
2013
2014/* Saved state callbacks. */
2015
2016/**
2017 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2018 */
2019static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2020{
2021 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2022 /* Save Codec nodes states */
2023 codecSaveState(&pThis->Codec, pSSM);
2024
2025 /* Save MMIO registers */
2026 AssertCompile(RT_ELEMENTS(pThis->au32Regs) == 112);
2027 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
2028 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
2029
2030 /* Save HDA dma counters */
2031 SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2032 SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2033 SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2034 return VINF_SUCCESS;
2035}
2036
2037
2038/**
2039 * @callback_method_impl{FNSSMDEVLOADEXEC}
2040 */
2041static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2042{
2043 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2044
2045 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2046
2047 /*
2048 * Load Codec nodes states.
2049 */
2050 int rc = codecLoadState(&pThis->Codec, pSSM, uVersion);
2051 if (RT_FAILURE(rc))
2052 return rc;
2053
2054 /*
2055 * Load MMIO registers.
2056 */
2057 uint32_t cRegs;
2058 switch (uVersion)
2059 {
2060 case HDA_SSM_VERSION_1:
2061 /* Starting with r71199, we would save 112 instead of 113
2062 registers due to some code cleanups. This only affected trunk
2063 builds in the 4.1 development period. */
2064 cRegs = 113;
2065 if (SSMR3HandleRevision(pSSM) >= 71199)
2066 {
2067 uint32_t uVer = SSMR3HandleVersion(pSSM);
2068 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
2069 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
2070 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
2071 cRegs = 112;
2072 }
2073 break;
2074
2075 case HDA_SSM_VERSION_2:
2076 case HDA_SSM_VERSION_3:
2077 cRegs = 112;
2078 AssertCompile(RT_ELEMENTS(pThis->au32Regs) == 112);
2079 break;
2080
2081 case HDA_SSM_VERSION:
2082 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
2083 AssertLogRelMsgReturn(cRegs == RT_ELEMENTS(pThis->au32Regs),
2084 ("cRegs is %d, expected %d\n", cRegs, RT_ELEMENTS(pThis->au32Regs)),
2085 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2086 break;
2087
2088 default:
2089 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2090 }
2091
2092 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
2093 {
2094 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
2095 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
2096 }
2097 else
2098 {
2099 RT_ZERO(pThis->au32Regs);
2100 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
2101 }
2102
2103 /*
2104 * Load HDA dma counters.
2105 */
2106 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
2107 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
2108 SSMR3GetStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), fFlags, paFields, NULL);
2109 SSMR3GetStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), fFlags, paFields, NULL);
2110 rc = SSMR3GetStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), fFlags, paFields, NULL);
2111 AssertRCReturn(rc, rc);
2112
2113 /*
2114 * Update stuff after the state changes.
2115 */
2116 AUD_set_active_in(pThis->Codec.SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2117 AUD_set_active_out(pThis->Codec.SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2118
2119 pThis->u64CORBBase = RT_MAKE_U64(CORBLBASE(pThis), CORBUBASE(pThis));
2120 pThis->u64RIRBBase = RT_MAKE_U64(RIRLBASE(pThis), RIRUBASE(pThis));
2121 pThis->u64DPBase = RT_MAKE_U64(DPLBASE(pThis), DPUBASE(pThis));
2122 return VINF_SUCCESS;
2123}
2124
2125
2126/* Debug and log type formatters. */
2127
2128/**
2129 * @callback_method_impl{FNRTSTRFORMATTYPE}
2130 */
2131static DECLCALLBACK(size_t)
2132hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2133 const char *pszType, void const *pvValue,
2134 int cchWidth, int cchPrecision, unsigned fFlags,
2135 void *pvUser)
2136{
2137 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
2138 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2139 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
2140 sdCtl,
2141 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> ICH6_HDA_SDCTL_NUM_SHIFT,
2142 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
2143 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
2144 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> ICH6_HDA_SDCTL_STRIPE_SHIFT,
2145 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
2146 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
2147 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
2148 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
2149}
2150
2151/**
2152 * @callback_method_impl{FNRTSTRFORMATTYPE}
2153 */
2154static DECLCALLBACK(size_t)
2155hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2156 const char *pszType, void const *pvValue,
2157 int cchWidth, int cchPrecision, unsigned fFlags,
2158 void *pvUser)
2159{
2160 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
2161 uint32_t cb;
2162 switch (uSdFifos)
2163 {
2164 case HDA_SDONFIFO_16B: cb = 16; break;
2165 case HDA_SDONFIFO_32B: cb = 32; break;
2166 case HDA_SDONFIFO_64B: cb = 64; break;
2167 case HDA_SDONFIFO_128B: cb = 128; break;
2168 case HDA_SDONFIFO_192B: cb = 192; break;
2169 case HDA_SDONFIFO_256B: cb = 256; break;
2170 case HDA_SDINFIFO_120B: cb = 120; break;
2171 case HDA_SDINFIFO_160B: cb = 160; break;
2172 default: cb = 0; break;
2173 }
2174 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
2175}
2176
2177/**
2178 * @callback_method_impl{FNRTSTRFORMATTYPE}
2179 */
2180static DECLCALLBACK(size_t)
2181hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2182 const char *pszType, void const *pvValue,
2183 int cchWidth, int cchPrecision, unsigned fFlags,
2184 void *pvUser)
2185{
2186 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
2187 uint32_t cb;
2188 switch (uSdFifos)
2189 {
2190 case HDA_SDFIFOW_8B: cb = 8; break;
2191 case HDA_SDFIFOW_16B: cb = 16; break;
2192 case HDA_SDFIFOW_32B: cb = 32; break;
2193 default: cb = 0; break;
2194 }
2195 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
2196}
2197
2198/**
2199 * @callback_method_impl{FNRTSTRFORMATTYPE}
2200 */
2201static DECLCALLBACK(size_t)
2202hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2203 const char *pszType, void const *pvValue,
2204 int cchWidth, int cchPrecision, unsigned fFlags,
2205 void *pvUser)
2206{
2207 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
2208 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2209 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
2210 uSdSts,
2211 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
2212 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
2213 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
2214 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
2215}
2216
2217
2218static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
2219{
2220 int iReg = 0;
2221 for (; iReg < HDA_NREGS; ++iReg)
2222 if (!RTStrICmp(g_aIchIntelHDRegMap[iReg].abbrev, pszArgs))
2223 return iReg;
2224 return -1;
2225}
2226
2227
2228static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
2229{
2230 Assert( pThis
2231 && iHdaIndex >= 0
2232 && iHdaIndex < HDA_NREGS);
2233 pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", g_aIchIntelHDRegMap[iHdaIndex].abbrev, pThis->au32Regs[iHdaIndex]);
2234}
2235
2236
2237/**
2238 * @callback_method_impl{FNDBGFHANDLERDEV}
2239 */
2240static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2241{
2242 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2243 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
2244 if (iHdaRegisterIndex != -1)
2245 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
2246 else
2247 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
2248 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
2249}
2250
2251
2252static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
2253{
2254 Assert( pThis
2255 && iHdaStrmIndex >= 0
2256 && iHdaStrmIndex < 7);
2257 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
2258 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, CTL, iHdaStrmIndex));
2259 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, STS, iHdaStrmIndex));
2260 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, FIFOS, iHdaStrmIndex));
2261 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, FIFOW, iHdaStrmIndex));
2262}
2263
2264
2265static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
2266{
2267 /* todo: add args parsing */
2268 return -1;
2269}
2270
2271
2272/**
2273 * @callback_method_impl{FNDBGFHANDLERDEV}
2274 */
2275static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2276{
2277 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2278 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
2279 if (iHdaStrmIndex != -1)
2280 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
2281 else
2282 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
2283 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
2284}
2285
2286/**
2287 * @callback_method_impl{FNDBGFHANDLERDEV}
2288 */
2289static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2290{
2291 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2292 if (pThis->Codec.pfnCodecDbgListNodes)
2293 pThis->Codec.pfnCodecDbgListNodes(&pThis->Codec, pHlp, pszArgs);
2294 else
2295 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2296}
2297
2298
2299/**
2300 * @callback_method_impl{FNDBGFHANDLERDEV}
2301 */
2302static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2303{
2304 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2305 if (pThis->Codec.pfnCodecDbgSelector)
2306 pThis->Codec.pfnCodecDbgSelector(&pThis->Codec, pHlp, pszArgs);
2307 else
2308 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2309}
2310
2311
2312/* PDMIBASE */
2313
2314/**
2315 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2316 */
2317static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
2318{
2319 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
2320 Assert(&pThis->IBase == pInterface);
2321
2322 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2323 return NULL;
2324}
2325
2326
2327/* PDMDEVREG */
2328
2329/**
2330 * Reset notification.
2331 *
2332 * @returns VBox status.
2333 * @param pDevIns The device instance data.
2334 *
2335 * @remark The original sources didn't install a reset handler, but it seems to
2336 * make sense to me so we'll do it.
2337 */
2338static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
2339{
2340 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2341 GCAP(pThis) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
2342 VMIN(pThis) = 0x00; /* see 6.2.2 */
2343 VMAJ(pThis) = 0x01; /* see 6.2.3 */
2344 VMAJ(pThis) = 0x01; /* see 6.2.3 */
2345 OUTPAY(pThis) = 0x003C; /* see 6.2.4 */
2346 INPAY(pThis) = 0x001D; /* see 6.2.5 */
2347 pThis->au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
2348 pThis->au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
2349 CORBRP(pThis) = 0x0;
2350 RIRBWP(pThis) = 0x0;
2351
2352 Log(("hda: inter HDA reset.\n"));
2353 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
2354
2355 if (pThis->pu32CorbBuf)
2356 memset(pThis->pu32CorbBuf, 0, pThis->cbCorbBuf);
2357 else
2358 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
2359
2360 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
2361 if (pThis->pu64RirbBuf)
2362 memset(pThis->pu64RirbBuf, 0, pThis->cbRirbBuf);
2363 else
2364 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
2365
2366 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2367
2368 HDABDLEDESC stEmptyBdle;
2369 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2370 {
2371 HDASTREAMTRANSFERDESC StreamDesc;
2372 PHDABDLEDESC pBdle = NULL;
2373 if (u8Strm == 0)
2374 pBdle = &pThis->StInBdle;
2375 else if(u8Strm == 4)
2376 pBdle = &pThis->StOutBdle;
2377 else
2378 {
2379 memset(&stEmptyBdle, 0, sizeof(HDABDLEDESC));
2380 pBdle = &stEmptyBdle;
2381 }
2382 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2383 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
2384 HDA_STREAM_REG2(pThis, CTL, u8Strm) = 0;
2385 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
2386 }
2387
2388 /* emulation of codec "wake up" (HDA spec 5.5.1 and 6.5)*/
2389 STATESTS(pThis) = 0x1;
2390
2391 Log(("hda: reset finished\n"));
2392}
2393
2394
2395/**
2396 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2397 */
2398static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
2399{
2400 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2401
2402 int rc = codecDestruct(&pThis->Codec);
2403 AssertRC(rc);
2404
2405 RTMemFree(pThis->pu32CorbBuf);
2406 pThis->pu32CorbBuf = NULL;
2407
2408 RTMemFree(pThis->pu64RirbBuf);
2409 pThis->pu64RirbBuf = NULL;
2410
2411 return VINF_SUCCESS;
2412}
2413
2414/**
2415 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2416 */
2417static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2418{
2419 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2420 int rc;
2421
2422 Assert(iInstance == 0);
2423 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2424
2425 /*
2426 * Validations.
2427 */
2428 if (!CFGMR3AreValuesValid(pCfgHandle, "\0"))
2429 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2430 N_ ("Invalid configuration for the Intel HDA device"));
2431
2432 /// @todo r=michaln: This device may need R0/RC enabling, especially if guests
2433 /// poll some register(pThis).
2434
2435 /*
2436 * Initialize data (most of it anyway).
2437 */
2438 pThis->pDevIns = pDevIns;
2439 /* IBase */
2440 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
2441
2442 /* PCI Device */
2443 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
2444 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEICE_ID); /* HDA */
2445
2446 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
2447 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2448 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
2449 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
2450 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
2451 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2452 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
2453 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
2454 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2455 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
2456 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
2457
2458#if defined(HDA_AS_PCI_EXPRESS)
2459 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
2460#elif defined(VBOX_WITH_MSI_DEVICES)
2461 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
2462#else
2463 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
2464#endif
2465
2466 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2467 /// of these values needs to be properly documented!
2468 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2469 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
2470
2471 /* Power Management */
2472 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2473 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
2474 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2475
2476#ifdef HDA_AS_PCI_EXPRESS
2477 /* PCI Express */
2478 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2479 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
2480 /* Device flags */
2481 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
2482 /* version */ 0x1 |
2483 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2484 /* MSI */ (100) << 9 );
2485 /* Device capabilities */
2486 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2487 /* Device control */
2488 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
2489 /* Device status */
2490 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
2491 /* Link caps */
2492 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
2493 /* Link control */
2494 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
2495 /* Link status */
2496 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
2497 /* Slot capabilities */
2498 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
2499 /* Slot control */
2500 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
2501 /* Slot status */
2502 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
2503 /* Root control */
2504 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
2505 /* Root capabilities */
2506 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
2507 /* Root status */
2508 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
2509 /* Device capabilities 2 */
2510 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
2511 /* Device control 2 */
2512 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
2513 /* Link control 2 */
2514 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
2515 /* Slot control 2 */
2516 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
2517#endif
2518
2519 /*
2520 * Register the PCI device.
2521 */
2522 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
2523 if (RT_FAILURE(rc))
2524 return rc;
2525
2526 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
2527 if (RT_FAILURE(rc))
2528 return rc;
2529
2530#ifdef VBOX_WITH_MSI_DEVICES
2531 PDMMSIREG MsiReg;
2532 RT_ZERO(MsiReg);
2533 MsiReg.cMsiVectors = 1;
2534 MsiReg.iMsiCapOffset = 0x60;
2535 MsiReg.iMsiNextOffset = 0x50;
2536 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
2537 if (RT_FAILURE(rc))
2538 {
2539 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2540 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
2541 }
2542#endif
2543
2544 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2545 if (RT_FAILURE(rc))
2546 return rc;
2547
2548 /*
2549 * Attach driver.
2550 */
2551 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Audio Driver Port");
2552 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2553 Log(("hda: No attached driver!\n"));
2554 else if (RT_FAILURE(rc))
2555 {
2556 AssertMsgFailed(("Failed to attach Intel HDA LUN #0! rc=%Rrc\n", rc));
2557 return rc;
2558 }
2559
2560 pThis->Codec.pvHDAState = pThis;
2561 rc = codecConstruct(pDevIns, &pThis->Codec, pCfgHandle);
2562 if (RT_FAILURE(rc))
2563 AssertRCReturn(rc, rc);
2564
2565 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2566 verb F20 should provide device/codec recognition. */
2567 Assert(pThis->Codec.u16VendorId);
2568 Assert(pThis->Codec.u16DeviceId);
2569 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->Codec.u16VendorId); /* 2c ro - intel.) */
2570 PCIDevSetSubSystemId( &pThis->PciDev, pThis->Codec.u16DeviceId); /* 2e ro. */
2571
2572 hdaReset(pDevIns);
2573 pThis->Codec.id = 0;
2574 pThis->Codec.pfnTransfer = hdaTransfer;
2575 pThis->Codec.pfnReset = hdaCodecReset;
2576
2577 /*
2578 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2579 * hdaReset shouldn't affects these registers.
2580 */
2581 WAKEEN(pThis) = 0x0;
2582 STATESTS(pThis) = 0x0;
2583
2584 /*
2585 * Debug and string formatter types.
2586 */
2587 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
2588 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
2589 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
2590 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
2591
2592 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
2593 AssertRC(rc);
2594 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
2595 AssertRC(rc);
2596 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
2597 AssertRC(rc);
2598 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
2599 AssertRC(rc);
2600#if 0
2601 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
2602 AssertRC(rc);
2603#endif
2604
2605 return VINF_SUCCESS;
2606}
2607
2608/**
2609 * The device registration structure.
2610 */
2611const PDMDEVREG g_DeviceICH6_HDA =
2612{
2613 /* u32Version */
2614 PDM_DEVREG_VERSION,
2615 /* szName */
2616 "hda",
2617 /* szRCMod */
2618 "",
2619 /* szR0Mod */
2620 "",
2621 /* pszDescription */
2622 "Intel HD Audio Controller",
2623 /* fFlags */
2624 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2625 /* fClass */
2626 PDM_DEVREG_CLASS_AUDIO,
2627 /* cMaxInstances */
2628 1,
2629 /* cbInstance */
2630 sizeof(HDASTATE),
2631 /* pfnConstruct */
2632 hdaConstruct,
2633 /* pfnDestruct */
2634 hdaDestruct,
2635 /* pfnRelocate */
2636 NULL,
2637 /* pfnIOCtl */
2638 NULL,
2639 /* pfnPowerOn */
2640 NULL,
2641 /* pfnReset */
2642 hdaReset,
2643 /* pfnSuspend */
2644 NULL,
2645 /* pfnResume */
2646 NULL,
2647 /* pfnAttach */
2648 NULL,
2649 /* pfnDetach */
2650 NULL,
2651 /* pfnQueryInterface. */
2652 NULL,
2653 /* pfnInitComplete */
2654 NULL,
2655 /* pfnPowerOff */
2656 NULL,
2657 /* pfnSoftReset */
2658 NULL,
2659 /* u32VersionEnd */
2660 PDM_DEVREG_VERSION
2661};
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