VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 44666

Last change on this file since 44666 was 44666, checked in by vboxsync, 12 years ago

DevIchIntelHDA.cpp: Build fix + document references.
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1/* $Id: DevIchIntelHDA.cpp 44666 2013-02-13 12:01:25Z vboxsync $ */
2/** @file
3 * DevIchIntelHDA - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2013 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_DEV_AUDIO
26#include <VBox/vmm/pdmdev.h>
27#include <VBox/version.h>
28
29#include <iprt/assert.h>
30#include <iprt/uuid.h>
31#include <iprt/string.h>
32#include <iprt/mem.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35
36#include "VBoxDD.h"
37
38extern "C" {
39#include "audio.h"
40}
41#include "DevCodec.h"
42
43
44/*******************************************************************************
45* Defined Constants And Macros *
46*******************************************************************************/
47//#define HDA_AS_PCI_EXPRESS
48#define VBOX_WITH_INTEL_HDA
49
50#if defined(VBOX_WITH_HP_HDA)
51/* HP Pavilion dv4t-1300 */
52# define HDA_PCI_VENDOR_ID 0x103c
53# define HDA_PCI_DEICE_ID 0x30f7
54#elif defined(VBOX_WITH_INTEL_HDA)
55/* Intel HDA controller */
56# define HDA_PCI_VENDOR_ID 0x8086
57# define HDA_PCI_DEICE_ID 0x2668
58#elif defined(VBOX_WITH_NVIDIA_HDA)
59/* nVidia HDA controller */
60# define HDA_PCI_VENDOR_ID 0x10de
61# define HDA_PCI_DEICE_ID 0x0ac0
62#else
63# error "Please specify your HDA device vendor/device IDs"
64#endif
65
66/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
67 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
68 * is read only except for bit 15 like the HDA spec states.
69 *
70 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
71 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
72#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
73
74#define HDA_NREGS 112
75/* Registers */
76#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
77#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
78#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
79#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
80#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
81#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[(x)])
82#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
83#define HDA_REG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
84#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
85#define HDA_REG_SVALUE(pThis, reg, val) (HDA_REG_VALUE(pThis, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
86
87#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
88#define GCAP(pThis) (HDA_REG((pThis), GCAP))
89/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
90 * oss (15:12) - number of output streams supported
91 * iss (11:8) - number of input streams supported
92 * bss (7:3) - number of bidirectional streams supported
93 * bds (2:1) - number of serial data out signals supported
94 * b64sup (0) - 64 bit addressing supported.
95 */
96#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
97 ( (((oss) & 0xF) << 12) \
98 | (((iss) & 0xF) << 8) \
99 | (((bss) & 0x1F) << 3) \
100 | (((bds) & 0x3) << 2) \
101 | ((b64sup) & 1))
102#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
103#define VMIN(pThis) (HDA_REG((pThis), VMIN))
104
105#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
106#define VMAJ(pThis) (HDA_REG((pThis), VMAJ))
107
108#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
109#define OUTPAY(pThis) (HDA_REG((pThis), OUTPAY))
110
111#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
112#define INPAY(pThis) (HDA_REG((pThis), INPAY))
113
114#define ICH6_HDA_REG_GCTL (5)
115#define ICH6_HDA_GCTL_RST_SHIFT (0)
116#define ICH6_HDA_GCTL_FSH_SHIFT (1)
117#define ICH6_HDA_GCTL_UR_SHIFT (8)
118#define GCTL(pThis) (HDA_REG((pThis), GCTL))
119
120#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
121#define WAKEEN(pThis) (HDA_REG((pThis), WAKEEN))
122
123#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
124#define STATESTS(pThis) (HDA_REG((pThis), STATESTS))
125#define ICH6_HDA_STATES_SCSF 0x7
126
127#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
128#define ICH6_HDA_GSTS_FSH_SHIFT (1)
129#define GSTS(pThis) (HDA_REG(pThis, GSTS))
130
131#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
132#define ICH6_HDA_INTCTL_GIE_SHIFT 31
133#define ICH6_HDA_INTCTL_CIE_SHIFT 30
134#define ICH6_HDA_INTCTL_S0_SHIFT (0)
135#define ICH6_HDA_INTCTL_S1_SHIFT (1)
136#define ICH6_HDA_INTCTL_S2_SHIFT (2)
137#define ICH6_HDA_INTCTL_S3_SHIFT (3)
138#define ICH6_HDA_INTCTL_S4_SHIFT (4)
139#define ICH6_HDA_INTCTL_S5_SHIFT (5)
140#define ICH6_HDA_INTCTL_S6_SHIFT (6)
141#define ICH6_HDA_INTCTL_S7_SHIFT (7)
142#define INTCTL(pThis) (HDA_REG((pThis), INTCTL))
143#define INTCTL_GIE(pThis) (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
144#define INTCTL_CIE(pThis) (HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE))
145#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
146#define INTCTL_SALL(pThis) (INTCTL((pThis)) & 0xFF)
147
148/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
149 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
150 * the datasheet.
151 */
152#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
153#define SSYNC(pThis) (HDA_REG((pThis), SSYNC))
154
155#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
156#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
157#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
158#define ICH6_HDA_INTSTS_S0_SHIFT (0)
159#define ICH6_HDA_INTSTS_S1_SHIFT (1)
160#define ICH6_HDA_INTSTS_S2_SHIFT (2)
161#define ICH6_HDA_INTSTS_S3_SHIFT (3)
162#define ICH6_HDA_INTSTS_S4_SHIFT (4)
163#define ICH6_HDA_INTSTS_S5_SHIFT (5)
164#define ICH6_HDA_INTSTS_S6_SHIFT (6)
165#define ICH6_HDA_INTSTS_S7_SHIFT (7)
166#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
167#define INTSTS(pThis) (HDA_REG((pThis), INTSTS))
168#define INTSTS_GIS(pThis) (HDA_REG_FLAG_VALUE((pThis), INTSTS, GIS)
169#define INTSTS_CIS(pThis) (HDA_REG_FLAG_VALUE((pThis), INTSTS, CIS)
170#define INTSTS_SX(pThis, X) (HDA_REG_FLAG_VALUE(pThis), INTSTS, S##X)
171#define INTSTS_SANY(pThis) (INTSTS((pThis)) & 0xFF)
172
173#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
174#define CORBLBASE(pThis) (HDA_REG((pThis), CORBLBASE))
175#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
176#define CORBUBASE(pThis) (HDA_REG((pThis), CORBUBASE))
177#define ICH6_HDA_REG_CORBWP 15 /* 48 */
178#define ICH6_HDA_REG_CORBRP 16 /* 4A */
179#define ICH6_HDA_CORBRP_RST_SHIFT 15
180#define ICH6_HDA_CORBRP_WP_SHIFT 0
181#define ICH6_HDA_CORBRP_WP_MASK 0xFF
182
183#define CORBRP(pThis) (HDA_REG(pThis, CORBRP))
184#define CORBWP(pThis) (HDA_REG(pThis, CORBWP))
185
186#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
187#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
188#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
189
190#define CORBCTL(pThis) (HDA_REG(pThis, CORBCTL))
191
192
193#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
194#define CORBSTS(pThis) (HDA_REG(pThis, CORBSTS))
195#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
196
197#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
198#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
199#define ICH6_HDA_CORBSIZE_SZ 0x3
200#define CORBSIZE_SZ(pThis) (HDA_REG(pThis, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
201#define CORBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
202/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
203
204#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
205#define RIRLBASE(pThis) (HDA_REG((pThis), RIRLBASE))
206
207#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
208#define RIRUBASE(pThis) (HDA_REG((pThis), RIRUBASE))
209
210#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
211#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
212#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
213#define RIRBWP(pThis) (HDA_REG(pThis, RIRBWP))
214
215#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
216#define RINTCNT(pThis) (HDA_REG((pThis), RINTCNT))
217#define RINTCNT_N(pThis) (RINTCNT((pThis)) & 0xff)
218
219#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
220#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
221#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
222#define ICH6_HDA_ROI_DMA_SHIFT (2)
223#define RIRBCTL(pThis) (HDA_REG((pThis), RIRBCTL))
224#define RIRBCTL_RIRB_RIC(pThis) (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
225#define RIRBCTL_RIRB_DMA(pThis) (HDA_REG_FLAG_VALUE((pThis), RIRBCTL, DMA)
226#define RIRBCTL_ROI(pThis) (HDA_REG_FLAG_VALUE((pThis), RIRBCTL, ROI))
227
228#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
229#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
230#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
231#define RIRBSTS(pThis) (HDA_REG(pThis, RIRBSTS))
232#define RIRBSTS_RINTFL(pThis) (HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL))
233#define RIRBSTS_RIRBOIS(pThis) (HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS))
234
235#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
236#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
237#define ICH6_HDA_RIRBSIZE_SZ 0x3
238
239#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
240#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
241
242
243#define ICH6_HDA_REG_IC 27 /* 0x60 */
244#define IC(pThis) (HDA_REG(pThis, IC))
245#define ICH6_HDA_REG_IR 28 /* 0x64 */
246#define IR(pThis) (HDA_REG(pThis, IR))
247#define ICH6_HDA_REG_IRS 29 /* 0x68 */
248#define ICH6_HDA_IRS_ICB_SHIFT (0)
249#define ICH6_HDA_IRS_IRV_SHIFT (1)
250#define IRS(pThis) (HDA_REG(pThis, IRS))
251#define IRS_ICB(pThis) (HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
252#define IRS_IRV(pThis) (HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
253
254#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
255#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
256#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
257#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
258#define DPBASE_ENABLED 1
259#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
260
261#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
262#define HDA_STREAM_REG(pThis, name, num) (HDA_REG((pThis), N_(HDA_STREAM_REG_DEF(name, num))))
263/* Note: sdnum here _MUST_ be stream reg number [0,7] */
264#define HDA_STREAM_REG2(pThis, name, sdnum) (HDA_REG_IND((pThis), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
265
266#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
267#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
268#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
269#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
270#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
271#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
272#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
273#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
274
275#define SD(func, num) SD##num##func
276#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
277#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
278#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
279#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
280#define ICH6_HDA_SDCTL_DIR_SHIFT (19)
281#define ICH6_HDA_SDCTL_TP_SHIFT (18)
282#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)
283#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)
284#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
285#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
286#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
287#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
288#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
289
290#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
291#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
292#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
293#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
294#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
295#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
296#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
297#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
298
299#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
300#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
301#define ICH6_HDA_SDSTS_DE_SHIFT (4)
302#define ICH6_HDA_SDSTS_FE_SHIFT (3)
303#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
304
305#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
306#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
307#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
308#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
309#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
310#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
311#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
312#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
313
314#define SDLPIB(pThis, num) HDA_REG((pThis), SD(LPIB, num))
315
316#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
317#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
318#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
319#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
320#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
321#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
322#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
323#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
324
325#define SDLCBL(pThis, num) HDA_REG((pThis), SD(CBL, num))
326
327#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
328#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
329#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
330#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
331#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
332#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
333#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
334#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
335
336#define SDLVI(pThis, num) HDA_REG((pThis), SD(LVI, num))
337
338#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
339#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
340#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
341#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
342#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
343#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
344#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
345#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
346
347/*
348 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
349 */
350#define HDA_SDFIFOW_8B (0x2)
351#define HDA_SDFIFOW_16B (0x3)
352#define HDA_SDFIFOW_32B (0x4)
353#define SDFIFOW(pThis, num) HDA_REG((pThis), SD(FIFOW, num))
354
355#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
356#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
357#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
358#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
359#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
360#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
361#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
362#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
363
364/*
365 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
366 * formula: size - 1
367 * Other values not listed are not supported.
368 */
369#define HDA_SDONFIFO_16B (0x0F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
370#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
371#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
372#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
373#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
374#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
375#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
376#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
377#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
378
379#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
380#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
381#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
382#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
383#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
384#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
385#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
386#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
387
388#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
389#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
390#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
391#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
392#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
393#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
394#define ICH6_HDA_SDFMT_BITS_SHIFT (4)
395#define ICH6_HDA_SDFMT_BITS_MASK (0x7)
396#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
397#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
398#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
399
400#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
401#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
402#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
403#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
404#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
405#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
406#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
407#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
408
409#define SDBDPL(pThis, num) HDA_REG((pThis), SD(BDPL, num))
410
411#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
412#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
413#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
414#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
415#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
416#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
417#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
418#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
419
420#define SDBDPU(pThis, num) HDA_REG((pThis), SD(BDPU, num))
421
422
423/*******************************************************************************
424* Structures and Typedefs *
425*******************************************************************************/
426typedef struct HDABDLEDESC
427{
428 uint64_t u64BdleCviAddr;
429 uint32_t u32BdleMaxCvi;
430 uint32_t u32BdleCvi;
431 uint32_t u32BdleCviLen;
432 uint32_t u32BdleCviPos;
433 bool fBdleCviIoc;
434 uint32_t cbUnderFifoW;
435 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
436} HDABDLEDESC, *PHDABDLEDESC;
437
438typedef struct HDASTREAMTRANSFERDESC
439{
440 uint64_t u64BaseDMA;
441 uint32_t u32Ctl;
442 uint32_t *pu32Sts;
443 uint8_t u8Strm;
444 uint32_t *pu32Lpib;
445 uint32_t u32Cbl;
446 uint32_t u32Fifos;
447} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
448
449/**
450 * ICH Intel HD Audio Controller state.
451 */
452typedef struct HDASTATE
453{
454 /** The PCI device structure. */
455 PCIDevice PciDev;
456 /** Pointer to the device instance. */
457 PPDMDEVINSR3 pDevIns;
458 /** Pointer to the connector of the attached audio driver. */
459 PPDMIAUDIOCONNECTOR pDrv;
460 /** Pointer to the attached audio driver. */
461 PPDMIBASE pDrvBase;
462 /** The base interface for LUN\#0. */
463 PDMIBASE IBase;
464 RTGCPHYS MMIOBaseAddr;
465 uint32_t au32Regs[HDA_NREGS];
466 HDABDLEDESC StInBdle;
467 HDABDLEDESC StOutBdle;
468 HDABDLEDESC StMicBdle;
469 /** Interrupt on completion */
470 bool fCviIoc;
471 uint64_t u64CORBBase;
472 uint64_t u64RIRBBase;
473 uint64_t u64DPBase;
474 /** pointer to CORB buf */
475 uint32_t *pu32CorbBuf;
476 /** size in bytes of CORB buf */
477 uint32_t cbCorbBuf;
478 /** pointer on RIRB buf */
479 uint64_t *pu64RirbBuf;
480 /** size in bytes of RIRB buf */
481 uint32_t cbRirbBuf;
482 /** indicates if HDA in reset. */
483 bool fInReset;
484 CODECState Codec;
485 /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
486 uint8_t u8Counter;
487 uint64_t u64BaseTS;
488} HDASTATE;
489/** Pointer to the ICH Intel HD Audio Controller state. */
490typedef HDASTATE *PHDASTATE;
491
492#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
493 ( AUDIO_FORMAT_SELECTOR(&(pThis)->Codec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
494#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
495 ( AUDIO_FORMAT_SELECTOR(&(pThis)->Codec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
496
497
498/*******************************************************************************
499* Internal Functions *
500*******************************************************************************/
501static FNPDMDEVRESET hdaReset;
502
503static int hdaRegReadUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
504static int hdaRegWriteUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
505static int hdaRegReadGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
506static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
507static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
508static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
509static int hdaRegReadGCAP(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
510static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
511static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
512static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
513static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
514static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
515static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
516static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
517static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
518static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
519static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
520static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
521static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
522static int hdaRegReadSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
523
524static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
525static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
526static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
527static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
528static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
529static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
530static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
531static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
532static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
533static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
534static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
535static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
536static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
537static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
538static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
539static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
540
541DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
542 PHDASTREAMTRANSFERDESC pStreamDesc);
543static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
544#ifdef LOG_ENABLED
545static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
546#endif
547
548
549/*******************************************************************************
550* Global Variables *
551*******************************************************************************/
552/* see 302349 p 6.2*/
553static const struct HDAREGDESC
554{
555 /** Register offset in the register space. */
556 uint32_t offset;
557 /** Size in bytes. Registers of size > 4 are in fact tables. */
558 uint32_t size;
559 /** Readable bits. */
560 uint32_t readable;
561 /** Writable bits. */
562 uint32_t writable;
563 /** Read callback. */
564 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
565 /** Write callback. */
566 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
567 /** Abbreviated name. */
568 const char *abbrev;
569 /** Full name. */
570 const char *name;
571} g_aHdaRegMap[HDA_NREGS] =
572{
573 /* offset size read mask write mask read callback write callback abbrev full name */
574 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
575 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
576 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
577 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
578 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
579 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
580 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
581 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
582 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
583 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
584 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
585 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
586 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
587 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
588 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
589 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
590 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
591 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
592#ifdef OLD_REGISTER_TABLE
593 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
594#else /** @todo 18.2.17 indicates that the 15th bit can be read as well as and written. hdaRegReadU8 is wrong, a special reader should be used. */
595 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
596#endif
597 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
598 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
599 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
600 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
601 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
602 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
603 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
604 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
605 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
606 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
607 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
608 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
609#ifdef OLD_REGISTER_TABLE
610 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
611#else /* 18.2.30 as well as the table says 16-bit. Linux accesses it as a 16-bit register. */
612 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
613#endif
614 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
615 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
616
617 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
618 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
619 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
620 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
621 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
622 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
623 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
624 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
625 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
626 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
627
628 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
629 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
630 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
631 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
632 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
633 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
634 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
635 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
636 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
637 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
638
639 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
640 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
641 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
642 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
643 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
644 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
645 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
646 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
647 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
648 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
649
650 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
651 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
652 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
653 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
654 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
655 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
656 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
657 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
658 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
659 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
660
661 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
662 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
663 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
664 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
665 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
666 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
667 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
668 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
669 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
670 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
671
672 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
673 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
674 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
675 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
676 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
677 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
678 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
679 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
680 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
681 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
682
683 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
684 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
685 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
686 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
687 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
688 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
689 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
690 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
691 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
692 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
693
694 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
695 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
696 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
697 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
698 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
699 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
700 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
701 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
702 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
703 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
704};
705
706/**
707 * HDA register aliases (HDA spec 3.3.45).
708 * @remarks Sorted by offReg.
709 */
710static const struct
711{
712 /** The alias register offset. */
713 uint32_t offReg;
714 /** The register index. */
715 int idxAlias;
716} g_aHdaRegAliases[] =
717{
718 { 0x2084, HDA_REG_IND_NAME(SD0LPIB) },
719 { 0x20a4, HDA_REG_IND_NAME(SD1LPIB) },
720 { 0x20c4, HDA_REG_IND_NAME(SD2LPIB) },
721 { 0x20e4, HDA_REG_IND_NAME(SD3LPIB) },
722 { 0x2104, HDA_REG_IND_NAME(SD4LPIB) },
723 { 0x2124, HDA_REG_IND_NAME(SD5LPIB) },
724 { 0x2144, HDA_REG_IND_NAME(SD6LPIB) },
725 { 0x2164, HDA_REG_IND_NAME(SD7LPIB) },
726};
727
728
729/** HDABDLEDESC field descriptors the v3+ saved state. */
730static SSMFIELD const g_aHdaBDLEDescFields[] =
731{
732 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
733 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
734 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
735 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
736 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
737 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
738 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
739 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
740 SSMFIELD_ENTRY_TERM()
741};
742
743/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
744static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
745{
746 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
747 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
748 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
749 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
750 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
751 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
752 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
753 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
754 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
755 SSMFIELD_ENTRY_TERM()
756};
757
758/**
759 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
760 */
761static uint32_t const g_afMasks[5] =
762{
763 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0xffffff00), UINT32_C(0xffffffff)
764};
765
766
767DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
768{
769 if (pThis->u64DPBase & DPBASE_ENABLED)
770 PDMDevHlpPhysWrite(pThis->pDevIns,
771 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
772 pStreamDesc->pu32Lpib, sizeof(uint32_t));
773}
774DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
775{
776#if 0
777 switch(HDA_STREAM_REG2(pThis, FIFOW, pStreamDesc->u8Strm))
778 {
779 case HDA_SDFIFOW_8B: return 8;
780 case HDA_SDFIFOW_16B: return 16;
781 case HDA_SDFIFOW_32B: return 32;
782 default:
783 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
784 }
785#endif
786 return 0;
787}
788
789static int hdaProcessInterrupt(PHDASTATE pThis)
790{
791#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
792 ( INTCTL_SX((pThis), num) \
793 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
794 bool fIrq = false;
795 if ( INTCTL_CIE(pThis)
796 && ( RIRBSTS_RINTFL(pThis)
797 || RIRBSTS_RIRBOIS(pThis)
798 || (STATESTS(pThis) & WAKEEN(pThis))))
799 fIrq = true;
800
801 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
802 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
803 fIrq = true;
804
805 if (INTCTL_GIE(pThis))
806 {
807 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
808 PDMDevHlpPCISetIrq(pThis->pDevIns, 0 , fIrq);
809 }
810 return VINF_SUCCESS;
811}
812
813/**
814 * Looks up a register at the exact offset given by @a offReg.
815 *
816 * @returns Register index on success, -1 if not found.
817 * @param pThis The HDA device state.
818 * @param offReg The register offset.
819 */
820static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
821{
822 /*
823 * Aliases.
824 */
825 if (offReg >= g_aHdaRegAliases[0].offReg)
826 {
827 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
828 if (offReg == g_aHdaRegAliases[i].offReg)
829 return g_aHdaRegAliases[i].idxAlias;
830 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
831 return -1;
832 }
833
834 /*
835 * Binary search the
836 */
837 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
838 int idxLow = 0;
839 for (;;)
840 {
841 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
842 if (offReg < g_aHdaRegMap[idxMiddle].offset)
843 {
844 if (idxLow == idxMiddle)
845 break;
846 idxEnd = idxMiddle;
847 }
848 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
849 {
850 idxLow = idxMiddle + 1;
851 if (idxLow >= idxEnd)
852 break;
853 }
854 else
855 return idxMiddle;
856 }
857
858#ifdef RT_STRICT
859 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
860 Assert(g_aHdaRegMap[i].offset != offReg);
861#endif
862 return -1;
863}
864
865/**
866 * Looks up a register covering the offset given by @a offReg.
867 *
868 * @returns Register index on success, -1 if not found.
869 * @param pThis The HDA device state.
870 * @param offReg The register offset.
871 */
872static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
873{
874 /*
875 * Aliases.
876 */
877 if (offReg >= g_aHdaRegAliases[0].offReg)
878 {
879 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
880 {
881 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
882 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
883 return g_aHdaRegAliases[i].idxAlias;
884 }
885 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
886 return -1;
887 }
888
889 /*
890 * Binary search the
891 */
892 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
893 int idxLow = 0;
894 for (;;)
895 {
896 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
897 if (offReg < g_aHdaRegMap[idxMiddle].offset)
898 {
899 if (idxLow == idxMiddle)
900 break;
901 idxEnd = idxMiddle;
902 }
903 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
904 {
905 idxLow = idxMiddle + 1;
906 if (idxLow >= idxEnd)
907 break;
908 }
909 else
910 return idxMiddle;
911 }
912
913#ifdef RT_STRICT
914 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
915 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
916#endif
917 return -1;
918}
919
920
921static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
922{
923 int rc = VINF_SUCCESS;
924 if (fLocal)
925 {
926 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
927 rc = PDMDevHlpPhysRead(pThis->pDevIns, pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
928 if (RT_FAILURE(rc))
929 AssertRCReturn(rc, rc);
930#ifdef DEBUG_CMD_BUFFER
931 uint8_t i = 0;
932 do
933 {
934 Log(("hda: corb%02x: ", i));
935 uint8_t j = 0;
936 do
937 {
938 const char *prefix;
939 if ((i + j) == CORBRP(pThis))
940 prefix = "[R]";
941 else if ((i + j) == CORBWP(pThis))
942 prefix = "[W]";
943 else
944 prefix = " "; /* three spaces */
945 Log(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
946 j++;
947 } while (j < 8);
948 Log(("\n"));
949 i += 8;
950 } while(i != 0);
951#endif
952 }
953 else
954 {
955 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
956 rc = PDMDevHlpPhysWrite(pThis->pDevIns, pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
957 if (RT_FAILURE(rc))
958 AssertRCReturn(rc, rc);
959#ifdef DEBUG_CMD_BUFFER
960 uint8_t i = 0;
961 do {
962 Log(("hda: rirb%02x: ", i));
963 uint8_t j = 0;
964 do {
965 const char *prefix;
966 if ((i + j) == RIRBWP(pThis))
967 prefix = "[W]";
968 else
969 prefix = " ";
970 Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
971 } while (++j < 8);
972 Log(("\n"));
973 i += 8;
974 } while (i != 0);
975#endif
976 }
977 return rc;
978}
979
980static int hdaCORBCmdProcess(PHDASTATE pThis)
981{
982 int rc;
983 uint8_t corbRp;
984 uint8_t corbWp;
985 uint8_t rirbWp;
986
987 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
988
989 rc = hdaCmdSync(pThis, true);
990 if (RT_FAILURE(rc))
991 AssertRCReturn(rc, rc);
992 corbRp = CORBRP(pThis);
993 corbWp = CORBWP(pThis);
994 rirbWp = RIRBWP(pThis);
995 Assert((corbWp != corbRp));
996 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pThis), CORBWP(pThis), RIRBWP(pThis)));
997 while (corbRp != corbWp)
998 {
999 uint32_t cmd;
1000 uint64_t resp;
1001 pfn = (PFNCODECVERBPROCESSOR)NULL;
1002 corbRp++;
1003 cmd = pThis->pu32CorbBuf[corbRp];
1004 rc = pThis->Codec.pfnLookup(&pThis->Codec, cmd, &pfn);
1005 if (RT_FAILURE(rc))
1006 AssertRCReturn(rc, rc);
1007 Assert(pfn);
1008 (rirbWp)++;
1009
1010 if (RT_LIKELY(pfn))
1011 rc = pfn(&pThis->Codec, cmd, &resp);
1012 else
1013 rc = VERR_INVALID_FUNCTION;
1014
1015 if (RT_FAILURE(rc))
1016 AssertRCReturn(rc, rc);
1017 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
1018 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1019 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1020 {
1021 Log(("hda: unexpected unsolicited response.\n"));
1022 pThis->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
1023 return rc;
1024 }
1025 pThis->pu64RirbBuf[rirbWp] = resp;
1026 pThis->u8Counter++;
1027 if (pThis->u8Counter == RINTCNT_N(pThis))
1028 break;
1029 }
1030 pThis->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
1031 pThis->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
1032 rc = hdaCmdSync(pThis, false);
1033 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pThis), CORBWP(pThis), RIRBWP(pThis)));
1034 if (RIRBCTL_RIRB_RIC(pThis))
1035 {
1036 RIRBSTS((pThis)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1037 pThis->u8Counter = 0;
1038 rc = hdaProcessInterrupt(pThis);
1039 }
1040 if (RT_FAILURE(rc))
1041 AssertRCReturn(rc, rc);
1042 return rc;
1043}
1044
1045static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
1046{
1047 Log(("hda: reset of stream (%d) started\n", u8Strm));
1048 Assert(( pThis
1049 && pBdle
1050 && pStreamDesc
1051 && u8Strm <= 7));
1052 memset(pBdle, 0, sizeof(HDABDLEDESC));
1053 *pStreamDesc->pu32Lpib = 0;
1054 *pStreamDesc->pu32Sts = 0;
1055 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1056 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
1057 HDA_STREAM_REG2(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1058
1059 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1060 HDA_STREAM_REG2(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1061 HDA_STREAM_REG2(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
1062 HDA_STREAM_REG2(pThis, CBL, u8Strm) = 0;
1063 HDA_STREAM_REG2(pThis, LVI, u8Strm) = 0;
1064 HDA_STREAM_REG2(pThis, FMT, u8Strm) = 0;
1065 HDA_STREAM_REG2(pThis, BDPU, u8Strm) = 0;
1066 HDA_STREAM_REG2(pThis, BDPL, u8Strm) = 0;
1067 Log(("hda: reset of stream (%d) finished\n", u8Strm));
1068}
1069
1070
1071/* Register access handlers. */
1072
1073static int hdaRegReadUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1074{
1075 *pu32Value = 0;
1076 return VINF_SUCCESS;
1077}
1078
1079static int hdaRegWriteUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1080{
1081 return VINF_SUCCESS;
1082}
1083
1084/* U8 */
1085static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1086{
1087 Assert(((pThis->au32Regs[iReg] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1088 return hdaRegReadU32(pThis, iReg, pu32Value);
1089}
1090
1091static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1092{
1093 Assert((u32Value & 0xffffff00) == 0);
1094 return hdaRegWriteU32(pThis, iReg, u32Value);
1095}
1096
1097/* U16 */
1098static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1099{
1100 Assert(((pThis->au32Regs[iReg] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1101 return hdaRegReadU32(pThis, iReg, pu32Value);
1102}
1103
1104static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1105{
1106 Assert((u32Value & 0xffff0000) == 0);
1107 return hdaRegWriteU32(pThis, iReg, u32Value);
1108}
1109
1110/* U24 */
1111static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1112{
1113 Assert(((pThis->au32Regs[iReg] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1114 return hdaRegReadU32(pThis, iReg, pu32Value);
1115}
1116
1117static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1118{
1119 Assert((u32Value & 0xff000000) == 0);
1120 return hdaRegWriteU32(pThis, iReg, u32Value);
1121}
1122
1123/* U32 */
1124static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1125{
1126 *pu32Value = pThis->au32Regs[iReg] & g_aHdaRegMap[iReg].readable;
1127 return VINF_SUCCESS;
1128}
1129
1130static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1131{
1132 pThis->au32Regs[iReg] = (u32Value & g_aHdaRegMap[iReg].writable)
1133 | (pThis->au32Regs[iReg] & ~g_aHdaRegMap[iReg].writable);
1134 return VINF_SUCCESS;
1135}
1136
1137static int hdaRegReadGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1138{
1139 return hdaRegReadU32(pThis, iReg, pu32Value);
1140}
1141
1142static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1143{
1144 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1145 {
1146 /* exit reset state */
1147 GCTL(pThis) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1148 pThis->fInReset = false;
1149 }
1150 else
1151 {
1152 /* enter reset state*/
1153 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1154 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1155 {
1156 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1157 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1158 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1159 }
1160 hdaReset(pThis->pDevIns);
1161 GCTL(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1162 pThis->fInReset = true;
1163 }
1164 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1165 {
1166 /* Flush: GSTS:1 set, see 6.2.6*/
1167 GSTS(pThis) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1168 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1169 }
1170 return VINF_SUCCESS;
1171}
1172
1173static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1174{
1175 uint32_t v = pThis->au32Regs[iReg];
1176 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
1177 pThis->au32Regs[iReg] &= ~(v & nv); /* write of 1 clears corresponding bit */
1178 return VINF_SUCCESS;
1179}
1180
1181static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1182{
1183 uint32_t v = 0;
1184 if ( RIRBSTS_RIRBOIS(pThis)
1185 || RIRBSTS_RINTFL(pThis)
1186 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1187 || STATESTS(pThis))
1188 v |= RT_BIT(30);
1189#define HDA_IS_STREAM_EVENT(pThis, stream) \
1190 ( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1191 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1192 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1193#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
1194 MARK_STREAM(pThis, 0, v);
1195 MARK_STREAM(pThis, 1, v);
1196 MARK_STREAM(pThis, 2, v);
1197 MARK_STREAM(pThis, 3, v);
1198 MARK_STREAM(pThis, 4, v);
1199 MARK_STREAM(pThis, 5, v);
1200 MARK_STREAM(pThis, 6, v);
1201 MARK_STREAM(pThis, 7, v);
1202 v |= v ? RT_BIT(31) : 0;
1203 *pu32Value = v;
1204 return VINF_SUCCESS;
1205}
1206
1207static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1208{
1209 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1210 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->pDevIns)
1211 - pThis->u64BaseTS, 24, 1000);
1212 return VINF_SUCCESS;
1213}
1214
1215static int hdaRegReadGCAP(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1216{
1217 return hdaRegReadU16(pThis, iReg, pu32Value);
1218}
1219
1220static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1221{
1222 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1223 CORBRP(pThis) = 0;
1224#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1225 else
1226 return hdaRegWriteU8(pThis, iReg, u32Value);
1227#endif
1228 return VINF_SUCCESS;
1229}
1230
1231static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1232{
1233 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1234 AssertRC(rc);
1235 if ( CORBWP(pThis) != CORBRP(pThis)
1236 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1237 return hdaCORBCmdProcess(pThis);
1238 return rc;
1239}
1240
1241static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1242{
1243 uint32_t v = CORBSTS(pThis);
1244 CORBSTS(pThis) &= ~(v & u32Value);
1245 return VINF_SUCCESS;
1246}
1247
1248static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1249{
1250 int rc;
1251 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1252 if (RT_FAILURE(rc))
1253 AssertRCReturn(rc, rc);
1254 if (CORBWP(pThis) == CORBRP(pThis))
1255 return VINF_SUCCESS;
1256 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1257 return VINF_SUCCESS;
1258 rc = hdaCORBCmdProcess(pThis);
1259 return rc;
1260}
1261
1262static int hdaRegReadSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1263{
1264 return hdaRegReadU24(pThis, iReg, pu32Value);
1265}
1266
1267static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1268{
1269 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1270 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1271 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1272 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1273 int rc = VINF_SUCCESS;
1274 if (fInReset)
1275 {
1276 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1277 * from reset
1278 */
1279 Assert((!fReset));
1280 Log(("hda: guest initiated exit of stream reset.\n"));
1281 goto l_done;
1282 }
1283 else if (fReset)
1284 {
1285 /*
1286 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1287 */
1288 uint8_t u8Strm = 0;
1289 PHDABDLEDESC pBdle = NULL;
1290 HDASTREAMTRANSFERDESC StreamDesc;
1291 Assert((!fInRun && !fRun));
1292 switch (iReg)
1293 {
1294 case ICH6_HDA_REG_SD0CTL:
1295 u8Strm = 0;
1296 pBdle = &pThis->StInBdle;
1297 break;
1298 case ICH6_HDA_REG_SD4CTL:
1299 u8Strm = 4;
1300 pBdle = &pThis->StOutBdle;
1301 break;
1302 default:
1303 Log(("hda: changing SRST bit on non-attached stream\n"));
1304 goto l_done;
1305 }
1306 Log(("hda: guest initiated enter to stream reset.\n"));
1307 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1308 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
1309 goto l_done;
1310 }
1311
1312 /* we enter here to change DMA states only */
1313 if ( (fInRun && !fRun)
1314 || (fRun && !fInRun))
1315 {
1316 Assert((!fReset && !fInReset));
1317 switch (iReg)
1318 {
1319 case ICH6_HDA_REG_SD0CTL:
1320 AUD_set_active_in(pThis->Codec.SwVoiceIn, fRun);
1321 break;
1322 case ICH6_HDA_REG_SD4CTL:
1323 AUD_set_active_out(pThis->Codec.SwVoiceOut, fRun);
1324 break;
1325 default:
1326 Log(("hda: changing RUN bit on non-attached stream\n"));
1327 goto l_done;
1328 }
1329 }
1330
1331l_done:
1332 rc = hdaRegWriteU24(pThis, iReg, u32Value);
1333 if (RT_FAILURE(rc))
1334 AssertRCReturn(rc, VINF_SUCCESS);
1335 return rc;
1336}
1337
1338static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1339{
1340 uint32_t v = HDA_REG_IND(pThis, iReg);
1341 v &= ~(u32Value & v);
1342 HDA_REG_IND(pThis, iReg) = v;
1343 hdaProcessInterrupt(pThis);
1344 return VINF_SUCCESS;
1345}
1346
1347static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1348{
1349 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1350 if (RT_FAILURE(rc))
1351 AssertRCReturn(rc, VINF_SUCCESS);
1352 return rc;
1353}
1354
1355static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1356{
1357 switch (u32Value)
1358 {
1359 case HDA_SDFIFOW_8B:
1360 case HDA_SDFIFOW_16B:
1361 case HDA_SDFIFOW_32B:
1362 return hdaRegWriteU16(pThis, iReg, u32Value);
1363 default:
1364 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1365 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1366 }
1367 return VINF_SUCCESS;
1368}
1369
1370/**
1371 * @note This method could be called for changing value on Output Streams
1372 * only (ICH6 datasheet 18.2.39)
1373 */
1374static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1375{
1376 switch (iReg)
1377 {
1378 /* SDInFIFOS is RO, n=0-3 */
1379 case ICH6_HDA_REG_SD0FIFOS:
1380 case ICH6_HDA_REG_SD1FIFOS:
1381 case ICH6_HDA_REG_SD2FIFOS:
1382 case ICH6_HDA_REG_SD3FIFOS:
1383 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1384 return VINF_SUCCESS;
1385 case ICH6_HDA_REG_SD4FIFOS:
1386 case ICH6_HDA_REG_SD5FIFOS:
1387 case ICH6_HDA_REG_SD6FIFOS:
1388 case ICH6_HDA_REG_SD7FIFOS:
1389 switch(u32Value)
1390 {
1391 case HDA_SDONFIFO_16B:
1392 case HDA_SDONFIFO_32B:
1393 case HDA_SDONFIFO_64B:
1394 case HDA_SDONFIFO_128B:
1395 case HDA_SDONFIFO_192B:
1396 return hdaRegWriteU16(pThis, iReg, u32Value);
1397
1398 case HDA_SDONFIFO_256B:
1399 Log(("hda: 256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1400 default:
1401 return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);
1402 }
1403 return VINF_SUCCESS;
1404 default:
1405 AssertMsgFailed(("Something weird happened with register lookup routine"));
1406 }
1407 return VINF_SUCCESS;
1408}
1409
1410static void hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1411{
1412 Assert((pAudSetting));
1413#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1414 uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1415 uint32_t u32HzMult = 1;
1416 uint32_t u32HzDiv = 1;
1417 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))
1418 {
1419 case 0: u32HzMult = 1; break;
1420 case 1: u32HzMult = 2; break;
1421 case 2: u32HzMult = 3; break;
1422 case 3: u32HzMult = 4; break;
1423 default:
1424 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1425 }
1426 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))
1427 {
1428 case 0: u32HzDiv = 1; break;
1429 case 1: u32HzDiv = 2; break;
1430 case 2: u32HzDiv = 3; break;
1431 case 3: u32HzDiv = 4; break;
1432 case 4: u32HzDiv = 5; break;
1433 case 5: u32HzDiv = 6; break;
1434 case 6: u32HzDiv = 7; break;
1435 case 7: u32HzDiv = 8; break;
1436 }
1437 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1438
1439 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_BITS_MASK, ICH6_HDA_SDFMT_BITS_SHIFT))
1440 {
1441 case 0:
1442 Log(("hda: %s requested 8-bit\n", __FUNCTION__));
1443 pAudSetting->fmt = AUD_FMT_S8;
1444 break;
1445 case 1:
1446 Log(("hda: %s requested 16-bit\n", __FUNCTION__));
1447 pAudSetting->fmt = AUD_FMT_S16;
1448 break;
1449 case 2:
1450 Log(("hda: %s requested 20-bit\n", __FUNCTION__));
1451 break;
1452 case 3:
1453 Log(("hda: %s requested 24-bit\n", __FUNCTION__));
1454 break;
1455 case 4:
1456 Log(("hda: %s requested 32-bit\n", __FUNCTION__));
1457 pAudSetting->fmt = AUD_FMT_S32;
1458 break;
1459 default:
1460 AssertMsgFailed(("Unsupported"));
1461 }
1462 pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;
1463 pAudSetting->fmt = AUD_FMT_S16;
1464 pAudSetting->endianness = 0;
1465#undef EXTRACT_VALUE
1466}
1467
1468static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1469{
1470#ifdef VBOX_WITH_HDA_CODEC_EMU
1471 /** @todo a bit more investigation is required here. */
1472 int rc = 0;
1473 audsettings_t as;
1474 /* no reason to reopen voice with same settings */
1475 if (u32Value == HDA_REG_IND(pThis, iReg))
1476 return VINF_SUCCESS;
1477 hdaSdFmtToAudSettings(u32Value, &as);
1478 switch (iReg)
1479 {
1480 case ICH6_HDA_REG_SD0FMT:
1481 rc = codecOpenVoice(&pThis->Codec, PI_INDEX, &as);
1482 break;
1483 case ICH6_HDA_REG_SD4FMT:
1484 rc = codecOpenVoice(&pThis->Codec, PO_INDEX, &as);
1485 break;
1486 default:
1487 Log(("HDA: attempt to change format on %d\n", iReg));
1488 rc = 0;
1489 }
1490 return hdaRegWriteU16(pThis, iReg, u32Value);
1491#else
1492 return hdaRegWriteU16(pThis, iReg, u32Value);
1493#endif
1494}
1495
1496static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1497{
1498 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1499 if (RT_FAILURE(rc))
1500 AssertRCReturn(rc, VINF_SUCCESS);
1501 return rc;
1502}
1503
1504static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1505{
1506 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1507 if (RT_FAILURE(rc))
1508 AssertRCReturn(rc, VINF_SUCCESS);
1509 return rc;
1510}
1511
1512static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1513{
1514 int rc = VINF_SUCCESS;
1515 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1516 if ( CORBWP(pThis) != CORBRP(pThis)
1517 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1518 IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1519
1520 rc = hdaRegReadU32(pThis, iReg, pu32Value);
1521 return rc;
1522}
1523
1524static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1525{
1526 int rc = VINF_SUCCESS;
1527 uint64_t resp;
1528 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1529 /*
1530 * if guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1531 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1532 */
1533 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1534 && !IRS_ICB(pThis))
1535 {
1536 uint32_t cmd = IC(pThis);
1537 if (CORBWP(pThis) != CORBRP(pThis))
1538 {
1539 /*
1540 * 3.4.3 defines behavior of immediate Command status register.
1541 */
1542 LogRel(("hda: guest attempted process immediate verb (%x) with active CORB\n", cmd));
1543 return rc;
1544 }
1545 IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1546 Log(("hda: IC:%x\n", cmd));
1547 rc = pThis->Codec.pfnLookup(&pThis->Codec, cmd, &pfn);
1548 if (RT_FAILURE(rc))
1549 AssertRCReturn(rc, rc);
1550 rc = pfn(&pThis->Codec, cmd, &resp);
1551 if (RT_FAILURE(rc))
1552 AssertRCReturn(rc, rc);
1553 IR(pThis) = (uint32_t)resp;
1554 Log(("hda: IR:%x\n", IR(pThis)));
1555 IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1556 IRS(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1557 return rc;
1558 }
1559 /*
1560 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1561 */
1562 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1563 && IRS_IRV(pThis))
1564 IRS(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1565 return rc;
1566}
1567
1568static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1569{
1570 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1571 {
1572 RIRBWP(pThis) = 0;
1573 }
1574 /* The remaining bits are O, see 6.2.22 */
1575 return VINF_SUCCESS;
1576}
1577
1578static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1579{
1580 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1581 if (RT_FAILURE(rc))
1582 AssertRCReturn(rc, rc);
1583 switch(iReg)
1584 {
1585 case ICH6_HDA_REG_CORBLBASE:
1586 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
1587 pThis->u64CORBBase |= pThis->au32Regs[iReg];
1588 break;
1589 case ICH6_HDA_REG_CORBUBASE:
1590 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
1591 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iReg] << 32);
1592 break;
1593 case ICH6_HDA_REG_RIRLBASE:
1594 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
1595 pThis->u64RIRBBase |= pThis->au32Regs[iReg];
1596 break;
1597 case ICH6_HDA_REG_RIRUBASE:
1598 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
1599 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iReg] << 32);
1600 break;
1601 case ICH6_HDA_REG_DPLBASE:
1602 /** @todo: first bit has special meaning */
1603 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
1604 pThis->u64DPBase |= pThis->au32Regs[iReg];
1605 break;
1606 case ICH6_HDA_REG_DPUBASE:
1607 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
1608 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iReg] << 32);
1609 break;
1610 default:
1611 AssertMsgFailed(("Invalid index"));
1612 }
1613 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
1614 return rc;
1615}
1616
1617static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1618{
1619 uint8_t v = RIRBSTS(pThis);
1620 RIRBSTS(pThis) &= ~(v & u32Value);
1621
1622 return hdaProcessInterrupt(pThis);
1623}
1624
1625#ifdef LOG_ENABLED
1626static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1627{
1628#if 0
1629 uint64_t addr;
1630 uint32_t len;
1631 uint32_t ioc;
1632 uint8_t bdle[16];
1633 uint32_t counter;
1634 uint32_t i;
1635 uint32_t sum = 0;
1636 Assert(pBdle && pBdle->u32BdleMaxCvi);
1637 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1638 {
1639 PDMDevHlpPhysRead(pThis->pDevIns, u64BaseDMA + i*16, bdle, 16);
1640 addr = *(uint64_t *)bdle;
1641 len = *(uint32_t *)&bdle[8];
1642 ioc = *(uint32_t *)&bdle[12];
1643 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1644 sum += len;
1645 }
1646 Log(("hda: sum: %d\n", sum));
1647 for (i = 0; i < 8; ++i)
1648 {
1649 PDMDevHlpPhysRead(pThis->pDevIns, (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1650 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
1651 i , counter));
1652 }
1653#endif
1654}
1655#endif
1656
1657static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1658{
1659 uint8_t bdle[16];
1660 Assert(( pStreamDesc->u64BaseDMA
1661 && pBdle
1662 && pBdle->u32BdleMaxCvi));
1663 PDMDevHlpPhysRead(pThis->pDevIns, pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1664 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1665 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1666 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1667#ifdef LOG_ENABLED
1668 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
1669#endif
1670}
1671
1672DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1673 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1674{
1675 uint32_t cb2Copy;
1676 /*
1677 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
1678 */
1679 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1680 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1681 /*
1682 * we may increase the counter in range of [0, FIFOS + 1]
1683 */
1684 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1685 Assert((u32SoundBackendBufferBytesAvail > 0));
1686
1687 /* sanity check to avoid overriding the backend audio buffer */
1688 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1689 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1690
1691 if (cb2Copy <= pBdle->cbUnderFifoW)
1692 return 0;
1693 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
1694 return cb2Copy;
1695}
1696
1697DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1698 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1699{
1700 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1701 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1702 Assert((cbCopied));
1703 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1704 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
1705 * Probably we need to move the buffer, but it is rather hard to imagine a situation
1706 * where it might happen.
1707 */
1708 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write the entire buffer including unreported bytes */
1709 if ( pBdle->cbUnderFifoW
1710 && pBdle->cbUnderFifoW <= cbCopied)
1711 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1712
1713 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1714 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
1715
1716 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
1717 pBdle->u32BdleCviPos += cbArranged2Copy;
1718
1719 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1720 /* We report all bytes (including previously unreported bytes) */
1721 *pu32DMACursor += cbCopied;
1722 /* Decrease the backend counter by the number of bytes we copied to the backend */
1723 *pu32BackendBufferCapacity -= cbCopied;
1724 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1725 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1726}
1727
1728DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1729 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1730{
1731 Assert((cbCopied, cbArranged2Copy));
1732 *pu32BackendBufferCapacity -= cbCopied;
1733 pBdle->u32BdleCviPos += cbCopied;
1734 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1735 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1736 pBdle->cbUnderFifoW = 0;
1737 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1738 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1739}
1740
1741DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1742 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1743{
1744 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1745 pBdle->u32BdleCviPos += cbCopied;
1746 pBdle->cbUnderFifoW += cbCopied;
1747 /* In case of a read transaction we're always copying from the backend buffer */
1748 if (pu32BackendBufferCapacity)
1749 *pu32BackendBufferCapacity -= cbCopied;
1750 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1751 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
1752}
1753
1754DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1755{
1756 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1757 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1758
1759 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1760
1761 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1762 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1763 hdaUpdatePosBuf(pThis, pStreamDesc);
1764
1765 /* don't touch BdleCvi counter on uninitialized descriptor */
1766 if ( pBdle->u32BdleCviPos
1767 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1768 {
1769 pBdle->u32BdleCviPos = 0;
1770 pBdle->u32BdleCvi++;
1771 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1772 pBdle->u32BdleCvi = 0;
1773 }
1774 return fOnBufferEdge;
1775}
1776
1777DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1778 uint32_t cbInc)
1779{
1780 /*
1781 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
1782 * (ICH6 datasheet 18.2.38)
1783 */
1784 if (!pBdle->cbUnderFifoW)
1785 {
1786 *pStreamDesc->pu32Lpib += cbInc;
1787
1788 /*
1789 * Assert. The buffer counters should never overlap.
1790 */
1791 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1792
1793 hdaUpdatePosBuf(pThis, pStreamDesc);
1794
1795 }
1796}
1797
1798static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1799{
1800 bool fDoNextTransferLoop = true;
1801 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1802 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1803 {
1804 if ( !pBdle->cbUnderFifoW
1805 && pBdle->fBdleCviIoc)
1806 {
1807 /**
1808 * @todo - more carefully investigate BCIS flag.
1809 * Speech synthesis works fine on Mac Guest if this bit isn't set
1810 * but in general sound quality gets worse.
1811 */
1812 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1813
1814 /*
1815 * we should generate the interrupt if ICE bit of SDCTL register is set.
1816 */
1817 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1818 hdaProcessInterrupt(pThis);
1819 }
1820 fDoNextTransferLoop = false;
1821 }
1822 return fDoNextTransferLoop;
1823}
1824
1825/*
1826 * hdaReadAudio - copies samples from audio backend to DMA.
1827 * Note: this function writes to the DMA buffer immediately, but "reports bytes" when all conditions are met (FIFOW)
1828 */
1829static uint32_t hdaReadAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1830{
1831 PHDABDLEDESC pBdle = &pThis->StInBdle;
1832 uint32_t cbTransferred = 0;
1833 uint32_t cb2Copy = 0;
1834 uint32_t cbBackendCopy = 0;
1835
1836 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1837
1838 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1839 if (!cb2Copy)
1840 {
1841 /* if we enter here we can't report "unreported bits" */
1842 *fStop = true;
1843 goto l_done;
1844 }
1845
1846
1847 /*
1848 * read from backend input line to the last unreported position or at the begining.
1849 */
1850 cbBackendCopy = AUD_read(pThis->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1851 /*
1852 * write the HDA DMA buffer
1853 */
1854 PDMDevHlpPhysWrite(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1855
1856 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
1857 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1858
1859 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pThis, 0))
1860 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1861 else
1862 {
1863 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1864 *fStop = true;
1865 }
1866l_done:
1867 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
1868 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1869 return cbTransferred;
1870}
1871
1872static uint32_t hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1873{
1874 PHDABDLEDESC pBdle = &pThis->StOutBdle;
1875 uint32_t cbTransferred = 0;
1876 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1877 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1878
1879 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1880
1881 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1882
1883 /*
1884 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
1885 * previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
1886 */
1887 if (!cb2Copy)
1888 {
1889 *fStop = true;
1890 goto l_done;
1891 }
1892
1893 PDMDevHlpPhysRead(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1894 /*
1895 * Write to audio backend. we should ensure that we have enough bytes to copy to the backend.
1896 */
1897 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
1898 {
1899 /*
1900 * Feed the newly fetched samples, including unreported ones, to the backend.
1901 */
1902 cbBackendCopy = AUD_write (pThis->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1903 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1904 }
1905 else
1906 {
1907 /* Not enough bytes to be processed and reported, we'll try our luck next time around */
1908 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
1909 *fStop = true;
1910 }
1911
1912l_done:
1913 Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
1914 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransferred:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1915 return cbTransferred;
1916}
1917
1918/**
1919 * @interface_method_impl{HDACODEC,pfnReset}
1920 */
1921DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1922{
1923 PHDASTATE pThis = (PHDASTATE)pCodecState->pvHDAState;
1924 return VINF_SUCCESS;
1925}
1926
1927DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
1928 PHDASTREAMTRANSFERDESC pStreamDesc)
1929{
1930 Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
1931
1932 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1933 pStreamDesc->u8Strm = u8Strm;
1934 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pThis, CTL, u8Strm);
1935 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pThis, BDPL, u8Strm),
1936 HDA_STREAM_REG2(pThis, BDPU, u8Strm));
1937 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pThis, LPIB, u8Strm);
1938 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pThis, STS, u8Strm);
1939 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pThis, CBL, u8Strm);
1940 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pThis, FIFOS, u8Strm);
1941
1942 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pThis, LVI, u8Strm);
1943
1944#ifdef LOG_ENABLED
1945 if ( pBdle
1946 && pBdle->u32BdleMaxCvi)
1947 {
1948 Log(("Initialization of transfer descriptor:\n"));
1949 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
1950 }
1951#endif
1952}
1953
1954
1955/**
1956 * @interface_method_impl{HDACODEC,pfnTransfer}
1957 */
1958static DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1959{
1960 PHDASTATE pThis = (PHDASTATE)pCodecState->pvHDAState;
1961 uint8_t u8Strm = 0;
1962 PHDABDLEDESC pBdle = NULL;
1963
1964 switch (src)
1965 {
1966 case PO_INDEX:
1967 {
1968 u8Strm = 4;
1969 pBdle = &pThis->StOutBdle;
1970 break;
1971 }
1972 case PI_INDEX:
1973 {
1974 u8Strm = 0;
1975 pBdle = &pThis->StInBdle;
1976 break;
1977 }
1978 default:
1979 return;
1980 }
1981
1982 HDASTREAMTRANSFERDESC StreamDesc;
1983 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1984
1985 bool fStop = false;
1986 while (avail && !fStop)
1987 {
1988 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1989 && avail
1990 && StreamDesc.u64BaseDMA);
1991
1992 /* Fetch the Buffer Descriptor Entry (BDE). */
1993
1994 if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
1995 hdaFetchBdle(pThis, pBdle, &StreamDesc);
1996 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1997 Assert((avail >= 0 && (StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib)))); /* sanity */
1998 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
1999 Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
2000 Log(("hda: CBL=%d, LPIB=%d\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
2001 uint32_t cb;
2002 switch (src)
2003 {
2004 case PO_INDEX:
2005 cb = hdaWriteAudio(pThis, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
2006 break;
2007 case PI_INDEX:
2008 cb = hdaReadAudio(pThis, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
2009 break;
2010 default:
2011 cb = 0;
2012 fStop = true;
2013 AssertMsgFailed(("Unsupported"));
2014 }
2015 Assert(cb <= StreamDesc.u32Fifos + 1);
2016 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2017
2018 /* Process end of buffer condition. */
2019 hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cb);
2020 fStop = !fStop ? !hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc) : fStop;
2021 }
2022}
2023
2024
2025/* MMIO callbacks */
2026
2027/**
2028 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
2029 *
2030 * @note During implementation, we discovered so-called "forgotten" or "hole"
2031 * registers whose description is not listed in the RPM, datasheet, or
2032 * spec.
2033 */
2034PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2035{
2036 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2037 int rc;
2038
2039 /*
2040 * Look up and log.
2041 */
2042 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2043 int idxReg = hdaRegLookup(pThis, offReg);
2044#ifdef LOG_ENABLED
2045 unsigned const cbLog = cb;
2046 uint32_t offRegLog = offReg;
2047#endif
2048
2049 Log(("hdaMMIORead: offReg=%#x cb=%#x\n", offReg, cb));
2050#define NEW_READ_CODE
2051#ifdef NEW_READ_CODE
2052 Assert(cb == 4); Assert((offReg & 3) == 0);
2053
2054 if (pThis->fInReset && idxReg != ICH6_HDA_REG_GCTL)
2055 Log(("hda: access to registers except GCTL is blocked while reset\n"));
2056
2057 if (idxReg == -1)
2058 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
2059
2060 if (idxReg != -1)
2061 {
2062 /* ASSUMES gapless DWORD at end of map. */
2063 if (g_aHdaRegMap[idxReg].size == 4)
2064 {
2065 /*
2066 * Straight forward DWORD access.
2067 */
2068 rc = g_aHdaRegMap[idxReg].pfnRead(pThis, idxReg, (uint32_t *)pv);
2069 Log(("hda: read %s => %x (%Rrc)\n", g_aHdaRegMap[idxReg].abbrev, *(uint32_t *)pv, rc));
2070 }
2071 else
2072 {
2073 /*
2074 * Multi register read (unless there are trailing gaps).
2075 * ASSUMES that only DWORD reads have sideeffects.
2076 */
2077 uint32_t u32Value = 0;
2078 unsigned cbLeft = 4;
2079 do
2080 {
2081 uint32_t const cbReg = g_aHdaRegMap[idxReg].size;
2082 uint32_t u32Tmp = 0;
2083
2084 rc = g_aHdaRegMap[idxReg].pfnRead(pThis, idxReg, &u32Tmp);
2085 Log(("hda: read %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxReg].abbrev, cbReg, *(uint32_t *)pv, rc));
2086 if (rc != VINF_SUCCESS)
2087 break;
2088 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
2089
2090 cbLeft -= cbReg;
2091 offReg += cbReg;
2092 idxReg++;
2093 } while (cbLeft > 0 && g_aHdaRegMap[idxReg].offset == offReg);
2094
2095 if (rc == VINF_SUCCESS)
2096 *(uint32_t *)pv = u32Value;
2097 else
2098 Assert(!IOM_SUCCESS(rc));
2099 }
2100 }
2101 else
2102 {
2103 rc = VINF_IOM_MMIO_UNUSED_FF;
2104 Log(("hda: hole at %x is accessed for read\n", offReg));
2105 }
2106#else
2107 if (idxReg != -1)
2108 {
2109 /** @todo r=bird: Accesses crossing register boundraries aren't handled
2110 * right from what I can tell? If they are, please explain
2111 * what the rules are. */
2112 uint32_t mask = 0;
2113 uint32_t shift = (g_aHdaRegMap[idxReg].offset - offReg) % sizeof(uint32_t) * 8;
2114 uint32_t u32Value = 0;
2115 switch(cb)
2116 {
2117 case 1: mask = 0x000000ff; break;
2118 case 2: mask = 0x0000ffff; break;
2119 case 4:
2120 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2121 case 8:
2122 mask = 0xffffffff;
2123 cb = 4;
2124 break;
2125 }
2126#if 0
2127 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
2128 */
2129 //Assert((cb <= g_aHdaRegMap[idxReg].size - (offReg - g_aHdaRegMap[idxReg].offset)));
2130 if (cb > g_aHdaRegMap[idxReg].size - (offReg - g_aHdaRegMap[idxReg].offset))
2131 {
2132 int off = cb - (g_aHdaRegMap[idxReg].size - (offReg - g_aHdaRegMap[idxReg].offset));
2133 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2134 if (RT_FAILURE(rc))
2135 AssertRCReturn (rc, rc);
2136 }
2137 //Assert(((offReg - g_aHdaRegMap[idxReg].offset) == 0));
2138#endif
2139 mask <<= shift;
2140 rc = g_aHdaRegMap[idxReg].pfnRead(pThis, idxReg, &u32Value);
2141 *(uint32_t *)pv |= (u32Value & mask);
2142 Log(("hda: read %s[%x/%x]\n", g_aHdaRegMap[idxReg].abbrev, u32Value, *(uint32_t *)pv));
2143 }
2144 else
2145 {
2146 *(uint32_t *)pv = 0xFF;
2147 Log(("hda: hole at %x is accessed for read\n", offReg));
2148 rc = VINF_SUCCESS;
2149 }
2150#endif
2151
2152 /*
2153 * Log the outcome.
2154 */
2155#ifdef LOG_ENABLED
2156 if (cbLog == 4)
2157 Log(("hdaMMIORead: @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
2158 else if (cbLog == 2)
2159 Log(("hdaMMIORead: @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
2160 else if (cbLog == 1)
2161 Log(("hdaMMIORead: @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
2162#endif
2163 return rc;
2164}
2165
2166
2167DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxReg, uint32_t u32Value, char const *pszLog)
2168{
2169 if (pThis->fInReset && idxReg != ICH6_HDA_REG_GCTL)
2170 Log(("hda: access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
2171
2172#ifdef LOG_ENABLED
2173 uint32_t const u32CurValue = pThis->au32Regs[idxReg];
2174#endif
2175 int rc = g_aHdaRegMap[idxReg].pfnWrite(pThis, idxReg, u32Value);
2176 Log(("hda: write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxReg].abbrev,
2177 g_aHdaRegMap[idxReg].size, u32CurValue, pThis->au32Regs[idxReg], pszLog));
2178 return rc;
2179}
2180
2181
2182/**
2183 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
2184 */
2185PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2186{
2187 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2188 int rc;
2189
2190 /*
2191 * The behavior of accesses that aren't aligned on natural boundraries is
2192 * undefined. Just reject them out right.
2193 */
2194 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
2195 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
2196 if (GCPhysAddr & (cb - 1))
2197 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
2198
2199 /*
2200 * Lookup and log the access.
2201 */
2202 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2203 int idxReg = hdaRegLookup(pThis, offReg);
2204 uint64_t u64Value;
2205 if (cb == 4) u64Value = *(uint32_t const *)pv;
2206 else if (cb == 2) u64Value = *(uint16_t const *)pv;
2207 else if (cb == 1) u64Value = *(uint8_t const *)pv;
2208 else if (cb == 8) u64Value = *(uint64_t const *)pv;
2209 else
2210 AssertReleaseMsgFailed(("%d\n", cb));
2211
2212#ifdef LOG_ENABLED
2213 uint32_t const u32LogOldValue = idxReg != -1 ? pThis->au32Regs[idxReg] : UINT32_MAX;
2214 uint32_t const offRegLog = offReg;
2215 int const idxRegLog = idxReg;
2216 if (idxReg == -1)
2217 Log(("hdaMMIOWrite: @%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
2218 else if (cb == 4)
2219 Log(("hdaMMIOWrite: @%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxReg].abbrev));
2220 else if (cb == 2)
2221 Log(("hdaMMIOWrite: @%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxReg].abbrev));
2222 else if (cb == 1)
2223 Log(("hdaMMIOWrite: @%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxReg].abbrev));
2224 if (idxReg != -1 && g_aHdaRegMap[idxReg].size != cb)
2225 Log(("hdaMMIOWrite: size=%d != cb=%d!!\n", g_aHdaRegMap[idxReg].size, cb));
2226#endif
2227
2228#define NEW_WRITE_CODE
2229#ifdef NEW_WRITE_CODE
2230 /*
2231 * Try for a direct hit first.
2232 */
2233 if (idxReg != -1 && g_aHdaRegMap[idxReg].size == cb)
2234 rc = hdaWriteReg(pThis, idxReg, u64Value, "");
2235 /*
2236 * Partial or multiple register access, loop thru the requested memory.
2237 */
2238 else
2239 {
2240 /* If it's an access beyond the start of the register, shift the input
2241 value and fill in missing bits. Natural alignment rules means we
2242 will only see 1 or 2 byte accesses of this kind, so no risk of
2243 shifting out input values. */
2244 if (idxReg == -1 && (idxReg = hdaRegLookupWithin(pThis, offReg)) != -1)
2245 {
2246 uint32_t const cbBefore = g_aHdaRegMap[idxReg].offset - offReg; Assert(cbBefore > 0 && cbBefore < 4);
2247 offReg -= cbBefore;
2248 u64Value <<= cbBefore * 8;
2249 u64Value |= pThis->au32Regs[idxReg] & g_afMasks[cbBefore];
2250 Log(("hdaMMIOWrite: Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
2251 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
2252 }
2253
2254 /* Loop thru the write area, it may covert multiple registers. */
2255 rc = VINF_SUCCESS;
2256 for (;;)
2257 {
2258 uint32_t cbReg;
2259 if (idxReg != -1)
2260 {
2261 cbReg = g_aHdaRegMap[idxReg].size;
2262 if (cb < cbReg)
2263 {
2264 u64Value |= pThis->au32Regs[idxReg] & g_afMasks[cbReg] & ~g_afMasks[cb];
2265 Log(("hdaMMIOWrite: Supplying missing bits (%#x): %#llx -> %#llx ...\n",
2266 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
2267 }
2268 rc = hdaWriteReg(pThis, idxReg, u64Value, "*");
2269 }
2270 else
2271 {
2272 LogRel(("hda: Invalid write access @0x%x!\n", offReg));
2273 cbReg = 1;
2274 }
2275 if (cbReg >= cb)
2276 break;
2277
2278 /* advance */
2279 offReg += cbReg;
2280 cb -= cbReg;
2281 u64Value >>= cbReg * 8;
2282 if (idxReg == -1)
2283 idxReg = hdaRegLookup(pThis, offReg);
2284 else
2285 {
2286 idxReg++;
2287 if ( (unsigned)idxReg >= RT_ELEMENTS(g_aHdaRegMap)
2288 || g_aHdaRegMap[idxReg].offset != offReg)
2289 idxReg = -1;
2290 }
2291 }
2292 }
2293#else
2294 if (idxReg != -1)
2295 {
2296 /** @todo r=bird: This looks like code for handling unaligned register
2297 * accesses. If it isn't, then add a comment explaining what you're
2298 * trying to do here. OTOH, if it is then it has the following
2299 * issues:
2300 * -# You're calculating the wrong new value for the register.
2301 * -# You're not handling cross register accesses. Imagine a
2302 * 4-byte write starting at CORBCTL, or a 8-byte write.
2303 *
2304 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
2305 * nobody seems to be using it and it just adds complexity when reading
2306 * the code.
2307 *
2308 */
2309 uint32_t u32CurValue = pThis->au32Regs[idxReg];
2310 uint32_t u32NewValue;
2311 uint32_t mask;
2312 switch (cb)
2313 {
2314 case 1:
2315 u32NewValue = *(uint8_t const *)pv;
2316 mask = 0xff;
2317 break;
2318 case 2:
2319 u32NewValue = *(uint16_t const *)pv;
2320 mask = 0xffff;
2321 break;
2322 case 4:
2323 case 8:
2324 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2325 u32NewValue = *(uint32_t const *)pv;
2326 mask = 0xffffffff;
2327 cb = 4;
2328 break;
2329 default:
2330 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
2331 }
2332 /* cross-register access, see corresponding comment in hdaMMIORead */
2333 uint32_t shift = (g_aHdaRegMap[idxReg].offset - offReg) % sizeof(uint32_t) * 8;
2334 mask <<= shift;
2335 u32NewValue <<= shift;
2336 u32NewValue &= mask;
2337 u32NewValue |= (u32CurValue & ~mask);
2338
2339 rc = g_aHdaRegMap[idxReg].pfnWrite(pThis, idxReg, u32NewValue);
2340 Log(("hda: write %s:(%x) %x => %x\n", g_aHdaRegMap[idxReg].abbrev, u32NewValue,
2341 u32CurValue, pThis->au32Regs[idxReg]));
2342 }
2343 else
2344 rc = VINF_SUCCESS;
2345#endif
2346 Log(("hdaMMIOWrite: @%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2347 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2348 return rc;
2349}
2350
2351
2352/* PCI callback. */
2353
2354/**
2355 * @callback_method_impl{FNPCIIOREGIONMAP}
2356 */
2357static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
2358 PCIADDRESSSPACE enmType)
2359{
2360 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2361 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
2362 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
2363 int rc;
2364
2365 /*
2366 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
2367 *
2368 * Let IOM talk DWORDs when reading, saves a lot of complications. On
2369 * writing though, we have to do it all ourselves because of sideeffects.
2370 */
2371 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2372 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2373#ifdef NEW_READ_CODE
2374 IOMMMIO_FLAGS_READ_DWORD |
2375#else
2376 IOMMMIO_FLAGS_READ_PASSTHRU |
2377#endif
2378 IOMMMIO_FLAGS_WRITE_PASSTHRU,
2379 hdaMMIOWrite, hdaMMIORead, "ICH6_HDA");
2380
2381 if (RT_FAILURE(rc))
2382 return rc;
2383
2384 pThis->MMIOBaseAddr = GCPhysAddress;
2385 return VINF_SUCCESS;
2386}
2387
2388
2389/* Saved state callbacks. */
2390
2391/**
2392 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2393 */
2394static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2395{
2396 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2397 /* Save Codec nodes states */
2398 codecSaveState(&pThis->Codec, pSSM);
2399
2400 /* Save MMIO registers */
2401 AssertCompile(RT_ELEMENTS(pThis->au32Regs) == 112);
2402 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
2403 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
2404
2405 /* Save HDA dma counters */
2406 SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2407 SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2408 SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2409 return VINF_SUCCESS;
2410}
2411
2412
2413/**
2414 * @callback_method_impl{FNSSMDEVLOADEXEC}
2415 */
2416static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2417{
2418 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2419
2420 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2421
2422 /*
2423 * Load Codec nodes states.
2424 */
2425 int rc = codecLoadState(&pThis->Codec, pSSM, uVersion);
2426 if (RT_FAILURE(rc))
2427 return rc;
2428
2429 /*
2430 * Load MMIO registers.
2431 */
2432 uint32_t cRegs;
2433 switch (uVersion)
2434 {
2435 case HDA_SSM_VERSION_1:
2436 /* Starting with r71199, we would save 112 instead of 113
2437 registers due to some code cleanups. This only affected trunk
2438 builds in the 4.1 development period. */
2439 cRegs = 113;
2440 if (SSMR3HandleRevision(pSSM) >= 71199)
2441 {
2442 uint32_t uVer = SSMR3HandleVersion(pSSM);
2443 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
2444 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
2445 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
2446 cRegs = 112;
2447 }
2448 break;
2449
2450 case HDA_SSM_VERSION_2:
2451 case HDA_SSM_VERSION_3:
2452 cRegs = 112;
2453 AssertCompile(RT_ELEMENTS(pThis->au32Regs) == 112);
2454 break;
2455
2456 case HDA_SSM_VERSION:
2457 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
2458 AssertLogRelMsgReturn(cRegs == RT_ELEMENTS(pThis->au32Regs),
2459 ("cRegs is %d, expected %d\n", cRegs, RT_ELEMENTS(pThis->au32Regs)),
2460 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2461 break;
2462
2463 default:
2464 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2465 }
2466
2467 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
2468 {
2469 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
2470 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
2471 }
2472 else
2473 {
2474 RT_ZERO(pThis->au32Regs);
2475 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
2476 }
2477
2478 /*
2479 * Load HDA dma counters.
2480 */
2481 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
2482 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
2483 SSMR3GetStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), fFlags, paFields, NULL);
2484 SSMR3GetStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), fFlags, paFields, NULL);
2485 rc = SSMR3GetStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), fFlags, paFields, NULL);
2486 AssertRCReturn(rc, rc);
2487
2488 /*
2489 * Update stuff after the state changes.
2490 */
2491 AUD_set_active_in(pThis->Codec.SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2492 AUD_set_active_out(pThis->Codec.SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2493
2494 pThis->u64CORBBase = RT_MAKE_U64(CORBLBASE(pThis), CORBUBASE(pThis));
2495 pThis->u64RIRBBase = RT_MAKE_U64(RIRLBASE(pThis), RIRUBASE(pThis));
2496 pThis->u64DPBase = RT_MAKE_U64(DPLBASE(pThis), DPUBASE(pThis));
2497 return VINF_SUCCESS;
2498}
2499
2500
2501/* Debug and log type formatters. */
2502
2503/**
2504 * @callback_method_impl{FNRTSTRFORMATTYPE}
2505 */
2506static DECLCALLBACK(size_t)
2507hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2508 const char *pszType, void const *pvValue,
2509 int cchWidth, int cchPrecision, unsigned fFlags,
2510 void *pvUser)
2511{
2512 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
2513 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2514 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
2515 sdCtl,
2516 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> ICH6_HDA_SDCTL_NUM_SHIFT,
2517 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
2518 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
2519 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> ICH6_HDA_SDCTL_STRIPE_SHIFT,
2520 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
2521 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
2522 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
2523 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
2524}
2525
2526/**
2527 * @callback_method_impl{FNRTSTRFORMATTYPE}
2528 */
2529static DECLCALLBACK(size_t)
2530hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2531 const char *pszType, void const *pvValue,
2532 int cchWidth, int cchPrecision, unsigned fFlags,
2533 void *pvUser)
2534{
2535 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
2536 uint32_t cb;
2537 switch (uSdFifos)
2538 {
2539 case HDA_SDONFIFO_16B: cb = 16; break;
2540 case HDA_SDONFIFO_32B: cb = 32; break;
2541 case HDA_SDONFIFO_64B: cb = 64; break;
2542 case HDA_SDONFIFO_128B: cb = 128; break;
2543 case HDA_SDONFIFO_192B: cb = 192; break;
2544 case HDA_SDONFIFO_256B: cb = 256; break;
2545 case HDA_SDINFIFO_120B: cb = 120; break;
2546 case HDA_SDINFIFO_160B: cb = 160; break;
2547 default: cb = 0; break;
2548 }
2549 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
2550}
2551
2552/**
2553 * @callback_method_impl{FNRTSTRFORMATTYPE}
2554 */
2555static DECLCALLBACK(size_t)
2556hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2557 const char *pszType, void const *pvValue,
2558 int cchWidth, int cchPrecision, unsigned fFlags,
2559 void *pvUser)
2560{
2561 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
2562 uint32_t cb;
2563 switch (uSdFifos)
2564 {
2565 case HDA_SDFIFOW_8B: cb = 8; break;
2566 case HDA_SDFIFOW_16B: cb = 16; break;
2567 case HDA_SDFIFOW_32B: cb = 32; break;
2568 default: cb = 0; break;
2569 }
2570 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
2571}
2572
2573/**
2574 * @callback_method_impl{FNRTSTRFORMATTYPE}
2575 */
2576static DECLCALLBACK(size_t)
2577hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2578 const char *pszType, void const *pvValue,
2579 int cchWidth, int cchPrecision, unsigned fFlags,
2580 void *pvUser)
2581{
2582 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
2583 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2584 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
2585 uSdSts,
2586 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
2587 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
2588 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
2589 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
2590}
2591
2592
2593static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
2594{
2595 int iReg = 0;
2596 for (; iReg < HDA_NREGS; ++iReg)
2597 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
2598 return iReg;
2599 return -1;
2600}
2601
2602
2603static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
2604{
2605 Assert( pThis
2606 && iHdaIndex >= 0
2607 && iHdaIndex < HDA_NREGS);
2608 pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[iHdaIndex]);
2609}
2610
2611
2612/**
2613 * @callback_method_impl{FNDBGFHANDLERDEV}
2614 */
2615static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2616{
2617 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2618 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
2619 if (iHdaRegisterIndex != -1)
2620 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
2621 else
2622 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
2623 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
2624}
2625
2626
2627static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
2628{
2629 Assert( pThis
2630 && iHdaStrmIndex >= 0
2631 && iHdaStrmIndex < 7);
2632 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
2633 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, CTL, iHdaStrmIndex));
2634 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, STS, iHdaStrmIndex));
2635 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, FIFOS, iHdaStrmIndex));
2636 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, FIFOW, iHdaStrmIndex));
2637}
2638
2639
2640static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
2641{
2642 /* todo: add args parsing */
2643 return -1;
2644}
2645
2646
2647/**
2648 * @callback_method_impl{FNDBGFHANDLERDEV}
2649 */
2650static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2651{
2652 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2653 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
2654 if (iHdaStrmIndex != -1)
2655 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
2656 else
2657 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
2658 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
2659}
2660
2661/**
2662 * @callback_method_impl{FNDBGFHANDLERDEV}
2663 */
2664static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2665{
2666 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2667 if (pThis->Codec.pfnCodecDbgListNodes)
2668 pThis->Codec.pfnCodecDbgListNodes(&pThis->Codec, pHlp, pszArgs);
2669 else
2670 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2671}
2672
2673
2674/**
2675 * @callback_method_impl{FNDBGFHANDLERDEV}
2676 */
2677static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2678{
2679 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2680 if (pThis->Codec.pfnCodecDbgSelector)
2681 pThis->Codec.pfnCodecDbgSelector(&pThis->Codec, pHlp, pszArgs);
2682 else
2683 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2684}
2685
2686
2687/* PDMIBASE */
2688
2689/**
2690 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2691 */
2692static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
2693{
2694 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
2695 Assert(&pThis->IBase == pInterface);
2696
2697 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2698 return NULL;
2699}
2700
2701
2702/* PDMDEVREG */
2703
2704/**
2705 * Reset notification.
2706 *
2707 * @returns VBox status.
2708 * @param pDevIns The device instance data.
2709 *
2710 * @remark The original sources didn't install a reset handler, but it seems to
2711 * make sense to me so we'll do it.
2712 */
2713static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
2714{
2715 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2716 GCAP(pThis) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
2717 VMIN(pThis) = 0x00; /* see 6.2.2 */
2718 VMAJ(pThis) = 0x01; /* see 6.2.3 */
2719 VMAJ(pThis) = 0x01; /* see 6.2.3 */
2720 OUTPAY(pThis) = 0x003C; /* see 6.2.4 */
2721 INPAY(pThis) = 0x001D; /* see 6.2.5 */
2722 pThis->au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
2723 pThis->au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
2724 CORBRP(pThis) = 0x0;
2725 RIRBWP(pThis) = 0x0;
2726
2727 Log(("hda: inter HDA reset.\n"));
2728 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
2729
2730 if (pThis->pu32CorbBuf)
2731 memset(pThis->pu32CorbBuf, 0, pThis->cbCorbBuf);
2732 else
2733 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
2734
2735 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
2736 if (pThis->pu64RirbBuf)
2737 memset(pThis->pu64RirbBuf, 0, pThis->cbRirbBuf);
2738 else
2739 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
2740
2741 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2742
2743 HDABDLEDESC StEmptyBdle;
2744 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2745 {
2746 HDASTREAMTRANSFERDESC StreamDesc;
2747 PHDABDLEDESC pBdle = NULL;
2748 if (u8Strm == 0)
2749 pBdle = &pThis->StInBdle;
2750 else if(u8Strm == 4)
2751 pBdle = &pThis->StOutBdle;
2752 else
2753 {
2754 memset(&StEmptyBdle, 0, sizeof(HDABDLEDESC));
2755 pBdle = &StEmptyBdle;
2756 }
2757 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2758 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
2759 HDA_STREAM_REG2(pThis, CTL, u8Strm) = 0;
2760 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
2761 }
2762
2763 /* emulation of codec "wake up" (HDA spec 5.5.1 and 6.5)*/
2764 STATESTS(pThis) = 0x1;
2765
2766 Log(("hda: reset finished\n"));
2767}
2768
2769
2770/**
2771 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2772 */
2773static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
2774{
2775 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2776
2777 int rc = codecDestruct(&pThis->Codec);
2778 AssertRC(rc);
2779
2780 RTMemFree(pThis->pu32CorbBuf);
2781 pThis->pu32CorbBuf = NULL;
2782
2783 RTMemFree(pThis->pu64RirbBuf);
2784 pThis->pu64RirbBuf = NULL;
2785
2786 return VINF_SUCCESS;
2787}
2788
2789/**
2790 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2791 */
2792static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2793{
2794 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2795 int rc;
2796
2797 Assert(iInstance == 0);
2798 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2799
2800 /*
2801 * Validations.
2802 */
2803 if (!CFGMR3AreValuesValid(pCfgHandle, "\0"))
2804 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2805 N_ ("Invalid configuration for the Intel HDA device"));
2806
2807 /// @todo r=michaln: This device may need R0/RC enabling, especially if guests
2808 /// poll some register(pThis).
2809
2810 /*
2811 * Initialize data (most of it anyway).
2812 */
2813 pThis->pDevIns = pDevIns;
2814 /* IBase */
2815 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
2816
2817 /* PCI Device */
2818 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
2819 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEICE_ID); /* HDA */
2820
2821 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
2822 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2823 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
2824 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
2825 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
2826 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2827 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
2828 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
2829 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2830 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
2831 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
2832
2833#if defined(HDA_AS_PCI_EXPRESS)
2834 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
2835#elif defined(VBOX_WITH_MSI_DEVICES)
2836 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
2837#else
2838 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
2839#endif
2840
2841 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2842 /// of these values needs to be properly documented!
2843 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2844 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
2845
2846 /* Power Management */
2847 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2848 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
2849 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2850
2851#ifdef HDA_AS_PCI_EXPRESS
2852 /* PCI Express */
2853 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2854 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
2855 /* Device flags */
2856 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
2857 /* version */ 0x1 |
2858 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2859 /* MSI */ (100) << 9 );
2860 /* Device capabilities */
2861 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2862 /* Device control */
2863 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
2864 /* Device status */
2865 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
2866 /* Link caps */
2867 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
2868 /* Link control */
2869 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
2870 /* Link status */
2871 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
2872 /* Slot capabilities */
2873 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
2874 /* Slot control */
2875 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
2876 /* Slot status */
2877 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
2878 /* Root control */
2879 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
2880 /* Root capabilities */
2881 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
2882 /* Root status */
2883 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
2884 /* Device capabilities 2 */
2885 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
2886 /* Device control 2 */
2887 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
2888 /* Link control 2 */
2889 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
2890 /* Slot control 2 */
2891 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
2892#endif
2893
2894 /*
2895 * Register the PCI device.
2896 */
2897 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
2898 if (RT_FAILURE(rc))
2899 return rc;
2900
2901 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
2902 if (RT_FAILURE(rc))
2903 return rc;
2904
2905#ifdef VBOX_WITH_MSI_DEVICES
2906 PDMMSIREG MsiReg;
2907 RT_ZERO(MsiReg);
2908 MsiReg.cMsiVectors = 1;
2909 MsiReg.iMsiCapOffset = 0x60;
2910 MsiReg.iMsiNextOffset = 0x50;
2911 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
2912 if (RT_FAILURE(rc))
2913 {
2914 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2915 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
2916 }
2917#endif
2918
2919 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2920 if (RT_FAILURE(rc))
2921 return rc;
2922
2923 /*
2924 * Attach driver.
2925 */
2926 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Audio Driver Port");
2927 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2928 Log(("hda: No attached driver!\n"));
2929 else if (RT_FAILURE(rc))
2930 {
2931 AssertMsgFailed(("Failed to attach Intel HDA LUN #0! rc=%Rrc\n", rc));
2932 return rc;
2933 }
2934
2935 pThis->Codec.pvHDAState = pThis;
2936 rc = codecConstruct(pDevIns, &pThis->Codec, pCfgHandle);
2937 if (RT_FAILURE(rc))
2938 AssertRCReturn(rc, rc);
2939
2940 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2941 verb F20 should provide device/codec recognition. */
2942 Assert(pThis->Codec.u16VendorId);
2943 Assert(pThis->Codec.u16DeviceId);
2944 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->Codec.u16VendorId); /* 2c ro - intel.) */
2945 PCIDevSetSubSystemId( &pThis->PciDev, pThis->Codec.u16DeviceId); /* 2e ro. */
2946
2947 hdaReset(pDevIns);
2948 pThis->Codec.id = 0;
2949 pThis->Codec.pfnTransfer = hdaTransfer;
2950 pThis->Codec.pfnReset = hdaCodecReset;
2951
2952 /*
2953 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2954 * hdaReset shouldn't affects these registers.
2955 */
2956 WAKEEN(pThis) = 0x0;
2957 STATESTS(pThis) = 0x0;
2958
2959 /*
2960 * Debug and string formatter types.
2961 */
2962 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
2963 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
2964 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
2965 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
2966
2967 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
2968 AssertRC(rc);
2969 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
2970 AssertRC(rc);
2971 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
2972 AssertRC(rc);
2973 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
2974 AssertRC(rc);
2975#if 0
2976 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
2977 AssertRC(rc);
2978#endif
2979
2980 /*
2981 * Some debug assertions.
2982 */
2983 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
2984 {
2985 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
2986 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
2987
2988 /* binary search order. */
2989 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
2990 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
2991 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
2992
2993 /* alignment. */
2994 AssertReleaseMsg( pReg->size == 1
2995 || (pReg->size == 2 && (pReg->offset & 1) == 0)
2996 || (pReg->size == 3 && (pReg->offset & 3) == 0)
2997 || (pReg->size == 4 && (pReg->offset & 3) == 0),
2998 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
2999
3000 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
3001 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
3002 if (pReg->offset & 3)
3003 {
3004 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
3005 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3006 if (pPrevReg)
3007 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
3008 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3009 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
3010 }
3011#if 0
3012 if ((pReg->offset + pReg->size) & 3)
3013 {
3014 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3015 if (pNextReg)
3016 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
3017 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3018 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3019 }
3020#endif
3021
3022 /* The final entry is a full dword, no gaps! Allows shortcuts. */
3023 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
3024 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3025 }
3026
3027 return VINF_SUCCESS;
3028}
3029
3030/**
3031 * The device registration structure.
3032 */
3033const PDMDEVREG g_DeviceICH6_HDA =
3034{
3035 /* u32Version */
3036 PDM_DEVREG_VERSION,
3037 /* szName */
3038 "hda",
3039 /* szRCMod */
3040 "",
3041 /* szR0Mod */
3042 "",
3043 /* pszDescription */
3044 "Intel HD Audio Controller",
3045 /* fFlags */
3046 PDM_DEVREG_FLAGS_DEFAULT_BITS,
3047 /* fClass */
3048 PDM_DEVREG_CLASS_AUDIO,
3049 /* cMaxInstances */
3050 1,
3051 /* cbInstance */
3052 sizeof(HDASTATE),
3053 /* pfnConstruct */
3054 hdaConstruct,
3055 /* pfnDestruct */
3056 hdaDestruct,
3057 /* pfnRelocate */
3058 NULL,
3059 /* pfnIOCtl */
3060 NULL,
3061 /* pfnPowerOn */
3062 NULL,
3063 /* pfnReset */
3064 hdaReset,
3065 /* pfnSuspend */
3066 NULL,
3067 /* pfnResume */
3068 NULL,
3069 /* pfnAttach */
3070 NULL,
3071 /* pfnDetach */
3072 NULL,
3073 /* pfnQueryInterface. */
3074 NULL,
3075 /* pfnInitComplete */
3076 NULL,
3077 /* pfnPowerOff */
3078 NULL,
3079 /* pfnSoftReset */
3080 NULL,
3081 /* u32VersionEnd */
3082 PDM_DEVREG_VERSION
3083};
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