HDAStream.cpp@ 87760

Last change on this file since 87760 was 87758, checked in by vboxsync, 4 years ago

Audio/HDA: Lots more code in the hope to resolve issue ticketoem2ref:36, namely:

Decoupled async I/O timing from guest driver-specific DMA timing to further reduce EMT workload.
Added data transfer heuristics (based on set-up DMA buffers) to detect Windows 10 guests (enabled by default).
Also expose and support 16kHz + 22,5kHz streams (16-bit signed).

Only tested on Win10 20H2 and various Ubuntu guests so far.

Property svn:eol-style set to native
Property svn:keywords set to Author Date Id Revision

File size: 84.5 KB

Line
1	/* $Id: HDAStream.cpp 87758 2021-02-15 12:14:09Z vboxsync $ */
2	/** @file
3	* HDAStream.cpp - Stream functions for HD Audio.
4	*/
5
6	/*
7	* Copyright (C) 2017-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_HDA
23	#include <VBox/log.h>
24
25	#include <iprt/mem.h>
26	#include <iprt/semaphore.h>
27
28	#include <VBox/AssertGuest.h>
29	#include <VBox/vmm/pdmdev.h>
30	#include <VBox/vmm/pdmaudioifs.h>
31
32	#include "DrvAudio.h"
33
34	#include "DevHDA.h"
35	#include "HDAStream.h"
36
37	#ifdef IN_RING3 /* whole file */
38
39
40	/*********************************************************************************************************************************
41	* Internal Functions *
42	*********************************************************************************************************************************/
43	static void hdaR3StreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB);
44
45	static int hdaR3StreamAsyncIODestroy(PHDASTREAMR3 pStreamR3);
46	static int hdaR3StreamAsyncIONotify(PHDASTREAMR3 pStreamR3);
47
48
49
50	/**
51	* Creates an HDA stream.
52	*
53	* @returns IPRT status code.
54	* @param pStreamShared The HDA stream to construct - shared bits.
55	* @param pStreamR3 The HDA stream to construct - ring-3 bits.
56	* @param pThis The shared HDA device instance.
57	* @param pThisCC The ring-3 HDA device instance.
58	* @param uSD Stream descriptor number to assign.
59	*/
60	int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis, PHDASTATER3 pThisCC, uint8_t uSD)
61	{
62	int rc;
63
64	pStreamR3->u8SD = uSD;
65	pStreamShared->u8SD = uSD;
66	pStreamR3->pMixSink = NULL;
67	pStreamR3->pHDAStateShared = pThis;
68	pStreamR3->pHDAStateR3 = pThisCC;
69	Assert(pStreamShared->hTimer != NIL_TMTIMERHANDLE); /* hdaR3Construct initalized this one already. */
70
71	pStreamShared->State.fInReset = false;
72	pStreamShared->State.fRunning = false;
73	#ifdef HDA_USE_DMA_ACCESS_HANDLER
74	RTListInit(&pStreamR3->State.lstDMAHandlers);
75	#endif
76
77	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
78	rc = RTCritSectInit(&pStreamR3->CritSect);
79	AssertRCReturn(rc, rc);
80	# endif
81
82	rc = hdaR3StreamPeriodCreate(&pStreamShared->State.Period);
83	AssertRCReturn(rc, rc);
84
85	#ifdef DEBUG
86	rc = RTCritSectInit(&pStreamR3->Dbg.CritSect);
87	AssertRCReturn(rc, rc);
88	#endif
89
90	const bool fIsInput = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN;
91
92	if (fIsInput)
93	{
94	pStreamShared->State.Cfg.u.enmSrc = PDMAUDIORECSRC_UNKNOWN;
95	pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_IN;
96	}
97	else
98	{
99	pStreamShared->State.Cfg.u.enmDst = PDMAUDIOPLAYBACKDST_UNKNOWN;
100	pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_OUT;
101	}
102
103	pStreamR3->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
104
105	if (pStreamR3->Dbg.Runtime.fEnabled)
106	{
107	char szFile[64];
108	char szPath[RTPATH_MAX];
109
110	/* pFileStream */
111	if (fIsInput)
112	RTStrPrintf(szFile, sizeof(szFile), "hdaStreamWriteSD%RU8", uSD);
113	else
114	RTStrPrintf(szFile, sizeof(szFile), "hdaStreamReadSD%RU8", uSD);
115
116	int rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
117	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
118	AssertRC(rc2);
119
120	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileStream);
121	AssertRC(rc2);
122
123	/* pFileDMARaw */
124	if (fIsInput)
125	RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawWriteSD%RU8", uSD);
126	else
127	RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawReadSD%RU8", uSD);
128
129	rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
130	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
131	AssertRC(rc2);
132
133	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMARaw);
134	AssertRC(rc2);
135
136	/* pFileDMAMapped */
137	if (fIsInput)
138	RTStrPrintf(szFile, sizeof(szFile), "hdaDMAWriteMappedSD%RU8", uSD);
139	else
140	RTStrPrintf(szFile, sizeof(szFile), "hdaDMAReadMappedSD%RU8", uSD);
141
142	rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
143	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
144	AssertRC(rc2);
145
146	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMAMapped);
147	AssertRC(rc2);
148
149	/* Delete stale debugging files from a former run. */
150	DrvAudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileStream);
151	DrvAudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMARaw);
152	DrvAudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMAMapped);
153	}
154
155	return rc;
156	}
157
158	/**
159	* Destroys an HDA stream.
160	*
161	* @param pStreamShared The HDA stream to destroy - shared bits.
162	* @param pStreamR3 The HDA stream to destroy - ring-3 bits.
163	*/
164	void hdaR3StreamDestroy(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
165	{
166	LogFlowFunc(("[SD%RU8] Destroying ...\n", pStreamShared->u8SD));
167
168	hdaR3StreamMapDestroy(&pStreamR3->State.Mapping);
169
170	int rc2;
171
172	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
173	rc2 = hdaR3StreamAsyncIODestroy(pStreamR3);
174	AssertRC(rc2);
175	#endif
176
177	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
178	if (RTCritSectIsInitialized(&pStreamR3->CritSect))
179	{
180	rc2 = RTCritSectDelete(&pStreamR3->CritSect);
181	AssertRC(rc2);
182	}
183	# endif
184
185	if (pStreamR3->State.pCircBuf)
186	{
187	RTCircBufDestroy(pStreamR3->State.pCircBuf);
188	pStreamR3->State.pCircBuf = NULL;
189	}
190
191	hdaR3StreamPeriodDestroy(&pStreamShared->State.Period);
192
193	#ifdef DEBUG
194	if (RTCritSectIsInitialized(&pStreamR3->Dbg.CritSect))
195	{
196	rc2 = RTCritSectDelete(&pStreamR3->Dbg.CritSect);
197	AssertRC(rc2);
198	}
199	#endif
200
201	if (pStreamR3->Dbg.Runtime.fEnabled)
202	{
203	DrvAudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileStream);
204	pStreamR3->Dbg.Runtime.pFileStream = NULL;
205
206	DrvAudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMARaw);
207	pStreamR3->Dbg.Runtime.pFileDMARaw = NULL;
208
209	DrvAudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMAMapped);
210	pStreamR3->Dbg.Runtime.pFileDMAMapped = NULL;
211	}
212
213	LogFlowFuncLeave();
214	}
215
216	/**
217	* Sets up ((re-)iniitalizes) an HDA stream.
218	*
219	* @returns IPRT status code. VINF_NO_CHANGE if the stream does not need
220	* be set-up again because the stream's (hardware) parameters did
221	* not change.
222	* @param pDevIns The device instance.
223	* @param pThis The shared HDA device state (for HW register
224	* parameters).
225	* @param pStreamShared HDA stream to set up, shared portion.
226	* @param pStreamR3 HDA stream to set up, ring-3 portion.
227	* @param uSD Stream descriptor number to assign it.
228	*/
229	int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
230	{
231	/* This must be valid all times. */
232	AssertReturn(uSD < HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
233
234	/* These member can only change on data corruption, despite what the code does further down (bird). */
235	AssertReturn(pStreamShared->u8SD == uSD, VERR_WRONG_ORDER);
236	AssertReturn(pStreamR3->u8SD == uSD, VERR_WRONG_ORDER);
237
238	const uint64_t u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
239	HDA_STREAM_REG(pThis, BDPU, uSD));
240	const uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, uSD);
241	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
242	const uint8_t u8FIFOS = HDA_STREAM_REG(pThis, FIFOS, uSD) + 1;
243	uint8_t u8FIFOW = hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, uSD));
244	const uint16_t u16FMT = HDA_STREAM_REG(pThis, FMT, uSD);
245
246	/* Is the bare minimum set of registers configured for the stream?
247	* If not, bail out early, as there's nothing to do here for us (yet). */
248	if ( !u64BDLBase
249	\|\| !u16LVI
250	\|\| !u32CBL
251	\|\| !u8FIFOS
252	\|\| !u8FIFOW
253	\|\| !u16FMT)
254	{
255	LogFunc(("[SD%RU8] Registers not set up yet, skipping (re-)initialization\n", uSD));
256	return VINF_SUCCESS;
257	}
258
259	PDMAUDIOPCMPROPS Props;
260	int rc = hdaR3SDFMTToPCMProps(u16FMT, &Props);
261	if (RT_FAILURE(rc))
262	{
263	LogRel(("HDA: Warning: Format 0x%x for stream #%RU8 not supported\n", HDA_STREAM_REG(pThis, FMT, uSD), uSD));
264	return rc;
265	}
266
267	/* Reset (any former) stream map. */
268	hdaR3StreamMapReset(&pStreamR3->State.Mapping);
269
270	/*
271	* Initialize the stream mapping in any case, regardless if
272	* we support surround audio or not. This is needed to handle
273	* the supported channels within a single audio stream, e.g. mono/stereo.
274	*
275	* In other words, the stream mapping always knows the real
276	* number of channels in a single audio stream.
277	*/
278	rc = hdaR3StreamMapInit(&pStreamR3->State.Mapping, &Props);
279	AssertRCReturn(rc, rc);
280
281	ASSERT_GUEST_LOGREL_MSG_RETURN( pStreamR3->State.Mapping.cbFrameSize > 0
282	&& u32CBL % pStreamR3->State.Mapping.cbFrameSize == 0,
283	("CBL for stream #%RU8 does not align to frame size (u32CBL=%u cbFrameSize=%u)\n",
284	uSD, u32CBL, pStreamR3->State.Mapping.cbFrameSize),
285	VERR_INVALID_PARAMETER);
286
287	#ifndef VBOX_WITH_AUDIO_HDA_51_SURROUND
288	if (Props.cChannels > 2)
289	{
290	/*
291	* When not running with surround support enabled, override the audio channel count
292	* with stereo (2) channels so that we at least can properly work with those.
293	*
294	* Note: This also involves dealing with surround setups the guest might has set up for us.
295	*/
296	LogRel2(("HDA: More than stereo (2) channels are not supported (%RU8 requested), "
297	"falling back to stereo channels for stream #%RU8\n", Props.cChannels, uSD));
298	Props.cChannels = 2;
299	Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(Props.cbSample, Props.cChannels);
300	}
301	#endif
302
303	/* Make sure the guest behaves regarding the stream's FIFO. */
304	ASSERT_GUEST_LOGREL_MSG_STMT(u8FIFOW <= u8FIFOS,
305	("Guest tried setting a bigger FIFOW (%RU8) than FIFOS (%RU8), limiting\n", u8FIFOW, u8FIFOS),
306	u8FIFOW = u8FIFOS /* ASSUMES that u8FIFOS has been validated. */);
307
308	pStreamShared->u8SD = uSD;
309
310	/* Update all register copies so that we later know that something has changed. */
311	pStreamShared->u64BDLBase = u64BDLBase;
312	pStreamShared->u16LVI = u16LVI;
313	pStreamShared->u32CBL = u32CBL;
314	pStreamShared->u8FIFOS = u8FIFOS;
315	pStreamShared->u8FIFOW = u8FIFOW;
316	pStreamShared->u16FMT = u16FMT;
317
318	PPDMAUDIOSTREAMCFG pCfg = &pStreamShared->State.Cfg;
319	pCfg->Props = Props;
320
321	/* Set the stream's direction. */
322	pCfg->enmDir = hdaGetDirFromSD(uSD);
323
324	/* The the stream's name, based on the direction. */
325	switch (pCfg->enmDir)
326	{
327	case PDMAUDIODIR_IN:
328	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
329	# error "Implement me!"
330	# else
331	pCfg->u.enmSrc = PDMAUDIORECSRC_LINE;
332	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
333	RTStrCopy(pCfg->szName, sizeof(pCfg->szName), "Line In");
334	# endif
335	break;
336
337	case PDMAUDIODIR_OUT:
338	/* Destination(s) will be set in hdaAddStreamOut(),
339	* based on the channels / stream layout. */
340	break;
341
342	default:
343	AssertFailedReturn(VERR_NOT_SUPPORTED);
344	break;
345	}
346
347	/* Assign the global device rate to the stream. */
348	pStreamShared->State.uTimerIoHz = pThis->uTimerHz;
349
350	/* Set scheduling hint (if available). */
351	if (pStreamShared->State.uTimerIoHz)
352	pCfg->Device.cMsSchedulingHint = RT_MS_1SEC / pStreamShared->State.uTimerIoHz;
353
354	LogRel2(("HDA: Stream #%RU8 DMA @ 0x%x (%RU32 bytes = %RU64ms total)\n",
355	uSD, pStreamShared->u64BDLBase, pStreamShared->u32CBL,
356	DrvAudioHlpBytesToMilli(pStreamShared->u32CBL, &pStreamShared->State.Cfg.Props)));
357
358	/* Make sure that the chosen Hz rate dividable by the stream's rate. */
359	if (pStreamShared->State.Cfg.Props.uHz % pStreamShared->State.uTimerIoHz != 0)
360	LogRel(("HDA: Stream #%RU8 timer Hz rate (%RU32) does not fit to stream #%RU8 timing (%RU32)\n",
361	uSD, pStreamShared->State.uTimerIoHz, uSD, pStreamShared->State.Cfg.Props.uHz));
362
363	/* Figure out how many transfer fragments we're going to use for this stream. */
364	uint8_t cTransferFragments = pStreamShared->u16LVI + 1;
365	if (cTransferFragments <= 1)
366	LogRel(("HDA: Warning: Stream #%RU8 transfer fragments (%RU8) invalid -- buggy guest audio driver!\n",
367	uSD, pStreamShared->u16LVI));
368
369	/*
370	* Handle the stream's position adjustment.
371	*/
372	uint32_t cfPosAdjust = 0;
373
374	LogFunc(("[SD%RU8] fPosAdjustEnabled=%RTbool, cPosAdjustFrames=%RU16\n",
375	uSD, pThis->fPosAdjustEnabled, pThis->cPosAdjustFrames));
376
377	if (pThis->fPosAdjustEnabled) /* Is the position adjustment enabled at all? */
378	{
379	HDABDLE BDLE;
380	RT_ZERO(BDLE);
381
382	int rc2 = hdaR3BDLEFetch(pDevIns, &BDLE, pStreamShared->u64BDLBase, 0 /* Entry */);
383	AssertRC(rc2);
384
385	/* Note: Do not check if this BDLE aligns to the stream's frame size.
386	* It can happen that this isn't the case on some guests, e.g.
387	* on Windows with a 5.1 speaker setup.
388	*
389	* The only thing which counts is that the stream's CBL value
390	* properly aligns to the stream's frame size.
391	*/
392
393	/* If no custom set position adjustment is set, apply some
394	* simple heuristics to detect the appropriate position adjustment. */
395	if ( !pThis->cPosAdjustFrames
396	/* Position adjustmenet buffer must have the IOC bit set! */
397	&& hdaR3BDLENeedsInterrupt(&BDLE))
398	{
399	/** @todo Implement / use a (dynamic) table once this gets more complicated. */
400	#ifdef VBOX_WITH_INTEL_HDA
401	/* Intel ICH / PCH: 1 frame. */
402	if (BDLE.Desc.u32BufSize == (uint32_t)(1 * pStreamR3->State.Mapping.cbFrameSize))
403	{
404	cfPosAdjust = 1;
405	}
406	/* Intel Baytrail / Braswell: 32 frames. */
407	else if (BDLE.Desc.u32BufSize == (uint32_t)(32 * pStreamR3->State.Mapping.cbFrameSize))
408	{
409	cfPosAdjust = 32;
410	}
411	#endif
412	}
413	else /* Go with the set default. */
414	cfPosAdjust = pThis->cPosAdjustFrames;
415
416	if (cfPosAdjust)
417	{
418	/* Also adjust the number of fragments, as the position adjustment buffer
419	* does not count as an own fragment as such.
420	*
421	* This e.g. can happen on (newer) Ubuntu guests which use
422	* 4 (IOC) + 4408 (IOC) + 4408 (IOC) + 4408 (IOC) + 4404 (= 17632) bytes,
423	* where the first buffer (4) is used as position adjustment.
424	*
425	* Only skip a fragment if the whole buffer fragment is used for
426	* position adjustment.
427	*/
428	if ((cfPosAdjust * pStreamR3->State.Mapping.cbFrameSize) == BDLE.Desc.u32BufSize)
429	cTransferFragments--;
430
431	/* Initialize position adjustment counter. */
432	pStreamShared->State.cfPosAdjustDefault = cfPosAdjust;
433	pStreamShared->State.cfPosAdjustLeft = pStreamShared->State.cfPosAdjustDefault;
434
435	LogRel2(("HDA: Position adjustment for stream #%RU8 active (%RU32 frames)\n",
436	uSD, pStreamShared->State.cfPosAdjustDefault));
437	}
438	}
439
440	Log3Func(("[SD%RU8] cfPosAdjust=%RU32, cFragments=%RU8\n", uSD, cfPosAdjust, cTransferFragments));
441
442	/*
443	* Set up data transfer stuff.
444	*/
445
446	/* Prevent division by zero. */
447	ASSERT_GUEST_LOGREL_MSG_STMT(pStreamShared->State.uTimerIoHz,
448	("Timer Hz rate for stream #%RU8 is invalid\n", uSD),
449	pStreamShared->State.uTimerIoHz = HDA_TIMER_HZ_DEFAULT);
450	/*
451	* Determine the transfer Hz the guest OS expects data transfer at.
452	*
453	* Guests also expect a very extact DMA timing for reading / writing audio data, so we run on a constant
454	* (virtual) rate which we expose to the guest.
455	*
456	* Data rate examples:
457	* * Windows 10 @ 44,1kHz / 16-bit stereo
458	* * Default mode: 448 audio frames -> ~10.15ms) = 1792 byte every ~10ms.
459	* * Fast mode: 128 audio frames -> ~ 2.90ms) = 512 byte every ~3ms.
460	*/
461
462	/* The transfer Hz depend on the heuristics above, that is,
463	how often the guest expects to see a new data transfer. */
464	unsigned uTransferHz;
465
466	if (pThis->fTransferHeuristicsEnabled) /* Are data transfer heuristics enabled? */
467	{
468
469	/* Use the whole CBL as a starting point.
470	* This basically ASSUMES that we have one consequtive buffer with only one interrupt at the end. */
471	uint32_t cbTransferHeuristicsMin = pStreamShared->u32CBL;
472
473	/* Don't take frames (as bytes) into account which are part of the position adjustment. */
474	uint32_t cbTransferHeuristicsPosAdjust = pStreamShared->State.cfPosAdjustDefault * pStreamR3->State.Mapping.cbFrameSize;
475
476	HDABDLEDESC bd;
477	uint32_t cbTransferHeuristicsCur = 0;
478	for (uint8_t i = 0; i < cTransferFragments; i++)
479	{
480	PDMDevHlpPhysRead(pDevIns, u64BDLBase + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
481
482	/* Position adjustment (still) needed / active? */
483	if (cbTransferHeuristicsPosAdjust)
484	{
485	const uint32_t cbTransferHeuristicsPosAdjustMin = RT_MIN(cbTransferHeuristicsPosAdjust, bd.u32BufSize);
486
487	bd.u32BufSize -= cbTransferHeuristicsPosAdjustMin;
488	cbTransferHeuristicsPosAdjust -= cbTransferHeuristicsPosAdjustMin;
489	}
490
491	/* Anything left to process for the current BDLE after doing the position adjustment? */
492	if (bd.u32BufSize == 0)
493	continue;
494
495	/* Is an interrupt expected for the current BDLE? */
496	if (bd.fFlags & HDA_BDLE_F_IOC)
497	{
498	cbTransferHeuristicsCur += bd.u32BufSize;
499	cbTransferHeuristicsMin = RT_MIN(cbTransferHeuristicsCur, cbTransferHeuristicsMin);
500	cbTransferHeuristicsCur = 0;
501	}
502	else /* No interrupt expected -> add it to the former BDLE size. */
503	cbTransferHeuristicsCur += bd.u32BufSize;
504	}
505
506	/* !!! HACK ALERT BEGIN !!! */
507
508	/* Windows 10's audio driver expects a transfer all ~10.1ms (~1764 bytes), although
509	* it sets up 1792 bytes per BDLE.
510	*
511	* I currently don't have any clue why it does this that way, so try to simply detect this
512	* and alter the value so that we get a somewhat proper audio output. */
513	if (cbTransferHeuristicsMin == 1792)
514	{
515	LogRel2(("HDA: Guest seems to be Windows 10 -- setting a fixed transfer minimum size\n"));
516	cbTransferHeuristicsMin = 1764;
517	}
518
519	/* !!! HACK ALERT END !!! */
520
521	uint32_t msTransferHeuristicsMin = DrvAudioHlpBytesToMilli(cbTransferHeuristicsMin, &pCfg->Props);
522
523	/* Prevent division by zero. */
524	ASSERT_GUEST_LOGREL_MSG_STMT(msTransferHeuristicsMin,
525	("Transfer heuristics for stream #%RU8 buggy\n", uSD),
526	msTransferHeuristicsMin = 10 /* ms, equals 100 Hz */);
527
528	uTransferHz = RT_MS_1SEC / msTransferHeuristicsMin;
529
530	LogRel2(("HDA: Stream #%RU8 needs a data transfer at least every %RU64ms (%RU32 bytes) -- transfers run at %u Hz\n",
531	uSD, msTransferHeuristicsMin, cbTransferHeuristicsMin, uTransferHz));
532	}
533	else
534	{
535	/* Use I/O timing rate instead. */
536	uTransferHz = pStreamShared->State.uTimerIoHz;
537	}
538
539	if (uTransferHz > 400) /* Anything above 400 Hz looks fishy -- tell the user. */
540	LogRel(("HDA: Calculated transfer Hz rate for stream #%RU8 looks incorrect (%u), please re-run with audio debug mode and report a bug\n",
541	uSD, uTransferHz));
542
543	pStreamShared->State.cbTransferSize =
544	(pStreamShared->State.Cfg.Props.uHz * pStreamR3->State.Mapping.cbFrameSize) / uTransferHz;
545	ASSERT_GUEST_LOGREL_MSG_STMT(pStreamShared->State.cbTransferSize,
546	("Transfer size for stream #%RU8 is invalid\n", uSD), rc = VERR_INVALID_PARAMETER);
547	if (RT_SUCCESS(rc))
548	{
549	/*
550	* Calculate the bytes we need to transfer to / from the stream's DMA per iteration.
551	* This is bound to the device's Hz rate and thus to the (virtual) timing the device expects.
552	*
553	* As we don't do chunked transfers the moment, the chunk size equals the overall transfer size.
554	*/
555	pStreamShared->State.cbTransferChunk = pStreamShared->State.cbTransferSize;
556	ASSERT_GUEST_LOGREL_MSG_STMT(pStreamShared->State.cbTransferChunk,
557	("Transfer chunk for stream #%RU8 is invalid\n", uSD),
558	rc = VERR_INVALID_PARAMETER);
559	if (RT_SUCCESS(rc))
560	{
561	/* Make sure that the transfer chunk does not exceed the overall transfer size. */
562	AssertStmt(pStreamShared->State.cbTransferChunk <= pStreamShared->State.cbTransferSize,
563	pStreamShared->State.cbTransferChunk = pStreamShared->State.cbTransferSize);
564
565	const uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer);
566
567	const double cTicksPerHz = uTimerFreq / pStreamShared->State.uTimerIoHz;
568	double cTicksPerByte = cTicksPerHz / (double)pStreamShared->State.cbTransferChunk;
569
570	if (pStreamShared->State.uTimerIoHz < uTransferHz)
571	cTicksPerByte /= uTransferHz / pStreamShared->State.uTimerIoHz;
572	else
573	cTicksPerByte *= pStreamShared->State.uTimerIoHz / uTransferHz;
574
575	Assert(cTicksPerByte);
576
577	#define HDA_ROUND_NEAREST(a_X) ((a_X) >= 0 ? (uint32_t)((a_X) + 0.5) : (uint32_t)((a_X) - 0.5)) /** @todo r=andy Do we have rounding in IPRT? */
578
579	/* Calculate the timer ticks per byte for this stream. */
580	pStreamShared->State.cTicksPerByte = HDA_ROUND_NEAREST(cTicksPerByte);
581	Assert(pStreamShared->State.cTicksPerByte);
582
583	const double cTransferTicks = pStreamShared->State.cbTransferChunk * cTicksPerByte;
584
585	/* Calculate timer ticks per transfer. */
586	pStreamShared->State.cTransferTicks = HDA_ROUND_NEAREST(cTransferTicks);
587	Assert(pStreamShared->State.cTransferTicks);
588
589	#undef HDA_ROUND_NEAREST
590
591	LogRel2(("HDA: Stream #%RU8 is using %uHz I/O timer (%RU64 virtual ticks / Hz), stream Hz=%RU32, "
592	"cTicksPerByte=%RU64, cTransferTicks=%RU64 -> cbTransferChunk=%RU32 (%RU64ms), cbTransferSize=%RU32 (%RU64ms)\n",
593	uSD, pStreamShared->State.uTimerIoHz, (uint64_t)cTicksPerHz, pStreamShared->State.Cfg.Props.uHz,
594	pStreamShared->State.cTicksPerByte, pStreamShared->State.cTransferTicks,
595	pStreamShared->State.cbTransferChunk, DrvAudioHlpBytesToMilli(pStreamShared->State.cbTransferChunk, &pCfg->Props),
596	pStreamShared->State.cbTransferSize, DrvAudioHlpBytesToMilli(pStreamShared->State.cbTransferSize, &pCfg->Props)));
597
598	/* Make sure to also update the stream's DMA counter (based on its current LPIB value). */
599	hdaR3StreamSetPositionAbs(pStreamShared, pDevIns, pThis, HDA_STREAM_REG(pThis, LPIB, uSD));
600
601	#ifdef LOG_ENABLED
602	hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
603	#endif
604	}
605	}
606
607	/*
608	* Set up internal ring buffer.
609	*/
610	if (RT_SUCCESS(rc))
611	{
612	/* (Re-)Allocate the stream's internal DMA buffer,
613	* based on the timing and PCM properties we just got above. */
614	if (pStreamR3->State.pCircBuf)
615	{
616	RTCircBufDestroy(pStreamR3->State.pCircBuf);
617	pStreamR3->State.pCircBuf = NULL;
618	}
619
620	/*
621	* The default size of our internal ring buffer depends on the transfer timing
622	* we have to reach in order to make the guest driver happy and on the I/O timing.
623	*
624	* We always use triple the minimum timing of both timings for safety (triple buffering),
625	* otherwise we risk running into buffer overflows.
626	*/
627	const unsigned uTransferHzMin = RT_MIN(uTransferHz, pStreamShared->State.uTimerIoHz);
628
629	uint32_t cbCircBuf;
630	const uint32_t cbCircBufDefault = DrvAudioHlpMilliToBytes((RT_MS_1SEC / uTransferHzMin) * 3, &pCfg->Props);
631
632	LogRel2(("HDA: Stream #%RU8 default ring buffer size is %RU64ms (%RU32 bytes)\n",
633	uSD, DrvAudioHlpBytesToMilli(cbCircBufDefault, &pCfg->Props), cbCircBufDefault));
634
635	uint32_t cbCircBufGlobal = DrvAudioHlpMilliToBytes( hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN
636	? pThis->cbCircBufInMs : pThis->cbCircBufOutMs, &pCfg->Props);
637	if (cbCircBufGlobal) /* Anything set via CFGM? */
638	{
639
640	ASSERT_GUEST_LOGREL_MSG_STMT(DrvAudioHlpBytesIsAligned(cbCircBufGlobal, &pCfg->Props),
641	("Ring buffer size for stream #%RU8 is misaligned (%zu), setting to default\n", uSD, cbCircBufGlobal),
642	cbCircBufGlobal = cbCircBufDefault);
643
644	LogRel2(("HDA: Stream #%RU8 is using a custom ring buffer size of %RU64ms (%RU32 bytes)\n",
645	uSD, DrvAudioHlpBytesToMilli(cbCircBufGlobal, &pCfg->Props), cbCircBufGlobal));
646
647	cbCircBuf = cbCircBufGlobal;
648	}
649	else
650	cbCircBuf = cbCircBufDefault;
651
652	ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf,
653	("Ring buffer size for stream #%RU8 is invalid\n", uSD),
654	rc = VERR_INVALID_PARAMETER);
655	if (RT_SUCCESS(rc))
656	rc = RTCircBufCreate(&pStreamR3->State.pCircBuf, cbCircBuf);
657	}
658
659	if (RT_FAILURE(rc))
660	LogRel(("HDA: Initializing stream #%RU8 failed with %Rrc\n", uSD, rc));
661
662	return rc;
663	}
664
665	/**
666	* Resets an HDA stream.
667	*
668	* @param pThis The shared HDA device state.
669	* @param pThisCC The ring-3 HDA device state.
670	* @param pStreamShared HDA stream to reset (shared).
671	* @param pStreamR3 HDA stream to reset (ring-3).
672	* @param uSD Stream descriptor (SD) number to use for this stream.
673	*/
674	void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
675	{
676	AssertPtr(pThis);
677	AssertPtr(pStreamShared);
678	AssertPtr(pStreamR3);
679	Assert(uSD < HDA_MAX_STREAMS);
680	AssertMsg(!pStreamShared->State.fRunning, ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
681
682	LogFunc(("[SD%RU8] Reset\n", uSD));
683
684	/*
685	* Set reset state.
686	*/
687	Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false); /* No nested calls. */
688	ASMAtomicXchgBool(&pStreamShared->State.fInReset, true);
689
690	/*
691	* Second, initialize the registers.
692	*/
693	HDA_STREAM_REG(pThis, STS, uSD) = HDA_SDSTS_FIFORDY;
694	/* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
695	* bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
696	HDA_STREAM_REG(pThis, CTL, uSD) = 0x40000 \| (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_SRST);
697	/* ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39. */
698	HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
699	/* See 18.2.38: Always defaults to 0x4 (32 bytes). */
700	HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
701	HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
702	HDA_STREAM_REG(pThis, CBL, uSD) = 0;
703	HDA_STREAM_REG(pThis, LVI, uSD) = 0;
704	HDA_STREAM_REG(pThis, FMT, uSD) = 0;
705	HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
706	HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
707
708	#ifdef HDA_USE_DMA_ACCESS_HANDLER
709	hdaR3StreamUnregisterDMAHandlers(pThis, pStream);
710	#endif
711
712	/* Assign the default mixer sink to the stream. */
713	pStreamR3->pMixSink = hdaR3GetDefaultSink(pThisCC, uSD);
714
715	/* Reset position adjustment counter. */
716	pStreamShared->State.cfPosAdjustLeft = pStreamShared->State.cfPosAdjustDefault;
717
718	/* Reset transfer stuff. */
719	pStreamShared->State.cTransferPendingInterrupts = 0;
720	pStreamShared->State.tsTransferLast = 0;
721	pStreamShared->State.tsTransferNext = 0;
722
723	/* Initialize timestamps. */
724	pStreamShared->State.tsLastTransferNs = 0;
725	pStreamShared->State.tsLastReadNs = 0;
726
727	RT_ZERO(pStreamShared->State.BDLE);
728	pStreamShared->State.uCurBDLE = 0;
729
730	if (pStreamR3->State.pCircBuf)
731	RTCircBufReset(pStreamR3->State.pCircBuf);
732
733	/* Reset the stream's period. */
734	hdaR3StreamPeriodReset(&pStreamShared->State.Period);
735
736	#ifdef DEBUG
737	pStreamR3->Dbg.cReadsTotal = 0;
738	pStreamR3->Dbg.cbReadTotal = 0;
739	pStreamR3->Dbg.tsLastReadNs = 0;
740	pStreamR3->Dbg.cWritesTotal = 0;
741	pStreamR3->Dbg.cbWrittenTotal = 0;
742	pStreamR3->Dbg.cWritesHz = 0;
743	pStreamR3->Dbg.cbWrittenHz = 0;
744	pStreamR3->Dbg.tsWriteSlotBegin = 0;
745	#endif
746
747	/* Report that we're done resetting this stream. */
748	HDA_STREAM_REG(pThis, CTL, uSD) = 0;
749
750	LogFunc(("[SD%RU8] Reset\n", uSD));
751
752	/* Exit reset mode. */
753	ASMAtomicXchgBool(&pStreamShared->State.fInReset, false);
754	}
755
756	/**
757	* Enables or disables an HDA audio stream.
758	*
759	* @returns IPRT status code.
760	* @param pStreamShared HDA stream to enable or disable - shared bits.
761	* @param pStreamR3 HDA stream to enable or disable - ring-3 bits.
762	* @param fEnable Whether to enable or disble the stream.
763	*/
764	int hdaR3StreamEnable(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable)
765	{
766	AssertPtr(pStreamR3);
767	AssertPtr(pStreamShared);
768
769	LogFunc(("[SD%RU8] fEnable=%RTbool, pMixSink=%p\n", pStreamShared->u8SD, fEnable, pStreamR3->pMixSink));
770
771	int rc = VINF_SUCCESS;
772
773	AUDMIXSINKCMD enmCmd = fEnable
774	? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE;
775
776	/* First, enable or disable the stream and the stream's sink, if any. */
777	if ( pStreamR3->pMixSink
778	&& pStreamR3->pMixSink->pMixSink)
779	rc = AudioMixerSinkCtl(pStreamR3->pMixSink->pMixSink, enmCmd);
780
781	if ( RT_SUCCESS(rc)
782	&& fEnable
783	&& pStreamR3->Dbg.Runtime.fEnabled)
784	{
785	Assert(DrvAudioHlpPCMPropsAreValid(&pStreamShared->State.Cfg.Props));
786
787	if (fEnable)
788	{
789	if (!DrvAudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileStream))
790	{
791	int rc2 = DrvAudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileStream, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
792	&pStreamShared->State.Cfg.Props);
793	AssertRC(rc2);
794	}
795
796	if (!DrvAudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMARaw))
797	{
798	int rc2 = DrvAudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMARaw, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
799	&pStreamShared->State.Cfg.Props);
800	AssertRC(rc2);
801	}
802
803	if (!DrvAudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped))
804	{
805	int rc2 = DrvAudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
806	&pStreamShared->State.Cfg.Props);
807	AssertRC(rc2);
808	}
809	}
810	}
811
812	if (RT_SUCCESS(rc))
813	{
814	pStreamShared->State.fRunning = fEnable;
815	}
816
817	LogFunc(("[SD%RU8] rc=%Rrc\n", pStreamShared->u8SD, rc));
818	return rc;
819	}
820
821	#if 0 /* Not used atm. */
822	static uint32_t hdaR3StreamGetPosition(PHDASTATE pThis, PHDASTREAM pStreamShared)
823	{
824	return HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD);
825	}
826	#endif
827
828	/**
829	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
830	* setting its associated LPIB register and DMA position buffer (if enabled) to an absolute value.
831	*
832	* @param pStreamShared HDA stream to update read / write position for (shared).
833	* @param pDevIns The device instance.
834	* @param pThis The shared HDA device state.
835	* @param uLPIB Absolute position (in bytes) to set current read / write position to.
836	*/
837	static void hdaR3StreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB)
838	{
839	AssertPtrReturnVoid(pStreamShared);
840	AssertReturnVoid (uLPIB <= pStreamShared->u32CBL); /* Make sure that we don't go out-of-bounds. */
841
842	Log3Func(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n", pStreamShared->u8SD, uLPIB, pThis->fDMAPosition));
843
844	/* Update LPIB in any case. */
845	HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = uLPIB;
846
847	/* Do we need to tell the current DMA position? */
848	if (pThis->fDMAPosition)
849	{
850	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
851	pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
852	(void *)&uLPIB, sizeof(uint32_t));
853	AssertRC(rc2);
854	}
855	}
856
857	/**
858	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
859	* adding a value to its associated LPIB register and DMA position buffer (if enabled).
860	*
861	* @note Handles automatic CBL wrap-around.
862	*
863	* @param pStreamShared HDA stream to update read / write position for (shared).
864	* @param pDevIns The device instance.
865	* @param pThis The shared HDA device state.
866	* @param uToAdd Position (in bytes) to add to the current read / write position.
867	*/
868	void hdaR3StreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uToAdd)
869	{
870	if (!uToAdd) /* No need to update anything if 0. */
871	return;
872
873	hdaR3StreamSetPositionAbs(pStreamShared, pDevIns, pThis,
874	(HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) + uToAdd) % pStreamShared->u32CBL);
875	}
876
877	/**
878	* Retrieves the available size of (buffered) audio data (in bytes) of a given HDA stream.
879	*
880	* @returns Available data (in bytes).
881	* @param pStreamR3 HDA stream to retrieve size for (ring-3).
882	*/
883	static uint32_t hdaR3StreamGetUsed(PHDASTREAMR3 pStreamR3)
884	{
885	AssertPtrReturn(pStreamR3, 0);
886
887	if (pStreamR3->State.pCircBuf)
888	return (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
889	return 0;
890	}
891
892	/**
893	* Retrieves the free size of audio data (in bytes) of a given HDA stream.
894	*
895	* @returns Free data (in bytes).
896	* @param pStreamR3 HDA stream to retrieve size for (ring-3).
897	*/
898	static uint32_t hdaR3StreamGetFree(PHDASTREAMR3 pStreamR3)
899	{
900	AssertPtrReturn(pStreamR3, 0);
901
902	if (pStreamR3->State.pCircBuf)
903	return (uint32_t)RTCircBufFree(pStreamR3->State.pCircBuf);
904	return 0;
905	}
906
907	/**
908	* Returns whether a next transfer for a given stream is scheduled or not.
909	*
910	* This takes pending stream interrupts into account as well as the next scheduled
911	* transfer timestamp.
912	*
913	* @returns True if a next transfer is scheduled, false if not.
914	* @param pStreamShared HDA stream to retrieve schedule status for (shared).
915	* @param tsNow The current time.
916	*/
917	bool hdaR3StreamTransferIsScheduled(PHDASTREAM pStreamShared, uint64_t tsNow)
918	{
919	if (pStreamShared)
920	{
921	if (pStreamShared->State.fRunning)
922	{
923	if (pStreamShared->State.cTransferPendingInterrupts)
924	{
925	Log3Func(("[SD%RU8] Scheduled (%RU8 IRQs pending)\n", pStreamShared->u8SD, pStreamShared->State.cTransferPendingInterrupts));
926	return true;
927	}
928
929	if (pStreamShared->State.tsTransferNext > tsNow)
930	{
931	Log3Func(("[SD%RU8] Scheduled in %RU64\n", pStreamShared->u8SD, pStreamShared->State.tsTransferNext - tsNow));
932	return true;
933	}
934	}
935	}
936	return false;
937	}
938
939	/**
940	* Returns the (virtual) clock timestamp of the next transfer, if any.
941	* Will return 0 if no new transfer is scheduled.
942	*
943	* @returns The (virtual) clock timestamp of the next transfer.
944	* @param pStreamShared HDA stream to retrieve timestamp for (shared).
945	*/
946	uint64_t hdaR3StreamTransferGetNext(PHDASTREAM pStreamShared)
947	{
948	return pStreamShared->State.tsTransferNext;
949	}
950
951	/**
952	* Writes audio data from a mixer sink into an HDA stream's DMA buffer.
953	*
954	* @returns IPRT status code.
955	* @param pStreamR3 HDA stream to write to (ring-3).
956	* @param pvBuf Data buffer to write.
957	* If NULL, silence will be written.
958	* @param cbBuf Number of bytes of data buffer to write.
959	* @param pcbWritten Number of bytes written. Optional.
960	*/
961	static int hdaR3StreamWrite(PHDASTREAMR3 pStreamR3, const void pvBuf, uint32_t cbBuf, uint32_t pcbWritten)
962	{
963	Assert(cbBuf);
964
965	PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
966	AssertPtr(pCircBuf);
967
968	uint32_t cbWrittenTotal = 0;
969	uint32_t cbLeft = RT_MIN(cbBuf, (uint32_t)RTCircBufFree(pCircBuf));
970
971	while (cbLeft)
972	{
973	void *pvDst;
974	size_t cbDst;
975	RTCircBufAcquireWriteBlock(pCircBuf, cbLeft, &pvDst, &cbDst);
976
977	if (cbDst)
978	{
979	if (pvBuf)
980	memcpy(pvDst, (uint8_t *)pvBuf + cbWrittenTotal, cbDst);
981	else /* Send silence. */
982	{
983	/** @todo Use a sample spec for "silence" based on the PCM parameters.
984	* For now we ASSUME that silence equals NULLing the data. */
985	RT_BZERO(pvDst, cbDst);
986	}
987
988	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
989	{ /* likely */ }
990	else
991	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileStream, pvDst, cbDst, 0 /* fFlags */);
992	}
993
994	RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
995
996	Assert(cbLeft >= (uint32_t)cbDst);
997	cbLeft -= (uint32_t)cbDst;
998	cbWrittenTotal += (uint32_t)cbDst;
999	}
1000
1001	Log3Func(("cbWrittenTotal=%RU32\n", cbWrittenTotal));
1002
1003	if (pcbWritten)
1004	*pcbWritten = cbWrittenTotal;
1005
1006	return VINF_SUCCESS;
1007	}
1008
1009
1010	/**
1011	* Reads audio data from an HDA stream's DMA buffer and writes into a specified mixer sink.
1012	*
1013	* @returns IPRT status code.
1014	* @param pStreamR3 HDA stream to read audio data from (ring-3).
1015	* @param cbToRead Number of bytes to read.
1016	* @param pcbRead Number of bytes read. Optional.
1017	*/
1018	static int hdaR3StreamRead(PHDASTREAMR3 pStreamR3, uint32_t cbToRead, uint32_t *pcbRead)
1019	{
1020	Assert(cbToRead);
1021
1022	PHDAMIXERSINK pSink = pStreamR3->pMixSink;
1023	AssertMsgReturnStmt(pSink, ("[SD%RU8] Can't read from a stream with no sink attached\n", pStreamR3->u8SD),
1024	if (pcbRead) *pcbRead = 0,
1025	VINF_SUCCESS);
1026
1027	PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1028	AssertPtr(pCircBuf);
1029
1030	int rc = VINF_SUCCESS;
1031
1032	uint32_t cbReadTotal = 0;
1033	uint32_t cbLeft = RT_MIN(cbToRead, (uint32_t)RTCircBufUsed(pCircBuf));
1034
1035	while (cbLeft)
1036	{
1037	void *pvSrc;
1038	size_t cbSrc;
1039
1040	uint32_t cbWritten = 0;
1041
1042	RTCircBufAcquireReadBlock(pCircBuf, cbLeft, &pvSrc, &cbSrc);
1043
1044	if (cbSrc)
1045	{
1046	if (pStreamR3->Dbg.Runtime.fEnabled)
1047	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileStream, pvSrc, cbSrc, 0 /* fFlags */);
1048
1049	rc = AudioMixerSinkWrite(pSink->pMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbWritten);
1050	AssertRC(rc);
1051
1052	Assert(cbSrc >= cbWritten);
1053	Log2Func(("[SD%RU8] %RU32/%zu bytes read\n", pStreamR3->u8SD, cbWritten, cbSrc));
1054	}
1055
1056	RTCircBufReleaseReadBlock(pCircBuf, cbWritten);
1057
1058	if ( !cbWritten /* Nothing written? */
1059	\|\| RT_FAILURE(rc))
1060	break;
1061
1062	Assert(cbLeft >= cbWritten);
1063	cbLeft -= cbWritten;
1064
1065	cbReadTotal += cbWritten;
1066	}
1067
1068	if (pcbRead)
1069	*pcbRead = cbReadTotal;
1070
1071	return rc;
1072	}
1073
1074	/**
1075	* Transfers data of an HDA stream according to its usage (input / output).
1076	*
1077	* For an SDO (output) stream this means reading DMA data from the device to
1078	* the HDA stream's internal FIFO buffer.
1079	*
1080	* For an SDI (input) stream this is reading audio data from the HDA stream's
1081	* internal FIFO buffer and writing it as DMA data to the device.
1082	*
1083	* @returns IPRT status code.
1084	* @param pDevIns The device instance.
1085	* @param pThis The shared HDA device state.
1086	* @param pThisCC The ring-3 HDA device state.
1087	* @param pStreamShared HDA stream to update (shared).
1088	* @param pStreamR3 HDA stream to update (ring-3).
1089	* @param cbToProcessMax How much data (in bytes) to process as maximum.
1090	* @param fInTimer Set if we're in the timer callout.
1091	*/
1092	static int hdaR3StreamTransfer(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared,
1093	PHDASTREAMR3 pStreamR3, uint32_t cbToProcessMax, bool fInTimer)
1094	{
1095	LogFlowFuncEnter();
1096
1097	uint8_t const uSD = pStreamShared->u8SD;
1098	hdaR3StreamLock(pStreamR3);
1099
1100	PHDASTREAMPERIOD pPeriod = &pStreamShared->State.Period;
1101	hdaR3StreamPeriodLock(pPeriod);
1102
1103	bool fProceed = true;
1104
1105	/* Stream not running (anymore)? */
1106	if (!pStreamShared->State.fRunning)
1107	{
1108	Log3Func(("[SD%RU8] Not running, skipping transfer\n", uSD));
1109	fProceed = false;
1110	}
1111
1112	else if (HDA_STREAM_REG(pThis, STS, uSD) & HDA_SDSTS_BCIS)
1113	{
1114	Log3Func(("[SD%RU8] BCIS bit set, skipping transfer\n", uSD));
1115	#ifdef HDA_STRICT
1116	/* Timing emulation bug or guest is misbehaving -- let me know. */
1117	AssertMsgFailed(("BCIS bit for stream #%RU8 still set when it shouldn't\n", uSD));
1118	#endif
1119	fProceed = false;
1120	}
1121
1122	if (!fProceed)
1123	{
1124	hdaR3StreamPeriodUnlock(pPeriod);
1125	hdaR3StreamUnlock(pStreamR3);
1126	return VINF_SUCCESS;
1127	}
1128
1129	/* Update real-time timestamp. */
1130	const uint64_t tsNowNs = RTTimeNanoTS();
1131	#ifdef LOG_ENABLED
1132	const uint64_t tsDeltaMs = (tsNowNs - pStreamShared->State.tsLastTransferNs) / RT_NS_1MS;
1133	Log3Func(("[SD%RU8] tsDeltaNs=%RU64ms\n", uSD, tsDeltaMs));
1134	#endif
1135	pStreamShared->State.tsLastTransferNs = tsNowNs;
1136
1137	const uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1138
1139	if (!pStreamShared->State.tsTransferLast)
1140	pStreamShared->State.tsTransferLast = tsNow;
1141
1142	pStreamShared->State.tsTransferLast = tsNow;
1143
1144	/* Register sanity checks. */
1145	Assert(uSD < HDA_MAX_STREAMS);
1146	Assert(pStreamShared->u64BDLBase);
1147	Assert(pStreamShared->u32CBL);
1148	Assert(pStreamShared->u8FIFOS);
1149
1150	/* State sanity checks. */
1151	Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false);
1152	Assert(ASMAtomicReadBool(&pStreamShared->State.fRunning));
1153
1154	/* Transfer sanity checks. */
1155	Assert(pStreamShared->State.cbTransferSize);
1156	Assert(pStreamShared->State.cbTransferChunk <= pStreamShared->State.cbTransferSize);
1157
1158	int rc = VINF_SUCCESS;
1159
1160	/* Fetch first / next BDL entry. */
1161	PHDABDLE pBDLE = &pStreamShared->State.BDLE;
1162	if (hdaR3BDLEIsComplete(pBDLE))
1163	{
1164	rc = hdaR3BDLEFetch(pDevIns, pBDLE, pStreamShared->u64BDLBase, pStreamShared->State.uCurBDLE);
1165	AssertRC(rc);
1166	}
1167
1168	uint32_t cbToProcess = RT_MIN(pStreamShared->State.cbTransferSize, pStreamShared->State.cbTransferChunk);
1169
1170	Assert(cbToProcess); /* Nothing to process when there should be data. Accounting bug? */
1171
1172	/* More data to process than maximum allowed? */
1173	#ifdef HDA_STRICT
1174	AssertStmt(cbToProcess <= cbToProcessMax, cbToProcess = cbToProcessMax);
1175	#else
1176	if (cbToProcess > cbToProcessMax)
1177	cbToProcess = cbToProcessMax;
1178	#endif
1179
1180	uint32_t cbProcessed = 0;
1181	uint32_t cbLeft = cbToProcess;
1182
1183	/* Whether an interrupt has been sent (asserted) for this transfer period already or not.
1184	*
1185	* Note: Windows 10 relies on this, e.g. sending more than one interrupt per transfer period
1186	* confuses the Windows' audio driver and will screw up the audio data. So only send
1187	* one interrupt per transfer period.
1188	*/
1189	bool fInterruptSent = false;
1190
1191	while (cbLeft)
1192	{
1193	/* Limit the chunk to the stream's FIFO size and what's left to process. */
1194	uint32_t cbChunk = RT_MIN(cbLeft, pStreamShared->u8FIFOS);
1195
1196	/* Limit the chunk to the remaining data of the current BDLE. */
1197	cbChunk = RT_MIN(cbChunk, pBDLE->Desc.u32BufSize - pBDLE->State.u32BufOff);
1198
1199	/* If there are position adjustment frames left to be processed,
1200	* make sure that we process them first as a whole. */
1201	if (pStreamShared->State.cfPosAdjustLeft)
1202	cbChunk = RT_MIN(cbChunk, uint32_t(pStreamShared->State.cfPosAdjustLeft * pStreamR3->State.Mapping.cbFrameSize));
1203
1204	if (!cbChunk)
1205	break;
1206
1207	uint32_t cbDMA = 0;
1208	PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1209	uint8_t *pabFIFO = pStreamShared->abFIFO;
1210
1211	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN) /* Input (SDI). */
1212	{
1213	STAM_PROFILE_START(&pThis->StatIn, a);
1214
1215	uint32_t cbDMAWritten = 0;
1216	uint32_t cbDMAToWrite = cbChunk;
1217
1218	/** @todo Do we need interleaving streams support here as well?
1219	* Never saw anything else besides mono/stereo mics (yet). */
1220	while (cbDMAToWrite)
1221	{
1222	void *pvBuf; size_t cbBuf;
1223	RTCircBufAcquireReadBlock(pCircBuf, cbDMAToWrite, &pvBuf, &cbBuf);
1224
1225	if ( !cbBuf
1226	&& !RTCircBufUsed(pCircBuf))
1227	break;
1228
1229	memcpy(pabFIFO + cbDMAWritten, pvBuf, cbBuf);
1230
1231	RTCircBufReleaseReadBlock(pCircBuf, cbBuf);
1232
1233	Assert(cbDMAToWrite >= cbBuf);
1234	cbDMAToWrite -= (uint32_t)cbBuf;
1235	cbDMAWritten += (uint32_t)cbBuf;
1236	Assert(cbDMAWritten <= cbChunk);
1237	}
1238
1239	if (cbDMAToWrite)
1240	{
1241	LogRel2(("HDA: FIFO underflow for stream #%RU8 (%RU32 bytes outstanding)\n", uSD, cbDMAToWrite));
1242
1243	Assert(cbChunk == cbDMAWritten + cbDMAToWrite);
1244	memset((uint8_t *)pabFIFO + cbDMAWritten, 0, cbDMAToWrite);
1245	cbDMAWritten = cbChunk;
1246	}
1247
1248	rc = hdaR3DMAWrite(pDevIns, pThis, pStreamShared, pStreamR3, pabFIFO, cbDMAWritten, &cbDMA /* pcbWritten */);
1249	if (RT_FAILURE(rc))
1250	LogRel(("HDA: Writing to stream #%RU8 DMA failed with %Rrc\n", uSD, rc));
1251
1252	STAM_PROFILE_STOP(&pThis->StatIn, a);
1253	}
1254	else if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT) /* Output (SDO). */
1255	{
1256	STAM_PROFILE_START(&pThis->StatOut, a);
1257
1258	rc = hdaR3DMARead(pDevIns, pThis, pStreamShared, pStreamR3, pabFIFO, cbChunk, &cbDMA /* pcbRead */);
1259	if (RT_SUCCESS(rc))
1260	{
1261	const uint32_t cbFree = (uint32_t)RTCircBufFree(pCircBuf);
1262
1263	/*
1264	* Most guests don't use different stream frame sizes than
1265	* the default one, so save a bit of CPU time and don't go into
1266	* the frame extraction code below.
1267	*
1268	* Only macOS guests need the frame extraction branch below at the moment AFAIK.
1269	*/
1270	if (pStreamR3->State.Mapping.cbFrameSize == HDA_FRAME_SIZE_DEFAULT)
1271	{
1272	uint32_t cbDMARead = 0;
1273	uint32_t cbDMALeft = RT_MIN(cbDMA, cbFree);
1274
1275	while (cbDMALeft)
1276	{
1277	void *pvBuf; size_t cbBuf;
1278	RTCircBufAcquireWriteBlock(pCircBuf, cbDMALeft, &pvBuf, &cbBuf);
1279
1280	if (cbBuf)
1281	{
1282	memcpy(pvBuf, pabFIFO + cbDMARead, cbBuf);
1283	cbDMARead += (uint32_t)cbBuf;
1284	cbDMALeft -= (uint32_t)cbBuf;
1285	}
1286
1287	RTCircBufReleaseWriteBlock(pCircBuf, cbBuf);
1288	}
1289	}
1290	else
1291	{
1292	/*
1293	* The following code extracts the required audio stream (channel) data
1294	* of non-interleaved and interleaved audio streams.
1295	*
1296	* We by default only support 2 channels with 16-bit samples (HDA_FRAME_SIZE),
1297	* but an HDA audio stream can have interleaved audio data of multiple audio
1298	* channels in such a single stream ("AA,AA,AA vs. AA,BB,AA,BB").
1299	*
1300	* So take this into account by just handling the first channel in such a stream ("A")
1301	* and just discard the other channel's data.
1302	*
1303	* I know, the following code is horribly slow, but seems to work for now.
1304	*/
1305	/** @todo Optimize channel data extraction! Use some SSE(3) / intrinsics? */
1306	for (unsigned m = 0; m < pStreamR3->State.Mapping.cMappings; m++)
1307	{
1308	const uint32_t cbFrame = pStreamR3->State.Mapping.cbFrameSize;
1309
1310	Assert(cbFree >= cbDMA);
1311
1312	PPDMAUDIOSTREAMMAP pMap = &pStreamR3->State.Mapping.paMappings[m];
1313	AssertPtr(pMap);
1314
1315	Log3Func(("Mapping #%u: Start (cbDMA=%RU32, cbFrame=%RU32, offNext=%RU32)\n",
1316	m, cbDMA, cbFrame, pMap->offNext));
1317
1318
1319	/* Skip the current DMA chunk if the chunk is smaller than what the current stream mapping needs to read
1320	* the next associated frame (pointed to at pMap->cbOff).
1321	*
1322	* This can happen if the guest did not come up with enough data within a certain time period, especially
1323	* when using multi-channel speaker (> 2 channels [stereo]) setups. */
1324	if (pMap->offNext > cbChunk)
1325	{
1326	Log2Func(("Mapping #%u: Skipped (cbChunk=%RU32, cbMapOff=%RU32)\n", m, cbChunk, pMap->offNext));
1327	continue;
1328	}
1329
1330	uint8_t *pbSrcBuf = pabFIFO;
1331	size_t cbSrcOff = pMap->offNext;
1332
1333	for (unsigned i = 0; i < cbDMA / cbFrame; i++)
1334	{
1335	void *pvDstBuf; size_t cbDstBuf;
1336	RTCircBufAcquireWriteBlock(pCircBuf, pMap->cbStep, &pvDstBuf, &cbDstBuf);
1337
1338	Assert(cbDstBuf >= pMap->cbStep);
1339
1340	if (cbDstBuf)
1341	{
1342	Log3Func(("Mapping #%u: Frame #%02u: cbStep=%u, offFirst=%u, offNext=%u, cbDstBuf=%u, cbSrcOff=%u\n",
1343	m, i, pMap->cbStep, pMap->offFirst, pMap->offNext, cbDstBuf, cbSrcOff));
1344
1345	memcpy(pvDstBuf, pbSrcBuf + cbSrcOff, cbDstBuf);
1346
1347	#if 0 /* Too slow, even for release builds, so disabled it. */
1348	if (pStreamR3->Dbg.Runtime.fEnabled)
1349	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMAMapped, pvDstBuf, cbDstBuf,
1350	0 /* fFlags */);
1351	#endif
1352	Assert(cbSrcOff <= cbDMA);
1353	if (cbSrcOff + cbFrame + pMap->offFirst<= cbDMA)
1354	cbSrcOff += cbFrame + pMap->offFirst;
1355
1356	Log3Func(("Mapping #%u: Frame #%02u: -> cbSrcOff=%zu\n", m, i, cbSrcOff));
1357	}
1358
1359	RTCircBufReleaseWriteBlock(pCircBuf, cbDstBuf);
1360	}
1361
1362	Log3Func(("Mapping #%u: End cbSize=%u, cbDMA=%RU32, cbSrcOff=%zu\n",
1363	m, pMap->cbStep, cbDMA, cbSrcOff));
1364
1365	Assert(cbSrcOff <= cbDMA);
1366
1367	const uint32_t cbSrcLeft = cbDMA - (uint32_t)cbSrcOff;
1368	if (cbSrcLeft)
1369	{
1370	Log3Func(("Mapping #%u: cbSrcLeft=%RU32\n", m, cbSrcLeft));
1371
1372	if (cbSrcLeft >= pMap->cbStep)
1373	{
1374	void *pvDstBuf; size_t cbDstBuf;
1375	RTCircBufAcquireWriteBlock(pCircBuf, pMap->cbStep, &pvDstBuf, &cbDstBuf);
1376
1377	Assert(cbDstBuf >= pMap->cbStep);
1378
1379	if (cbDstBuf)
1380	{
1381	memcpy(pvDstBuf, pbSrcBuf + cbSrcOff, cbDstBuf);
1382	}
1383
1384	RTCircBufReleaseWriteBlock(pCircBuf, cbDstBuf);
1385	}
1386
1387	Assert(pMap->cbFrame >= cbSrcLeft);
1388	pMap->offNext = pMap->cbFrame - cbSrcLeft;
1389	}
1390	else
1391	pMap->offNext = 0;
1392
1393	Log3Func(("Mapping #%u finish (cbSrcOff=%zu, offNext=%zu)\n", m, cbSrcOff, pMap->offNext));
1394	}
1395	}
1396	}
1397	else
1398	LogRel(("HDA: Reading from stream #%RU8 DMA failed with %Rrc\n", uSD, rc));
1399
1400	STAM_PROFILE_STOP(&pThis->StatOut, a);
1401	}
1402
1403	else /** @todo Handle duplex streams? */
1404	AssertFailed();
1405
1406	if (cbDMA)
1407	{
1408	/* We always increment the position of DMA buffer counter because we're always reading
1409	* into an intermediate DMA buffer. */
1410	pBDLE->State.u32BufOff += (uint32_t)cbDMA;
1411	Assert(pBDLE->State.u32BufOff <= pBDLE->Desc.u32BufSize);
1412
1413	/* Are we done doing the position adjustment?
1414	* Only then do the transfer accounting .*/
1415	if (pStreamShared->State.cfPosAdjustLeft == 0)
1416	{
1417	Assert(cbLeft >= cbDMA);
1418	cbLeft -= cbDMA;
1419
1420	cbProcessed += cbDMA;
1421	}
1422
1423	Log3Func(("[SD%RU8] cbDMA=%RU32 -> %R[bdle]\n", uSD, cbDMA, pBDLE));
1424	}
1425
1426	if (hdaR3BDLEIsComplete(pBDLE))
1427	{
1428	Log3Func(("[SD%RU8] Completed %R[bdle]\n", uSD, pBDLE));
1429
1430	/* Make sure to also update the wall clock when a BDLE is complete.
1431	* Needed for Windows 10 guests. */
1432	hdaR3WalClkSet(pThis, pThisCC,
1433	hdaWalClkGetCurrent(pThis)
1434	+ hdaR3StreamPeriodFramesToWalClk(pPeriod,
1435	pBDLE->Desc.u32BufSize
1436	/ pStreamR3->State.Mapping.cbFrameSize),
1437	false /* fForce */);
1438
1439	/*
1440	* Update the stream's current position.
1441	* Do this as accurate and close to the actual data transfer as possible.
1442	* All guetsts rely on this, depending on the mechanism they use (LPIB register or DMA counters).
1443	*
1444	* Note for Windows 10: The OS' driver is very picky about when the (DMA) positions get updated!
1445	* Not doing this at the right time will result in ugly sound crackles!
1446	*/
1447	hdaR3StreamSetPositionAdd(pStreamShared, pDevIns, pThis, pBDLE->Desc.u32BufSize);
1448
1449	/* Does the current BDLE require an interrupt to be sent? */
1450	if ( hdaR3BDLENeedsInterrupt(pBDLE)
1451	/* Are we done doing the position adjustment?
1452	* It can happen that a BDLE which is handled while doing the
1453	* position adjustment requires an interrupt on completion (IOC) being set.
1454	*
1455	* In such a case we need to skip such an interrupt and just move on. */
1456	&& pStreamShared->State.cfPosAdjustLeft == 0)
1457	{
1458	/* If the IOCE ("Interrupt On Completion Enable") bit of the SDCTL register is set
1459	* we need to generate an interrupt.
1460	*/
1461	if (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_IOCE)
1462	{
1463	/* Assert the interrupt before actually fetching the next BDLE below. */
1464	if (!fInterruptSent)
1465	{
1466	pStreamShared->State.cTransferPendingInterrupts++;
1467
1468	AssertMsg(pStreamShared->State.cTransferPendingInterrupts <= 32,
1469	("Too many pending interrupts (%RU8) for stream #%RU8\n",
1470	pStreamShared->State.cTransferPendingInterrupts, uSD));
1471
1472	Log3Func(("[SD%RU8] Scheduling interrupt (now %RU8 total)\n", uSD, pStreamShared->State.cTransferPendingInterrupts));
1473
1474	/*
1475	* Set the stream's BCIS bit.
1476	*
1477	* Note: This only must be done if the whole period is complete, and not if only
1478	* one specific BDL entry is complete (if it has the IOC bit set).
1479	*
1480	* This will otherwise confuses the guest when it 1) deasserts the interrupt,
1481	* 2) reads SDSTS (with BCIS set) and then 3) too early reads a (wrong) WALCLK value.
1482	*
1483	* snd_hda_intel on Linux will tell.
1484	*/
1485	HDA_STREAM_REG(pThis, STS, uSD) \|= HDA_SDSTS_BCIS;
1486
1487	/* Trigger an interrupt first and let hdaRegWriteSDSTS() deal with
1488	* ending / beginning a period. */
1489	HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1490
1491	fInterruptSent = true;
1492	}
1493	}
1494	}
1495
1496	if (pStreamShared->State.uCurBDLE == pStreamShared->u16LVI)
1497	{
1498	pStreamShared->State.uCurBDLE = 0;
1499	}
1500	else
1501	pStreamShared->State.uCurBDLE++;
1502
1503	/* Fetch the next BDLE entry. */
1504	hdaR3BDLEFetch(pDevIns, pBDLE, pStreamShared->u64BDLBase, pStreamShared->State.uCurBDLE);
1505	}
1506
1507	/* Do the position adjustment accounting. */
1508	pStreamShared->State.cfPosAdjustLeft -=
1509	RT_MIN(pStreamShared->State.cfPosAdjustLeft, cbDMA / pStreamR3->State.Mapping.cbFrameSize);
1510
1511	if (RT_FAILURE(rc))
1512	break;
1513	}
1514
1515	/* Sanity. */
1516	Assert(cbProcessed == cbToProcess);
1517	Assert(cbLeft == 0);
1518
1519	/* Only do the data accounting if we don't have to do any position
1520	* adjustment anymore. */
1521	if (pStreamShared->State.cfPosAdjustLeft == 0)
1522	{
1523	hdaR3StreamPeriodInc(pPeriod, RT_MIN(cbProcessed / pStreamR3->State.Mapping.cbFrameSize,
1524	hdaR3StreamPeriodGetRemainingFrames(pPeriod)));
1525	}
1526
1527	const bool fTransferComplete = cbLeft == 0;
1528	uint64_t tsTransferNext = 0;
1529
1530	if (fTransferComplete)
1531	{
1532	/*
1533	* Try updating the wall clock.
1534	*
1535	* Note 1) Only certain guests (like Linux' snd_hda_intel) rely on the WALCLK register
1536	* in order to determine the correct timing of the sound device. Other guests
1537	* like Windows 7 + 10 (or even more exotic ones like Haiku) will completely
1538	* ignore this.
1539	*
1540	* Note 2) When updating the WALCLK register too often / early (or even in a non-monotonic
1541	* fashion) this will upset guest device drivers and will completely fuck up the
1542	* sound output. Running VLC on the guest will tell!
1543	*/
1544	const bool fWalClkSet = hdaR3WalClkSet(pThis, pThisCC,
1545	hdaWalClkGetCurrent(pThis)
1546	+ hdaR3StreamPeriodFramesToWalClk(pPeriod,
1547	cbProcessed
1548	/ pStreamR3->State.Mapping.cbFrameSize),
1549	false /* fForce */);
1550	RT_NOREF(fWalClkSet);
1551	}
1552
1553	/* Does the period have any interrupts outstanding? */
1554	if (!pStreamShared->State.cTransferPendingInterrupts)
1555	{
1556	/* No, set relative timer ticks for the next transfer to happen.
1557	* This must happen at a constant rate. */
1558	tsTransferNext = tsNow + pStreamShared->State.cTransferTicks;
1559	}
1560
1561	/* If we need to do another transfer, (re-)arm the device timer. */
1562	if (tsTransferNext) /* Can be 0 if no next transfer is needed. */
1563	{
1564	Log3Func(("[SD%RU8] Scheduling timer @ %RU64\n", uSD, tsTransferNext));
1565
1566	/* Make sure to assign next transfer timestamp before setting the timer. */
1567	pStreamShared->State.tsTransferNext = tsTransferNext;
1568
1569	Assert(!fInTimer \|\| tsNow == PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer));
1570	hdaR3TimerSet(pDevIns, pStreamShared, tsTransferNext,
1571	true /* fForce - skip tsTransferNext check */, fInTimer ? tsNow : 0);
1572	}
1573
1574	pStreamShared->State.tsTransferLast = tsNow;
1575
1576	Log3Func(("[SD%RU8] %R[bdle] -- %RU32/%RU32\n",
1577	uSD, pBDLE, cbProcessed, pStreamShared->State.cbTransferSize));
1578	Log3Func(("[SD%RU8] fTransferComplete=%RTbool, cTransferPendingInterrupts=%RU8\n",
1579	uSD, fTransferComplete, pStreamShared->State.cTransferPendingInterrupts));
1580	Log3Func(("[SD%RU8] tsNow=%RU64, tsTransferNext=%RU64 (in %RU64 ticks)\n",
1581	uSD, tsNow, tsTransferNext, tsTransferNext ? tsTransferNext - tsNow : 0));
1582
1583	LogFlowFuncLeave();
1584
1585	hdaR3StreamPeriodUnlock(pPeriod);
1586	hdaR3StreamUnlock(pStreamR3);
1587
1588	return VINF_SUCCESS;
1589	}
1590
1591	/**
1592	* Updates a HDA stream by doing its required data transfers.
1593	*
1594	* The host sink(s) set the overall pace.
1595	*
1596	* This routine is called by both, the synchronous and the asynchronous
1597	* (VBOX_WITH_AUDIO_HDA_ASYNC_IO), implementations.
1598	*
1599	* When running synchronously, the device DMA transfers and the mixer sink
1600	* processing is within the device timer.
1601	*
1602	* When running asynchronously, only the device DMA transfers are done in the
1603	* device timer, whereas the mixer sink processing then is done in the stream's
1604	* own async I/O thread. This thread also will call this function
1605	* (with fInTimer set to @c false).
1606	*
1607	* @param pDevIns The device instance.
1608	* @param pThis The shared HDA device state.
1609	* @param pThisCC The ring-3 HDA device state.
1610	* @param pStreamShared HDA stream to update (shared bits).
1611	* @param pStreamR3 HDA stream to update (ring-3 bits).
1612	* @param fInTimer Whether to this function was called from the timer
1613	* context or an asynchronous I/O stream thread (if supported).
1614	*/
1615	void hdaR3StreamUpdate(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
1616	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fInTimer)
1617	{
1618	if (!pStreamShared)
1619	return;
1620
1621	PAUDMIXSINK pSink = NULL;
1622	if (pStreamR3->pMixSink)
1623	pSink = pStreamR3->pMixSink->pMixSink;
1624
1625	if (!AudioMixerSinkIsActive(pSink)) /* No sink available? Bail out. */
1626	return;
1627
1628	const uint64_t tsNowNs = RTTimeNanoTS();
1629
1630	int rc2;
1631
1632	if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
1633	{
1634	bool fDoRead = false; /* Whether to read from the HDA stream or not. */
1635
1636	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1637	if (fInTimer)
1638	# endif
1639	{
1640	uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1641	if (!cbStreamFree)
1642	{
1643	LogRel2(("HDA: Warning: Hit stream #%RU8 overflow, dropping audio data\n", pStreamShared->u8SD));
1644	# ifdef HDA_STRICT
1645	AssertMsgFailed(("Hit stream #%RU8 overflow -- timing bug?\n", pStreamShared->u8SD));
1646	# endif
1647	/* When hitting an overflow, drop all remaining data to make space for current data.
1648	* This is needed in order to keep the device emulation running at a constant rate,
1649	* at the cost of losing valid (but too much) data. */
1650	RTCircBufReset(pStreamR3->State.pCircBuf);
1651	cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1652	}
1653
1654	/* Do the DMA transfer. */
1655	rc2 = hdaR3StreamTransfer(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3, cbStreamFree, fInTimer);
1656	AssertRC(rc2);
1657
1658	/* Never read yet? Set initial timestamp. */
1659	if (pStreamShared->State.tsLastReadNs == 0)
1660	pStreamShared->State.tsLastReadNs = tsNowNs;
1661
1662	/* Only read from the HDA stream at the given scheduling rate. */
1663	Assert(tsNowNs >= pStreamShared->State.tsLastReadNs);
1664	const uint64_t tsDeltaMs = (tsNowNs - pStreamShared->State.tsLastReadNs) / RT_NS_1MS;
1665	if (tsDeltaMs >= pStreamShared->State.Cfg.Device.cMsSchedulingHint)
1666	fDoRead = true;
1667
1668	Log3Func(("tsDeltaMs=%RU64, fDoRead=%RTbool\n", tsDeltaMs, fDoRead));
1669	}
1670
1671	if (fDoRead)
1672	{
1673	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1674	/* Notify the async I/O worker thread that there's work to do. */
1675	rc2 = hdaR3StreamAsyncIONotify(pStreamR3);
1676	AssertRC(rc2);
1677	# endif
1678	/* Update last read timestamp so that we know when to run next. */
1679	pStreamShared->State.tsLastReadNs = tsNowNs;
1680	}
1681
1682	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1683	if (!fInTimer) /* In async I/O thread */
1684	# else
1685	if (fDoRead)
1686	# endif
1687	{
1688	const uint32_t cbSinkWritable = AudioMixerSinkGetWritable(pSink);
1689	const uint32_t cbStreamReadable = hdaR3StreamGetUsed(pStreamR3);
1690	uint32_t cbToReadFromStream = RT_MIN(cbStreamReadable, cbSinkWritable);
1691	/* Make sure that we always align the number of bytes when reading to the stream's PCM properties. */
1692	cbToReadFromStream = DrvAudioHlpBytesAlign(cbToReadFromStream, &pStreamShared->State.Cfg.Props);
1693
1694	#ifdef LOG_ENABLED
1695	Assert(tsNowNs >= pStreamShared->State.tsLastReadNs);
1696	const uint64_t deltaLastReadMs = (tsNowNs - pStreamShared->State.tsLastReadNs) / RT_NS_1MS;
1697	Log3Func(("[SD%RU8] deltaLastReadMs=%RU64\n",
1698	pStreamShared->u8SD, deltaLastReadMs));
1699	#endif
1700	Log3Func(("[SD%RU8] cbSinkWritable=%RU32, cbStreamReadable=%RU32 -> cbToReadFromStream=%RU32\n",
1701	pStreamShared->u8SD, cbSinkWritable, cbStreamReadable, cbToReadFromStream));
1702
1703	if (cbToReadFromStream)
1704	{
1705	/* Read (guest output) data and write it to the stream's sink. */
1706	rc2 = hdaR3StreamRead(pStreamR3, cbToReadFromStream, NULL /* pcbRead */);
1707	AssertRC(rc2);
1708	}
1709
1710	/* When running synchronously, update the associated sink here.
1711	* Otherwise this will be done in the async I/O thread. */
1712	rc2 = AudioMixerSinkUpdate(pSink);
1713	AssertRC(rc2);
1714	}
1715	}
1716	else /* Input (SDI). */
1717	{
1718	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1719	if (!fInTimer)
1720	# endif
1721	{
1722	rc2 = AudioMixerSinkUpdate(pSink);
1723	AssertRC(rc2);
1724
1725	/* Is the sink ready to be read (host input data) from? If so, by how much? */
1726	uint32_t cbSinkReadable = AudioMixerSinkGetReadable(pSink);
1727
1728	/* How much (guest input) data is available for writing at the moment for the HDA stream? */
1729	const uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1730
1731	Log3Func(("[SD%RU8] cbSinkReadable=%RU32, cbStreamFree=%RU32\n", pStreamShared->u8SD, cbSinkReadable, cbStreamFree));
1732
1733	/* Do not read more than the HDA stream can hold at the moment.
1734	* The host sets the overall pace. */
1735	if (cbSinkReadable > cbStreamFree)
1736	cbSinkReadable = cbStreamFree;
1737
1738	if (cbSinkReadable)
1739	{
1740	uint8_t *pabFIFO = pStreamShared->abFIFO;
1741
1742	while (cbSinkReadable)
1743	{
1744	uint32_t cbRead;
1745	rc2 = AudioMixerSinkRead(pSink, AUDMIXOP_COPY,
1746	pabFIFO, RT_MIN(cbSinkReadable, (uint32_t)sizeof(pStreamShared->abFIFO)), &cbRead);
1747	AssertRCBreak(rc2);
1748
1749	if (!cbRead)
1750	{
1751	AssertMsgFailed(("Nothing read from sink, even if %RU32 bytes were (still) announced\n", cbSinkReadable));
1752	break;
1753	}
1754
1755	/* Write (guest input) data to the stream which was read from stream's sink before. */
1756	uint32_t cbWritten;
1757	rc2 = hdaR3StreamWrite(pStreamR3, pabFIFO, cbRead, &cbWritten);
1758	AssertRCBreak(rc2);
1759	AssertBreak(cbWritten > 0); /* Should never happen, as we know how much we can write. */
1760
1761	Assert(cbSinkReadable >= cbRead);
1762	cbSinkReadable -= cbRead;
1763	}
1764	}
1765	}
1766	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1767	else /* fInTimer */
1768	# endif
1769	{
1770	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1771	if (tsNowNs - pStreamShared->State.tsLastReadNs >= pStreamShared->State.Cfg.Device.cMsSchedulingHint * RT_NS_1MS)
1772	{
1773	rc2 = hdaR3StreamAsyncIONotify(pStreamR3);
1774	AssertRC(rc2);
1775
1776	pStreamShared->State.tsLastReadNs = tsNowNs;
1777	}
1778	# endif
1779	const uint32_t cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
1780	if (cbStreamUsed)
1781	{
1782	rc2 = hdaR3StreamTransfer(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3, cbStreamUsed, fInTimer);
1783	AssertRC(rc2);
1784	}
1785	}
1786	}
1787	}
1788
1789	/**
1790	* Locks an HDA stream for serialized access.
1791	*
1792	* @returns IPRT status code.
1793	* @param pStreamR3 HDA stream to lock (ring-3 bits).
1794	*/
1795	void hdaR3StreamLock(PHDASTREAMR3 pStreamR3)
1796	{
1797	AssertPtrReturnVoid(pStreamR3);
1798	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1799	int rc2 = RTCritSectEnter(&pStreamR3->CritSect);
1800	AssertRC(rc2);
1801	# else
1802	Assert(PDMDevHlpCritSectIsOwner(pStream->pHDAState->pDevInsR3, pStream->pHDAState->CritSect));
1803	# endif
1804	}
1805
1806	/**
1807	* Unlocks a formerly locked HDA stream.
1808	*
1809	* @returns IPRT status code.
1810	* @param pStreamR3 HDA stream to unlock (ring-3 bits).
1811	*/
1812	void hdaR3StreamUnlock(PHDASTREAMR3 pStreamR3)
1813	{
1814	AssertPtrReturnVoid(pStreamR3);
1815	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1816	int rc2 = RTCritSectLeave(&pStreamR3->CritSect);
1817	AssertRC(rc2);
1818	# endif
1819	}
1820
1821	#if 0 /* unused - no prototype even */
1822	/**
1823	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1824	* updating its associated LPIB register and DMA position buffer (if enabled).
1825	*
1826	* @returns Set LPIB value.
1827	* @param pDevIns The device instance.
1828	* @param pStream HDA stream to update read / write position for.
1829	* @param u32LPIB New LPIB (position) value to set.
1830	*/
1831	uint32_t hdaR3StreamUpdateLPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint32_t u32LPIB)
1832	{
1833	AssertMsg(u32LPIB <= pStreamShared->u32CBL,
1834	("[SD%RU8] New LPIB (%RU32) exceeds CBL (%RU32)\n", pStreamShared->u8SD, u32LPIB, pStreamShared->u32CBL));
1835
1836	u32LPIB = RT_MIN(u32LPIB, pStreamShared->u32CBL);
1837
1838	LogFlowFunc(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1839	pStreamShared->u8SD, u32LPIB, pThis->fDMAPosition));
1840
1841	/* Update LPIB in any case. */
1842	HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = u32LPIB;
1843
1844	/* Do we need to tell the current DMA position? */
1845	if (pThis->fDMAPosition)
1846	{
1847	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
1848	pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
1849	(void *)&u32LPIB, sizeof(uint32_t));
1850	AssertRC(rc2);
1851	}
1852
1853	return u32LPIB;
1854	}
1855	#endif
1856
1857	# ifdef HDA_USE_DMA_ACCESS_HANDLER
1858	/**
1859	* Registers access handlers for a stream's BDLE DMA accesses.
1860	*
1861	* @returns true if registration was successful, false if not.
1862	* @param pStream HDA stream to register BDLE access handlers for.
1863	*/
1864	bool hdaR3StreamRegisterDMAHandlers(PHDASTREAM pStream)
1865	{
1866	/* At least LVI and the BDL base must be set. */
1867	if ( !pStreamShared->u16LVI
1868	\|\| !pStreamShared->u64BDLBase)
1869	{
1870	return false;
1871	}
1872
1873	hdaR3StreamUnregisterDMAHandlers(pStream);
1874
1875	LogFunc(("Registering ...\n"));
1876
1877	int rc = VINF_SUCCESS;
1878
1879	/*
1880	* Create BDLE ranges.
1881	*/
1882
1883	struct BDLERANGE
1884	{
1885	RTGCPHYS uAddr;
1886	uint32_t uSize;
1887	} arrRanges[16]; /** @todo Use a define. */
1888
1889	size_t cRanges = 0;
1890
1891	for (uint16_t i = 0; i < pStreamShared->u16LVI + 1; i++)
1892	{
1893	HDABDLE BDLE;
1894	rc = hdaR3BDLEFetch(pDevIns, &BDLE, pStreamShared->u64BDLBase, i /* Index */);
1895	if (RT_FAILURE(rc))
1896	break;
1897
1898	bool fAddRange = true;
1899	BDLERANGE *pRange;
1900
1901	if (cRanges)
1902	{
1903	pRange = &arrRanges[cRanges - 1];
1904
1905	/* Is the current range a direct neighbor of the current BLDE? */
1906	if ((pRange->uAddr + pRange->uSize) == BDLE.Desc.u64BufAddr)
1907	{
1908	/* Expand the current range by the current BDLE's size. */
1909	pRange->uSize += BDLE.Desc.u32BufSize;
1910
1911	/* Adding a new range in this case is not needed anymore. */
1912	fAddRange = false;
1913
1914	LogFunc(("Expanding range %zu by %RU32 (%RU32 total now)\n", cRanges - 1, BDLE.Desc.u32BufSize, pRange->uSize));
1915	}
1916	}
1917
1918	/* Do we need to add a new range? */
1919	if ( fAddRange
1920	&& cRanges < RT_ELEMENTS(arrRanges))
1921	{
1922	pRange = &arrRanges[cRanges];
1923
1924	pRange->uAddr = BDLE.Desc.u64BufAddr;
1925	pRange->uSize = BDLE.Desc.u32BufSize;
1926
1927	LogFunc(("Adding range %zu - 0x%x (%RU32)\n", cRanges, pRange->uAddr, pRange->uSize));
1928
1929	cRanges++;
1930	}
1931	}
1932
1933	LogFunc(("%zu ranges total\n", cRanges));
1934
1935	/*
1936	* Register all ranges as DMA access handlers.
1937	*/
1938
1939	for (size_t i = 0; i < cRanges; i++)
1940	{
1941	BDLERANGE *pRange = &arrRanges[i];
1942
1943	PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)RTMemAllocZ(sizeof(HDADMAACCESSHANDLER));
1944	if (!pHandler)
1945	{
1946	rc = VERR_NO_MEMORY;
1947	break;
1948	}
1949
1950	RTListAppend(&pStream->State.lstDMAHandlers, &pHandler->Node);
1951
1952	pHandler->pStream = pStream; /* Save a back reference to the owner. */
1953
1954	char szDesc[32];
1955	RTStrPrintf(szDesc, sizeof(szDesc), "HDA[SD%RU8 - RANGE%02zu]", pStream->u8SD, i);
1956
1957	int rc2 = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
1958	hdaDMAAccessHandler,
1959	NULL, NULL, NULL,
1960	NULL, NULL, NULL,
1961	szDesc, &pHandler->hAccessHandlerType);
1962	AssertRCBreak(rc2);
1963
1964	pHandler->BDLEAddr = pRange->uAddr;
1965	pHandler->BDLESize = pRange->uSize;
1966
1967	/* Get first and last pages of the BDLE range. */
1968	RTGCPHYS pgFirst = pRange->uAddr & ~PAGE_OFFSET_MASK;
1969	RTGCPHYS pgLast = RT_ALIGN(pgFirst + pRange->uSize, PAGE_SIZE);
1970
1971	/* Calculate the region size (in pages). */
1972	RTGCPHYS regionSize = RT_ALIGN(pgLast - pgFirst, PAGE_SIZE);
1973
1974	pHandler->GCPhysFirst = pgFirst;
1975	pHandler->GCPhysLast = pHandler->GCPhysFirst + (regionSize - 1);
1976
1977	LogFunc(("\tRegistering region '%s': 0x%x - 0x%x (region size: %zu)\n",
1978	szDesc, pHandler->GCPhysFirst, pHandler->GCPhysLast, regionSize));
1979	LogFunc(("\tBDLE @ 0x%x - 0x%x (%RU32)\n",
1980	pHandler->BDLEAddr, pHandler->BDLEAddr + pHandler->BDLESize, pHandler->BDLESize));
1981
1982	rc2 = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
1983	pHandler->GCPhysFirst, pHandler->GCPhysLast,
1984	pHandler->hAccessHandlerType, pHandler, NIL_RTR0PTR, NIL_RTRCPTR,
1985	szDesc);
1986	AssertRCBreak(rc2);
1987
1988	pHandler->fRegistered = true;
1989	}
1990
1991	LogFunc(("Registration ended with rc=%Rrc\n", rc));
1992
1993	return RT_SUCCESS(rc);
1994	}
1995
1996	/**
1997	* Unregisters access handlers of a stream's BDLEs.
1998	*
1999	* @param pStream HDA stream to unregister BDLE access handlers for.
2000	*/
2001	void hdaR3StreamUnregisterDMAHandlers(PHDASTREAM pStream)
2002	{
2003	LogFunc(("\n"));
2004
2005	PHDADMAACCESSHANDLER pHandler, pHandlerNext;
2006	RTListForEachSafe(&pStream->State.lstDMAHandlers, pHandler, pHandlerNext, HDADMAACCESSHANDLER, Node)
2007	{
2008	if (!pHandler->fRegistered) /* Handler not registered? Skip. */
2009	continue;
2010
2011	LogFunc(("Unregistering 0x%x - 0x%x (%zu)\n",
2012	pHandler->GCPhysFirst, pHandler->GCPhysLast, pHandler->GCPhysLast - pHandler->GCPhysFirst));
2013
2014	int rc2 = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2015	pHandler->GCPhysFirst);
2016	AssertRC(rc2);
2017
2018	RTListNodeRemove(&pHandler->Node);
2019
2020	RTMemFree(pHandler);
2021	pHandler = NULL;
2022	}
2023
2024	Assert(RTListIsEmpty(&pStream->State.lstDMAHandlers));
2025	}
2026	# endif /* HDA_USE_DMA_ACCESS_HANDLER */
2027
2028	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2029	/**
2030	* @callback_method_impl{FNRTTHREAD,
2031	* Asynchronous I/O thread for a HDA stream.
2032	*
2033	* This will do the heavy lifting work for us as soon as it's getting notified
2034	* by another thread.}
2035	*/
2036	static DECLCALLBACK(int) hdaR3StreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
2037	{
2038	PHDASTREAMR3 const pStreamR3 = (PHDASTREAMR3)pvUser;
2039	PHDASTREAMSTATEAIO const pAIO = &pStreamR3->State.AIO;
2040	PHDASTATE const pThis = pStreamR3->pHDAStateShared;
2041	PHDASTATER3 const pThisCC = pStreamR3->pHDAStateR3;
2042	PPDMDEVINS const pDevIns = pThisCC->pDevIns;
2043	PHDASTREAM const pStreamShared = &pThis->aStreams[pStreamR3 - &pThisCC->aStreams[0]];
2044	Assert(pStreamR3 - &pThisCC->aStreams[0] == pStreamR3->u8SD);
2045	Assert(pStreamShared->u8SD == pStreamR3->u8SD);
2046
2047	/* Signal parent thread that we've started */
2048	ASMAtomicXchgBool(&pAIO->fStarted, true);
2049	RTThreadUserSignal(hThreadSelf);
2050
2051	LogFunc(("[SD%RU8] Started\n", pStreamShared->u8SD));
2052
2053	for (;;)
2054	{
2055	int rc2 = RTSemEventWait(pAIO->hEvent, RT_INDEFINITE_WAIT);
2056	if (RT_FAILURE(rc2))
2057	break;
2058
2059	if (ASMAtomicReadBool(&pAIO->fShutdown))
2060	break;
2061
2062	rc2 = RTCritSectEnter(&pAIO->CritSect);
2063	AssertRC(rc2);
2064	if (RT_SUCCESS(rc2))
2065	{
2066	if (!pAIO->fEnabled)
2067	{
2068	RTCritSectLeave(&pAIO->CritSect);
2069	continue;
2070	}
2071
2072	hdaR3StreamUpdate(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3, false /* fInTimer */);
2073
2074	int rc3 = RTCritSectLeave(&pAIO->CritSect);
2075	AssertRC(rc3);
2076	}
2077	}
2078
2079	LogFunc(("[SD%RU8] Ended\n", pStreamShared->u8SD));
2080	ASMAtomicXchgBool(&pAIO->fStarted, false);
2081
2082	return VINF_SUCCESS;
2083	}
2084
2085	/**
2086	* Creates the async I/O thread for a specific HDA audio stream.
2087	*
2088	* @returns IPRT status code.
2089	* @param pStreamR3 HDA audio stream to create the async I/O thread for.
2090	*/
2091	int hdaR3StreamAsyncIOCreate(PHDASTREAMR3 pStreamR3)
2092	{
2093	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2094
2095	int rc;
2096
2097	if (!ASMAtomicReadBool(&pAIO->fStarted))
2098	{
2099	pAIO->fShutdown = false;
2100	pAIO->fEnabled = true; /* Enabled by default. */
2101
2102	rc = RTSemEventCreate(&pAIO->hEvent);
2103	if (RT_SUCCESS(rc))
2104	{
2105	rc = RTCritSectInit(&pAIO->CritSect);
2106	if (RT_SUCCESS(rc))
2107	{
2108	rc = RTThreadCreateF(&pAIO->hThread, hdaR3StreamAsyncIOThread, pStreamR3, 0 /cbStack/,
2109	RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, "hdaAIO%RU8", pStreamR3->u8SD);
2110	if (RT_SUCCESS(rc))
2111	rc = RTThreadUserWait(pAIO->hThread, 10 * 1000 /* 10s timeout */);
2112	}
2113	}
2114	}
2115	else
2116	rc = VINF_SUCCESS;
2117
2118	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamR3->u8SD, rc));
2119	return rc;
2120	}
2121
2122	/**
2123	* Destroys the async I/O thread of a specific HDA audio stream.
2124	*
2125	* @returns IPRT status code.
2126	* @param pStreamR3 HDA audio stream to destroy the async I/O thread for.
2127	*/
2128	static int hdaR3StreamAsyncIODestroy(PHDASTREAMR3 pStreamR3)
2129	{
2130	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2131
2132	if (!ASMAtomicReadBool(&pAIO->fStarted))
2133	return VINF_SUCCESS;
2134
2135	ASMAtomicWriteBool(&pAIO->fShutdown, true);
2136
2137	int rc = hdaR3StreamAsyncIONotify(pStreamR3);
2138	AssertRC(rc);
2139
2140	int rcThread;
2141	rc = RTThreadWait(pAIO->hThread, 30 * 1000 /* 30s timeout */, &rcThread);
2142	LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
2143
2144	if (RT_SUCCESS(rc))
2145	{
2146	pAIO->hThread = NIL_RTTHREAD;
2147
2148	rc = RTCritSectDelete(&pAIO->CritSect);
2149	AssertRC(rc);
2150
2151	rc = RTSemEventDestroy(pAIO->hEvent);
2152	AssertRC(rc);
2153	pAIO->hEvent = NIL_RTSEMEVENT;
2154
2155	pAIO->fStarted = false;
2156	pAIO->fShutdown = false;
2157	pAIO->fEnabled = false;
2158	}
2159
2160	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamR3->u8SD, rc));
2161	return rc;
2162	}
2163
2164	/**
2165	* Lets the stream's async I/O thread know that there is some data to process.
2166	*
2167	* @returns IPRT status code.
2168	* @param pStreamR3 HDA stream to notify async I/O thread for.
2169	*/
2170	static int hdaR3StreamAsyncIONotify(PHDASTREAMR3 pStreamR3)
2171	{
2172	return RTSemEventSignal(pStreamR3->State.AIO.hEvent);
2173	}
2174
2175	/**
2176	* Locks the async I/O thread of a specific HDA audio stream.
2177	*
2178	* @param pStreamR3 HDA stream to lock async I/O thread for.
2179	*/
2180	void hdaR3StreamAsyncIOLock(PHDASTREAMR3 pStreamR3)
2181	{
2182	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2183
2184	if (!ASMAtomicReadBool(&pAIO->fStarted))
2185	return;
2186
2187	int rc2 = RTCritSectEnter(&pAIO->CritSect);
2188	AssertRC(rc2);
2189	}
2190
2191	/**
2192	* Unlocks the async I/O thread of a specific HDA audio stream.
2193	*
2194	* @param pStreamR3 HDA stream to unlock async I/O thread for.
2195	*/
2196	void hdaR3StreamAsyncIOUnlock(PHDASTREAMR3 pStreamR3)
2197	{
2198	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2199
2200	if (!ASMAtomicReadBool(&pAIO->fStarted))
2201	return;
2202
2203	int rc2 = RTCritSectLeave(&pAIO->CritSect);
2204	AssertRC(rc2);
2205	}
2206
2207	/**
2208	* Enables (resumes) or disables (pauses) the async I/O thread.
2209	*
2210	* @param pStreamR3 HDA stream to enable/disable async I/O thread for.
2211	* @param fEnable Whether to enable or disable the I/O thread.
2212	*
2213	* @remarks Does not do locking.
2214	*/
2215	void hdaR3StreamAsyncIOEnable(PHDASTREAMR3 pStreamR3, bool fEnable)
2216	{
2217	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2218	ASMAtomicXchgBool(&pAIO->fEnabled, fEnable);
2219	}
2220	# endif /* VBOX_WITH_AUDIO_HDA_ASYNC_IO */
2221
2222	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Audio/HDAStream.cpp@ 87760

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